AK8181A ms1342-e-00 nov-2011 - 1 - features four differential 3.3v lvpecl outputs selectable two lvttl/lvcmos inputs clock output frequency up to 266mhz output skew : 30ps maximum part-to-part skew : 200ps maximum propagation delay : 1.4ns maximum additive phase jitter(rms) : < 0.06ps(typical) operating temperature range: -40 to +85 package: 20-pin tssop (pb free) pin compatible with ics8535i-01 description the AK8181A is a member of akm? lvpecl clock fanout buffer family designed for telecom, networking and computer applications, requiring a range of clocks with high performance and low skew. the AK8181A distributes 4 buffered clocks. AK8181A are derived from akm? long-term- experienced clock device technology, and enable clock output to perform low skew. the AK8181A is available in a 20-pin tssop package. block diagram 0 1 clk_sel clk0 clk1 q d le clk_en q3 q3n q2 q2n q1 q1n q0 q0n 3.3v lvpecl 1:4 clock fanout buffer AK8181A
AK8181A nov-2011 ms1342-e-00 - 2 - pin descriptions package: 20-pin tssop (top view) pin no. pin name pin type pullup down description 1 vss pwr -- negative supply 2 clk_en in pu synchronizing clock output enable (lvcmos/lvttl) h: clock outputs follow clock input. l: q outputs are forced low, qn outputs are forced high. 3 clk_sel in pd clk select input (lvcmos/lvttl) h: selects clk1 input l: selects clk0 input 4 clk0 in pd lvcmos/lvttl clock input 5 nc -- -- no connect 6 clk1 in pd lvcmos/lvttl clock input 7 nc -- -- no connect 8, test -- -- factory use. internally pulled down. leave open or tied to vss. 9 nc -- -- no connect 10 vdd pwr -- power supply 11, 12 q3n, q3 out -- different ial clock output pair (lvpecl) 13 vdd pwr -- power supply 14, 15 q2n, q2 out -- differential clock output (lvpecl) 16, 17 q1n, q1 out -- differential clock output (lvpecl) 18 vdd pwr -- power supply 19, 20 q0n, q0 out -- differential clock output (lvpecl) ordering information part number marking shipping packaging package temperature range AK8181A AK8181A tape and reel 20-pin tssop -40 to 85
AK8181A ms1342-e-00 nov-2011 - 3 - absolute maximum rating over operating free-air temperat ure range unless otherwise noted (1) items symbol ratings unit supply voltage (2) vdd -0.3 to 4.6 v input voltage (2) vin -0.3 to vdd+0.3 v input current (any pins except supplies) i in 10 ma storage temperature tstg -55 to 130 c note (1) stress beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditions? is not implied. exposure to absolute-maximum-rating conditions for extended periods may affect device reliabi lity. electrical parameters are guaranteed only over the recommended operating temperature range. (2) vss=0v this device is manufactured on a cmos proce ss, therefore, generically susceptible to damage by excessive static voltage. fa ilure to observe proper handling and installation procedures can cause damage. akm recommends that this device is handled with appropriate precautions. recommended operation conditions parameter symbol conditions min typ max unit operating temperature ta -40 85 c supply voltage (1) vdd vdd 5% 3.135 3.3 3.465 v (1) power of 3.3v requires to be supplied from a single source. a decoupling capacitor of 0.1 f for power supply line should be located close to each vdd pin. pin characteristics parameter symbol conditions min typ max unit input capacitance c in 4 pf input pullup resistor r pu 51 k ? input pulldown resistor r pd 51 k ? esd sensitive device
AK8181A nov-2011 ms1342-e-00 - 4 - dc characteristics all specifications at vdd= 3.3v 5%, ta: -40 to +85 , unless otherwise noted parameter symbol conditions min typ max unit clk0, clk1 2.0 vdd+0.3 v input high voltage clk_en, clk_sel v ih 2.0 vdd+0.3 clk0, clk1 -0.3 1.3 v input low voltage clk_en, clk_sel v il -0.3 0.8 clk0, clk1, clk_sel vin=vdd 150 a input high current clk_en i h vin=vdd 5 a clk0, clk1, clk_sel vin=vss -5 a input low current clk_en i l vin=vss -150 a output high voltage (1) v oh vdd-1.4 vdd-0.9 v output low voltage (1) v ol vdd-2.0 vdd-1.7 v peak-to-peak output voltage swing (1) v swing 0.6 1.0 v supply current i dd 35 50 ma (1) .outputs terminated with 50 ? to vdd-2v. ac characteristics all specifications at vdd= 3.3v 5%, ta: -40 to +85 , unless otherwise noted (1) measured from the vdd/2 of the input to the differential output crossing point. (2) defined as skew between outputs at the same supply voltage and with equal load conditions. (3) this parameter is defined in accordance with jedec standard 65. (4) defined as skew between outputs on di fferent devices operating at the sa me supply voltages and with equal load conditions. using the same type of i nputs on each device, the outputs are measur ed at the differential cross points. parameter symbol conditions min typ max unit output frequency f out 266 mhz propagation delay (1) t pd 0.6 1.4 ns output skew (2)(3) t sk(o) 30 ps part-to-part skew (3)(4) t skpp 200 ps buffer additive jitter, rms t jit 12khz to 20mhz 0.06 ps output rise/fall time t r , t f 20% to 80% 200 600 ps output duty cycle dc out 48 50 52 %
AK8181A ms1342-e-00 nov-2011 - 5 - figure 1 3.3v output load test ci rcuit figure 2 part-to-part skew clock outputs 80% qx t sk(o) qxn qyn qy t r t f 20% 80% 20% v swing figure 3 output skew figure 4 output rise/fall time figure 5 propagation delay figure 6 output duty/ pulse width/ period
AK8181A nov-2011 ms1342-e-00 - 6 - function table the following table shows the inputs/outputs cloc k state configured through the control pins. table 1: control input function table inputs outputs clk_en clk_sel selected source q0:q3 q0n:q3n 0 0 clk0 disabled: low disabled: high 0 1 clk1 disabled: low disabled: high 1 0 clk0 enabled enabled 1 1 clk1 enabled enabled after clk_en switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in figure 7. in the active mode, the state of the outputs is a function of the clk0 and clk1 as described in table 2. clk0, clk1 clk_en q0n : q3n q0 : q3 disabled enabled figure 7 clk_en timing diagram table 2 clock input function table inputs outputs clk0 or clk1 q0 : q3 q0n : q3n 0 low high 1 high low
AK8181A ms1342-e-00 nov-2011 - 7 - package information ? mechanical data : 20pin tssop 20 11 10 1 0.90 0.05 s 0.10 s 6.50 0.10 0.15 0.05 0.25 0.05 0.65 0 8 ? marking ? rohs compliance all integrated circuits form asahi kasei microdevices corporation (akm) assembled in ?lead-free? packages* are fully compliant with rohs. (*) rohs compliant products from akm are identified with ?pb free? letter indication on product label posted on the anti-shield bag and boxes. a: #1 pin index b: part number c: date code ( 7 digits) 1 20 10 11 AK8181A xxxxxxx a b c
AK8181A nov-2011 ms1342-e-00 - 8 - important notice z these products and their specifications ar e subject to change without notice. when you consider any use or application of these products , please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized dist ributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related in formation contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. you are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. akm assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for in fringement of any patent, intellectual property, or other rights in the applic ation or use of such info rmation contained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by re presentative director of akm. as used here: note1) a critical component is one w hose failure to function or perform ma y reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effe ctiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or syst em is one designed or intended for life support or maintenance of safety or for applications in medi cine, aerospace, nuclear energy, or other fi elds, in which its failure to function or perform may reasonably be expect ed to result in loss of life or in signi ficant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products, who distributes, dispos es of, or otherwise places the product with a third party, to notify such third party in advance of the a bove content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said produc t in the absence of such notification.
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