www.siliconstandard.com 1 of 5 dual p-channel enhancement-mode power mosfets bv dss -20v r ds(on) 45mw i d -5.6a the SSM4955GM acheives fast switching performance with low gate charge without a complex drive circuit. it is suitable for low voltage applications such as battery absolute maximum ratings v ds v gs i d i dm p d w/c t stg t j symbol parameter value units r qja maximum thermal resistance, junction-ambient 3 62.5 c/w symbol parameter value units drain-source voltage -20 v gate-source voltage continuous drain current 3 , t a = 25c -5.6 a t a = 100c -4.5 a pulsed drain current 1,2 -20 a operating junction temperature range -55 to 150 c linear derating factor 0.016 storage temperature range total power dissipation 3 , t a = 25c 2 w -55 to 150 c thermal characteristics 20 v pb-free; rohs-compliant so-8 product summary description notes: 1.pulse width must be limited to avoid exceeding the maximum junction temperature of 150c. 2.pulse width <300us, duty cycle <2%. 3.mounted on a square inch of copper pad on fr4 board ; 135c/w when mounted on the minimum pad area required for soldering. management and general load-switching circuits. the SSM4955GM is supplied in an rohs-compliant so-8 package, which is widely used for medium power commercial and industrial surface mount applications. s1 g1 s2 g2 d1 d1 d2 d2 so-8 ssm 4 9 55 g m 1 1 / 2 6/2005 re v. 3 .01
www.siliconstandard.com 2 of 5 electrical characteristics (at tj = 25c, unless otherwise specified) notes: 1.pulse width must be limited to avoid exceeding the maximum junction temperature of 150c. 2.pulse width <300us, duty cycle <2%. symbol parameter test conditions min. typ. max. units bv dss drain-source breakdown voltage v gs =0v, i d =-250ua -20 - - v d bv dss / d t j breakdown voltage temperature coefficient reference to 25c, i d =-1ma - -0.01 - v/c r ds(on) static drain-source on-resistance 2 v gs =-4.5v, i d =-5a - - 45 mw v gs =-2.5v, i d =-4a - - 65 mw v gs(th) gate threshold voltage v ds =v gs , i d =-250ua -0.5 - -1.2 v g fs forward transconductance v ds =-5v, i d =-5a - 9 - s i dss drain-source leakage current v ds =-20v, v gs =0v - - -1 ua v ds =-16v ,v gs =0v, tj = 70c - - -25 ua i gss gate-source leakage current v gs =20v - - 100 na q g total gate charge 2 i d =-5a - 19 30 nc q gs gate-source charge v ds =-16v - 3 - nc q gd gate-drain ("miller") charge v gs =-4.5v - 6 - nc t d(on) turn-on delay time 2 v ds =-10v - 9 - ns t r rise time i d =-1a - 10 - ns t d(off) turn-off delay time r g =3.3w , v gs =-10v - 52 - ns t f fall time r d =10w - 24 - ns c iss input capacitance v gs =0v - 1400 2240 pf c oss output capacitance v ds =-20 v - 270 - pf c rss reverse transfer capacitance f=1.0mhz - 230 - pf source-drain diode symbol parameter test conditions min. typ. max. units v sd forward voltage 2 i s =-1.6a, v gs =0v - - -1.2 v t rr reverse-recovery time i s =-5a, v gs =0v, - 32 - ns q rr reverse-recovery charge di/dt=100a/s - 22 - nc ssm 4 9 55 g m 1 1 / 2 6/2005 re v. 3 .01
www.siliconstandard.com 3 of 5 ssm 4 9 55 g m 1 1 / 2 6/2005 re v. 3 .01 fig 1. typical output characteristics fig 2. typical output characteristics fig 3. on-resistance vs. gate voltage fig 4. normalized on-resistance vs. junction temperature fig 5. forward characteristic of fig 6. gate threshold voltage vs. reverse diode junction temperature 0.0 0.5 1.0 1.5 2.0 -50 0 50 100 150 t j , junction temperature ( o c) -v gs(th) (v) 0.6 0.8 1.0 1.2 1.4 1.6 -50 0 50 100 150 t j , junction temperature ( o c) normalized r ds(on) i d =-5a v g =-10v 0 10 20 30 40 50 60 70 0123456789 -v ds , drain-to-source voltage (v) -i d , drain current (a) t a =25 o c -5.0v -4.5v -3.0v -2.5v v g =- 2.0 v 30 35 40 45 50 55 23456 -v gs , gate-to-source voltage (v) r ds(on) (mw ) i d =-4a t a =25 o c 0 10 20 30 40 50 60 0123456789 -v ds , drain-to-source voltage (v) -i d , drain current (a) t a = 150 o c -5.0v -4.5v -3.0v -2.5v v g =- 2.0 v 0 1 2 3 4 5 0 0.2 0.4 0.6 0.8 1 1.2 1.4 -v sd , source-to-drain voltage (v) -i s (a) t j =25 o c t j =150 o c
www.siliconstandard.com 4 of 5 SSM4955GM 11 /26/2005 rev.3.01 fig 7. gate charge characteristics fig 8. typical capacitance characteristics fig 9. maximum safe operating area fig 10. effective transient thermal impedance fig 11. switching time waveform fig 12. gate charge waveform t d(on) t r t d(off) t f v ds v gs 10% 90% q v g -4.5v q gs q gd q g charge 0.01 0.1 1 10 100 0.1 1 10 100 -v ds , drain-to-source voltage (v) -i d (a) t a =25 o c single pulse 1ms 10ms 100ms 1s dc 100 1000 10000 1 5 9 13 17 21 25 29 -v ds , drain-to-source voltage (v) c (pf) f =1.0mhz c iss c oss c rss 0 2 4 6 8 10 12 14 0 1 02 03 04 05 0 q g , total gate charge (nc) -v gs , gate to source voltage (v) i d =-5a v ds =-16v 0.001 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 10 100 1000 t , pulse width (s) normalized thermal response (r thja ) p dm duty factor = t/t peak t j = p dm x r thja + t a r thja =135 o c/w t t 0.02 0.01 0.05 0.1 0.2 duty factor=0.5 single pulse
www.siliconstandard.com 5 of 5 physical dimensions part marking packing: moisture sensitivity level msl3 3000 pcs in antistatic tape on a 13 inch (330mm) reel packed in a moisture barrier bag (mbb). symbol min max a 1.35 1.75 a1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 d 4.80 5.00 e 3.80 4.00 e 1.27(typ) h 5.80 6.50 l 0.38 1.27 d h e a b a1 c e l dimensions do not include mold protrusions. part number: 4955gm xxxxx x ywwsss date/lot code: (ywwsss) y = last digit of the year ww = week sss = lot code sequence all dimensions in millimeters. ssm 4 9 55 g m 1 1 / 2 6/2005 re v. 3 .01
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