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ibm11e4490bg IBM11D4490BG ibm11e8490bg ibm11d8490bg preliminary 4m/8m x 36 ecc-on-simm w/ error lines 75h3879 revised 10/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 1 of 20 features ? 72-pin jedec-standard single in-line memory module ? performance: ? single-error-correct (sec) high-speed ecc algorithm ? single 5.0v 0.25v power supply ? all inputs & outputs are fully ttl & cmos compatible ? fast page mode access cycle ? refresh modes: ras-only and cbr ? 2048 refresh cycles distributed across 32ms ? 11/11 addressing (row/column) ? provides ecc and retro?ts to standard x36 socket ? au and sn/pb versions available ? error indicator signals for each byte of data description the IBM11D4490BG/ibm11d8490bg are 16mb/32mb industry standard 72-pin 4-byte single in-line memory modules (simm) that have fully func- tional, retrofittable and plug-compatible on-board error-correcting-code (ecc). the ecc function is completely self-contained and transparent to the system. the module is manufactured with 4 ecc asics and either 12 4m x 4 drams (16mb) or 24 4m x 4 drams (32mb) in soj packages. a unique assembly with 6 4 m x 4 drams in tsop and 18 4m x 4 drams in soj packages (32mb) is also avail- able. the ecc-on-simm module corrects single-bit errors that may occur in any byte of simm data. it is recommended for systems that run critical applica- tions but do not have native ecc. this family of simms (4m x 36 and 8m x 36) provides the memory reliability required by these applications with no per- formance penalty. an error line is activated when- ever a single-bit error is being corrected during a read cycle, or whenever a multi-bit uncorrectable error is detected. -70 t rac ras access time 70ns t cac cas access time 20ns t aa access time from address 35ns t rc cycle time 130ns t pc fast page mode cycle time 45ns card outline 1 36 37 72 4m x 36 8m x 36 1 36 37 72 ibm11d4480ba4m x 36 eos11/11, 5.0v, sn/pb. ibm11e4480ba4m x 36 eos11/11, 5.0v, au. discontinued (7/00 - last order; 9/00 - last ship)
?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 2 of 20 75h3879 revised 10/98 IBM11D4490BG ibm11e4490bg ibm11d8490bg ibm11e8490bg 4m/8m x 36 ecc-on-simm w/ error lines preliminary pin description ras0, ras2 row address strobe (16mb) ras0 - ras3 row address strobe (32mb) cas0 - cas3 column address strobe we read/write input a0 - a10 address inputs dq0-7, 9-16, 18-25, 27-34 data input/output pq8, 17, 26, 35 parity input/output error0 - error3 error lines v cc power (+5v) v ss ground nc no connect pd1 - pd4 presence detects pinout pin# name pin# name pin# name 1 v ss 25 dq24 49 dq9 2 dq0 26 dq7 50 dq27 3 dq18 27 dq25 51 dq10 4 dq1 28 a7 52 dq28 5 dq19 29 error0 53 dq11 6 dq2 30 v cc 54 dq29 7 dq20 31 a8 55 dq12 8 dq3 32 a9 56 dq30 9 dq21 33 ras3 (1) 57 dq13 10 v cc 34 ras2 58 dq31 11 nc 35 pq26 59 v cc 12 a0 36 pq8 60 dq32 13 a1 37 pq17 61 dq14 14 a2 38 pq35 62 dq33 15 a3 39 v ss 63 dq15 16 a4 40 cas0 64 dq34 17 a5 41 cas2 65 dq16 18 a6 42 cas3 66 error2 19 a10 43 cas1 67 pd1 20 dq4 44 ras0 68 pd2 21 dq22 45 ras1 (1) 69 pd3 22 dq5 46 error1 70 pd4 23 dq23 47 we 71 error3 24 dq6 48 nc 72 v ss 1 - ras1 and ras3 are nc on 16mb simm ordering information part number organization speed addr. leads dimensions dram- package notes IBM11D4490BG-70 4m x 36 70ns 11/11 sn/pb 4.25 x 1.04 x .397 soj 1 ibm11e4490bg-70 au IBM11D4490BG-70 sn/pb ibm11e4490bg-70 au ibm11d8490bg-70 8m x 36 sn/pb 4.25 x 1.40 x .397 soj 1 ibm11e8490bg-70 au tsop/soj 1, 2 1. dram package designator appended to speed portion of partnumber on assemblies beginning with dram die rev e. 2. this assembly consists of 6 tsop and 18 soj drams discontinued (7/00 - last order; 9/00 - last ship)
ibm11e4490bg IBM11D4490BG ibm11e8490bg ibm11d8490bg preliminary 4m/8m x 36 ecc-on-simm w/ error lines 75h3879 revised 10/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 3 of 20 block diagram cas0 we cas1 cas3 cas2 we oe dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 44 plcc 44 plcc 44 plcc 44 plcc byte 0 byte 1 byte 2 byte 3 pq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq16 pq17 dq18 dq19 dq20 dq21 dq22 dq23 dq24 dq25 pq26 dq27 dq28 dq29 dq30 dq31 dq32 dq33 dq34 pq35 data ras0 ras2 data data data we oe we oe we oe 4m x 4 4m x 4 4m x 4 4m x 4 4m x 4 4m x 4 4m x 4 4m x 4 4m x 4 4m x 4 4m x 4 4m x 4 4m x 4 4m x 4 4m x 4 4m x 4 4m x 4 4m x 4 4m x 4 4m x 4 4m x 4 4m x 4 4m x 4 4m x 4 ras1 ras3 error 0 error 1 error 2 error 3 applies to 32mb simm only discontinued (7/00 - last order; 9/00 - last ship)
IBM11D4490BG ibm11e4490bg ibm11d8490bg ibm11e8490bg 4m/8m x 36 ecc-on-simm w/ error lines preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 4 of 20 75h3879 revised 10/98 truth table function ras cas we row address column address error line all dq, pq bits notes standby h x x x x high impedance read l l h row col valid data out early-write l l l row col valid data in fast page mode - read: 1st cycle l h ? l h row col valid data out subsequent cycles l h ? l h n/a col valid data out fast page mode - write: 1st cycle l h ? l l row col valid data in subsequent cycles l h ? l l n/a col valid data in ras-only refresh l h x row n/a high impedance cas-before- ras refresh h ? l l h x x high impedance error during read x l h x x l data out 1 error during write x l l x x l data in 2 1. if all pqs are valid, ecc has successfully corrected single bit error, dq contains valid data out. if a pq is invalid, ecc h as detected a multi-bit error, dqs for the corresponding byte contain invalid data out. 2. a parity error has been detected on data received from system. a subsequent read of this data will indicate a parity error (p q invalid). the operation of the error line during a write has not been characterized. presence detect pin 4mx36 (industry standard -70) 8mx36 (industry standard -70) notes pd1 v ss nc 1 pd2 nc v ss 1 pd3 v ss v ss 1 pd4 nc nc 1 1. nc= open , v ss = gnd. absolute maximum ratings symbol parameter rating units notes v cc power supply voltage -0.3 to 6.5 v 1 v in input voltage -0.3 to v cc + 0.3 v1 v out output voltage -0.3 to v cc + 0.3 v1 t c operating temperature (case) 0 to +65 c 1 t stg storage temperature -40 to +125 c 1 p d power dissipation 24 w 1 i out short circuit output current 50 ma 1 1. stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and device functio nal operation at or above the conditions indicated is not implied. exposure to absolute maximum rating conditions for extended peri - ods may affect reliability. discontinued (7/00 - last order; 9/00 - last ship)
ibm11e4490bg IBM11D4490BG ibm11e8490bg ibm11d8490bg preliminary 4m/8m x 36 ecc-on-simm w/ error lines 75h3879 revised 10/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 5 of 20 load diagram recommended dc operating conditions (t c = 0 to 65 c) symbol parameter min typ max units notes v cc supply voltage 4.75 5.0 5.25 v 1 v ih input high voltage 2.4 v cc v1 v il input low voltage 0.0 0.8 v 1 1. all voltages referenced to v ss . capacitance (t c = 0 to +65 c, v cc = 5.0 0.25v) symbol parameter 4m x 36 max 8m x 36 max units c i1 input capacitance (a0-a10) 100 161 pf c i2 input capacitance ( ras) 70 70 pf c i3 input capacitance ( cas) 50 70 pf c i4 input capacitance ( we) 35 35 pf c i/o1 output capacitance (dq0-dq34) 12 12 pf c i/o2 output capacitance (pq8, 17, 26, 35) 12 12 pf c i/o3 output capacitance ( error0 - error3) 12 12 pf output 1.31 v 5.0 v output rl = 436 ohms rl1 = 1656 ohms cl = 100 pf cl = 100 pf rl2 = 590 ohms load circuit alternate load circuit . . discontinued (7/00 - last order; 9/00 - last ship)
IBM11D4490BG ibm11e4490bg ibm11d8490bg ibm11e8490bg 4m/8m x 36 ecc-on-simm w/ error lines preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 6 of 20 75h3879 revised 10/98 dc electrical characteristics (tc = 0 to +65 c, v cc = 5.0 0.25v) symbol parameter 4m x 36 8m x 36 units notes min max min max i cc1 operating current average power supply operating current ( ras, cas, address cycling: t rc = t rc min) -70 1080 1104 ma 1, 2, 3 i cc2 standby current (ttl) power supply standby current ( ras = cas 3 v ih ) 2448ma i cc3 ras only refresh current average power supply current, ras only mode ( ras cycling, cas 3 v ih : t rc = t rc min) -70 1080 1104 ma 1, 3, 4 i cc4 fast page mode current average power supply current, fast page mode ( ras = v il , cas, address cycling: t pc = t pc min) -70 960 984 ma 1, 2, 3 i cc5 standby current (cmos) power supply standby current ( ras = cas = v cc - 0.2v) 1224ma i cc6 cas before ras refresh current average power supply current, cas before ras mode ( ras, cas, cycling: t rc = t rc min) -70 1080 1104 ma 1, 3, 4 i i(l) input leakage current input leakage current, any input (0.0 v in (v cc < 6.0v)) all other pins not under test = 0v ras -460 +460 -460 +460 m a cas, we -40 +40 -70 +70 address -120 +120 -240 +240 i o(l) output leakage current (d out is disabled, 0.0 v out v cc ) -10 +10 -10 +10 m a v oh output high level output "h" level voltage (i out = -4ma @ 2.4v) 2.4 2.4 v v ol output low level output "l" level voltage (i out = +4ma @ 0.4v) 0.4 0.4 v 1. i cc1 , i cc3 , i cc4 and i cc6 depend on cycle rate. 2. i cc1 , i cc4 depend on output loading. speci?ed values are obtained with the output open. 3. address can be changed once or less while ras = v il . in the case of i cc4 , it can be changed once or less when cas = v ih . 4. when refreshing both banks at once, the refresh current becomes 2160ma. discontinued (7/00 - last order; 9/00 - last ship)
ibm11e4490bg IBM11D4490BG ibm11e8490bg ibm11d8490bg preliminary 4m/8m x 36 ecc-on-simm w/ error lines 75h3879 revised 10/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 7 of 20 ac characteristics (t c = 0 to +65 c, v cc = 5.0 0.25v) 1. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il . 2. an initial pause of 500ms is required after power-up followed by 8 ras only refresh cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 cas before ras refresh cycles instead of 8 ras only refresh cycles is required. to prevent excess power dissipation during power-up, ras should rise coincident with the power supply voltage. 3. ac measurements assume t t = 5ns. read, write, and refresh cycles (common parameters) symbol parameter -70 units notes min max t rc random read or write cycle time 130 ns t rp ras precharge time 50 ns t cp cas precharge time 10 ns t ras ras pulse width 70 10k ns t cas cas pulse width 20 ns t asr row address setup time 0 ns t rah row address hold time 10 ns t asc column address setup time 0 ns t cah column address hold time 10 ns t rcd ras to cas delay time 20 50 ns 1 t rad ras to column address delay time 15 35 ns 2 t rsh ras hold time 20 ns t csh cas hold time 70 ns t crp cas to ras precharge time 10 ns t dzc cas delay time from d in 0ns t t transition time (rise and fall) 3 30 ns 1. operation within the t rcd (max) limit ensures that t rac (max) can be met. t rcd (max) is specified as a reference point only: if t rcd is greater than the specified t rcd (max) limit, then access time is controlled by t cac . 2. operation within the t rad (max) limit ensures that t rac (max) can be met. t rad (max) is speci?ed as a reference point only: if t rad is greater than the speci?ed t rad (max) limit, then access time is controlled by t aa . discontinued (7/00 - last order; 9/00 - last ship)
IBM11D4490BG ibm11e4490bg ibm11d8490bg ibm11e8490bg 4m/8m x 36 ecc-on-simm w/ error lines preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 8 of 20 75h3879 revised 10/98 write cycle symbol parameter -70 units min max t wcs write command set up time 0 ns t wch write command hold time 15 ns t wp write command pulse width 15 ns t rwl write command to ras lead time 20 ns t cwl write command to cas lead time 20 ns t ds d in setup time 0ns t dh d in hold time 20 ns read cycle symbol parameter -70 units notes min max t rac access time from ras 70 ns 1, 2 t cac access time from cas 20 ns 1, 2 t aa access time from address 35 ns 1, 2 t rcs read command setup time 0 ns t rch read command hold time to cas 0 ns 3 t rrh read command hold time to ras 0 ns 3 t ral column address to ras lead time 35 ns t cal column address to cas lead time 35 ns t clz cas to output in low-z 0 ns t oh output data hold time 0 ns t cdd cas to d in delay time 15 ns t off output buffer turn-off delay 0 15 ns 4 1. measured with the specified current load and 100pf. 2. access time is determined by the latter of t rac , t cac , t cpa , t aa . 3. either t rch or t rrh must be satis?ed for a read cycle. 4. t off (max) de?nes the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. discontinued (7/00 - last order; 9/00 - last ship)
ibm11e4490bg IBM11D4490BG ibm11e8490bg ibm11d8490bg preliminary 4m/8m x 36 ecc-on-simm w/ error lines 75h3879 revised 10/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 9 of 20 fast page mode cycle symbol parameter -70 units notes min max t pc fast page mode cycle time 45 ns t rasp fast page mode ras pulse width 70 100k ns t cprh ras hold time from cas precharge 40 ns t cpa access time from cas precharge 45 ns 1, 2 1. access time is determined by the latter of t rac , t cac , t cpa , t aa . 2. access time assumes a load of 100pf. read error-line functionality cycle symbol parameter -70 units notes min max t err error access time from cas 20 ns 1, 2 t ech error output hold/hi-z 3 20 ns t eclz cas to error output in low-z 0 ns t ercs error read command setup time 0 ns t erch error read command hold time 3 ns 1. ras is a dont care. 2. address and data are the speci?ed address and read data. refresh cycle symbol parameter -70 units notes min max t chr cas hold time ( cas before ras refresh cycle) 10 ns t csr cas setup time ( cas before ras refresh cycle) 5ns t wrp we setup time ( cas before ras refresh cycle) 5ns t wrh we hold time ( cas before ras refresh cycle) 10 ns t rpc ras precharge to cas hold time 5 ns t ref refresh period 32 ms 1 1. 2048 refreshes are required every 32ms. the dc variation in the v cc supply may not exceed 300mv within a refresh interval (32ms). discontinued (7/00 - last order; 9/00 - last ship)
IBM11D4490BG ibm11e4490bg ibm11d8490bg ibm11e8490bg 4m/8m x 36 ecc-on-simm w/ error lines preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 10 of 20 75h3879 revised 10/98 read ras v ih v il v ih v il v ih v il we v ih v il v ih v il d out v oh v ol d in row column valid data out t ras t rp t rc t cas t rsh t csh t crp t rah t asc t cah t asr t rad t ral t rcs t t dzc t cdd t off t clz t cac t rac hi-z hi-z hi-z t rch t rrh : h or l t rcd t cal t oh aa cas a ddress discontinued (7/00 - last order; 9/00 - last ship)
ibm11e4490bg IBM11D4490BG ibm11e8490bg ibm11d8490bg preliminary 4m/8m x 36 ecc-on-simm w/ error lines 75h3879 revised 10/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 11 of 20 write cycle (early write) ras v ih v il v ih v il address v ih v il we v ih v il v ih v il d out v oh v ol d in row column t ras t rp t rc t rcd t rsh t csh t crp t rah t asc t cah t asr t rad t wcs hi-z valid data in t wp t wch t ds t dh : h or l t ar cas t cas t cwl t rwl discontinued (7/00 - last order; 9/00 - last ship)
IBM11D4490BG ibm11e4490bg ibm11d8490bg ibm11e8490bg 4m/8m x 36 ecc-on-simm w/ error lines preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 12 of 20 75h3879 revised 10/98 fast page mode read cycle ras v ih v il v ih v il address v ih v il we v ih v il v ih v il d out v oh v ol d in t rasp t rp row column 1 column 2 column n d out 1d out 2d out n t asr t asc t rah t cah t csh t asc t cah t asc t cah t ral t rsh t pc t cp t crp t rad t rch t rcs t rch t rcs t rch t rrh t aa rcs t t aa t cpa t aa t cpa t clz t off t off t dzc t cac t t cdd t t clz t clz t cac t cac t rcd t cp t cal dzc dzc t oh t oh t cprh : h or l t rac cas t cas t cas t cas t dzc t oh t off discontinued (7/00 - last order; 9/00 - last ship)
ibm11e4490bg IBM11D4490BG ibm11e8490bg ibm11d8490bg preliminary 4m/8m x 36 ecc-on-simm w/ error lines 75h3879 revised 10/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 13 of 20 fast page mode write cycle ras v ih v il v ih v il address v ih v il we v ih v il v ih v il d out v oh v ol d in t rasp t rp row column 1 column 2 column n t asr t asc t rah t cah t csh t asc t cah t asc t cah t rsh t rcd t pc t cp t crp t rad d in 1 d in 2 d in n t ds t dh t ds t dh t ds t dh t wp t wp t wp t wcs t wch t wcs t wch t wcs t wch t cwl t rwl t cwl t cwl t cp : h or l cas t cas t cas t cas discontinued (7/00 - last order; 9/00 - last ship)
IBM11D4490BG ibm11e4490bg ibm11d8490bg ibm11e8490bg 4m/8m x 36 ecc-on-simm w/ error lines preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 14 of 20 75h3879 revised 10/98 read error-line functionality timing diagram ras cas we error t erch t err t eoh t eclz t ercs valid error line discontinued (7/00 - last order; 9/00 - last ship)
ibm11e4490bg IBM11D4490BG ibm11e8490bg ibm11d8490bg preliminary 4m/8m x 36 ecc-on-simm w/ error lines 75h3879 revised 10/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 15 of 20 ras only refresh cycle ras v ih v il v ih v il address v ih v il d out v oh v ol row t ras t rp t rc t rah t asr hi-z note: we, d in are h or l t rpc t crp : h or l cas discontinued (7/00 - last order; 9/00 - last ship)
IBM11D4490BG ibm11e4490bg ibm11d8490bg ibm11e8490bg 4m/8m x 36 ecc-on-simm w/ error lines preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 16 of 20 75h3879 revised 10/98 cas before ras refresh cycle ras v ih v il v ih v il we v ih v il d in v ih v il t ras t rp t rpc t crp d out v oh v ol hi-z t off hi-z t cdd t chr rc t t cp t csr t wrh t wrp t note: addresses are h or l rpc : h or l cas discontinued (7/00 - last order; 9/00 - last ship)
ibm11e4490bg IBM11D4490BG ibm11e8490bg ibm11d8490bg preliminary 4m/8m x 36 ecc-on-simm w/ error lines 75h3879 revised 10/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 17 of 20 layout drawing (4m x 36) 10.08 .397 max. side 5.459 1.27 + _ .050 + _ .1016 .0762 .004 .003 .214 min. note: all dimensions are typical unless otherwise stated. 4.316 .169 min. 107.95 4.25 44.45 1.75 1.27 pitch .050 1.00 width .039 6.35 .250 101.190 3.983 (2x) 0 3.1877 .1255 2.03 .08 26.411 10.16 1.040 .400 6.35 .25 95.25 3.75 ref. millimeters inches front discontinued (7/00 - last order; 9/00 - last ship)
IBM11D4490BG ibm11e4490bg ibm11d8490bg ibm11e8490bg 4m/8m x 36 ecc-on-simm w/ error lines preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 18 of 20 75h3879 revised 10/98 layout drawing (8m x 36) note: all dimensions are typical unless otherwise stated. 107.95 4.25 44.45 1.75 1.27 pitch .050 1.00 width .039 6.35 .250 101.19 3.983 (2x) 0 3.1877 .1255 2.03 .08 35.56 10.16 1.40 .400 6.35 .25 95.25 3.75 ref. millimeters inches 10.08 .397 max. side 4.826 1.27 + _ .050 + _ .1016 .0762 .004 .003 .190 min. 4.826 .190 min. front a unique assembly is available with these 6 drams in tsop and the other 18 in soj packages.. discontinued (7/00 - last order; 9/00 - last ship)
ibm11e4490bg IBM11D4490BG ibm11e8490bg ibm11d8490bg preliminary 4m/8m x 36 ecc-on-simm w/ error lines 75h3879 revised 10/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 19 of 20 revision log rev contents of modi?cation 7/96 initial release. 8/96 corrected typos 10/98 added rev g part numbers. discontinued (7/00 - last order; 9/00 - last ship)
intern ational business machines corp.1998 copyright printed in the united states of america all rights reserved ibm and the ibm logo are registered trademarks of the ibm corporation. this document may contain preliminary information and is subject to change by ibm without notice. ibm assumes no responsibility or liability for any use of the information contained herein. nothing in this document shall operate as an express or implied lice nse or indemnity under the intellectual property rights of ibm or third parties. the products described in this document are not inten ded for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. no warranties of any kind, including, but not limited to, the implied warranties of merchantability or fitness for a particular purpose, are offered in this document . for more information contact your ibm microelectronics sales representative or visit us on world wide web at http://www.chips.ibm.com ibm microelectronics manufacturing is iso 9000 compliant. a discontinued (7/00 - last order; 9/00 - last ship)

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