View SI8900D-A01-GS_4522272.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 1.0 6/12 copyright ? 2012 by silicon labora tories si8900/1/2 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. si8900/1/2 i solated m onitoring adc features applications description the si8900/1/2 series of isolated monitoring adcs are useful as linear signal galvanic isolators, level shifters, and/or ground loop eliminators in many applications incl uding power-delivery syst ems and solar inverters. these devices integrate a 10-bit sar adc subsystem, supervisory state machine and isolated uart (si8900), i 2 c/smbus port (si8901), or spi port (si8902) in a single package. based on silicon labs? proprietary cmos isolation technology, ordering options include a choice of 2.5 or 5 kv isolation ratings. all products ar e safety certified by ul, csa, and vde (pending). the si8900/1/2 devices offer a typical common-mode transient immunity performance of 45 kv/s for robust performance in noisy and high-voltage environments. devices in this family are available in 16-pin soic wide-body packages. safety approval (pending) ? adc ?? 3 input channels ?? 10-bit resolution ?? 2 s conversion time ? isolated serial i/o port ?? uart (si8900) ?? i 2 c/smbus (si8901) ?? 2.5 mhz spi port (si8902) ? transient immunity: 45 kv/s (typ) ? temperature range: ?40 to +85 c ? >60-year life at rated working voltage ? csa component notice 5a approval ? iec 60950, 61010, 60601 ? vde/iec 60747-5-2 ? ul1577 recognized ?? up to 5 kvrms for 1 minute ? i s o l a t e d d a t a a c q u i s i t i o n ? ac mains monitor ? solar inverters ? isolated temp/humidity sensing ? switch mode power systems ? te l e m e t r y ? ul 1577 recognized ?? u p t o 5 k v r m s f o r 1 m i n u t e ? csa component notice 5a approval ?? iec 60950, 61010, 60601 ? vde certification conformity ? ied 60747-5-2 (vde 0884 part 2) ordering information: see page 25. pin assignments vddb nc nc scl sda nc vddb gndb si8901 vdda vref rst ain0 ain1 ain2 rsda gnda ain2 vddb nc nc rx tx nc vddb gndb si8900 vdda vref ain0 ain1 nc rst gnda vddb nc sdo sclk sdi en vddb gndb si8902 vdda rst nc vref ain0 ain1 ain2 gnda
si8900/1/2 2 rev. 1.0
si8900/1/2 rev. 1.0 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. regulatory information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 4. adc data transmission modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1. uart (si8900) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2. i2c/smbus (si8901) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.3. spi port (si8902) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.4. master controller firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5. si8900/1/2 configuration regi sters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6. applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1. isolated outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 0 6.2. device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3. application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7. device pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 8. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9. package outline: 16-pin wide body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10. land pattern: 16-pi n wide-body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 11. top marking: 16-pin wide b ody soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 11.1. si8900/1/2 top marki ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 11.2. top marking explana tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 document change list: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
si8900/1/2 4 rev. 1.0 1. electrical specifications table 1. recommended operating conditions parameter symbol conditions min typ max units input side supply voltage v dda with respect to gnd1 2.7 ? 3.6 v input side supply current i dda v dda = 3.3 v, si890x active ? 10 13.3 ma v dda = 3.3 v, si890x idle ? 8.6 11.4 output side supply voltage v ddb with respect to gnd2 2.7 ? 5.5 v output side supply current i ddb v ddb = 3.3 v to 5.5 v, si890x active ? 4.4 5.8 ma v ddb = 3.3 v to 5.5 v, si890x idle ? 3.3 3.9 operating temperature t a ?40 ? +85 c table 2. electrical specifications parameter symbol test conditions min typ max units adc resolution r 10 bits integral nonlinearity inl vref = 2.4 v ? 0.5 1 lsb differential nonlinearity dnl vref = 2.4 v, guaranteed monotonic ?0.51lsb offset error ofs ?2 0 +2 lsb full scale error fse ?2 0 +2 lsb offset tempco t os ?45?ppm/c input voltage range v in 0v ref v sampling capacitance c in ?5?pf input mux impedance r mux ?5?k ? power supply rejection psrr ? ?70 ? db reference voltage v ref default v ref =v dda 0?v dda v vref supply current i vref ?12?a adc conversion time t conv 2 s
si8900/1/2 rev. 1.0 5 reset and undervoltage lockout power-on reset voltage threshold high vrsth ? ? 1.8 v power-on reset voltage threshold low vrstl 1.7 ? ? v vdda power-on reset ramp time tramp time from vdda = 0 v to vdda > vrst ??1ms power-on reset delay time tpor tramp < 1 ms 0.3 ms output side uvlo threshold uvlo ? 2.3 ? v output side uvlo hysteresis h?100?mv digital inputs logic high level input voltage v ih 0.7 x v ddb ??v logic low level input voltage v il ??0.6v logic input current i in vin = 0 v or v dd ?10 +10 a input capacitance c in ?15?pf digital outputs logic high level output voltage v oh v ddb =5v, i oh =?4ma v ddb ?0.4 4.8 ? v v ddb =3.3v, i oh =?4ma 3.1 ? ? v logic low level output voltage v ol v ddb = 3.3 to 5 v, i ol =4ma ?0.20.4v digital output series impedance r out ?85? ? serial ports uart bit rate 60 ? 234 kbps smbus/i 2 c bit rate slave address = 1111000x ? ? 240 kbps spi port ? ? 2.5 mbps table 2. electrical specifications (continued) parameter symbol test conditions min typ max units
si8900/1/2 6 rev. 1.0 figure 1. spi port timing characteristics spi port timing en falling edge to sclk rising edge t se 80 ? ? ns last clock edge to /en rising t sd 80 ? ? ns en falling to sdo valid t sez ? ? 160 ns en rising to sdo high-z t sdz ? ? 160 ns sclk high time t ckh 200 ? ? ns sclk low time t ckl 200 ? ? ns sdi valid to sclk sample edge t sis 80 ? ? ns sclk sample edge to sdi change t sih 80 ? ? ns sclk shift edge to sdo change t soh ? ? 160 ns table 2. electrical specifications (continued) parameter symbol test conditions min typ max units tsez tsoh tsis tsih tclkh tsdz sclk sdi sdo en tckl tse tsd
si8900/1/2 rev. 1.0 7 figure 2. (wb soic-16) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 figure 3. (nb soic-16) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 table 3. thermal characteristics parameter symbol test condition wb soic-16 nb soic-16 unit ic junction-to-air thermal resistance ? ja 100 105 oc/w 0 200 150 100 50 500 400 200 100 0 temperature (oc) safety-limiting current (ma) 450 300 370 220 v dd1 , v dd2 = 2.70 v v dd1 , v dd2 = 3.6 v v dd1 , v dd2 = 5.5 v 0 200 150 100 50 500 400 200 100 0 temperature (oc) safety-limiting current (ma) 430 300 360 210 v dd1 , v dd2 = 2.70 v v dd1 , v dd2 = 3.6 v v dd1 , v dd2 = 5.5 v
si8900/1/2 8 rev. 1.0 table 4. absolute maximum ratings parameter symbol min typ max units storage temperature t stg ?65 ? 150 c ambient temperature under bias t a ?40 ? 85 c input-side supply voltage v dda ?0.5 ? 6.0 v output-side supply voltage v ddb ?0.5 ? 6.0 v input/output voltage v i ?0.5 ? vdd +0.5 v output current drive i o ?? 10 ma lead solder temperature (10 s) ? ? 260 c maximum isolation voltage ? ? 6500 v rms *note: permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
si8900/1/2 rev. 1.0 9 2. regulatory information the si8900/1/2 family is certified by underwriters laboratories, csa intern ational, and vde. table 5 summarizes the certification levels supported. table 5. regulatory information csa the si89xx is certified under csa component acceptance notice 5a. for more details, see file 232873. 61010-1: up to 600 vrms reinforced insulation working volt age; up to 600 vrms basic insulation working voltage. 60950-1: up to 600 vrms reinforced insulation working volt age; up to 1000 vrms basic insulation working voltage. 60601-1: up to 125 vrms reinforced insulation working volt age; up to 380 vrms basic insulation working voltage. vde the si89xx is certified according to iec 60747-5-2. for more details, see file 5006301-4880-0001. 60747-5-2: up to 1200 vpeak for basic insulation working voltage. 60950-1: up to 600 vrms reinforced insulation working volt age; up to 1000 vrms basic insulation working voltage. ul the si89xx is certified under ul1577 component recognition program. for more details, see file e257455. rated up to 5000 vrms isolation voltage for basic protection.
si8900/1/2 10 rev. 1.0 3. functional description the si8900/1/2 (figure 4) are isolated monitoring adcs th at convert linear input signals into digital format and transmit the resulting data through an on-chip isolated se rial port to an external master processor (typically a microcontroller). the si890x access protocol is simple: the master configures and controls the start of adc conversion by writing a configuration register (cnfg_0) command byte to the si890x. the master then acquires adc conversion data by reading the si890x serial port. device s in this series differ only in the type of serial port. options include a uart with on-chip baud rate generato r that operates at 234 kbps max (si8900), an smbus/i 2 c port that operates at 240 kbps max (si8901), and an spi port that operates at 2.5 mhz max (si8902). the integrated adc subsystem consists of a three-channel analog input multiplexer (mux) followed by a series gain amplifier (selectable 1x or 0.5x gain) and 10-bit sar adc. serial-port-accessible adc options allow the user to select an internal or external voltage reference, se t the programmable gain amplifier (pga), and select the adc mux address. the master can configure the si890x to return adc data on-demand (demand mode) or continuously (burst mode). for more information, see "cnfg_0 command byte" on page 18. figure 4. si8900/1/2 block diagrams vdda gnda ain0 ain1 ain2 vref ?????? si8900 adc? subsystem uart pga mux 10 \ bit adc isolation tx rx gndb vddb all ? blocks rx ? data tx ? data vref state ? machine/ ? user ? registers vdda gnd1 ain0 ain1 ain2 vref ?????? si8902 adc ? subsystem spi ? port pga mux 10 \ bit adc isolation sck gnd2 vddb all ? blocks rx ? data tx ? data vref state ? machine/ ? user ? registers sdi sdo vdda gnda ain0 ain1 ain2 vref ?????? si8901 adc ? subsystem smbus/ i 2 c pga mux 10 \ bit adc isolation sda scl gndb vddb all ? blocks rx ? data tx ? data vref state ? machine/ ? user ? registers rsda rst rst rst en
si8900/1/2 rev. 1.0 11 4. adc data transmission modes the master can access adc read-only registers adc_h a nd adc_l using either demand mode or burst mode. in demand mode (mode = 1), the master triggers indi vidual a/d conversions ?on-demand?. in burst mode (mode = 0), the si890x performs adc conversions continuously. figure 5. adc demand mode operation referring to figure 5a, a demand mode adc read is init iated when the master writ es a command byte to the si8900. (the command byte is a copy of the cnfg_0 regi ster that has been properly configured by the master.) upon receipt of the command byte, the si8900 updates it s cnfg_0 register and triggers the start of an adc conversion, at which time the master may immediately begin reading adc conversion data from the si8900 uart. the adc conversion data packet contains a copy of th e command byte for verification and two-bytes of adc conversion data. the si8901 (figure 5b) adc read transaction is identical to that of the si8900 with the exception of the added i 2 c/smbus slave address byte (si8901 slave addr ess is 0xf0). the si8902 demand mode adc read transaction (figure 5c) is the same as that of the si8900, except the master must wait 8 s after the transmission of the command byte before reading the si 8902 spi port because byte transmission time is two times shorter versus the si8900/01. c) ?? si8901 ? demand ? mode ? adc? read b) ?? si8900 ? demand ? mode ? adc? read ? master ? to ? slave slave ? to ? master cnfg_0 command byte t conv master ? writes ? cnfg_0 ? command ? byte ? to ? si8900 ? rx ? master ? reads ? updated ? cnfg_0 ? and? adc ? data ? from ? si8900 ? (tx ? output) mode = 1 adc_h adc_l cnfg_0 command byte master ? to ? slave slave ? to ? master master ? reads ? slave ? address, ? updated ? cnfg_0 ? and? adc ? data ? from ? si8901 ? (sda ? pin) ? ? ? ? ? ? d) ?? si8902 ? demand ? mode ? adc? read ?? master ? writes ? cnfg_0 ? command ? byte ? to ? si8902 ? sdi ? master ? reads ? updated ? cnfg_0 ? and? adc ? data ? from ? si8902 ? sdo master ? to ? slave slave ? to ? master mode = 1 adc_h adc_l cnfg_0 command byte slave address master ? writes ? slave ? address ? and ? cnfg_0 ? command ? byte ? to ? si8901 ? sda the ? master ? must ? wait ? 8s? (track \ and \ hold ? time) ? before ? reading ? adc ? data ? packet. ? ?
si8900/1/2 12 rev. 1.0 the burst mode adc transactions for the si8900 (figure 6a) and si8901 (figure 6b) are substantially the same. a burst mode adc read is initiated when the master wr ites a cnfg_0 (mode = 0) comma nd byte to the si8900/1, which updates the cnfg_0 register and triggers the ad c continuously. like the demand mode example, the si8901 has a slave address byte prior to the cnfg_0 command byte. when using the si8901, the master must write the i 2 c port address prior to reading the serial port. the si8902 burst mode (figure 6c) is similar to that of the si8900/1, except the master must wait 8 s before re ading the first burst mode adc data packet. after reading the first burst mode adc data packet, the master may read all adc data packets that follow without delay. figure 6. adc burst mode operation a) ?? si8900 ? adc ? burst ? mode ? (mode ? = ? 0) master ? to ? slave slave ? to ? master cnfg_0 command byte 0 t conv master ? writes ? cnfg_0 ? command ? byte ? to ? si8900 ? rx master ? reads ? updated ? cnfg_0 ? command ? byte ? and ? adc ? data ? from ? si8900 ? tx ? ? ? ? ? b) ?? si8901 ? adc ? burst ? mode ? (mode ? = ? 0) master ? to ? slave slave ? to ? master mode = 0 t conv master ? reads ? slave ? address, ? updated ? cnfg_0 ??and ? adc ? data ? from ? si8901 ? sda adc_h data adc_l data adc_h data adc_l data t conv t conv cnfg_0 command byte 0 cnfg_0 command byte master ? writes ? slave ? address ? & ? cnfg_0 ? command ? byte ? to ? si8901 ? sda ? ? ? ? c) ?? si8902 ? adc ? burst ? mode ? (mode ? = ? 0) master ? to ? slave slave ? to ? master master ? writes ? cnfg_0 ? command ? byte ? to ? si8902 ? sdi ? ? master ? reads ? updated ? cnfg_0 ? and ? adc ? data ?? from ? si8902 ? sdo ? ? ? ?
si8900/1/2 rev. 1.0 13 4.1. uart (si8900) the uart is a two-wire interface (tx, rx) and operates as an asynchronous, full-duplex serial port with internal auto baud rate generator that measures the period of incoming data stream and automatically adjusts the internal baud rate generator to match. the auto baud rate de tection and matching optimizes uart timing for minimum bit error rate. for more information, see ?an635: ac line monitoring using the si890x family of isolated adcs?. there are a total of 10 bits per data read/write: one start bit, eight data bits (lsb first), and one stop bit with data transmitted lsb first as shown in figure 7. figure 8a an d figure 8b show master/si8900 adc read transactions for demand mode and bu rst mode, respectively. figure 7. uart data byte figure 8. si8900 adc read operation d7 d6d5 d4 d3 d2 d1d0 start ? bit mark space bit ? times bit ? sampling stop ? bit master ? to ? slave slave ? to ? master a) si8900 demand mode adc read d0 ???d1 ???d2 ???d3 ??d4 ???d5 ??d6 ???d7 ? d0 ??d1 ??? d2 ??? d3 ???d4 ?? d5 ??? d6 ??d7 stop start start stop d0 ??? d1 ??? d2 ???d3 ??? d4 ??? d5 ???d6 ???d7 stop start s start p cnfg_0 ? write ? command ? byte b) si8900 burst mode adc read start stop ? d0 ??d1 ? d2 ? d3 ??d4 ? d5 ? d6 ?? d7 cnfg_0 ? read ? data stop start stop start periodic ? adc ? data cnfg_0 ? read ? data adc ? data d0 ?? d1 ? d2 ? d3 ? d4 ? d5 ??d6 ? d7 ? d0 ?? d1 ??d2 ? d3 ? d4 ? d5 ? d6 ? d7 d0 ??d1 ?? d2 ? d3 ? d4 ? d5 ? d6 ??d7 ? d0 ? d1 ? d2 ? d3 ?? d4 ? d5 ? d6 ? d7 s p d0 ???? d1 ????? d2 ????d3 ??? d4 ???d5 ????d6 ???? d7 cnfg_0 ? write ? command ? byte stop start stop start stop start d0 ?????d1 ????d2 ????d3 ???? d4 ?????d5 ????d6 ????d7 \ mx1 mode = 1 mx0 pga 1 1 vref \ mx1 mode=0 mx0 pga 1 1 vref s s p p s s p vref mx0 pga mode = 0 mx1 \ ? ? \ stop start s p d1 d0 0 0 d5 d4 d3 d2
si8900/1/2 14 rev. 1.0 4.2. i 2 c/smbus (si8901) the i 2 c/smbus serial port is a two-wire serial bus wher e data line sda is bidirectional and clock line scl is unidirectional. reads and writes to this interface by the master are byte-oriented, with the i 2 c/smbus master controlling the serial data rates up to 240 kbps. the sda and scl lines mu st be pulled high through pull-up resistors of 5 k ? or less. an si8901 adc read transaction begins with a start condition (?s? or repeated start condition ?sr?), which is defined as a high-to-low tran sition on sda while scl is high (figure 9). the master terminates a transmission with a stop condition (p), defi ned as a low-to-high transition on sda while scl is high. the data on sda must remain stable during the high peri od of the scl clock pulse bec ause such changes in either line will be interpreted as a co ntrol command (e.g., s, p sr). sda and scl idle in the high state when the bus is not busy. acknowledge bits (figure 10) provide detection of successful data tran sfers, whereas unsuccessful transfers conclude with a not-acknowledge bit (nack). both the master and the si8901 generate ack and nack bits. an ack bit is generated when the receiving device pulls sda low before the rising edge of the acknowledged related (ninth) scl pulse and maintains it low during the high period of the clock pulse. a nack bit is generated when the receiver allows sda to be pulled high before the rising edge of the acknowledged related scl pulse and maintains it high during the high period of the clock pulse. an unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master attempts communication at a later time. figure 11a shows the i 2 c slave address byte and cnfg_0 byte for the si8901. figure 11b and figure 11c show master/si8901 adc read transactions for demand mode and burst mode, respectively. figure 9. start and stop conditions figure 10. acknowledge cycle sda scl s s r p sda scl s not ? acknowledge ? (nack) acknowledge ? (ack) 12 9
si8900/1/2 rev. 1.0 15 figure 11. si8901 adc read operation figure 12. master connection to si8902 master ? to ? slave slave ? to ? master a) ?? si8901 ? cnfg_0 ?write ? b) ?? si8901 ? demand ? mode ?adc ? read s s6 s5 s4 s3 s2 s1 a 1 a start ack ack si8901 cnfg_0 write data write mx0 pga p vref stop r/w ? =? 0 d7 d6 d5 d4 d3 d2 d1 d0 mx1 mode 1 d7 d6 d5 d4 d3 d2 d1 d0 ack adc data stop ack d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 c) ?? si8901 ? burst ? mode ?adc ? read si8901 slave address s0 ack si8901 cnfg_0 read data d7 d6 d5 d4 d3 d2 d1 d0 s s6 s5 s4 s3 s2 s1 a a start ack ack si8901 cnfg_0 write data write p stop r/w ? = ? 0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 si8901 write slave address s0 start ack ack si8901 cnfg_0 write data write stop d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 si8901 slave address stop si8901 ? slave ? address ? =? start read d7 d6 d5 d4 d3 d2 d1 d0 si8901 read slave address start ack ack d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 ack si8901 cnfg_0 read data d7 d6 d5 d4 d3 d2 d1 d0 periodic adc data p start read d7 d6 d5 d4 d3 d2 d1 d0 si8901 read slave address start \ 1 mx0 pga vref mx1 mode=1 1 \ a a 0 0 0 p mx1 mx0 d9 d8 a d7 d6 d5 d4 d3 d2 d1 d0 s 1 mx0 pga vref mx1 mode=1 1 s s6 s5 s4 s3 s2 s1 r/w ? =? 1 s0 \ 1 s 1 a mx0 pga vref mx1 mode=0 1 a s s6 s5 s4 s3 s2 s1 r/w ? =? 1 s0 \ 0 0 0 mx1 mx0 d9 d8 a d7 d6 d5 d4 d3 d2 d1 d0 1 a s s6 s5 s4 s3 s2 s1 a a p r/w ? = ? 0 s0 1 mx0 pga vref mx1 mode=0 1 \ master s i 8902 mosi miso sclk sdi sdo sclk /en 7 6 5 4 3 2 1 0 spi shift register receive buffer baud rate generator en or px.y 7 6 5 4 3 2 1 0 spi shift register receive buffer
si8900/1/2 16 rev. 1.0 4.3. spi port (si8902) figure 13. si8902 data/clock timing the serial peripheral interface (spi po rt) is a slave mode, full-duplex, synchron ous, 4-wire serial bus that connects to the master as shown in figure 12. the master's clock and data timing must match the si8902 timing shown figure 12 (for more information about clock and data ti ming, please see the ?spi port? section of table 2 on page 6). as shown in figure 13, an spi bus transaction begins with the master driving en low and maintaining this state for the duration of the read transaction(s). the master transmi ts data from its master-ou t/slave-in termin al (mosi) to the si8902 serial read/write input terminal (sdi). the si8 902 transmits data to the master from its serial data-out terminal (sdo) to the master-in/slave-out terminal (miso), and data transfer ends when the master returns /en to the high state. figure 14a shows the si8902 cnfg_0 command byte format, while figures 14b and 14c show si8902 demand mode and burst mode adc reads. msb bit ? 6 bit ? 5 bit ? 4 bit ? 3 bit ? 2 bit ? 1 bit ? 0 msb bit ? 6 bit ? 5 bit ? 4 bit ? 3 bit ? 2 bit ? 1 bit ? 0 sclk sdi sdo en
si8900/1/2 rev. 1.0 17 figure 14. si8902 adc read operation 4.4. master cont roller firmware the user's master controller must include firmware to manage the si890x demand and burst operating modes and serial port control. in some cases, the master controller may also require a firmware moving average function to reduce noise. for more information on master controller firmware, see an638, available for download at www.silabs.com/isolation . master ? to ? slave slave ? to ? master b) ?? si8902 ? adc ? demand ? mode ? read adc data 1 0 mx1 mx0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 a) ?? si8902 ? cnfg_0 ? command ? byte cnfg_0 write command byte d7 d6 d5 d4 d3 d2 d1 d0 c) ?? si8902 ? adc ? burst ? mode ? read si8902 cnfg_0 read byte d7 d6 d5 d4 d3 d2 d1 d0 cnfg_0 write command byte mx0 pga vref d7 d6 d5 d4 d3 d2 d1 d0 mx1 mode 1 1 d7 d6 d5 d4 d3 d2 d1 d0 periodic adc data cnfg_0 write command byte si8902 cnfg_0 read byte \ mx0 pga vref mx1 mode=1 1 1 \ mx0 pga vref mx1 mode ? = ? 1 1 \ 0 0 mx0 pga vref mx1 mode=0 1 1 \ ? ?? ??? ?? ?? ?? ??? ?? ? ? ? ???????????????????????????????? ? ????????????????????????????????? 1 mx1 mx0 d9 d8 d7 d6 0 0 d5 d4 d3 d2 d1 d0 0 1 mx1 mx0 d9 d8 d7 d6 mx0 pga vref mx1 mode ? = ? 0 1 \ 0 0 d5 d4 d3 d2 d1 d0 0 d7 d0 d7 d0 d7 d0
si8900/1/2 18 rev. 1.0 5. si8900/1/2 conf iguration registers cnfg_0 command byte bitd7d6d5d4d3d2d1d0 name 1 1 mx1 mx0 vref ? mode pga type r/w r/w r/w r/w r/w r/w r/w r/w default 11111111 bit name function 7:6 1,1 internal use. these bits are always set to 1. 5:4 mx1, mx0 adc mux address. adc mux address selection is cont rolled by mx1, mx0 as follows: 3vref adc voltage reference source vdd is selected as the reference voltage when this bit is set to 1. an externally con- nected voltage reference generator is selected when this bit is reset to 0. 2 ? not used. 1mode adc read mode adc demand mode read is enabled when this bit is 1, and burst mode is enabled when this bit is 0. for more informatio n on demand and burst mode operation, please see "adc data transmission modes" on page 11. 0pga pga gain set pga gain is 1 when this bit is set to 1. pg a gain is 0.5 when this bit is reset to 0. mx1 mx0 selected adc mux channel 1 1 not used 10 ain2 01 ain1 00 ain0
si8900/1/2 rev. 1.0 19 adc_h byte bitd7d6d5d4d3d2d1d0 name 1 0 mx1 mx0 d9 d8 d7 d6 type rrrrrrrr default ???????? bit name function 7:6 1,0 internal use. these bits are always set to 1,0. 5:4 mx1, mx0 adc mux address adc input mux address for the co nverted data in adc_h, adc_l. 3:0 d9: d6 adc conversion data bits d9:d6 most significant 4 bits of adc conversion data. adc_l byte bitd7d6d5d4d3d2d1d0 name 0 d5d4d3d2d1d0 0 type rrrrrrrr default ???????? bit name function 7 0 internal use. this bit is always set to 0. 6:1 d5:d0 adc conversion data bits d5:d0 least significant 6 bits of adc conversion data. 0 0 internal use. this bit is always set to 0.
si8900/1/2 20 rev. 1.0 6. applications 6.1. isolated outputs the si890x serial outputs are internally isolated from the device input side. to ensure safety in the end-user application, high voltage circuits (i.e., circuits with >30 va c) must be physically separated from the safety extra-low voltage circuits (i.e., circuits with <30 vac) by a certai n distance (creepage/clearance ). if a component straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating (commonly referred to as working voltage protection). tables published in the component standards (ul1577, iec60747, csa 5a) are readily accepted by certif ication bodies to provide proof for end-system specifications requirements. refer to the end-system sp ecification (61010-1 , 60950-1, 60601- 1, etc.) requirements before starting any circuit design th at uses galvanic isolation. to enhance the robustness of a design, it is further recommended that the user also include 100 ? resistors in series with the si890x inputs and outputs if the system is excessively noisy. the nomina l impedance of an isolated si890x output channel is approximately 50 ? and is a combination of the value of the on- chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects are a factor, output pins should be appropriately terminated with controlled-impedance pcb traces. the si890x supply inputs must be bypassed with a para llel combination of 10 f an d 0.1 f capacitors at vdda and vddb as shown in figure 15a. the capacitors should be placed as close to the package as possible. the si890x uses the vdda supply as its internal adc voltage reference by default. a precision external reference can be installed as shown in figure 15a and must be bypassed with a parallel combination of 0.1 f and 4.7 f capacitors. (note that the cnfg_0 vref bit must be set to 0 when using the external reference.) the si890x has an on-chip power on reset circuit (p or) that maintains the device in its reset state until vdda has stabilized. a 2k ? pull-up resistor on rst is strongly recommended to reduce the possibility of exte rnal noise coupling into the reset input. the si8901 will also require a 5 k ? pull-up resistor to vdda on the rsda input. figure 15. si890x installation figure 15b shows the required pcb ground configuration, where an 8 mm (min) ?keep-out area? is provided to ensure adequate creepage and clearance distance s between the two grounds. pcb metal traces cannot be present or cross through the keep-out area on the pcb top, bottom, or internal layer. si890x gnda gndb 0.1 ?f 4.7 ?f vdda si890x vref rst rsda vdda gnda vddb gndb vref 2 ?k vdda 5 ?k si8901 ? only 0.1 ?f 10 ?f 2.7 v to 3.6 v 0.1 ?f 10 ?f 2.5 v to 5.5 v 8 mm (min) gndb gnda keep r out area (no metal in this area) board ? edge board ? edge ab optional ? external ? vref
si8900/1/2 rev. 1.0 21 6.2. device reset during power-up, the si890x is held in the reset stat e by the internal power-on reset signal (por) until vdda settles above vrst. when this condition is met, a delay is initiated that maintains the si890x in the reset state for time period tpor, after which the reset signal is driven high allowing the si890x to start-up. note the maximum allowable vdd ramp time (i.e. time fr om 0 v to vdda settled above vrst) is 1 ms. slower ramp times may cause the si890x to be released from reset before vdda reaches the vrst level. figure 16 shows typical vdda monitor reset timing where the internal reset is driven low (si890x in reset) when vdda falls below vrst (e.g., during a power down or vdda brownout). the internal reset is released to its high state when vdda again settles above vr st. external circuitry can also be used to force a reset event by driving the external rst input low. a 2 k ? pull-up resistor on rst is recommended to avoid erroneous reset events from external noise coupling to the rst input. figure 16. si890x power-on and monitor reset vdda ? monitor ? reset power \on ?reset tpor v rsth v d d a v dda (min) v dda v rstl internal reset
si8900/1/2 22 rev. 1.0 6.3. application example figure 17 shows the si8900 operating as a single-phase ac line voltage and current monitor. the vdda dc bias circuit uses a low-cost 3.3 v linear regulator referenced to the neutral (white wire). the ac current is measured on adc input ain0. the ac line voltage is scaled by resist ors r17 and r18 and level-shifted by the 1.5 v vref. ac line current is measured using differential amplifier u1 c onnected across shunt resistor r1. data is transferred to the external controller or processor via the isolated uart. figure 17. ac line monitor application example u1 low ? cost ? dual ? opamp r1 c1 u2 3.3 ? v ? ldo c4 c5 si8900 ain0 vdda gnda ain1 white black d1 t x r x vddb gndb external ? master ? controller output ? side ? bias ? supply c2 1.5 ? v r2 r3 r6 r5 r7 r8 r9 1.5 ?v r11 c3 1.5 ? v r12 r13 r14 r15 r4 single r phase ac line r10 r17 r18
si8900/1/2 rev. 1.0 23 7. device pin assignments figure 18. si8900/1/2 pinout (16sow) table 6. si8900/1/2 pin assignments pin si8900 pin si8901 pin si8902 pin description 1 vdda input side vdd bias voltage (typically 3.3 v) 2vrefrst si8900/1: external voltage reference input. si8902: active low reset. 3 ain0 ain0 nc si8900: adc analog input channel 0. si8901: adc analog input channel 0. si8902: no connection 4 ain1 ain1 vref si8900: adc analog input channel 1. si8901: adc analog input channel 1. si8902: extern al vref in. 5 ain2 ain2 ain0 si8900: adc analog input channel 2. si8901: adc analog input channel 2. si8902: adc analog input channel 0. 6ncrst ain1 si8900: no connection. si8901: active low reset. si8902: adc analog input channel 1. 7rst rsda ain2 si8900: ac tive low reset. si8901: rsda bias resistor (typically 5 k ? ). si8902: adc analog input channel 2. 8 gnda input side ground 9 gndb output side ground 10 vddb output side vdd bias voltage (2.7 v to 5.5 v) 11 nc en si8900/1: no connection. si8902: spi port enable. 12 tx sda sdi si8900: uart unidirectional transmit output. si8901: i 2 c bidirectional data input/output. si8902: spi port serial data in. 13 rx scl sclk si8900: uart unid irectional receive input. si8901: i 2 c port unidirectional serial clock input. si8902: spi port unidirectional serial clock input. ain2 vddb nc nc rx tx nc vddb gndb si8900 vdda vref ain0 ain1 nc rst gnda vddb nc nc scl sda nc vddb gndb si8901 vdda vref rst ain0 ain1 ain2 rsda gnda vddb nc sdo sclk sdi en vddb gndb si8902 vdda rst nc vref ain0 ain1 ain2 gnda
si8900/1/2 24 rev. 1.0 14 nc sdo si8900/1: no connection. si8902: spi port serial data out (sdo) 15 nc no connection 16 vddb si8900/1/2: output side vd d bias voltage (2.7 v to 5.5 v). table 6. si8900/1/2 pin assignments (continued) pin si8900 pin si8901 pin si8902 pin description
si8900/1/2 rev. 1.0 25 8. ordering guide table 7. product ordering information 1,2,3 part number (opn) serial port pack age isolation rating temp range si8900b-a01-gs uart wb soic 2.5 kv ?40 to +85 c SI8900D-A01-GS uart wb soic 5.0 kv ?40 to +85 c si8901b-a01-gs i 2 c/smbus wb soic 2.5 kv ?40 to +85 c si8901d-a01-gs i 2 c/smbus wb soic 5.0 kv ?40 to +85 c si8902b-a01-gs spi port wb soic 2.5 kv ?40 to +85 c si8902d-a01-gs spi port wb soic 5.0 kv ?40 to +85 c notes: 1. add an ?r? suffix to the part number to specify th e tape and reel option. example: ?si8900ab-a-isr?. 2. all packages are rohs-compliant. 3. moisture sensitivity level is msl3 for wide-body soic-16 pa ckage with peak reflow temperatures of 260 c according to the jedec industry standard classifications and peak solder temperatures.
si8900/1/2 26 rev. 1.0 9. package outline: 16-pin wide body soic figure 19 illustrates the package details for the si8900/1/2 digital isolator. table 8 lists the values for the dimensions shown in the illustration. figure 19. 16-pin wide body soic table 8. package diagram dimensions symbol millimeters min max a ? 2.65 a1 0.1 0.3 d 10.3 bsc e 10.3 bsc e1 7.5 bsc b0.310.51 c0.200.33 e 1.27 bsc h0.250.75 l 0.4 1.27 ? 0 7
si8900/1/2 rev. 1.0 27 10. land pattern: 16-pin wide-body soic figure 20 illustrates the recommended la nd pattern details for the si8900/1/ 2 in a 16-pin wide-body soic. table 9 lists the values for the dimens ions shown in the illustration. figure 20. 16-pin soic land pattern table 9. 16-pin wide body soic land pattern dimensions dimension feature (mm) c1 pad column spacing 9.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.90 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p1032x265-16an for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed.
si8900/1/2 28 rev. 1.0 11. top marking: 16-pin wide body soic 11.1. si8900/1/2 top marking 11.2. top marking explanation line 1 marking: base part number ordering options (see ordering guide for more information). si89 = isolator product series serial port 0=uart 1=i 2 c 2 = spi y = channel configuration x = # of data channels (3, 2, 1) y = # of reverse channels (1, 0) v = insulation rating b = 2.5 kv; d = 5.0 kv line 2 marking: yy = year ww = workweek assigned by assembly subcontractor. corresponds to the year and workweek of the mold date. tttttt = mfg code manufacturing code from assembly house line 3 marking: circle = 1.5 mm diameter (center-justified) ?e3? pb-free symbol country of origin iso code abbreviation tw = taiwan si89xyov yywwtttttt tw e3
si8900/1/2 rev. 1.0 29 d ocument c hange l ist : revision 0.5 to revision 1.0 ? no changes.
si8900/1/2 30 rev. 1.0 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsibi lity for any consequences resu lting from the use of information included herein. ad ditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of t he silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmles s against all claims and damages.

▲Up To Search▲

Price & Availability of SI8900D-A01-GS

	To Download SI8900D-A01-GS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .