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qap quad analog pots peb 3465 version 1.2 data sheet, ds1, july 2000 wired communications never stop thinking.
edition 2000-07-14 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 16. 8. 00. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
wired communications p r e l i m in a r y qap quad analog pots peb 3465 version 1.2 data sheet, ds1, july 2000 never stop thinking.
for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com peb 3465 preliminary revision history: 2000-07-14 ds1 previous version: page subjects (major changes since last revision)
peb 3465 table of contents page data sheet 5 2000-07-14 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2.1 pin definition and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2.2 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.2.3 application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.1 principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.1.1 signal flow graph: ac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.1.2 signal flow graph: dc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1 mupp/qap interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2 qap/ahv-slic interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.3 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3.1 transmission values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.3.3 mupp-interface timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 39 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
peb 3465 list of figures page data sheet 6 2000-07-14 figure 1 application of an analog linecard for 16 subscribers using muslic . . 8 figure 2 pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 4 qap with ahv-slic and mupp c (for one subscriber) . . . . . . . . . . 16 figure 5 qap with ahv-slic and mupp iom-2 (for one subscriber) . . . . . . . . 16 figure 6 signal flow graph: ac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7 signal flow graph: dc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 8 mupp/qap interface: frame, bit structure . . . . . . . . . . . . . . . . . . . . . 22 figure 9 transmission characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 10 frequency response transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 11 frequency response receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 12 gain tracking (transmit and receive) . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 13 total distortion receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 14 total distortion transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 15 dc-feeding test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 16 frequency response transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 17 frequency response receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 18 frequency response: longitudinal current input & auxiliary inputs. . 38 figure 19 mupp-interface timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 20 package outline: peb 3465 (qap) . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
peb 3465 list of tables page data sheet 7 2000-07-14 table 1 muslic chip set ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2 pin definition and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3 list of components in application circuits ( figure 4 & figure 5 ) . . . . 17 table 4 total distortion receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 5 total distortion receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
peb 3465 data sheet 8 2000-07-14 preliminary 1 general description the highly integrated muslic chip set supports to realize an extremely compact analog subscriber line interface module. only a few external components are required and there is no trimming or adjustment necessary to meet worldwide recommendations. the chip set consists of three out of seven available ics: the quad analog pots ic (qap) peb 3465 provides all analog frontend functions for four completely independent channels. each channel is equipped with all necessary a/ d- and d/a converters and filter functions for the ac and dc- path as well with a control and supervision interface to the ahv-slic, including digital i/o pins for channel specific control functions. additionally the qap provides analog input pins for measurement purposes. only four signals are needed for the highspeed serial interface to the mupp iom-2/ mupp c (?mupp?), which provides all signal processing and system interfacing for 16 channels. figure 1 application of an analog linecard for 16 subscribers using muslic table 1 muslic chip set ics peb 31664 peb 31665 peb 31666 mupp c-s mupp iom ? -2 mupp c-e multichannel processor for pots peb 3465 qap quad analog pots peb 4164 peb 4165 peb 4166 ahv-slic-s ahv-slic ahv-slic-e advanced high voltage subscriber line circuit ezm07117.wmf peb 3465 peb 3465 peb 3465 peb 3465 peb 31664/ 31665/ 31666 peb 4164/ 4165/ 4166 p- dso 20-5 p- mqfp 80-1 p- mqfp 64-1 p- mqfp 44-2/ p- mqfp 64-1/ peb 4164/ 4165/ 4166 peb 4164/ 4165/ 4166 peb 4164/ 4165/ 4166 iom-2 pcm/ c
data sheet 9 2000-07-14 type package peb 3465 p-mqfp-80-1 quad analog pots qap peb 3465 version 1.2 preliminary p-mqfp-80-1 1.1 features four channel analog frontend for pots only a few external components are required no trimming or adjustments are required advanced low power bicmos 1) technology high performance ad and da conversion four pin serial interface three operating modes: power down, active and ringing standard smd p-mqfp-80-1 package 1) abbreviations see page 41
peb 3465 data sheet 10 2000-07-14 preliminary 1.2 pin configuration (top view) figure 2 pin configuration (top view) 1 2 3 4 5 6 7 8 9 1011121314151617181920 21 22 23 24 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 66 65 80 79 78 77 76 75 74 73 72 71 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 61 62 63 64 c1-a c2-a vdd-a o1-a gnd-a i/o1-a i/o2-a i1-a nc vbim vb va vddz gndz vss rref i1-b i/o2-b i/o1-b gnd-b o1-b vdd-b c2-b c1-b c1-d c2-d vdd-d o1-d gnd-d i/o1-d i/o2-d i1-d adu add afsc adcl vddi gndi adr reset i1-c i/o2-c i/o1-c gnd-c o1-c vdd-c c2-c c1-c acn-b acp-b dcn-b dcp-b il-b vr-b itac-b it-b it-c itac-c vr-c il-c dcp-c dcn-c acp-c acn-c acn-a acp-a dcn-a dcp-a il-a vr-a itac- a it-a it-d itac-d vr-d il-d dcp-d dcn-d acp-d acn-d peb 3465 p-mqfp-80-1 ezm03114.emf
peb 3465 data sheet 11 2000-07-14 preliminary 1.2.1 pin definition and functions the following tables group the pins according to their functions. they include pin number, pin name, type, a brief description of the function, and cross-references referring to the sections in which the pin functions are discussed. table 2 pin definition and functions pin no. name type function power supply pins 1 vdd-a ? + 5 v analog supply voltage (channel a) 20 vdd-b ? + 5 v analog supply voltage (channel b) 41 vdd-c ? + 5 v analog supply voltage (channel c) 60 vdd-d ? + 5 v analog supply voltage (channel d) 3 gnd-a ? analog ground (channel a) 18 gnd-b ? analog ground (channel b) 43 gnd-c ? analog ground (channel c) 58 gnd-d ? analog ground (channel d) 11 vddz ? + 5 v analog supply voltage (bias) 12 gndz ? analog ground (bias) 13 vss ? ? 5 v analog supply voltage 50 vddi ? + 3.3 v or + 5 v digital supply voltage 49 gndi ? digital ground interface pins to mupp 54 adu o analog data upstream 53 add i analog data downstream 51 adcl i analog data-clock 52 afsc i analog frame-sync. 48 adr i select odd or even port nr. 47 reset i interface-reset (active high)
peb 3465 data sheet 12 2000-07-14 preliminary interface to ahv-slic 71 it-a i transversal current input (ac+dc), channel a 72 itac-a i transversal current input (ac), channel a 73 vr-a i reference input, channel a 74 il-a i longitudinal current input, channel a 77 acp-a o two wire output voltage (acp), channel a 78 acn-a o two wire output voltage (acn), channel a 75 dcp-a o two wire output voltage (dcp), channel a 76 dcn-a o two wire output voltage (dcn), channel a 79 c1-a i/o digital interface to ahv-slic, channel a 80 c2-a o digital interface to ahv-slic, channel a 30 it-b i transversal current input (ac+dc), channel b 29 itac-b i transversal current input (ac), channel b 28 vr-b i reference input, channel b 27 il-b i longitudinal current input, channel b 24 acp-b o two wire output voltage (acp), channel b 23 acn-b o two wire output voltage (acn), channel b 26 dcp-b o two wire output voltage (dcp), channel b 25 dcn-b o two wire output voltage (dcn), channel b 22 c1-b i/o digital interface to ahv-slic, channel b 21 c2-b o digital interface to ahv-slic, channel b 31 it-c i transversal current input (ac+dc), channel c 32 itac-c i transversal current input (ac), channel c 33 vr-c i reference input, channel c 34 il-c i longitudinal current input, channel c 37 acp-c o two wire output voltage (acp), channel c 38 acn-c o two wire output voltage (acn), channel c 35 dcp-c o two wire output voltage (dcp), channel c 36 dcn-c o two wire output voltage (dcn), channel c table 2 pin definition and functions (continued) pin no. name type function
peb 3465 data sheet 13 2000-07-14 preliminary 39 c1-c i/o digital interface to ahv-slic, channel c 40 c2-c o digital interface to ahv-slic, channel c 70 it-d i transversal current input (ac+dc), channel d 69 itac-d i transversal current input (ac), channel d 68 vr-d i reference input, channel d 67 il-d i longitudinal current input, channel d 64 acp-d o two wire output voltage (acp), channel d 63 acn-d o two wire output voltage (acn), channel d 66 dcp-d o two wire output voltage (dcp), channel d 65 dcn-d o two wire output voltage (dcn), channel d 62 c1-d i/o digital interface to ahv-slic, channel d 61 c2-d o digital interface to ahv-slic, channel d table 2 pin definition and functions (continued) pin no. name type function
peb 3465 data sheet 14 2000-07-14 preliminary io pins 1) 4 io1-a i/o user-programmable i/o pin, channel a 5io2-a 2) i/o user-programmable i/o pin, channel a 6 i1-a i fixed input pin, channel a 2 o1-a o fixed output pin, channel a 17 io1-b i/o user-programmable i/o pin, channel b 16 io2-b 2) i/o user-programmable i/o pin, channel b 15 i1-b i fixed input pin, channel b 19 o1-b o fixed output pin, channel b 44 io1-c i/o user-programmable i/o pin, channel c 45 io2-c 2) i/o user-programmable i/o pin, channel c 46 i1-c i fixed input pin, channel c 42 o1-c o fixed output pin, channel c 57 io1-d i/o user-programmable i/o pin, channel d 56 io2-d 2) i/o user-programmable i/o pin, channel d 55 i1-d i fixed input pin, channel d 59 o1-d o fixed output pin, channel d miscellaneous function pins 14 rref o test pin, do not connect 10 va i voltage sense a 9 vb i voltage sense b 8 vbim i battery image sense input pins not used 7n.c. ? not connected (not used) 1) unused fixed input pin should be terminatedd with pull up or pull down. unused programmable pins should be programmed to output. 2) if the peb3465 is used together with the ahv-slics peb4164 or peb4166 it is recommended to use the io2- pin to drive the c3-pin of the slic. table 2 pin definition and functions (continued) pin no. name type function
peb 3465 data sheet 15 2000-07-14 preliminary 1.2.2 functional block diagram figure 3 functional block diagram channel a channel b channel c channel d common bias itac acp acn c1 c2 dcp it prefi s d a / d d / a buffer hw - filter hw - filter im prefi s d a / d hw - filter buffer d / a hw - filter dc - path ( 1 channel ) ac - path ( 1 channel ) hv- interface a / d supervision & i/o ( 1 channel ) vdd gnd itac acp acn c1 c2 dcp it vdd gnd rref interface for 4 channels dcn il vddi gndi vr vr dcn il itac acp acn c1 c2 dcp it vdd gnd vr dcn il itac acp acn c1 c2 dcp it vdd gnd vr dcn il vss gndz vddz va vb vbim add adu afsc adcl adr reset i / o i/o1 i1 o1 i/o2 channel a ezm17001.wmf
peb 3465 data sheet 16 2000-07-14 preliminary 1.2.3 application diagrams figure 4 qap with ahv-slic and mupp c (for one subscriber) figure 5 qap with ahv-slic and mupp iom-2 (for one subscriber) ezm07127b.wmf 50 ? 50 ? 18n / 100v bgnd 50 ? 50 ? bgnd tip ring bgnd agnd bgnd agnd supfi ahv slic agnd agnd 680k 1,5k 470n it il acp acn dcp dcn c1 c2 1,5k itac-a vr-a il-a acp-a acn-a dcp-a dcn-a c1-a c2-a it-a io1-a io2-a i1-a o1-a agnd dgnd rref gnd-a gndz gndi qap v dd-a , v ddz reset adcl afsc add adu adr dgnd reset adcl afsc add 1/2 adu 1/2 dgnd 4x680k ? io1 io2 io3 io4 id0 id1 id2 id3 dgnd vss mupp c tca dra dxa pclk tcb drb dxb dgnd a0 a7 dio0 dio7 csq ale wrq rdq intr muxq intq/mot peb 4166 peb 3465 peb 31666 c- interface pcm- highway a pcm- highway b fsc mclk agnd agnd c dcp c dcn 470n agnd v h v bat -5v v h v dd v ss v bat agnd dgnd agnd -5v v ddi v ss v a v b v bim dgnd +3,3v dgnd v dd v dd5 v bat2 v bat2 100n 100n 100n reset 22 100n +3,3v 100n v ddp dgnd 100n v h v bat 3*100n bgnd -5v 2*1 agnd 22f dgnd e.g. stps 160a +5v +5v v bat2 680k 18n / 100v r pt2 r pt1 r pr2 r pr1 c pt c pr 1) 1) this diode (one per linecard) is only necessary if it is not guaranteed that the 5v line is settled before or at the same time as v dd (3.3 v) c itac r it r il r qio c3 r qio c sup +5v +3,3v or +5v +5v +5v ezm03112.wmf 50 ? 50 ? 18n / 100v bgnd 50 ? 50 ? bgnd tip ring bgnd agnd bgnd agnd supfi ahv slic agnd agnd 680k 1,5k 470n it il acp acn dcp dcn c1 c2 1,5k itac-a vr-a il-a acp-a acn-a dcp-a dcn-a c1-a c2-a it-a io1-a io2-a i1-a o1-a agnd dgnd rref gnd-a gndz gndi qap v dd-a , v ddz reset adcl afsc add adu adr dgnd reset adcl afsc add 1/2 adu 1/2 dgnd 4x680k ? io1 io2 io3 io4 id0 id1 id2 id3 dgnd vss mupp dgnd peb 4166 peb 3465 peb 31665 agnd agnd c dcp c dcn 470n agnd v h v bat -5v v h v dd v ss v bat agnd dgnd agnd -5v v ddi v ss v a v b v bim dgnd +3,3v dgnd v dd v dd5 v bat2 v bat2 100n 100n 100n reset 22 100n +3,3v 100n v ddp dgnd 100n v h v bat 3*100n bgnd -5v 2*1 agnd 22f dgnd e.g. stps 160a +5v +5v v bat2 680k 18n / 100v bat 41 r pt2 r pt1 r pr2 r pr1 c pt c pr 1) 1) this diode (one per linecard) is only necessary if it is not guaranteed that the 5v line is settled before or at the same time as v dd (3.3 v) c itac r it r il r qio c3 r qio c sup +5v +3,3v or +5v +5v +5v dio0 dio7 csq ale wrq rdq c- interface du1 dd1 dcl fsc du2 dd2 iom ? -2 interface iom-2 dgnd tst1
peb 3465 data sheet 17 2000-07-14 preliminary table 3 list of components in application circuits ( figure 4 & figure 5 ) symbol value unit tolerance min. typ. max. r pt1 1) 1) absolut value not critical, but matching with rpr1 is important 30 50 ? 0,1 % r pt2 2) 2) absolut value not critical, but matching with rpr2 is important. 050 ? 0,1 % r pr1 30 50 ? 0,1 % r pr2 050 ? 0,1 % r it 1,5 k ? 1% r il 1,5 k ? 1% r qio 680 k ? 5% r mio 680 k ? 5% c pt 0,2 18 20 nf 10 % c pr 0,2 18 20 nf 10 % c itac 470 nf 10 % c dcp/n 100 nf 10 % c sup 470 nf 10 %
peb 3465 data sheet 18 2000-07-14 preliminary 2 functional description the multichannel signal processing subscriber line interface codec filter chip set, muslic, is a logic continuation of the well established family of the infineon technologies pcm-codec-filter-ics with the integration of all dc-feeding, supervision and meterpulse injection features on chip as well. fabricated in advanced cmos, bicmos and high voltage technology spt 170 the muslic is tailored for very flexible solutions in analog/digital communication systems. the chip set consists of the digital signal processor for 16 channels (mupp, multichannel processor for pots), the analog/digital and digital/analog converter for 4 channels (qap, quad analog pots) and the high voltage interface chip for 1 channel (ahv-slic, advanced high voltage subscriber line interface circuit). the mupp uses the benefits of a dsp not only for the voice channel but even for line feeding and supervision which leads to a very high flexibility without the need of external components. based on an advanced digital filter concept, the peb 31665/peb 31666/ peb 31664 (mupp) and the peb 3465 (qap) provide excellent transmission performance. the new filter concept leads to a maximum of independence between the different filter blocks. each filter block can be seen as a one to one representative of the corresponding network element. together with the software package muslicos, filter optimizing to different applications can be done in a clear and straight forward procedure. the ac frequency behavior is mainly determined by the digital filters. using the oversampling 1 bit ? -ad/da converters, linearity is only limited by second order parasitic effects. the digital solution of line feeding offers free programmability of feeding current and voltage as well as very fast settling of the dc-operating point after transitions. a 0.3 hz lowpass filter in the dc-loop is mainly responsible for the system stability. additionally teletax generation and filtering is implemented as well as free programmable balanced ring generation with zero-crossing injection. off hook detection with programmable thresholds is possible in all operating modes. to reduce overall power consumption of the linecard, the mupp, the qap and the ahv-slics provide a power down mode with off-hook detection (pdnr). to program the muslic or to get status information about the chip set or the system, two user interfaces are available: the iom ? -2 interface and a 8-bit-parallel simple microcontroller interface. the ahv-slics peb4165 and peb4166 provide battery feeding between - 15 v and - 80 v and ringing injection with a differential ring voltage up to 85 vrms. in order to achieve these high amplitudes, an auxiliary positive battery voltage is used during ringing. this voltage can also be applied to drive very long telephone lines. the ahv-slics are designed for a voltage feeding - current sensing line interface concept and provide sensing of transversal and longitudinal currents on both wires. in
peb 3465 data sheet 19 2000-07-14 preliminary power down mode the ahv-slic is switched off turning the line outputs to a high impedance state. off-hook supervision is provided by activating a line current sensor. 2.1 principles 2.1.1 signal flow graph: ac figure 6 signal flow graph: ac transmit path the analog input signal has to be connected to pin itac of the qap by an external capacitor (470 nf) for ac/dc separation. after passing a programmable gain stage (agx = 0, 3.5 or 9.5 db) and a simple antialiasing prefilter the voice signal is converted to a 1-bit digital data stream in the ? -converter. the first down sampling steps are done in fast running digital hardware filters on the qap. this down sampled ac-signal (64 khz sampling rate) is sent to the mupp via the mupp/qap-interface in the adu-channel. the following signal processing is done in the dsp-machine of the mupp. the benefits are the programmability of frequency and the gain behavior. at the end the fully processed signal is transferred to the pcm / iom-2 interface (a-law / ?law / 16 bit linear) signal representation. peb3465_0001_ac-work graph .emf peb31664 / peb31665 / peb31666 peb 3465 agx adc im 2 imfix1 agr dac aim im1 imfix2 int dez xfix1 frx ax1 cmp ar2 rfix2 ttx- gen. xfix2 ttx- filter x1 ax2 rfix1 frr ar1 exp th thfix + + + itac acp, acn pcm / iom -2 output pcm / iom -2 input dhpr dhpx tg1 tg2 receive path transmit path functional block user programmable block fixed filter block not available in peb 31664
peb 3465 data sheet 20 2000-07-14 preliminary receive path the digital input signal is received via the pcm / iom-2 interface of the mupp. expansion, pcm-lowpass-filtering, gain correction and frequency response correction are the next steps which are done by the dsp-machine. this 64 khz ac signal is sent from the mupp to the qap via the mupp/qap-interface in the add-channel. the up sampling interpolation steps are processed by fast hardware structures in the qap to reduce the dsp-workload. the 1-bit data stream is then converted to an analog equivalent. a subsequent programmable gain stage (agr = 0 or ? 3,5 db) and smoothing filter provides the ac output signal at the pins acp and acn of the qap for direct connection to the ahv-slic. loops there are two different loops implemented: the impedance matching (im) loop which is divided into 3 separate loops to guarantee very high flexibility to various impedances, and the transhybrid balancing (th) loop. 2.1.2 signal flow graph: dc figure 7 signal flow graph: dc user programmable block functional block fixed filter block dc - flow graph it dcp, dcn pcm / iom-2 input pcm / iom-2 output adc rng dec. ag dcr dac int. ag dcx qap mupp ramp lpo3 dcchar lpo5 levelmeter unit not available in peb 31664 ezm03113.emf
peb 3465 data sheet 21 2000-07-14 preliminary dc characteristic the incoming information (transmit direction) at pin it (scaled transversal ac + dc- current, transferred to a voltage via an external 1.5 k ? resistor at it) passes first an antialiasing filter and is then converted to a 1-bit digital data stream in the ? -converter. down sampling is done in hardware filters of the qap. this dc-information (2 khz sampling rate) is then fed to the mupp where it is first lowpass filtered (0.3 hz corner frequency) for stability and noise reasons. the following dc-characteristic consists of three branches which represents different kinds of feeding behavior. in typical applications it acts as a programmable constant current source ( r in >30k ? ). if the desired value cannot be held feeding switches automatically and smoothly to the resistive branch ( r in programmable between 0 ? 1.6 k ? ). the third branch is used for feeding long lines - the dc-characteristic switches to a constant voltage behavior. for superimposing voice as well as teletax pulses the necessary drop at the line can be calculated and taken into account as well. the outgoing bit stream (2 khz sampling rate), representing the dc-feeding value is then sent back to the qap where a 1-bit ? - converter and a following smoothing filter (using 2*100 nf external capacitor) establish the desired values at the pins dcp and dcn, respectively. depending on the operating mode (active, ringing, active with boosted battery) a gain of 0 or 4 db is inserted. for test purposes it is possible to close a loop to test either the analog part or the digital part of the dc path. additional features the qap provides three general purpose input pins (va, vb, vbim) for measuring. via the mupp/qap-interface it is possible to select one of these inputs for the measurement. the dc-signal at the selected input is converted to digital using the same ? -converter as for ground key information (il, accuracy of + 8%) and sent to the mupp. the input range is between ? 2.4 v ? + 2.4 v. as a further selection it is also possible to measure the internal vddz-voltage of the qap.this voltage is internal divided by 4 and can be measured by setting vddim.
peb 3465 data sheet 22 2000-07-14 preliminary 3 interfaces 3.1 mupp/qap interface the mupp/qap-interface, the link between mupp and qap is a serial interface based on the 6 signals afsc (analog frame sync), adcl (analog data clock), adu1/adu2 (analog data upstream) and add1/add2 (analog data downstream). adu1 and add1 are common to the first group of 8 time slots (channels) and adu2 and add2 to the second 8 time slots (channels). afsc and adcl are common to both groups of time slots. figure 8 mupp/qap interface: frame, bit structure 012 31 30 ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 . . . . . . . . 012 31 30 ch 8 ch 9 ch 14 ch 15 . . . . . . . . 0 12 31 30 dc, control 17 18 19 20 afsc add1/adu1 (slot group 1) add2/adu2 (slot group 2) 15.625 s (64 khz) 500 s (2 khz) 1.95 s (512 khz) ac (voice, data) 61ns (16.384mhz) ezm07129.wmf
peb 3465 data sheet 23 2000-07-14 preliminary 3.2 qap/ahv-slic interface output voltage ac (acp, acn) the output voltage at the pins acp and acn represents the ac-information together with teletax information at the receive path. the ac-information is received via the mupp/qap-interface in the add channel. the 64 khz bitstream is converted to analog, passes a programmable gain stage of 0 / ? 3.5 db (ttx is also affected) and is buffered to drive a load of r l >15k ? and c l < 20 pf, which is the input impedance of the ahv- slic. output voltage dc (dcp, dcn) the output voltage at the pins dcp and dcn represents the dc-information together with the ring burst at the receive path. the dc-information is received via the mupp/ qap-interface in the add channel. the 2 khz bitstream is converted to analog and buffered to drive external smoothing capacitors of 2*100 nf. the pins are directly connected to the ahv-slic. transversal current sense ac - input (itac) the pin itac is the input voltage pin for the ac transversal current information from the ahv-slic in the transmit path. ac/dc separation is done by an external highpass filter (ext. capacitor = 470 nf). the input resistance is larger than 20 k ? . current/voltage conversion is done via an external resistor of 1.5 k ? (same for pin it). the signal passes a programmable gain stage of 0, 3.5 or 9.5 db, is converted to digital and sent to the mupp via the mupp/qap-interface in the adu channel (64 khz bitstream). transversal current sense dc - input (it) the pin it is the input voltage pin for the dc transversal current information from the ahv-slic in the transmit path. the input resistance is larger than 500 k ? . current/ voltage conversion is done via an external resistor of 1.5 k ? (same for pin itac). the voltage at pin it is lowpass filtered and converted to digital. the bitstream (2 khz) is sent to the mupp via the mupp/qap-interface for further signal processing. longitudinal current sense - input (il) the scaled longitudinal current information transferred from the ahv-slic - the current/ voltage conversion is done by an external resistor of 1.5 k ? - is converted into digital and sent to the mupp via the mupp/qap-interface in the adu channel. ternary interface (c1, c2) in order to set the ahv-slics to the different operating modes, the mode information of the board-contoller is passed through from the iom-2-channel (peb 31665) or c-
peb 3465 data sheet 24 2000-07-14 preliminary interface (peb 31666, peb 31664) via the mupp/qap-interface to the ternary ahv- slic interface pins c1 and c2.
peb 3465 data sheet 25 2000-07-14 preliminary 4 electrical characteristics 4.1 absolute maximum ratings note: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. functional operation under these conditions is not implied. exposure to conditions beyond those indicated in the recommended operational conditions of this specification may effect device reliability. parameter symbol limit values unit test condition min. max. vdda-vddd referred to gnda-gndd ? 0.3 7 v vddi referred to gndi ? 0.3 7 v vss referred to all gnd pins ? 70.3v gnda-gndd to gndi ? 0.3 0.3 v vdda-vddd to vddi ? 0.3 0.3 v analog input and output voltages referred to vdd = 5 v; (vss = ? 5v) ? 10.3 0.3 v referred to vss = ? 5v;(vdd = 5v) ? 0.3 10.3 v all digital input voltages referred to gndi = 0 v; (vddi = 5 v) ? 0.3 5.3 v referred to vddi = 5 v; (gndi = 0 v) ? 5.3 0.3 v dc input and output current at any input or output pin (free from latch-up) 100 ma storage temperature t stg ? 65 125 c ambient temperature under bias t a ? 45 90 c power dissipation p d 1w
peb 3465 data sheet 26 2000-07-14 preliminary 4.2 operating range vdda...vddd, vddz = 5 v 5%; vddi= 3.3 v 5% vss = - 5 v 10%; all gnd ? s = 0 v parameter symbol limit values unit test condition min. typ. max. v dd supply current power down digital iddd pd 7 10 ma all channels pdown power down analog idda pd 10 13 ma all channels pdown active digital iddd act. 23 30 ma all channels active active analog idda act. 60 70 ma all channels active v ss supply current power down iss pdown 0.5 1 ma all channels pdown active iss act 10 13 ma all channels active power supply rejection-ratio psrr ripple: 1 khz, 80 mvrms receive vdd 45 60 db receive vss 45 60 db transmit vdd 40 60 db transmit vss 40 60 db power dissipation power down p pdown 75 108 mw all channels pdown active p act1 175 mw 1 channel active active p act 425 550 mw all channels active
peb 3465 data sheet 27 2000-07-14 preliminary 4.3 electrical parameters functionality and performance is guaranteed for t a =0 c to 70 c by production testing. extended temperature range operation at ? 40 c< t a <85 c is guaranteed by design, characterization and periodically sampling and testing production devices at the temperature extremes. the target figures in this specification are based on the subscriber-line board requirements. unless otherwise noted, the transmission characteristics are guaranteed within the test conditions. the 0 dbm0 definitions for receive and transmit are different. a 0 dbm0 signal in transmit direction is equivalent to 604 mvrms. a 0 dbm0 signal in receive direction is equivalent to 4365 mvrms. figure 9 transmission characteristics with u it = 0 dbm0| qap = ? 2.17 dbm0| 775mv = 604 mv for transmit with u ac = 0 dbm0| qap = 15.02 dbm0| 775mv = 4365 mv for receive itac it acp 470 n qap / mupp- interface u 1500 u ac it transmit receive 0 dbm0 0 dbm0 4365 mv 604 mv qap peb 3465 acn vr ezm17010.emf
peb 3465 data sheet 28 2000-07-14 preliminary 4.3.1 transmission values all vdd s=5v 5%; vss = ? 5v 10%; all gnd s=0v. parameter symbol limit values unit test condition fig. min. typ. max. absolute gain (f = 300..3400 hz) transmit (ag6db = 0) gx0 ? 0.20 0.05 0.20 db f = 1 khz receive (ag6db = 0) gr0 ? 0.20 0.05 0.20 db f = 1 khz transmit (ag6db = 1) gxg ? 0.25 0.05 0.25 db f = 1 khz receive (ag6db = 1) grg ? 0.25 0.05 0.25 db f = 1 khz transmit (ag6db = 1, usgain = 1) grg ? 0.3 0.05 0.3 db f = 1 khz transmit (ttx-signals) gttx-x ? 2.1 ? 2.4 ? 2.7 db f = 16 khz 10 receive (ttx-signals) gttx-r ? 4.0 ? 3.7 ? 3.4 db f = 16 khz 11 absolute gain variation with temp. ? 40 to 85 ?.1 db total harmonic distortion transmit thdt ? 56 ? 48 db at ? 17 dbm0; f=1khz; 2 nd , 3 rd order receive thdr ? 56 ? 48 db at ? 17 dbm0; f = khz; 2nd, 3rd order idle channel noise transmit ntp ? 96 ? 91 dbm0p psophometric, vin = 0 v nttxtp ? 99 ? 88 dbm0p psophometric, vin = 16 khz, ? 1dbm0 receive nrp ? 100 ? 95 dbm0p psophometric, code +0 nttxrp ? 96 ? 90 dbm0p psophometric, vin = 16 khz, ? 1dbm0 crosstalk; any combination of direction and channel ct ? 100 db at 0 dbm0, f = 1 khz; guaranteed by design
peb 3465 data sheet 29 2000-07-14 preliminary frequency response 1. transmit: reference frequency 1 khz, signal level ? 17 dbm0: figure 10 frequency response transmit 2. receive: reference frequency 1 khz, signal level ? 17 dbm0: figure 11 frequency response receive 0 k h z f re q u e n c y -0.2 0.2 -2.4 -2.1 -2.7 tbd 1 frequency khz gain db 0 3.4 1.0 .3 12 16 ezm17002.emf 0 k h z f re q u e n c y -0.2 0.2 -3.7 -3.4 -4.0 tbd 1 frequency khz gain db 0 3.4 1.0 .3 12 16 ezm17003.emf
peb 3465 data sheet 30 2000-07-14 preliminary 3. out-of-band signals at analog output (receive) with a 0 dbm0 sine wave with frequency f (300 hz to 3.4 khz) applied to the digital input, the level of any resulting out-of-band signal at the analog output will stay at least 45 db below a 0 dbm0, 1 khz sine wave reference signal at the analog output. gain tracking the gain deviations stay within the limits in the figure below. transmit and receive: measured with sine wave f = 1004 hz; reference level = ? 17 dbm0 figure 12 gain tracking (transmit and receive) 0 db -72 -50 -30 -20 -10 0 10 dbm0 -2 -1 +1 +2 3 input level g +0.5 -40 -17 +0.25 -0.5 -0.25 -67 -57 ezm17007.emf
peb 3465 data sheet 31 2000-07-14 preliminary total distortion the signal to distortion ratio exceeds the limits in the following figures: 1. receive: measured with sine wave f = 1004 hz. figure 13 total distortion receive table 4 total distortion receive parameter symbol limit values unit test condition fig. min. typ. max. signal to distortion sd r 48 60 db signal s = ? 14 dbm0 13 -14 0 dbm0 db 12 input level s/d 48 3 -72 -36 ezm17008.emf
peb 3465 data sheet 32 2000-07-14 preliminary 2. transmit: measured with sine wave f = 1004 hz figure 14 total distortion transmit table 5 total distortion receive parameter symbol limit values unit test condition fig. min. typ. max. signal to distortion sd t 48 60 db signal s = ? 14 dbm0 14 -14 0 dbm0 db 12 input level s/d 48 3 -72 -36 ezm17009.emf
peb 3465 data sheet 33 2000-07-14 preliminary 4.3.2 dc characteristics i/o-pins all v dd ? s = 5 v 5%; v ss = ? 5v 10%; all gnd ? s = 0 v parameter symbol limit values unit test condition min max. digital input pins adcl, afsc, add, adr, reset v low - input voltage v il ? 0.3 0.8 v high - input voltage v ih 2.0 vdd +0,3 v input leakage current i il ? 11 a ? 0.3 <= v in <= v dd spike rejection for reset t rej 50 200 ns digital output pin adu low-output voltage v ol 0.45 v i o = ? 2 ma high-output voltage v oh 2.4 v i o = 2 ma for i/o1 and o1: low-output voltage v ol 0.6 v i o = = ? 50 ma high-output voltage v oh 3.5 v i o = 2 ma for i/o2: low-output voltage v ol 0.5 v i o = = ? 2 ma high-output voltage v oh 3.5 v i o = = 2 ma
peb 3465 data sheet 34 2000-07-14 preliminary dc-feeding figure 15 dc-feeding test circuit with u it = 0 dbm0dc| qap = 1.1822 v for transmit with u dc = 0 dbm0dc| qap = 1.8915 v for receive it dcp qap / mupp- interface u 1500 u dc it transmit receive 0 dbm0dc 0 dbm0dc 1.8915 v 1.1822 v qap peb 3465 dcn vr ezm17011.emf
peb 3465 data sheet 35 2000-07-14 preliminary all v dd ? s = 5 v 5 % ; v ss = ? 5v 10%; all gnd ? s = 0 v parameter symbol limit values unit test condition fig. min. typ. max. ? line current ? measurement (it): transmit v it offset 1) 1) this offset can be compensated in the system by performing an offset measurement as described in the application note "line and board testing with muslic". ? 50 50 mv v it gain ? 0.5 ? 1.2 0 ? 0.65 0.5 ? 0.1 db db f < 50 hz f=300hz 16 16 v it thd- 40 50 db f = 300 hz additional gain variation with temperature ? 40 to + 85 0.1 db ? line voltage ? feeding (dcp, dcn): receive v dc offset ? 25 25 mv v dc gain ? 0.5 ? 1.1 0 ? 0.55 0.5 0.0 db db f<50hz, dc_dispofi = 1 f=300hz, dc_dispofi = 1 17 17 v dc thd 40 50 db f=300 hz, dc_dispofi = 1 receive boosted v dc boost 3.5 4.1 4.7 db dc_dacgain = 1 additional gain variation with temperature ? 40 to + 85 0.1 db
peb 3465 data sheet 36 2000-07-14 preliminary dc-frequency response 1. transmit: reference frequency 50 hz, signal level 0dbm0 dc figure 16 frequency response transmit 2. receive: reference frequency 50 hz, signal level 0dbm0 dc figure 17 frequency response receive 0 -0.5 0.5 -0.65 hz frequency 300 50 gain db ezm17004.emf 0 -0.5 0.5 -0.55 hz frequency 300 50 gain db ezm17005.emf
peb 3465 data sheet 37 2000-07-14 preliminary ahv-slic interface & supervision functions all v dd ? s = 5 v 5%; v ss = ? 5v 10%; all gnd ? s = 0 v parameter symbol limit values unit test condition/result fig. min. typ. max. output voltage: ahv-slic- interface c1, c2 high level v ohhv 3.65 v i out <10 a mid level v omhv 2.2 2.8 v i out <10 a low level v olhv 1.35 v i out <10 a current drained from pin c1 in all 3 states i otlo i othi 130 30 a ? tempa = 0 1) tempa = 1 1) tempa is reported via the mupp/qap-interface to the mupp longitudinal current input (il) v il gain ? 1.2 ? 0.5 0.2 db f < 50 hz; v in =0dbm0 dc 18 ? 1.8 ? 1.1 ? 0.4 db f = 300hz 18 auxiliary inputs (v a , v b , v bim ) v x gain ? 1.2 ? 0.5 0.2 db f < 50hz; v in =0dbm0 dc 18 ? 1.8 ? 1.1 ? 0.4 db f = 300hz 18 v ddim v ddim 0.22* vdd 0.24* vdd 0.26* vdd v internal connected to vddz/4 18
peb 3465 data sheet 38 2000-07-14 preliminary figure 18 frequency response: longitudinal current input & auxiliary inputs -0.5 0.5 -1.5 hz frequency 300 50 gain db -1.1 ezm17006.emf
peb 3465 data sheet 39 2000-07-14 preliminary 4.3.3 mupp-interface timing characteristics figure 19 mupp-interface timing characteristics parameter symbol limit values unit min. typ. max. period adcl t adcl 1/16384 ms adcl duty cycle t adclh 40 50 60 % period afsc t afsc 500 s afsc setup t afsc_s 10 ns afsc hold t afsc_h 10 ns add setup time t add s 10 ns add hold time t add h 10 ns adu delay t dadu 15 30 ns adcl t adcl t adclh t afsc_h t afsc_s t afsc afsc add adu t dadu t add_s t add_h ezm17012.wmf
peb 3465 data sheet 40 2000-07-14 preliminary 5 package outlines figure 20 package outline: peb 3465 (qap) p-mqfp-80-1 (plastic metric quad flat package) 0.65 0.3 12.35 0.1 2 2.45 max 1 80 index marking 17.2 14 0.25 min +0.1 0.88 1) 0.6x45? 1) does not include plastic or metal protrusions of 0.25 max per side a-b 0.2 h d 4x a-b 0.2 d 80x a b d c 0.12 80x d a-b m c 1) 14 17.2 -0.05 h 7?max -0.02 +0.08 0.15 ?.08 gpm05249.eps sorts of packing package outlines for tubes, trays etc. are contained in our data book ?ackage information. dimensions in mm smd = surface mounted device
peb 3465 data sheet 41 2000-07-14 preliminary 6 glossary act active mode adc analog digital converter agr attenuation receive agx attenuation transmit ahv-slic advanced high voltage subscriber line interface circuit bb boosted battery bicmos bipolar complementary metal oxid semiconductor c1, 2 digital interface between qap and ahv-slic cmp compander codec coder decoder dac digital analog converter dcchar dc characteristic block dcl data clock dd data downstream dsp digital signal processor exp expander frr frequency response receive filter frx frequency response transmit filter fsc frame sync. i1 fixed input pin il longitudinal current input io user programmable i/o pin isdn integrated service digital network it transversal current input (for ac and dc) itac transversal current input (for ac) mupp multi channel processor for pots muslic multi channel subscriber line interface circuit muslicos muslic oriented software o1 fixed output pin
peb 3465 data sheet 42 2000-07-14 preliminary pcm pulse code modulation pots plain old telephone service prefi antialiasing pre filter qap quad analog pots rng ring generator slic subscriber line interface circuit tst1 test pin th transhybrid balancing thfix transhybrid balancing filter (fixed) ttx teletax ttxgen teletax generator vbim battery image input
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