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ICS9FG104D idt ? frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1541c ?12/16/10 frequency generator for cpu, qpi, fbd, pcie gen 2 & sata datasheet 1 description the ICS9FG104D is a frequency timing generator that provides 4 differential output pairs that are compliant to the intel ck410 specification. it also provides support for pci-express and sata. the part synthesizes several output frequencies from either a 14.31818 mhz crystal or a 25 mhz crystal. the device can also be driven by a reference input clock instead of a crystal. it provides outputs with cycle-to-cycle jitter of less than 50 ps and output-to- output skew of less than 35 ps. the ICS9FG104D also provides a copy of the reference clock. frequency selection can be accomplished via strap pins or smbus control. key specifications ? output cycle-to-cycle jitter < 50 ps ? output to output skew < 35 ps ? +/-300 ppm frequency accuracy on output clocks ? +/-50 ppm at any frequency w/spread off features/benefits ? generates common frequencies from 14.318 mhz or 25 mhz ? crystal or reference input ? 4 - 0.7v current-mode differential output pairs ? supports serial-ata at 100 mhz ? two spread spectrum modes: 0 to -0.5 downspread and +/-0.25% centerspread ? unused inputs may be disabled in either driven or hi-z state for power management. functional block diagram stop logic xin/clkin x2 dif(3:0) control logic spread fs(2:0) s data sclk sel14m_25m# dif_stop# programmable spread pll 4 iref 2 osc r e f o u t
idt ? frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1541c ?12/16/10 ICS9FG104D frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 2 pin configuration functionality table 28-pin ssop/tssop power groups xin/clkin 1 28 vdda x2 2 27 gnda vdd 3 26 iref gnd 4 25 vfs0 refout 5 24 vfs1 vfs2 6 23 dif_0 dif_3 7 22 dif_0# dif_3# 8 21 vdd vdd 9 20 gnd gnd 10 19 dif_1 dif_2 11 18 dif_1# dif_2# 12 17 ^sel14m_25m# sdata 13 16 vspread sclk 14 15 dif_stop# ICS9FG104D ^ pin has internal 120k pull up v pin has internal 120k pull down sel14m_25m# (fs3) fs2 fs1 fs0 output(mhz) 0 000 100.00 0 001 125.00 0 010 133.33 0 011 166.67 0 100 200.00 0 101 266.00 0 110 333.00 0 111 400.00 1 000 100.00 1 001 125.00 1 010 133.33 1 011 166.67 1 100 200.00 1 101 266.00 1 110 333.00 1 111 400.00 vdd gnd 34 9,21 10,20 28 27 iref, analo g vdd, gnd for pll core descri p tion pin number refout, digital inputs dif outputs
idt ? frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1541c ?12/16/10 ICS9FG104D frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 3 pin description pin # pin name pin type description 1 xin/clkin in crystal input or reference clock input 2 x2 out crystal output, nominally 14.318mhz 3 vdd pwr power supply, nominal 3.3v 4 gnd pwr ground pin. 5 refout out reference clock output 6 vfs2 in 3.3v frequency select latched input pin with internal 120kohm pull down resistor. 7 dif_3 out 0.7v differential true clock output 8 dif_3# out 0.7v differential complementary clock output 9 vdd pwr power supply, nominal 3.3v 10 gnd pwr ground pin. 11 dif_2 out 0.7v differential true clock output 12 dif_2# out 0.7v differential complementary clock output 13 sdata i/o data pin for smbus circuitry, 5v tolerant. 14 sclk in clock pin of smbus circuitry, 5v tolerant. 15 dif_stop# in active low input to stop differential output clocks. 16 vspread in asynchronous, active high input to enable spread spectrum functionality. this pin has a 120kohm pull down resistor. 17 ^sel14m_25m# in select 14.31818 mhz or 25 mhz input frequency. this pin has an internal 120kohm pull up resistor. 1 = 14.31818 mhz, 0 = 25 mhz 18 dif_1# out 0.7v differential complementary clock output 19 dif_1 out 0.7v differential true clock output 20 gnd pwr ground pin. 21 vdd pwr power supply, nominal 3.3v 22 dif_0# out 0.7v differential complementary clock output 23 dif_0 out 0.7v differential true clock output 24 vfs1 in 3.3v frequency select latched input pin with internal 120kohm pull down resistor. 25 vfs0 in 3.3v frequency select latched input pin with internal 120kohm pull down resistor. 26 iref out this pin establishes the reference for the differential current-mode output pairs. it requires a fixed precision resistor to ground. 475ohm is the standard value for 100ohm differential impedance. other impedances require different values. see data sheet. 27 gnda pwr ground pin for the pll core. 28 vdda pwr 3.3v power for the pll core.
idt ? frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1541c ?12/16/10 ICS9FG104D frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 4 absolute max electrical characteristics - input/supply/common output parameters t a = t ambient ; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage v ih 3.3 v +/-5% 2 v dd + 0.3 v1 input low voltage v il 3.3 v +/-5% v ss - 0.3 0.8 v 1 input high current i ih v in = v dd -5 5 ua 1 i il1 v in = 0 v; inputs with no pull- up resistors -5 ua 1 i il2 v in = 0 v; inputs with pull-up resistors -200 ua 1 full active, c l = full load; f = 400 mhz 125 150 ma 1 full active, c l = full load; f = 100 mhz 110 125 ma 1 all outputs stopped driven 106 120 ma 1 all outputs stopped hi-z 48 60 ma 1 sel14m_25m# = 0 22.5 25.00 27.5 mhz 3 sel14m_25m# = 1 12.886 14.31818 15.75 mhz 3 pin inductance 1 l p in 7nh1 c in logic inputs 1.5 5 pf 1 c ou t output pin capacitance 6 pf 1 t stabcom from v dd power-up to 1st clock (commercial) 1.8 ms 1,2 t stabind from v dd power-up to 1st clock (industrial) 1.8 ms 1,2 modulation frequency f mod sel14m_25m# = 0 32.541 khz 1,3,4 modulation frequency f mod sel14m_25m# = 1 32.467 khz 1,3,4 dif output enable t di foe dif output enable after dif_stop# de-assertion 15 ns 1 input rise and fall times t r /t f 20% to 80% of vdd 5 ns 1 1 guaranteed by design, not 100% tested in production. 2 see timin g dia g rams for timin g requirements. 4 these values assume 25mhz or 14.31818mhz inputs respectively. using a higher or lower frequency will scale these fr equencies accordingly. the output frequecy selected by the fs inputs w ill also scale. for example, 27mhz input with an fs selection of 100mhz w ill yield an output fr equency of 27/25 x 100 = 108mhz. 3 input frequency should be measured at the ref pin and tuned to 0 ppm to meet ppm frequency accuracy on pll outputs. input/output capacitance 1 f i input frequency 3 clk stabilization 1,2 input low current i dd3. 3stop i dd3.3op operating supply current symbol parameter min max units vddxx 3.3v supply voltage 4.6 v ts storage temperature -65 150 c tambient a mbient operating temp?(commerical grade ) 0+70c tambient ambient operating temp?(industrial grade) -40 +85 c tcase case temperature 115 c esd prot input esd protection?human body model 2000 v
idt ? frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1541c ?12/16/10 ICS9FG104D frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 5 electrical characteristics - dif 0.7v current mode differential pair t a = t ambient ; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 ? , r p =49.9 ? , i ref = 475 ? parameter symbol conditions min typ max units notes output impedance zo 1 v o = v x 3000 ? 1 voltage high vhigh 660 850 1 voltage low vlow -150 150 1 max voltage vovs 1150 1 min voltage vuds -300 1 crossing voltage (abs) vcross(abs) 250 550 mv 1 crossing voltage (var) d-vcross crossing variation over all edges 140 mv 1 long accuracy ppm see tperiod min-max values -300 300 ppm 1,2,5 400mhz nominal 2.49988 2.5000 2.5001 ns 2 400mhz spread 2.4993 2.5133 ns 2,3 333.33mhz nominal 2.99985 3.0000 3.0002 ns 2 333.33mhz spread 2.9991 3.016 ns 2,3 266.66mhz nominal 3.74981 3.7500 3.7502 ns 2 266.66mhz spread 3.7489 3.77 ns 2,3 200mhz nominal 4.9998 5.0000 5.0003 ns 2 200mhz spread 4.9985 5.0266 ns 2,3 166.66mhz nominal 5.9997 6.0000 6.0003 ns 2 166.66mhz spread 5.9982 6.0320 ns 2,3 133.33mhz nominal 7.4996 7.5000 7.5004 ns 2 133.33mhz spread 7.4978 5.4000 ns 2,3 100.00mhz nominal 9.9995 10.0000 10.0005 ns 2 100.00mhz spread 9.9970 10.0533 ns 2,3 400mhz nominal/spread 2.4143 ns 1,2 333.33mhz nominal/spread 2.9141 ns 1,2 266.66mhz nominal/spread 3.6639 ns 1,2 200mhz nominal/spread 4.8735 ns 1,2 166.66mhz nominal/spread 5.8732 ns 1,2 133.33mhz nominal/spread 7.3728 ns 1,2 100.00mhz nominal/spread 9.8720 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r 125 ps 1 fall time variation d-t f 125 ps 1 duty cycle d t3 measured differentially 45 55 % 1 skew, output to output t sk3 v t = 50% 35 ps 1 jitter, cycle to cycle t jcyc-cyc measured differentially 50 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 3 figures are for down spread. absolute min period statistical measurement on single ended signal using oscilloscope math function. 5 +/- 50 pp m at an y fre q uenc y with s p read off 4 this figure is the peak-to-peak phase jitter as defined by pci-sig for a pci express reference clock. please visit http://www.pcisig.com for additional details 2 all lon g term accurac y and clock period s p ecifications are g uaranteed assumin g that refout is tuned to 0 mv measurement on single ended signal using absolute value. mv t absmin average period tperiod
idt ? frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1541c ?12/16/10 ICS9FG104D frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 6 electrical characteristics - ref-14.318/25 mhz t a = t ambient ; v dd = 3.3 v +/-5%;r s =33 ? c l = 5 pf (unless otherwise specified) parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values ppm 1,2 14.318mhz output nominal ns 1,2 25.000mhz output nominal ns 1,2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 output high current i oh v oh @min = 1.0 v, v oh @max = 3.135 v -29 -23 ma 1 output low current i ol v ol @min = 1.95 v, v ol @max = 0.4 v 29 27 ma 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 1 1.6 2.5 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 1 1.6 2.5 ns 1,2 duty cycle d t1 v t = 1.5 v 45 52.5 55 % 1,2 jitter t j c y c-c y ccom v t = 1.5 v (commerical) 150 200 ps 1 jitter t jcyc-cycind vt = 1.5 v (commerical) 400 600 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 0 69.8413 40.0000 2 trim ca p acitors must be used to tune the ref to the exact cr y stal fre q uenc y . clock period t period electrical characteristics - differential phase jitter parameters parameter symbol conditions min typ max units notes t jp hasepll pcie gen 1 40 86 ps (p-p) 1,2 t jphaselo pcie gen 2 10khz < f < 1.5mhz 1.2 3 ps (rms) 1,2 t jphasehigh pcie gen 2 1.5mhz < f < nyquist (50mhz) 2.2 3.1 ps (rms) 1,2 t jphqpi qpi 133mhz 4.8g/6.4gb,12ui 0.25/0.2 0.5 ps (rms) 1,3 t jphfbd3.2g fbd specs (11 to 33mhz) 2.2 3 ps (rms) 1 t jphfbd4.8g fbd specs (11 to 33mhz) 1.8 2.5 ps (rms) 1 1 guaranteed by design and characterization, not 100% tested in production. 2 see htt p ://www. p cisi g .com for com p elte s p ecs 3 first number is 4.8g link s p eed , second number is 6.4g link s p eed. from intel clock jit tool 1.5.1 jitter, phase
idt ? frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1541c ?12/16/10 ICS9FG104D frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 7 general smbus serial interface information for the ICS9FG104D how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address dc (h) ? ics clock will acknowledge ? controller (host) sends the begining byte location = n ? ics clock will acknowledge ? controller (host) sends the data byte count = x ? ics clock will acknowledge ? controller (host) starts sending byte n through byte n + x -1 ? ics clock will acknowledge each byte one at a time ? controller (host) sends a stop bit how to read: ? controller (host) will send start bit. ? controller (host) sends the write address dc (h) ? ics clock will acknowledge ? controller (host) sends the begining byte location = n ? ics clock will acknowledge ? controller (host) will send a separate start bit. ? controller (host) sends the read address dd (h) ? ics clock will acknowledge ? ics clock will send the data byte count = x ? ics clock sends byte n + x -1 ? ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . ? controller (host) will need to acknowledge each byte ? controllor (host) will send a not acknowledge bit ? controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p byte n + x - 1 data byte count = x beginning byte n stop bit x byte index block write operation slave address dc (h) beginning byte = n write start bit controller (host) tstart bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address dd (h) index block read operation slave address dc (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
idt ? frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1541c ?12/16/10 ICS9FG104D frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 8 smbus table: device control register, read/write address (dc/dd) pin # name control function type 0 1 default bit 7 rw pin 17 bit 6 rw pin 6 bit 5 rw pin 24 bit 4 rw pin 25 bit 3 rw off on pin 16 bit 2 rw hardware select software select 0 bit 1 rw driven hi-z 0 bit 0 rw down center 0 notes: 1. these bits reflect the state of the corresponding pins at power up, but may be written to if byte 0, bit 2 is set to '1'. fs3 is the sel14m_25m# pin. smbus table: output enable register pin # name control function type 0 1 default bit 7 1 bit 6 dif_3 en output enable rw disable enable 1 bit 5 dif_2 en output enable rw disable enable 1 bit 4 1 bit 3 1 bit 2 dif_1 en output enable rw disable enable 1 bit 1 dif_0 en output enable rw disable enable 1 bit 0 1 smbus table: output stop control register pin # name control function type 0 1 default bit 7 0 bit 6 dif_3 stop en free run/ stop enable rw free-run stop-able 0 bit 5 dif_2 stop en free run/ stop enable rw free-run stop-able 0 bit 4 0 bit 3 0 bit 2 dif_1 stop en free run/ stop enable rw free-run stop-able 0 bit 1 dif_0 stop en free run/ stop enable rw free-run stop-able 0 bit 0 0 reserved reserved reserved see frequency selection table, page 1 fs3 1 fs2 1 fs1 1 fs0 1 - - - - - - - byte 2 - - - - - - byte 1 - - - dif_stop# drive mode spread type 16 spread enable 1 - enable software control of frequency, spread enable (spread type always software control) 24 25 byte 0 17 6 reserved reserved reserved reserved reserved
idt ? frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1541c ?12/16/10 ICS9FG104D frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 9 smbus table: frequency select readback register pin # name control function type 0 1 default bit 7 sel14m_25m# 1 (fs3) state of pin 17 r pin 17 bit 6 fs2 1 state of pin 6 r pin 6 bit 5 fs1 1 state of pin 24 r pin 24 bit 4 fs0 1 state of pin 25 r pin 25 bit 3 spread 1 state of pin 26 r off on pin 16 bit 2 0 bit 1 0 bit 0 0 notes: 1. these bits reflect the state of the corresponding pins, regardless of whether software programming is enabled or not. smbus table: vendor & revision id register pin # name control function type 0 1 default bit 7 rid3 r - - x bit 6 rid2 r - - x bit 5 rid1 r - - x bit 4 rid0 r - - x bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 smbus table: device id pin # name control function type 0 1 default bit 7 did7 r - - 0 bit 6 did6 r - - 0 bit 5 did5 r - - 0 bit 4 did4 r - - 0 bit 3 did3 r - - 1 bit 2 did2 r - - 0 bit 1 did1 r - - 0 bit 0 did0 r - - 0 smbus table: byte count register pin # name control function type 0 1 default bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 0 bit 2 bc2 rw - - 1 bit 1 bc1 rw - - 1 bit 0 bc0 rw - - 1 byte 6 writing to this register will configure how many bytes will be read back, default is 07 = 7 bytes. - - - - - - - - byte 5 - - - - - - - byte 4 - revision id - - - - - 16 vendor id - - - 45 44 see frequency selection table, page 1 6 27 reserved reserved reserved device id = 08 hex byte 3
idt ? frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1541c ?12/16/10 ICS9FG104D frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 10 smbus table: reserved register pin # name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smbus table: reserved register pin # name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smbus table: m/n programming enable pin # name control function type 0 1 default bit 7 m/n_enable m/n prog. enable rw disable enable 0 bit 6 1 bit 5 refout_en refout enable rw disable enable 1 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smbus table: pll frequency control register pin # name control function type 0 1 default bit 7 pll n div8 n divider prog bit 8 rw x bit 6 pll n div9 n divider prog bit 9 rw x bit 5 pll m div5 rw x bit 4 pll m div4 rw x bit 3 pll m div3 rw x bit 2 pll m div2 rw x bit 1 pll m div1 rw x bit 0 pll m div0 rw x reserved reserved reserved reserved reserved reserved reserved reserved - reserved reserved reserved - - - - byte 7 - - - - - - - byte 8 - - - reserved reserved reserved reserved 5 - reserved reserved byte 9 - - - reserved reserved reserved reserved - reserved - - - byte 10 - the decimal representation of m and n divider in byte 11 and 12 will configure the pll vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = fxtal x [ndiv(9:0)+8] / [mdiv(5:0)+2] - - m divider programming bit (5:0) - - - - -
idt ? frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1541c ?12/16/10 ICS9FG104D frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 11 smbus table: pll frequency control register pin # name control function type 0 1 default bit 7 pll n div7 rw x bit 6 pll n div6 rw x bit 5 pll n div5 rw x bit 4 pll n div4 rw x bit 3 pll n div3 rw x bit 2 pll n div2 rw x bit 1 pll n div1 rw x bit 0 pll n div0 rw x smbus table: pll spread spectrum control register pin # name control function type 0 1 default bit 7 pll ssp7 rw x bit 6 pll ssp6 rw x bit 5 pll ssp5 rw x bit 4 pll ssp4 rw x bit 3 pll ssp3 rw x bit 2 pll ssp2 rw x bit 1 pll ssp1 rw x bit 0 pll ssp0 rw x smbus table: pll spread spectrum control register pin # name control function type 0 1 default bit 7 0 bit 6 pll ssp14 rw x bit 5 pll ssp13 rw x bit 4 pll ssp12 rw x bit 3 pll ssp11 rw x bit 2 pll ssp10 rw x bit 1 pll ssp9 rw x bit 0 pll ssp8 rw x byte 11 - n divider programming byte11 bit(7:0) and byte10 bit(7:6) the decimal representation of m and n divider in byte 11 and 12 will configure the pll vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = fxtal x [ndiv(9:0)+8] / [mdiv(5:0)+2] - - - - - - - byte 12 - spread spectrum programming bit(7:0) these spread spectrum bits in byte 13 and 14 will program the spread pecentage of pll - - - - - - - byte 13 - reserved spread spectrum programming bit(14:8) these spread spectrum bits in byte 13 and 14 will program the spread pecentage of pll - - - - - - -
idt ? frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1541c ?12/16/10 ICS9FG104D frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 12 asserting dif_stop# pin stops all dif outputs that are set to be stoppable after their next transition. when the smbus dif_stop tri-state bit corresponding to the dif output of interest is programmed to a '0', dif output will stop dif_true = high and dif_complement = low. when the smbus dif_stop tri-state bit corresponding to the dif output of interest is programmed to a '1', difoutputs will be tri-stated. dif_stop# - assertion (transition from '1' to '0') with the de-assertion of dif_stop# all stopped dif outputs will resume without a glitch. the maximum latency from the de-assertion to active outputs is 2 - 6 dif clock periods. if the control register tristate bit corresponding to the output of interest is programmed to '1', then the stopped dif outputs will be driven high within 15ns of dif_stop# de-assertion to a voltage greater than 200mv. dif_stop# - de-assertion (transition from '0' to '1') dif_stop# dif dif# dif_stop# tdrive_dif_stop, 15ns >200mv dif dif# dif internal
idt ? frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1541c ?12/16/10 ICS9FG104D frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 13 common recommendations for differential routing dimension or value unit figure l1 length, route as non-coupled 50ohm trace 0.5 max inch 1 l2 length, route as non-coupled 50ohm trace 0.2 max inch 1 l3 length, route as non-coupled 50ohm trace 0.2 max inch 1 rs 33 ohm 1 rt 49.9 ohm 1 down device differential routing l4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1 l4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1 differential routing to pci express connector l4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2 l4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2 dif reference clock hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express down device ref_clk input figure 1: down device routing hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express add-in board ref_clk input figure 2: pci express connector routing
idt ? frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1541c ?12/16/10 ICS9FG104D frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 14 vdiff vp-p vcm r1 r2 r3 r4 note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ics874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 standard lvds r1a = r1b = r1 r2a = r2b = r2 alternative termination for lvds and other common differential signals (figure 3) hcsl output buffer l1 l1' r1b l2 l2' r1a l4' l4 l3 r2a r2b down device ref_clk input figure 3 l3' r3 r4 component value note r5a, r5b 8.2k 5% r6a, r6b 1k 5% cc 0.1 f vcm 0.350 volts cable connected ac coupled application (figure 4) pcie device ref_clk input figure 4 r5a l4' l4 3.3 volts r5b r6a r6b cc cc
idt ? frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1541c ?12/16/10 ICS9FG104D frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 15 index area index area 1 2 n d h x 45 e1 e e - c - b .10 (.004) c .10 (.004) c c l min max min max a -- 2.00 -- .079 a1 0.05 -- .002 -- a2 1.65 1.85 .065 .073 b 0.22 0.38 .009 .015 c 0.09 0.25 .0035 .010 d e 7.40 8.20 .291 .323 e1 5.00 5.60 .197 .220 e l 0.55 0.95 .022 .037 n 0 8 0 8 variations min max min max 28 9.90 10.50 .390 .413 10-0033 reference doc.: jedec publication 95, mo-150 0.0256 basic common dimensions in millimeters in inches common dimensions 209 mil ssop n see variations see variations d mm. d (inch) symbol see variations see variations 0.65 basic 28-pin ssop package drawing and dimensions
idt ? frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 1541c ?12/16/10 ICS9FG104D frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 16 min max min max a--1.20--.047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 d e e1 4.30 4.50 .169 .177 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 variations min max min max 28 9.60 9.80 .378 .386 10-0035 4.40 mm. body, 0.65 mm. pitch tssop 6.40 basic 0.252 basic 0.0256 basic common dimensions in millimeters in inches common dimensions (173 mil) (25.6 mil) symbol see variations see variations 0.65 basic reference doc.: jedec publication 95, mo-153 n see variations see variations d mm. d (inch) index area 12 n d e1 e sea ting plane a1 a a2 e - c - -- b c l aaa c 28-pin tssop package drawing and dimensions ordering information part/order number shipping packaging package temperature 9fg104dflf tubes 28-pin ssop 0 to +70c 9fg104dflft tape and reel 28-pin ssop 0 to +70c 9fg104dfilf tubes 28-pin ssop -40 to +85c 9fg104dfilft tape and reel 28-pin ssop -40 to +85c 9fg104dglf tubes 28-pin tssop 0 to +70c 9fg104dglft tape and reel 28-pin tssop 0 to +70c 9fg104dgilf tubes 28-pin tssop -40 to +85c 9fg104dgilft tape and reel 28-pin tssop -40 to +85c parts that are ordered with a ?lf? suffix to the part number are the pb-free configuration and are rohs compliant.
ICS9FG104D frequency generator for cpu, qpi, fbd, pcie gen 2 & sata 17 innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 ? 2010 integrated device technology , inc. all rights reserved. product specifications subject to change without notice. idt, ic s, and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa tm revision history rev. issue date description page # 0.1 12/18/2008 1. created rev d data sheet from original non revision specific version. 2. updated phase noise characterisitcs for rev d. 3. corrected footnote reference to ppm on cpu electrical characteristics 0.2 4/1/2009 1. updated ppm footnotes 2. modified input frequency ranges for each setting of the sel14m_25m# input. various a 5/14/2009 1. corrected/added tstab for industrial temperature range 2. corrected/added ref cyc- cyc jitter for industrial temperature r ange 3. move to final 4, 6 b 11/8/2010 1. corrected pin type on pin 24. changed pull up pull down designators to ^ and v respectively 2, 3 c 12/16/2010 updated vdd supply voltage specs 4

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