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sg745 i 2 c clock generator for sis5591/2, or via mvp3, 3 dimm, socket 7 designs with agp support. approved product international microcircuits, inc. 525 los coches st. rev.1.7 8/14/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 1 of 13 product features ? supports pentium ? , pentium ? ii, m2,& k6 cpus. ? designed to support sis5591/2 and mvp3 logic. ? 4 cpu & 2 (sync./ async.) agp clocks ? up to 12 sdram clocks for 3 dimms. ? 6 (sync./ async.) pci clocks. ? optional common or mixed supply mode: (vdd = vddpci = vddcpu = 3.3v) or (vdd = vddpci = 3.3v, vddcpu = 2.5v) ? < 250ps skew among cpu or sdram clocks. ? < 250ps skew among pci clocks. ? i 2 c 2-wire serial interface ? programmable registers featuring: - jumperless frequency selection - enable/disable each output pin - mode as tri-state, test, or normal ? power management capability. ? 48 mhz for usb support ? internal crystal load capacitors. ? 48-pin ssop package ? spread spectrum technology for emi reduction block diagram frequency table (mhz) sd s2 s1 s0 cpu pci agp sdram 0 0 0 0 60 30 60 60 0 0 0 1 66.8 33.4 66.8 66.8 0 0 1 0 50 25 50 50 0 0 1 1 75 37.5 64 64 0 1 0 0 75 32 64 64 0 1 0 1 83.3 32 64 64 0 1 1 0 90 30 60 60 0 1 1 1 100 33.3 66.6 66.6 1 0 0 0 60 30 60 60 1 0 0 1 66.8 33.4 66.8 66.8 1 0 1 0 50 25 50 50 1 0 1 1 75 37.5 64 75 1 1 0 0 75 32 64 75 1 1 0 1 83.3 32 64 83.3 1 1 1 0 90 30 60 90 1 1 1 1 100 33.3 66.6 100 connection diagram 24 mhz sdata sclk pll2 48 mhz sd_sel# cs# s2 s1 pll1 s0 mode pci (f, 0:4) cpu (0:3) vddcpu 4 dly sdram(0:11) 12 ref0 ref1 agp (1:2) 6 2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 vdd agp2 ref1/sd_sel# vss cpu0 cpu1 vddcpu cpu2 cpu3 vss sdram0 sdram1 vddsd0 sdram2 sdram3 vss sdram4 sdram5 vddsd1 sdram6 sdram7 vss 48mhz/s0 24 mhz/mode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ref xin xout b b b b vdd ref0/cs# vss xin xout vddpci pci_f/s1 fci0/s2 vss pci1 pci2 pci3 pci4 vddpci agp1 vss sdram11 sdram10 vddsd2 sdram9 sdram8 vss sdata sclk
sg745 i 2 c clock generator for sis5591/2, or via mvp3, 3 dimm, socket 7 designs with agp support. approved product international microcircuits, inc. 525 los coches st. rev.1.7 8/14/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 2 of 13 pin description pin number pin name pwr i/o type description 4 xin vdd i these pins form an on-chip reference oscillator when connected to terminals of an external parallel resonant crystal (typ. 14.318 mhz). xin may also serve as input for an externally generated 5 xout vdd o reference signal. in which case pin 5 is left unconnected 7 pci_f vddpci o this is a bidirectional pin. during power up, this pin is an input for frequency selection s1 control bit (see page1, and app note on page 12) and sets the bit to its initial state. when the power reaches the s1 vdd i rail (see fig.1, page 3), this pin becomes a low skew pci clock output. 8 pci0 vddpci o this is a bidirectional pin. during power up, this pin is an input for frequency selection s2 control bit (see page1, and app note on page s2 vdd i 12) and sets the bit to its initial state. when the power reaches the rail( see fig.1, page 3), this pin becomes a low skew pci clock output. 10, 11, 12, 13 pci (1:4) vddpci o low skew pci output clocks. powered by vddpci 15, 47 agp(1:2) vdd o accelerated graphics port output clocks. see frequency table page1. 44, 43, 41, 40 cpu(0:3) vddcpu o low skew (<250 ps) clock outputs for host frequencies such as cpu, agp, chipset, cache. powered by vddcpu. 38, 37, 35,34, 32, 31, 29, 28, 21, 20, 18, 17 sdram(0:11) vddsd(0:2) o synchronous dram dim clocks. they are powered by vddsd0 thru vddsd2. see vddsd power pin description. 2 ref0 vdd o if mode=1 this pin becomes a buffered reference of the crystal. cs# vdd i if mode=0 then this pin controls cpu clock outputs by enabling (set to a logic 1) or disabling (set to a logic 0). 46 sd_sel# vdd i this is a bidirectional pin. during power up, this pin is an input sd_sel for selecting the sdram frequency (see page1, and app note on page 12). if sd_sel# is high (default), the sdram frequency is same as cpu. if it is low, the sdram frequency is same as agp. when the power reaches the rail, (see fig.1, page 3), ref1 vdd o this pin becomes a 14.318 mhz reference clock output. 26 48 mhz vddsd1 i/o this is a bidirectional pin. during power up, this pin is an input for frequency selection s0 control bit (see page1, and app note on page 12) and sets the bit to its initial state. after a fixed period of time (see s0 i* fig.1, page 3), this pin becomes a 48 mhz frequency clock. 25 24 mhz vddsd1 o this is a bidirectional pin. during power up, this pin is an input that enables (0) or disables (1) the power management shared pin (2, (see app note on page 12) and sets the bit to its initial state). after mode vdd i a fixed period of time (see fig.1, page 3), this pin becomes a 24 mhz frequency clock. 23 sdata vdd i serial data for i 2 c 2-wire control interface. has internal pull-up. 24 sclk vdd i serial clock of i 2 c 2-wire control interface. has internal pull-up. 3, 9, 16, 22, 27, 33, 39, 45 vss -p ground pins. 1,48 vdd -p power supply pins for analog circuit, core logic and reference clock buffers, and agp clocks. 6, 14 vddpci - p 3.3 volt power for pci clocks. 36, 30, 19 vddsd0,1,2 - p 3.3 volt power for sdram clocks. 42 vddcpu - p 3.3 or 2.5 volt power for cpu clocks. *note: require external 10k ohm pull-up resistors or 10k ohm pull down resistors for programming. a bypass capacitor (0.1 m m f) should be placed as close as possible to each power (vdd) pin. if these bypass capacitors are not close to the pins their high frequency filtering characteristic will be canceled by the lead inductances of the traces.
sg745 i 2 c clock generator for sis5591/2, or via mvp3, 3 dimm, socket 7 designs with agp support. approved product international microcircuits, inc. 525 los coches st. rev.1.7 8/14/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 3 of 13 spectrum spread clocking spectrum analysis spectrum spreading selection table rested frequency center spreading in mhz ssw=1 ssw=0 desired (actual) f min f center f max spread f min f center f max spread 50 (50.11) 49.62 49.97 50.32 +/- 0.70% 49.28 49.97 50.66 +/- 1.38% 60 (60.00) 59.75 60.10 60.45 +/- 0.58% 59.41 60.10 60.79 +/- 1.15% 66.6 (66.82) 66.39 66.74 67.09 +/- 0.52% 66.05 66.74 67.43 +/- 1.04% 75 (75.00) 74.78 75.13 75.48 +/- 0.47% 74.43 75.13 75.83 +/- 0.93% 83.3 (83.52) 83.16 83.51 83.86 +/- 0.42% 82.82 83.51 84.20 +/- 0.83% 100 (100.23) 99.59 99.94 100.29 +/- 0.35% 99.24 99.94 100.64 +/- 0.70% center spread amplitude (db ) frequency(mhz ) center without spectrum spread with spectrum spread f min f max
sg745 i 2 c clock generator for sis5591/2, or via mvp3, 3 dimm, socket 7 designs with agp support. approved product international microcircuits, inc. 525 los coches st. rev.1.7 8/14/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 4 of 13 power up bidirectional pin timing power management functions when mode=0, pin 2 is an input cs# (cpu_stop#), (when mode=1, this functions are not available). a particular output is enabled only when both the serial interface and these pins indicate that it should be enabled. the imisg745 cpu(0:3) clocks may be disabled according to the following table in order to reduce power consumption. all clocks are stopped in the low state. all clocks maintain a valid high period on transitions from running to stopped. the cpu clocks transition between running and stopped by waiting for one positive edge on pciclk_f followed by a negative edge on the clock of interest, after which high levels of the output are either enabled or disabled. cpu_stop# cpu other clks xtal & vcos 0 low running running 1 running running running please note that all clocks can be asynchronously enabled or stopped via the 2-wire i 2 c control interface. in this case all clocks are stopped in the low state. power supply vdd pci_f / s1 pci0 / s2 48 mhz / s0 24 mhz / mode ref1 / sd_sel# hi-z (tristate), inputs toggle , outputs fig.1
sg745 i 2 c clock generator for sis5591/2, or via mvp3, 3 dimm, socket 7 designs with agp support. approved product international microcircuits, inc. 525 los coches st. rev.1.7 8/14/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 5 of 13 2-wire i 2 c control interface the 2-wire control interface implements a write only slave interface. the imisg745 cannot be read back. sub- addressing is not supported, thus all preceding bytes must be sent in order to change one of the control bytes. the 2- wire control interface allows each clock output to be individually enabled or disabled. during normal data transfer, the sdata signal only changes when the sclk signal is low, and is stable when sclk is high. there are two exceptions to this. a high to low transition on sdata while sclk is high is used to indicate the start of a data transfer cycle. a low to high transition on sdata while sclk is high indicates the end of a data transfer cycle. data is always sent as complete 8-bit bytes, after which an acknowledge is generated. the first byte of a transfer cycle is a 7-bit address with a read/write bit as the lsb. data is transferred msb first. the imisg745 will respond to writes to 10 bytes (max) of data to address d2 by generating the acknowledge (low) signal on the sdata wire following reception of each byte. the imisg745 will not respond to any other control interface conditions. previously set control registers are retained. serial control registers note: the pin# column lists the affected pin number where applicable. the @pup column gives the state at true power up. bytes are set to the values shown only on true power up, and not when the pwr_dwn# pin is activated. following the acknowledge of the address byte (d2), two additional bytes must be sent: 1) command code byte, and 2) byte count byte. although the data (bits) in these two bytes are considered dont care, they must be sent and will be acknowledged. after the command code and the count bytes have been acknowledged, the below described sequence (byte 0, byte 1, byte 2, ...) will be valid and acknowledged. byte 0: frequency, function select register (1 = enable, 0 = stopped) bit @pup pin# description 7 1 * ssw bit. selects spread spectrum width. 0 = wide; 1 = narrow. see table on pa g e 3 61 * s2 (for frequency table selection by software via i2c) 51 * s1 (for frequency table selection by software via i2c) 41 * s0 (for frequency table selection by software via i2c) 3 0 * enables freq. selection by hardware (set to 0) or software i 2 c (set to 1) 2 1 * reserved 1 0 0 0 bit 1 bit 0 1 1 tri-state 1 0 normal (with spread spectrum on) mode 0 1 test mode 0 0 normal (no spread spectrum) mode
sg745 i 2 c clock generator for sis5591/2, or via mvp3, 3 dimm, socket 7 designs with agp support. approved product international microcircuits, inc. 525 los coches st. rev.1.7 8/14/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 6 of 13 serial control registers (cont.) function table function outputs description cpu pci sdram ref agp tri-state hi-z hi-z hi-z hi-z hi-z normal see table see table cpu 14.318 14.318 notes: 1. tclk is a test clock over driven on the xin input during test mode. byte 1: cpu, sio, usb clock register (1 = enable, 0 = stopped) bit @pup pin# description 7 1 26 48 mhz enable/stopped 6 1 25 24 mhz enable/stopped 5 1 - 0 = reserved for imi test. 1 = normal operation. 4 x - reserved 3 1 40 cpuclk3 enable/stopped 2 1 41 cpuclk2 enable/stopped 1 1 43 cpuclk1 enable/stopped 0 1 44 cpuclk0 enable/stopped byte 2: pci clock register (1 = enable, 0 = stopped) bit @pup pin# description 7x - reserved 6 1 7 pci_f enable/stopped 5 1 15 agp1 enable/stopped 4 1 13 pci4 enable/stopped 3 1 12 pci3 enable/stopped 2 1 11 pci2 enable/stopped 1 1 10 pci1 enable/stopped 0 1 8 pci0 enable/stopped
sg745 i 2 c clock generator for sis5591/2, or via mvp3, 3 dimm, socket 7 designs with agp support. approved product international microcircuits, inc. 525 los coches st. rev.1.7 8/14/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 7 of 13 serial control registers (cont.) byte 3: sdram clock register ( 1 = enable, 0 = stopped ) bit @pup pin# description 7 1 28,29,31,32 sdram(4:7) enable/stopped 6 1 - reserved 5 1 - reserved 4 1 - reserved 3 1 34,35,37,38 sdram(0:3) enable/stopped 2 1 - reserved 1 1 - reserved 0 1 - reserved byte 4: additional sdram clock register (1 = enable, 0 = stopped) bit @pup pin# description 7 x - reserved 6 x - reserved 5 x - reserved 4 x - reserved 3 1 17,18,20,21 sdram(8:11) enable/stopped 2 1 - reserved 1 1 - reserved 0 1 - reserved byte 5: peripheral control (1 = enable, 0 = stopped) bit @pup pin# description 7 x - reserved 6 x - reserved 5 x - reserved 4 1 47 agp2 enable/stopped 3 x - reserved 2 x - reserved 1 x 46 ref1 / sd_sel# enable/stopped 0 1 2 ref0 / cs# enable/stopped
sg745 i 2 c clock generator for sis5591/2, or via mvp3, 3 dimm, socket 7 designs with agp support. approved product international microcircuits, inc. 525 los coches st. rev.1.7 8/14/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 8 of 13 maximum ratings voltage relative to vss: -0.3v voltage relative to vdd: 0.3v storage temperature: -65oc to + 150oc ambient temperature: 0oc to +70oc maximum power supply: 7v this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, vin and vout should be constrained to the range: vss<(vin or vout) sg745 i 2 c clock generator for sis5591/2, or via mvp3, 3 dimm, socket 7 designs with agp support. approved product international microcircuits, inc. 525 los coches st. rev.1.7 8/14/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 9 of 13 tb4_v buffer characteristics for cpu (0:3) characteristic symbol min type max units conditions pull-up current min ioh min 13 - 20 ma vout = vdd - .5v pull-up current max ioh max 22 - 37 ma vout = 1.25v pull-down current min iol min 18 - 23 ma vout = 0.4v pull-down current max iol max 50 - 61 ma vout = 1.5v rise/fall time min between 0.4 v and 2.0 v trf min 0.4 - - ns 10 pf load rise/fall time max between 0.4 v and 2.0 v trf max - - 2.0 ns 20 pf load vdd = vddsd* = vddpci =3.3v 5 %, vddcpu = 2.5 + 5%, ta = 0oc to +70oc tb4 buffer characteristics for pciclk(0:4,f), sdram(0:11), and ref0 characteristic symbol min type max units conditions pull-up current min ioh min 18 - 23 ma vout = vdd - .5v pull-up current max ioh max 44 - 64 ma vout = 1.5v pull-down current min iol min 18 - 25 ma vout = 0.4v pull-down current max iol max 50 - 70 ma vout = 1.5v rise/fall time min between 0.4 v and 2.4 v trf min 0.5 - - ns 15 pf load rise/fall time max between 0.4 v and 2.4 v trf max - - 2.0 ns 30 pf load vdd = vddsd* = vddpci =3.3v 5 %, vddcpu = 2.5 + 5%, ta = 0oc to +70oc tb5 buffer characteristics for 24m, 48m and ref1 characteristic symbol min type max units conditions pull-up current min ioh min 13 - 17 ma vout = vdd - .5v pull-up current max ioh max 30 - 40 ma vout = 1.5v pull-down current min iol min 13 - 19 ma vout = 0.4v pull-down current max iol max 32 - 44 ma vout = 1.5v rise/fall time max between 0.4 v and 2.4 v trf - - 2.0 ns 20 pf load vdd = vddsd* = vddpci =3.3v 5 %, vddcpu = 2.5 + 5%, ta = 0oc to +70oc
sg745 i 2 c clock generator for sis5591/2, or via mvp3, 3 dimm, socket 7 designs with agp support. approved product international microcircuits, inc. 525 los coches st. rev.1.7 8/14/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 10 of 13 crystal and reference oscillator parameters characteristic symbol min type max units conditions frequency f o 12.00 14.31818 16.00 mhz tolerance tc - - +/-100 ppm calibration note 1 ts - - +/- 100 ppm stability (ta -10 to +60c) note 1 ta - - 5 ppm aging (first year @ 25c) note 1 mode om - - - parallel resonant pin capacitance cp 36 pf capacitance of xin and xout pins to g round (each) dc bias voltage v bias 0.3vdd vdd/2 0.7vdd v startup time ts - - 30 m s load capacitance cl - 20 - pf the crystals rated load. note 1 effective series resistance (esr) r1 - - 40 ohms power dissipation dl - - 0.10 mw note 1 shunt capacitance co - -- 8 pf crystals internal packa g e capacitance (total) for maximum accuracy, the total circuit loadin g capacitance should be equal to cl. this loadin g capacitance is the effective capacitance across the crystal pins and includes the device pin capacitance (cp) in parallel with any circuit traces, the clock g enerator and any onboard discrete load capacitors. bud g etin g calculations typical trace capacitance, (< half inch) is 4 pf, load to the crystal is therefore = 2.0 pf clock g enerator internal pin capacitance of 36 pf, load to the crystal is therefore = 18.0 pf the total parasitic capacitance would therefore be = 20.0 pf. note 1: it is recommended but not mandatory that a crystal meets these specifications.
sg745 i 2 c clock generator for sis5591/2, or via mvp3, 3 dimm, socket 7 designs with agp support. approved product international microcircuits, inc. 525 los coches st. rev.1.7 8/14/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 11 of 13 application note for selection on bidirectional pins pins 7, 8, 25, 26 and 46 are power up bidirectional pins and are used for selecting different functions in this device (see pin description, page 2). during power-up of the device, these pins are in input mode (see fig1, page4), therefore, they are considered input select pins internal to the ic, these pins have a large value pull-up each (250k w) , therefore, a selection 1 is the default. if the system uses a slow power supply (over 5ms settling time), then it is recommended to use an external pullup (rup) in order to insure a high selection. in this case, the designer may choose one of two configurations, see fig.3a and fig. 3b. fig. 3a represents an additional pull up resistor 50k w connected from the pin to the power line, which allows a faster pull to a high level. if a selection 0 is desired, then a jumper is placed on jp1 to a 5k w resistor as implemented as shown in fig. 3a. please note the selection resistors (rup, and rdn ) are placed before the damping resistor (rd) close to the pin. fig. 3b represents a single resistor 10k w connected to a 3 way jumper, jp2. when a 1 selection is desired, a jumper is placed between leads1 and 3. when a 0 selection is desired, a jumper is placed between leads 1 and 2. if the system power supply is fast (less than 5ms settling time), then fig3a only applies and pull up rup resistor is not necessary. load load fig.3a fig.3b vdd vdd rup 50k rd imisg745 bidirectional jp1 jumper jp2 3 way jumper rsel 10k rd imisg745 bidirectional rdn 5k
sg745 i 2 c clock generator for sis5591/2, or via mvp3, 3 dimm, socket 7 designs with agp support. approved product international microcircuits, inc. 525 los coches st. rev.1.7 8/14/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 12 of 13 pcb layout suggestion this is only a layout recommendation for best performance and lower emi. the designer may choose a different approach but c1, c6, c14, c19, c30, c36, c42, and c48 (all are 0.1 m f) should always be used and placed as close as possible to their vdd pins. via to vdd island via to gnd plane via to vcc plane imisg745 c6 fb3 c36 5 6 7 8 9 10 11 12 13 14 15 16 17 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 19 20 21 22 23 24 18 30 29 28 27 26 25 31 c14 c48 c30 vcc 1 fb1 c22 22 m f c22 22 m f 1 2 3 4 c1 c19 c42 vcc 3 vcc 2 fb2 c22 22 m f + + +
sg745 i 2 c clock generator for sis5591/2, or via mvp3, 3 dimm, socket 7 designs with agp support. approved product international microcircuits, inc. 525 los coches st. rev.1.7 8/14/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 13 of 13 package drawing and dimensions 48 pin ssop outline dimensions inches millimeters symbol min nom max min nom max a 0.095 0.102 0.110 2.41 2.59 2.79 a 1 0.008 0.012 0.016 0.20 0.31 0.41 a2 0.085 0.090 0.095 2.16 2.29 2.41 b 0.008 0.010 0.0135 0.203 0.254 0.343 c 0.005 .008 0.010 0.127 0.20 0.254 d 0.620 0.625 0.637 15.75 15.88 16.18 e 0.291 0.295 0.299 7.39 7.49 7.59 e 0.0256 bsc 0.640 bsc h 0.395 0.408 0.420 10.03 10.36 10.67 l 0.024 0.030 0.040 0.61 0.76 1.02 a0o 4o8o 0o4o8o ordering information part number package type production flow IMISG745BYB 48 pin ssop commercial, 0oc to +70oc note: the ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. marking: example: imi sg745byb date code, lot # IMISG745BYB flow b = commercial, 0oc to + 70oc package y = ssop revision imi device number b e a a 1 a 2 e a l c d h

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