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sprs067e may 1998 revised may 2000 1 post office box 1443 ? houston, texas 772511443 highest performance floating-point digital signal processor (dsp) tms320c6701 8.3-, 6.7-, 6-ns instruction cycle time 120-, 150-, 167-mhz clock rate eight 32-bit instructions/cycle 1 gflops tms320c6201 fixed-point dsp pin-compatible velociti ? advanced very long instruction word (vliw) 'c67x cpu core eight highly independent functional units: four alus (floating- and fixed-point) two alus (fixed-point) two multipliers (floating- and fixed-point) load-store architecture with 32 32-bit general-purpose registers instruction packing reduces code size all instructions conditional instruction set features hardware support for ieee single-precision instructions hardware support for ieee double-precision instructions byte-addressable (8-, 16-, 32-bit data) 8-bit overflow protection saturation bit-field extract, set, clear bit-counting normalization 1m-bit on-chip sram 512k-bit internal program/cache (16k 32-bit instructions) 512k-bit dual-access internal data (64k bytes) 32-bit external memory interface (emif) glueless interface to synchronous memories: sdram and sbsram glueless interface to asynchronous memories: sram and eprom 52m-byte addressable external memory space four-channel bootloading direct-memory-access (dma) controller with an auxiliary channel 16-bit host-port interface (hpi) access to entire memory map two multichannel buffered serial ports (mcbsps) direct interface to t1/e1, mvip, scsa framers st-bus-switching compatible up to 256 channels each ac97-compatible serial-peripheral-interface (spi) compatible (motorola ? ) two 32-bit general-purpose timers flexible phase-locked-loop (pll) clock generator ieee-1149.1 (jtag 2 ) boundary-scan-compatible 352-pin ball grid array (bga) package (gjc suffix) 0.18- m m/5-level metal process cmos technology 3.3-v i/os, 1.8-v internal (120-, 150-mhz) 3.3-v i/os, 1.9-v internal (167-mhz only) copyright ? 2000, texas instruments incorporated
!$%'#)!%$ !( *''$) ( % &*"!)!%$ ) '%*)( %$%'# )% (&!!)!%$( &' ) )'#( % ,( $()'*#$)( ()$' +''$)- '%*)!%$ &'%((!$ %( $%) $(('!"- !$"* )()!$ % "" &'#)'( please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 1 26 gjc (352-pin bga) package (bottom view) velociti is a trademark of texas instruments. motorola is a trademark of motorola, inc. 2 ieee standard 1149.1-1990 standard-test-access port and boundary scan architecture.

sprs067e may 1998 revised may 2000 2 post office box 1443 ? houston, texas 772511443 table of contents parameter measurement information 29 . . . . . . . . . . . . . . . signal-transition levels 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . input and output clocks 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . asynchronous memory timing 33 . . . . . . . . . . . . . . . . . . . . . synchronous-burst memory timing 35 . . . . . . . . . . . . . . . . . synchronous dram timing 39 . . . . . . . . . . . . . . . . . . . . . . . . hold /holda timing 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset timing 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external interrupt timing 46 . . . . . . . . . . . . . . . . . . . . . . . . . . host-port interface timing 47 . . . . . . . . . . . . . . . . . . . . . . . . . multichannel buffered serial port timing 50 . . . . . . . . . . . . . dmac, timer, power-down timing 61 . . . . . . . . . . . . . . . . . . jtag test-port timing 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . mechanical data 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . description 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device characteristics 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . functional block and cpu diagram 4 . . . . . . . . . . . . . . . . . . . . . cpu description 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signal groups description 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signal descriptions 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . development support 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . documentation support 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . clock pll 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings over operating case temperature range 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions 27 . . . . . . . . . . . . . . . . . . . electrical characteristics over recommended ranges of supply voltage and operating case temperature 28 . . . .

sprs067e may 1998 revised may 2000 3 post office box 1443 ? houston, texas 772511443 description the tms320c67x dsps are the floating-point dsp family in the tms320c6000 ? dsp platform. the tms320c6701 ('c6701) device is based on the high-performance, advanced velociti very-long-instruction-word (vliw) architecture developed by texas instruments (ti), making this dsp an excellent choice for multichannel and multifunction applications. with performance of up to 1 giga floating-point operations per second (gflops) at a clock rate of 167 mhz, the 'c6701 offers cost-effective solutions to high-performance dsp programming challenges. the 'c6701 dsp possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. this processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. the eight functional units provide four floating-/fixed-point alus, two fixed-point alus, and two floating-/fixed-point multipliers. the 'c6701 can produce two multiply-accumulates (macs) per cycle for a total of 334 million macs per second (mmacs). the 'c6701 dsp also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. the 'c6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. program memory consists of a 64k-byte block that is user-configurable as cache or memory-mapped program space. data memory consists of two 32k-byte blocks of ram. the peripheral set includes two multichannel buffered serial ports (mcbsps), two general-purpose timers, a host-port interface (hpi), and a glueless external memory interface (emif) capable of interfacing to sdram or sbsram and asynchronous peripherals. the 'c6701 has a complete set of development tools which includes: a new c compiler, an assembly optimizer to simplify programming and scheduling, and a windows ? debugger interface for visibility into source code execution. device characteristics table 1 provides an overview of the 'c6701 dsp. the table shows significant features of each device, including the capacity of on-chip ram, the peripherals, the execution time, and the package type with pin count, etc. table 1. characteristics of the 'c6701 processors hardware features 'c6701 emif 1 dma 4-channel peripherals host-port interface (hpi) 1 peri herals mcbsps 2 32-bit timers 2 internal program memory size (bytes) 64k internal program memory organization 64k bytes cache/mapped program internal data memory size (bytes) 64k internal data memory organization 2 blocks: eight 16-bit banks per block 50/50 split frequency mhz 120, 150, 167 cycle time ns 6 ns ('6701-167); 6.7 ns ('6701-150); 8.3 ns ('6701-120) core (v) 1.8 ('6701-120, -150) voltage core (v) 1.9 ('6701-167 only) voltage i/o (v) 3.3 pll options clkin frequency multiplier bypass (x1), x4 bga package 35 x 35 mm 352-pin gjc process technology m m 0.18 m m product status product preview (pp) advance information (ai) production data (pd) pd tms320c6000 is a trademark of texas instruments. windows is a registered trademark of microsoft corporation.

sprs067e may 1998 revised may 2000 4 post office box 1443 ? houston, texas 772511443 functional block and cpu diagram program control logic test 'c67x cpu data path b b register file program access/cache controller instruction fetch instruction dispatch instruction decode data path a a register file data access controller power- down logic .l1 2 .s1 2 .m1 2 .d1 .d2 .m2 2 .s2 2 .l2 2 32 rom/flash sram i/o devices 16 timer 0 timer 1 external memory interface (emif) multichannel buffered serial port 0 multichannel buffered serial port 1 direct memory access controller (dma) (4 channels) host port interface (hpi) internal program memory 1 block program/cache (64k bytes) control registers internal data memory (64k bytes) 2 blocks of 8 banks each in-circuit emulation interrupt control framing chips: h.100, mvip, scsa, t1, e1 ac97 devices, spi devices, codecs dma buses data bus 'c6701 digital signal processor pll (x1, x4) bus sbsram sdram host connection mc68360 glueless mpc860 glueless pci9050 bridge + inverter mc68302 + pal mpc750 + pal mpc960 (jx/rx) + pal 2 these functional units execute floating-point instructions.

sprs067e may 1998 revised may 2000 5 post office box 1443 ? houston, texas 772511443 cpu description the cpu fetches velociti advanced very-long instruction words (vliw) (256 bits wide) to supply up to eight 32-bit instructi ons to the eight functional units during every clock cycle. the velociti vliw architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. the first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. fetch packets are always 256 bits wide; however, the execute packets can vary in size. the variable-length execute packets are a key memory-saving feature, distinguishing the 'c67x cpu from other vliw architectures. the cpu features two sets of functional units. each set contains four units and a register file. one set contains functional units .l1, .s1, .m1, and .d1; the other set contains units .d2, .m2, .s2, and .l2. the two register files contain 16 32-bit registers each for the total of 32 general-purpose registers. the two sets of functional units, along with two register files, compose sides a and b of the cpu (see the functional and cpu block diagram and figure 1). the four functional units on each side of the cpu can freely share the 16 registers belonging to that side. additionally, each side features a single data bus connected to all registers on the other side, by which the two sets of functional units can access data from the register files on opposite sides. while register access by functional units on the same side of the cpu as the register file can service all the units in a single clock cycle, register access using the register file across the cpu supports one read and one write per cycle. the 'c67x cpu executes all tms320c62x ? dsp fixed-point instructions. in addition to the 'c62x dsp fixed-point instructions, the six out of eight functional units (.l1, .m1, .d1, .d2, .m2, and .l2) also execute floating-point instructions. the remaining two functional units (.s1 and .s2) also execute the new lddw instruction which loads 64 bits per cpu side for a total of 128 bits per cycle. another key feature of the 'c67x cpu is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). two sets of data-addressing units (.d1 and .d2) are responsible for all data transfers between the register files and the memory. the data address driven by the .d units allows data addresses generated from one register file to be used to load or store data to or from the other register file. the 'c67x cpu supports a variety of indirect-addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. all instructions are conditional, and most can access any one of the 32 registers. some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically atrueo). the two .m functional units are dedicated for multiplies. the two .s and .l functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. the processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. the 32-bit instructions destined for the individual functional units are alinkedo together by a1o bits in the least significant bit (lsb) position of the instructions. the instructions that are achainedo together for simultaneous execution (up to eight in total) compose an execute packet. a a0o in the lsb of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. if an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with nop instructions. the number of execute packets within a fetch packet can vary from one to eight. execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. after decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. while most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. all load and store instructions are byte-, half-word, or word-addressable. tms320c62x is a trademark of texas instruments.

sprs067e may 1998 revised may 2000 6 post office box 1443 ? houston, texas 772511443 cpu description (continued) 8 8 long src dst src2 src1 src1 src1 src1 src1 src1 src1 src1 long dst long dst dst dst dst dst dst dst dst src2 src2 src2 src2 src2 src2 src2 long src long src long dst long dst long src 8 8 8 2x 1x .l2 2 .s2 2 .m2 2 .d2 .d1 .m1 2 .s1 2 .l1 2 control register file da1 da2 st1 ld1 32 lsb ld2 32 lsb ld2 32 msb 32 32 data path a data path b register file a (a0a15) register file b (b0b15) ld1 32 msb 32 st2 32 8 8 8 2 these functional units execute floating-point instructions. figure 1. tms320c67x cpu data paths

sprs067e may 1998 revised may 2000 7 post office box 1443 ? houston, texas 772511443 signal groups description hhwil hbe0 hbe1 hcntl0 hcntl1 trst ext_int7 clock/pll ieee standard 1149.1 (jtag) emulation reserved data register select half-word/byte select boot mode reset and interrupts little endian big endian dma status power-down status control hpi (host-port interface) 16 control/status tdi tdo tms tck clkin clkout2 clkout1 clkmode1 clkmode0 pllfreq3 pllfreq2 pllfreq1 pllv pllg pllf emu1 emu0 rsv3 rsv2 rsv1 rsv0 hd[15:0] bootmode4 bootmode3 bootmode2 bootmode1 bootmode0 nmi iack inum3 inum2 inum1 inum0 lendian dmac3 dmac2 dmac1 dmac0 pd has hr/w hcs hds1 hds2 hrdy hint rsv7 rsv6 rsv5 rsv4 rsv8 ext_int6 ext_int5 ext_int4 reset rsv9 figure 2. cpu and peripheral signals

sprs067e may 1998 revised may 2000 8 post office box 1443 ? houston, texas 772511443 signal groups description (continued) ce3 are ed[31:0] ce2 ce1 ce0 ea[21:2] be3 be2 be1 be0 hold holda tout1 clkx1 fsx1 dx1 clkr1 fsr1 dr1 clks1 aoe awe ardy ssads ssoe sswe ssclk sda10 sdras sdcas sdwe sdclk tout0 clkx0 fsx0 dx0 clkr0 fsr0 dr0 clks0 data memory map space select word address byte enables hold/ holda 32 20 asynchronous memory control sbsram control sdram control emif (external memory interface) timer 1 receive receive timer 0 timers mcbsp1 mcbsp0 transmit transmit clock clock mcbsps (multichannel buffered serial ports) tinp1 tinp0 figure 3. peripheral signals

sprs067e may 1998 revised may 2000 9 post office box 1443 ? houston, texas 772511443 signal descriptions signal type 2 description name no. type 2 description clock/pll clkin c10 i clock input clkout1 af22 o clock output at full device speed clkout2 af20 o clock output at half of device speed clkmode1 c6 i clock mode select clkmode0 c5 i ? selects whether the output clock frequency = input clock frequency x4 or x1 pllfreq3 a9 pll f (3 2 d 1) pllfreq2 d11 i pll frequency range (3, 2, and 1) ? the target range for clkout1 frequency is determined by the 3 - bit value of the pllfreq p ins pllfreq1 b10 i ? th e t arge t range f or clkout1 f requency i s d e t erm i ne d b y th e 3 - bit va l ue o f th e pllfreq p i ns. pllv 3 d12 a pll analog v cc connection for the low-pass filter pllg 3 c12 a pll analog gnd connection for the low-pass filter pllf a11 a pll low-pass filter connection to external components and a bypass capacitor jtag emulation tms l3 i jtag test-port mode select (features an internal pullup) tdo w2 o/z jtag test-port data out tdi r4 i jtag test-port data in (features an internal pullup) tck r3 i jtag test-port clock trst t1 i jtag test-port reset (features an internal pulldown) emu1 y1 i/o/z emulation pin 1, pullup with a dedicated 20-k w resistor ? emu0 w3 i/o/z emulation pin 0, pullup with a dedicated 20-k w resistor ? control reset k2 i device reset nmi l2 i nonmaskable interrupt ? edge-driven (rising edge) ext_int7 u3 ext_int6 v2 i external interrupts ext_int5 w1 i external interru ts ? edge-driven (rising edge) ext_int4 u4 g(gg) iack y2 o interrupt acknowledge for all active interrupts serviced by the cpu inum3 aa1 inum2 w4 o active interrupt identification number ? valid during iack for all active interru p ts (not just external) inum1 aa2 o ? valid during iack for all active interrupts (not just external) ? en cod in g o r de r f o ll o w s t h e in te rr u p t - se rvi ce f etc h-p ac k et o r de rin g inum0 ab1 ? encoding order follows the interru t - service fetch - acket ordering lendian h3 i if high, lendian selects little-endian byte/half-word addressing order within a word if low, lendian selects big-endian addressing pd d3 o power-down mode 3 (active if high) 2 i = input, o = output, z = high impedance, s = supply voltage, gnd = ground 3 pllv and pllg are not part of external voltage supply or ground. see the clock/pll documentation for information on how to conn ect these pins. a = analog signal (pll filter) ? for emulation and normal operation, pull up emu1 and emu0 with a dedicated 20-k w resistor. for boundary scan, pull down emu1 and emu0 with a dedicated 20-k w resistor.

sprs067e may 1998 revised may 2000 10 post office box 1443 ? houston, texas 772511443 signal descriptions (continued) signal type 2 description name no. type 2 description host-port interface (hpi) hint h26 o host interrupt (from dsp to host) hcntl1 f23 i host control selects between control, address, or data registers hcntl0 d25 i host control selects between control, address, or data registers hhwil c26 i host half-word select first or second half-word (not necessarily high or low order) hbe1 e23 i host byte select within word or half-word hbe0 d24 i host byte select within word or half-word hr/w c23 i host read or write select hd15 b13 hd14 b14 hd13 c14 hd12 b15 hd11 d15 hd10 b16 hd9 a17 hd8 b17 i/o/z host port data (used for transfer of data address and control) hd7 d16 i/o/z host-port data (used for transfer of data, address, and control) hd6 b18 hd5 a19 hd4 c18 hd3 b19 hd2 c19 hd1 b20 hd0 b21 has c22 i host address strobe hcs b23 i host chip select hds1 d22 i host data strobe 1 hds2 a24 i host data strobe 2 hrdy j24 o host ready (from dsp to host) boot mode bootmode4 d8 bootmode3 b4 bootmode2 a3 i boot mode bootmode1 d5 i boot mode bootmode0 c4 2 i = input, o = output, z = high impedance, s = supply voltage, gnd = ground

sprs067e may 1998 revised may 2000 11 post office box 1443 ? houston, texas 772511443 signal descriptions (continued) signal type 2 description name no. type 2 description emif control signals common to all types of memory ce3 ae22 o/z ce2 ad26 o/z memory space enables ce1 ab24 o/z ? enabled by bits 24 and 25 of the word address ce0 ac26 o/z ? only one asserted during any external data access be3 ab25 o/z byte-enable control be2 aa24 o/z ? decoded from the two lowest bits of the internal address be1 y23 o/z ? byte-write enables for most types of memory be0 aa26 o/z ? can be directly connected to sdram read and write mask signal (sdqm) emif address ea21 j26 ea20 k25 ea19 l24 ea18 k26 ea17 m26 ea16 m25 ea15 p25 ea14 p24 ea13 r25 ea12 t26 o/z external address (word address) ea11 r23 o/z external address (word address) ea10 u26 ea9 u25 ea8 t23 ea7 v26 ea6 v25 ea5 w26 ea4 v24 ea3 w25 ea2 y26 2 i = input, o = output, z = high impedance, s = supply voltage, gnd = ground

sprs067e may 1998 revised may 2000 12 post office box 1443 ? houston, texas 772511443 signal descriptions (continued) signal type 2 description name no. type 2 description emif data ed31 ab2 ed30 ac1 ed29 aa4 ed28 ad1 ed27 ac3 ed26 ad4 ed25 af3 ed24 ae4 ed23 ad5 ed22 af4 ed21 ae5 ed20 ad6 ed19 ae6 ed18 ad7 ed17 ac8 ed16 af7 i/o/z external data ed15 ad9 i/o/z external data ed14 ad10 ed13 af9 ed12 ac11 ed11 ae10 ed10 ae11 ed9 af11 ed8 ae14 ed7 af15 ed6 ae15 ed5 af16 ed4 ac15 ed3 ae17 ed2 af18 ed1 af19 ed0 ac17 emif asynchronous memory control are y24 o/z asynchronous memory read enable aoe ac24 o/z asynchronous memory output enable awe ad23 o/z asynchronous memory write enable ardy w23 i asynchronous memory ready input 2 i = input, o = output, z = high impedance, s = supply voltage, gnd = ground

sprs067e may 1998 revised may 2000 13 post office box 1443 ? houston, texas 772511443 signal descriptions (continued) signal type 2 description name no. type 2 description emif synchronous burst sram control ssads ac20 o/z sbsram address strobe ssoe af21 o/z sbsram output enable sswe ad19 o/z sbsram write enable ssclk ad17 o sbsram clock emif synchronous dram control sda10 ad21 o/z sdram address 10 (separate for deactivate command) sdras af24 o/z sdram row-address strobe sdcas ad22 o/z sdram column-address strobe sdwe af23 o/z sdram write enable sdclk ae20 o sdram clock emif bus arbitration hold aa25 i hold request from the host holda a7 o hold-request-acknowledge to the host timers tout1 h24 o timer 1 or general-purpose output tinp1 k24 i timer 1 or general-purpose input tout0 m4 o timer 0 or general-purpose output tinp0 k4 i timer 0 or general-purpose input dma action complete dmac3 d2 dmac2 f4 o dma action complete dmac1 d1 o dma action complete dmac0 e2 multichannel buffered serial port 1 (mcbsp1) clks1 e25 i external clock source (as opposed to internal) clkr1 h23 i/o/z receive clock clkx1 f26 i/o/z transmit clock dr1 d26 i receive data dx1 g23 o/z transmit data fsr1 e26 i/o/z receive frame sync fsx1 f25 i/o/z transmit frame sync 2 i = input, o = output, z = high impedance, s = supply voltage, gnd = ground

sprs067e may 1998 revised may 2000 14 post office box 1443 ? houston, texas 772511443 signal descriptions (continued) signal type 2 description name no. type 2 description multichannel buffered serial port 0 (mcbsp0) clks0 l4 i external clock source (as opposed to internal) clkr0 m2 i/o/z receive clock clkx0 l1 i/o/z transmit clock dr0 j1 i receive data dx0 r1 o/z transmit data fsr0 p4 i/o/z receive frame sync fsx0 p3 i/o/z transmit frame sync reserved for test rsv0 t2 i reserved for testing, pullup with a dedicated 20-k w resistor rsv1 g2 i reserved for testing, pullup with a dedicated 20-k w resistor rsv2 c11 i reserved for testing, pullup with a dedicated 20-k w resistor rsv3 b9 i reserved for testing, pullup with a dedicated 20-k w resistor rsv4 a6 i reserved for testing, pulldown with a dedicated 20-k w resistor rsv5 c8 o reserved (leave unconnected, do not connect to power or ground) rsv6 c21 i reserved for testing, pullup with a dedicated 20-k resistor rsv7 b22 i reserved for testing, pullup with a dedicated 20-k resistor rsv8 a23 i reserved for testing, pullup with a dedicated 20-k resistor rsv9 e4 o reserved (leave unconnected, do not connect to power or ground) supply voltage pins a10 a15 a18 a21 a22 b7 c1 d17 f3 g24 dv dd g25 s 3.3-v supply voltage dv dd h25 s 3 . 3v su ly voltage j25 l25 m3 n3 n23 r26 t24 u24 w24 2 i = input, o = output, z = high impedance, s = supply voltage, gnd = ground

sprs067e may 1998 revised may 2000 15 post office box 1443 ? houston, texas 772511443 signal descriptions (continued) signal type 2 description name no. type 2 description supply voltage pins (continued) y4 ab3 ab4 ab26 ac6 ac10 ac19 ac21 ac22 dv dd ac25 s 3.3-v supply voltage dv dd ad11 s 3 . 3v su ly voltage ad13 ad15 ad18 ae18 ae21 af5 af6 af17 a5 a12 a16 a20 b2 b6 b11 b12 b25 cv c3 s 1.8-v suppl y volta g e ( for '6701-120, -150 ) cv dd c15 s 1 . 8v su ly voltage (for 6701 120 , 150) 1.9-v supply voltage (for '6701-167 only) c20 yg( y) c24 d4 d6 d7 d9 d14 d18 d20 2 i = input, o = output, z = high impedance, s = supply voltage, gnd = ground

sprs067e may 1998 revised may 2000 16 post office box 1443 ? houston, texas 772511443 signal descriptions (continued) signal type 2 description name no. type 2 description supply voltage pins (continued) d23 e1 f1 h4 j4 j23 k1 k23 m1 m24 n4 n25 p2 p23 t3 t4 cv u1 s 1.8-v suppl y volta g e ( for '6701-120, -150 ) cv dd v4 s 1 . 8v su ly voltage (for 6701 120 , 150) 1.9-v supply voltage (for '6701-167 only) v23 yg( y) ac4 ac9 ac12 ac13 ac18 ac23 ad3 ad8 ad14 ad24 ae2 ae8 ae12 ae25 af12 2 i = input, o = output, z = high impedance, s = supply voltage, gnd = ground

sprs067e may 1998 revised may 2000 17 post office box 1443 ? houston, texas 772511443 signal descriptions (continued) signal type 2 description name no. type 2 description ground pins a1 a2 a4 a13 a14 a25 a26 b1 b3 b5 b24 b26 c2 c7 c13 c16 c17 c25 d13 v ss d19 gnd ground pins v ss e3 gnd ground ins e24 f2 f24 g3 g4 g26 j3 l23 l26 m23 n1 n2 n24 n26 p1 p26 r24 t25 2 i = input, o = output, z = high impedance, s = supply voltage, gnd = ground

sprs067e may 1998 revised may 2000 18 post office box 1443 ? houston, texas 772511443 signal descriptions (continued) signal type 2 description name no. type 2 description ground pins (continued) u2 u23 v1 v3 y3 y25 aa3 aa23 ab23 ac2 ac5 ac7 ac14 ac16 ad2 ad12 ad16 ad20 v ss ad25 gnd ground pins v ss ae1 gnd ground ins ae3 ae7 ae9 ae13 ae16 ae19 ae23 ae24 ae26 af1 af2 af8 af10 af13 af14 af25 af26 2 i = input, o = output, z = high impedance, s = supply voltage, gnd = ground

sprs067e may 1998 revised may 2000 19 post office box 1443 ? houston, texas 772511443 signal descriptions (continued) signal type 2 description name no. type 2 description remaining unconnected pins a8 b8 c9 d10 d21 nc g1 unconnected pins nc h1 unconnected ins h2 j2 k3 r2 2 i = input, o = output, z = high impedance, s = supply voltage, gnd = ground

sprs067e may 1998 revised may 2000 20 post office box 1443 ? houston, texas 772511443 development support ti offers an extensive line of development tools for the tms320c6000 dsp platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. the following products support development of c6000 dsp-based applications: software development tools: code composer studio integrated development environment (ide): including editor c/c++/assembly code generation, and debug plus additional development tools scalable, real-time foundation software (dsp bios), which provides the basic run-time target software needed to support any dsp application. hardware development tools: extended development system (xds ? ) emulator (supports c6000 dsp multiprocessor system debug) evm (evaluation module) the tms320 dsp development support reference guide (spru011) contains information about development-support products for all tms320 dsp family member devices, including documentation. see this document for further information on tms320 dsp documentation or any tms320 dsp support products from texas instruments. an additional document, the tms320 third-party support reference guide (spru052), contains information about tms320 dsp-related products from other companies in the industry. to receive tms320 dsp literature, contact the literature response center at 800/477-8924. for a complete listing of development-support tools for the tms320c6000 dsp platform, visit the texas instruments web site on the worldwide web at http://www.ti.com uniform resource locator (url) and under adevelopment toolso, select adigital signal processorso. for information on pricing and availability, contact the nearest ti field sales office or authorized distributor. code composer studio, xds, and tms320 are trademarks of texas instruments.

sprs067e may 1998 revised may 2000 21 post office box 1443 ? houston, texas 772511443 device and development-support tool nomenclature to designate the stages in the product-development cycle, ti assigns prefixes to the part numbers of all tms320 ? dsp devices and support tools. each tms320 ? dsp family member has one of three prefixes: tmx, tmp, or tms. t exas instruments recommends two of three possible prefix designators for support tools: tmdx and tmds. these prefixes represent evolutionary stages of product development from engineering prototypes (tmx/tmdx) through fully qualified production devices/tools (tms/tmds). device development evolutionary flow: tmx experimental device that is not necessarily representative of the final device's electrical specifications tmp final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification tms fully qualified production device support tool development evolutionary flow: tmdx development-support product that has not yet completed t exas instruments internal qualification testing. tmds fully qualified development-support product tmx and tmp devices and tmdx development-support tools are shipped against the following disclaimer: adevelopmental product is intended for internal evaluation purposes.o tms devices and tmds development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. ti's standard warranty applies. predictions show that prototype devices (tmx or tmp) have a greater failure rate than the standard production devices. t exas instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. only qualified production devices are to be used. ti device nomenclature also incl udes a suffix with the device family name. this suffix indicates the package type (for example, gjc), the temperature range (for example, blank is the default commercial temperature range), and the device speed range in megahertz (for example, -167 is 167 mhz). table 2 identifies the available tms320c6701 devices by their associated orderable part numbers (p/ns) and gives device-specific ordering information (for example, device speeds, core and i/o supply voltage values, and device operating temperature ranges). figure 4 provides a legend for reading the complete device name for any tms320 ? dsp family member. table 2. tms320c6701 device p/ns and ordering information device orderable p/n device speed cv dd (core voltage) dv dd (i/o voltage) operating case temperature range tmsc6701gjc16719v 167 mhz/1 gflops 1.9 v 3.3 v 0 c to 90 c tms320c6701gjc150 150 mhz/900 mflops 1.8 v 3.3 v 0 c to 90 c tms320c6701gjca120 120 mhz/720 mflops 1.8 v 3.3 v 40 c to 105 c

sprs067e may 1998 revised may 2000 22 post office box 1443 ? houston, texas 772511443 device and development-support tool nomenclature (continued) prefix device speed range tms 320 c 6701 gjc 167 tmx = experimental device tmp = prototype device tms = qualified device smj = mil-prf-38535 (qml) sm = commercial processing device family 320 = tms320 ? dsp family technology 100 mhz 120 mhz 150 mhz 167 mhz package type 2 n = plastic dip j = ceramic dip jd = ceramic dip side-brazed gb = ceramic pga fz = ceramic cc fn = plastic leaded cc fd = ceramic leadless cc pj = 100-pin plastic eiaj qfp pq = 132-pin plastic bumpered qfp pz = 100-pin plastic tqfp pbk = 128-pin plastic tqfp pge = 144-pin plastic tqfp gfn = 256-pin plastic bga ggu = 144-pin plastic bga ggp = 352-pin plastic bga gjc = 352-pin plastic bga gjl = 352-pin plastic bga gls = 384-pin plastic bga glw = 340-pin plastic bga ghk = 288-pin plastic microstar bga c = cmos e = cmos eprom f = cmos flash eeprom device '1x dsp: 10 16 14 17 15 '2x dsp: 25 26 '2xx dsp: 203 206 240 204 209 '3x dsp: 30 31 32 '4x dsp: 40 44 '5x dsp: 50 53 51 56 52 57 '54x dsp: 541 545 542 546 543 548 '6x dsp: 6201 6205 6202 6211 6202b 6701 6203 6711 6204 2 dip = dual-in-line package pga = pin grid array cc = chip carrier qfp = quad flat package tqfp = thin quad flat package bga = ball grid array temperature range (default: 0 c to 90 c) (a) blank = 0 c to 90 c, commercial temperature a = 40 c to 105 c, extended temperature 200 mhz 233 mhz 250 mhz 300 mhz figure 4. tms320 ? dsp device nomenclature (including tms320c6701) microstar bga is a trademark of texas instruments.

sprs067e may 1998 revised may 2000 23 post office box 1443 ? houston, texas 772511443 documentation support extensive documentation supports all tms320 ? dsp family generations of devices from product announcement through applications development. the types of documentation available include: data sheets, such as this document, with design specifications; complete user's reference guides for all devices; technical briefs; development-support tools; and hardware and software applications. the following is a brief, des criptive list of support documentation specific to the 'c6x devices: the tms320c6000 cpu and instruction set reference guide (literature number spru189) describes the c6000 ? dsp cpu architecture, instruction set, pipeline, and associated interrupts. the tms320c6000 peripherals reference guide (literature number spru190) describes the functionality of the peripherals available on 'c6x devices, such as the external memory interface (emif), host-port interface (hpi), multichannel buffered serial ports (mcbsps), direct-memory-access (dma), enhanced direct-memory-access (edma) controller, expansion bus (xb), clocking and phase-locked loop (pll); and power-down modes. this guide also includes information on internal data and program memories. the tms320c6000 technical brief (literature number spru197) gives an introduction to the 'c62x/c67x devices, associated development tools, and third-party support. the tools support documentation is electronically available within the code composer studio ? integrated development environment (ide). for a complete listing of c6000 ? dsp latest documentation, visit the texas instruments web site on the worldwide web at http://www.ti.com uniform resource locator (url).

sprs067e may 1998 revised may 2000 24 post office box 1443 ? houston, texas 772511443 clock pll all of the internal 'c67x clocks are generated from a single source through the clkin pin. this source clock either drives the pll, which multiplies the source clock in frequency to generate the internal cpu clock, or bypasses the pll to become the internal cpu clock. to use the pll to generate the cpu clock, the external pll filter circuit must be properly designed. table 3, table 4, and figure 5 show the external pll circuitry for either x1 (pll bypass) or x4 pll multiply modes. table 3 and figure 6 show the external pll circuitry for a system with only x1 (pll bypass) mode. to minimize the clock jitter, a single clean power supply should power both the 'c67x device and the external clock oscillator circuit. noise coupling into pllf will directly impact pll clock jitter. the minimum clkin rise and fall times should also be observed. for the input clock timing requirements, see the input and output clocks electricals section. table 3. clkout1 frequency ranges 2 pllfreq3 (a9) pllfreq2 (d11) pllfreq1 (b10) clkout1 frequency range (mhz) 0 0 0 50140 0 0 1 65167 0 1 0 130167 2 due to overlap of frequency ranges when choosing the pllfreq, more than one frequency range can contain the clkout1 frequency. choose the lowest frequency range that includes the desired frequency. for example, for clkout1 = 133 mhz, choose pllfreq value of 000b. for clkout1 = 167 mhz, choose pllfreq value of 001b. pllfreq values other than 000b, 001b, and 010b are reserved. table 4. 'c6701 pll component selection table clkmode clkin range (mhz) cpu clock frequency (clkout1) range (mhz) clkout2 range (mhz) r1 ( w ) c1 (nf) c2 (pf) typical lock time ( m s) 3 x4 12.541.7 50167 2583.5 60.4 27 560 75 3 under some operating conditions, the maximum pll lock time may vary as much as 150% from the specified typical value. for examp le, if the typical lock time is specified as 100 m s, the maximum value may be as long as 250 m s.

sprs067e may 1998 revised may 2000 25 post office box 1443 ? houston, texas 772511443 clock pll (continued) available multiply factors clkmode1 clkmode0 pll multiply factors cpu clock frequency f(cpuclock) 0 0 x1(bypass) 1 x f(clkin) 0 1 reserved reserved 1 0 reserved reserved 1 1 x4 4 x f(clkin) notes: a. keep the lead length and the number of vias between the pllf pin, the pllg pin, and r1, c1, and c2 to a minimum. in add ition, place all pll external components (r1, c1, c2, c3, c4, and the emi filter) as close to the c6000 ? dsp device as possible. for the best performance, ti recommends that all the pll external components be on a single side of the board without jumpers, switches, or components other than the ones shown. b. for reduced pll jitter, maximize the spacing between switching signals and the pll external components (r1, c1, c2, c3, c4, and the emi filter). c. the 3.3-v supply for the emi filter must be from the same 3.3-v power plane supplying the i/o voltage, dv dd . d. emi filter manufacturer: tdk part number acf451832-333, 223, 153, 103. panasonic part number exccet103u. figure 5. external pll circuitry for either pll x4 mode or x1 (bypass) mode clkmode0 clkmode1 pll pllv clkin loop filter pllclk pllmult clkin pllg internal to 'c6701 cpu clock pllf 1 0 3.3v (see table 3) pllfreq1 pllfreq2 pllfreq3 notes: a. for a system with only pll x1 (bypass) mode, short the pllf terminal to the pllg terminal. b. the 3.3-v supply for the emi filter must be from the same 3.3-v power plane supplying the i/o voltage, dv dd . figure 6. external pll circuitry for x1 (bypass) mode only clkmode0 clkmode1 pll pllv clkin loop filter pllclk pllmult clkin pllg c2 internal to 'c6701 cpu clock c1 r1 3.3v 10 f 0.1 f pllf emi filter c3 c4 1 0 (see table 3) pllfreq1 pllfreq2 pllfreq3

sprs067e may 1998 revised may 2000 26 post office box 1443 ? houston, texas 772511443 absolute maximum ratings over operating case temperature range (unless otherwise noted) 2 supply voltage range, cv dd (see note 1) 0.3 v to 2.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltage range, dv dd (see note 1) 0.3 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range 0.3 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range 0.3 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating case temperature range, t c (default) 0 c to 90 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a version) 40 c to 105 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 55 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: all voltage values are with respect to v ss . recommended operating conditions min nom max unit cv supply voltage core 3 '6701-120, -150 1.71 1.8 1.89 v cv dd supply voltage, core 3 '6701-167 only 1.81 1.9 1.99 v dv dd supply voltage, i/o 3 3.14 3.30 3.46 v v ss supply ground 0 0 0 v v ih high-level input voltage 2.0 v v il low-level input voltage 0.8 v i oh high-level output current 12 ma i ol low-level output current 12 ma t c case tem p erature default 0 90 c t c case temperature a version 40 105 c 3 ti dsp's do not require specific power sequencing between the core supply and the i/o supply. however, systems should be design ed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage. exces sive exposure to these conditions can adversely affect the long term reliability of the device. system-level concerns such as bus contention may require supply sequencing to be implemented. in this case, the core supply should be powered up at the same time as, or prior to (and powered down after), the i/o buf fers. for additional power supply sequencing information, see the power supply sequencing solutions for dual supply voltage dsps application report (literature number slva073).

sprs067e may 1998 revised may 2000 27 post office box 1443 ? houston, texas 772511443 electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) parameter test conditions min typ max unit v oh high-level output voltage dv dd = min, i oh = max 2.4 v v ol low-level output voltage dv dd = min, i ol = max 0.6 v i i input current 2 v i = v ss to dv dd 10 ua i oz off-state output current v o = dv dd or 0 v 10 ua i supply current cpu cpu memory access 3 cv dd = nom, cpu clock = 150 mhz 470 ma i dd2v supply current, cpu + cpu memory access 3 cv dd = nom, cpu clock = 120 mhz 380 ma i supply current peripherals 3 cv dd = nom, cpu clock = 150 mhz 250 ma i dd2v supply current, peripherals 3 cv dd = nom, cpu clock = 120 mhz 200 ma i supply current i/o pins 3 dv dd = nom, cpu clock = 150 mhz 85 ma i dd3v supply current, i/o pins 3 dv dd = nom, cpu clock = 120 mhz 70 ma c i input capacitance 10 pf c o output capacitance 10 pf 2 tms and tdi are not included due to internal pullups. trst is not included due to internal pulldown. 3 measured with average activity (50% high / 50% low power). for more detailed information on cpu/peripheral/i/o activity, see the tms320c6000 power consumption summary application report (literature number spra486).

sprs067e may 1998 revised may 2000 28 post office box 1443 ? houston, texas 772511443 parameter measurement information tester pin electronics v ref i ol c t = 30 pf 2 i oh output under test 50 w 2 typical distributed load circuit capacitance. signal-transition levels all input and output timing parameters are referenced to 1.5 v for both a0o and a1o logic levels. v ref = 1.5 v figure 7. input and output voltage reference levels for ac timing measurements

sprs067e may 1998 revised may 2000 29 post office box 1443 ? houston, texas 772511443 input and output clocks timing requirements for clkin ('c6701-150, -167 devices only) 23 (see figure 8) 'c6701-150 'c6701-167 no. clkmode = x4 clkmode = x1 clkmode = x4 clkmode = x1 unit no. min max min max min max min max unit 1 t c(clkin) cycle time, clkin 26.7 6.7 24 6 ns 2 t w(clkinh) pulse duration, clkin high 0.4c 0.45c 0.4c 0.45c ns 3 t w(clkinl) pulse duration, clkin low 0.4c 0.45c 0.4c 0.45c ns 4 t t(clkin) transition time, clkin 5 0.6 5 0.6 ns 2 the reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of v ih . 3 c = clkin cycle time in ns. for example, when clkin frequency is 10 mhz, use c = 100 ns. timing requirements for clkin ('c6701-120 device only) 23 (see figure 8) 'c6701-120 no. clkmode = x4 clkmode = x1 unit no. min max min max unit 1 t c(clkin) cycle time, clkin 33.3 8.3 ns 2 t w(clkinh) pulse duration, clkin high 0.4c 0.45c ns 3 t w(clkinl) pulse duration, clkin low 0.4c 0.45c ns 4 t t(clkin) transition time, clkin 5 0.6 ns 2 the reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of v ih . 3 c = clkin cycle time in ns. for example, when clkin frequency is 10 mhz, use c = 100 ns. clkin 1 2 3 4 4 figure 8. clkin timings

sprs067e may 1998 revised may 2000 30 post office box 1443 ? houston, texas 772511443 input and output clocks (continued) switching characteristics for clkout1 23 (see figure 9) no. parameter 'c6701-120 'c6701-150 'c6701-167 unit no . parameter clkmode = x4 clkmode = x1 unit min max min max 1 t c(cko1) cycle time, clkout1 p 0.7 p + 0.7 p 0.7 p + 0.7 ns 2 t w(cko1h) pulse duration, clkout1 high (p/2) 0.5 (p/2) + 0.5 ph 0.5 ph + 0.5 ns 3 t w(cko1l) pulse duration, clkout1 low (p/2) 0.5 (p/2) + 0.5 pl 0.5 pl + 0.5 ns 4 t t(cko1) transition time, clkout1 0.6 0.6 ns 2 p = 1/cpu clock frequency in nanoseconds (ns). 3 ph is the high period of clkin in ns and pl is the low period of clkin in ns. clkout1 1 3 4 4 2 figure 9. clkout1 timings switching characteristics for clkout2 (see figure 10) no. parameter 'c6701-120 'c6701-150 'c6701-167 unit min max 1 t c(cko2) cycle time, clkout2 2p 0.7 2p + 0.7 ns 2 t w(cko2h) pulse duration, clkout2 high p 0.7 p + 0.7 ns 3 t w(cko2l) pulse duration, clkout2 low p 0.7 p + 0.7 ns 4 t t(cko2) transition time, clkout2 0.6 ns p = 1/cpu clock frequency in ns. clkout2 1 2 3 4 4 figure 10. clkout2 timings

sprs067e may 1998 revised may 2000 31 post office box 1443 ? houston, texas 772511443 input and output clocks (continued) sdclk, ssclk timing parameters sdclk timing parameters are the same as clkout2 parameters. ssclk timing parameters are the same as clkout1 or clkout2 parameters, depending on ssclk configuration. switching characteristics for the relation of ssclk, sdclk, and clkout2 to clkout1 (see figure 11) no. parameter 'c6701-120 'c6701-150 'c6701-167 unit min max 1 t d(cko1-ssclk) delay time, clkout1 edge to ssclk edge 0.8 3.4 ns 2 t d(cko1-ssclk1/2) delay time, clkout1 edge to ssclk edge (1/2 clock rate) 1.0 3.0 ns 3 t d(cko1-cko2) delay time, clkout1 edge to clkout2 edge 1.5 2.5 ns 4 t d(cko1-sdclk) delay time, clkout1 edge to sdclk edge 1.5 1.9 ns 4 3 2 1 clkout1 ssclk ssclk (1/2rate) clkout2 sdclk figure 11. relation of clkout2, sdclk, and ssclk to clkout1

sprs067e may 1998 revised may 2000 32 post office box 1443 ? houston, texas 772511443 asynchronous memory timing timing requirements for asynchronous memory cycles 2 (see figure 12 and figure 13) no. 'c6701-120 'c6701-150 'c6701-167 unit min max 6 t su(edv-cko1h) setup time, read edx valid before clkout1 high 4.5 ns 7 t h(cko1h-edv) hold time, read edx valid after clkout1 high 1.5 ns 10 t su(ardy-cko1h) setup time, ardy valid before clkout1 high 3.5 ns 11 t h(cko1h-ardy) hold time, ardy valid after clkout1 high 1.5 ns 2 to ensure data setup time, simply program the strobe width wide enough. ardy is internally synchronized. if ardy does meet setu p or hold time, it may be recognized in the current cycle or the next cycle. thus, ardy can be an asynchronous input. switching characteristics for asynchronous memory cycles 3 (see figure 12 and figure 13) no. parameter 'c6701-120 'c6701-150 'c6701-167 unit min max 1 t d(cko1h-cev) delay time, clkout1 high to cex valid 1.0 4.5 ns 2 t d(cko1h-bev) delay time, clkout1 high to bex valid 4.5 ns 3 t d(cko1h-beiv) delay time, clkout1 high to bex invalid 1.0 ns 4 t d(cko1h-eav) delay time, clkout1 high to eax valid 4.5 ns 5 t d(cko1h-eaiv) delay time, clkout1 high to eax invalid 1.0 ns 8 t d(cko1h-aoev) delay time, clkout1 high to aoe valid 1.0 4.5 ns 9 t d(cko1h-arev) delay time, clkout1 high to are valid 0.5 4.5 ns 12 t d(cko1h-edv) delay time, clkout1 high to edx valid 4.5 ns 13 t d(cko1h-ediv) delay time, clkout1 high to edx invalid 1.0 ns 14 t d(cko1h-awev) delay time, clkout1 high to awe valid 1.0 4.5 ns 3 the minimum delay is also the minimum output hold after clkout1 high.

sprs067e may 1998 revised may 2000 33 post office box 1443 ? houston, texas 772511443 asynchronous memory timing (continued) 11 11 10 10 9 9 8 8 7 6 5 4 3 2 1 1 clkout1 cex be[3:0] ea[21:2] ed[31:0] aoe are awe ardy setup = 2 strobe = 5 not ready = 2 hold = 1 figure 12. asynchronous memory read timing 11 10 11 10 14 14 13 12 5 4 3 2 1 1 clkout1 cex be[3:0] ea[21:2] ed[31:0] aoe are awe ardy setup = 2 strobe = 5 not ready = 2 hold = 1 figure 13. asynchronous memory write timing

sprs067e may 1998 revised may 2000 34 post office box 1443 ? houston, texas 772511443 synchronous-burst memory timing timing requirements for synchronous-burst sram cycles (full-rate ssclk) (see figure 14) no. 'c6701-120 'c6701-150 'c6701-167 unit no . min max min max unit 7 t su(edv-ssclkh) setup time, read edx valid before ssclk high 2.0 2.0 ns 8 t h(ssclkh-edv) hold time, read edx valid after ssclk high 2.9 2.1 ns switching characteristics for synchronous-burst sram cycles 2 (full-rate ssclk) (see figure 14 and figure 15) no. parameter 'c6701-120 'c6701-150 'c6701-167 unit no . parameter min max min max unit 1 t osu(cev-ssclkh) output setup time, cex valid before ssclk high 0.5p 1.3 0.5p 1.3 ns 2 t oh(ssclkh-cev) output hold time, cex valid after ssclk high 0.5p 2.9 0.5p 2.3 ns 3 t osu(bev-ssclkh) output setup time, bex valid before ssclk high 0.5p 1.3 0.5p 1.6 ns 4 t oh(ssclkh-beiv) output hold time, bex invalid after ssclk high 0.5p 2.9 0.5p 2.3 ns 5 t osu(eav-ssclkh) output setup time, eax valid before ssclk high 0.5p 1.3 0.5p 1.7 ns 6 t oh(ssclkh-eaiv) output hold time, eax invalid after ssclk high 0.5p 2.9 0.5p 2.3 ns 9 t osu(adsv-ssclkh) output setup time, ssads valid before ssclk high 0.5p 1.3 0.5p 1.3 ns 10 t oh(ssclkh-adsv) output hold time, ssads valid after ssclk high 0.5p 2.9 0.5p 2.3 ns 11 t osu(oev-ssclkh) output setup time, ssoe valid before ssclk high 0.5p 1.3 0.5p 1.3 ns 12 t oh(ssclkh-oev) output hold time, ssoe valid after ssclk high 0.5p 2.9 0.5p 2.3 ns 13 t osu(edv-ssclkh) output setup time, edx valid before ssclk high 0.5p 1.3 0.5p 1.3 ns 14 t oh(ssclkh-ediv) output hold time, edx invalid after ssclk high 0.5p 2.9 0.5p 2.3 ns 15 t osu(wev-ssclkh) output setup time, sswe valid before ssclk high 0.5p 1.3 0.5p 1.3 ns 16 t oh(ssclkh-wev) output hold time, sswe valid after ssclk high 0.5p 2.9 0.5p 2.3 ns 2 when the pll is used (clkmode x4), p = 1/cpu clock frequency in ns. for example, when running parts at 167 mhz, use p = 6 ns. for clkmode x1, 0.5p is defined as ph (pulse duration of clkin high) for all output setup times; 0.5p is defined as pl (pulse d uration of clkin low) for all output hold times.

sprs067e may 1998 revised may 2000 35 post office box 1443 ? houston, texas 772511443 synchronous-burst memory timing (continued) be1 be2 be3 be4 a1 a2 a3 a4 q1 q2 q3 q4 12 11 10 9 8 7 6 5 4 3 2 1 ssclk cex be[3:0] ea[21:2] ed[31:0] ssads ssoe sswe figure 14. sbsram read timing (full-rate ssclk) be1 be2 be3 be4 a1 a2 a3 a4 d1 d2 d3 d4 16 15 10 9 14 13 6 5 4 3 2 1 ssclk cex be[3:0] ea[21:2] ed[31:0] ssads ssoe sswe figure 15. sbsram write timing (full-rate ssclk)

sprs067e may 1998 revised may 2000 36 post office box 1443 ? houston, texas 772511443 synchronous-burst memory timing (continued) timing requirements for synchronous-burst sram cycles (half-rate ssclk) (see figure 16) no. 'c6701-120 'c6701-150 'c6701-167 unit min max 7 t su(edv-ssclkh) setup time, read edx valid before ssclk high 3.6 ns 8 t h(ssclkh-edv) hold time, read edx valid after ssclk high 1.5 ns switching characteristics for synchronous-burst sram cycles 2 (half-rate ssclk) (see figure 16 and figure 17) no. parameter 'c6701-120 'c6701-150 'c6701-167 unit no . parameter min max min max unit 1 t osu(cev-ssclkh) output setup time, cex valid before ssclk high 1.5p 4.5 1.5p 4.5 ns 2 t oh(ssclkh-cev) output hold time, cex valid after ssclk high 0.5p 2.5 0.5p 2 ns 3 t osu(bev-ssclkh) output setup time, bex valid before ssclk high 1.5p 4.5 1.5p 4.5 ns 4 t oh(ssclkh-beiv) output hold time, bex invalid after ssclk high 0.5p 2.5 0.5p 2 ns 5 t osu(eav-ssclkh) output setup time, eax valid before ssclk high 1.5p 4.5 1.5p 4.5 ns 6 t oh(ssclkh-eaiv) output hold time, eax invalid after ssclk high 0.5p 2.5 0.5p 2 ns 9 t osu(adsv-ssclkh) output setup time, ssads valid before ssclk high 1.5p 4.5 1.5p 4.5 ns 10 t oh(ssclkh-adsv) output hold time, ssads valid after ssclk high 0.5p 2.5 0.5p 2 ns 11 t osu(oev-ssclkh) output setup time, ssoe valid before ssclk high 1.5p 4.5 1.5p 4.5 ns 12 t oh(ssclkh-oev) output hold time, ssoe valid after ssclk high 0.5p 2.5 0.5p 2 ns 13 t osu(edv-ssclkh) output setup time, edx valid before ssclk high 1.5p 4.5 1.5p 4.5 ns 14 t oh(ssclkh-ediv) output hold time, edx invalid after ssclk high 0.5p 2.5 0.5p 2 ns 15 t osu(wev-ssclkh) output setup time, sswe valid before ssclk high 1.5p 4.5 1.5p 4.5 ns 16 t oh(ssclkh-wev) output hold time, sswe valid after ssclk high 0.5p 2.5 0.5p 2 ns 2 when the pll is used (clkmode x4), p = 1/cpu clock frequency in ns. for example, when running parts at 167 mhz, use p = 6 ns. for clkmode x1: 1.5p = p + ph, where p = 1/cpu clock frequency, and ph = pulse duration of clkin high. 0.5p = pl, where pl = pulse duration of clkin low.

sprs067e may 1998 revised may 2000 37 post office box 1443 ? houston, texas 772511443 synchronous-burst memory timing (continued) ssclk cex be[3:0] ea[21:2] ed[31:0] ssads ssoe sswe be1 be2 be3 be4 a1 a2 a3 a4 q1 q2 q3 q4 12 11 10 9 6 5 4 3 2 1 8 7 figure 16. sbsram read timing (1/2 rate ssclk) ssclk cex be[3:0] ea[21:2] ed[31:0] ssads ssoe sswe be1 be2 be3 be4 a1 a2 a3 a4 q1 q2 q3 q4 16 15 10 9 14 13 6 5 4 3 2 1 figure 17. sbsram write timing (1/2 rate ssclk)

sprs067e may 1998 revised may 2000 38 post office box 1443 ? houston, texas 772511443 synchronous dram timing timing requirements for synchronous dram cycles (see figure 18) no. 'c6701-120 'c6701-150 'c6701-167 unit min max 7 t su(edv-sdclkh) setup time, read edx valid before sdclk high 1.8 ns 8 t h(sdclkh-edv) hold time, read edx valid after sdclk high 3 ns switching characteristics for synchronous dram cycles 2 (see figure 18figure 23) no. parameter 'c6701-120 'c6701-150 'c6701-167 unit no . parameter min max min max unit 1 t osu(cev-sdclkh) output setup time, cex valid before sdclk high 1.5p 4 1.5p 4 ns 2 t oh(sdclkh-cev) output hold time, cex valid after sdclk high 0.5p 1.9 0.5p 1.5 ns 3 t osu(bev-sdclkh) output setup time, bex valid before sdclk high 1.5p 4 1.5p 4 ns 4 t oh(sdclkh-beiv) output hold time, bex invalid after sdclk high 0.5p 1.9 0.5p 1.5 ns 5 t osu(eav-sdclkh) output setup time, eax valid before sdclk high 1.5p 4 1.5p 4 ns 6 t oh(sdclkh-eaiv) output hold time, eax invalid after sdclk high 0.5p 1.9 0.5p 1.5 ns 9 t osu(sdcas-sdclkh) output setup time, sdcas valid before sdclk high 1.5p 4 1.5p 4 ns 10 t oh(sdclkh-sdcas) output hold time, sdcas valid after sdclk high 0.5p 1.9 0.5p 1.5 ns 11 t osu(edv-sdclkh) output setup time, edx valid before sdclk high 1.5p 4 1.5p 4 ns 12 t oh(sdclkh-ediv) output hold time, edx invalid after sdclk high 0.5p 1.9 0.5p 1.5 ns 13 t osu(sdwe-sdclkh) output setup time, sdwe valid before sdclk high 1.5p 4 1.5p 4 ns 14 t oh(sdclkh-sdwe) output hold time, sdwe valid after sdclk high 0.5p 1.9 0.5p 1.5 ns 15 t osu(sda10v-sdclkh) output setup time, sda10 valid before sdclk high 1.5p 4 1.5p 4 ns 16 t oh(sdclkh-sda10iv) output hold time, sda10 invalid after sdclk high 0.5p 1.9 0.5p 1.5 ns 17 t osu(sdras-sdclkh) output setup time, sdras valid before sdclk high 1.5p 4 1.5p 4 ns 18 t oh(sdclkh-sdras) output hold time, sdras valid after sdclk high 0.5p 1.9 0.5p 1.5 ns 2 when the pll is used (clkmode x4), p = 1/cpu clock frequency in ns. for example, when running parts at 167 mhz, use p = 6 ns. for clkmode x1: 1.5p = p + ph, where p = 1/cpu clock frequency, and ph = pulse duration of clkin high. 0.5p = pl, where pl = pulse duration of clkin low.

sprs067e may 1998 revised may 2000 39 post office box 1443 ? houston, texas 772511443 synchronous dram timing (continued) sdclk cex be[3:0] ea[15:2] ed[31:0] sda10 sdras sdcas sdwe be1 be2 be3 ca1 ca2 ca3 d1 d2 d3 10 9 16 15 6 5 4 3 2 1 8 7 read read read figure 18. three sdram read commands sdclk cex be[3:0] ea[15:2] ed[31:0] sda10 sdras sdcas sdwe be1 be2 be3 ca1 ca2 ca3 d1 d2 d3 14 13 10 9 16 15 12 11 6 5 4 3 2 1 write write write figure 19. three sdram write commands

sprs067e may 1998 revised may 2000 40 post office box 1443 ? houston, texas 772511443 synchronous dram timing (continued) sdclk cex be[3:0] ea[15:2] ed[31:0] sda10 sdras sdcas sdwe bank activate/row address row address 18 17 15 5 2 1 actv figure 20. sdram actv command sdclk cex be[3:0] ea[15:2] ed[31:0] sda10 sdras sdcas sdwe 14 18 16 2 15 1 17 13 dcab figure 21. sdram dcab command

sprs067e may 1998 revised may 2000 41 post office box 1443 ? houston, texas 772511443 synchronous dram timing (continued) sdclk cex be[3:0] ea[15:2] ed[31:0] sda10 sdras sdcas sdwe 10 9 18 17 2 1 refr figure 22. sdram refr command sdclk cex be[3:0] ea[15:2] ed[31:0] sda10 sdras sdcas sdwe mrs value 14 10 18 6 2 1 5 17 9 13 mrs figure 23. sdram mrs command

sprs067e may 1998 revised may 2000 42 post office box 1443 ? houston, texas 772511443 hold /holda timing timing requirements for the hold/hold acknowledge cycles 2 (see figure 24) no. 'c6701-120 'c6701-150 'c6701-167 unit min max 1 t su(holdh-cko1h) setup time, hold high before clkout1 high 5 ns 2 t h(cko1h-holdl) hold time, hold low after clkout1 high 2 ns 2 hold is synchronized internally. therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the next cycle. thus, hold can be an asynchronous input. switching characteristics for the hold/hold acknowledge cycles 3 (see figure 24) no. parameter 'c6701-120 'c6701-150 'c6701-167 unit min max 3 t r(holdl-emhz) response time, hold low to emif high impedance 4p ns 4 t r(emhz-holdal) response time, emif high impedance to holda low 2p ns 5 t r(holdh-holdah) response time, hold high to holda high 4p 7p ns 6 t d(cko1h-holdal) delay time, clkout1 high to holda valid 1 8 ns 7 t d(cko1h-bhz) delay time, clkout1 high to emif bus high impedance ? 1 8 ns 8 t d(cko1h-blz) delay time, clkout1 high to emif bus low impedance ? 1 12 ns 9 t r(holdh-blz) response time, hold high to emif bus low impedance ? 3p 6p ns 3 p = 1/cpu clock frequency in ns. for example, when running parts at 167 mhz, use p = 6 ns. all pending emif transactions are allowed to complete before holda is asserted. the worst cases for this is an asynchronous read or write with external ardy used or a minimum of eight consecutive sdram reads or writes when rbtr8 = 1. if no bus transactions are occurring , then the minimum delay time can be achieved. also, bus hold can be indefinitely delayed by setting the nohold = 1. ? emif bus consists of ce[3:0] , be[3:0] , ed[31:0], ea[21:2], are , aoe , awe , ssads , ssoe , sswe , sda10, sdras , sdcas , and sdwe . dsp owns bus external requester dsp owns bus 'c6701 ext req 'c6701 8 7 3 4 6 6 1 2 clkout1 hold holda emif bus 2 1 5 9 2 2 emif bus consists of ce[3:0] , be[3:0] , ed[31:0], ea[21:2], are , aoe , awe , ssads , ssoe , sswe , sda10, sdras , sdcas , and sdwe . figure 24. hold /holda timing

sprs067e may 1998 revised may 2000 43 post office box 1443 ? houston, texas 772511443 reset timing timing requirements for reset (see figure 25) no. 'c6701-120 'c6701-150 'c6701-167 unit min max 1 t w(reset) width of the reset pulse (pll stable) 2 10 clkout1 cycles 1 t w(reset) width of the reset pulse (pll needs to sync up) 3 250 m s 2 this parameter applies to clkmode x1 when clkin is stable and applies to clkmode x4 when clkin and pll are stable. 3 this parameter only applies to clkmode x4. the reset signal is not connected internally to the clock pll circuit. the pll, however, may need up to 250 m s to stabilize following device powerup or after pll configuration has been changed. during that time, reset must be asserted to ensure proper device operation. see the clock pll section for pll lock times. switching characteristics during reset ? (see figure 25) no. parameter 'c6701-120 'c6701-150 'c6701-167 unit min max 2 t r(reset) response time to change of value in reset signal 1 clkout1 cycles 3 t d(cko1h-cko2iv) delay time, clkout1 high to clkout2 invalid 1 ns 4 t d(cko1h-cko2v) delay time, clkout1 high to clkout2 valid 10 ns 5 t d(cko1h-sdclkiv) delay time, clkout1 high to sdclk invalid 1 ns 6 t d(cko1h-sdclkv) delay time, clkout1 high to sdclk valid 10 ns 7 t d(cko1h-ssckiv) delay time, clkout1 high to ssclk invalid 1 ns 8 t d(cko1h-ssckv) delay time, clkout1 high to ssclk valid 10 ns 9 t d(cko1h-lowiv) delay time, clkout1 high to low group invalid 1 ns 10 t d(cko1h-lowv) delay time, clkout1 high to low group valid 10 ns 11 t d(cko1h-highiv) delay time, clkout1 high to high group invalid 1 ns 12 t d(cko1h-highv) delay time, clkout1 high to high group valid 10 ns 13 t d(cko1h-zhz) delay time, clkout1 high to z group high impedance 1 ns 14 t d(cko1h-zv) delay time, clkout1 high to z group valid 10 ns low group consists of: iack, inum[3:0], dmac[3:0], pd, tout0, and tout1. high group consists of: hint . z group consists of: ea[21:2], ed[31:0], ce[3:0] , be[3:0] , are , awe , aoe , ssads , ssoe , sswe , sda10, sdras , sdcas , sdwe , hd[15:0], clkx0, clkx1, fsx0, fsx1, dx0, dx1, clkr0, clkr1, fsr0, and fsr1. ? hrdy is gated by input hcs . if hcs = 0 at device reset, hrdy belongs to the high group. if hcs = 1 at device reset, hrdy belongs to the low group.

sprs067e may 1998 revised may 2000 44 post office box 1443 ? houston, texas 772511443 reset timing (continued) 1 2 2 14 13 12 11 10 9 8 7 6 5 4 3 clkout1 reset clkout2 sdclk ssclk low group 23 high group 23 z group 23 2 low group consists of: iack, inum[3:0], dmac[3:0], pd, tout0, and tout1. high group consists of: hint . z group consists of: ea[21:2], ed[31:0], ce[3:0] , be[3:0] , are , awe , aoe , ssads , ssoe , sswe , sda10, sdras , sdcas , sdwe , hd[15:0], clkx0, clkx1, fsx0, fsx1, dx0, dx1, clkr0, clkr1, fsr0, and fsr1. 3 hrdy is gated by input hcs . if hcs = 0 at device reset, hrdy belongs to the high group. if hcs = 1 at device reset, hrdy belongs to the low group. figure 25. reset timing

sprs067e may 1998 revised may 2000 45 post office box 1443 ? houston, texas 772511443 external interrupt timing timing requirements for interrupt response cycles 23 (see figure 26) no. 'c6701-120 'c6701-150 'c6701-167 unit min max 2 t w(ilow) width of the interrupt pulse low 2p ns 3 t w(ihigh) width of the interrupt pulse high 2p ns 2 interrupt signals are synchronized internally and are potentially recognized one cycle later if setup and hold times are violat ed. thus, they can be connected to asynchronous inputs. 3 p = 1/cpu clock frequency in ns. for example, when running parts at 167 mhz, use p = 6 ns. switching characteristics during interrupt response cycles (see figure 26) no. parameter 'c6701-120 'c6701-150 'c6701-167 unit min max 1 t r(einth-iackh) response time, ext_intx high to iack high 9p ns 4 t d(cko2l-iackv) delay time, clkout2 low to iack valid 0.5p 13 0.5p ns 5 t d(cko2l-inumv) delay time, clkout2 low to inumx valid 10 0.5p ns 6 t d(cko2l-inumiv) delay time, clkout2 low to inumx invalid 0.5p ns p = 1/cpu clock frequency in ns. for example, when running parts at 167 mhz, use p = 6 ns. when the pll is used (clkmode x4), 0.5p = 1/(2 cpu clock frequency). for clkmode x1: 0.5p = ph, where ph is the high period of clkin. interrupt number 6 5 4 4 3 2 clkout2 ext_intx, nmi 1 intr flag iack inumx figure 26. interrupt timing

sprs067e may 1998 revised may 2000 46 post office box 1443 ? houston, texas 772511443 host-port interface timing timing requirements for host-port interface cycles 23 (see figure 27, figure 28, figure 29, and figure 30) no. 'c6701-120 'c6701-150 'c6701-167 unit min max 1 t su(sel-hstbl) setup time, select signals valid before hstrobe low 4 ns 2 t h(hstbl-sel) hold time, select signals valid after hstrobe low 2 ns 3 t w(hstbl) pulse duration, hstrobe low 2p ns 4 t w(hstbh) pulse duration, hstrobe high between consecutive accesses 2p ns 10 t su(sel-hasl) setup time, select signals valid before has low 4 ns 11 t h(hasl-sel) hold time, select signals valid after has low 2 ns 12 t su(hdv-hstbh) setup time, host data valid before hstrobe high 3 ns 13 t h(hstbh-hdv) hold time, host data valid after hstrobe high 2 ns 14 t h(hrdyl-hstbl) hold time, hstrobe low after hrdy low. hstrobe should not be inacti- vated until hrdy is active (low); otherwise, hpi writes will not complete properly. 1 ns 18 t su(hasl-hstbl) setup time, has low before hstrobe low 2 ns 19 t h(hstbl-hasl) hold time, has low after hstrobe low 2 ns 2 hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . 3 p = 1/cpu clock frequency in ns. for example, when running parts at 167 mhz, use p = 6 ns. select signals include: hcntrl[1:0], hr/w , and hhwil. switching characteristics during host-port interface cycles 23 (see figure 27, figure 28, figure 29, and figure 30) no. parameter 'c6701-120 'c6701-150 'c6701-167 unit min max 5 t d(hcs-hrdy) delay time, hcs to hrdy ? 1 12 ns 6 t d(hstbl-hrdyh) delay time, hstrobe low to hrdy high # 1 12 ns 7 t d(hstbl-hdlz) delay time, hstrobe low to hd low impedance for an hpi read 4 ns 8 t d(hdv-hrdyl) delay time, hd valid to hrdy low p 3 p + 3 ns 9 t oh(hstbh-hdv) output hold time, hd valid after hstrobe high 3 12 ns 15 t d(hstbh-hdhz) delay time, hstrobe high to hd high impedance 3 12 ns 16 t d(hstbl-hdv) delay time, hstrobe low to hd valid 3 12 ns 17 t d(hstbh-hrdyh) delay time, hstrobe high to hrdy high || 1 12 ns 20 t d(hasl-hrdyh) delay time, has low to hrdy high 3 12 ns 2 hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . 3 p = 1/cpu clock frequency in ns. for example, when running parts at 167 mhz, use p = 6 ns. ? hcs enables hrdy , and hrdy is always low when hcs is high. the case where hrdy goes high when hcs falls indicates that hpi is busy completing a previous hpid write or read with autoincrement. # this parameter is used during an hpid read. at the beginning of the first half-word transfer on the falling edge of hstrobe , the hpi sends the request to the dma auxiliary channel, and hrdy remains high until the dma auxiliary channel loads the requested data into hpid. || this parameter is used after the second half-word of an hpid write or autoincrement read. hrdy remains low if the access is not an hpid write or autoincrement read. reading or writing to hpic or hpia does not affect the hrdy signal.

sprs067e may 1998 revised may 2000 47 post office box 1443 ? houston, texas 772511443 host-port interface timing (continued) 1st half-word 2nd half-word 5 17 8 6 5 17 8 5 15 9 16 15 9 7 4 3 2 1 2 1 2 1 2 1 2 1 2 1 has hcntl[1:0] hr/w hhwil hstrobe 2 hcs hd[15:0] (output) hrdy (case 1) hrdy (case 2) 2 hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . figure 27. hpi read timing (has not used, tied high) has hcntl[1:0] hr/w hhwil hstrobe 2 hcs hd[15:0] (output) hrdy (case 1) hrdy (case 2) 1st half-word 2nd half-word 5 17 8 20 5 17 8 5 15 9 16 15 9 7 4 3 11 10 11 10 11 10 11 10 11 10 11 10 19 19 18 18 2 hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . figure 28. hpi read timing (has used)

sprs067e may 1998 revised may 2000 48 post office box 1443 ? houston, texas 772511443 host-port interface timing (continued) 1st half-word 2nd half-word 5 17 5 13 12 13 12 4 14 3 2 1 2 1 2 1 2 1 13 12 13 12 2 1 2 1 has hcntl[1:0] hr/w hhwil hstrobe 2 hcs hd[15:0] (input) hrdy hbe[1:0] 2 hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . figure 29. hpi write timing (has not used, tied high) 1st half-word 2nd half-word 5 17 5 13 12 13 12 4 14 3 11 10 11 10 11 10 11 10 11 10 11 10 13 12 13 12 has hcntl[1:0] hr/w hhwil hstrobe 2 hcs hd[15:0] (input) hrdy hbe[1:0] 19 19 18 18 2 hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . figure 30. hpi write timing (has used)

sprs067e may 1998 revised may 2000 49 post office box 1443 ? houston, texas 772511443 multichannel buffered serial port timing timing requirements for mcbsp 23 (see figure 31) no. 'c6701-120 'c6701-150 'c6701-167 unit min max 2 t c(ckrx) cycle time, clkr/x clkr/x ext 2p ns 3 t w(ckrx) pulse duration, clkr/x high or clkr/x low clkr/x ext p 1 ? ns 5 t setup time external fsr high before clkr low clkr int 13 ns 5 t su(frh-ckrl) setup time, external fsr high before clkr low clkr ext 4 ns 6 t hold time external fsr high after clkr low clkr int 7 ns 6 t h(ckrl-frh) hold time, external fsr high after clkr low clkr ext 4 ns 7 t setup time dr valid before clkr low clkr int 10 ns 7 t su(drv-ckrl) setup time, dr valid before clkr low clkr ext 1 ns 8 t hold time dr valid after clkr low clkr int 4 ns 8 t h(ckrl-drv) hold time, dr valid after clkr low clkr ext 4 ns 10 t setup time external fsx high before clkx low clkx int 13 ns 10 t su(fxh-ckxl) setup time, external fsx high before clkx low clkx ext 4 ns 11 t hold time external fsx high after clkx low clkx int 7 ns 11 t h(ckxl-fxh) hold time, external fsx high after clkx low clkx ext 3 ns 2 p = 1/cpu clock frequency in ns. for example, when running parts at 167 mhz, use p = 6 ns. 3 clkrp = clkxp = fsrp = fsxp = 0. if polarity of any of the signals is inverted, then the timing references of that signal are a lso inverted. the maximum mcbsp bit rate is 50 mhz; therefore, the minimum clkr/x clock cycle is either twice the cpu cycle time (2p), or 20 ns (50 mhz), whichever value is larger. for example, when running parts at 167 mhz (p = 6 ns), use 20 ns as the minimum clkr/x clock cycle ( by setting the appropriate clkgdv ratio or external clock source). when running parts at 80 mhz (p = 12.5 ns), use 2p = 25 ns (40 mhz) as the minimum clkr/x clock cycle. the maximum mcbsp bit rate applies when the serial port is a master of clock and frame syncs and the other device the mcbsp communicates to is a slave. ? the minimum clkr/x pulse duration is either (p1) or 9 ns, whichever is larger. for example, when running parts at 167 mhz (p = 6 ns), use 9 ns as the minimum clkr/x pulse duration. when running parts at 80 mhz (p = 12.5 ns), use (p1) = 11.5 ns as the minimum clkr/ x pulse duration.

sprs067e may 1998 revised may 2000 50 post office box 1443 ? houston, texas 772511443 multichannel buffered serial port timing (continued) switching characteristics for mcbsp 23 (see figure 31) no. parameter 'c6701-120 'c6701-150 'c6701-167 unit min max 1 t d(cksh-ckrxh) delay time, clks high to clkr/x high for internal clkr/x generated from clks input 3 15 ns 2 t c(ckrx) cycle time, clkr/x clkr/x int 2p ? ns 3 t w(ckrx) pulse duration, clkr/x high or clkr/x low clkr/x int c 1 # c + 1 # ns 4 t d(ckrh-frv) delay time, clkr high to internal fsr valid clkr int 4 4 ns 9 t delay time clkx high to internal fsx valid clkx int 4 5 ns 9 t d(ckxh-fxv) delay time, clkx high to internal fsx valid clkx ext 3 16 ns 12 t disable time, dx hi g h impedance followin g last data bit from clkx int 3 2 ns 12 t dis(ckxh-dxhz) disable time , dx high im edance following last data bit from clkx high clkx ext 2 9 ns 13 t delay time clkx high to dx valid clkx int 2 4 ns 13 t d(ckxh-dxv) delay time, clkx high to dx valid. clkx ext 3 16 ns 14 t dela y time, fsx hi g h to dx valid. fsx int 2 4 ns 14 t d(fxh-dxv) delay time , fsx high to dx valid . only applies when in data delay 0 (xdatdly = 00b) mode. fsx ext 2 10 ns 2 clkrp = clkxp = fsrp = fsxp = 0. if polarity of any of the signals is inverted, then the timing references of that signal are a lso inverted. 3 minimum delay times also represent minimum output hold times. p = 1/cpu clock frequency in ns. for example, when running parts at 167 mhz, use p = 6 ns. ? the maximum mcbsp bit rate is 50 mhz; therefore, the minimum clkr/x clock cycle is either twice the cpu cycle time (2p), or 20 ns (50 mhz), whichever value is larger. for example, when running parts at 167 mhz (p = 6 ns), use 20 ns as the minimum clkr/x clock cycle ( by setting the appropriate clkgdv ratio or external clock source). when running parts at 80 mhz (p = 12.5 ns), use 2p = 25 ns (40 mhz) as the minimum clkr/x clock cycle. the maximum mcbsp bit rate applies when the serial port is a master of clock and frame syncs and the other device the mcbsp communicates to is a slave. # c = h or l s = sample rate generator input clock = p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero clkgdv should be set appropriately to ensure the mcbsp bit rate does not exceed the 50 mhz limit.

sprs067e may 1998 revised may 2000 51 post office box 1443 ? houston, texas 772511443 multichannel buffered serial port timing (continued) bit(n-1) (n-2) (n-3) bit 0 bit(n-1) (n-2) (n-3) 14 13 12 11 10 9 3 3 2 8 7 6 5 4 4 3 1 3 2 clks clkr fsr (int) fsr (ext) dr clkx fsx (int) fsx (ext) fsx (xdatdly=00b) dx 13 figure 31. mcbsp timings

sprs067e may 1998 revised may 2000 52 post office box 1443 ? houston, texas 772511443 multichannel buffered serial port timing (continued) timing requirements for fsr when gsync = 1 (see figure 32) no. 'c6701-120 'c6701-150 'c6701-167 unit min max 1 t su(frh-cksh) setup time, fsr high before clks high 4 ns 2 t h(cksh-frh) hold time, fsr high after clks high 4 ns 2 1 clks fsr external clkr/x (no need to resync) clkr/x(needs resync) figure 32. fsr timing when gsync = 1

sprs067e may 1998 revised may 2000 53 post office box 1443 ? houston, texas 772511443 multichannel buffered serial port timing (continued) timing requirements for mcbsp as spi master or slave: clkstp = 10b, clkxp = 0 23 (see figure 33) no. 'c6701-120 'c6701-150 'c6701-167 unit no . master slave unit min max min max 4 t su(drv-ckxl) setup time, dr valid before clkx low 12 2 3p ns 5 t h(ckxl-drv) hold time, dr valid after clkx low 4 5 + 6p ns 2 p = 1/cpu clock frequency in ns. for example, when running parts at 167 mhz, use p = 6 ns. 3 for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. switching characteristics for mcbsp as spi master or slave: clkstp = 10b, clkxp = 0 23 (see figure 33) no. parameter 'c6701-120 'c6701-150 'c6701-167 unit no . parameter master slave unit min max min max 1 t h(ckxl-fxl) hold time, fsx low after clkx low ? t 4 t + 4 ns 2 t d(fxl-ckxh) delay time, fsx low to clkx high # l 4 l + 4 ns 3 t d(ckxh-dxv) delay time, clkx high to dx valid 4 4 3p + 1 5p + 17 ns 6 t dis(ckxl-dxhz) disable time, dx high impedance following last data bit from clkx low l 2 l + 3 ns 7 t dis(fxh-dxhz) disable time, dx high impedance following last data bit from fsx high p + 4 3p + 17 ns 8 t d(fxl-dxv) delay time, fsx low to dx valid 2p + 1 4p + 13 ns 2 p = 1/cpu clock frequency in ns. for example, when running parts at 167 mhz, use p = 6 ns. 3 for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. s = sample rate generator input clock = p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx).

sprs067e may 1998 revised may 2000 54 post office box 1443 ? houston, texas 772511443 multichannel buffered serial port timing (continued) bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 7 6 2 1 clkx fsx dx dr figure 33. mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 0

sprs067e may 1998 revised may 2000 55 post office box 1443 ? houston, texas 772511443 multichannel buffered serial port timing (continued) timing requirements for mcbsp as spi master or slave: clkstp = 11b, clkxp = 0 23 (see figure 34) no. 'c6701-120 'c6701-150 'c6701-167 unit no . master slave unit min max min max 4 t su(drv-ckxh) setup time, dr valid before clkx high 12 2 3p ns 5 t h(ckxh-drv) hold time, dr valid after clkx high 4 5 + 6p ns 2 p = 1/cpu clock frequency in ns. for example, when running parts at 167 mhz, use p = 6 ns. 3 for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. switching characteristics for mcbsp as spi master or slave: clkstp = 11b, clkxp = 0 23 (see figure 34) no. parameter 'c6701-120 'c6701-150 'c6701-167 unit no . parameter master slave unit min max min max 1 t h(ckxl-fxl) hold time, fsx low after clkx low ? l 4 l + 4 ns 2 t d(fxl-ckxh) delay time, fsx low to clkx high # t 4 t + 4 ns 3 t d(ckxl-dxv) delay time, clkx low to dx valid 4 4 3p + 1 5p + 17 ns 6 t dis(ckxl-dxhz) disable time, dx high impedance following last data bit from clkx low 2 4 3p + 4 5p + 17 ns 7 t d(fxl-dxv) delay time, fsx low to dx valid h 2 h + 3 2p + 1 4p + 13 ns 2 p = 1/cpu clock frequency in ns. for example, when running parts at 167 mhz, use p = 6 ns. 3 for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. s = sample rate generator input clock = p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx). bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 4 3 7 6 2 1 clkx fsx dx dr 5 figure 34. mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 0

sprs067e may 1998 revised may 2000 56 post office box 1443 ? houston, texas 772511443 multichannel buffered serial port timing (continued) timing requirements for mcbsp as spi master or slave: clkstp = 10b, clkxp = 1 23 (see figure 35) no. 'c6701-120 'c6701-150 'c6701-167 unit no . master slave unit min max min max 4 t su(drv-ckxh) setup time, dr valid before clkx high 12 2 3p ns 5 t h(ckxh-drv) hold time, dr valid after clkx high 4 5 + 6p ns 2 p = 1/cpu clock frequency in ns. for example, when running parts at 167 mhz, use p = 6 ns. 3 for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. switching characteristics for mcbsp as spi master or slave: clkstp = 10b, clkxp = 1 23 (see figure 35) no. parameter 'c6701-120 'c6701-150 'c6701-167 unit no . parameter master slave unit min max min max 1 t h(ckxh-fxl) hold time, fsx low after clkx high ? t 4 t + 4 ns 2 t d(fxl-ckxl) delay time, fsx low to clkx low # h 4 h + 4 ns 3 t d(ckxl-dxv) delay time, clkx low to dx valid 4 4 3p + 1 5p + 17 ns 6 t dis(ckxh-dxhz) disable time, dx high impedance following last data bit from clkx high h 2 h + 3 ns 7 t dis(fxh-dxhz) disable time, dx high impedance following last data bit from fsx high p + 4 3p + 17 ns 8 t d(fxl-dxv) delay time, fsx low to dx valid 2p + 1 4p + 13 ns 2 p = 1/cpu clock frequency in ns. for example, when running parts at 167 mhz, use p = 6 ns. 3 for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. s = sample rate generator input clock = p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx).

sprs067e may 1998 revised may 2000 57 post office box 1443 ? houston, texas 772511443 multichannel buffered serial port timing (continued) bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 7 6 2 1 clkx fsx dx dr figure 35. mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 1

sprs067e may 1998 revised may 2000 58 post office box 1443 ? houston, texas 772511443 multichannel buffered serial port timing (continued) timing requirements for mcbsp as spi master or slave: clkstp = 11b, clkxp = 1 23 (see figure 36) no. 'c6701-120 'c6701-150 'c6701-167 unit no . master slave unit min max min max 4 t su(drv-ckxl) setup time, dr valid before clkx low 12 2 3p ns 5 t h(ckxl-drv) hold time, dr valid after clkx low 4 5 + 6p ns 2 p = 1/cpu clock frequency in ns. for example, when running parts at 167 mhz, use p = 6 ns. 3 for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. switching characteristics for mcbsp as spi master or slave: clkstp = 11b, clkxp = 1 23 (see figure 36) no. parameter 'c6701-120 'c6701-150 'c6701-167 unit no . parameter master slave unit min max min max 1 t h(ckxh-fxl) hold time, fsx low after clkx high ? h 4 h + 4 ns 2 t d(fxl-ckxl) delay time, fsx low to clkx low # t 4 t + 4 ns 3 t d(ckxh-dxv) delay time, clkx high to dx valid 4 4 3p + 1 5p + 17 ns 6 t dis(ckxh-dxhz) disable time, dx high impedance following last data bit from clkx high 2 4 3p + 4 5p + 17 ns 7 t d(fxl-dxv) delay time, fsx low to dx valid l 2 l + 3 2p + 1 4p + 13 ns 2 p = 1/cpu clock frequency in ns. for example, when running parts at 167 mhz, use p = 6 ns. 3 for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. s = sample rate generator input clock = p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx).

sprs067e may 1998 revised may 2000 59 post office box 1443 ? houston, texas 772511443 multichannel buffered serial port timing (continued) bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 7 6 2 1 clkx fsx dx dr figure 36. mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 1

sprs067e may 1998 revised may 2000 60 post office box 1443 ? houston, texas 772511443 dmac, timer, power-down timing switching characteristics for dmac outputs (see figure 37) no. parameter 'c6701-120 'c6701-150 'c6701-167 unit min max 1 t d(cko1h-dmacv) delay time, clkout1 high to dmac valid 2 11 ns 1 1 clkout1 dmac[0:3] figure 37. dmac timing timing requirements for timer inputs (see figure 38) 2 no. 'c6701-120 'c6701-150 'c6701-167 unit min max 1 t w(tinph) pulse duration, tinp high 2p ns 2 p = 1/cpu clock frequency in ns. for example, when running parts at 167 mhz, use p = 6 ns. switching characteristics for timer outputs (see figure 38) no. parameter 'c6701-120 'c6701-150 'c6701-167 unit min max 2 t d(cko1h-toutv) delay time, clkout1 high to tout valid 1 10 ns 2 1 clkout1 tinp tout 2 figure 38. timer timing

sprs067e may 1998 revised may 2000 61 post office box 1443 ? houston, texas 772511443 dmac, timer, power-down timing (continued) switching characteristics for power-down outputs (see figure 39) no. parameter 'c6701-120 'c6701-150 'c6701-167 unit min max 1 t d(cko1h-pdv) delay time, clkout1 high to pd valid 1 9 ns 1 1 clkout1 pd figure 39. power-down timing

sprs067e may 1998 revised may 2000 62 post office box 1443 ? houston, texas 772511443 jtag test-port timing timing requirements for jtag test port (see figure 40) no. 'c6701-120 'c6701-150 'c6701-167 unit min max 1 t c(tck) cycle time, tck 35 ns 3 t su(tdiv-tckh) setup time, tdi/tms/trst valid before tck high 10 ns 4 t h(tckh-tdiv) hold time, tdi/tms/trst valid after tck high 9 ns switching characteristics for jtag test port (see figure 40) no. parameter 'c6701-120 'c6701-150 'c6701-167 unit min max 2 t d(tckl-tdov) delay time, tck low to tdo valid 3 12 ns tck tdo tdi/tms/trst 1 2 3 4 2 figure 40. jtag test-port timing

sprs067e may 1998 revised may 2000 63 post office box 1443 ? houston, texas 772511443 mechanical data gjc (s-pbga-n352) plastic ball grid array 31,75 typ 0,635 af ad ab ac y v w aa ae r t n p l m j k g e f b c a d h u 25 26 22 23 20 19 21 17 15 16 12 13 14 18 10 9 8 7 5 6 3 4 2 1 seating plane 11 4173506-2/d 07/99 24 sq 35,20 34,80 sq 33,20 32,80 21,00 nom see note e heat slug 0,90 0,60 1,00 nom 0,50 min 3,50 max 0,635 21,00 nom 1,27 0,15 1,27 m ? 0,10 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. thermally enhanced plastic package with heat slug (hsl). d. flip chip application only e. possible protrusion in this area, but within 3,50 max package height specification f. falls within jedec mo-151/bar-2 thermal resistance characteristics (s-pbga package) no c/w air flow lfpm 2 1 r q jc junction-to-case 0.74 n/a 2 r q ja junction-to-free air 11.31 0 3 r q ja junction-to-free air 9.60 100 4 r q ja junction-to-free air 8.34 250 5 r q ja junction-to-free air 7.30 500 2 lfpm = linear feet per minute
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. customers are responsible for their applications using ti components. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 2000, texas instruments incorporated

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