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?1 cxp82940/82948/82952/82960 e95130-pk cmos 8-bit single chip microcomputer description the cxp82940/82948/82952/82960 is a cmos 8-bit single chip microcomputer integrating on a single chip an a/d converter, serial interface, timer/counter, time base timer, fluorescent display panel controller/driver, i 2 c bus interface, remote control transmission circuit, remote control reception circuit, and 32khz timer/counter besides the basic configurations of 8-bit cpu, rom, ram, and i/o port. features1 wide-range instruction system (213 instructions) to cover various types of data ?16-bit arithmetic/multiplication and division/boolean bit operation instructions minimum instruction cycle 250ns at 16mhz operation (122s at 32khz operation) incorporated rom capacity 40k bytes (cxp82940) 48k bytes (cxp82948) 52k bytes (cxp82952) 60k bytes (CXP82960) incorporated ram capacity 2048 bytes (including fluorescent display area) periphera; functions ?a/d converter 8-bit, 8-channel, successive approximation method (conversion time of 20s/16mhz) serial interface buffer ram incorporated (auto transfer for 1 to 32 bytes), 1 channel 8-bit, 8-stage fifo incorporated (auto transfer for 1 to 8 bytes), 1 channel ?timers 8-bit timer, 8-bit timer/counter, 19-bit time base timer 32khz timer/counter ? fluorescent display panel controller/driver maximum of 196 segments display possible 1 to 16-digit dynamic display dimmer function high voltage drive output (40v) incorporated pull-down resistor (mask option) hardware key scan function maximum of 12 8 key matrix supportable ?i 2 c bus interface ?remote control transmission circuit auto transmission for 1 to 32 bytes, restart function, carrier output function ?remote control reception circuit 8-bit pulse measurement counter, 6-stage fifo interruption 16 factors, 15 vectors, multi-interruption possible standby mode sleep/stop package 80-pin plastic qfp piggyback/evaluation chip cxp82900 80-pin ceramic qfp perchase of sony? i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specifications as defined by philips. sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 80 pin qfp (plastic) structure silicon gate cmos ic
?2 cxp82940/82948/82952/82960 ram 2048 bytes spc 700 cpu core interrupt controller a/d converter serial interface unit (ch0) serial interface unit (ch1) 8 bit timer/counter 0 8 bit timer 1 i 2 c bus interface unit int3/nmi int1 int0 int2 an0 to an7 8 pa0 to pa7 buffer ram remocon in fdp controller/ driver 32khz timer/counter prescaler/ time base timer rst v dd v ss port a port b port c port d port e port f port g 8 8 6 2 4 4 8 8 pb0 to pb7 pc0 to pc7 pd0 to pd7 pe0 to pe5 pf0 to pf3 pg0 to pg3 pe6 to pe7 tex extal xtal tx av ref av ss t0 to t7 t8/s19 to t15/s12 s0 to s11 v fdp kr0 to kr7 rmco rmc cs0 si0 so0 sck0 si1 so1 sck1 ec scl0 scl1 sda0 2 8 8 rom 40k/48k/52k/60k bytes 12 8 ram ram key scan 2 clock generator system control buffer ram remocon out sda1 av dd fifo fifo adj to 2 block diagram
?3 cxp82940/82948/82952/82960 pin assignment (top view) pe0/ec/int0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 75 76 77 78 79 80 1 t0 t1 t2 t3 t4 t5 t6 pb5/sck1 pb3/si0 pb4/so0 pb6/si1 pb7/so1 pa7/an7 pa0/an0 pa1/an1 pa2/an2 pa3/an3 pa4/an4 pa5/an5 pa6/an6 t7 t10/s17 t11/s16 t12/s15 t13/s14 t14/s13 t15/s12 s11 s10 s9 s8 pd7/s7 pd6/s6 t8/s19 t9/s18 pc6/kr6 pc7/kr7 pd5/s5 pd4/s4 pd3/s3 pd2/s2 pd1/s1 pd0/s0 v fdp nc tex tx v dd pg3 pg2 pg1 pg0 pe1/int1 pe2/int2 pe3/int3/nmi pe4/rmc pe5 pe6/rmco pe7/to/adj pb0 pb1/cs0 pb2/sck0 av dd pc0/kr0 pc1/kr1 pc2/kr2 pc3/kr3 pc4/kr4 pc5/kr5 av ref v ss av ss pf0/scl0 pf1/scl1 pf2/sda0 pf3/sda1 extal xtal rst note) nc (pin 75) must be connected to v dd .
?4 cxp82940/82948/82952/82960 pin description pin code i/o functions i/o/ analog input pa0/an0 to pa7/an7 analog inputs to a/d converter. (8 pins) i/o/input pc0/kr0 to pc7/kr7 pe0/int0/ec pe1/int1 pe2/int2 pe3/int3/ nmi pe4/rmc pe5 pe6/rmco pe7/to/adj pf0/scl0 pf1/scl1 pf2/sda0 pf3/sda1 input/input/input input/input input/input input/input/input input/input input output/output output/output/ output output/i/o output/i/o serves as key return inputs when operating key scan with fluorescent display panel (fdp) segment signal (8 pins). (port e) 8-bit port. lower 6 bits are for inputs; upper 2 bits are for outputs. (8 pins) (port f) 4-bit output port, operating as n-ch open drain output for large current (12ma). (4 pins) external event inputs for timer/counter. inputs for external interruption request. (4 pins) non-maskable interruption request input. remote control reception circuit input. carrier output of remote control transmission circuit. output for the timer/counter rectangular waves, and 32khz oscillation dividing frequency. transfer clock i/os for i 2 c bus interface. transfer data i/os for i 2 c bus interface. i/o i/o/input i/o/i/o i/o/input i/o/output i/o/i/o i/o/input i/o/output pb0 pb1/cs0 pb2/sck0 pb3/si0 pb4/so0 pb5/sck1 pb6/si1 pb7/so1 (port b) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) chip select input for serial interface (ch0). serial clock i/o (ch0). serial data input (ch0). serial data output (ch0). serial clock i/o (ch1). serial data input (ch1). serial data output (ch1). (port a) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) (port c) 8-bit i/o port. i/o can be set in a unit of single bits. capable of driving 12ma sync current. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins)
?5 cxp82940/82948/82952/82960 pin code i/o functions output/output pd0/s0 to pd7/s7 (port d) 8-bit output ports. (8 pins) fdp segment signal outputs. (8 pins) output s8 to s11 fdp segment signal outputs. (4 pins) output/output t8/s12 to t15/s19 outputs for fdp timing signals/segment signals. (8 pins) i/o pg0 to pg3 (port g) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (4 pins) v fdp extal xtal tex tx rst nc av ref av ss v dd v ss input output input output input input fdp voltage supply when incorporated resistor is set by mask option. t0 to t7 fdp timing signal outputs. crystal connectors for system clock oscillation. when the clock is supplied externally, input to extal; opposite phase clock should be input to xtal. crystal connectors for 32khz timer/counter clock oscillation. set 32khz crystal oscillator between tex and tx. for usage as event input, attach clock source to tex, and open tx. low-level active, system reset. nc. under normal operation, connect to v dd . av dd positive power supply for a/d converter. reference voltage input for a/d converter. a/d converter gnd. positive power supply. gnd. output
?6 cxp82940/82948/82952/82960 port b data bus rd (port b) aaaa aa port b direction ip aa aa aaaa aaaa port b data aaaa aaaa pull-up resistor "0" when reset "0" when reset * pull-up transistor approx. 100k w * schmitt input cs0 si0 si1 not schmitt input for si0 and si1. 8 pins hi-z hi-z when reset pa0/an0 to pa7/an7 pb1/cs0 pb3/si0 pb6/si1 port b data bus rd (port b) aa ip aa aa aaaa port b output selection "0" when reset * pull-up transistor approx. 100k w * schmitt input sck in aaaa aaaa port b data aaaa aaaa port b direction "0" when reset aaaa aaaa pull-up resistor "0" when reset sck out output enable 3 pins 2 pins hi-z pb2/sck0 pb5/sck1 data bus rd (port a) aaaa aa port a direction ip aa aa aaaa aaaa port a data aaaa aaaa pull-up resistor aaaa a aa a aaaa port a input selection input protection circuit "0" when reset "0" when reset "0" when reset input multiplexer a/d converter * pull-up transistor approx. 100k w * port a pin circuit format i/o circuit format for pins
?7 cxp82940/82948/82952/82960 2 pins hi-z hi-z pb4/so0 pb7/so1 pc0/kr0 to pc7/kr7 8 pins 5 pins 1 pin hi-z high level hi-z pe0/ec/int0 pe1/int1 pe2/int2 pe3/int3/nmi pe4/rmc aa aa ip aa aa schmitt input rd (port e) data bus ec/int0 int1 int2 int3/nmi rmc data bus rd (port c) aaaa aa port c direction ip aa aa aaaa aaaa port c data aaaa aaaa pull-up resistor "0" when reset "0" when reset * 1 large current 12ma * 2 pull-up transistor approx. 100k w * 2 * 1 key input signal data bus rd (port b) aa ip aa aa aaaa port b output selection "0" when reset * pull-up transistor approx. 100k w * aaaa aaaa port b data aaaa aaaa port b direction ??when reset aaaa pull-up resistor so output enable "0" when reset port e pe5 1 pin pe6/rmco aa aa ip aa aa rd (port e) data bus port e port e output selection rd (port e) data bus "0" when reset reset e data "1" when reset remote control transmission circuit output enable port e port c port b when reset pin circuit format
?8 cxp82940/82948/82952/82960 1 pin pe7/to/adj aa aa aaaa port e data * 1 adj signal is a frequency dividing output for 32khz oscillation frequency adjustment. adj2 can be used for buzzer output. * 2 pull-up transistor approx. 150k w . aaaaa aaaaa port e output selection (lower) "00" when reset aaaaa port e output selection (upper) to adj16k * 1 adj2k * 1 to output enable 01 10 11 00 mpx internal reset signal * 2 "1" when reset port e 4 pins hi-z pf0/scl0 pf1/scl1 pf2/sda0 pf3/sda1 scl, sda (i 2 c circuit) aa aa aaa aaa port f data scl, sda i 2 c output enable ("0" when reset) large current 12ma to internal i 2 c pin (to scl1 for scl0) bus sw "1" when reset aa aa ip schmitt input port f 5 pins hi-z pb0 pg0 to pg3 data bus rd (port b or port g) aa aa ip aa aa aaaaa aaaaa port b data or port g data "0" when reset * pull-up transistor approx. 100k w * aaaa pull-up resistor "0" when reset aaaaa aaaaa port b direction or port g direction port b port g high level ( with approx. 150k resistor when reset) when reset pin circuit format
?9 cxp82940/82948/82952/82960 20 pins hi-z or low level (when pd resistor is connected) s8 to s11 t15/s12 to t8/s19 t0 to t7 aa aa * segment output data timing output data output selection control signal ("0" when reset) op aa aa mask option pull-down resistor v fdp * high voltage drive transistor 2 pins oscillation extal xtal aa aa ip aa extal xtal diagram shows circuit composition during oscillation. feedback resistor is removed during stop, and xtal becomes high. a ip 2 pins oscillation tex tx aa aa ip aa tex tx diagram shows circuit composition during oscillation. a ip when the operation of the oscillation circuit is stopped by the software, the feedback resistor is removed, and tex becomes low level and tx becomes high level. 1 pin low level rst aa aa schmitt input pull-up resistor mask option op a a ip 8 pins hi-z or low level (when pd resistor is connected) pd0/s0 to pd7/s7 data bus rd (port d) aa aa aaaaa aaaaa port d data * segment output data output selection control signal ("0" when reset) op aa aa mask option pull-down transistor v fdp * high voltage drive transistor port d when reset pin circuit format
?10 cxp82940/82948/82952/82960 * 1 v in and v out must not exceed v dd + 0.3v. * 2 specifies output current of general-purpose i/o ports. * 3 the large current drive transistor is the n-ch transistor of port c (pc) and port f (pf). note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should be conducted under the recommended operating conditions. exceeding these conditions may adversely affect the reliability of the lsi. supply voltage input voltage output voltage display output voltage high level output current high level total output current low level output current low level total output current operating temperature storage temperature allowable power dissipation v dd v in v out v od i oh i odh1 i odh2 i oh i odh i ol i olc i ol topr tstg p d ?.3 to +7.0 ?.3 to +7.0 * 1 ?.3 to +7.0 * 1 v dd ?40 to v dd + 0.3 ? ?5 ?5 ?0 ?00 15 20 100 ?0 to +75 ?5 to +150 600 v v v v ma ma ma ma ma ma ma ma ? ? mw as p channel transistor is open drain, v dd is reference. all pins excluding outputs * 2 (value per pin) display outputs s0 to s11 (value per pin) display outputs t0 to t7, and t8/s19 to t15/s12 (value per pin) total for all pins excluding display outputs total for all display outputs port (value per pin) large current port (value per pin) * 3 total for all output pins item symbol rating unit remarks absolute maximum ratings (vss = 0v reference)
?11 cxp82940/82948/82952/82960 high level input voltage low level input voltage operating temperature supply voltage 5.5 5.5 5.5 5.5 v dd v dd v dd + 0.3 0.3v dd 0.2v dd 0.4 +75 v v v v v v v v v v ? item symbol min. max. unit remarks 4.5 3.5 2.7 2.5 0.7v dd 0.8v dd v dd ?0.4 0 0 ?.3 ?0 v ih v ihs v ihex v il v ils v ilex topr guaranteed operation range for high-speed mode (1/2, 1/4 frequency dividing clock) guaranteed operation range for low-speed mode (1/16 frequency dividing clock) or sleep mode guaranteed operation range with tex clock guaranteed data hold range during stop * 1 hysteresis input * 2 extal * 3 * 1 hysteresis input * 2 extal * 3 v dd * 1 value for each pin of normal input port (pa, pb0, pb3, pb4, pb6, pb7, pc, pe5, pg). * 2 value of the following pins: rst, cs0, sck0, sck1, ec/int0, int1, int2, int3/nmi, rmc, scl0, scl1, sda0, sda1. * 3 specifies only during external clock input. recommended operating conditions (vss = 0v reference)
?12 cxp82940/82948/82952/82960 v dd = 4.5v, i oh = ?.5ma v dd = 4.5v, i oh = ?.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 12.0ma v dd = 4.5v, i ol = 3.0ma v dd = 4.5v, i ol = 4.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v il = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v il = 0.4v v dd = 4.5v, v il = 4.0v v dd = 4.5v v oh = v dd ?2.5v v dd = 5.5v v ol = v dd ?35v v fdp = v dd ?35v v dd = 5v v od ?v fdp = 30v v dd = 5.5v v i = 0, 5.5v v dd = 5.5v, v oh = 5.5v v dd = 4.5v v scl0 = v scl1 = 2.25v v sda0 = v sda1 = 2.25v 4.0 3.5 0.5 ?.5 0.1 ?.1 ?.5 ?.3 ? ?0 60 v v v v v v v ? ? ? ? ? ? ? ma ma ? k ? ? pc, pf pf (scl0, scl1, sda0, sda1) pa, pb, pc, pe6, pe7, pg extal tex rst * 1 pa to pc * 2 , pg * 2 pa to pc * 2 , pg * 2 , rst * 1 s0 to s11, s12/t15 to s19/t8, t0 to t7 i iz i il i oh i lol r l v oh v ol i ihe i ile i iht i ilt i ilr 100 0.4 0.6 1.5 0.4 0.6 40 ?0 10 ?0 ?00 ?0 ?0 270 ?0 10 120 s0 to s11, s12/t15 to s19/t8, t0 to t7 open drain output leakage current (n-ch tr off state) i loh pf i 2 c bus switch connection impedance (output tr off state) r bs scl0: scl1 sda0: sda1 s12/t15 to s19/t8, t0 to t7 s0 to s11 high level output current display output current item symbol pins conditions min. open drain output leakage current (p-ch tr off state) pull-down resistance * 3 i/o leakage current low level output current input current typ. max. unit dc characteristics electrical characteristics (ta = ?0 to +75?, vss = 0v reference)
?13 cxp82940/82948/82952/82960 pa to pc, pe0 to pe5, pf, pg, extal, xtal, tex, tx, rst * 1 rst specifies the input current when pull-up resistance has been selected; leakage current when no resistance has been selected. * 2 pa to pc and pg specify the input current when pull-up resistance has been selected, leakage current when no resistance has been selected. * 3 when incorporated pull-down resistance has been selected through mask option. * 4 when all pins are open. power supply current * 4 input capacity v dd i dds1 i dd2 i dd1 i dds2 i dds3 stop mode v dd = 5.5v, termination of 16mhz and 32khz crystal oscillation v dd = 5.5v, 16mhz crystal oscillation (c 1 = c 2 = 15pf) v dd = 3v, 32khz crystal oscillation (c 1 = c 2 = 47pf) 2.5 10 ma 830a v dd = 5.5v, 10mhz crystal oscillation (c 1 = c 2 = 15pf) v dd = 3v, 32mhz crystal oscillation (c 1 = c 2 = 47pf) 10 a c in clock 1mhz 0v for all pins excluding measured pins 10 20 pf sleep mode high speed mode operation (1/2 frequency dividing clock) 31 50 ma 40 100 a symbol pins conditions min. typ. max. unit item
?14 cxp82940/82948/82952/82960 * t sys indicates the three values below according to the upper two bits (cpu clock selected) of the control clock registor (address: 00fe h ). t sys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") extal t xh t xl t cf t cr 0.4v v dd ?0.4v 1/fc aaaa a aa a aaaa aaaa a aa a aaaa crystal oscillation ceramic oscillation extal xtal external clock extal xtal 74hc04 c 1 c 2 aaaa a aa a aaaa 32khz clock applied condition crystal oscillation tex tx c 1 c 2 tex ec t eh t el t ef t er 0.2v dd 0.8v dd t th t tl t tf t tr ac characteristics (1) clock timing system clock frequency system clock input pulse width system clock input rise time, fall time event count input clock pulse width event count input clock rise time, fall time system clock frequency event count input pulse width event count input rise time, fall time f c t xl t xh t cr t cf t eh t el t er t ef f c t tl t th t tr t tf xtal extal extal extal ec ec tex tx tex tex mhz ns ns ns ms khz ? ms item symbol pin conditions min. unit fig. 1, fig. 2 fig. 1, fig. 2 external clock drive fig. 1, fig. 2 external clock drive fig. 3 fig. 3 v dd = 2.7 to 5.5v fig. 2 (32khz clock applied condition) fig. 3 fig. 3 1 28 4 t sys * 10 typ. 32.768 max. 16 200 20 20 (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v reference) fig. 2. clock applied conditions fig. 1. clock timing fig. 3. event count clock timing
?15 cxp82940/82948/82952/82960 chip select transfer mode (sck = output mode) chip select transfer mode (sck = output mode) chip select transfer mode chip select transfer mode chip select transfer mode note 1) t sys indicates the three values below according to the upper two bits (cpu clock selected) of the control clock registor (address: 00fe h ). t sys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") note 2) cs, sck, si and so correspond to each pin of cs0, sck0, si0 and so0. note 3) the load condition for the sck output mode, so output delay time is 50pf + 1ttl. (2) serial transfer (ch0) (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v reference) item cs ? sck delay time cs - ? sck float delay time cs ? so delay time cs - ? so float delay time cs high level width sck cycle time sck high, low level width si input setup time (for sck - ) si input hold time (for sck - ) sck ? so delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0 sck0 so0 so0 cs0 sck0 sck0 si0 si0 so0 input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode ns ns ns ns ns symbol pin min. 1.5 t sys + 200 1.5 t sys + 200 1.5 t sys + 200 1.5 t sys + 200 t sys + 200 2 t sys + 200 8000/fc t sys + 100 8000/fc ?100 t sys + 100 200 2 t sys + 100 100 ns ns ns ns ns ns ns ns ns ns 2 t sys + 200 100 max. unit condition
?16 cxp82940/82948/82952/82960 fig. 4. serial transfer ch0 timing (ch0) cso sck0 0.2v dd 0.8v dd t whcs t dcsk t dcskf 0.8v dd 0.2v dd 0.8v dd t kcy t kl t kh 0.8v dd 0.2v dd si0 t sik input data t dcso t kso t dcsof output data 0.8v dd 0.2v dd so0 t ksi
?17 cxp82940/82948/82952/82960 serial transfer (ch1) (sio mode) (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v reference) item sck1 cycle time t kcy sck1 input mode ouput mode input mode ouput mode sck1 input mode sck1 ouput mode sck1 input mode sck1 ouput mode sck1 input mode sck1 ouput mode 2 t sys + 200 16000/fc t sys + 100 8000/fc ?50 100 200 t sys + 200 100 t sys + 200 100 ns ns ns ns ns ns ns ns ns ns sck1 si1 si1 so1 t kh t kl t sik t ksi t kso sck1 high, low level width si1 input setup time (for sck1 - ) si1 input hold time (for sck1 - ) sck1 ? so1 delay time symbol pin condition min. max. unit note 1) t sys indicates the three values below according to the upper two bits (cpu clock selected) of the control clock registor (address: 00fe h ). t sys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") note 2) the load condition for the sck1output mode, so1 output delay time is 50pf + 1ttl. fig. 5. serial transfer ch1 timing (sio mode) sck1 si1 so1 t kcy t kl t kh 0.2v dd 0.8v dd t sik t ksi t kso input data output data 0.2v dd 0.8v dd 0.2v dd 0.8v dd
?18 cxp82940/82948/82952/82960 so1 cycle time si1 data setup time si1 data hold time t lcy * t lsu t lhd so1 si1 si1 si1 2 2 104 s ? ? item symbol pin condition min. typ. max. unit * t lcy is specified only when the lower two bits (so1 clock selected) of the serial mode register (ch1) (siom1: address 01e2 h ) is set to 104s. note) the load condition for so1 is 50pf + 1ttl. serial transfer (ch1) (special mode) (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v reference) fig. 6. serial transfer ch1 timing (special mode) so1 si1 t lcy start bit output data bit t lcy 0.5v dd 0.8v dd 0.2v dd t lcy/2 t lsu t lhd input data bit
?19 cxp82940/82948/82952/82960 t conv t samp v ref v ian v zt * 1 v ft * 2 i ref av ref an0 to an7 ta = 25? v dd = av dd = av ref = 5.0v v ss = av ss = 0v v dd = av dd = 4.5 to 5.5v av ref i refs ? ? v v av dd av ref 1.0 ma 10 a 0.6 160/f adc * 3 12/f adc * 3 av dd ?0.5 0 bits 8 3 lsb 70 mv 5030 10 4970 ?0 4910 mv fig. 7. definition of a/d converter terms analog input linearity error v ft v zt 00 h 01 h fe h ff h digital conversion value 00 ( f = f ex /2) 01 ( f = f ex /4) 11 ( f = f ex /16) f adc = f c /2 f adc = f c /4 f adc = f c /16 0 ( f /2 selection) cks pck1, pck0 f adc = f c f adc = f c /2 f adc = f c /8 1 ( f selection) conversion time sampling time reference input voltage analog input voltage operation mode sleep mode stop mode 32khz operation mode linearity error zero transition voltage full-scale transition voltage resolution av ref current item symbol pin condition min. typ. max. unit (3) a/d converter characteristics (ta = ?0 to +75?, v dd = 4.5 to 5.5v, av ref = 4.0 to av dd , vss = av ss = 0v reference) * 1 v zt : value at which the digital conversion value change from 00 h to 01 h and vice versa. * 2 v ft : value at which the digital conversion value changes from fe h to ff h and vice versa. * 3 f adc indicates the below values due to the contents of bit 6 (cks) of the a/d control register (address: 00f9 h ) and bits 7 (pck1) and 6 (pck0) of the clock control register (address: 00fe h ).
?20 cxp82940/82948/82952/82960 external interruption high, low level width reset input low level width int0 int1 int2 int3 nmi rst 1 32/fc ? ? item symbol pin condition min. max. unit t ih t il t rsl (4) interruption, reset input (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v reference) 0.2v dd 0.8v dd t ih t il int0 int1 int2 int3 nmi (nmi specifies only the falling edge.) t il t ih fig. 8. interruption input timing t rsl 0.2v dd rst fig. 9. rst input timing
?21 cxp82940/82948/82952/82960 (5) i 2 c bus timing (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v reference) item scl clock frequency bus-free time before starting transfer hold time for starting transfer clock low level width clock high level width setup time for repetitive transfers data hold time data setup time sda, scl rise time sda, scl fall time setup time for transfer completion f slc t buf t hd; sta t low t high t su; sta t hd; dat t su; dat t r t f t su; sto scl sda, scl sda, scl scl scl sda, scl sda, scl sda, scl sda, scl sda, scl sda, scl 0 4.7 4.0 4.7 4.0 4.7 0 * 250 4.7 100 1 300 khz ? ? ? ? ? ? ns ? ns ? symbol pin condition min. max. unit * the data hold time must exceed 300ns because the scl rise time (300ns max.) is not taken into consideration. fig.10. i 2 c bus transfer timing p st t su ; sto t su ; sta t hd ; sta t su ; dat t high t hd ; dat t f t r t low t hd ; sta s p t buf sda scl fig.11. recommended circuit example for i 2 c device i 2 c device i 2 c device r s r s r s r s r p r p sda0 (or sda1) scl0 (or scl1) pull-up resistors (r p ) must be connected to sda0 (or sda1) and scl0 (or scl1). serial resistance (rs = 300 or less) of sda0 (or sda1) and scl0 (scl1) reduces spike noise caused by crt flash-over.
?22 cxp82940/82948/82952/82960 appendix fig. 12. recommended oscillation circuit aaaaa a aaa a aaaaa extal xtal c 1 c 2 rd (i) aaaaa a aaa a aaaaa tex tx c 1 c 2 rd (ii) manufacturer river eletec co., ltd. kinseki ltd. model hc-49/u03 hc-49/u (-s) p3 fc (mhz) 8.00 10.00 12.00 8.00 10.00 12.00 12 12 12 12 0 16.00 30 18 470k (ii) 32.768khz 10 5 16 (12) 10 16.00 5 16 (12) 16 (12) 16 (12) 0 0 0 c 1 (pf) c 2 (pf) rd ( ) circuit example (i) (i) item content reset pin pull-up resistance non-existent existent non-existent existent (selectable for each pin) mask option table high voltage drive output port pull-down resistance
?23 cxp82940/82948/82952/82960 characteristics curve v dd ?supply voltage [ v ] i dd vs. v dd (fc = 16mhz, ta = 25?, typical) 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode sleep mode 30 20 10 0 2 10 15 34 6 57 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode sleep mode 32khz mode (instruction) 32khz sleep mode i dd ?supply current [ma] 50 30 20 10 5 1 0.5 (500a) 0.1 (100a) 0.05 (50a) 0.01 (10a) i dd vs. fc (v dd = 5v, ta = 25?, typical) 5 01 frequency [mhz] i dd ?supply current [ma]
?24 cxp82940/82948/82952/82960 package structure sony code eiaj code jedec code qfp-80p-l01 * qfp080-p-1420-a package material lead treatment lead material package weight epoxy resin solder plating copper / 42 alloy 1.6g 23.9 0.4 20.0 ?0.1 + 0.4 1 80 65 64 41 40 25 24 0.8 0.35 ?0.1 + 0.15 14.0 ?0.1 + 0.4 17.9 0.4 16.3 0.1 ?0.05 + 0.2 2.75 ?0.15 + 0.35 0.8 0.2 0.15 ?0.05 + 0.1 80pin qfp (plastic) m 0.12 0.15 0?to 10 detail a a package outline unit: mm

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