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ultra-low distortion differential adc driver preliminary technical data ada4938-1 rev. prd information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features extremely low harmonic distortion ?112 dbc hd2 @ 10 mhz ?79 dbc hd2 @ 50 mhz ?102 dbc hd3 @ 10 mhz ?81 dbc hd3 @ 50 mhz low input voltage noise: 2.2 nv/hz high speed ?3 db bandwidth of 1.5 ghz, g = 1 slew rate: 4700 v/s 0.1 db gain flatness to 125 mhz fast overdrive recovery of 4 ns 1 mv typical offset voltage externally adjustable gain differential to differential or single-ended to differential operation adjustable output common-mode voltage wide supply voltage range: +5 v & 5 v pb-free 3 mm x 3 mm lfcsp package applications adc drivers single-ended-to-differential converters if and baseband gain blocks differential buffers line drivers functional block diagram + ? figure 1. general description the ada4938-1 is a low noise, ultra-low distortion, high speed differential amplifier. it is an ideal choice for driving high performance adcs with resolutions up to 16 bits from dc to 70 mhz. the output common mode voltage is adjustable over a wide range, allowing the ada4938-1 to match the input of the adc. the internal common mode feedback loop also provides exceptional output balance as well as suppression of even-order harmonic distortion products. full differential and single-ended to differential gain configurations are easily realized with the ada4938-1. a simple external feedback network of four resistors determines the amplifiers closed-loop gain. the ada4938-1 is fabricated using adis proprietary third generation high-voltage xfcb process, enabling it to achieve very low levels of distortion with input voltage noise of only 2.2 nv/hz. the low dc offset and excellent dynamic performance of the ada4938-1 make it well suited for a wide variety of data acquisition and signal processing and applications. the ada4938-1 is available in a pb-free, 3 mm x 3mm lead frame chip scale package (lfcsp). pinout has been optimized to facilitate layout and minimize distortion. the part is specified to operate over the extended industrial temperature range of ?40c to +85c.
ada4938-1 preliminary technical data rev. prd | page 2 of 14 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 dual supply operation ................................................................ 3 single supply operation.............................................................. 5 absolute maximum ratings............................................................ 7 thermal resistance ...................................................................... 7 esd caution.................................................................................. 7 pin configuration and function descriptions............................. 8 operational description.................................................................. 9 definition of terms.......................................................................9 theory of operation ...................................................................... 10 analyzing an application circuit ............................................ 10 setting the closed-loop gain .................................................. 10 estimating the output noise voltage ...................................... 10 the impact of mismatches in the feedback networks ......... 11 calculating the input impedance of an application circuit 11 input common-mode voltage range in single-supply applications ................................................................................ 11 setting the output common-mode voltage .......................... 11 layout, grounding, and bypassing.............................................. 13 outline dimensions ....................................................................... 14 ordering guide .......................................................................... 14 revision history 05/07rev. prc to rev. prd changes to features.......................................................................... 1 changes to figure 1.......................................................................... 1 changes to table 1............................................................................ 3 changes to table 2............................................................................ 5 changes to figure 3.......................................................................... 8 changes to table 5 ........................................................................... 8 added to operational description section .................................. 9 added to theory of operation section ....................................... 10 added to layout, grounding, and bypassing section............... 13 04/07rev. prb to rev. prc changes to features.......................................................................... 1 changes to table 1............................................................................ 3 changes to table 2............................................................................ 5 changes to table 3............................................................................ 7 changes to table 4............................................................................ 7 added figure 2 ................................................................................. 7 changes to figure 4.......................................................................... 9 changes to ordering guide ............................................................ 9 01/07rev. pra to rev. prb changes to features.......................................................................... 1 changes to general description .................................................... 1 changes to table 1............................................................................ 3 changes to table 2............................................................................ 5 12/06revision pra: initial version
preliminary technical data ada4938-1 rev. prd | page 3 of 14 specifications dual supply operation t a = 25c, +v s = 5 v, ?v s = -5 v, v ocm = 0 v, r t = 61.9 , r g = r f = 200 , g = 1, r l, dm = 1 k, unless otherwise noted. all specifications refer to single-ended input and differential outputs, unless otherwise noted. table 1. parameter conditions min typ max unit d in to out performance dynamic performance ?3 db small signal bandwidth v out = 0.1 v p-p, differential input 1500 mhz bandwidth for 0.1 db flatness v out = 2 v p-p, differential input 125 mhz large signal bandwidth v out = 2 v p-p, differential input 1300 mhz v out = 4 v p-p, differential input 800 mhz slew rate v out = 2 v p-p 4700 v/s overdrive recovery time v in = 5 v to 0 v step, g = +2 4 ns noise/harmonic performance second harmonic v out = 2 v p-p, 10 mhz ?112 dbc v out = 2 v p-p, 50 mhz ?79 dbc third harmonic v out = 2 v p-p, 10 mhz ?102 dbc v out = 2 v p-p, 50 mhz ?81 dbc imd 50 mhz dbc ip3 50 mhz dbm voltage noise (rti) 2.2 nv/hz noise figure g = +2 21 db input current noise 2 pa/hz input characteristics offset voltage v os, dm = v out, dm /2; v din+ = v din? = 0 v 1 mv t min to t max variation 4 v/c input bias current 3.5 a t min to t max variation ?0.01 a/c input resistance differential 6 m common mode 3 m input capacitance 1 pf input common-mode voltage ?4.7 to 3.4 v cmrr ?v out, dm /?v in, cm ; ?v in, cm = 1 v ?77 db output characteristics output voltage swing maximum ?v out ; single-ended output -3.9 3.9 v linear output current 95 ma output balance error ?v out, cm /?v out, dm ; ?v out, dm = 1 v; 10 mhz ?66 db v ocm to out performance v ocm dynamic performance ?3 db bandwidth 400 mhz slew rate 1700 v/s input voltage noise (rti) 7.5 nv/hz v ocm input characteristics input voltage range ?3.8 3.8 v input resistance 200 k input offset voltage v os, cm = v out, cm ; v din+ = v dinC = 0 v 1 3.5 mv input bias current 0.5 a v ocm cmrr ?v out, dm /?v ocm ; ?v ocm = 1 v ?75 db gain ?v out, cm /?v ocm ; ?v ocm = 1 v 1 v/v power supply operating range 4.5 11 v
ada4938-1 preliminary technical data rev. prd | page 4 of 14 parameter conditions min typ max unit quiescent current 40 ma t min to t max variation 40 a/c powered down < 1 ma power supply rejection ratio ?v out, dm /?v s ; ?v s = 1 v ?90 db power down ( pd ) pd input voltage powered down 1 v enabled 2 v turn-off time 1 s turn-on time 200 ns pd bias current enabled pd = 5 v 40 a disabled pd = 0 v 200 a operating temperature range ?40 +85 c
preliminary technical data ada4938-1 rev. prd | page 5 of 14 single supply operation t a = 25c, +v s = 5 v, ?v s = 0 v, v ocm = +v s /2, r t = 61.9 , r g = r f = 200 , g = 1, r l, dm = 1 k, unless otherwise noted. all specifications refer to single-ended input and differential outputs, unless otherwise noted. table 2. parameter conditions min typ max unit d in to out performance dynamic performance ?3 db small signal bandwidth v out = 0.1 v p-p, differential input 1500 mhz bandwidth for 0.1 db flatness v out = 2 v p-p, differential input 125 mhz large signal bandwidth v out = 2 v p-p, differential input 1100 mhz slew rate v out = 2 v p-p 3900 v/s overdrive recovery time v in = 2.5 v to 0 v step, g = +2 4 ns noise/harmonic performance second harmonic v out = 2 v p-p, 10 mhz ?110 dbc v out = 2 v p-p, 50 mhz ?79 dbc third harmonic v out = 2 v p-p, 10 mhz ?100 dbc v out = 2 v p-p, 50 mhz ?79 dbc imd 50 mhz dbc ip3 50 mhz dbm voltage noise (rti) 2.2 nv/hz noise figure g = +2 21 db input current noise 2 pa/hz input characteristics offset voltage v os, dm = v out, dm /2; v din+ = v din? = v ocm = 2.5 v 1 mv t min to t max variation 4 v/c input bias current 3.5 a t min to t max variation ?0.01 a/c input resistance differential 6 m common mode 3 m input capacitance 1 pf input common-mode voltage 0.3 to 3.4 v cmrr ?v out, dm /?v in, cm ; ?v in, cm = 1 v ?77 db output characteristics output voltage swing maximum ?v out ; single-ended output 1.1 3.9 v output current 95 ma output balance error ?v out, cm /?v out, dm ; ?v out, dm = 1 v ?66 db v ocm to out performance v ocm dynamic performance ?3 db bandwidth 400 mhz slew rate v = 0.5 v 1700 v/s input voltage noise (rti) 7.5 nv/hz v ocm input characteristics input voltage range 1.2 3.8 v input resistance 200 k input offset voltage v os, cm = v out, cm ; v din+ = v dinC = v ocm = 2.5 v 1 mv input bias current 0.5 a v ocm cmrr ?v out, dm /?v ocm ; ?v ocm = 1 v ?75 db gain ?v out, cm /?v ocm ; ?v ocm = 1 v 1 v/v power supply operating range 4.5 11 v quiescent current 36 ma t min to t max variation 40 a/c powered down < 1 ma
ada4938-1 preliminary technical data rev. prd | page 6 of 14 parameter conditions min typ max unit power supply rejection ratio ?v out, dm /?v s ; ?v s = 1 v ?90 db power down ( pd ) pd input voltage powered down 1 v enabled 2 v turn-off time 1 s turn-on time 200 ns pd bias current enabled pd = 5 v 20 a disabled pd = 0 v ?120 a operating temperature range ?40 +85 c
preliminary technical data ada4938-1 rev. prd | page 7 of 14 absolute maximum ratings table 3. parameter rating supply voltage 12 v power dissipation see figure 2 storage temperature range ?65c to +125c operating temperature range ?40c to +85c lead temperature (soldering, 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum rating may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the device (including exposed pad) soldered to a high thermal conductivity 2s2p circuit board, as described in eia/jesd 51-7. table 4. thermal resistance package type ja unit 16-lead lfcsp (exposed pad) 95 c/w maximum power dissipation the maximum safe power dissipation in the ada4938-1 package is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150c, which is the glass transition temperature, the plastic changes its properties. even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ada4938-1. exceeding a junction temperature of 150c for an extended period can result in changes in the silicon devices, potentially causing failure. the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ). the power dissipated due to the load drive depends upon the particular application. the power due to load drive is calculated by multiplying the load current by the associated voltage drop across the device. rms voltages and currents must be used in these calculations. airflow increases heat dissipation, effectively reducing ja . in addition, more metal directly in contact with the package leads/exposed pad from metal traces, through-holes, ground, and power planes reduces the ja . figure 2 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 16-lead lfcsp (95 c/w) on a jedec standard 4-layer board. 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?45 105 95 85 75 65 55 45 35 25 15 5 ?5 ?15 ?25 ?35 maximum power dissipation (w) ambient temperature (c) 06591-003 figure 2. maximum power dissipation vs. temperature for a 4-layer board esd caution
ada4938-1 preliminary technical data rev. prd | page 8 of 14 pin configuration and fu nction descriptions figure 3. pin configuration table 5. pin function descriptions pin no. mnemonic description 1 ?fb negative output for feedback component connection 2 +in positive input summing node 3 ?in negative input summing node 4 +fb positive output for feedback component connection 5 to 8 +v s positive supply voltage 9 v ocm output common-mode voltage 10 +out positive output for load connection 11 ?out negative output for load connection 12 pd power-down pin 13 to 16 ?v s negative supply voltage
preliminary technical data ada4938-1 rev. prd | page 9 of 14 operational description definition of terms figure 4. circuit definitions differential voltage this refers to the difference between two node voltages. for example, the output differential voltage (or equivalently, output differential-mode voltage) is defined as v out, dm = ( v +out ? v ?out ) where v +out and v ?out refer to the voltages at the +out and ?out terminals with respect to a common reference. common-mode voltage this refers to the average of two node voltages. the output common-mode voltage is defined as v out, cm = ( v +out + v ?out )/2 balance balance is a measure of how well differential signals are matched in amplitude and are exactly 180 apart in phase. balance is most easily determined by placing a well-matched resistor divider between the differential voltage nodes and comparing the magnitude of the signal at the dividers midpoint with the magnitude of the differential signal. by this definition, output balance is the magnitude of the output common-mode voltage divided by the magnitude of the output differential mode voltage. dm out cm out v v error balance output , , =
ada4938-1 preliminary technical data rev. prd | page 10 of 14 theory of operation the ada4938-1 differs from conven tional op amps in that it has two outputs whose voltages move in opposite directions. like an op amp, it relies on open-loop gain and negative feedback to force these outputs to the desired voltages. the ada4938-1 behaves much like a standard voltage feedback op amp and makes it easier to perform single-ended-to-differential conversions, common-mode level shifting, and amplifications of differential signals. also like an op amp, the ada4938-1 has high input impedance and low output impedance. two feedback loops are employed to control the differential and common-mode output voltages. the differential feedback, set with external resistors, controls only the differential output voltage. the common-mode feedback controls only the common- mode output voltage. this architecture makes it easy to set the output common-mode level to any arbitrary value. it is forced, by internal common-mode feedback, to be equal to the voltage applied to the v ocm input, without affecting the differential output voltage. the ada4938-1 architecture results in outputs that are highly balanced over a wide frequency range without requiring tightly matched external components. the common-mode feedback loop forces the signal component of the output common- mode voltage to zero. this results in nearly perfectly balanced differential outputs that are identical in amplitude and are exactly 180 apart in phase. analyzing an application circuit the ada4938-1 uses open-loop gain and negative feedback to force its differential and common-mode output voltages in such a way as to minimize the differential and common-mode error voltages. the differential error voltage is defined as the voltage between the differential inputs labeled +in and ?in (see figure 4). for most purposes, this voltage can be assumed to be zero. similarly, the difference between the actual output common-mode voltage and the voltage applied to v ocm can also be assumed to be zero. starting from these two assumptions, any application circuit can be analyzed. setting the closed-loop gain the differential-mode gain of the circuit in figure 4 can be determined by g f dm in dm out r r v v = , , this assumes the input resistors ( r g ) and feedback resistors ( r f ) on each side are equal. estimating the output noise voltage the differential output noise of the ada4938-1 can be estimated using the noise model in figure 5. the input-referred noise voltage density, v nin , is modeled as a differential input, and the noise currents, i nin? and i nin+ , appear between each input and ground. the noise currents are assumed to be equal and produce a voltage across the parallel combination of the gain and feedback resistances. v ncm is the noise voltage density at the v ocm pin. each of the four resistors contributes (4ktr x ) 1/2 . table 6 summarizes the input noise sources, the multiplication factors, and the output-referred noise density terms. ada4938-1 + r f2 v nod v ncm v ocm v nin r f1 r g2 r g1 v nrf1 v nrf2 v nrg1 v nrg2 i nin+ i nin? figure 5. ada4938-1 noise model table 6. output noise voltag e density calculations input noise contribution input noise term input noise voltage density output multiplication factor output noise voltage density term differential input v nin v nin g n v no1 = g n (v nin ) inverting input i nin? i nin? (r g2 ||r f2 ) g n v no2 = g n [i nin? (r g2 ||r f2 )] noninverting input i nin+ i nin+ (r g1 ||r f1 ) g n v no3 = g n [i nin+ (r g1 ||r f1 )] v ocm input v ncm v ncm g n ( 1 ? 2 ) v no4 = g n ( 1 ? 2 )(v ncm ) gain resistor r g1 v nrg1 (4ktr g1 ) 1/2 g n (1 ? 2 ) v no5 = g n (1 ? 2 )(4ktr g1 ) 1/2 gain resistor r g2 v nrg2 (4ktr g2 ) 1/2 g n (1 ? 1 ) v no6 = g n (1 ? 1 )(4ktr g2 ) 1/2 feedback resistor r f1 v nrf1 (4ktr f1 ) 1/2 1 v no7 = (4ktr f1 ) 1/2 feedback resistor r f2 v nrf2 (4ktr f2 ) 1/2 1 v no8 = (4ktr f2 ) 1/2
preliminary technical data ada4938-1 rev. prd | page 11 of 14 similar to the case of a conventional op amp, the output noise voltage densities can be estimated by multiplying the input- referred terms at +in and ?in by the appropriate output factor, where: () 2 1 n g + = 2 is the circuit noise gain. g1 f1 g1 1 r r r + = and g2 f2 g2 2 r r r + = are the feedback factors. when r f1 /r g1 = r f2 /r g2 , then 1 = 2 = , and the noise gain becomes g f n r r g + = = 1 1 note that the output noise from v ocm goes to zero in this case. the total differential output noise density, v nod , is the root-sum- square of the individual output noise terms. = = 8 1 i 2 noi nod v v the impact of mismatch es in the feedback networks as previously mentioned, even if the external feedback networks ( r f /r g ) are mismatched, the internal common-mode feedback loop still forces the outputs to remain balanced. the amplitudes of the signals at each output remain equal and 180 out of phase. the input-to-output, differential mode gain varies proportionately to the feedback mismatch, but the output balance is unaffected. as well as causing a noise contribution from v ocm , ratio matching errors in the external resistors result in a degradation of the ability of the circuit to reject input common-mode signals, much the same as for a four-resistor difference amplifier made from a conventional op amp. in addition, if the dc levels of the input and output common- mode voltages are different, matching errors result in a small differential-mode output offset voltage. when g = 1, with a ground referenced input signal and the output common-mode level set to 2.5 v, an output offset of as much as 25 mv (1% of the difference in common-mode levels) can result if 1% tolerance resistors are used. resistors of 1% tolerance result in a worst- case input cmrr of about 40 db, a worst-case differential- mode output offset of 25 mv due to 2.5 v level-shift, and no significant degradation in output balance error. calculating the input impedance of an application circuit the effective input impedance of a circuit depends on whether the amplifier is being driven by a single-ended or differential signal source. for balanced differential input signals, as shown in figure 6, the input impedance (r in, dm ) between the inputs (+d in and ?d in ) is simply r in, dm = 2 r g . figure 6. ada4938-1 configured for balanced (differential) inputs for an unbalanced, single-ended input signal (see figure 7), the input impedance is () ? ? ? ? ? ? ? ? ? ? ? ? + ? = f g f g cm in r r r r r 2 1 , figure 7. ada4938-1 configured fo r unbalanced (single-ended) input the input impedance of the circuit is effectively higher than it would be for a conventional op amp connected as an inverter because a fraction of the differential output voltage appears at the inputs as a common-mode signal, partially bootstrapping the voltage across the input resistor r g . input common-mode voltage range in single-supply applications the ada4938-1 is optimized for level-shifting, ground-referenced input signals. as such, the center of the input common-mode range is shifted approximately 1 v down from midsupply. for 5 v single-supply operation, the input common-mode range at the summing nodes of the amplifier is 0.3 v to 3.0 v. to avoid clipping at the outputs, the voltage swing at the +in and Cin terminals must be confined to these ranges. setting the output common-mode voltage the v ocm pin of the ada4938-1 is internally biased at a voltage approximately equal to the midsupply point (average value of the voltages on v+ and v?). relying on this internal bias results in an output common-mode voltage that is within about 100 mv of the expected value. in cases where more accurate control of the output common- mode level is required, it is recommended that an external source, or resistor divider (10 k or greater resistors), be used. it is also possible to connect the v ocm input to a common-mode level (cml) output of an adc. however, care must be taken to
ada4938-1 preliminary technical data rev. prd | page 12 of 14 assure that the output has sufficient drive capability. the input impedance of the v ocm pin is approximately 10 k. if multiple ada4938-1 devices share one reference output, it is recommended that a buffer be used. table 7 and table 8 list several common gain settings, associated resistor values, input impedance, output noise density, and approximate large signal bandwidth for both balanced and unbalanced input configurations. also shown are the input common-mode voltage swings under the given conditions for different v ocm settings with both dual and single 5 v supplies. table 7. differential ground-reference d input, dc-coupled; see figure 6 common-mode swing at +in, ?in (v) +v s = 5 v, -v s = -5 v v out, dm = 2.0 v p-p +v s =5 v v out, dm = 2.0 v p-p nominal gain (db) r f () r g () r in, dm () differential output noise density (nv/hz) approximate large-signal bandwidth (mhz) v ocm = 0 v v ocm = 3.5 v v ocm = 2.5 v v ocm = 3.2 v 0 200 200 400 5.8 -0.50 to 0.50 1.25 to 2.25 0.75 to 1.75 1.10 to 2.10 348 348 696 6.7 3 280 200 400 7.2 -0.35 to 0.35 1.10 to 1.82 0.69 to 1.40 0.98 to 1.69 348 249 498 7.6 6 200 100 200 8.0 -0.25 to 0.25 0.92 to 1.42 0.58 to 1.08 0.82 to 1.32 348 174 348 9.0 10 316 100 200 11 -0.16 to 0.16 0.68 to 1.00 0.44 to 0.76 0.61 to 0.92 348 110 220 12 12 402 100 200 14 -0.13 to 0.13 0.57 to 0.82 0.37 to 0.62 0.51 to 0.76 348 86.6 173 13 14 499 100 200 17 -0.10 to 0.10 0.48 to 0.68 0.32 to 0.52 0.43 to 0.63 348 69.8 140 16 table 8. single-ended ground-referenced input, dc-coupled, r s = 50 ; see figure 7 common-mode swing at +in, -in (v) +v s = 5 v, -v s = -5 v v out,dm = 2.0 v p-p +v s =5 v v out, dm = 2.0 v p-p nominal gain (db) r f () r g1 () r t () r in,cm () r g2 () 1 differential output noise density (nv/hz) approximate large-signal bandwidth (mhz) v ocm = 0 v v ocm = 3.5 v v ocm = 2.5 v v ocm = 3.2 v 0 200 200 61.9 267 226 5.5 -0.56 to 0.56 1.29 to 2.42 0.75 to 1.75 1.13 to 2.26 348 348 56.2 464 374 6.5 3 280 200 60.4 282 226 6.8 -0.40 to 0.40 1.16 to 1.97 0.71 to 1.52 1.03 to 1.83 348 249 59.0 351 274 7.3 6 200 100 75.0 150 130 7.0 -0.33 to 0.33 1.05 to 1.70 0.66 to 1.31 0.94 to 1.59 348 174 61.9 261 200 8.4 10 316 100 73.2 161 130 9.7 -0.21 to 0.21 0.82 to 1.23 0.52 to 0.93 0.73 to 1.14 348 110 69.8 177 140 10 12 402 100 71.5 167 130 12 -0.16 to 0.16 0.70 to 1.02 0.45 to 0.77 0.62 to 0.94 348 86.6 76.8 144 118 11 14 499 100 71.5 171 130 14 -0.13 to 0.13 0.59 to 0.85 0.39 to 0.65 0.53 to 0.79 348 69.8 86.6 120 100 12 1 r g2 = r g1 + (r s ||r t )
preliminary technical data ada4938-1 rev. prd | page 13 of 14 layout, grounding, and bypassing as a high speed device, the ada4938-1 is sensitive to the pcb environment in which it operates. realizing its superior performance requires attention to the details of high speed pcb design. the first requirement is a solid ground plane that covers as much of the board area around the ada4938-1 as possible. however, the area near the feedback resistors (r f ), gain resistors (r g ), and the input summing nodes (pin 2 and pin 3) should be cleared of all ground and power planes (see figure 8). this minimizes any stray capacitance at these nodes and prevents peaking of the response of the amplifier at high frequencies. 06591-052 figure 8. ground and power plane voiding in vicinity of r f and r g the power supply pins should be bypassed as close to the device as possible and directly to a nearby ground plane. high frequency ceramic chip capacitors should be used. it is recommended that two parallel bypass capacitors (1000 pf and 0.1 f) be used for each supply. the 1000 pf capacitor should be placed closer to the device. further away, low frequency bypassing should be provided, using 10 f tantalum capacitors from each supply to ground. signal routing should be short and direct to avoid parasitic effects. wherever complementary signals exist, a symmetrical layout should be provided to maximize balanced performance. when routing differential signals over a long distance, pcb traces should be close together, and any differential wiring should be twisted such that lo op area is minimized. this reduces radiated energy and makes the circuit less susceptible to interference.
preliminary technical data ada4938-1 ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. pr06592-0-6/07(prd) outline dimensions 1 0.50 bsc 0.60 max pin 1 indicator 1.50 ref 0.50 0.40 0.30 0.25 min 0.45 2.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indicato r 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 3.00 bsc sq * 1.45 1.30 sq 1.15 exposed pad 16 5 13 8 9 12 4 (bottom view) * compliant to jedec standards mo-220-veed-2 except for exposed pad dimension. figure 9. 16-lead lead frame chip scale package [lfcsp_vq] 3 mm 3 mm body (cp-16-2) dimensions shown in millimeters ordering guide model ordering quantity temperature range pa ckage description package option branding ada4938-1acpz-r2 5,000 ?40c to +85c 16-lead 3 mm 3 mm lfcsp cp-16-2 tbd ADA4938-1ACPZ-RL 1,500 ?40c to +85c 16-lead 3 mm 3 mm lfcsp cp-16-2 tbd ada4938-1acpz-r7 250 ?40c to +85c 16-lead 3 mm 3 mm lfcsp cp-16-2 tbd

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