? semiconductor components industries, llc, 2008 april, 2008 - rev. 3 1 publication order number: nb6l14m/d nb6l14m 2.5 v/3.3 v?3.0 ghz differential 1:4 cml fanout buffer multi-level inputs with internal termination description the nb6l14m is a 3.0 ghz differential 1:4 cml clock or data fanout buffer. the differential inputs incorporate internal 50 termination resistors that are accessed through the vt pin. this feature allows the nb6l14m to accept various logic standards, such as lvpecl, cml, or lvds logic levels. the 16 ma differential cml outputs provide matching internal 50 terminations and produce 400 mv output swings when externally terminated with a 50 resistor to v cc . the v refac reference output can be used to rebias capacitor-coupled differential or single-ended input signals. the 1:4 fanout design was optimized for low output skew applications. the nb6l14m is a member of the eclinps max ? family of high performance clock and data products. features ? input clock frequency > 3.0 ghz ? input data rate > 2.5 gb/s ? < 20 ps within device output skew ? 350 ps typical propagation delay ? 90 ps typical rise and fall times ? differential cml outputs, 340 mv amplitude, typical ? cml mode operating range: v cc = 2.375 v to 3.63 v with gnd = 0 v ? internal input and output termination resistors, 50 ? v refac reference output voltage ? -40 c to +85 c ambient operating temperature ? available in 3 mm x 3 mm 16 pin qfn ? these are pb-free devices marking diagram* http://onsemi.com qfn-16 mn suffix case 485g nb6l 14m alyw a = assembly location l = wafer lot y = year w = work week = pb-free package (note: microdot may be in either location) 16 1 *for additional marking information, refer to application note and8002/d. see detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. ordering information figure 1. simplified logic diagram q d q0 q0 q1 q1 q2 q2 q3 q3 in vt in en vrefac
nb6l14m http://onsemi.com 2 q3 v cc q0 q0 v cc in v refac q2 5678 16 15 14 13 12 11 10 9 1 2 3 4 exposed pad (ep) figure 2. qfn-16 pinout (top view) gnd vt in q3 en q2 q1 q1 figure 3. logic diagram q0 /q0 q1 /q1 q2 /q2 q3 /q3 q d 50 50 en vrefac clk in in vt table 1. en truth table in in en q0:q3 q0 :q3 0 1 x 1 0 x 1 1 0 0 1 0+ 1 0 1+ + = on next negative transition of the input signal (in). x = don't care. table 2. pin description pin name i/o description 1 q1 cml output non-inverted differential output. typically terminated with 50 resistor to v cc . 2 q1 cml output inverted differential output. typically terminated with 50 resistor to v cc . 3 q2 cml output non-inverted differential output. typically terminated with 50 resistor to v cc . 4 q2 cml output inverted differential output. typically terminated with 50 resistor to v cc . 5 q3 cml output non-inverted differential output. typically terminated with 50 resistor to v cc . 6 q3 cml output inverted differential output. typically terminated with 50 resistor to v cc . 7 v cc - positive supply voltage 8 en lvttl/lvcmos synchronous output enable. when low, q outputs will go low and q outputs will go high on the next negative transition of in input. the internal d ff register is clocked on the falling edge of in input (see figure 16). the en pin has an internal pullup resistor and defaults high when left open. 9 in lvpecl, cml, lvds inverted differential clock input. internal 50 resistor to termination pin, vt. 10 v refac output voltage reference for capacitor-coupled inputs, only. 11 vt internal 100 center-tapped termination pin for in and in . 12 in lvpecl, cml, lvds non-inverted differential clock input. internal 50 resistor to termination pin, vt. 13 gnd - negative supply voltage 14 v cc - positive supply voltage 15 q0 cml output noninverted differential output. typically terminated with 50 resistor to v cc . 16 q0 cml output inverted differential output. typically terminated with 50 resistor to v cc . - ep - the exposed pad (ep) on the qfn-16 package bottom is thermally connected to the die for improved heat transfer out of package. the exposed pad must be attached to a heat-sinking conduit. the pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to gnd on the pc board. 1. in the dif ferential configuration when the input termination pin vt , is connected to a common termination voltage or left open, and if no signal is applied on in/in inputs, then the device will be susceptible to self-oscillation.
nb6l14m http://onsemi.com 3 table 3. attributes characteristics value esd protection human body model machine mode > 2 kv > 200 v moisture sensitivity (note 2) qfn-16 level 1 flammability rating oxygen index: 28 to 34 ul 94 v-0 @ 0.125 in transistor count 167 meets or exceeds jedec spec eia/jesd78 ic latchup test 2. for additional information, see application note and8003/d. table 4. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply gnd = 0 v 4.0 v v io positive input/output gnd = 0 v -0.5 v v io v cc + 0.5 v 4.5 v i in input current source or sink current (in/in ) 50 ma i vrefac sink/source current 2.0 ma t a operating temperature range -40 to +85 c t stg storage temperature range -65 to +150 c ja thermal resistance (junction-to-ambient) (note 3) 0 lfpm 500 lfpm qfn-16 qfn-16 42 35 c/w c/w jc thermal resistance (junction-to-case) 2s2p (note 3) qfn-16 4 c/w t sol wave solder pb-free 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 3. jedec standard multilayer board - 2s2p (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
nb6l14m http://onsemi.com 4 table 5. dc characteristics, multi-level inputs, cml outputs v cc = 2.375 v to 3.63 v, gnd = 0 v, t a = -40 c to +85 c symbol characteristic min typ max unit i cc power supply current (inputs and outputs open) 80 100 130 ma cml output (notes 4 and 5) v oh output high voltage v cc = 3.3 v v cc = 2.5 v v cc - 40 3260 2460 v cc - 10 3290 2490 v cc 3300 2500 mv v ol output low voltage v cc = 3.3 v v cc = 2.5 v v cc - 500 2800 2000 v cc - 400 2900 2100 v cc - 300 3000 2200 mv differential input driven single-ended (see figures 5 and 6) v th input threshold reference voltage range (note 6) 1100 v cc - 100 mv v ih single-ended input high voltage v th + 100 v cc mv v il single-ended input low voltage gnd v th - 100 mv v ise single-ended input voltage amplitude (v ih - v il ) 200 v cc - gnd mv v refac v refac output reference voltage (v cc 2.5 v) v cc - 1525 v cc - 1425 v cc - 1325 mv differential inputs driven differentially (see figures 7 and 8) (note 7) v ihd differential input high voltage 1200 v cc mv v ild differential input low voltage gnd v ihd - 100 mv v id differential input voltage (in-in ) (v ihd- v ild ) 100 v cc - gnd mv v cmr input common mode range (differential configuration) (note 8) 950 v cc C 50 mv i ih input high current in/in (vt open) -150 +150 a i il input low current in/in (vt open) -150 +150 a lvttl/lvcmos input dc electrical characteristics v ih input high voltage 2.0 v cc v v il input low voltage gnd 0.8 v i ih input high current, v cc = v in = 3.63 v -150 +150 a i il input low current, v cc = 3.63 v, v in = 0 v -150 +150 a termination resistors r tin internal input termination resistor (in to vt) 40 50 60 r diff_in differential input resistance (in to in ) 80 100 120 r tout internal output termination resistor 40 50 60 note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. cml outputs loaded with 50 to v cc for proper operation. 5. input and output parameters vary 1:1 with v cc . 6. v th is applied to the complementary input when operating in single-ended mode. 7. v ihd , v ild , v id and v cmr parameters must be complied with simultaneously. 8. v cmr minimum varies 1:1 with gnd, v cmr max varies 1:1 with v cc . the v cmr range is referenced to the most positive side of the dif ferential input signal.
nb6l14m http://onsemi.com 5 table 6. ac characteristics v cc = 2.375 v to 3.63 v, gnd = 0 v, t a = -40 c to +85 c (note 9) symbol characteristic min typ max unit v outpp output voltage amplitude (@ v inppmin ) (note 10) f in 2.5 ghz 2.5 ghz f in 3.0 ghz 180 100 340 250 mv f data maximum operating data rate 2.5 gb/s t pd propagation delay in to q 230 350 480 ps t s set-up time (note 11) en to in, in 300 ps t h hold time (note 11) en to in, in 300 ps t skew within-device skew (note 12) device-to-device skew (note 13) 5.0 20 80 ps t dc output clock duty cycle f in 3.0 ghz (referenced duty cycle = 50%) 40 50 60 % t jitter rms random jitter (note 14) f in 3.0 ghz peak-to-peak data dependent jitter (note 15) f data 3.0 gb/s 0.2 20 0.5 ps v inpp input voltage swing/sensitivity (differential configuration) (note 10) 100 v cc - gnd mv t r ,t f output rise/fall times (20%-80%) 90 150 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. measured by forcing v inpp (minimum) from a 50% duty cycle clock source. all loading with an external r l = 50 to v cc . input edge rates 40 ps (20%-80%). 10. input and output voltage swing is a single-ended measurement operating in differential mode. 11. set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. for async hronous applications, set-up and hold times do not apply. 12. within device skew is measured between two different outputs under identical power supply, temperature and input conditions. 13. device to device skew is measured between outputs under identical transition @ 0.5 ghz. 14. additive rms jitter with 50% duty cycle clock signal. 15. additive peak-to-peak data dependent jitter with input nrz data at prbs 23-1 and k28.5 at 2.5 gb/s.
nb6l14m http://onsemi.com 6 figure 4. input structure 50 50 inn vtn inn in v th in v th figure 5. differential input driven single-ended v ih v il v ihmax v ilmax v ih v th v il v ihmin v ilmin v cc v thmax v thmin gnd v th figure 6. v th diagram in in figure 7. differential inputs driven differentially v il v ih(max) v ih v il v ih v il(min) v cmr gnd v id = v ihd - v ild v cc figure 8. v cmr diagram in in q q t pd t pd v outpp = v oh (q) - v ol (q) v inpp = v ih (in) - v il (in) figure 9. ac reference measurement
nb6l14m http://onsemi.com 7 cml driver v cc gnd z o = 50 vt = v cc - 2 v z o = 50 nb6l14m in 50 50 in gnd figure 10. cml interface lvds driver v cc gnd z o = 50 vt = open z o = 50 nb6l14m in 50 50 in gnd figure 11. lvds interface v cc v cc cml driver v cc gnd z o = 50 vt = v cc z o = 50 nb6l14m in 50 50 in gnd v cc figure 12. standard 50 load cml interface differential driver v cc gnd z o = 50 vt = v ref _ac* z o = 50 nb6l14m in 50 50 in gnd v cc figure 13. capacitor-coupled differential interface (vt connected to v refac ) *v refac bypassed to ground with a 0.01 f capacitor single-ended driver v cc gnd z o = 50 vt = v ref _ac* nb6l14m in 50 50 in gnd v cc figure 14. capacitor-coupled single-ended interface (vt connected to v refac ) (open)
nb6l14m http://onsemi.com 8 800 700 600 500 400 300 200 100 0 0123 f out , clock output frequency (ghz) v outpp output voltage amplitude (mv) (typical) figure 15. output voltage amplitude (v outpp ) versus output frequency at ambient temperature (typical) 3.5 v inpp /in in v cc /2 t s v cc /2 t h t pd en /q q v outpp figure 16. en timing diagram q q v cc 16 ma 50 50 figure 17. cml output structure gnd
nb6l14m http://onsemi.com 9 driver device receiver device qd figure 18. typical cml termination for output driver and device evaluation q d v cc 50 50 z = 50 z = 50 ordering information device package shipping ? NB6L14MMNG qfn-16, 3x3 mm (pb-free) 123 units / rail nb6l14mmnr2g qfn-16, 3x3 mm (pb-free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nb6l14m http://onsemi.com 10 package dimensions 16 pin qfn mn suffix case 485g-01 issue c 16x seating plane l d e 0.15 c a a1 e d2 e2 b 1 4 58 12 9 16 13 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. l max condition can not violate 0.2 mm minimum spacing between lead tip and flag ?? ?? ?? b a 0.15 c top view side view bottom view pin 1 location 0.10 c 0.08 c (a3) c 16 x e 16x note 5 0.10 c 0.05 c a b note 3 k 16x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 1.65 1.85 e 3.00 bsc e2 1.65 1.85 e 0.50 bsc k l 0.30 0.50 exposed pad 0.18 typ mm inches scale 10:1 0.50 0.02 0.575 0.022 1.50 0.059 3.25 0.128 0.30 0.012 3.25 0.128 0.30 0.012 exposed pad *for additional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including typicals must be validated for each custom er application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800-282-9855 toll free usa/canada japan : on semiconductor, japan customer focus center ?2-9-1 kamimeguro, meguro-ku, tokyo, japan 153-0051 ? phone : 81-3-5773-3850 nb6l14m/d eclinps max is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : ?literature distribution center for on semiconductor ?p.o. box 5163, denver, colorado 80217 usa ? phone : 303-675-2175 or 800-344-3860 toll free usa/canada ? fax : 303-675-2176 or 800-344-3867 toll free usa/canada ? email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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