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general description the max2390?ax2393/max2396/max2400/max2401 (referred to as the ?ax2390 family? fully integrated direct-conversion receiver ics are designed for w-cdma and td-scdma applications. the max2390 family of receiver ics have over 90db of dynamic gain control, and typical noise figure of 2.7db referred to lna input. each receiver consists of an ultra- low-current low-noise amplifier (lna) with on-chip output matching and a two-step gain control. the zero-if demodulator has a differential circuit topology for mini- mum lo leakage to receiver? input. the channel selec- tivity is done completely in the baseband section of the receiver with an on-chip lowpass filter. the agc section has over 50db of gain-control range. lo quadrature generation is done on-chip through a divide-by-2 prescaler. the dc offset cancellation in the i/q baseband channels is done fully on-chip using a dc servo loop. to quickly correct for large dc offset transients in minimal time, very fast settling time is obtained by optimization of the dc-offset-cancellation circuit? time constant. t he max2390 family includes a 3-wire serial bus for con- figuring the different receiver modes. they also include a shdn pin for full device shutdown. the receivers are fabricated using an advanced high-frequency sige bicmos process. the ics operate from a single +2.7v to +3.3v supply and are housed in a small 28-pin leadless qfn-ep and thin qfn-ep packages (5mm x 5mm). applications features ? fully monolithic direct-conversion receivers ? eliminate external if saw + if agc + i/q demod ? meet all 3gpp receiver? standard requirements with at least 3db margin on eb/no ? operate from a +2.7v to +3.3v single supply ? over 90db of rf+ baseband gain-control range ? channel selectivity over 40db ? receiver current consumption 32ma ? on-chip dc offset cancellation ? compatible with various cmos logic levels max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers ________________________________________________________________ maxim integrated products 1 ordering information/selector guide 19-2754; rev 2; 11/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available * ep = exposed paddle. + denotes lead-free package. part temp range pin-package application chip rate (mcps) rf band (mhz) synthesizer max2390 eti -40? to +85? 28 thin qfn-ep* w-cdma band ii 3.84 1930 to 1990 on-chip max2391 eti -40? to +85? 28 thin qfn-ep* imt2000/umts 3.84 2110 to 2170 on-chip max2391eti+ -40? to +85? 28 thin qfn-ep* imt2000/umts 3.84 2110 to 2170 on-chip max2392 eti -40? to +85? 28 thin qfn-ep* td-scdma 1.28 2010 to 2025 on-chip max2392eti+ -40? to +85? 28 thin qfn-ep* td-scdma 1.28 2010 to 2025 on-chip max2393 egi -40? to +85? 28 qfn-ep* w-tdd/td-scdma 3.84 or 1.28 1900 to 1920 on-chip max2396 egi -40? to +85? 28 qfn-ep* imt2000/umts 3.84 2110 to 2170 external max2400 eti -40? to +85? 28 thin qfn-ep* w-cdma band ii 3.84 1930 to 1990 external max2401 eti -40? to +85? 28 thin qfn-ep* w-cdma band iii 3.84 1805 to 1880 on-chip max2401eti+ -40? to +85? 28 thin qfn-ep* w-cdma band iii 2.84 1805 to 1880 on-chip pin configurations/ functional diagrams 28 27 26 21 20 19 1 2 3 18 4 17 16 5 6 15 7 25 24 23 22 8910 11 12 13 14 q- q+ agc shdn ld refin v cc v cc rf+ rf- bias v cc g_lna lna_out tank sclk sdata g_mxr i+ i- cs v cc gnd lna_in gnd cp v cc v cc tune max2390?ax2393/ max2401 integer-n pll serial interface /2 lna imt2000 handsets umts handsets w-cdma band ii (pcs) handsets td-scdma handsets w-cdma tdd handsets w-cdma band iii (dcs) handsets pin configurations continued at end of data sheet.
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc = 2.7v to 3.3v, v shdn = v dh (note 1), g_lna = g_mxr = v ih , hgml mode (see table 6), no rf input signals, rf input and output ports are terminated into 50 ? , baseband i and q outputs loaded with 10k ? || 5pf, v agc = 2.2v, t a = -40? to +85?. typical values are for v cc = 2.8v, t a = +25?, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ...........................................................-0.3v to +3.6v all other pins to gnd.................................-0.3v to (v cc + 0.3v) lna_in ...........................................................................+15dbm digital input current .........................................................?0ma digital output open-collector current .................................1ma continuous power dissipation (t a = +70?) 28-pin qfn (derate 20.8mw/? above +70?) ......1666.7mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +160? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units supply voltage v cc 2.7 2.8 3.3 v hgml mode 33 39 hghl mode 34 40 lg mode 29 35 max2391, max2392, max2393, max2400 idle mode 11.5 13 hgml mode 31 38 lg mode 27 34 max2396 idle mode 10.5 12 hgml mode 35 42 hghl mode 36 43 lg mode 31 37 max2390, max2401 idle mode 12 14 ma operating supply current i cc all versions shdn mode 0.5 15 ? 0.3v v agc 2.4v -10 +10 gain-control input bias current i agc v agc 0.3v; v shdn = v dl 3 ? (v cm = 0 in opctrl register) 1.10 1.20 1.30 common-mode output voltage at i and q outputs v cm v i(cm) = (v i+ + v i- ) / 2, v q ( cm ) = (v q+ + v q- ) / 2 (v cm = 1 in opctrl register) 1.30 1.42 1.55 v lock indicator high leakage current pll locked, v ld = v cc (max2390?ax2393, max2401) 0.1 ? lock indicator low sink voltage sinking 100?, pll unlocked (max2390?ax2393, max2401) 0.4 v max2390?ax2393, max2401 1.5 v cc shdn input-logic high v dh max2396/max2400 v cc - 0.5 v cc v shdn input-logic low v dl 0 0.5 v shdn input resistance resistance to gnd 50 k ? caution! esd sensitive device
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers _______________________________________________________________________________________ 3 dc electrical characteristics (continued) (v cc = 2.7v to 3.3v, v shdn = v dh (note 1), g_lna = g_mxr = v ih , hgml mode (see table 6), no rf input signals, rf input and output ports are terminated into 50 ? , baseband i and q outputs loaded with 10k ? || 5pf, v agc = 2.2v, t a = -40? to +85?. typical values are for v cc = 2.8v, t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units idle input-logic high v ih v cc - 0.5 v cc v idle input-logic low v il 0 0.5 v idle input resistance max2396, max2400 only resistance to gnd 50 k ? digital input-logic high v ih 0.7 v dh or 1.2v, whichever is greater v cc digital input-logic low v il 0 0.3 v dh v input-logic high current i ih 1a input-logic low current i il cs , sdata, sclk, g_mxr, g_lna (note 1) -1 ? ac electrical characteristics (devices tested on their respective evaluation kits (ev kits); lna input port is driven with a 50 ? source; lna output port is terminated with 50 ? load, mixer differential input port is driven through a 1:4 impedance balun with a 50 ? source; baseband i/q output differential load = 10k ? || 5pf; reference oscillator input: 19.2mhz (max2390/max2391/max2392/max2393), 26mhz (max2401), 15.36mhz (max2396/max2400); agc is set to result in a 0.3v p-p differential output-voltage swing at the baseband i/q output; registers set to power-up defaults ( table 2); t a = -40? to +85?. typical values are for v cc = 2.8v and t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units lna performance max2391/max2396 2110 2140 2170 max2392 2010 2017 2025 max2393 1900 1910 1920 max2390/max2400 1930 1960 1990 rf frequency range (note 2) f rf max2401 1805 1842 1880 mhz signal phase change ? switching between any of the lna modes 8 d eg r ees lna high gain (?glna? g_lna = v ih ) power gain g lna (note 3) 13 16 18 db noise figure nf lna (note 3) 1.5 2.0 db input -1db compression point ip -1db (note 3) -20 -16 dbm max2391/max2396 -4.5 -2.5 max2392/max2393 -6 -4 3rd-order input intercept point (note 4) iip3 lna max2390/max2400/max2401 -7 -4 dbm input return loss db[s11] on ev kit, externally matched to 50 ? -14 db output return loss db[s22] on ev kit, internally matched to 50 ? -14 db reverse isolation db[s12] on ev kit -35 db lna low gain (g_lna = v il ) power gain g lna (note 3) -12 -8.0 -5 db noise figure nf lna (note 3) 18 22 db input -1db compression point ip-1db (note 3) -6 -3 dbm
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers 4 _______________________________________________________________________________________ ac electrical characteristics (continued) (devices tested on their respective evaluation kits (ev kits); lna input port is driven with a 50 ? source; lna output port is terminated with 50 ? load, mixer differential input port is driven through a 1:4 impedance balun with a 50 ? source; baseband i/q output differential load = 10k ? || 5pf; reference oscillator input: 19.2mhz (max2390/max2391/max2392/max2393), 26mhz (max2401), 15.36mhz (max2396/max2400); agc is set to result in a 0.3v p-p differential output-voltage swing at the baseband i/q output; registers set to power-up defaults ( table 2); t a = -40? to +85?. typical values are for v cc = 2.8v and t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units input return loss db[s11] on ev kit, externally matched to 50 ? -11 db output return loss db[s22] on ev kit, internally matched to 50 ? -11 db reverse isolation db[s12] on ev kit -30 db zero-if demodulator performance (rf+/rf- to baseband i and q outputs) hgml mode, v agc = 2.2v 80 86 voltage gain (note 5) av mg or lg mode, v agc = 2.2v 68 76 db baseband gain-control range ? av v agc = 0.3v to 2.4v (note 3) 53 60 db baseband gain-control slope dav/dv v agc = 0.3v to 2.4v (note 3) 25 29 33 db/v max2391/max2392/ max2393/max2396 10.5 14 hgml or hghl mode, v agc 1.8v max2390/max2400/ max2401 9.5 13 dsb noise figure (notes 3, 6) nf mg or lg mode, v agc 1.8v 18.5 25 db hgml mode, v agc = 2.2v (note 7) -5 -1 hghl mode, v agc = 2.2v (note 3, 7) -3.5 0 3rd-order input intercept point iip3 max2390/max2400/max2401 hgml or hghl mode (note 8) -16 dbm input -1db compression point i p-1db lg mode, v agc = 0.5v -23 dbm v agc 1.3v 1.0 1.5 -1db output compression differential voltage o v-1db all modes (note 3) v agc = 0.5v 0.6 1.0 v p-p (max2391/max2396) 190mhz offset; all modes, v agc 0.5v (note 9) +34 (max2390/max2400) 80mhz offset, all modes, v agc 0.5v (note 9) +33 (max2401) 95mhz offset, all modes, v agc 0.5v (note 9) +33 (max2390/max2391/ max2393/max2396/ max2400/max2401) 15mhz offset +25 +33 2nd-order input intercept point iip2 v agc = 2.2v, hgml mode (note 10) (max2392) 4.8mhz offset +25 +33 dbm lo leakage x lo at lna_in, hgml mode, rx band (note 3) -100 -95 dbm i/q gain imbalance | ? g i/q | all modes, v agc = 0.5v to 2.2v 0.2 1.5 db
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers _______________________________________________________________________________________ 5 ac electrical characteristics (continued) (devices tested on their respective evaluation kits (ev kits); lna input port is driven with a 50 ? source; lna output port is terminated with 50 ? load, mixer differential input port is driven through a 1:4 impedance balun with a 50 ? source; baseband i/q output differential load = 10k ? || 5pf; reference oscillator input: 19.2mhz (max2390/max2391/max2392/max2393), 26mhz (max2401), 15.36mhz (max2396/max2400); agc is set to result in a 0.3v p-p differential output-voltage swing at the baseband i/q output; registers set to power-up defaults ( table 2); t a = -40? to +85?. typical values are for v cc = 2.8v and t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units i/q quadrature phase imbalance | ? i/q | all modes, v agc = 0.5v to 2.2v 4 d eg r ees max2391/max2392/max2393/max2396 15 error vector magnitude (note 11) evm max2390/max2400/max2401 17 % differential dc offset at i/q baseband output ? dc including dc servo loop; v agc = 2.2v ?5 mv baseband channel response (w-cdma); max2391/max2393/max2396 -3db lowpass corner frequency f -3db 2.4 mhz at 5mhz offset 51 58 at 10mhz offset 59 67 filter attenuation relative to 180khz adb at 15mhz offset 64 75 db passband gain flatness ? a db 100khz to 1.92mhz (note 3) 1.2 1.7 db baseband channel response (w-cdma); max2390/max2400/max2401 max2390/max2400 2.1 -3db lowpass corner frequency f -3db max2401 2.2 mhz at 2.7mhz offset, max2390/max2400 at 2.8mhz offset, max2401 36 56 at 3.5mhz offset, max2390/max2400 at 3.6mhz offset, max2401 50 56 at 5mhz offset 57 65 filter attenuation relative to 180khz adb at 15mhz offset 65 75 db passband gain flatness ? a db 100khz to 1.92mhz (note 3) 1.9 2.5 db baseband channel response (td-scdma); max2392/max2393 -3db lowpass corner frequency f -3db 0.75 mhz at 1.6mhz offset 51 57 at 3.2mhz offset 56 65 filter attenuation relative to 180khz a db at 6.4mhz offset 64 76 db passband gain flatness ? a db 50khz to 0.64mhz (note 3) 1.2 1.7 db
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers 6 _______________________________________________________________________________________ ac electrical characteristics (continued) (devices tested on their respective evaluation kits (ev kits); lna input port is driven with a 50 ? source; lna output port is terminated with 50 ? load, mixer differential input port is driven through a 1:4 impedance balun with a 50 ? source; baseband i/q output differential load = 10k ? || 5pf; reference oscillator input: 19.2mhz (max2390/max2391/max2392/max2393), 26mhz (max2401), 15.36mhz (max2396/max2400); agc is set to result in a 0.3v p-p differential output-voltage swing at the baseband i/q output; registers set to power-up defaults ( table 2); t a = -40? to +85?. typical values are for v cc = 2.8v and t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units on-chip vco max2391/max2396 4220 4340 max2392 4020 4050 max2393 3800 3840 max2390/max2400 3860 3980 vco frequency (vco range is 2x the lo range) f osc max2401 3610 3760 mhz phase noise na t 10mhz offset; locked (note 3) -139 -133 dbc/hz pulling from idle mode to on mode (note 3) 0.5 1 mhz p-p pushing v cc stepped 3.3v to 2.7v (note 3) 13 mhz/v vco interface to external synthesizer (max2396/max2400) m ax 2396 130 300 vco tuning gain k vco refer r ed to the v c o fr eq uency ( 2x rflo) m ax 2400 100 270 mhz/v max2396 1406.67 1426.67 1446.67 vco output frequency output to synthesizer is f vco / 3 = 2f rflo / 3 max2400 1286.67 1306.67 1326.67 mhz vco output differential voltage (note 12) 180 mv p-p vco tuning voltage range v tune 0.4 2.3 v integer-n rf synthesizer (max2390?ax2393, max2401) main pll integer division ratio 15- b i t r eg i ster ( 64/65 d ual - m od ul us p r escal er ) , f c om p = 200kh z 4032 10700 32767 reference frequency range f ref 10 19.2 40 mhz refdiv reference-divider ratio 9-bit register 16 96 511 charge-pump output current (sink or source) i cp config:cp1 = 1, config:cp0 = 1, v cpout = v cc / 2 2.0 2.5 3.0 ma charge-pump leakage current i l_cp 10 na system timing turn-on time including dc offset cancellation t on from idle mode to on mode vga set to maximum gain with -40dbm signal at demodulator input (note 3) 30 60 ? 3-wire serial interface timing data to clock setup t cs per timing diagram 20 ns data to clock hold time t ch per timing diagram 10 ns clock pulse-width high t cwh per timing diagram 20 ns clock pulse-width low t cwl per timing diagram 20 ns clock to load enable/setup time t es per timing diagram 20 ns clock frequency 20 mhz note 1: logic thresholds track v shdn . this allows the digital interface to operate with logic levels from 1.2v to v cc . note 2: all min and max specifications are measured over this frequency range. note 3: guaranteed by design and characterization.
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers _______________________________________________________________________________________ 7 ac electrical characteristics (continued) (devices tested on their respective evaluation kits (ev kits); lna input port is driven with a 50 ? source; lna output port is terminated with 50 ? load, mixer differential input port is driven through a 1:4 impedance balun with a 50 ? source; baseband i/q output differential load = 10k ? || 5pf; reference oscillator input: 19.2mhz (max2390/max2391/max2392/max2393), 26mhz (max2401), 15.36mhz (max2396/max2400); agc is set to result in a 0.3v p-p differential output-voltage swing at the baseband i/q output; registers set to power-up defaults ( table 2); t a = -40? to +85?. typical values are for v cc = 2.8v and t a = +25?, unless otherwise noted.) note 4: max2391/max2396 : tones at 2025.0mhz and 1930.0mhz (-28dbm/tone); receiver tuned for input rf of 2120.0mhz. max2392 : tones at 2020.6mhz and 2023.8mhz (-35dbm/tone); receiver tuned for input rf of 2017.4mhz. max2393 :t ones at 1910.0mhz and 1920.0mhz (-35dbm/tone); receiver tuned for input rf of 1900.0mhz. max2390/max2400 :t ones at 1963.5mhz and 1965.9mhz (-35dbm/tone); receiver tuned for input rf of 1960.0mhz. max2401 : tones at 1846mhz and 1848.4mhz (-35dbm/tone); receiver tuned for input rf of 1842.4mhz. note 5: voltage gain defined as the differential baseband rms i or q output voltage, measured across the 10k ? load, divided by the rms differential input voltage at rf+/rf-. note 6: nf is constant or flattens out for agc voltage 1.75v. note 7: max2391/max2396 : tones at 2150.0mhz and 2160.18mhz (-35dbm/tone); receiver tuned for input rf of 2140mhz. max2392 : tones at 2020.6mhz and 2023.98mhz (-35dbm/tone); receiver tuned for input rf of 2017.4mhz. max2393 : tones at 1910.0mhz and 1919.82mhz (-35dbm/tone); receiver tuned for input rf of 1900.0mhz. max2390/max2400 : tones at 1970.0mhz and 1980.18mhz (-35dbm/tone); receiver tuned for input rf of 1960.0mhz. max2401 : tones at 1852.4mhz and 1862.58mhz (-35dbm/tone); receiver tuned for input rf of 1842.4mhz. measure im3 product at 180khz. note 8: max2390/max2400 : tones at 1963.5mhz and 1965.9mhz (-35dbm/tone); receiver tuned for input rf of 1960.0mhz, im3 at 1.1mhz baseband. max2401 : tones at 1846mhz and 1848.4mhz (-35dbm/tone); receiver tuned for input rf of 1842.4mhz. im3 at 1.2 mhz baseband. note 9: max2391/max2396 : tones at 1950.0mhz and 1950.18mhz (-35dbm/tone); receiver tuned for input rf of 2140mhz. max2390/max2400 : tones at 1880.0mhz and 1880.18mhz (-35dbm/tone); receiver tuned for input rf of 1960.0mhz. max2401 : tones at 1747.4mhz and 1747.58mhz (-35dbm/tone); receive tuned for input rf of 1842.4mhz. measure im2 product at 180khz. note 10: max2391/max2396 : tones at 2155.0mhz and 2155.18mhz (-35dbm/tone); receiver tuned for input rf of 2140mhz. max2392 : tones at 2022.2mhz and 2022.38mhz (-35dbm/tone); receiver tuned for input rf of 2017.4mhz. max2393 : tones at 1915.0mhz and 1915.18mhz (-35dbm/tone); receiver tuned for input rf of 1900.0mhz. max2390/max2400 : tones at 1975.0mhz and 1975.18mhz (-35dbm/tone); receiver tuned for input rf of 1960.0mhz. max2401 : tones at 1857.4mhz and 1857.58mhz (-35dbm/tone); receiver tuned for input rf of 1842.4mhz. measure im2 product at 180khz. note 11: the receiver is tested using the dl reference measurement channel (12.2kbps) as specified in subclause c.3.1 in the 3gpp 25.101 standard document. note 12: i/q differential output load impedance is 5k ? minimum (10k ? typical) in parallel with 5pf. timing diagram sdata bit 1 bit 2 bit 15 3-wire serial interface timing bit 16 bit 23 t cwh t cwl t ch t cs t es bit 24 sclk cs note: data shifted on rising edge of clock data is shifted in bit 1 first as defined in the pll bit register.
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers 8 _______________________________________________________________________________________ max2390 typical operating characteristics (max2390 ev kit, v cc = 2.8v, hgml mode (see table 6), f rf = 1960mhz, t a = +25?, unless otherwise noted.) supply current vs. supply voltage max2390 toc01 v cc (v) i cc (ma) 3.2 3.1 2.8 2.9 3.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 0 2.7 3.3 t a = -40 c t a = +25 c t a = +85 c idle supply current vs. supply voltage lg mode max2390 toc02 v cc (v) i cc (ma) 3.2 3.1 2.8 2.9 3.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 0 2.7 3.3 t a = -40 c t a = +25 c t a = +85 c idle lna |s 11 | and |s 22 | vs. frequency max2390 toc03 frequency (mhz) |s 11 |, |s 22 | (db) 1980 1970 1960 1950 1940 -15.0 -10.0 -5.0 0 -20.0 1930 1990 |s 22 |, lg |s 11 |, lg |s 22 |, hg |s 11 |, hg lna |s 21 | and |s 12 | vs. frequency max2390 toc04 frequency (mhz) |s 21 | (db) |s 12 | (db) 1980 1970 1960 1950 1940 -5.0 0 5.0 10.0 15.0 20.0 -10.0 1930 1990 |s 12 |, hg |s 21 |, lg |s 12 |, lg |s 21 |, hg -38 -36 -34 -32 -30 -28 -26 -40 lna in-band iip3 vs. supply voltage max2390 toc05 v cc (v) iip3 (dbm) 3.2 3.1 3.0 2.9 2.8 -4.0 -2.0 0 2.0 4.0 6.0 8.0 -6.0 2.7 3.3 lg hg t a = +85 c t a = -40 c t a = +25 c lna gain and nf vs. frequency hg mode max2390 toc06 frequency (mhz) gain (db) nf (db) 1980 1970 1960 1950 1940 11 12 13 14 15 16 10 1.5 2.0 2.5 3.0 3.5 4.0 1.0 1930 1990 gain, -40 c gain, +25 c gain, +85 c nf, +85 c nf, +25 c nf, -45 c vco f osc and k vco vs. v tune max2390 toc07 v tune (v) f osc (mhz) 2.2 2.0 0.6 0.8 1.0 1.4 1.6 1.2 1.8 3750 3800 3850 3900 3950 4000 4050 4100 3700 k vco (mhz/v) 125 150 175 200 225 250 275 300 100 0.4 2.4
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers _______________________________________________________________________________________ 9 max2390 typical operating characteristics (continued) (max2390 ev kit, v cc = 2.8v, hgml mode (see table 6), f rf = 1960mhz, t a = +25?, unless otherwise noted.) -50 -140 11000 100 10 synthesizer closed-loop phase noise -110 -130 -70 -90 -40 -100 -120 -60 -80 max2390 toc08 f offset (khz) phase noise (dbc/hz) f osc = 1960mhz, i cp = 2.5ma -10 -4 -6 -8 0 -2 8 6 4 2 10 0100 200 300 400 500 600 700 max2390 toc09 time ( s) frequency offset (khz) pll settling time 60mhz step 203 s demodulator |s 11 | vs. frequency max2390 toc10 frequency (mhz) |s 11 | (db) 1980 1970 1960 1950 1940 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 -20 1930 1990 hgml lg demodulator gain and nf vs. v agc max2390 toc11 v agc (v) voltage gain (db) noise figure (db) 2.2 2.0 1.6 1.8 0.6 0.8 1.0 1.2 1.4 0.4 10 0 20 30 40 50 60 70 80 90 20 100 18 16 14 12 10 8 6 0 0.2 2.4 t a = -40 c t a = +25 c t a = +85 c cascaded gain and nf vs. v agc max2390 toc12a v agc (v) voltage gain (db) noise figure (db) 2.2 2.0 1.6 1.8 0.6 0.8 1.0 1.2 1.4 0.4 30 20 40 50 60 70 80 90 100 110 120 1 0 2 3 4 5 6 7 8 9 10 0.2 2.4 t a = -40 c t a = +25 c t a = +85 c calculated 1.4db loss at post-lna filter evm = 16.5% rms composite evm w-cdma: pccpch + sch max2390 toc12b baseband channel response vs. frequency max2390 toc13 f offset (mhz) response, relative to 300mhz (db) 10 1 0.1 0.01 -80 -70 -60 -50 -40 -30 -20 -10 0 10 -90 0.001 100 baseband channel group delay vs. frequency max2390 toc14 f offset (mhz) group delay (ns) 2.1 1.9 0.5 0.7 0.9 1.3 1.5 1.1 1.7 500 600 700 800 900 1000 1100 1200 400 0.3 2.3
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers 10 ______________________________________________________________________________________ max2391 typical operating characteristics (max2391 ev kit, v cc = 2.8v, hgml mode (see table 6), f rf = 2140mhz, t a = +25?, unless otherwise noted.) 0 5 10 15 20 25 30 35 40 2.7 2.9 2.8 3.0 t a = -40 c 3.1 3.2 3.3 hgml mode supply current vs. supply voltage max2391 toc15 v cc (v) i cc (ma) t a = +25 c idle t a = +85 c 0 5 10 15 20 25 30 35 40 2.7 2.9 2.8 3.0 t a = -40 c 3.1 3.2 3.3 lg mode supply current vs. supply voltage max2391 toc16 v cc (v) i cc (ma) t a = +25 c idle t a = +85 c -25 -20 -10 -15 -5 0 2110 2130 2120 2140 2150 2160 2170 lna |s 11 | and |s 22 | vs. frequency max2391 toc17 frequency (mhz) |s 11 |, |s 22 | (db) |s 11 |, hg |s 11 |, lg |s 11 |, hg |s 22 |, lg |s 22 |, hg -15 -5 -10 5 0 15 10 20 2110 2130 2140 2120 2150 2160 2170 lna |s 21 | and |s 12 | vs. frequency max2391 toc18 frequency (mhz) |s 21 | (db) -40 -36 -38 -32 -34 -28 -30 -26 |s 12 | (db) |s 21 |, hg |s 12 |, lg |s 12 |, hg |s 21 |, lg -4 0 -2 4 2 8 6 10 2.7 2.9 3.0 2.8 3.1 3.2 3.3 lna in-band iip3 vs. supply voltage max2391 toc19 v cc (v) iip3 (dbm) t a = -40 c lg hg t a = +25 c t a = +85 c lna gain (hg mode) and nf vs. frequency max2391 toc20 frequency (mhz) gain (db) 2160 2150 2120 2130 2140 11 12 13 14 15 16 17 18 10 nf (db) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 2110 2170 t a = -40 c t a = +25 c t a = +85 c vco f osc vs. v tune max2391 toc21 v tune (v) f osc (mhz) 2.2 2.0 1.6 1.8 0.8 1.0 1.2 1.4 0.6 4000 4050 4100 4150 4200 4250 4300 4350 4400 4450 3950 125 150 175 200 225 250 275 300 325 350 100 0.4 2.4 k vco (mhz/v)
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers ______________________________________________________________________________________ 11 -50 -140 1100 0 100 10 synthesizer closed-loop phase noise -110 -130 -70 -90 -40 -100 -120 -60 -80 max2391 toc22 f offset (khz) phase noise (dbc/hz) f osc = 2140mhz, i cp = 2.5ma -10 -4 -6 -8 0 -2 8 6 4 2 10 0100 200 300 400 500 600 700 max2391 toc23 time ( s) frequency offset (khz) pll settling time 60mhz step 203 s -20 -14 -16 -18 -12 -10 -8 -6 -4 -2 0 2110 2130 2120 2140 2150 2160 2170 demodulator |s 11 | vs. frequency max2391 toc24 frequency (mhz) |s 11 | (db) lg hg max2391 typical operating characteristics (continued) (max2391 ev kit, v cc = 2.8v, hgml mode (see table 6), f rf = 2140mhz, t a = +25?, unless otherwise noted.) 20 30 90 50 40 60 70 80 100 0.2 0.6 0.8 1.0 0.4 1.2 1.4 2.0 1.8 2.2 1.6 2.4 demodulator gain (hgml mode) and nf vs. v agc max2391 toc25 v agc (v) voltage gain (db) 6 8 20 12 10 14 16 18 22 noise figure (db) t a = +25 c t a = -40 c t a = +85 c 40 50 110 70 60 80 90 100 120 0.2 0.6 0.8 1.0 0.4 1.2 1.4 2.0 1.8 2.2 1.6 2.4 cascaded gain (hgml mode) and nf vs. v agc max2391 toc26 v agc (v) voltage gain (db) 0 1 7 3 2 4 5 6 8 noise figure (db) t a = +25 c t a = -40 c t a = +85 c = calculated with 2db loss at post-lna filter evm = 15% rms composite evm w-cdma: pccpch + sch max2391 toc27 +10 -90 0.003 30 10 0.1 1 0.01 baseband channel frequency response max2391 toc28 frequency (mhz) loss (db) -80 -70 -60 -50 -40 -30 -20 -10 0 300 400 350 500 450 600 550 650 750 700 800 0.3 0.7 0.9 1.1 0.5 1.3 1.5 1.7 2.1 1.9 2.3 baseband channel group delay vs. frequency max2391 toc29 f offset (mhz) group delay (ns)
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers 12 ______________________________________________________________________________________ 0 5 10 15 20 25 30 35 40 2.7 2.9 2.8 3.0 t a = -40 c 3.1 3.2 3.3 hgml mode supply current vs. supply voltage max2392 toc30 v cc (v) i cc (ma) t a = +25 c idle t a = +85 c 0 5 10 15 20 25 30 35 40 2.7 2.9 2.8 3.0 t a = -40 c 3.1 3.2 3.3 lg mode supply current vs. supply voltage max2392 toc31 v cc (v) i cc (ma) t a = +25 c idle t a = +85 c max2392 typical operating characteristics (max2392 ev kit, v cc = 2.8v, hgml mode (see table 6), f rf = 2017mhz, t a = +25?, unless otherwise noted.) -4 0 -2 4 2 8 6 10 2.7 2.9 3.0 2.8 3.1 3.2 3.3 lna in-band iip3 vs. supply voltage max2392 toc34 v cc (v) iip3 (dbm) t a = -40 c lg hg t a = +25 c t a = +85 c lna gain (hg mode) and nf vs. frequency max2392 toc35 frequency (mhz) gain (db) 2022.5 2020.0 2012.5 2015.0 2017.5 11 12 13 14 15 16 17 18 10 nf (db) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 2010.0 2025.0 t a = -40 c t a = +25 c t a = +85 c -20 -14 -16 -18 -12 -10 -8 -6 -4 -2 0 2010.0 2015.0 2012.5 2017.5 2020.0 2022.5 2025.0 max2392 toc32 lna |s 11 | and |s 22 | vs. frequency frequency (mhz) |s 11 |, |s 22 | (db) |s 11 |, hg |s 11 |, lg |s 22 |, lg |s 22 |, hg -15 -5 -10 5 0 15 10 20 2010.0 2015.0 2017.5 2012.5 2020.0 2022.5 2025.0 max2392 toc33 -40 -36 -38 -32 -34 -28 -30 -26 lna |s 21 | and |s 12 | vs. frequency frequency (mhz) |s 21 | (db) |s 12 | (db) |s 21 |, hg |s 12 |, lg |s 12 |, hg |s 21 |, lg
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers ______________________________________________________________________________________ 13 max2392 toc36 v tune (v) f osc (mhz) 2.2 2.0 0.6 0.8 1.0 1.4 1.6 1.2 1.8 3800 3850 3900 3950 4000 4050 4100 4150 3750 k vco (mhz/v) 100 125 150 175 200 225 250 275 75 0.4 2.4 vco f osc and k vco vs. v tune -50 -140 1 1000 100 10 synthesizer closed-loop phase noise -110 -130 -70 -90 -40 -100 -120 -60 -80 max2392 toc37 f offset (khz) phase noise (dbc/hz) f osc = 2017.5mhz, i cp = 2.5ma -10 -4 -6 -8 0 -2 +8 +6 +4 +2 +10 0 100 200 300 400 500 600 700 max2392 toc38 time ( s) frequency offset (khz) pll settling time 15mhz step 130 s -20 -14 -16 -18 -12 -10 -8 -6 -4 -2 0 2010.0 2015.0 2012.5 2017.5 2020.0 2022.5 2025.0 demodulator |s 11 | vs. frequency max2392 toc39 frequency (mhz) |s 11 | (db) lg hgml 20 30 90 50 40 60 70 80 100 0.2 0.6 0.8 1.0 0.4 1.2 1.4 2.0 1.8 2.2 1.6 2.4 demodulator gain (hgml mode) and nf vs. v agc max2392 toc40 v agc (v) voltage gain (db) 6 8 20 12 10 14 16 18 22 noise figure (db) t a = +25 c t a = -40 c t a = +85 c 40 50 110 70 60 80 90 100 120 0.2 0.6 0.8 1.0 0.4 1.2 1.4 2.0 1.8 2.2 1.6 2.4 cascaded gain (hgml mode) and nf vs. v agc max2392 toc41 v agc (v) voltage gain (db) 0 1 7 3 2 4 5 6 8 noise figure (db) t a = +25 c t a = -40 c t a = +85 c = calculated with 2db loss at post-lna filter max2392 typical operating characteristics (continued) (max2392 ev kit, v cc = 2.8v, hgml mode (see table 6), f rf = 2017mhz, t a = +25?, unless otherwise noted.) +10 -90 0.003 3 0.1 1 0.01 baseband channel frequency response max2392 toc42 frequency (mhz) loss (db) -80 -70 -60 -50 -40 -30 -20 -10 0 baseband channel group delay vs. frequency max2392 toc43 f offset (mhz) group delay (ns) 0.65 0.60 0.55 0.50 0.45 0.40 0.35 1200 1400 1600 1800 2000 2200 2400 1000 0.30 0.70
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers 14 ______________________________________________________________________________________ 0 5 10 15 20 25 30 35 40 2.7 2.9 2.8 3.0 t a = -40 c 3.1 3.2 3.3 lg mode supply current vs. supply voltage max2393 toc44 v cc (v) i cc (ma) t a = +25 c idle t a = +85 c 0 5 10 15 20 25 30 35 40 2.7 2.9 2.8 3.0 t a = -40 c 3.1 3.2 3.3 hgml mode supply current vs. supply voltage max2393 toc45 v cc (v) i cc (ma) idle t a = +85 c t a = +25 c -25 -20 -10 -15 -5 0 lna |s 11 | and |s 22 | vs. frequency max2393 toc46 frequency (mhz) |s 11 |, |s 22 | (db) 1900 1910 1905 1915 1920 |s 11 |, hg |s 11 |, lg |s 22 |, lg |s 22 |, hg -15 -5 -10 5 0 15 10 20 lna |s 21 | and |s 12 | vs. frequency max2393 toc47 frequency (mhz) |s 21 | (db) -40 -36 -38 -32 -34 -28 -30 -26 |s 12 | (db) 1900 1905 1910 1915 1920 |s 12 |, hg |s 12 |, lg |s 21 |, hg |s 21 |, lg -4 0 -2 4 2 8 6 10 2.7 2.9 3.0 2.8 3.1 3.2 3.3 lna in-band iip3 vs. supply voltage max2393 toc48 v cc (v) iip3 (dbm) t a = -40 c lg hg t a = +25 c t a = +85 c lna gain (hg mode) and nf vs. frequency max2393 toc49 frequency (mhz) gain (db) 1915 1910 1905 11 12 13 14 15 16 17 18 10 nf (db) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 1900 1920 t a = -40 c t a = +25 c t a = +85 c vco f osc and k vco vs. v tune max2393 toc50 v tune (v) f osc (mhz) 2.2 2.0 0.6 0.8 1.0 1.4 1.6 1.2 1.8 3600 3650 3700 3750 3800 3850 3900 3950 3550 k vco (mhz/v) 100 125 150 175 200 225 250 275 75 0.4 2.4 max2393 typical operating characteristics (max2393 ev kit, v cc = 2.8v, hgml mode (see table 6), f rf = 1910mhz, t a = +25?, unless otherwise noted.)
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers ______________________________________________________________________________________ 15 -50 -140 1 1000 100 10 synthesizer closed-loop phase noise -110 -130 -70 -90 -40 -100 -120 -60 -80 max2393 toc51 f offset (khz) phase noise (dbc/hz) f osc = 1910mhz, i cp = 2.5ma -10 -4 -6 -8 0 -2 8 6 4 2 10 0 100 200 300 400 500 600 700 max2393 toc52 time ( s) frequency offset (khz) pll settling time 20mhz step 117 s demodulator |s 11 | vs. frequency max2393 toc53 frequency (mhz) |s 11 | (db) -25 -20 -15 -10 -5 0 1900 1905 1910 1915 1920 hg lg 20 30 90 50 40 60 70 80 100 0.2 0.6 0.8 1.0 0.4 1.2 1.4 2.0 1.8 2.2 1.6 2.4 demodulator gain (hgml mode) and nf vs. v agc max2393 toc54 v agc (v) voltage gain (db) 6 8 20 12 10 14 16 18 22 noise figure (db) t a = +25 c t a = -40 c t a = +85 c 40 50 110 70 60 80 90 100 120 0.2 0.6 0.8 1.0 0.4 1.2 1.4 2.0 1.8 2.2 1.6 2.4 cascaded gain (hgml mode) and nf vs. v agc max2393 toc55 v agc (v) voltage gain (db) 0 1 7 3 2 4 5 6 8 noise figure (db) t a = +25 c t a = -40 c t a = +85 c x = calculated with 2db loss at post-lna filter x x x x x x evm = 15% rms composite evm w-cdma: pccpch + sch max2393 toc56 +10 -90 0.003 30 10 0.1 1 0.01 baseband channel frequency response max2393 toc57 frequency (mhz) loss (db) -80 -70 -60 -50 -40 -30 -20 -10 0 1.28mcps 3.84mcps 500 400 300 600 700 800 0.3 0.7 0.9 1.1 0.5 1.3 1.5 1.7 2.1 1.9 2.3 baseband channel group delay vs. frequency 3.84mcps max2393 toc58 f offset (mhz) group delay (ns) baseband channel group delay vs. frequency 1.28mcps max2393 toc59 f offset (mhz) group delay (ns) 0.7 0.6 0.5 0.4 1400 1600 1800 2000 2200 2400 1200 0.3 0.8 max2393 typical operating characteristics (continued) (max2393 ev kit, v cc = 2.8v, hgml mode (see table 6), f rf = 1910mhz, t a = +25?, unless otherwise noted.)
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers 16 ______________________________________________________________________________________ max2396 typical operating characteristics (max2396 ev kit, v cc = 2.8v, hgml mode (see table 6), f rf = 2140mhz, t a = +25?, unless otherwise noted.) 0 5 10 15 20 25 30 35 40 2.7 2.9 2.8 3.0 3.1 3.2 3.3 hghl mode supply current vs. supply voltage max2396 toc60 v cc (v) i cc (ma) t a = -40 c t a = +25 c t a = +85 c idle 0 5 10 15 20 25 30 35 40 2.7 2.9 2.8 3.0 3.1 3.2 3.3 lg mode supply current vs. supply voltage max2396 toc61 v cc (v) i cc (ma) t a = -40 c t a = +25 c t a = +85 c idle -4 0 -2 4 2 8 6 10 2.7 2.9 3.0 2.8 3.1 3.2 3.3 lna in-band iip3 vs. supply voltage max2396 toc62 v cc (v) iip3 (dbm) t a = -40 c lg hg t a = +25 c t a = +85 c lna gain and nf (hg mode) vs. frequency max2396 toc63 frequency (mhz) gain (db) 2160 2150 2120 2130 2140 11 12 13 14 15 16 17 18 10 nf (db) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 2110 2170 t a = -40 c t a = +25 c t a = +85 c vco f osc and k vco vs.v tune v cc (v) f osc (mhz) 2.2 2.0 1.6 1.8 0.8 1.0 1.2 1.4 0.6 4000 4050 4100 4150 4200 4250 4300 4350 4400 4450 3950 125 150 175 200 225 250 275 300 325 350 100 0.4 2.4 k vco (mhz/v) max2396 toc64 t a = -40 c t a = +25 c t a = +85 c 20 30 90 50 40 60 70 80 100 0.2 0.6 0.8 1.0 0.4 1.2 1.4 2.0 1.8 2.2 1.6 2.4 demodulator gain and nf vs. v agc max2396 toc65 v agc (v) voltage gain (db) 6 8 20 12 10 14 16 18 22 noise figure (db) t a = +25 c t a = -40 c t a = +85 c 40 50 110 70 60 80 90 100 120 0.2 0.6 0.8 1.0 0.4 1.2 1.4 2.0 1.8 2.2 1.6 2.4 cascaded gain and nf vs. v agc max2396 toc66 v agc (v) voltage gain (db) 0 1 7 3 2 4 5 6 8 noise figure (db) t a = +25 c t a = -40 c t a = +85 c = calculated with 2db loss at post-lna filter evm = 15% rms composite evm w-cdma: pccpch + sch max2396 toc67 +10 -90 0.003 30 10 0.1 1 0.01 frequency response max2396 toc68 frequency (mhz) loss (db) -80 -70 -60 -50 -40 -30 -20 -10 0
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers ______________________________________________________________________________________ 17 supply current vs. supply voltage hgml mode max2400 toc69 v cc (v) i cc (ma) 3.2 3.1 2.8 2.9 3.0 5 10 15 20 25 30 35 40 0 2.7 3.3 t a = -40 c t a = +25 c t a = +85 c idle supply current vs. supply voltage lg mode max2400 toc70 v cc (v) i cc (ma) 3.2 3.1 2.8 2.9 3.0 5 10 15 20 25 30 35 40 0 2.7 3.3 idle t a = -40 c t a = +25 c t a = +85 c lna |s 11 | and |s 22 | vs. frequency max2400 toc71 frequency (mhz) |s 11 |, |s 22 | (db) 1980 1970 1960 1950 1940 -15.0 -10.0 -5.0 0 -20.0 1930 1990 |s 22 |, lg |s 11 |, lg |s 22 |, hg |s 11 |, hg lna |s 21 | and |s 12 | vs. frequency max2400 toc72 frequency (mhz) |s 21 | (db) |s 12 | (db) 1980 1970 1960 1950 1940 -5.0 0 5.0 10.0 15.0 20.0 -10.0 1930 1990 |s 12 |, hg |s 21 |, lg |s 12 |, lg |s 21 |, hg -38 -36 -34 -32 -30 -28 -26 -40 lna in-band iip3 vs. supply voltage max2400 toc73 v cc (v) iip3 (dbm) 3.2 3.1 3.0 2.9 2.8 -4.0 -2.0 0 2.0 4.0 6.0 8.0 -6.0 2.7 3.3 lg hg t a = +85 c t a = -40 c t a = +25 c lna gain and nf vs. frequency hg mode max2400 toc74 frequency (mhz) gain (db) nf (db) 1980 1970 1960 1950 1940 11 12 13 14 15 16 10 1.5 2.0 2.5 3.0 3.5 4.0 1.0 1930 1990 gain, -40 c gain, +25 c gain, +85 c nf, +85 c nf, +25 c nf, -45 c vco f osc and k vco vs. v tune max2400 toc75 v tune (v) f osc (mhz) 2.2 2.0 0.6 0.8 1.0 1.4 1.6 1.2 1.8 3750 3800 3850 3900 3950 4000 4050 4100 3700 k vco (mhz/v) 125 150 175 200 225 250 275 300 100 0.4 2.4 demodulator |s 11 | vs. frequency max2400 toc76 frequency (mhz) |s 11 | (db) 1980 1970 1960 1950 1940 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 -20 1930 1990 hgml lg max2400 typical operating characteristics (max2400 ev kit, v cc = 2.8v, hgml mode (see table 6), f rf = 1960mhz, t a = +25?, unless otherwise noted.)
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers 18 ______________________________________________________________________________________ demodulator gain and nf vs. v agc max2400 toc77 v agc (v) voltage gain (db) noise figure (db) 2.2 2.0 1.6 1.8 0.6 0.8 1.0 1.2 1.4 0.4 10 0 20 30 40 50 60 70 80 90 20 100 18 16 14 12 10 8 6 0 0.2 2.4 t a = -40 c t a = +25 c t a = +85 c cascaded gain and nf vs. v agc max2400 toc78 v agc (v) voltage gain (db) noise figure (db) 2.2 2.0 1.6 1.8 0.6 0.8 1.0 1.2 1.4 0.4 30 20 40 50 60 70 80 90 100 110 120 1 0 2 3 4 5 6 7 8 9 10 0.2 2.4 t a = -40 c t a = +25 c t a = +85 c calculated 1.4db loss at post-lna filter evm = 16.5% rms composite evm w-cdma: pccpch + sch max2400 toc79 baseband channel response vs. frequency max2400 toc80 f offset (mhz) response, relative to 300mhz (db) 10 1 0.1 0.01 -80 -70 -60 -50 -40 -30 -20 -10 0 10 -90 0.001 100 baseband channel group delay vs. frequency max2400 toc81 f offset (mhz) group delay (ns) 2.1 1.9 0.5 0.7 0.9 1.3 1.5 1.1 1.7 500 600 700 800 900 1000 1100 1200 400 0.3 2.3 max2400 typical operating characteristics (continued) (max2400 ev kit, v cc = 2.8v, hgml mode (see table 6), f rf = 1960mhz, t a = +25?, unless otherwise noted.)
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers ______________________________________________________________________________________ 19 0 5 10 15 20 25 30 35 40 2.7 2.9 2.8 3.0 t a = -40 c 3.1 3.2 3.3 hgml mode supply current vs. supply voltage max2401 toc82 v cc (v) i cc (ma) t a = +25 c idle t a = +85 c 0 5 10 15 20 25 30 35 40 2.7 2.9 2.8 3.0 t a = -40 c 3.1 3.2 3.3 lg mode supply current vs. supply voltage max2401 toc83 v cc (v) i cc (ma) t a = +25 c idle t a = +85 c -14 -13 -12 -11 -10 -9 1805 1820 1835 1850 1865 1880 max2401 toc84 lna |s 11 | and |s 22 | vs. frequency frequency (mhz) |s 11 |, |s 22 | (db) |s 11 |, hg |s 11 |, lg |s 22 |, lg |s 22 |, hg -15 -5 -10 5 0 15 10 20 1805 1820 1835 1850 1865 1880 max2401 toc85 -44 -40 -42 -36 -38 -34 lna |s 21 | and |s 12 | vs. frequency frequency (mhz) |s 21 | (db) |s 12 | (db) |s 21 |, hg |s 12 |, lg |s 12 |, hg |s 21 |, lg -6 -2 -4 2 0 6 4 8 2.7 2.9 3.0 2.8 3.1 3.2 3.3 lna in-band iip3 vs. supply voltage max2401 toc86 v cc (v) iip3 (dbm) t a = -40 c lg hg t a = +25 c t a = +85 c lna gain and nf vs. frequency max2401 toc87 frequency (mhz) gain (db) 1865 1835 1850 1820 11 12 13 14 15 16 17 10 nf (db) 1.5 2.0 2.5 3.0 3.5 4.0 4.5 1.0 1805 1880 gain, t a = -40 c nf, t a = +25 c gain, t a = +85 c nf, t a = -45 c gain, t a = +25 c nf, t a = +85 c vco f osc and k vco vs. v tune max2401 toc88 v tune (v) f osc (mhz) 2.2 2.0 0.6 0.8 1.0 1.4 1.6 1.2 1.8 3600 3630 3660 3690 3720 3750 3780 3810 3570 k vco (mhz/v) 70 90 110 130 150 170 190 210 50 0.4 2.4 max2401 typical operating characteristics (max2401 ev kit, v cc = 2.8v, hgml mode (see table 6), f rf = 1842.4mhz, t a = +25?, unless otherwise noted.)
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers 20 ______________________________________________________________________________________ max2401 typical operating characteristics (continued) (max2401 ev kit, v cc = 2.8v, hgml mode (see table 6), f rf = 1842.4mhz, t a = +25?, unless otherwise noted.) -130 1 1000 100 10 synthesizer closed-loop phase noise -100 -120 -80 -60 -90 -110 -70 max2401 toc89 f offset (khz) phase noise (dbc/hz) f osc = 1842.4mhz, i cp = 2.5ma -10 -4 -6 -8 0 -2 8 6 4 2 10 0 100 200 300 400 500 600 700 max2401 toc90 time ( s) frequency offset (khz) pll settling time 60mhz step 203 s demodulator |s 11 | vs. frequency max2401 toc91 frequency (mhz) |s 11 | (db) -24 -21 -18 -15 -12 1805 1820 1835 1865 1880 1850 hgml lg 30 90 50 40 60 70 80 100 0.2 0.6 0.8 1.0 0.4 1.2 1.4 2.0 1.8 2.2 1.6 2.4 demodulator gain and nf vs. v agc max2401 toc92 v agc (v) voltage gain (db) 7 9 13 11 15 17 19 21 noise figure (db) t a = +25 c t a = -40 c t a = +85 c 40 50 110 70 60 80 90 100 120 0.2 0.6 0.8 1.0 0.4 1.2 1.4 2.0 1.8 2.2 1.6 2.4 cascaded gain and nf vs. v agc max2401 toc93 v agc (v) voltage gain (db) 1 2 8 4 3 5 6 7 9 noise figure (db) t a = +25 c t a = -40 c t a = +85 c calculated with 1.4db loss at post-lna filter evm = 16% rms composite evm w-cdma: pccpch + sch max2401 toc94 baseband channel response vs. frequency max2401 toc95 f offset (mhz) response, relative to 300mhz (db) 10 1 0.1 0.01 -80 -70 -60 -50 -40 -30 -20 -10 0 10 -90 0.001 100 baseband channel group delay vs. frequency max2401 toc96 f offset (mhz) group delay (ns) 2.1 1.9 0.5 0.7 0.9 1.3 1.5 1.1 1.7 500 600 700 800 900 1000 1100 1200 400 0.3 2.3
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers ______________________________________________________________________________________ 21 pin description pin name function 1v cc supply pin for i/q mixers. this pin must be bypassed to system ground as close to the pin as possible. the ground vias for the bypass capacitor should not be shared by any other branch. use 100pf for rf bypassing to gnd. 2rf + n oni nver ti ng rf inp ut to z er o- if d em od ul ator ( 200 ? d i ffer enti al n om i nal im p ed ance betw een rf+ and rf- ) 3 rf- inverting rf input to zero-if demodulator (200 ? differential nominal impedance between rf+ and rf-) 4 bias external bias resistor connection 5v cc supply pin for lna. this pin must be bypassed to system ground as close to the pin as possible. the ground vias for the bypass capacitor should not be shared by any other branch. use 100pf for rf bypassing to gnd. 6 g_lna lna gain mode logic-control pin 7 lna_out lna output. internally matched to 50 ? . 8 gnd rf ground return for lna. provide multiple vias to the system ground plane as close to the pin as possible. 9 lna_in lna input. externally matched to 50 ? . see the applications information section for more information. 10 gnd rf vco varactor ground return. provide multiple vias to the system ground plane as close to the pin as possible. 11 v cc supply pin for vco. this pin must be bypassed to system ground as close to the pin as possible. the ground vias for the bypass capacitor should not be shared by any other branch. use 100pf for rf bypassing to gnd. 12 tune rf vco varactor tune input. connect pll loop filter between cp and tune. cp (max2390?ax2393, max2401) high-impedance output of the rf charge pump. the rf pll? loop filter is connected between this pin and tune. 13 lo_out+ (max2396/max2400) vco divide-by-3 noninverting output to synthesizer v cc (max2390?ax2393, max2401) supply pin for synthesizer charge pump. use 100nf for bypassing to gnd. 14 lo_out- (max2396/max2400) vco divide-by-3 inverting output to synthesizer 15 v cc supply pin for on-chip digital circuitry. use 100nf for bypassing to gnd. 16 refin synthesizer reference frequency input. ac-couple to the reference source through 1nf. ld (max2390?ax2393, max2401) open-drain output indicating lock status of the rf pll. it is open drain to wire-or with ld from tx chip. 17 idle (max2396/max2400) idle mode enable. drive idle low to disable all blocks except serial bus, vco, and divide-by-3 prescaler to pll. 18 shdn shutdown logic pin for entire receiver (active low) 19 agc analog input pin controlling the baseband vga gain 20 q + noninverting baseband output for q channel 21 q- inverting baseband output for q channel 22 i- inverting baseband output for i channel 23 i + noninverting baseband output for i channel 24 v cc supply pin for baseband circuitry. use 100nf for bypassing to gnd. 25 cs 3-wire serial bus enable input (active low) 26 g_mxr mixer gain mode logic-control pin 27 sdata 3-wire serial bus data input 28 sclk 3-wire serial bus clock input
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers 22 ______________________________________________________________________________________ 28 27 26 21 20 19 1 2 3 18 4 17 16 5 6 15 7 25 24 23 22 8910 11 12 13 14 q- q+ agc shdn idle refin v cc lo_out- v cc rf+ rf- bias v cc g_lna lna_out tank sclk sdata g_mxr i+ i- cs v cc gnd lna_in gnd lo_out+ v cc tune max2396 max2400 /3 serial interface /2 lna pin configuration/functional diagram for max2396/max2400
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers ______________________________________________________________________________________ 23 w-cdma fdd receiver operating circuit (max2390/max2391/max2401) 28 27 26 21 dac max5383 (6-pin sot) (optional external agc dac, uses 3-wire interface) 20 19 1 2 3 18 4 17 16 5 6 15 7 25 24 23 22 8910 11 12 13 14 q- q+ agc shdn ld refin tcxo 19.2mhz (max2390/max2391) 26mhz (max2401) baseband/dsp v cc v cc rf+ rf- +2.8v +2.8v bias v cc g_lna lna_out tx (from pa) tank sclk sdata g_mxr i+ i- cs v cc gnd lna_in gnd cp v cc v cc tune max2390/max2391 max2401 integer-n pll serial interface /2 lna rx +2.8v +2.8v +2.8v +2.8v dac cs
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers 24 ______________________________________________________________________________________ td-scdma receiver operating circuit (max2392) 28 27 26 21 dac max5383 (6-pin sot) (optional external agc dac, uses 3-wire interface) 20 19 1 2 3 18 4 17 16 5 6 15 7 25 24 23 22 8910 11 12 13 14 q- q+ agc shdn ld refin baseband/dsp v cc v cc v cc rf+ rf- +2.8v bias v cc g_lna lna_out tank sclk sdata g_mxr i+ i- cs v cc gnd lna_in gnd cp v cc v cc tune max2392 integer-n pll serial interface /2 lna rx td- scdma +2.8v +2.8v +2.8v +2.8v dac cs tx td-scdma tx gsm rx gsm tcxo 13.0mhz
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers ______________________________________________________________________________________ 25 w-tdd receiver operating circuit (max2393) 28 27 26 21 dac max5383 (6-pin sot) (optional external agc dac, uses 3-wire interface) 20 19 1 2 3 18 4 17 16 5 6 15 7 25 24 23 22 8910 11 12 13 14 q- q+ agc shdn ld refin baseband/dsp v cc v cc v cc rf+ rf- +2.8v bias v cc g_lna lna_out tank sclk sdata g_mxr i+ i- cs v cc gnd lna_in gnd cp v cc v cc tune max2393 integer-n pll serial interface /2 lna rx tdd +2.8v +2.8v +2.8v +2.8v dac cs tx tdd tcxo 19.2mhz
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers 26 ______________________________________________________________________________________ w-cdma fdd receiver operating circuit (external synthesizer) (max2396/max2400) 28 27 26 21 dac max5383 (6-pin sot) (optional external agc dac, uses 3-wire interface) 20 19 1 2 3 18 4 17 16 5 6 15 7 25 24 23 22 8910 11 12 13 14 q- q+ agc shdn idle refin tcxo 15.36mhz baseband/dsp v cc v cc rf+ rf- +2.8v +2.8v bias v cc g_lna lna_out tx (from pa) tank sclk sdata g_mxr i+ i- cs v cc gnd lna_in gnd lo_out+ lo_out- v cc tune max2396 max2400 /3 serial interface /2 lna rx +2.8v from external pll to external pll +2.8v +2.8v
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers ______________________________________________________________________________________ 27 detailed description with the exception of the analog-input agc, all func- tionality of these direct-conversion receivers can be controlled through the 3-wire serial interface (spi/qspi/microwire compatible). register definition all devices in this family have two programmable 20-bit registers: the configuration register (config) and the control register (opcntrl). the max2391/max2392/ max2393/max2401 have two additional programmable 20-bit registers: the main pll divide register (rfm) and the reference pll divide register (rfr). the 4 least sig- nificant bits of the data sent are the register? address. the 16 most significant bits are used for register data. all registers contain a few don? care bits. these can be either 0 or 1 and do not affect operation. tables 1a and 1b provide a register summary. data is shifted in msb first. when cs is low, data is shifted with the rising edge of the clock. when cs transitions to high, the shift register is latched into the register selected by the con- tents of the address bits. power-up defaults for the four registers are shown in table 2. the rfm register sets the main-frequency divide ratio for the rf pll. the rfr register sets the reference-fre- quency divide ratio. the rf lo frequency can be determined by the following: rf lo frequency = f refin x (rfm / rfr) where f refin is the external input reference frequency for the max2390?ax2393, max2401. the operation control register (opcntrl) and the con- figuration register (config) are used to program the receiver for the appropriate mode of operation. see tables 3 and 4 for the function of each bit. the test register is used to set the receiver in factory testing mode. it should only be programmed at receiver turn-on with the word 0370 (hex) for max2390?ax2393, max2401 and 2370 (hex) for max2396/max2400. power management bias control is distributed among several functional sec- tions and can be controlled to accommodate different power-down modes as shown in table 5. the ic has three bias states: shutdown, idle, and on. shutdown can be asserted by either a hardware control line ( shdn ) or by bit 5 of the operation control register (opctrl. shdn ). when the serial interface is used to shut down the part, an internal linear regulator, with iq 90?, stays functional to keep the serial inter- face operational. use the shdn logic-control pin to bring quiescent current below 10?. register bit set- tings maintain their values after a hard shutdown, pro- vided cs remains high. idle mode disables the lna, i/q mixers, and baseband circuitry, but keeps the serial interface and synthesizer operational, dropping quies- cent current to 11.5ma. the entire receiver is on when shdn is high and opcntrl. shdn and opcntrl. idle bits (max2390?ax2393, max2401) or the idle pin (max2396/max2400) are set to 1; the typical supply current is 32ma. table 1a. register defintion (max2390?ax2393, max2401) msb 20-bit register lsb data 16 bits address 4 bits register name b15 b14 b13 b12 b11 b10 b9 b8 b7 b 6b5b 4b3b2b1b0a3a2a1 a0 rfm x m14 m13 m12 m11 m10 m9 m8 m7 m6 m5 m4 m3 m2 m1 m0 001 1 rfr x x x x x x x r8 r7 r6 r5 r4 r3 r2 r1 r0 011 1 opcntrl x x x x (reserved) (reserved) (reserved) (reserved) rc1 rc0 shdn idle glna lmxr gmxr vcm 101 1 config x x x x (reserved) (reserved) (reserved) (reserved) (reserved) bw_sel dc_cancel_en rf_pll_en vco_en cp1 cp0 lna_en 111 1 microwire is a trademark of national semiconductor corp. spi and qspi are trademarks of motorola, inc.
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers 28 ______________________________________________________________________________________ table 1b. register defintion (max2396/max2400) msb 20-bit register lsb data 16 bits address 4 bits register name b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 a3 a2 a1 a0 opcntrl x x x x (reserved) (reserved) (reserved) (reserved) rc1 rc0 shdn (reserved) glna lmxr gmxr vcm 101 1 config x x x x (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) dc_cancel_en lo_gen_en vco_en (reserved) (reserved) lna_en 111 1 data shifted in msb first. x represents a ?on? care. set all (reserved) bits to 0. table 2. power-up default register settings register address default function 0x29cc (107800 dec )* max2391 0x2768 (10088 dec )* max2392 0x254e (9550 dec )* max2393 rfm 0011 b 0x2648 (9800 dec )* max2390, max2401 rf main-divider count 0x0060 (0096 dec )* max2390/max2391/max2393/max2401 rfr 0111 b 0x0041 (0065 dec )* max2392 rf reference- divider count opctrl 1011 b 03b hex operation control settings config 1111 b 07f hex configuration control settings 0370 hex** max2390?ax2393, max2401 test 0001 b 2370 hex** max2396/max2400 disables test mode data shifted in msb first. x represents a ?on? care. set all (reserved) bits to 0. * 200khz comparison frequency. ** needs to be programmed at receiver turn-on.
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers ______________________________________________________________________________________ 29 table 3. operation control register (opcntrl, address 1011) bit (b0 = lsb) power-up state bit name function b11, b10, b9, b8 0 0 0 0 (reserved) set to zero for normal operation. b7, b6 0 0 rc1, rc0 sets the -3db corner of the highpass filter used for dc offset removal at baseband (only possible when the automatic dc-offset-cancellation bit (config.b5) is disabled): 0 0 = 8.6khz highpass corner 0 1 = 17.2khz highpass corner 1 0 = 100khz highpass corner 1 1 = 1mhz highpass corner b5 1 shdn zero shuts down everything except serial interface and registers, retaining their values. idle for m ax 2390m ax 2393/m ax 2401: z er o s huts d ow n ever ythi ng excep t rf p ll, rf v c o , ser i al i nter face, and r eg i ster s, r etai ni ng thei r val ues. b4 1 (reserved) for m ax 2396/m ax 2400: s et to 1 for nor m al op er ati on. b3 1 glna sets lna operating mode according to the following: 1 = high gain 0 = low gain b2 0 lmxr sets mixer linearity in high-gain mode: 0 = medium linearity 1 = high linearity b1 1 gmxr sets mixer operating mode according to the following: 1 = high gain 0 = low gain b0 1 vcm sets output common-mode voltage for baseband i/q outputs: 0 = 1.2v 1 = 1.42v
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers 30 ______________________________________________________________________________________ table 4. configuration register (config, address 1111) bit power-up state bit name function b11, b10, b9, b8, b7 0 0 0 0 0 (reserved) set to 0 for normal operation. bw_sel for max2393 only: 1 = selects the 3g w-cdma mode for baseband filters. 0 = selects the td-scdma mode for baseband filters. b6 1 (reserved) set to 1 for normal operation. b5 1 dc_cancel_en 0 = disables the automatic dc-offset-cancellation circuit. rf_pll_en for max2390?ax2393/max2401: 0 = disables the rf pll + lo generation circuit. b4 1 lo_gen_en for max2396/max2400: 0 = disables the lo generation circuit. b3 1 vco_en 0 = disables the vco. cp1, cp0 for max2390?ax2393/max2401: a 2-bit word sets the rf charge-pump current as follows: 0 0 = 1000? 0 1 = 1500? 1 0 = 2000? 1 1 = 2500? b2, b1 1 1 (reserved) for max2396/max2400: set to 11 for normal operation. b0 1 lna_en 0 = disables on-chip lna. set to zero for external lna.
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers ______________________________________________________________________________________ 31 table 5. power-down modes logic power-down modes comments shdn pin shdn bit idle bit serial interface lna + i/q mixers + bb circuitry rf vco + rf pll + lo generation shdn pin is high, shdn bit is zero. all blocks are off except serial bus and registers, which retain their values; a low on shdn pin overrides shdn bit. 10 on shutdown shdn pin is low. all blocks are off; registers retain their preshutdown values. 0x x off off off idle idle bit (opctrl.b4) is zero. all blocks are off except rf pll, rf vco, serial bus, and registers, which retain their values. 110 on off on table 6. operational modes external control pins/ opctrl register bits mixer lna gmxr glna mode* lmxr (bit) (pin) (bit) (pin) (bit) corresponding lna mode corresponding mixer mode hgml 0 1 1 1 1 high gain high gain, medium linearity hghl 1 1 1 1 1 high gain high gain, high linearity 10 mg x 0x 11 high gain low gain 1010 lg x 0x0x low gain low gain * definitions: hgml: high gain, medium linearity hghl: high gain, high linearity mg: medium gain lg: low gain
max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers 32 ______________________________________________________________________________________ applications information lna and rfin matching the lna requires a simple two-element 50 ? matching network at the input. use the layout and matching net- work provided in the ev kit as a reference. the lna input is internally biased, so be sure to use a series 100pf dc blocking capacitor in front of the matching network. the lna offers a 23db gain step with less than 10 degrees phase change, selectable with either a dedi- cated logic pin (g_lna) or bit 3 in the operation control register (opctrl.glna). lna output matching is provided on-chip, offering bet- ter than 2:1 vswr. the required dc blocking capacitor is provided on-chip, so the lna output can be connect- ed directly to the rf saw filter or balun. i/q mixers the mixers?differential input impedance is 200 ? , allow- ing an easy interface to commercially available differ- ential-output rx saw filters or 1:4 baluns. no dc blocks are required, but a single, small shunt inductor is required to resonate out the parasitic capacitance from the saw filter and ic package. the mixer offers an 11db gain step, which is controlled by either the logic-control pin (g_mxr) or bit 1 of the operation control register (opctrl.gmxr). this offers the option to switch the mixer into a low-gain state if required, reducing current consumption by about 3ma. use the mixer gain step and agc before reducing lna gain for optimum receiver dynamic range. baseband i/q filters all receiver channel selectivity is implemented fully on- chip, with greater than 40db adjacent channel selectivi- ty (acs). this eliminates the need for any additional filtering by any subsequent baseband processor. the group delay of the integrated filters is compensat- ed through on-chip equalizers for optimum evm. agc the agc circuitry of the baseband amplifiers offers lin- ear (db/v) gain control for the receiver. with the agc voltage from 0.3v to 2.4v, the vga section provides 60db gain-control range, for a total of 95db including the lna and mixer gain steps. the agc control line has an input impedance of more than 100k ? at dc. internal capacitance creates a single pole at approximately 2mhz; this provides some high- frequency filtering, thereby reducing am distortion. for applications using a baseband processor with digi- tal-only agc, maxim offers an 8-bit voltage-output agc dac with an spi/qspi/microwire interface in a tiny 6-pin sot23 package. especially designed as a low- cost, all-in-one solution for cellular handset agc, the max5383 offers the following features: a serial interface good to 10mhz, guaranteed operation from a 2.7v to 3.6v supply, on-chip 2v reference, <10% full-scale error, max2390?ax2393/max2396/max2400/max2401 w-cdma/w-tdd/td-scdma zero-if receivers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 33 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. synthesizer and lo generation the max2390?ax2393, max2401 incorporate an inte- ger-n synthesizer on-chip, including the vco, tank, all dividers, phase comparator, etc. only a tcxo and a loop filter are required as external components. the lo leakage at the lna input is minimized by running the internal vco at 2x the desired lo frequency. the typical application uses a comparison frequency of 200khz the channel raster for 3gpp-fdd and -tdd systems. there are no special requirements for the synthesizer loop filter. the ev kits use a classic type-ii loop filter, with a bandwidth of about 20khz. this ensures a 200? settling time for a 60mhz frequency jump. use a 1nf dc-blocking capacitor in series with the ref- erence oscillator input so as not to disturb the dc bias. the max2396/max2400 integrate the vco and the divide-by-2 for the lo generation, but do not include the synthesizer. the lo leakage at the lna input is minimized by running the vco at twice the desired rf frequency. the vco signal is made available to the external pll through an on-chip divide-by-three prescaler. since f vco_output = f vco / 3, and f rflo = f vco / 2, then f vco_output = (2/3)f rflo . that is, when the rflo of the max2400 is running at midband (1960mhz), the vco output and the synthesizer are running at 1306.67mhz. package information for the latest package outline information, go to www.maxim-ic.com/packages .

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