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features description applications ads5546 slws183c ? november 2005 ? revised october 2006 14-bit, 190 msps adc with ddr lvds/cmos outputs power amplifier linearization 802.16d/e maximum sample rate: 190 msps test and measurement instrumentation 14-bit resolution high definition video no missing codes medical imaging total power dissipation 1.1 w radar systems internal sample and hold 73.2-dbfs snr at 70-mhz if 87-dbc sfdr at 70-mhz if, 0 db gain ads5546 is a high performance 14-bit, 190-msps double data rate (ddr) lvds and parallel a/d converter. it offers state-of-the art functionality cmos output options and performance using advanced techniques to minimize board space. using an internal sample and programmable gain up to 6 db for snr/sfdr hold and low jitter clock buffer, the adc supports trade-off at high if both high snr and high sfdr at high input reduced power modes at lower sample frequencies. it features programmable gain options rates that can be used to improve sfdr performance at supports input clock amplitude down to 400 lower full-scale analog input ranges. mv pp in a compact 48-pin qfn, the device offers fully clock duty cycle stabilizer differential lvds ddr (double data rate) interface while parallel cmos outputs can also be selected. no external reference decoupling required flexible output clock position programmability is internal and external reference support available to ease capture and trade-off setup for hold programmable output clock position to ease times. at lower sampling rates, the adc can be data capture operated at scaled down power with no loss in performance. ads5546 includes an internal 3.3-v analog and digital supply reference, while eliminating the traditional reference 48-qfn package (7 mm 7 mm) pins and associated external decoupling. the device also supports an external reference mode. the device is specified over the industrial wireless communications infrastructure temperature range (-40 c to 85 c). software defined radio please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. copyright ? 2005?2006, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. www .ti.com
ads5546 slws183c ? november 2005 ? revised october 2006 this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. package/ordering information (1) specified transport package- package package ordering product temperature media, lead designator marking number range quantity ads5546irgzt tape and reel, 250 ads5546 qfn-48 (2) rgz ?40 c to 85 c az5546 ADS5546IRGZR tape and reel, 2500 (1) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti web site at www.ti.com . (2) for thermal pad size on the package, see the mechanical drawings at the end of this data sheet. q ja = 25.41 c/w (0 lfm air flow), q jc = 16.5 c/w when used with 2 oz. copper trace and pad soldered directly to a jedec standard four layer 3 in x 3 in pcb. 2 submit documentation feedback www .ti.com b0095-01 sha 14-bit adc clockgen reference digital encoder and serializer control interface inp inm clkp clkm vcm clkoutpclkoutm d0_d1_p d0_d1_m d2_d3_p d4_d5_p d6_d7_p d8_d9_p d10_d11_p d12_d13_p d2_d3_md4_d5_m d6_d7_m d8_d9_m d10_d11_m d12_d13_m ovr ads5546 iref sclk sen sdata reset oe dfs mode lvds mode avdd agnd drvdd drgnd
absolute maximum ratings (1) recommended operating conditions ads5546 slws183c ? november 2005 ? revised october 2006 over operating free-air temperature range (unless otherwise noted) value unit supply voltage range, avdd ?0.3 v to 3.9 v supply voltage range, drvdd ?0.3 v to 3.9 v voltage between agnd and drgnd -0.3 to 0.3 v voltage between avdd to drvdd -0.3 to 3.3 v voltage applied to vcm pin (in external reference mode) -0.3 to 1.8 v voltage applied to analog input pins, inp and inm ?0.3 v to minimum (3.6, avdd + 0.3 v) v voltage applied to input clock pins, clkp and clkm -0.3 v to avdd + 0.3 v v t a operating free-air temperature range ?40 to 85 c t j operating junction temperature range 125 c t stg storage temperature range ?65 to 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute maximum rated conditions for extended periods may affect device reliability. over operating free-air temperature range (unless otherwise noted) min typ max unit supplies analog supply voltage, avdd 3 3.3 3.6 v digital supply voltage, drvdd 3 3.3 3.6 v analog inputs differential input voltage range 2 v pp input common-mode voltage 1.5 0.1 v voltage applied on vcm in external reference mode 1.45 1.5 1.55 v clock input input clock sample rate default speed mode 50 190 msps low speed mode 1 60 input clock amplitude differential (v (clkp) - v (clkm) ) sine wave, ac-coupled 0.4 1.5 v pp lvpecl, ac-coupled 1.6 v pp lvds, ac-coupled 0.7 v pp lvcmos, single-ended, ac-coupled 3.3 v input clock duty cycle (see figure 34 ) 35% 50% 65% digital outputs maximum external load capacitance from each output pin to drgnd (lvds and c l 5 pf cmos modes) r l differential load resistance between the lvds output pairs (lvds mode) 100 w operating free-air temperature ?40 85 c 3 submit documentation feedback www .ti.com
electrical characteristics ads5546 slws183c ? november 2005 ? revised october 2006 typical values are at 25 c, min and max values are across the full temperature range t min = ?40 c to t max = 85 c, avdd = drvdd = 3.3 v, sampling rate = 190 msps, sine wave input clock, 1.5 v pp differential clock amplitude, 50% clock duty cycle, ?1 dbfs differential analog input, internal reference mode, 0db gain, ddr lvds data output (unless otherwise noted) parameter test conditions min typ max unit resolution 14 bits analog input differential input voltage range 2 v pp differential input capacitance 7 pf analog input bandwidth ?3 db, source impedance 50 w 500 mhz analog input common mode current 310 m a (per input pin) reference voltages v (refb) internal reference bottom voltage internal reference mode 0.5 v v (reft) internal reference top voltage internal reference mode 2.5 v v cm common mode output voltage internal reference mode 1.5 v vcm output current capability internal reference mode 4 ma dc accuracy no missing codes specified dnl differential non-linearity ?0.9 0.5 2.5 lsb inl integral non-linearity ?5 3 5 lsb offset error 5 mv offset temperature coefficient 0.002 ppm/ c gain error 1 %fs gain temperature coefficient 0.01 d %/ c psrr dc power supply rejection ratio 0.6 mv/v power supply i (avdd) analog supply current 291 ma lvds mode, i o = 3.5 ma, 51 ma r l = 100 w , c l = 5 pf i (drvdd) digital supply current cmos mode, f in = 2.5 mhz, 43 ma c l = 5 pf i cc total supply current lvds mode 342 ma total power dissipation lvds mode 1.13 1.29 w in standby mode with clock standby power 100 150 mw running clock stop power with input clock stopped 100 150 mw 4 submit documentation feedback www .ti.com
electrical characteristics ads5546 slws183c ? november 2005 ? revised october 2006 typical values are at 25 c, min and max values are across the full temperature range t min = ?40 c to t max = 85 c, avdd = drvdd = 3.3 v, sampling rate = 190 msps, sine wave input clock, 1.5 v pp differential clock amplitude, 50% clock duty cycle, ?1 dbfs differential analog input, internal reference mode, 0db gain, ddr lvds data output (unless otherwise noted) parameter test conditions min typ max unit ac characteristics f in = 10 mhz 73.8 f in = 40 mhz 73.6 f in = 70 mhz 71.5 73.5 f in = 100 mhz 73 snr signal to noise ratio f in = 150 mhz 72.2 dbfs 0 db gain, 2 v pp fs (1) 71 f in = 225 mhz 3 db gain, 1.4 v pp fs 69.8 0 db gain, 2 v pp fs 70 f in = 300 mhz 3 db gain, 1.4 v pp fs 69 rms output noise inputs tied to common-mode 1.1 lsb f in = 10 mhz 90 f in = 40 mhz 89 f in = 70 mhz 77 87 f in = 100 mhz 84 sfdr spurious free dynamic range f in = 150 mhz 84 dbc 0 db gain, 2 v pp fs 75 f in = 225 mhz 3 db gain, 1.4 v pp fs 78 0 db gain, 2 v pp fs 72 f in = 300 mhz 3 db gain, 1.4 v pp fs 75 f in = 10 mhz 73.5 f in = 40 mhz 73.1 f in = 70 mhz 71 72.8 f in = 100 mhz 72.1 sinad signal to noise and distortion ratio f in = 150 mhz 71.8 dbfs 0 db gain, 2 v pp fs 69 f in = 225 mhz 3 db gain, 1.4 v pp fs 68.5 0 db gain, 2 v pp fs 67.8 f in = 300 mhz 3 db gain, 1.4 v pp fs 67.5 f in = 10 mhz 92 f in = 40 mhz 91 f in = 70 mhz 77 90 f in = 100 mhz 89 hd2 second harmonic f in = 150 mhz 87 dbc 0 db gain, 2 v pp fs 76 f in = 225 mhz 3 db gain, 1.4 v pp fs 79 0 db gain, 2 v pp fs 73 f in = 300 mhz 3 db gain, 1.4 v pp fs 75 (1) fs = full scale range 5 submit documentation feedback www .ti.com
ads5546 slws183c ? november 2005 ? revised october 2006 electrical characteristics (continued) typical values are at 25 c, min and max values are across the full temperature range t min = ?40 c to t max = 85 c, avdd = drvdd = 3.3 v, sampling rate = 190 msps, sine wave input clock, 1.5 v pp differential clock amplitude, 50% clock duty cycle, ?1 dbfs differential analog input, internal reference mode, 0db gain, ddr lvds data output (unless otherwise noted) parameter test conditions min typ max unit f in = 10 mhz 90 f in = 40 mhz 89 f in = 70 mhz 77 87 f in = 100 mhz 84 hd3 third harmonic f in = 150 mhz 84 dbc 0 db gain, 2 v pp fs 75 f in = 225 mhz 3 db gain, 1.4 v pp fs 78 0 db gain, 2 v pp fs 72 f in = 300 mhz 3 db gain, 1.4 v pp fs 74 f in = 10 mhz 93 f in = 40 mhz 92 f in = 70 mhz 91 worst harmonic (other than hd2, hd3) f in = 100 mhz 90 dbc f in = 150 mhz 89 f in = 225 mhz 87 f in = 300 mhz 87 f in = 10 mhz 85 f in = 40 mhz 85 f in = 70 mhz 75 83 thd total harmonic distortion f in = 100 mhz 81 dbc f in = 150 mhz 80 f in = 225 mhz 72 f in = 300 mhz 68 enob effective number of bits f in = 10 mhz 11.8 bits f in1 = 50.09 mhz, f in2 = 46.09 mhz, -7 dbfs 95 each tone imd two-tone intermodulation distortion dbfs f in1 = 135.08 mhz, f in2 = 130.08 mhz, -7 dbfs 89 each tone psrr ac power supply rejection ratio 30 mhz, 200 mv pp signal on 3.3-v supply 35 dbc recovery to 1% (of final value) for 6-db overload clock voltage overload recovery time 1 with sine-wave input at nyquist frequency cycles 6 submit documentation feedback www .ti.com
digital characteristics (1) timing characteristics ? lvds and cmos modes (1) ads5546 slws183c ? november 2005 ? revised october 2006 the dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1 avdd = drvdd = 3.3 v, i o = 3.5 ma, r l = 100 w (2) parameter test conditions min typ max unit digital inputs high-level input voltage 2.4 v low-level input voltage 0.8 v high-level input current 33 m a low-level input current ?33 m a input capacitance 4 pf digital outputs ? cmos mode high-level output voltage 3.3 v low-level output voltage 0 v output capacitance inside the device, from each output to output capacitance 2 pf ground digital outputs ? lvds mode high-level output voltage 1375 mv low-level output voltage 1025 mv output differential voltage, |v od | 225 350 mv v os output offset voltage, single-ended common-mode voltage of outp and outm 1200 mv output capacitance inside the device, from either output to output capacitance 2 pf ground (1) all lvds and cmos specifications are characterized, but not tested at production. (2) i o refers to the lvds buffer current setting, r l is the differential load resistance between the lvds output pair. typical values are at 25 c, min and max values are across the full temperature range t min = ?40 c to t max = 85 c, avdd = drvdd = 3.3 v, sampling frequency = 190 msps, sine wave input clock, 1.5 v pp clock amplitude, c l = 5 pf (2) , i o = 3.5 ma, r l = 100 w (3) , no internal termination, unless otherwise noted. for timings at lower sampling frequencies, see the output timing section in the application information of this data sheet. parameter test conditions min typ max unit t a aperture delay 1.2 ns t j aperture jitter 150 fs rms time to valid data after coming out of 100 standby mode wake-up time m s time to valid data after stopping and restarting 100 the input clock clock latency 14 cycles ddr lvds mode (4) t su data setup time (5) data valid (6) to zero-cross of clkoutp 1.2 1.7 ns zero-cross of clkoutp to data becoming t h data hold time (5) 0.4 0.9 ns invalid (6) input clock rising edge zero-cross to output t pdi clock propagation delay 4 4.7 5.4 ns clock rising edge zero-cross (1) timing parameters are specified by design and characterization and not tested in production. (2) c l is the effective external single-ended load capacitance between each output pin and ground. (3) i o refers to the lvds buffer current setting; r l is the differential load resistance between the lvds output pair. (4) measurements are done with a transmission line of 100 w characteristic impedance between the device and the load. (5) setup and hold time specifications take into account the effect of jitter on the output data and clock. these specifications also assume that the data and clock paths are perfectly matched within the receiver. any mismatch in these paths within the receiver would appear as reduced timing margin. (6) data valid refers to logic high of +50 mv and logic low of ?50 mv. 7 submit documentation feedback www .ti.com
ads5546 slws183c ? november 2005 ? revised october 2006 timing characteristics ? lvds and cmos modes (continued) for timings at lower sampling frequencies, see the output timing section in the application information of this data sheet. parameter test conditions min typ max unit duty cycle of differential clock, lvds bit clock duty cycle (clkoutp-clkoutm) 45% 50% 55% 80 fs 190 msps rise time measured from ?50 mv to 50 mv t r , data rise time, fall time measured from 50 mv to ?50 mv 50 100 200 ps t f data fall time 1 fs 190 msps rise time measured from ?50 mv to 50 mv t clkrise , output clock rise time, fall time measured from 50 mv to ?50 mv 50 100 200 ps t clkfall output clock fall time 1 fs 190 msps output enable (oe) to valid data t oe time to valid data after oe becomes active 1 m s delay parallel cmos mode t su data setup time (5) data valid (7) to 50% of clkout rising edge 2.2 3 ns 50% of clkout rising edge to data becoming t h data hold time (5) 0.5 0.9 ns invalid (7) input clock rising edge zero-cross to 50% of t pdi clock propagation delay 2.4 3.2 4 ns clkout rising edge duty cycle of output clock (clkout) output clock duty cycle 45% 80 fs 190 msps rise time measured from 20% to 80% of drvdd t r , data rise time, fall time measured from 80% to 20% of 0.8 1.5 2 ns t f data fall time drvdd 1 fs 190 msps rise time measured from 20% to 80% of drvdd t clkrise , output clock rise time, fall time measured from 80% to 20% of 0.4 0.8 1.2 ns t clkfall output clock fall time drvdd 1 fs 190 msps output enable (oe) to valid data t oe time to valid data after oe becomes active 50 ns delay (7) data valid refers to logic high of 2 v and logic low of 0.8 v 8 submit documentation feedback www .ti.com
ads5546 slws183c ? november 2005 ? revised october 2006 figure 1. latency figure 2. lvds mode timing 9 submit documentation feedback www .ti.com e e e e e e e e e e o o o o o o o o o o input clock clkoutm clkoutp output data dxp, dxm ddr lvds nC14 nC13 nC12 nC11 nC10 nC1 n n+1 n+2 nC14 nC13 nC12 nC11 nC10 n n+2 14 clock cycles 14 clock cycles clkout output data d0Cd13 parallel cmos input signal sample n n+1 n+2 n+3 n+4 t h t pdi t a t su t h t pdi clkp clkm n+14 n+15 n+16 n+17 t su e C even bits d0,d2,d4,d6,d8,d10,d12 o C odd bits d1,d3,d5,d7,d9,d11,d13 n+1 nC1 t0106-01 input clock output clock output data pair clkm clkoutp dn_dn+1_p, dn_dn+1_m clkp t pdi t su t h t h t su clkoutm (1) dn C bits d0, d2, d4, d6, d8, d10, d12 (2) dn+1 C bits d1, d3, d5, d7, d9, d11, d13 dn (1) dn+1 (2)
ads5546 slws183c ? november 2005 ? revised october 2006 figure 3. cmos mode timing 10 submit documentation feedback www .ti.com t0107-01 input clock output clock output data clkm dn clkp t pdi t su t h clkout (1) dn C bits d0Cd13 dn (1)
device programming modes using parallel interface control only using serial interface programming only using both the serial interface and parallel controls ads5546 slws183c ? november 2005 ? revised october 2006 ads5546 offers flexibility with several programmable features that are easily configured. the device can be configured independently using either a parallel interface control or a serial interface programming. in addition, the device supports a third mode, where both the parallel interface and the serial control registers are used. in this mode, the priority between the parallel and serial interfaces is determined by a priority table (table 2 ). if this additional level of flexibility is not required, the user can select either the serial interface programming or the parallel interface control. to control the device using the parallel interface, keep reset tied to high (drvdd). pins dfs, mode, sen, sclk, and sdata are used to directly control certain modes of the adc. the device is configured by connecting the parallel pins to the correct voltage levels (as described in table 4 to table 7 ). there is no need to apply reset. in this mode, sen, sclk, and sdata function as parallel interface control pins. frequently used functions are controlled in this mode?standby, selection between lvds/cmos output format, internal/external reference, two's complement/straight binary output format, and position of the output clock edge. table 1 has a description of the modes controlled by the four parallel pins. table 1. parallel pin definition pin control modes dfs data format and the lvds/cmos output interface mode internal or external reference sen clkout edge programmability sclk low speed mode control for low sampling frequencies (< 50 msps) sdata standby mode ? global (adc, internal references and output buffers are powered down) to program using the serial interface, the internal registers must first be reset to their default values, and the reset pin must be kept low. in this mode, sen, sdata, and sclk function as serial interface pins and are used to access the internal registers of adc. the registers are reset either by applying a pulse on the reset pin, or by a high setting on the bit (d1 in register 0x6c). the serial interface section describes the register programming and register reset in more detail. since the parallel pins dfs and mode are not used in this mode, they must be tied to ground. for increased flexibility, a combination of serial interface registers and parallel pin controls (dfs, mode) can also be used to configure the device. the serial registers must first be reset to their default values, and the reset pin must be kept low. in this mode sen, sdata, and sclk function as serial interface pins and are used to access the internal registers of adc. the registers are reset either by applying a pulse on reset pin or by a high setting on the bit (d1 in register 0x6c). the serial interface section describes the register programming and register reset in more detail. the parallel interface control pins dfs and mode are used, and their function is determined by the appropriate voltage levels as described in table 6 and table 7 . the voltage levels are derived by using a resistor string as illustrated in figure 4 . since some functions are controlled using both the parallel pins and serial registers, the priority between the two is determined by a priority table (table 2 ). 11 submit documentation feedback www .ti.com
ads5546 slws183c ? november 2005 ? revised october 2006 table 2. priority between parallel pins and serial registers pin functions supported priority when using the serial interface, bit (register 0x6d, bit d4) controls this mode, only mode internal/external reference if the mode pin is tied low. when using the serial interface, bit (register 0x63, bit d3) controls this mode, only if data format the dfs pin is tied low. dfs when using the serial interface, bit (register 0x6c, bits d3-d4) controls lvds/cmos lvds/cmos selection independent of the state of dfs pin figure 4. simple scheme to configure parallel pins 12 submit documentation feedback www .ti.com (1/3) avdd (1/3) avdd to parallel pin r avdd avdd gnd rr (2/3) avdd (2/3) avdd
description of parallel pins serial interface ads5546 slws183c ? november 2005 ? revised october 2006 table 3. sclk control pin sclk (pin 29) description 0 default speed - must be used for sampling frequency > 50 msps drvdd low speed - must be used for sampling frequency <= 50 msps table 4. sdata control pin sdata (pin 28) description 0 normal operation (default) drvdd standby. this is a global power down, where adc, internal references and the output buffers are powered down. table 5. sen control pin sen (pin 27) description 0 cmos mode: clkout edge later by (3/12)ts (1) ; lvds mode: clkout edge aligned with data transition (1/3)drvdd cmos mode: clkout edge later by (2/12)ts (1) ; lvds mode: clkout edge aligned with data transition (2/3)drvdd cmos mode: clkout edge later by (1/12)ts (1) ; lvds mode: clkout edge earlier by (1/12)ts (1) drvdd default clkout position (1) ts = 1/sampling frequency table 6. dfs control pin dfs (pin 6) description 0 2's complement data and ddr lvds output (default) (1/3)drvdd 2's complement data and parallel cmos output (2/3)drvdd offset binary data and parallel cmos output drvdd offset binary data and ddr lvds output table 7. mode control pin mode (pin 23) description 0 internal reference (1/3)avdd external reference (2/3)avdd external reference avdd internal reference the adc has a set of internal registers, which can be accessed through the serial interface formed by pins sen (serial interface enable), sclk (serial interface clock), sdata (serial interface data) and reset. after device power-up, the internal registers must be reset to their default values by applying a high-going pulse on reset (of width greater than 10 ns). serial shift of bits into the device is enabled when sen is low. serial data sdata is latched at every falling edge of sclk when sen is active (low). the serial data is loaded into the register at every 16th sclk falling edge when sen is low. if the word length exceeds a multiple of 16 bits, the excess bits are ignored. data is loaded in multiples of 16-bit words within a single active sen pulse. the first 8 bits form the register address and the remaining 8 bits form the register data. 13 submit documentation feedback www .ti.com
register initialization serial interface timing characteristics ads5546 slws183c ? november 2005 ? revised october 2006 after power-up, the internal registers must be reset to their default values. this is done in one of two ways: 1. either through hardware reset by applying a high-going pulse on reset pin (of width greater than 10 ns) as shown in figure 5 . or 2. by applying software reset. using the serial interface, set the bit (d1 in register 0x6c) to high. this initializes the internal registers to their default values and then self-resets the bit to low. in this case the reset pin is kept low. figure 5. serial interface timing diagram typical values at 25 c, min and max values across the full temperature range t min = ?40 c to t max = 85 c, avdd = drvdd = 3.3 v (unless otherwise noted) min typ max unit t sclk sclk period 50 ns sclk duty cycle 50% t sloads sen to sclk setup time 25 ns t sloadh sclk to sen hold time 25 ns t dsu sdata setup time 25 ns t dh sdata hold time 25 ns 14 submit documentation feedback www .ti.com t0109-01 register address register data t (sclk) t (dsu) t (dh) t (sloads) d7 a7 d3 a3 d5 a5 d1 a1 d6 a6 d2 a2 d4 a4 d0 a0 sdata sclk sen reset t (sloadh)
reset timing ads5546 slws183c ? november 2005 ? revised october 2006 typical values at 25 c, min and max values across the full temperature range t min = ?40 c to t max = 85 c, avdd = drvdd = 3.3 v (unless otherwise noted) parameter test conditions min typ max unit t 1 power-on delay delay from power-up of avdd and drvdd to reset pulse active 5 ms t 2 reset pulse width pulse width of active reset signal 10 ns t 3 register write delay delay from reset disable to sen active 25 ns t po power-up time delay from power-up of avdd and drvdd to output stable 6.5 ms note: a high-going pulse on reset pin is required in serial interface mode in case of initialization through hardware reset. for parallel interface operation, reset has to be tied permanently high. figure 6. reset timing diagram 15 submit documentation feedback www .ti.com t0108-01 t 1 t 3 t 2 power supply avdd, drvdd reset sen
description of serial registers ads5546 slws183c ? november 2005 ? revised october 2006 table 8 gives a summary of all the modes that can be programmed through the serial interface. table 8. serial interface register map register address register data description a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 ? global power down normal converter operation (default after 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 reset) 0 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 standby ? software reset 0 1 1 0 1 1 0 0 0 0 0 0 0 0 1 0 resets all registers to default values ? output data format 2's complement output format (default after 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 reset) 0 1 1 0 0 0 1 1 0 0 0 0 1 0 0 0 straight binary output format ? output data interface ddr lvds outputs (d4:d3 defaults to 00 0 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 after reset) 0 1 1 0 1 1 0 0 0 0 0 1 1 0 0 0 parallel cmos outputs ?internal/external reference mode 0 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 internal reference (default after reset) external reference ? force voltage on vcm 0 1 1 0 1 1 0 1 0 0 0 1 0 0 0 0 pin ? output test pattern on data outputs 0 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 normal operation (default after reset) 0 1 1 0 0 1 0 1 0 0 1 0 0 0 0 0 all zeros 0 1 1 0 0 1 0 1 0 1 0 0 0 0 0 0 all ones toggle pattern alternate 1s and 0s on each 0 1 1 0 0 1 0 1 0 1 1 0 0 0 0 0 data output and across the data outputs. ramp pattern ? output data ramps from 0 1 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0x0000 to 0x3fff every clock cycle custom pattern. write the custom pattern in 0 1 1 0 0 1 0 1 1 0 1 0 0 0 0 0 custom pattern registers a and b. 0 1 1 0 0 1 0 1 x x x 0 0 0 0 0 not used ? output custom pattern on data outputs 0 1 1 0 1 0 0 1 d7 d6 d5 d4 d3 d2 d1 d0 custom pattern d7-d0 0 1 1 0 1 0 1 0 0 0 d13 d12 d11 d10 d9 d8 custom pattern d13-d8 ? clock buffer gain programmability, gain decreases monotonically from gain 4 to gain 0 0 1 1 0 1 0 1 1 0 0 1 1 0 0 1 0 gain 4 0 1 1 0 1 0 1 1 0 0 1 0 1 0 1 0 gain 3 0 1 1 0 1 0 1 1 0 0 1 0 0 1 1 0 gain 2 0 1 1 0 1 0 1 1 0 0 1 0 0 0 0 0 gain 1 (default after reset) 0 1 1 0 1 0 1 1 0 0 1 0 0 0 1 1 gain 0 minimum gain power scaling vs sampling frequency. the adc can be operated at reduced power at lower sampling rates with no loss in performance. 0 1 1 0 1 1 0 1 0 0 1 0 0 0 0 0 default fs > 150 msps (default after reset) 0 1 1 0 1 1 0 1 1 0 1 0 0 0 0 0 power mode 1 ? 105 < fs 150 msps 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 0 power mode 2 ? 50 < fs 105 msps 0 1 1 0 1 1 0 1 1 1 1 0 0 0 0 0 power mode 3 ? fs 50 msps 16 submit documentation feedback www .ti.com
ads5546 slws183c ? november 2005 ? revised october 2006 table 8. serial interface register map (continued) register address register data description a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 gain programming - channel gain can be programmed from 0 to 6 db for sfdr/snr trade-off. for each gain setting, the input full-scale range has to be proportionally scaled. for 6 db gain, the full-scale range will be 1 v pp compared to 2 v pp at 0 db gain. 0 1 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 db (default after reset) 0 1 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1 db 0 1 1 0 1 0 0 0 0 0 0 0 1 0 1 0 2 db 0 1 1 0 1 0 0 0 0 0 0 0 1 0 1 1 3 db 0 1 1 0 1 0 0 0 0 0 0 0 1 1 0 0 4 db 0 1 1 0 1 0 0 0 0 0 0 0 1 1 0 1 5 db 0 1 1 0 1 0 0 0 0 0 0 0 1 1 1 0 6 db ? lvds output data and clock buffers nominal current programmability 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 3.5 ma (default after reset) 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 2.5 ma 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 4.5 ma 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1.75 ma ? the output data and clock buffer currents are doubled from the value selected by the register. value specified by 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 (default after reset) 0 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 2x data, 2x clock currents 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1x data, 2x clock currents 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 2x data, 4x clock currents internal termination - option to terminate the lvds data buffers inside the adc to improve signal integrity. by default, internal termination is disabled. 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 no termination (default after reset) 0 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 325 w 0 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 200 w 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 125 w 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 170 w 0 1 1 1 1 1 1 0 1 0 1 0 0 0 0 0 120 w 0 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 100 w 0 1 1 1 1 1 1 0 1 1 1 0 0 0 0 0 75 w internal termination - option to terminate the lvds clk buffers inside the adc to improve signal integrity. by default, internal termination is disabled. 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 no termination (default after reset) 0 1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 325 w 0 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 200 w 0 1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 125 w 0 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 170 w 0 1 1 1 1 1 1 0 0 0 0 1 0 1 0 0 120 w 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 100 w 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 75 w ? output clock rising edge programmability in cmos mode (1) 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 default position 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 1 clkout rising edge later by (1/12)ts 0 1 1 0 0 0 1 0 0 0 0 0 0 1 0 1 clkout rising edge later by (3/12)ts 0 1 1 0 0 0 1 0 0 0 0 0 0 1 1 1 clkout rising edge later by (2/12)ts (1) ts = 1/sampling frequency 17 submit documentation feedback www .ti.com
ads5546 slws183c ? november 2005 ? revised october 2006 table 8. serial interface register map (continued) register address register data description a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 ? output clock falling edge programmability in cmos mode (2) 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 default position 0 1 1 0 0 0 1 0 0 0 0 0 1 0 0 1 clkout falling edge later by (1/12)ts 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 1 clkout falling edge later by (3/12)ts 0 1 1 0 0 0 1 0 0 0 0 1 1 0 0 1 clkout falling edge later by (2/12)ts ? output clock rising edge programmability in lvds mode (2) 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 default position 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 1 clkout rising edge earlier by (1/12)ts clkout rising edge aligned with data 0 1 1 0 0 0 1 0 0 0 0 0 0 1 0 1 transition clkout rising edge aligned with data 0 1 1 0 0 0 1 0 0 0 0 0 0 1 1 1 transition ? output clock falling edge programmability in lvds mode (2) 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 default position 0 1 1 0 0 0 1 0 0 0 0 0 1 0 0 1 clkout falling edge earlier by (1/12)ts clkout falling edge aligned with data 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 1 transition clkout falling edge aligned with data 0 1 1 0 0 0 1 0 0 0 0 1 1 0 0 1 transition - for low sampling frequency operation default speed mode - for 50 pin configuration (lvds mode) ads5546 slws183c ? november 2005 ? revised october 2006 figure 7. lvds mode pinout pin assignments ? lvds mode pin pin number pin name description type number of pins 8, 18, 20, avdd analog power supply i 6 22, 24, 26 9, 12, 14, agnd analog ground i 6 17, 19, 25 clkp, clkm differential clock input i 10, 11 2 inp, inm differential analog input i 15, 16 2 internal reference mode ? common-mode voltage output. vcm external reference mode ? reference input. the voltage forced on this pin sets i/o 13 1 the internal references. iref current-set resistor, 56.2-k w resistor to ground. i 21 1 serial interface reset input. when using the serial interface mode, the user must initialize internal registers through hardware reset by applying a high-going pulse on this pin, or by using reset the software reset option. see the serial interface section. i 30 1 in parallel interface mode, the user has to tie the reset pin permanently high. (sdata and sen are used as parallel pin controls in this mode) the pin has an internal 100-k w pull-down resistor. 19 submit documentation feedback www .ti.com drgnd vcm drvdd agnd ovr inp clkoutm inm clkoutp agnd dfs a vdd oe agnd avdd avdd agnd iref clkp avdd clkm mode agnd avdd 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 drgnd d12_d13_p drvdd d12_d13_m d0_d1_p d10_d11_p d0_d1_m d10_d11_m nc d8_d9_p nc d8_d9_m reset d6_d7_p sclk d6_d7_m sdata d4_d5_p sen d4_d5_m avdd d2_d3_p agnd d2_d3_m 3635 34 33 32 31 30 29 28 27 26 25 48 47 46 4544 43 42 41 40 39 38 37 p0023-02 rgz package (top view)
ads5546 slws183c ? november 2005 ? revised october 2006 pin assignments ? lvds mode (continued) pin pin number pin name description type number of pins this pin functions as serial interface clock input when reset is low. it functions as low speed mode control pin when reset is tied high. tie sclk sclk i 29 1 to low for fs > 50 msps and sclk to high for fs 50 msps. see table 3 . the pin has an internal 100-k w pull-down resistor. this pin functions as serial interface data input when reset is low. it functions as standby control pin when reset is tied high. sdata i 28 1 see table 4 for detailed information. the pin has an internal 100 k w pull-down resistor. this pin functions as serial interface enable input when reset is low. it functions as clkout edge programmability when reset is tied high. see table 5 for sen i 27 1 detailed information. the pin has an internal 100-k w pull-up resistor to drvdd. output buffer enable input, active high. the pin has an internal 100-k w pull-up oe i 7 1 resistor to drvdd. data format select input. this pin sets the data format (twos complement or dfs offset binary) and the lvds/cmos output mode type. see table 6 for detailed i 6 1 information. mode select input. this pin selects the internal or external reference mode. see mode i 23 1 table 7 for detailed information. clkoutp differential output clock, true o 5 1 clkoutm differential output clock, complement o 4 1 d0_d1_p differential output data d0 and d1 multiplexed, true o 34 1 d0_d1_m differential output data d0 and d1 multiplexed, complement. o 33 1 d2_d3_p differential output data d2 and d3 multiplexed, true o 38 1 d2_d3_m differential output data d2 and d3 multiplexed, complement o 37 1 d4_d5_p differential output data d4 and d5 multiplexed, true o 40 1 d4_d5_m differential output data d4 and d5 multiplexed, complement o 39 1 d6_d7_p differential output data d6 and d7 multiplexed, true o 42 1 d6_d7_m differential output data d6 and d7 multiplexed, complement o 41 1 d8_d9_p differential output data d8 and d9 multiplexed, true o 44 1 d8_d9_m differential output data d8 and d9 multiplexed, complement o 43 1 d10_d11_p differential output data d10 and d11 multiplexed, true o 46 1 d10_d11_m differential output data d10 and d11 multiplexed, complement o 45 1 d12_d13_p differential output data d12 and d13 multiplexed, true o 48 1 d12_d13_m differential output data d12 and d13 multiplexed, complement o 47 1 ovr out-of-range indicator, cmos level signal o 3 1 drvdd digital and output buffer supply i 2, 35 2 drgnd digital and output buffer ground i 1, 36 2 nc do not connect 31, 32 2 20 submit documentation feedback www .ti.com
pin configuration (cmos mode) ads5546 slws183c ? november 2005 ? revised october 2006 figure 8. cmos mode pinout pin assignments ? cmos mode pin pin number pin name description type number of pins 8, 18, 20, avdd analog power supply i 6 22, 24, 26 9, 12, 14, 17, agnd analog ground i 6 19, 25 clkp, clkm differential clock input i 10, 11 2 inp, inm differential analog input i 15, 16 2 internal reference mode ? common-mode voltage output. vcm external reference mode ? reference input. the voltage forced on this pin sets i/o 13 1 the internal references. iref current-set resistor, 56.2-k w resistor to ground. i 21 1 serial interface reset input. when using the serial interface mode, the user must initialize internal registers through hardware reset by applying a high-going pulse on this pin, or by using the software reset option. see the serial interface section. reset i 30 1 in parallel interface mode, the user has to tie reset pin permanently high. (sdata and sen are used as parallel pin controls in this mode). the pin has an internal 100-k w pull-down resistor. this pin functions as serial interface clock input when reset is low. it functions as low speed mode control pin when reset is tied high. tie sclk sclk i 29 1 to low for fs > 50 msps and sclk to high for fs 50 msps. see table 3 . the pin has an internal 100-k w pull-down resistor. 21 submit documentation feedback www .ti.com drgnd vcm drvdd agnd ovr inp unused inm clkout agnd dfs avdd oe agnd avdd a vdd agnd iref clkp a vdd clkm mode agnd avdd 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1718 19 20 21 22 23 24 drgnd d13 drvdd d12 d1 d1 1 d0 d10 nc d9 nc d8 reset d7 sclk d6 sdata d5 sen d4 avdd d3 agnd d2 3635 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 p0023-03 rgz package (top view)
ads5546 slws183c ? november 2005 ? revised october 2006 pin assignments ? cmos mode (continued) pin pin number pin name description type number of pins this pin functions as serial interface data input when reset is low. it functions as standby control pin when reset is tied high. sdata i 28 1 see table 4 for detailed information. the pin has an internal 100 k w pull-down resistor. this pin functions as serial interface enable input when reset is low. it functions as clkout edge programmability when reset is tied high. see table 5 for sen i 27 1 detailed information. the pin has an internal 100-k w pull-up resistor to drvdd. output buffer enable input, active high. the pin has an internal 100-k w pull-up oe i 7 1 resistor to drvdd. data format select input. this pin sets the data format (twos complement or dfs offset binary) and the lvds/cmos output mode type. see table 6 for detailed i 6 1 information. mode select input. this pin selects the internal or external reference mode. see mode i 23 1 table 7 for detailed information. clkout cmos output clock o 5 1 d0 cmos output data d0 o 33 1 d0 cmos output data d1 o 34 1 d2 cmos output data d2 o 37 1 d2 cmos output data d3 o 38 1 d4 cmos output data d4 o 39 1 d4 cmos output data d5 o 40 1 d6 cmos output data d6 o 41 1 d7 cmos output data d7 o 42 1 d8 cmos output data d8 o 43 1 d9 cmos output data d9 o 44 1 d10 cmos output data d10 o 45 1 d11 cmos output data d11 o 46 1 d12 cmos output data d12 o 47 1 d13 cmos output data d13 o 48 1 ovr out-of-range indicator, cmos level signal o 3 1 drvdd digital and output buffer supply i 2, 35 2 drgnd digital and output buffer ground i 1, 36 2 unused unused pin in cmos mode 4 1 nc do not connect 31, 32 2 22 submit documentation feedback www .ti.com
typical characteristics ads5546 slws183c ? november 2005 ? revised october 2006 all plots are at 25 c, avdd = drvdd = 3.3 v, sampling frequency = 190 msps, sine wave input clock, 1.5 v pp differential clock amplitude, 50% clock duty cycle, ?1 dbfs differential analog input, internal reference mode, 0 db gain, ddr lvds data output (unless otherwise noted) fft for 10 mhz input signal fft for 40 mhz input signal figure 9. figure 10. fft for 70 mhz input signal fft for 100 mhz input signal figure 11. figure 12. fft for 130 mhz input signal fft for 150 mhz input signal figure 13. figure 14. 23 submit documentation feedback www .ti.com -140 0 f frequency mhz - - amplitude db - -20-40 -60 -80 -100-120 sfdr = 91.4 dbc,snr = 74.2 dbfs, sinad = 74 dbfs 90 0 80 50 10 40 30 20 70 60 -140 0 f frequency mhz - - amplitude db - -20-40 -60 -80 -100-120 sfdr = 89.2 dbc,snr = 74 dbfs, sinad = 73.7 dbfs 90 0 80 50 10 40 30 20 70 60 -140 0 f frequency mhz - - amplitude db - -20-40 -60 -80 -100-120 90 0 80 50 10 40 30 20 70 60 sfdr = 87.8 dbc,snr = 73.7 dbfs, sinad = 73.3 dbfs -140 0 amplitude db - -20-40 -60 -80 -100-120 sfdr = 86.9 dbc,snr = 73.2 dbfs, sinad = 72.8 dbfs 0 90 80 50 10 40 30 20 70 60 f frequency mhz - - -140 0 f frequency mhz - - amplitude db - -20-40 -60 -80 -100-120 90 0 80 50 10 40 30 20 70 60 sfdr = 86.5 dbc,snr = 72.8 dbfs, sinad = 72.3 dbfs -140 0 f frequency mhz - - amplitude db - -20-40 -60 -80 -100-120 90 0 80 50 10 40 30 20 70 60 sfdr = 85.2 dbc,snr = 72.4 dbfs, sinad = 71.9 dbfs
ads5546 slws183c ? november 2005 ? revised october 2006 typical characteristics (continued) all plots are at 25 c, avdd = drvdd = 3.3 v, sampling frequency = 190 msps, sine wave input clock, 1.5 v pp differential clock amplitude, 50% clock duty cycle, ?1 dbfs differential analog input, internal reference mode, 0 db gain, ddr lvds data output (unless otherwise noted) fft for 200 mhz input signal fft for 225 mhz input signal figure 15. figure 16. fft for 300 mhz input signal fft for 375 mhz input signal figure 17. figure 18. fft for 500 mhz input signal intermodulation distortion (imd) vs frequency figure 19. figure 20. 24 submit documentation feedback www .ti.com -140 0 amplitude db - -20-40 -60 -80 -100-120 sfdr = 74 dbc,snr = 71 dbfs, sinad = 69.9 dbfs 90 0 80 50 10 40 30 20 70 60 f frequency mhz - - -140 0 amplitude db - -20-40 -60 -80 -100-120 90 0 80 50 10 40 30 20 70 60 sfdr = 77.2 dbc,snr = 71.7 dbfs, sinad = 69.4 dbfs f frequency mhz - - -140 0 f frequency mhz - - amplitude db - -20-40 -60 -80 -100-120 90 0 80 50 10 40 30 20 70 60 sfdr = 65.6 dbc,snr = 68.7 dbfs, sinad = 62.3 dbfs -140 0 f frequency mhz - - amplitude db - -20-40 -60 -80 -100-120 90 0 80 50 10 40 30 20 70 60 sfdr = 72.1 dbc,snr = 70.1 dbfs, sinad = 66.3 dbfs -140 0 f frequency mhz - - amplitude db - -20-40 -60 -80 -100-120 90 0 80 50 10 40 30 20 70 60 sfdr = 59 dbc,snr = 66 dbfs, sinad = 56.3 dbfs -140 0 f frequency mhz - - amplitude db - -20-40 -60 -80 -100-120 90 0 80 50 10 40 30 20 70 60 f = 50.09 mhz, -7 dbfs, 2-tone imd, 95 dbfs in1 f = 46.09 mhz, -7 dbfs, in2
ads5546 slws183c ? november 2005 ? revised october 2006 typical characteristics (continued) all plots are at 25 c, avdd = drvdd = 3.3 v, sampling frequency = 190 msps, sine wave input clock, 1.5 v pp differential clock amplitude, 50% clock duty cycle, ?1 dbfs differential analog input, internal reference mode, 0 db gain, ddr lvds data output (unless otherwise noted) intermodulation distortion (imd) vs frequency sfdr vs input frequency figure 21. figure 22. snr vs input frequency snr vs input frequency figure 23. figure 24. sfdr vs gain snr vs gain figure 25. figure 26. 25 submit documentation feedback www .ti.com -140 0 amplitude db - -20-40 -60 -80 -100-120 90 0 80 50 10 40 30 20 70 60 f = 135.08 mhz, -7 dbfs, 2-tone imd, 89 dbfs in1 f = 130.08 mhz, -7 dbfs, in2 f frequency mhz - - 62 58 90 f input frequency mhz in - - sfdr dbc - 500 86 82 78 74 70 66 0 400 250 50 200 150 100 350 300 450 94 f ? input frequency ? mhz in 59 60 61 62 63 64 65 66 67 68 69 70 71 72 0 50 100 150 200 250 300 350 400 450 500 snr ? dbfs cmos mode 66 65 75 f input frequency mhz in - - snr dbfs - 500 74 73 72 71 70 67 0 400 250 50 200 150 100 350 300 450 6968 lvds mode f ? input frequency ? mhz in 67 68 69 70 71 72 73 74 75 10 30 50 70 90 110 130 150 170 210 230 snr ? dbfs 190 0 db 1 db3 db 4 db 5 db 6 db 2 db f ? input frequency ? mhz in 91 92 93 95 10 30 50 70 90 110 130 150 170 210 230 sfdr ? dbc 190 87 88 89 90 83 84 85 86 79 80 81 82 94 3 db 0 db input adjusted to -1 dbfs for each gain setting 2 db 1 db 5 db 6 db 4 db
ads5546 slws183c ? november 2005 ? revised october 2006 typical characteristics (continued) all plots are at 25 c, avdd = drvdd = 3.3 v, sampling frequency = 190 msps, sine wave input clock, 1.5 v pp differential clock amplitude, 50% clock duty cycle, ?1 dbfs differential analog input, internal reference mode, 0 db gain, ddr lvds data output (unless otherwise noted) performance vs avdd performance vs drvdd figure 27. figure 28. snr vs sampling frequency performance vs temperature across power scaling modes figure 29. figure 30. power dissipation vs performance vs sampling frequency input amplitude figure 31. figure 32. 26 submit documentation feedback www .ti.com drv ? supply v dd oltage ? v 85 86 87 88 89 90 3.0 3.1 3.2 3.3 3.4 3.5 3.6 sfdr ? dbc 72.4 72.872.0 73.2 73.6 74.0 snr ? dbfs snr sfdr f = 70 mhz av in dd = 3.3 v av supply voltage v dd - - sfdr dbc - snr dbfs - 88 90 89 86 73.3 3.6 3.3 3.2 3.1 3 3.5 3.4 85 73.2 sfdr snr 87 73.6 73.1 73.4 73.5 f = 70 mhz drv = 3.3 v in dd 85 86 87 88 89 90 sfdr ? dbc 73.5 7473 74.5 75 75.5 snr ? dbfs snr sfdr t ? free-air t a emperature ? c o ?40 10 35 85 f = 70 mhz in 50 ?15 f ? sampling frequency ? msps s 66 67 68 69 70 71 72 73 74 40 60 80 100 120 140 160 180 200 snr ? dbfs f = 70 mhz in power mode 3 power mode 2 default power mode 1 input amplitude ? dbfs 25 35 45 55 65 75 85 95 105 ?60 ?50 ?40 ?30 ?20 ?10 0 f = 10 mhz in sfdr ? dbc, dbfs 73.3 73.573.0 73.8 74.0 75.0 snr ? dbfs snr sfdr (dbc) sfdr (dbfs) 74.3 74.5 74.8 f ? sampling frequency ? msps s 0.61 0.66 0.71 0.76 0.81 0.86 0.91 0.96 1.01 1.06 1.11 1.16 1.21 0 20 40 60 80 100 120 140 160 180 200 p ? power dissipation ? w d power mode 1 power mode 2 power mode 3 l vds mode default
ads5546 slws183c ? november 2005 ? revised october 2006 typical characteristics (continued) all plots are at 25 c, avdd = drvdd = 3.3 v, sampling frequency = 190 msps, sine wave input clock, 1.5 v pp differential clock amplitude, 50% clock duty cycle, ?1 dbfs differential analog input, internal reference mode, 0 db gain, ddr lvds data output (unless otherwise noted) performance vs clock amplitude performance vs input clock duty cycle figure 33. figure 34. output noise histogram with inputs shorted to common-mode performance in external reference mode figure 35. figure 36. common-mode rejection ratio vs frequency figure 37. 27 submit documentation feedback www .ti.com 74 75 76 77 78 79 80 81 82 83 84 0.34 0.64 0.94 1.24 1.54 1.84 2.14 2.44 2.74 clock amplitude - v pp sfdr - dbc 70 71 72 73 74 75 snr snr - dbfs f = 150 mhz sine wave input clock in sfdr input clock duty cycle ? % 80 82 84 86 88 90 30 35 40 45 50 55 60 sfdr ? dbc 73.5 74.073.0 74.5 75.0 75.5 snr ? dbfs sfdr f = 10 mhz in snr 65 voltage forced on the cm pin ? v 80 82 84 86 88 90 1.4 1.45 1.5 1.55 1.6 sfdr ? dbc 72 7371 74 75 76 snr ? dbfs sfdr snr output code 0 5 10 15 20 25 30 35 occurence ? % 8193 8194 8195 8196 8197 8198 8199 8200 8192 8191 8190 f - frequency of ac common-mode voltage - mhz -70 -65 -60 -45 -40 -35 0 20 40 60 80 100 cmrr ? dbc -55 -50
ads5546 slws183c ? november 2005 ? revised october 2006 typical characteristics (continued) all plots are at 25 c, avdd = drvdd = 3.3 v, sampling frequency = 190 msps, sine wave input clock, 1.5 v pp differential clock amplitude, 50% clock duty cycle, ?1 dbfs differential analog input, internal reference mode, 0 db gain, ddr lvds data output (unless otherwise noted) figure 38. snr contour in dbfs figure 39. sfdr contour in dbc 28 submit documentation feedback www .ti.com 60 62 62 64 64 66 66 66 68 68 68 70 70 70 72 72 72 73 73 73 74 74 74 70 50 100 150 200 250 300 350 400 450 500 56 58 60 62 64 66 68 70 72 74 10 65 100 120 140 160 190 snr - dbfs f - sampling frequency - msps s f - input frequency - mhz in 180 80 50 55 55 60 60 60 65 65 65 70 70 70 70 75 75 75 75 80 80 80 85 85 85 85 85 85 85 70 70 90 90 85 90 90 90 90 10 100 150 200 250 300 350 400 450 500 65 100 120 140 160 190 45 50 55 60 65 70 75 80 85 90 95 sfdr - dbc f - sampling frequency - msps s f - input frequency - mhz in 180 80 50
application information theory of operation analog input ads5546 slws183c ? november 2005 ? revised october 2006 ads5546 is a low power 14-bit 190 msps pipeline adc in a cmos process. ads5546 is based on switched capacitor technology and runs off a single 3.3-v supply. the conversion process is initiated by a rising edge of the external input clock. once the signal is captured by the input sample and hold, the input sample is sequentially converted by a series of lower resolution stages, with the outputs combined in a digital correction logic block. at every clock edge, the sample propagates through the pipeline resulting in a data latency of 14 clock cycles. the output is available as 14-bit data, in ddr lvds or cmos and coded in either straight offset binary or binary 2?s complement format. the analog input consists of a switched-capacitor based differential sample and hold architecture, shown in figure 40 . this differential topology results in good ac-performance even for high input frequencies at high sampling rates. the inp and inm pins have to be externally biased around a common-mode voltage of 1.5 v available on vcm pin 13. for a full-scale differential input, each input pin inp, inm has to swing symmetrically between vcm + 0.5 v and vcm ? 0.5 v, resulting in a 2-v pp differential input swing. the maximum swing is determined by the internal reference voltages refp (2.5 v nominal) and refm (0.5 v, nominal). figure 40. input stage the input sampling circuit has a 3-db bandwidth that extends up to 500 mhz, see figure 41 (measured from the input pins to the voltage across the sampling capacitors). 29 submit documentation feedback www .ti.com resr 200 w lpkg 6 nh 25 w sampling capacitor csamp 3.2 pf inp inm cbond 2 pf 50 w cpar1 0.8 pf ron 10 w cpar2 1 pf ron 15 w ron 15 w cpar2 1 pf 50 w 4 pf lpkg 6 nh 25 w cbond 2 pf resr 200 w csamp 3.2 pf sampling capacitor sampling switch sampling switch r-c-r filter
drive circuit requirements example drive circuits ads5546 slws183c ? november 2005 ? revised october 2006 application information (continued) transfer function - adc only adc input impedance, z i figure 41. analog input bandwidth (data from actual figure 42. impedance looking into inp, inm (data from silicon) simulation) a 5- w resistor in series with each input pin is recommended to damp out ringing caused by the package parasitics. it is also necessary to present a low impedance (< 50 w ) for the common-mode switching currents. for example, this is achieved by using two resistors from each input terminated to the common-mode voltage (vcm). in addition to the above adc requirements, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency range and matched impedance to the source. for this, the adc input impedance has to be considered, see figure 42 . a configuration suitable for low input frequency ranges (< 100 mhz) is shown in figure 43 . note the 5- w series resistors and the low common-mode impedance (using 25- w resistors terminated to vcm). in addition, the circuit has low insertion loss, and good impedance match at low input frequencies, see figure 44 . figure 43. configuration for low input frequencies 30 submit documentation feedback www .ti.com -16 -10 -8 -6 -2 0 magnitude ? db f ? frequency ? mhz 0 500 700 1000 900 100 2 -4 -12 -14 300 200 400 600 800 0 150 250 300 400 450 magnitude ? w f ? frequency ? mhz 0 500 700 1000 900 100 500350 100 50 300 200 400 600 800 200 inpinm vcm adt1-1t 1:1 s11, z i ads5546 25 w 25 w 5 w 0.1 f m 0.1 f m 5 w
ads5546 slws183c ? november 2005 ? revised october 2006 application information (continued) figure 44. s11, input impedance and transfer function for the configuration in figure 43 for high input frequencies, the previous configuration has been modified to improve the insertion loss and impedance matching (see figure 45 ). the s11 curve shows that the matching is good from 100 mhz to 300 mhz. 31 submit documentation feedback www .ti.com -9 -7 -1 1 magnitude ? db f ? frequency ? mhz transfer function ? source to adc output (including the transformer) 0 250 3 -5 50 100 150 200 -3 -70 -60 -20 -10 s11 ? db f ? frequency ? mhz s11 0 250 0 -40 50 100 150 200 -30-50 frequency = 100 mhz s(1, 1) = 0.11/-1.19e2 impedance = 44.07 - j8.63 s(1, 1) frequency (100 khz to 500 mhz)
ads5546 slws183c ? november 2005 ? revised october 2006 application information (continued) a. includes transformer leakage inductances. figure 45. configuration for higher input frequencies figure 46. s11, input impedance and transfer function for the configuration in figure 45 32 submit documentation feedback www .ti.com tc4-1w tc4-1w 1:2 2:1 0.1 f m inpinm vcm ads5546 50 w 50 w 0.1 f m 12 nh (note a) 5 w 5 w s11, z i 12 nh (note a) -10 -8 -2 0 magnitude ? db f ? frequency ? mhz transfer function ? source to adc output (including the transformer) 0 500 2 -6 50 250 350 450 -4 -25 -20 -5 s1 1 ? db f ? frequency ? mhz s11 0 1000 0 -15 100 500 700 900 -10 100 150 200 300 400 200 300 400 600 800 frequency = 200 mhz s(1, 1) = 0.09/50.92 impedance = 55.57 + j8.03 s(1, 1) frequency (100 khz to 500 mhz)
using rf transformer-based drive circuits input common-mode (1) reference ads5546 slws183c ? november 2005 ? revised october 2006 application information (continued) for optimum performance, the analog inputs must be driven differentially. this improves the common-mode noise immunity and even order harmonic rejection. some examples of input configurations using rf transformers suitable for low and high input frequencies are shown in figure 45 and figure 46 . the single-ended signal is fed to the primary winding of the rf transformer. the transformer is terminated on the secondary side. putting the termination on the secondary side helps to shield the kickbacks caused by the sampling circuit from the rf transformer?s leakage inductances. the termination is accomplished by two resistors connected in series, with the center point connected to the 1.5 v common-mode (vcm pin 13). the value of the termination resistors (connected to common-mode) has to be low (< 100 w ) to provide a low-impedance path for the adc common-mode switching current. at high input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. connecting two identical rf transformers back-to-back helps minimize this mismatch, and good performance is obtained for high frequency input signals. an additional termination resistor pair (enclosed within the shaded box in figure 45 ) may be required between the two transformers to improve the balance between the p and m sides. the center point of this termination must be connected to ground. (note that the drive circuit has to be tuned to account for this additional termination, to get the desired s11 and impedance match). to ensure a low-noise common-mode reference, the vcm pin is filtered with a 0.1- m f low-inductance capacitor connected to ground. the vcm pin is designed to directly drive the adc inputs. the input stage of the adc sinks a common-mode current in the order of 310 m a (at 190 msps). equation 1 describes the dependency of the common-mode current and the sampling frequency. this equation helps to design the output capability and impedance of the cm driving circuit accordingly. ads5546 has built-in internal references refp and refm, requiring no external components. design schemes are used to linearize the converter load seen by the references; this and the integration of the requisite reference capacitors on-chip eliminates the need for external decoupling. the full-scale input range of the converter can be controlled in the external reference mode as explained below. the internal or external reference modes can be selected by controlling the mode pin 23 (see table 7 for details) or by programming the serial interface register bit . 33 submit documentation feedback www .ti.com 190 msps (310 a m ) x fs
internal reference external reference (2) low sampling frequency operation ads5546 slws183c ? november 2005 ? revised october 2006 application information (continued) figure 47. reference section when the device is in internal reference mode, the refp and refm voltages are generated internally. common-mode voltage (1.5 v nominal) is output on vcm pin, which can be used to externally bias the analog input pins. when the device is in external reference mode, the vcm acts as a reference input pin. the voltage forced on the vcm pin is buffered and gained by 1.33 internally, generating the refp and refm voltages. the differential input voltage corresponding to full-scale is given by equation 2 . in this mode, the 1.5 v common-mode voltage to bias the input pins has to be generated externally. there is no change in performance compared to internal reference mode. for best performance at high sampling frequencies, ads5546 uses a clock generator circuit to derive internal timing for the adc. the clock generator operates from 190 msps down to 50 msps in the default speed mode. the adc enters this mode after applying reset (with serial interface configuration) or by tying sclk pin to low (with parallel configuration). for low sampling frequencies (below 50 msps), the adc must be put in the low speed mode. this mode can be entered by: setting the register bit through the serial interface, or tying the sclk pin to high (see table 3 ) using the parallel configuration. 34 submit documentation feedback www .ti.com s0165-01 vcm refmrefp intref intref extref internal reference ads5546 full?scale differential input pp (voltage forced on vcm) 1.33
clock input ads5546 slws183c ? november 2005 ? revised october 2006 application information (continued) ads5546 clock inputs can be driven differentially (sine, lvpecl or lvds) or single-ended (lvcmos), with little or no difference in performance between configurations. the common-mode voltage of the clock inputs is set to vcm using internal 5-k w resistors as shown in figure 48 . this allows the use of transformer-coupled drive circuits for sine wave clock, or ac-coupling for lvpecl, lvds clock sources (figure 49 and figure 50 ) figure 48. internal clock buffer for best performance, it is recommended to drive the clock inputs differentially, reducing susceptibility to common-mode noise. in this case, it is best to connect both clock inputs to the differential input clock signal with 0.1- m f capacitors, as shown in figure 49 . figure 49. differential clock driving circuit 35 submit documentation feedback www .ti.com s0166-01 clkp vcm 5 k w 5 k w clkm vcm ads5546 clkpclkm differential sine-wave or pecl or lvds clock input ads5546 0.1 f m 0.1 f m
clock buffer gain ads5546 slws183c ? november 2005 ? revised october 2006 application information (continued) a single-ended cmos clock can be ac-coupled to the clkp input, with clkm (pin 11) connected to ground with a 0.1- m f capacitor, as shown in figure 50 . figure 50. single-ended clock driving circuit for best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode noise. for high input frequency sampling, the use a clock source with very low jitter is recommended. bandpass filtering of the clock source can help reduce the effect of jitter. there is no change in performance with a non-50% duty cycle clock input. figure 34 shows the performance variation of the adc versus clock duty cycle when using a sinusoidal clock input, the noise contributed by clock jitter improves as the clock amplitude is increased. therefore, using a large amplitude clock is recommended. in addition, the clock buffer has a programmable gain option to amplify the input clock. the clock buffer gain can be set by programming the register bits . the clock buffer gain decreases monotonically from gain 4 to gain 0 settings. 36 submit documentation feedback www .ti.com clkpclkm cmos clock input ads5546 0.1 f m 0.1 f m
programmable gain power down ads5546 slws183c ? november 2005 ? revised october 2006 application information (continued) table 9. clock buffer gain programming register address register data description a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 ? clock buffer gain programmability, gain decreases monotonically from gain 4 to gain 0 0 1 1 0 1 0 1 1 0 0 1 1 0 0 1 0 gain 4 0 1 1 0 1 0 1 1 0 0 1 0 1 0 1 0 gain 3 0 1 1 0 1 0 1 1 0 0 1 0 0 1 1 0 gain 2 0 1 1 0 1 0 1 1 0 0 1 0 0 0 0 0 gain 1 default gain 0 1 1 0 1 0 1 1 0 0 1 0 0 0 1 1 gain 0 minimum gain ads5546 has programmable gain from 0 db to 6 db in steps of 1 db. the corresponding full-scale input range varies from 2 v pp down to 1 v pp , with 0 db being the default gain. at high if, this is especially useful as the sfdr improvement is significant with marginal degradation in snr. the gain can be programmed using the serial interface (bits d3-d0 in register 0x68). table 10. programmable gain register address register data description a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 gain programming - channel gain can be programmed from 0 to 6 db for sfdr/snr trade-off. for each gain setting, the input full-scale range has to be proportionally scaled. for 6 db gain, the full-scale range will be 1 v pp compared to 2 v pp at 0 db gain. 0 1 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 db default after reset 0 1 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1 db 0 1 1 0 1 0 0 0 0 0 0 0 1 0 1 0 2 db 0 1 1 0 1 0 0 0 0 0 0 0 1 0 1 1 3 db 0 1 1 0 1 0 0 0 0 0 0 0 1 1 0 0 4 db 0 1 1 0 1 0 0 0 0 0 0 0 1 1 0 1 5 db 0 1 1 0 1 0 0 0 0 0 0 0 1 1 1 0 6 db ads5546 has three power-down modes ? global standby, output buffer disabled, and input clock stopped. global standby this mode can be initiated by controlling sdata (pin 28) or by setting the register bit through the serial interface. in this mode, the a/d converter, reference block and the output buffers are powered down and the total power dissipation reduces to about 100 mw. the output buffers are in high impedance state. the wake-up time from the global power down to data becoming valid normal mode is maximum 100 m s. output buffer disable the output buffers can be disabled using oe pin 7 in both the lvds and cmos modes, reducing the total power by about 100 mw. with the buffers disabled, the outputs are in high impedance state. the wake-up time from this mode to data becoming valid in normal mode is maximum 1 m s in lvds mode and 50 ns in cmos mode. input clock stop the converter enters this mode when the input clock frequency falls below 1 msps. the power dissipation is about 100 mw and the wake-up time from this mode to data becoming valid in normal mode is maximum 100 m s. 37 submit documentation feedback www .ti.com
power scaling modes power supply sequence ads5546 slws183c ? november 2005 ? revised october 2006 ads5546 has a power scaling mode in which the device can be operated at reduced power levels at lower sampling frequencies with no difference in performance. (see figure 30 ) (1) there are four power scaling modes for different sampling clock frequency ranges, using the serial interface register bits . only the avdd power is scaled, leaving the drvdd power unchanged. table 11. power scaling vs sampling speed sampling frequency analog power power scaling mode analog power in default mode msps (typical) > 150 default 960 mw at 190 msps 960 mw at 190 msps 105 to 150 power mode 1 841 mw at 150 msps 917 mw at 150 msps 50 to 105 power mode 2 670 mw at 105 msps 830 mw at 105 msps < 50 power mode 3 525 mw at 50 msps 760 mw at 50 msps (1) the performance in the power scaling modes is from characterization and not tested in production. register address register data description a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 power scaling vs sampling frequency. the adc can be operated at reduced power at lower sampling rates with no loss in performance. 0 1 1 0 1 1 0 1 0 0 1 0 0 0 0 0 default fs > 150 msps default after reset power mode1 105 < fs 150 0 1 1 0 1 1 0 1 1 0 1 0 0 0 0 0 msps power mode2 50 < fs 105 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 0 msps 0 1 1 0 1 1 0 1 1 1 1 0 0 0 0 0 power mode3 fs 50 msps during power-up, the avdd and drvdd supplies can come up in any sequence. the two supplies are separated inside the device. externally, they can be driven from separate supplies or from a single supply. 38 submit documentation feedback www .ti.com
digital output information output interface ddr lvds outputs ads5546 slws183c ? november 2005 ? revised october 2006 ads5546 provides 14-bit data, an output clock synchronized with the data and an out-of-range indicator that goes high when the output reaches the full-scale limits. in addition, output enable control (oe pin 7) is provided to power down the output buffers and put the outputs in high-impedance state. two output interface options are available ? double data rate (ddr) lvds and parallel cmos. they can be selected using the dfs (see table 6 ) or the serial interface register bit . in this mode, the 14 data bits and the output clock are available as lvds (low voltage differential signal) levels. two successive data bits are multiplexed and output on each lvds differential pair as shown in figure 51 . so, there are 7 lvds output pairs for the 14 data bits and 1 lvds output pair for the output clock. figure 51. ddr lvds outputs 39 submit documentation feedback www .ti.com s0169-01 clkoutpd0_d1_p d2_d3_p d4_d5_p d6_d7_p d8_d9_p d10_d11_p d12_d13_p ovr pins output clockdata bits d0. d1 data bits d2, d3 data bits d4, d5 data bits d6, d7 data bits d8, d9 data bits d10, d11 data bits d12, d13 out-of-range indicator clkoutmd0_d1_m d2_d3_m d4_d5_m d6_d7_m d8_d9_m d10_d11_m d12_d13_m ads5546
lvds buffer current programmability ads5546 slws183c ? november 2005 ? revised october 2006 even data bits d0, d2, d4, d6, d8, d10, and d12 are output at the falling edge of clkoutp and the odd data bits d1, d3, d5, d7, d9, d11, and d13 are output at the rising edge of clkoutp. both the rising and falling edges of clkoutp have to be used to capture all the 14 data bits (see figure 52 ). figure 52. ddr lvds interface the default lvds buffer output current is 3.5 ma. when terminated by 100 w , this results in a 350-mv single-ended voltage swing (700-mv pp differential swing). the lvds buffer currents can also be programmed to 2.5 ma, 4.5 ma, and 1.75 ma using the serial interface. in addition, there exists a current double mode, where this current is doubled for the data and output clock buffers. 40 submit documentation feedback www .ti.com t0110-01 clkoutp d0_d1_p, d0_d1_m d2_d3_p, d2_d3_m d4_d5_p, d4_d5_m d6_d7_p, d6_d7_m d8_d9_p, d8_d9_m d10_d11_p, d10_d11_m d12_d13_p, d12_d13_m d0d2 d4 d6 d8 d10d12 sample n+1 sample n d0d2 d4 d6 d8 d10d12 d1d3 d5 d7 d9 d11 d13 d1d3 d5 d7 d9 d11 d13 clkoutm
lvds buffer internal termination ads5546 slws183c ? november 2005 ? revised october 2006 table 12. lvds buffer currents programming register address register data description a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 ? output data and clock buffers current programmability 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 3.5 ma default after reset 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 2.5 ma 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 4.5 ma 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1.75 ma ? the output data and clock buffer currents are doubled from the value selected by the register. value specified by default after reset 0 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 2x data, 2x clock currents 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1x data, 2x clock currents 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 2x data, 4x clock currents an internal termination option is available (using the serial interface), by which the lvds buffers are differentially terminated inside the device. the termination resistances available are ? 325, 200, and 170 w (nominal with 20% variation). any combination of these three terminations can be programmed; the effective termination is the parallel combination of the selected resistances. this results in eight effective terminations from open (no termination) to 75 w . the internal termination helps to absorb any reflections coming from the receiver end, improving the signal integrity. with 100- w internal and 100- w external termination, the voltage swing at the receiver end is halved (compared to no internal termination). the voltage swing can be restored by using the lvds current double mode (see table 12 ). table 13. programming internal termination for lvds data and clock register address register data description a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 internal termination - option to terminate the lvds data buffers inside the adc to improve signal integrity. by default, internal termination is disabled. 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 no termination default after reset 0 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 325 w 0 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 200 w 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 125 w 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 170 w 0 1 1 1 1 1 1 0 1 0 1 0 0 0 0 0 120 w 0 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 100 w 0 1 1 1 1 1 1 0 1 1 1 0 0 0 0 0 75 w internal termination ? option to terminate the lvds clk buffers inside the adc to improve signal integrity. by default, internal termination is disabled. 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 no termination default after reset 0 1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 325 w 0 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 200 w 0 1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 125 w 0 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 170 w 0 1 1 1 1 1 1 0 0 0 0 1 0 1 0 0 120 w 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 100 w 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 75 w 41 submit documentation feedback www .ti.com
parallel cmos output clock position programmability output data format ads5546 slws183c ? november 2005 ? revised october 2006 in this mode, the 14 data outputs and the output clock are available as 3.3-v cmos voltage levels. each data bit and the output clock is available on a separate pin in parallel. by default, the data outputs are valid during the rising edge of the output clock. the output clock is clkout (pin 5). in both the lvds and cmos modes, the output clock can be moved around its default position. this can be done using sen pin 27 (as described in table 5 ) or using the serial interface register bits . using this allows to trade-off the setup and hold times leading to reliable data capture. there also exists an option to align the output clock edge with the data transition. note that programming the output clock position also affects the clock propagation delay times. table 14. clkout position programing register address register data description a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 ? output clock rising edge programmability in cmos mode 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 default position 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 1 output clock rising edge later by (1/12)ts 0 1 1 0 0 0 1 0 0 0 0 0 0 1 0 1 output clock rising edge later by (3/12)ts 0 1 1 0 0 0 1 0 0 0 0 0 0 1 1 1 output clock rising edge later by (2/12)ts ? output clock falling edge programmability in cmos mode 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 default position 0 1 1 0 0 0 1 0 0 0 0 0 1 0 0 1 output clock falling edge later by (1/12)ts 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 1 output clock falling edge later by (3/12)ts 0 1 1 0 0 0 1 0 0 0 0 1 1 0 0 1 output clock falling edge later by (2/12)ts ? output clock rising edge programmability in lvds mode 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 default position 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 1 output clock rising edge earlier by (1/12)ts 0 1 1 0 0 0 1 0 0 0 0 0 0 1 0 1 output clock rising edge aligned with data transition 0 1 1 0 0 0 1 0 0 0 0 0 0 1 1 1 output clock rising edge aligned with data transition ? output clock falling edge programmability in lvds mode 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 default position 0 1 1 0 0 0 1 0 0 0 0 0 1 0 0 1 output clock falling edge earlier by (1/12)ts 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 1 output clock falling edge aligned with data transition 0 1 1 0 0 0 1 0 0 0 0 1 1 0 0 1 output clock falling edge aligned with data transition two output data formats are supported ? 2's complement and offset binary. they can be selected using the dfs (pin 6) or the serial interface register bit . in the event of an input voltage overdrive, the digital outputs go to the appropriate full scale level. for a positive overdrive, the output code is 0x3fff in offset binary output format, and 0x1fff in 2's complement output format. for a negative input overdrive, the output code is 0x0000 in offset binary output format and 0x2000 in 2's complement output format. 42 submit documentation feedback www .ti.com
output timing ads5546 slws183c ? november 2005 ? revised october 2006 for the best performance at high sampling frequencies, ads5546 uses a clock generator circuit to derive internal timing for adc. this results in optimal setup and hold times of the output data and 50% output clock duty cycle for sampling frequencies from 80 msps to 190 msps. see table 15 for timing information above 80 msps. table 15. timing characteristics (80 msps to 190 msps) (1) t su data setup time, ns t h data hold time, ns t pdi clock propagation delay, ns fs, msps min typ max min typ max min typ max ddr lvds 190 1.3 1.8 0.5 1 3.9 4.6 5.3 150 1.6 2.1 0.6 1.1 4.3 5 5.7 130 2.0 2.5 0.8 1.3 4.5 5.2 5.9 80 3.6 4.1 1.6 2.1 4.7 5.7 6.7 parallel cmos 190 2.5 3.3 0.8 1.2 1.9 2.7 3.5 150 2.8 3.6 1.2 1.6 1.7 2.5 3.3 130 3.3 4.1 1.7 2.1 1.1 1.9 2.7 80 6 7 3.7 4.1 10.8 12 13.2 (1) timing parameters are specified by design and characterization and not tested in production. below 80 msps, the setup and hold times do not scale with the sampling frequency. the output clock duty cycle also progressively moves away from 50% as the sampling frequency is reduced from 80 msps. see table 16 for detailed timings at sampling frequencies below 80 msps. figure 53 shows the clock duty cycle across sampling frequencies in the ddr lvds and cmos modes. table 16. timing characteristics (1 msps to 80 msps) (1) t su data setup time, ns t h data hold time, ns t pdi clock propagation delay, ns fs, msps min typ max min typ max min typ max ddr lvds 1 to 80 3.6 1.6 5.7 parallel cmos 1 to 80 6 3.7 12 (1) timing parameters are specified by design and characterization and not tested in production. figure 53. output clock duty cycle (typical) vs sampling frequency the latency of ads5546 is 14 clock cycles from the sampling instant (input clock rising edge). in the lvds mode, the latency remains constant across sampling frequencies. in the cmos mode, the latency is 14 clock cycles above 80 msps and 13 clock cycles below 80 msps. 43 submit documentation feedback www .ti.com sampling frequency ? mhz 0 10 30 50 70 100 60 80 140 160 180 output clock duty cycle ? % cmos ddr lvds 0 20 40 100 120 20 40 60 9080
definition of specifications analog bandwidth aperture delay aperture uncertainty (jitter) clock pulse width/duty cycle maximum conversion rate minimum conversion rate differential nonlinearity (dnl) integral nonlinearity (inl) gain error offset error temperature drift ads5546 slws183c ? november 2005 ? revised october 2006 the analog input frequency at which the power of the fundamental is reduced by 3 db with respect to the low frequency value. the delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. the sample-to-sample variation in aperture delay. the duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. duty cycle is typically expressed as a percentage. a perfect differential sine-wave clock results in a 50% duty cycle. the maximum sampling rate at which certified operation is given. all parametric testing is performed at this sampling rate unless otherwise noted. the minimum sampling rate at which the adc functions. an ideal adc exhibits code transitions at analog input values spaced exactly 1 lsb apart. the dnl is the deviation of any single step from this ideal value, measured in units of lsbs the inl is the deviation of the adc?s transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of lsbs. the gain error is the deviation of the adc?s actual input full-scale range from its ideal value. the gain error is given as a percentage of the ideal input full-scale range. the offset error is the difference, given in number of lsbs, between the adc?s actual average idle channel output code and the ideal average idle channel output code. this quantity is often mapped into mv. the temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree celsius of the parameter from t min to t max . it is calculated by dividing the maximum deviation of the parameter across the t min to t max range by the difference t max ?t min . 44 submit documentation feedback www .ti.com
signal-to-noise ratio (3) signal-to-noise and distortion (sinad) (4) effective number of bits (enob) (5) total harmonic distortion (thd) (6) spurious-free dynamic range (sfdr) two-tone intermodulation distortion dc power supply rejection ratio (dc psrr) ads5546 slws183c ? november 2005 ? revised october 2006 definition of specifications (continued) snr is the ratio of the power of the fundamental (p s ) to the noise floor power (p n ), excluding the power at dc and the first nine harmonics. snr is either given in units of dbc (db to carrier) when the absolute power of the fundamental is used as the reference, or dbfs (db to full scale) when the power of the fundamental is extrapolated to the converter?s full-scale range. sinad is the ratio of the power of the fundamental (p s ) to the power of all the other spectral components including noise (p n ) and distortion (p d ), but excluding dc. sinad is either given in units of dbc (db to carrier) when the absolute power of the fundamental is used as the reference, or dbfs (db to full scale) when the power of the fundamental is extrapolated to the converter?s full-scale range. the enob is a measure of a converter?s performance as compared to the theoretical limit based on quantization noise. thd is the ratio of the power of the fundamental (p s ) to the power of the first nine harmonics (p d ). thd is typically given in units of dbc (db to carrier). the ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). sfdr is typically given in units of dbc (db to carrier). imd3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral component at either frequency 2f1?f2 or 2f2?f1. imd3 is either given in units of dbc (db to carrier) when the absolute power of the fundamental is used as the reference, or dbfs (db to full scale) when the power of the fundamental is extrapolated to the converter?s full-scale range. the dc pssr is the ratio of the change in offset error to a change in analog supply voltage. the dc psrr is typically given in units of mv/v. 45 submit documentation feedback www .ti.com snr 10log 10 p s p n sinad 10log 10 p s p n p d enob sinad 1.76 6.02 thd 10log 10 p s p n
ac power supply rejection ratio (ac psrr) (7) common mode rejection ratio (cmrr) (8) voltage overload recovery ads5546 slws183c ? november 2005 ? revised october 2006 definition of specifications (continued) ac psrr is the measure of rejection of variations in the supply voltage of the adc. if d v sup is the change in the supply voltage and d v out is the resultant change in the adc output code (referred to the input), then cmrr is the measure of rejection of variations in the input common-mode voltage of the adc. if d vcm is the change in the input common-mode voltage and d v out is the resultant change in the adc output code (referred to the input), then the number of clock cycles taken to recover to less than 1% error for a 6-db overload on the analog inputs. a 6-dbfs sine wave at nyquist frequency is used as the test stimulus. 46 submit documentation feedback www .ti.com (expressed in dbc) d v sup d v out 10 psrr = 20log (expressed in dbc) d v cm d v out 10 cmrr = 20log
ads5546 slws183c ? november 2005 ? revised october 2006 ads5546 revision history revision date description a 11/05 added new graphs to the typical characteristics. b 6/06 new timing characteristics table. new text for the device mode configuration parallel pin control section changed to parallel configuration only section. added serial interface configuration only section. added configuration using both the serial interface and parallel controls new text for the serial interface section added register reset section additions to table 8 , and revised typical characteristics graphs. added programmable gain section in the application information added default and low speed modes to the clock input of the recommended operating c 10/06 conditions changed the max standby power specifications. changed the max clock stop power specifications. changed analog input information and figures. changed drive circuit and example drive circuit information and figures. added using rf transformer-based drive circuits information. 47 submit documentation feedback www .ti.com
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) ADS5546IRGZR active qfn rgz 48 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr ADS5546IRGZRg4 active qfn rgz 48 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr ads5546irgzt active qfn rgz 48 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr ads5546irgztg4 active qfn rgz 48 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr pads5546irgzt preview qfn rgz 48 tbd call ti call ti (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 6-dec-2006 addendum-page 1

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