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wed416s8030a 1 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com description the wed416s8030a is 134,217,728 bits of synchronous high data rate dram organized as 4 x 2,097,152 words x 16 bits. synchronous design allows precise cycle control with the use of system clock, i/o transactions are possible on every clock cycle. range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. available in a 54 pin tsop type ii package the wed416s8030a is tested over the industrial temp range (-40 c to +85 c) providing a solution for rugged main memory applications. 2m x 16 bits x 4 banks synchronous dram features single 3.3v power supply fully synchronous to positive clock edge clock frequency = 100, 83mhz sdram cas latency = 3 (100mhz), 2 (83mhz) burst operation sequential or interleave burst length = programmable 1,2,4,8 or full page burst read and write multiple burst read and single write data mask control per byte auto refresh (cbr) and self refresh 4096 refresh cycles across 64ms automatic and controlled precharge commands suspend mode and power down mode industrial temperature range fig. 1 pin description pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v ss dq 15 v ssq dq 14 dq 13 v ddq dq 12 dq 11 v ssq dq 10 dq 9 v ddq dq 8 v ss nc/rfu udqm clk cke nc a 11 a 9 a 8 a 7 a 6 a 5 a 4 v ss v dd dq 0 v ddq dq 1 dq 2 v ssq dq 3 dq 4 v ddq dq 5 dq 6 v ssq dq 7 v dd ldqm we cas ras ce ba 0 ba 1 a 10 /ap a 0 a 1 a 2 a 3 v dd terminal connections (top veiw) june 2000 rev. 0 eco# 12861 a 0-11 address inputs ba 0, ba 1 bank select addresses ce chip select we write enable clk clock input cke clock enable dq 0-15 data input/output l(u)dqm data input/output mask ras row address strobe cas column address strobe v dd power (3.3v) v ddq data output power v ss ground v ssq data output ground nc no connection
2 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com wed416s8030a june 2000 rev. 0 input/output functional description symbol type signal polarity function clk input pulse positive edge the system clock input. all of the sdram inputs are sampled on the rising edge of the clock. cke input level active high activates the clk signal when high and deactivates the clk signal when low. by deactivating the clock, cke low initiates the power down mode, suspend mode, or the self refresh mode. ce input pulse active low ce disable or enable device operation by masking or enabling all inputs except clk, cke and dqm. ras, cas input pulse active low when sampled at the positive rising edge of the clock, cas, ras, and we define the operation to be we executed by the sdram. ba 0 ,ba 1 input level selects which sdram bank is to be active. during a bank activate command cycle, a 0-11 defines the row address (ra 0-11 ) when sampled at the rising clock edge. during a read or write command cycle, a 0-8 defines the column address (ca 0-8 ) when sampled at the a 0-11 , rising clock edge. in addition to the row address, a 10 /ap is used to invoke autoprecharge operation at a 10 /ap input level the end of the burst read or write cycle. if a 10 /ap is high, autoprecharge is selected and ba 0 , ba 1 defines the bank to beprecharged . if a 10 /ap is low, autoprecharge is disabled. during a precharge command cycle, a 10 /ap is used in conjunction with ba 0 , ba 1 to control which bank(s) to precharge. if a 10 /ap is high, all banks will be precharged regardless of the state of ba 0 , ba 1 . if a 10 /ap is low, then ba 0 , ba 1 is used to define which bank to precharge. dq 0-15 input/output level data input/output are multiplexed on the same pins. the data input/output mask places the dq buffers in a high impedance state when sampled high. in l(u)dqm input pulse mask read mode, dqm has a latency of two clock cycles and controls the output buffers like an output enable. active high in write mode, dqm has a latency of zero and operates as a word mask by allowing input data to be written if it is lowbut blocks the write operation if dqm is high. v dd , v ss supply power and ground for the input buffers and the core logic. v ddq , v ssq supply isolated power and ground for the output buffers to improve noise immunity.
3 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com wed416s8030a june 2000 rev. 0 recommended dc operating conditions (voltage referenced to: v ss = 0v, t a = -40 c to +85 c) absolute maximum ratings capacitance (t a = 25 c, f = 1mhz, v dd = 3.3v to 3.6v) parameter symbol min max units power supply voltage v dd -1.0 +4.6 v input voltage v in -1.0 +4.6 v output voltage v out -1.0 +4.6 v operating temperature t opr -40 +85 c storage temperature t stg -55 +125 c power dissipation p d 1.0 w short circuit output current i os 50 ma stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol max unit input capacitance (a 0-11 , ba 0-1 )c i1 4pf input capacitance (clk, cke, ras, c i2 4pf cas, we, ce, dqm) input/output capacitance (dq 0-15 )c out 5pf operating current characteristics (v cc = 3.3v, t a = -40 c to +85 c) parameter symbol test condition -10 -12 units notes operating current (one bank active) i cc1 burst length = 1, t rc t rc (min) 140 125 ma 1 operating current (burst mode) i cc4 page burst, 2 banks active, t ccd = 2 clocks 200 165 ma 1 precharge standby current in power down mode i cc2 p cke v il (max), t c c = 15ns 2 2 ma i cc2 ps cke, clk v il (max), t c c = , inputs stable 2 2 ma i cc1 n cke = v ih , t cc = 15ns 50 50 ma input change every 30ns i cc1 ns cke v ih (min), t c c = 35 35 ma no input change i cc3 p cke v il (max), t c c = 15ns 12 12 ma i cc3 ps cke v il (max), t c c = 12 12 ma i cc2 n cke = v ih , t c c = 15ns 30 30 ma input change every 30ns i cc2 ns cke v ih (min), t cc = , no input change 20 20 ma refresh current i cc5 t rc t rc (min) 210 210 ma 2 self refresh current i cc6 cke 0.2v 3 3 ma notes: 1. measured with outputs open. 2. refresh period is 64ms. precharge standby current in non-power down mode active standby current in non-power down mode active standby current in power down mode parameter symbol min typ max unit notes supply voltage v dd 3.0 3.3 3.6 v input high voltage v ih 2.0 3.0 v dd +0.3 v input low voltage v il -0.3 0.8 v output high voltage v oh 2.4 v (i oh = -2ma) output low voltage v ol 0.4 v (i ol = 2ma) input leakage voltage i il -5 5 a output leakage voltage i ol -5 5 a
4 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com wed416s8030a june 2000 rev. 0 refresh cycle parameters -10 -12 parameter symbol min max min max units notes refresh period t ref ?4?4ms1, 2 self refresh exit time t srex t rfc ? rfc ?s3 notes: 1. 4096 cycles. 2. any time that the refresh period has been exceeded, a minimum of two auto (cbr) refresh commands must be given to "wake-up" t he device. 3. the self refresh is exited by restarting the external clock and then asserting cke high. this must be followed by nops for a minimum time of t rfc before the sdram reaches idle state to begin normal operation. parameter symbol -10 -12 units notes min max min max cas latency = 3 10 1000 12 1000 cas latency = 2 13 1000 15 1000 clock to valid output delay t sac 7 8 ns 1, 2 output data hold time t oh 33ns2 clock high pulse width t ch 3.5 4.0 ns 3 clock low pulse width t cl 3.5 4.0 ns 3 input setup time t ss 2.5 3 ns 3 input hold time t sh 11ns3 clock to output in low-z t slz 11ns2 clock to output in high-z t shz 78ns row active to row active delay t rrd 20 24 ns 4 ras to cas delay t rcd 24 26 ns 4 row precharge time t rp 24 26 ns 4 row active time t ras 50 100,000 60 100,000 ns 4 row cycle time - operation t rc 80 90 ns 4 row cycle time - auto refresh t rfc 80 90 ns 4, 8 last data in to new column address delay t cdl 1 1 clk 5 last data in to row precharge t rdl 1 1 clk 5 last data in to burst stop t bdl 1 1 clk 5 column address to column address delay t ccd 1 1 clk 6 cas latency = 3 2 2 cas latency = 2 1 1 ac characteristics operating ac parameters (v cc = 3.3v, t a = -40 c to +85 c) clock cycle time t cc ns 1 notes: 1. parameters depend on programmed cas latency. 2. if clock rise time is longer than 1ns, (t rise 2-0.5)ns should be added to the parameter. 3. assumed input rise and fall time = 1ns. if t rise & t fall are longer than 1ns, [(t rise + t fall )/2]-1ns should be added to the parameter. 4. the minimum number of clock cycles required is determined by dividing the minimum time required by the clock cycle time and t hen rounding up to the next higher integer. 5. minimum delay is required to complete write. 6. all devices allow every cycle column address changes. 7. in case of row precharge interrupt, auto precharge and read burst stop. 8. a new command may be given t rfc after self refresh exit. number of valid output data ea 7
5 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com wed416s8030a june 2000 rev. 0 clock frequency and latency parameters - 100mhz (units = number of clocks) frequency cas t rc t ras t rp t rrd t rcd t ccd t cdl t rdl 80ns 50ns 24ns 20ns 24ns 10ns 10ns 10ns 100mhz (10ns) 3 8 5 3 2 3 1 1 1 83mhz (12ns) 3 7 5 2 2 2 1 1 1 75mhz (12ns) 2 6 4 2 2 2 1 1 1 66mhz (15ns) 2 6 4 2 2 2 1 1 1 latency clock frequency and latency parameters - 83mhz (units = number of clocks) frequency cas t rc t ras t rp t rrd t rcd t ccd t cdl t rdl 90ns 60ns 26ns 24ns 26ns 12ns 12ns 12ns 83mhz (12ns) 3 8 5 3 2 3 1 1 1 75mhz (13ns) 3 7 5 2 2 2 1 1 1 66mhz (15ns) 2 6 4 2 2 2 1 1 1 latency
6 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com wed416s8030a june 2000 rev. 0 register mode register set h x l l l l x op code refresh auto(cbr) h entry self l precharge single bank h xl l h l x ba l x 2 all banks xh x bank activate h x l l h h x ba row address 2 write auto precharge disable hxlhllxba l2 auto precharge enable h2 read auto precharge disable l2 auto precharge enable h2 burst stop h x l h h l x x x x 3 no operation h x l h h h x x x x device deselect h x h x x x x x x x clock suspend/standby mode l x xxxxxxx x 4 data write/output enable hxxxxx l xx x 5 mask/output disable h 5 power down mode entry x l hxxxxxx x 6 exit h 6 notes: 1. all of the sdram operations are defined by states of ce, we, ras, cas, and dqm at the positive rising edge of the clock. 2. bank select (ba), if ba 0 , ba 1 = 0, 0 then bank a is selected, if ba 0 , ba 1 = 1, 0 then bank b, if ba 0 , ba 1 = 0, 1 then bank c, if ba 0 , ba 1 = 1, 1 then bank d is selected, respectively. 3. during a burst write cycle there is a zero clock delay, for a burst read cycle the delay is equal to the cas latency. 4. during normal access mode, cke is held high and clk is enabled. when it is low, it freezes the internal clock and extends dat a read and write operations. one clock delay is required for mode entry and exit. 5. the dqm has two functions for the data dq read and write operations. during a read cycle, when dqm goes high at a clock timin g the data outputs are disabled and become high impedance after a two clock delay. dqm also provides a data mask function for write cycles. when it ac tivates, the write operation at the clock is prohibited (zero clock latency). 6. all banks must be precharged before entering the power down mode. the power down mode does not perform any refresh operations , therefore the device can't remain in this mode longer than the refresh period (t ref ) of the device. one clock delay is required for mode entry and exit. command cke ce ras cas we dqm ba previous current a 10 /a p a 11 , a 9-0 notes cycle cycle command truth table h lllhxxx x hx l h l h xba column address column address (x = don't care, h = logic high, l = logic low)
7 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com wed416s8030a june 2000 rev. 0 notes: 1. for the given current state cke must be low in the previous cycle. 2. when cke has a low to high transition, the clock and other inputs are re-enabled asynchronously. the minimum setup time for c ke ( tcks ) must be satisfied before any command other than exit is issued. 3. the address inputs (a 12-0 ) depend on the command that is issued. see the idle state section of the current state truth table for more information. 4. the power down mode, self refresh mode, and the mode register set can only be entered from the all banks idle state. must be a legal command as defined in the current state truth table. clock enable (cke 0 ) truth table h x x x x x x x invalid 1 l h h x x x x x exit self refresh with device deselect 2 l h l h h h x x exit self refresh with no operation 2 self refresh l h l h h l x x illegal 2 l h l h l x x x illegal 2 l h l l x x x x illegal 2 l l x x x x x x maintain self refresh h x x x x x x x invalid 1 power down l h h x x x x x power down mode exit, all banks idle 2 l h l x x x x x illegal 2 l l x x x x x x maintain power down mode hh h x x x hh l h x x refer to the idle state section of the 3 hh l l h x current state truth table h h l l l h x x cbr refresh h h l l l l op code mode register set 4 all banks idle h l h x x x hl l h x x refer to the idle state section of the 3 hl l l h x current state truth table h l l l l h x x entry self refresh 4 h l l l l l op code mode register set l x x x x x x x power down 4 hhxx xxxx refer to the operations in the current state truth table any state other h l x x x x x x begin clock suspend next cycle 5 than listed above l h x x x x x x exit clock suspend next cycle l l x x x x x x maintain clock suspend current state cke command action notes previous current ce ras cas we ba a 0-11
8 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com wed416s8030a june 2000 rev. 0 current state truth table l l l l op code mode register set set the mode register 2 l l l h x x auto orself refresh start auto orself refresh 2,3 l l h l x x precharge no operation l l h h ba row address bank activate activate the specified bank and row idle l h l l ba column write w/o precharge illegal 4 l h l h ba column read w/o precharge illegal 4 l h h l x x burst termination no operation l h h h x x no operation no operation h x x x x x device deselect no operation or power down 5 l l l l op code mode register set illegal l l l h x x auto orself refresh illegal l l h l x x precharge precharge 6 l l h h ba row address bank activate illegal 4 row active l h l l ba column write start write; determine if auto precharge 7,8 l h l h ba column read start read; determine if auto precharge 7,8 l h h l x x burst termination no operation l h h h x x no operation no operation h x x x x x device deselect no operation l l l l op code mode register set illegal l l l h x x auto orself refresh illegal l l h l x x precharge terminate burst; start the precharge l l h h ba row address bank activate illegal 4 read l h l l ba column write terminate burst; start the write cycle 8,9 l h l h ba column read terminate burst; start a new read cycle 8,9 l h h l x x burst termination terminate the burst l h h h x x no operation continue the burst h x x x x x device deselect continue the burst l l l l op code mode register set illegal l l l h x x auto orself refresh illegal l l h l x x precharge terminate burst; start the precharge l l h h ba row address bank activate illegal 4 write l h l l ba column write terminate burst; start a new write cycle 8,9 l h l h ba column read terminate burst; start the read cycle 8,9 l h h l x x burst termination terminate the burst l h h h x x no operation continue the burst h x x x x x device deselect continue the burst l l l l op code mode register set illegal l l l h x x auto orself refresh illegal l l h l x x precharge illegal 4 read with l l h h ba row address bank activate illegal 4 auto precharge l h l l ba column write illegal l h l h ba column read illegal l h h l x x burst termination illegal l h h h x x no operation continue the burst h x x x x x device deselect continue the burst current state command action notes ce ras cas we ba a 11 , description a 10 /ap - a 0
9 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com wed416s8030a june 2000 rev. 0 current state truth table (cont.) l l l l op code mode register set illegal l l l h x x auto orself refresh illegal l l h l x x precharge illegal 4 write with l l h h ba row address bank activate illegal 4 auto precharge l h l l ba column write illegal l h l h ba column read illegal l h h l x x burst termination illegal l h h h x x no operation continue the burst h x x x x x device deselect continue the burst l l l l op code mode register set illegal l l l h x x auto orself refresh illegal l l h l x x precharge no operation; bank(s) idle after t rp l l h h ba row address bank activate illegal 4 precharging l h l l ba column write illegal 4 l h l h ba column read illegal 4 l h h l x x burst termination no operation; bank(s) idle after t rp l h h h x x no operation no operation; bank(s) idle after t rp h x x x x x device deselect no operation; bank(s) idle after t rp l l l l op code mode register set illegal l l l h x x auto orself refresh illegal l l h l x x precharge illegal 4 l l h h ba row address bank activate illegal 4,10 row activating l h l l ba column write illegal 4 l h l h ba column read illegal 4 l h h l x x burst termination no operation; row active after t rcd l h h h x x no operation no operation; row active after t rcd h x x x x x device deselect no operation; row active after t rcd l l l l op code mode register set illegal l l l h x x auto orself refresh illegal l l h l x x precharge illegal 4 l l h h ba row address bank activate illegal 4 write recovering l h l l ba column write start write; determine if auto precharge 9 l h l h ba column read start read; determine if auto precharge 9 l h h l x x burst termination no operation; row active after t dpl l h h h x x no operation no operation; row active after t dpl h x x x x x device deselect no operation; row active after t dpl l l l l op code mode register set illegal l l l h x x auto orself refresh illegal l l h l x x precharge illegal 4 write recovering l l h h ba row address bank activate illegal 4 with auto l h l l ba column write illegal 4,9 precharge l h l h ba column read illegal 4,9 l h h l x x burst termination no operation; precharge after t dpl l h h h x x no operation no operation; precharge after t dpl h x x x x x device deselect no operation; precharge after t dpl current state command action notes ce ras cas we ba a 11 , description a 10 /ap - a 0
10 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com wed416s8030a june 2000 rev. 0 notes: 1. cke is assumed to be active (high) in the previous cycle for all entries. the current state is the state of the bank that the command is being applied to. 2. all banks must be idle otherwise it is an illegal action. 3. if cke is active (high) the sdram starts the auto (cbr) refresh operation, if cke is inactive (low) then the self refresh mod e is entered. 4. the current state refers only to one of the banks, if ba 0, ba 1 selects this bank then the action is illegal. if ba 0, ba 1 selects the bank not being referenced by the current state then the action may be legal depending on the state of that bank. 5. if cke is inactive (low) then the power down mode is entered, otherwise there is a no operation. 6. the minimum and maximum active time (t ras ) must be satisfied. 7. the ras to cas delay (t rcd ) must occur before the command is given. 8. address a10 is used to determine if the auto precharge function is activated. 9. the command must satisfy any bus contention, bus turn around, and/or write recovery requirements. the command is illegal if the minimum bank to bank delay time (t rrd ) is not satisfied. current state truth table (cont.) l l l l op code mode register set illegal l l l h x x auto orself refresh illegal l l h l x x precharge illegal l l h h ba row address bank activate illegal refreshing l h l l ba column write illegal l h l h ba column read illegal l h h l x x burst termination no operation; idle after t rc l h h h x x no operation no operation; idle after t rc h x x x x x device deselect no operation; idle after t rc l l l l op code mode register set illegal l l l h x x auto orself refresh illegal l l h l x x precharge illegal mode register l l h h ba row address bank activate illegal accessing l h l l ba column write illegal l h l h ba column read illegal l h h l x x burst termination illegal l h h h x x no operation no operation; idle after two clock cycles h x x x x x device deselect no operation; idle after two clock cycles current state command action notes ce ras cas we ba a 11 , description a 10 /ap - a 0
11 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com wed416s8030a june 2000 rev. 0 ras cas addr ba dqm t ss t sh a 10 /ap cke clock ce cb cc rb ca ra t sh dq row active precharge read write read row active db qc we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high t ss t sh t rcd t rp t ras t rcd t ss t sh t ss bs bs bs bs bs note 3 note 3 note 4 rb note 3 note 2, 3 note 2, 3 note 2 note 4 note 2, 3 ra bs qa t sh t ss t oh t sac t slz t ss t sh t ss t sh t rac t ss t sh t ccd t ch t cl t cc don't care note 2 fig. 2 single bit read-write cycle (same page) @cas latency=3, burst length=1 4. a10/ap and ba 0 -ba 1 control bank precharge when precharge command is asserted. notes: 1. all input except cke & dqm can be don't care when ce is high at the clk high going edge. 2. bank active & read/write are controlled by ba 0 ~ba 1 . 3. enable and disable auto precharge function are controlled by a10/ap in read/write command. ba0 ba1 active & read/write 0 0 bank a 0 1 bank b 1 0 bank c 1 1 bank d a10/ap ba0 ba1 precharge 0 0 0 bank a 0 0 1 bank b 0 1 0 bank c 0 1 1 bank d 1 x x all banks 0 0 distribute auto precharge, leave bank a active at end of burst. 0 1 disable auto precharge, leave bank b active at end of burst. 1 0 disable auto precharge, leave bank c active at end of burst. 1 1 disable auto precharge, leave bank d active at end of burst. 0 0 enable auto precharge, precharge bank a at end of burst. 0 1 enable auto precharge, precharge bank b at end of burst. 1 0 enable auto precharge, precharge bank c at end of burst. 1 1 enable auto precharge, precharge bank d at end of burst. a10/ap ba0 ba1 operation 0 1
12 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com wed416s8030a june 2000 rev. 0 fig. 3 power up sequence ras cas addr ba dqm a 10 /ap cke clock ce key raa dq mode register set row active (a-bank) auto refresh auto refresh precharge (all banks) we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 t rp raa high-z t rfc t rfc high level is necessary high level is necessary don't care
13 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com wed416s8030a june 2000 rev. 0 fig. 4 read & write cycle at same bank @ burst length=4 ras cas addr ba dqm a 10 /ap cke clock ce rb cb0 ca0 ra cl = 2 dq row active (a-bank) write (a-bank) precharge (a-bank) precharge (a-bank) read (a-bank) row active (a-bank) we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high t rcd t rc rb note 1 ra qa0 t shz t shz t rdl t rdl t rac t rac qa1 qa2 qa3 db0 db1 db2 db3 cl = 3 qa0 qa1 qa2 qa3 db0 db1 db2 db3 t sac t sac t oh t oh note 3 note 4 note 4 note 3 don't care note 2 notes: 1. minimum row cycle times are required to complete internal dram operation. 2. row precharge can interrupt burst on any cycle. (cas latency - 1) number of valid output data is available after row precharge. last valid output will be hi-z(t shz ) after the clock. 3. access time from row active command. t cc *(t rcd + cas latency - 1) + t sac . 4. output will be hi-z after the end of burst (1, 2, 4, 8 & full page bit burst).
14 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com wed416s8030a june 2000 rev. 0 fig. 5 page read & write cycle at same bank @ burst length=4 ras cas addr ba dqm a 10 /ap cke clock ce cc0 cd0 ca0 ra cl = 2 dq write (a-bank) write (a-bank) read (a-bank) precharge (a-bank) read (a-bank) row active (a-bank) we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high t rcd ra qa0 t rdl t cdl qa1 qb0 qb1 qb2 dc0 dc1 dd0 dd1 cl = 3 qa0 qa1 qb0 qb1 dc0 dc1 dd0 dd1 don't care cb0 note 2 note 3 note 1 notes: 1. to write data before burst read ends, dqm should be asserted three cycles prior to write command to avoid bus contention. 2. row precharge will interrupt writing. last data input, t rdl before row precharge, will be written. 3. dqm should mask invalid input data on precharge command cycle when asserting precharge before end of burst. input data after row precharge cycle will be masked internally.
15 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com wed416s8030a june 2000 rev. 0 fig. 6 page read cycle at different bank @ burst length=4 ras cas addr ba dqm a 10 /ap cke clock ce cac cbd cae rbb caa raa cl = 2 dq read (a-bank) read (a-bank) read (b-bank) row active (b-bank) read (b-bank) precharge (a-bank) read (a-bank) row active (a-bank) we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high raa qaa2 qaa3 qbb0 qbb1 qbb2 qbb3 qac0 qac1 qbd0 qbd1 qae0 qae1 cl = 3 qaa2 qaa3 qaa0 qaa1 qaa0 qaa1 qbb0 qbb1 qbb3 qbb2 qac0 qac1 qbd0 qbd1 qae0 qae1 don't care cbb note 2 note 1 rbb notes: 1. ce can be don't cared when ras, cas and we are high at the clock high going edge. 2. to interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
16 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com wed416s8030a june 2000 rev. 0 fig. 7 page write cycle at different bank @ burst length=4 ras cas addr ba dqm a 10 /ap cke clock ce cac cbd rbb caa raa dq write (a-bank) write (b-bank) row active (b-bank) write (b-bank) precharge (both banks) write (a-bank) row active (a-bank) we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high raa daa3 dbb0 dbb1 dbb2 dbb3 dac0 dac1 dbd0 dbd1 daa1 daa0 daa2 don't care cbb note 2 note 1 rbb t rdl t cdl notes: 1. to interrupt burst write by row precharge, dqm should be asserted to mask invalid input data. 2. to interrupt burst write by row precharge, both the write and the precharge banks must be the same.
17 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com wed416s8030a june 2000 rev. 0 fig. 8 read & write cycle at different bank @ burst length=4 ras cas addr ba dqm a 10 /ap cke clock ce rac cac caa rbb raa cl = 2 read (a-bank) row active (a-bank) read (a-bank) write (b-bank) precharge (a-bank) row active (b-bank) row active (a-bank) we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high raa qaa3 dbb0 dbb1 dbb2 dbb3 qac0 qac1 qaa1 qaa0 qaa2 don't care cbb note 1 rac rbb t cdl qac2 cl = 3 dq qaa3 dbb0 dbb1 dbb2 dbb3 qac0 qac1 qaa1 qaa0 qaa2 note: 1. t cdl should be met to complete write.
18 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com wed416s8030a june 2000 rev. 0 fig. 9 read & write cycle with auto precharge @ burst length=4 ras cas addr ba dqm a 10 /ap cke clock ce cb ca rb ra cl = 2 auto precharge start point (b-bank) auto precharge start point (a-bank) write with auto precharge (b-bank) read with auto precharge (a-bank) row active (b-bank) row active (a-bank) we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high ra qa3 db0 db1 db2 db3 qa1 qa0 qa2 don't care rb cl = 3 dq qa3 db0 db1 db2 db3 qa1 qa0 qa2 note: 1. t cdl should be controlled to meet minimum t ras before internal precharge start. (in the case of burst length=1 & 2 and brsw mode)
19 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com wed416s8030a june 2000 rev. 0 fig. 10 clock suspension & dqm operation cycle @ cas latency=2, burst length=4 ras cas addr ba dqm a 10 /ap cke clock ce cb cc ca dq read read dqm write write dqm write dqm clock suspension clock suspension read row active we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ra qa0 t shz t shz qa1 qa2 qa3 dc0 dc2 don't care qb1 qb1 ra note 1 note: 1. dqm is needed to prevent bus contention.
20 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com wed416s8030a june 2000 rev. 0 fig. 11 read interrupted by precharge command & read burst stop @ burst length=full page ras cas addr ba dqm a 10 /ap cke clock ce cab caa raa cl = 2 precharge (a-bank) read (a-bank) burst stop read (a-bank) row active (a-bank) we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high don't care raa qaa0 qaa1 qaa2 qaa3 qaa4 qab1 qab0 qab3 qab2 qab5 qab4 cl = 3 dq qaa0 qaa1 qaa2 qaa3 qaa4 qab1 qab0 qab3 qab2 qab5 qab4 note 2 1 1 2 2 notes: 1. at full page mode, burst is end at the end of burst. so auto precharge is possible. 2. about the valid dqs after burst stop, it is same as the case of ras interrupt. both cases are illustrated in above timing diagram. see the label 1, 2. but at burst write, burst stop and ras interrupt should be compared carefully. refer to the timing diagram of "full page write burst stop cycle." 3. burst stop is valid at every burst length.
21 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com wed416s8030a june 2000 rev. 0 fig. 12 write interrupted by precharge command & write burst stop cycle @ burst length=full page ras cas addr ba dqm a 10 /ap cke clock ce cab caa raa dq precharge (a-bank) write (a-bank) burst stop write (a-bank) row active (a-bank) we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high don't care raa daa0 daa1 daa2 daa3 daa4 dab1 dab0 dab3 dab2 dab5 dab4 note 2 t rdl t bdl notes: 1. at full page mode, burst is end at the end of burst. so auto precharge is possible. 2. data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell. it is defined by ac p arameter of t rdl . dqm at write interrupted by precharge command is needed to prevent invalid write. dqm should mask invalid input data on precharge c ommand cycle when asserting precharge before end of burst. input data after row precharge cycle will be masked internally. 3. burst stop is valid at every burst length.
22 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com wed416s8030a june 2000 rev. 0 fig. 13 burst read single bit write cycle @ burst length=2 ras cas addr ba dqm a 10 /ap cke clock ce cbc cad rbb caa raa cl = 2 row active (a-bank) read (a-bank) row active (b-bank) write with auto precharge (b-bank) precharge (both banks) write (a-bank) read with auto precharge (a-bank) row active (a-bank) we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high raa qab0 qab1 dbc0 qad0 qad1 daa0 don't care cab note 2 rbb rac rac cl = 3 dq qab0 qab1 dbc0 qad0 qad1 daa0 note 1 notes: 1. brsw mode is enabled by setting as "high" at mrs (mode register set). at the brsw mode, the burst length at write is fixed to "1" regardless of programmed burst length. 2. when brsw write command with auto precharge is executed, keep it in mind that t ras should not be violated. auto precharge is executed at the burst-end cycle, so in the case of brsw write command, the next cycle starts the precharge.
23 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com wed416s8030a june 2000 rev. 0 fig. 14 active/precharge power down mode @ cas latency=2, burst length=4 ras cas addr ba dqm a 10 /ap cke clock ce ra ca dq precharge read row active precharge power-down entry precharge power-down exit active power-down entry active power-down exit we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 note 3 note 2 t ss don't care t ss t ss t shz note 1 ra qa1 qa0 qa2 notes: 1 .both banks should be in idle state prior to entering precharge power down mode. 2. cke should be set high at least 1clk + tss prior to row active command. 3. can not violate minimum refresh specification (64ms).
24 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com wed416s8030a june 2000 rev. 0 fig. 15 self refresh entry & exit cycle ras cas addr ba dqm a 10 /ap cke clock ce dq auto refresh self refresh entry self refresh exit we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 t ss don't care note 1 note 3 note 4 t rfc min note 6 note 5 note 7 hi-z hi-z note 2 notes: to enter self refresh mode 1. ce, ras & cas with cke should be low at the same clock cycle. 2. after 1 clock cycle, all the inputs including the system clock can be don't care except for cke. 3. the device remains in self refresh mode as long as cke stays "low." once the device enters self refresh mode, minimum t ras is required before exit from self refresh. to exit self refresh mode 4. system clock restart and be stable before returning cke high. 5. ce starts from high. 6. minimum t rfc is required after cke going high to complete self refresh exit. 7. 4k cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh.
25 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com wed416s8030a june 2000 rev. 0 fig. 16 mode register set cycle fig. 17 auto refresh cycle ras cas addr dqm cke clock ce ra key dq new command new command auto refresh mrs we 012 345678 012345 678910 don't care t rfc hi-z hi-z note 2 note 1 note 3 high high notes: both banks precharge should be completed before mode register set cycle and auto refresh cycle. mode register set cycle 1. ce, ras, cas, & we activation at the same clock cycle with address key will set internal mode register. 2. minimum 2 clock cycles should be met before new ras activation. 3. please refer to mode register set table.
26 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com wed416s8030a june 2000 rev. 0 package dimension: 54 pin tsop ii 22.35 (0.880) 22.10 (0.870) 10.29 (0.405) 10.03 (0.395) 11.96 (0.471) 11.56 (0.455) 0.80 (0.0315) typ 0.51 (0.020) 0.25 (0.010) 0.15 (0.006) 0.05 (0.002) 0.61 (0.024) 0.41 (0.016) 1.20 (0.047) max see view a view a 0.203 (0.008) 0.125 (0.005) note 1 note 2 0 - 8 all linear dimensions are in millimeters and parenthetically in inches ordering information part number organization operating frequency package WED416S8030A10SI 2mx16bitsx4banks 100mhz 54 tsop ii wed416s8030a12si 2mx16bitsx4banks 83mhz 54 tsop ii notes: 1. dimension does not include 0.006 inch flash each side. 2. dimension does not include 0.010 inch flash each side.

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