View TMC2074-NE_4240868.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

smsc tmc2074 page 1 revision 0.1 (03-29-06) datasheet tmc2074 dual mode circlink ? controller datasheet product features ? low power cmos, 3.3 volt power supply with 5 volt tolerant i/o ? supports 8/16-bit data bus ? both 86xx and 68hxx platforms ? 1k on-chip dual port buffer memory ? sequential i/o mapped access ? enhanced token passing protocol from arcnet ? maximum 31 nodes per network ? token retry mechanism ? maximum 256 bytes per packet ? consecutive node id assignment ? memory mirror ? shared memory within network ? network standard time ? network time synchronization ? automatic time stamping ? coded mark inversion ? intelligent 1-bit error correction ? magnetic saturation prevention ? dual operation modes ? peripheral (host) mode operates with mcu ? standalone (i/o) mode operates without mcu ? supports 8 bit programmable general purpose i/o at peripheral mode ? supports 16 bit input and 16 bit output at standalone mode ? dual communication modes (with peripheral mode) ? free format mode ? remote buffer mode ? 3 port hub integrated ? 1 internal and 2 external ? flexible topologies ? bus, star and tree ? low cost media can be used ? rs485 differential driver ? fiber optics and twisted pair cable supported ? 128-pin vtqfp package; green, lead-free package also available ? temperature range from 0 to 70 degrees c
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 2 smsc tmc2074 datasheet ordering information order number(s): TMC2074-NE for 128 pin vtqfp package tmc2074-nu for 128 pin vtqfp package (green, lead-free) 80 arkay drive hauppauge, ny 11788 (631) 435-6000 fax (631) 273-3123 copyright ? 2006 smsc or its subs idiaries. all rights reserved. circuit diagrams and other information rela ting to smsc products are included as a m eans of illustrating typical applications. consequently, complete information sufficient for construction pur poses is not necessarily given. although the informat ion has been checked and is bel ieved to be accurate, no responsibility is assumed for ina ccuracies. smsc reserves the ri ght to make changes to specif ications and product descriptions at any time without notice. contact your local smsc sales office to obtain the late st specifications bef ore placing your product order. the provisi on of this information does not convey to the purchas er of the described semiconducto r devices any licenses under any patent rights or other intellect ual property rights of smsc or others. all sales are expressly conditional on your agr eement to the terms and conditions of the most re cently dated ve rsion of smsc's standard terms of sale agreement dated before the date of y our order (the "terms of sale ag reement"). the product may contain d esign defects or errors known as anomalies which may cause the product's f unctions to deviate from published s pecifications. a nomaly sheets are available upon request. smsc products are not des igned, intended, authorized or wa rranted for use in any life s upport or other application whe re product failure could cause or contri bute to personal injury or severe property damage. an y and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at the risk of the customer. copies of this document or other smsc litera ture, as well as the terms of sale agreement, may be obtained by visiting smsc?s website at http:// www.smsc.com. smsc is a registered tr ademark of standard microsystems corporation (?smsc?). product names and company names are the trademarks of their respective holders. smsc disclaims and excludes any and all warranties, including without limitation any and all implied warranties of merchantability, fitness for a particular purpose, ti tle, and against infringement and the like, and any and all warranties arising from any course of dealing or usag e of trade. in no event shall smsc be liable for any direct, incidental, indirect, special, p unitive, or consequential damages; or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contract; tort; negligence of smsc or others; strict liability; breach of warranty; or othe rwise; whether or not any remedy of buyer is held to have failed of its essential purpose, and whether or no t smsc has been advised of the possibility of such damages.
dual mode circlink? controller datasheet smsc tmc2074 page 3 revision 0.1 (03-29-06) datasheet table of contents chapter 1 general d escripti on............................................................................................................ ....................6 1.1 about circlink................................................................................................................. ..................................6 1.2 about tm c2074 .................................................................................................................. ...............................7 1.3 internal blo ck diag ram ......................................................................................................... ............................8 1.4 pin configuration .............................................................................................................. ................................9 1.5 pin description by functions................................................................................................... ......................13 1.5.1 cpu interface pins (27) ........................................................................................................ .........................13 1.5.2 transceiver interf ace pins (5)................................................................................................. .......................13 1.5.3 setup pins (37) ................................................................................................................ ..............................14 1.5.4 external output or i/o pins (10)............................................................................................... ......................14 1.5.5 test pins (5) .................................................................................................................. ................................15 1.5.6 clock pins (3) ................................................................................................................. ...............................15 1.6 setup pins..................................................................................................................... ...................................16 1.6.1 cpu type se lectio n............................................................................................................. ..........................16 1.6.2 address multiple x select ion .................................................................................................... .......................17 1.6.3 write timing select ion ......................................................................................................... ..........................18 1.6.4 read timing se lectio n.......................................................................................................... .........................19 1.6.5 data bus widt h select ion ....................................................................................................... .......................20 1.6.6 data bus by te sw ap ............................................................................................................. .........................20 1.6.7 data strobe polarity specific ation............................................................................................. .....................20 1.6.8 page size se lectio n............................................................................................................ ...........................21 1.6.9 maximum node (maxid) number setup .............................................................................................. .........21 1.6.10 node id setup.................................................................................................................. ..........................21 1.6.11 nst resoluti on setu p........................................................................................................... .....................22 1.6.12 standalone mode spec ification .................................................................................................. ................22 1.6.13 warning timer resolution/st andalone sending schedul e setu p...............................................................22 1.6.14 diagnosis mode................................................................................................................. .........................22 1.6.15 prescaler setup for communicati on s peed........................................................................................ ........22 1.6.16 nst carry output digit select.................................................................................................. ..................23 1.6.17 cmi bypass spec ificat ion....................................................................................................... ....................23 1.6.18 hub functi on on/of f ............................................................................................................ ..................23 1.6.19 optical transce iver mode ....................................................................................................... ...................23 1.6.20 txen polari ty se lect........................................................................................................... .......................24 1.6.21 extension time r setti ng 1 ...................................................................................................... ....................24 1.6.22 test pins ...................................................................................................................... ..............................24 chapter 2 functional d escripti on......................................................................................................... ................25 2.1 communication sp ecification .................................................................................................... ....................25 2.2 message class .................................................................................................................. ...............................25 2.3 circlink network communicat ion protocol overview ............................................................................... .26 2.4 circlink protocol enhancement .................................................................................................. ..................27 2.4.1 reducing to ken los s ............................................................................................................ ........................27 2.4.2 reduction of network re configurat ion ti me...................................................................................... ............27 2.4.3 reduction of reconfigurati on burst signal send time ............................................................................ ......28 2.5 ram page ex pansion............................................................................................................. .........................28 2.5.1 ram a ccess ..................................................................................................................... .............................29 2.5.2 packet buffer struct ure........................................................................................................ ..........................31 2.5.3 packet data struct ure.......................................................................................................... ..........................32 2.6 cpu inte rface .................................................................................................................. .................................33 2.6.1 cpu identification and com patibility between intel and mo torola proc essors ...............................................33
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 4 smsc tmc2074 datasheet 2.6.2 interface re strict ions ......................................................................................................... ............................34 2.7 circlink operation a nd communicati on modes ..................................................................................... .....35 2.7.1 operational mode ............................................................................................................... ...........................35 2.7.2 communicati on m ode ............................................................................................................. .......................36 2.8 sending in peri pheral mode ..................................................................................................... ......................38 2.8.1 example of sending control from cpu in free format m ode .......................................................................3 8 2.8.2 tx control from cpu in remote bu ffer m ode ...................................................................................... .........39 2.9 receive in pe ripheral mode..................................................................................................... .......................39 2.9.1 temporary receive and direct re ceive ........................................................................................... .............40 2.9.2 example of receive flow in free fo rmat m ode .................................................................................... ........43 2.9.3 example of receive flow in remote buffer mode.................................................................................. .......44 2.9.4 warning timer (wt) at remote buffe r rece ive .................................................................................... ........44 2.10 standalone mode ................................................................................................................ .........................47 2.10.1 general description of standal one m ode......................................................................................... ..........47 2.10.2 sending in st andalone m ode ..................................................................................................... ................47 2.10.3 reception in standalone mode ................................................................................................... ...............50 2.11 diagnostic mode ................................................................................................................ ..........................54 2.12 network standard time (nst) .................................................................................................... ................55 2.12.1 functions prov ided by nst...................................................................................................... ..................55 2.12.2 time-synchr onous s equence ...................................................................................................... ...............56 2.12.3 phase e rror .................................................................................................................... ............................57 2.12.4 nnstcout pulse g eneration cycle ................................................................................................ .........60 2.13 cmi modem...................................................................................................................... .............................62 2.14 hub functi on................................................................................................................... ............................62 2.14.1 operation example of hub f uncti on .............................................................................................. ...........64 2.14.2 timer expansion in mult i-stage cascade connecti on .............................................................................. ..65 2.15 8-bit general-purpose i/o port (new function) .................................................................................. .......66 chapter 3 description of regist ers ....................................................................................................... ...............67 3.1 register map................................................................................................................... .................................67 3.2 details of regist er ............................................................................................................ ...............................70 3.2.1 comr0 register: status/i nterrupt ma sk regi ster................................................................................. .........70 3.2.2 comr1 register: diagnos tic/command regist er .................................................................................... .....72 3.2.3 comr2 register: page regi ster .................................................................................................. .................74 3.2.4 comr3 register: page-inte rnal addre ss regi ster ................................................................................. .......75 3.2.5 comr5 register: s ub-address r egist er ........................................................................................... ............77 3.2.6 comr6 register: conf iguration regist er ......................................................................................... .............78 3.2.7 comr7 r egist er................................................................................................................. ...........................80 3.2.8 nst register: netw ork standar d time............................................................................................ ..............84 3.2.9 intsta register: ec interrupt status ........................................................................................... ................84 3.2.10 intmsk register: ec interrupt mask............................................................................................. ............87 3.2.11 eccmd register: ec command r egist er ............................................................................................ .....88 3.2.12 rsid register: receive sid ..................................................................................................... .................89 3.2.13 ssid regist er: sid............................................................................................................. ........................89 3.2.14 rxfh register: receiv e flag (hi gher si de)...................................................................................... ..........90 3.2.15 rxfl register: receiv e flag (low er si de)....................................................................................... ...........91 3.2.16 cmid register: clo ck master node id............................................................................................ ...........92 3.2.17 mode register: operati on mode setup regist er ................................................................................... ...93 3.2.18 carry register: carry select ion for exter nal ou tput ............................................................................ ...95 3.2.19 rxmh register: receiv e mode (hi gher si de) ...................................................................................... ........96 3.2.20 rxml register: receiv e mode (low er si de)....................................................................................... ........97 3.2.21 maxid register: sele ction of max. id........................................................................................... .............98 3.2.22 nid register: select ion of t he node id ......................................................................................... .............98 3.2.23 ps register: page si ze sele ction ............................................................................................... ...............99
dual mode circlink? controller datasheet smsc tmc2074 page 5 revision 0.1 (03-29-06) datasheet 3.2.24 ckp register: communica tion rate se lection..................................................................................... ......99 3.2.25 nstdif register: ns t phase di fference .......................................................................................... ......100 3.2.26 pininfo register: pi n setup in formati on ........................................................................................ ........101 3.2.27 errinfo register: error info rmation ............................................................................................ ..........102 a-1 outline .................................................................................................................... ............................................104 a-2 cmi code................................................................................................................... .........................................104 a-3 cmi modem c onfiguration.................................................................................................... ............................105 a-4 cmitx block ................................................................................................................ ......................................106 a-5 cmirx block ................................................................................................................ ......................................107 a-6 details rega rding reception................................................................................................ ............................108 list of figures figure 1 - tmc2074 blo ck diagr am ........................................................................................................ ...............8 figure 2 - pin names: pin name in peripher al mode/pin name in standalone mode ...........................................9 figure 3 - motorola cp u mode ( 68hxx) .................................................................................................... ............16 figure 4 - intel cpu mode ( 86xx) ........................................................................................................ .................16 figure 5 - non-multip lex bu s ............................................................................................................ ....................17 figure 6 - multiplex (ale falling-e dge ty pe) ............................................................................................ .............17 figure 7 - multiplex (ale rising-e dge ty pe) ............................................................................................. ............18 figure 8 - packet structure of free format mode (example of 32 byte s/page) ....................................................36 figure 9 - packet structure of remote buffe r mode (example of 32 byte s/page) .................................................37 figure 10 - data import timing in standalone mode and external trigger mode (m ode 3) ....................................49 figure 11 - transmission packet buffer c onfiguration (m ode 1, 2) ........................................................................4 9 figure 12 - transmission packet buffer configurati on (mode 3) ............................................................................ 50 figure 13 - strobe output timing in standalone mode, external trigger mode (m ode 3) ......................................51 figure 14 - reception packet buffer configurat ion (spre [2:0] = other t han 111) .................................................52 figure 15 - reception packet buffer conf iguration (spr e [2:0]= 111) ....................................................................53 figure 16 - internal 3 port hub block diagr am ............................................................................................ ..........63 figure 17 - cmi coding state transition diagr am.......................................................................................... ........104 figure 18 - cmi modem bl ock di agram ...................................................................................................... ..........105 figure 19 - example of unstable comparator output ........................................................................................ ...108 figure 20 - tmc2074 128 pin pa ckage out line .............................................................................................. .....111 figure 21 - timing measur ement po ints .................................................................................................... ...........115 list of tables table 1 - pin lists sort ed by f unction................................................................................................. ....................10 table 2 - the number of n odes and ram page si ze........................................................................................ .....28 table 3 - cpu type ..................................................................................................................... ...........................33 table 4 - distinction and matchi ng of the cpu ty pe..................................................................................... ..........33 table 5 - page format of packet bu ffer................................................................................................. .................42 table 6 - transmission period accord ing to time r setup ................................................................................. ......48 table 7 - circlink regi ster map........................................................................................................ ......................67 table 8 - tmc2074 128 pin pa ckage para meters........................................................................................... .....111
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 6 smsc tmc2074 datasheet chapter 1 general description 1.1 about circlink the circlink networking controller was developed fo r small control-orient ed local network data communication based on arcnet?s token-passing pr otocol that guarantees message integrity and calculatable maximum cycle time. in a circlink network, when a node receives the token it becomes the temporary ma ster of the network for a fixed, short period of time. no node can dominate the network since token c ontrol must be relinquished when transmission is complete. once a transmission is completed the token is passed on to the next node (logical neighbor), allowing it to be come the master. because of this token passing scheme, maximum wa iting time for network access can be calculated and the time performance of the network is predictable or deterministic. cont rol networking applications require predictable performance to ensure that controlled events occur when requir ed. however, rec onfiguration of a regular arcnet network becomes necessary when the token is missed due to electronic and magnetic noise. in these cases, the maximum wait time for sending datagrams cannot be guaranteed and the real- time characteristic is impaired. circlink makes severa l modification to the original arcnet protocol (such as maximum and consecutive node id assignment) to avoid token missing as much as possible and reduce the network reconfiguration time. circlink implements other enhancement s to the arcnet protocol incl uding a smaller-sized network , shorter packet size, and remote buffer mode operati on that enable more efficient and reliable small, control-oriented lans. in addition, circlink introduces several unique feat ures for reducing overall system cost while increasing system reliability. circlink can operate under a special mode called ?standalone? or ?i/o? m ode. in this mode, circlink does not need an administrating cpu for each node. only one cpu is needed to manage a circlink network composed up to maximum 31 nodes, reducing cost and complexity. in a circlink network, the data sent by the source node is received by all other nodes in the network and stored according to node source id. for the target node the received data is executed per arcnet flow control and the data is stored in it s buffer ram. the receiving node proc esses the data while the remaining nodes on the network discard the data when the receiving node has completed. this memory-mirroring function assures higher reliability and signi ficantly reduces network traffic. network standard time (nst) is also a unique circlin k feature. nst is rea lized by synchronizing the individual local time on each network node to the cl ock master in the desi gnated node from which the packet is sent. circlink also uses cmi code for trans mitting signals, rather than the dipulse or bipolar signals that are the standar d arcnet signals. since cmi encoding e liminates the dc element, a simple combination of a standard rs485 ic and a pulse tr ansformer can be used to implement a transformer- coupled network.
dual mode circlink? controller datasheet smsc tmc2074 page 7 revision 0.1 (03-29-06) datasheet 1.2 about tmc2074 the tmc2074 network controller is circlink technol ogy?s flagship product. the tmc2074?s flexibility and rich feature set enable a high-reliability and high-per formance, real-time and c ontrol-oriented network without the cumbersome middle laye r protocol stacks and complex packet prioritization schemes typically required. tmc2074 operates at network data transfer rate s up to 5 mbps. its embedded 1 kbyte ram can be configured into a maximum of 32 pages to implem ent a 31-node network where each node in the network has the same local memory. the tmc2074 has two operational modes: ?peripheral mode? and ?standalone mode?. it can operate with or without the exis tence of a system cpu on a network node. in peripheral mode, the tmc2074 has two selectable communication modes, ?free format m ode? and ?remote buffer mode?. free format mode, retained from arcnet, is ?packet oriented? comm unication. remote buffer mode communication is a circlink-specific featur e, and is a token oriented communica tion, which includes automatic data transmission when the token arrives. the tmc2074 has a flexible 8-bit or 16-bit databus to interface various cpu types including x86, 68xx, and shx with multiplexed or non-multiplexed addre ss/data. when operating in peripheral mode, the tmc2074 has 8-bit programmable i/o available. when operating in standalone mode, the tmc2074?s i/o configuration is16-bit. the tmc2074 al so integrates a 3-port hub (two por ts for external connection) to accommodate various network topologies (bus, star, etc.) and combinations.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 8 smsc tmc2074 datasheet 1.3 internal block diagram mode setting register access control circuit interrupt status interrupt mask ec command receive mode(#01-#31) receive flag(#01-#31) clock master sid net. standard time alarm setting receive sid search sid max id setting (maxid) node id setting (nid) page size setting (ps) data rate setting address pointer page register address register diag. register data register h data register l data latch tent-id register config register setup registers address multiplexer address pointer data latch shift register rx synchro- nous circuit tx signal generator cmi decode cmi encode cmi synchro txen txd rxin buffer memory 512b 512b improved arcnet protocol micro sequencer working registers memory access mediation circuit recon timer osc reset circuit micro-controller bus maxid nid ps ckp nmux nrwm w16 nswap nstalone ndiag flasho nnstcout txen2 rxin2 3port hub circuit err-info pin-info nhubon ncmibyp others clock figure 1 - tmc2074 block diagram
dual mode circlink? controller datasheet smsc tmc2074 page 9 revision 0.1 (03-29-06) datasheet 1.4 pin configuration *2 *2 *2 *3 *3 *1 *3 xxx *2 xx *1 vss gpio7 / po15 gpio6 / po14 gpio5 / po13 gpio4 / po12 gpio3 / po11 vss gpio2 / po10 gpio1 / po9 gpio0 / po8 flasho nnstcout vss x2 x1 vdd mckin nc nc nc vss ckp2 ckp1 ckp0 nc maxid4 maxid3 maxid2 maxid1 maxid0 nc vdd 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 *1 vdd 97 64 vss *2 wpre0 / spre0 98 63 nid4 wpre1 / spre1 99 62 nid3 wpre2 / spre2 100 61 nid2 x nc 101 60 nid1 ntest0 102 59 nid0 ntest1 103 58 nc x ntest2 104 57 ps1 ntest3 105 56 ps0 (high) / nstc0 106 55 nc x nehrd / nstc1 107 54 nstpre2 *2 vss 108 53 nstpre1 nehwr / nstc2 109 52 nstpre0 (high) / nstc3 110 51 nstalone ncmibyp 111 50 ndiag nopmd 112 49 vdd *1 *1 vdd 113 48 rxin2 nhubon 114 47 et1 x nc 115 46 rxin nmux / scm0 116 45 txenpol nrwm / scm1 117 44 vss *2 w16 / scm2 118 43 txen2 nswap / scm3 119 42 txd ncs / scm4 120 41 txen *2 vss 121 40 nintr / nstunloc x nc 122 39 vss *2 x nc 123 38 nreset *4 a0 / po0 (npostr) 124 37 nc x *1 vdd 125 36 nc x a1 /po1 126 35 d15 / pi15 a2 (ale) / po2 127 34 d14 / pi14 *2 vss 128 33 vdd *1 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132 vdd a3 (alepol) / po3 a4 / po4 a5 / po5 nc nc ndsinv / cmierrmd nrd (nds) / po6 ntmode nwr (dir) / po7 nc vss d0 (ad0) / pi0 (npistr) d1 (ad1) / pi1 d2 (ad2) / pi2 d3 (ad3) / pi3 vdd d4 (ad4) / pi4 d5 (ad5) / pi5 vss d6 / pi6 d7 / pi7 d8 / pi8 d9 / pi9 vdd d10 / pi10 d11 / pi11 vss d12 / pi12 d13 / pi13 nc vss *1 xx x *2 *1 *2 *1 *2 x *2 *1 power supply (v dd ) *2 power supply (vss) *3 clock signal *4 reset signal x nc figure 2 - pin names: pin name in peripheral mode/pin name in standalone mode
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 10 smsc tmc2074 datasheet table 1- pin lists sorted by function count pin no. pin name dir ec t ion pin name dir ec t ion pull-up type drive type 1 38 nreset in nreset in internal t-nrm --- --- 2 120 ncs in scm4 in internal t-nrm --- --- 3 124 a0 in po0/npostr 3s / o internal t-nrm 4ma 4 126 a1 in po1 3s.o internal t-nrm 4ma 5 127 a2/ale in po2 3s.o internal t-nrm 4ma 6 2 a3/alepol in po3 3s.o internal t-nrm 4ma 7 3 a4 in po4 3s.o internal t-nrm 4ma 8 4 a5 in po5 3s.o internal t-nrm 4ma 9 8 nrd/nds in po6 3s.o internal t-nrm 4ma 10 10 nwr/dir in po7 3s.o internal t-nrm 4ma 11 13 d0/ad0 bi pi0/npistr in internal t-nrm 4ma 12 14 d1/ad1 bi pi1 in internal t-nrm 4ma 13 15 d2/ad2 bi pi2 in internal t-nrm 4ma 14 16 d3/ad3 bi pi3 in internal t-nrm 4ma 15 18 d4/ad4 bi pi4 in internal t-nrm 4ma 16 19 d5/ad5 bi pi5 in internal t-nrm 4ma 17 21 d6 bi pi6 in internal t-nrm 4ma 18 22 d7 bi pi7 in internal t-nrm 4ma 19 23 d8 bi pi8 in internal t-nrm 4ma 20 24 d9 bi pi9 in internal t-nrm 4ma 21 26 d10 bi pi10 in internal t-nrm 4ma 22 27 d11 bi pi11 in internal t-nrm 4ma 23 29 d12 bi pi12 in internal t-nrm 4ma 24 30 d13 bi pi13 in internal t-nrm 4ma 25 34 d14 bi pi14 in internal t-nrm 4ma 26 35 d15 bi pi15 in internal t-nrm 4ma 27 40 nintr out nstunloc out --- --- 4ma to ta l :2 7 1 46 rxin in rxin in internal t-nrm --- --- 2 41 txen out txen out --- --- 4ma 3 42 txd out txd out --- --- 4ma 4 48 rxin2 in rxin2 in internal t-nrm --- --- 5 43 txen2 out txen2 out --- --- 4ma total:5 1 82 x1 in x1 in --- --- --- --- 2 83 x2 out x2 out --- --- --- --- 3 80 mc k in in mc k in in internal t-nrm --- --- total:3 cpu interface transceiver interface clock peripheral mode standalone mode pin input buffer output buffer
dual mode circlink? controller datasheet smsc tmc2074 page 11 revision 0.1 (03-29-06) datasheet cou nt pi n no. pin name di r e c t o n pin name di r ec t i o n pull-up type drive type 1 116 nm ux in scm 0in internal t-nrm --- --- 2 117 nrwm in scm 1in internal t-nrm --- --- 3 118 w16 in scm 2in internal t-nrm --- --- 4 119 nswap in scm 3in internal t-nrm --- --- 5 52 nstpre0 in nstpre0 in internal t-nrm --- --- 6 53 nstpre1 in nstpre1 in internal t-nrm --- --- 7 54 nstpre2 in nstpre2 in internal t-nrm --- --- 8 56 ps0 in ps0 in internal t-nrm --- --- 9 57 ps1 in ps1 in internal t-nrm --- --- 10 59 nid0 in nid0 in internal t-nrm --- --- 11 60 nid1 in nid1 in internal t-nrm --- --- 12 61 nid2 in nid2 in internal t-nrm --- --- 13 62 nid3 in nid3 in internal t-nrm --- --- 14 63 nid4 in nid4 in internal t-nrm --- --- 15 67 m axid0 in m axid0 in internal t-nrm --- --- 16 68 m axid1 in m axid1 in internal t-nrm --- --- 17 69 m axid2 in m axid2 in internal t-nrm --- --- 18 70 m axid3 in m axid3 in internal t-nrm --- --- 19 71 m axid4 in m axid4 in internal t-nrm --- --- 20 73 ckp0 in ckp0 in internal t-nrm --- --- 21 74 ckp1 in ckp1 in internal t-nrm --- --- 22 75 ckp2 in ckp2 in internal t-nrm --- --- 23 51 n stalone =h in n stalone =l in internal t-nrm --- --- 24 50 ndiag in ndiag in internal t-nrm --- --- 25 45 txenpol in txenpol in internal t-nrm --- --- 26 98 wpre0 in spre0 in internal t-nrm --- --- 27 99 wpre1 in spre1 in internal t-nrm --- --- 28 100 wpre2 in spre2 in internal t-nrm --- --- 29 106 un-use(high) in nstc0 in internal t-nrm --- --- 30 107 nehrd in nstc1 in internal t-nrm --- --- 31 109 nehwr in nstc2 in internal t-nrm --- --- 32 110 un-use(high) in nstc3 in internal t-nrm --- --- 33 7 ndsinv in cm ierrm din internal t-nrm --- --- 34 111 ncm ibyp in ncm ibyp in internal t-nrm --- --- 35 114 nhubon in nhubon in internal t-nrm --- --- 36 112 nopm din nopm din internal t-nrm --- --- 37 47 et1 in et1 in internal t-nrm --- --- tot a l : 3 7 setup pins output buffer pin peripheral mode standalone mode input buffer
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 12 smsc tmc2074 datasheet count pin no. pin name dir ec t ion pin name dir ec t ion pull-up type drive type 1 85 nnstcout out nnstcout out --- --- 4ma 2 86 flasho 3s.o flasho 3s.o --- --- 4ma 3 87 gpio0 3s.o po8 3s.o internal t-nrm 4ma 4 88 gpio1 3s.o po9 3s.o internal t-nrm 4ma 5 89 gpio2 3s.o po10 3s.o internal t-nrm 4ma 6 91 gpio3 3s.o po11 3s.o internal t-nrm 4ma 7 92 gpio4 3s.o po12 3s.o internal t-nrm 4ma 8 93 gpio5 3s.o po13 3s.o internal t-nrm 4ma 9 94 gpio6 3s.o po14 3s.o internal t-nrm 4ma 10 95 gpio7 3s.o po15 3s.o internal t-nrm 4ma tota l :1 0 1 102 ntest0 in ntest0 in nothing t-nrm --- --- 2 103 ntest1 in ntest1 in nothing t-nrm --- --- 3 104 ntest2 in ntest2 in nothing t-nrm --- --- 4 105 ntest3 in ntest3 in nothing t-nrm --- --- 5 9 ntmode in ntmode in internal t-nrm --- --- total 1,17,25, 33,49,65 ,81,97, 113,125 12,20,28, 32,39,44, 64,76,84, 90,96,108 ,121,128 total 5,6,11,31, 36,37,55, 58,66,72, 77,78,79, 101,115, 122,123 total t-nrm 3s / o 3s.o --- --- 24 --- --- --- nc (open) --- nc pins 1-17 nc (open) --- --- --- --- 11-24 vss pwr vss pwr --- --- --- --- vdd pwr 1-10 vdd pwr ttl level input w /o schmitt tri-state output tri-state output or nomal output standalone mode input buffer output bufer (high) : connect to vdd (open) : not connect total pin = 128 17 5 output or i/o pins test pins power pins pin peripheral mode
dual mode circlink? controller datasheet smsc tmc2074 page 13 revision 0.1 (03-29-06) datasheet 1.5 pin description by functions * a pin name starting with ?n? indicates an active-low pin. 1.5.1 cpu interface pins (27) d[15:6]/pi[15:6] data bus / standalone input port (bit15-6) d[5:1]/ad[5:1]/pi[5:1] data bus / addre ss data bus / standalone input port (bit5-1) d[0]//ad[0]//pi[0]/npistr data bus / address data bus / standalone input port (bit5-0) /standalone strobe input port ncs/scm[4] chip select input / standalone designate cmid (bit4) nwr/dir/po[7] write signal input / a ccess direction / standalone input port (bit7) nrd/nds/po[6] read signal input / da ta strobe / standalone i nput port (bit6) a[5:4]/po[5:4] address input / standalone input port (bit5-4) a[3]/alepol/po[3] address input / ale desi gnate polarity / standalone output port (bit3) a[2]/ale/po[2] address input / ale / standalone output port (bit2) a[1]/po[1] address input / standalone output port (bit1) a[0]/po[0]]/npostr address input / standalone ou tput port (bit0) / standalone strobe input port nintr/nstunloc interrupt output / nstunloc flag output for standalone nreset reset input (active low) 1.5.2 transceiver interface pins (5) rxin port1 receive data input txen port1 transmit enable output txd transmit data output (port1 & 2 common) rxin2 port2 receive data input txen2 port2 transmit enable output
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 14 smsc tmc2074 datasheet 1.5.3 setup pins (37) nmux/scm[0] select address multip lex mode/standalone desi gnate cmid (bit0) nrwm/scm[1] select r/w mode / standalone designate cmid (bit1) w16/scm[2] select data bus wi dth / standalone designate cmid (bit2) nswap/scm[3] select swap m ode / standalone designate cmid (bit3) ndsinv/cmierrmd nds designate polari ty / standalone cmi receive error mode ps[1:0] determine page size (*1) nid[4:0] determine myid number (*1) maxid[4:0] determi ne maxid number (*1) ckp[2:0] determine data rate (*1) nstpre[2:0] nst resolution nstalone select standalone mode wpre[2:0]/spre[2:0] select warni ng timer resolution / standalone tx schedule ndiag select diagnostics mode et1 determine arcnet extended timer (*1) nstc[3] select nst carry output digit in standalone mode bit[3] nehwr/nstc[2] enhanced write / nst carry output digit in standalone mode bit[2] nehrd/nstc[1] enhanced read / nst carry output digit in standalone mode bit[1] nstc[0] nst carry output digit in standalone mode bit[0] txenpol txen,txen2 designate polarity nopmd select optical transceiver mode ncmibyp bypass cmi modem nhubon on/off determine of internal hub function (*1) could be also determined by the register at the peripheral mode 1.5.4 external output or i/o pins (10) nnstcout nst carry output flasho outside output for flash
dual mode circlink? controller datasheet smsc tmc2074 page 15 revision 0.1 (03-29-06) datasheet gpio[7:0]/po[15:8] general-purpose i/o port (b it7-0) / standalone out put port (bit15-8) 1.5.5 test pins (5) ntest[3:0] test pins ntmode test mode 1.5.6 clock pins (3) mck x1 x2 mckin (internal masterclock) - using an external clock : x1 is connected to gnd with mckin connect ed to the input of the external clock - using xtal: mckin is connected to vdd with x1 , x2 connected to the crystal oscillator
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 16 smsc tmc2074 datasheet 1.6 setup pins setup pins are strapped high or low to configure options according to sy stem design. for low, strap to ground. many pins have internal pullups on their i nput buffers. these pins can be left unconnected to keep them in high state. 1.6.1 cpu type selection (nrwm/scm[1]: pin) ? peripheral mode: this pin selects the cpu type; in this case, the definit ion of nwr/dir (pin) and nrd/nds (pin) are selected (refer to figure 3 - motorola cpu mode (68hxx). ? standalone mode: this pin is the clock ?m aster-id-specification input scm[1]. [nrwm=h, ndsinv=h] read cycle write cycle nds dir figure 3- motorola cpu mode (68hxx) [nrwm=l, ndsinv=l or h] read cycle write cycle nrd nwr figure 4 - intel cpu mode (86xx)
dual mode circlink? controller datasheet smsc tmc2074 page 17 revision 0.1 (03-29-06) datasheet 1.6.2 address multiplex selection (nmux/scm[0]: pin) in peripheral mode, this pin specif ies the system data bus from bit5 to 0 and whether or not the addresses are multiplexed (refer to figure 5 - non-multiplex bu s). when the multiplexing bus option is selected, the polarity of a2/ale is specified based on a3/alepol. in standalone mode, this pin is the clock-master-id- specification input scm[0]. [in case of nmux=h]\ d15-8 data high byte a5-0 address data low byte d7-0 figure 5 - non-multiplex bus [in case of nmux=l, alepol=h] 1 bus cycle d15-8 data high byte ad5-0 address d ata bit7-6 d7-6 d ata bit5-0 ale figure 6 - multiplex (ale falling-edge type)
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 18 smsc tmc2074 datasheet [in case of nmux=l, alepol=l] 1 bus cycle d15-8 d ata h igh byte ad5-0 address d ata bit7-6 d7-6 d ata b it5-0 ale figure 7 - multiplex (ale rising-edge type) 1.6.3 write timing selection (nehwr/nstc[2]: pin) ? peripheral mode: this pin selects the write timing. ? standalone mode: this pin is nst- ca rry-output-digit-selection nstc[2]. [ example: nmux=h,nehwr=h ] ncs write signal tie to hi for cpu?s where ncs goes hi before the write signal goes hi. [ example: nmux=h,nehwr=l ] ncs write signal tie to low for cpus where ncs goes hi after the write signal goes hi.
dual mode circlink? controller datasheet smsc tmc2074 page 19 revision 0.1 (03-29-06) datasheet the write signal differs depending on the cpu type: nrwm = h: nds signal at dir = l nrwm = l: nwr signal note: refer to the ac timing specific ations (in another document) for deta ils (setup time, hold time, etc.). compare timing specifications for nehwr=l and nehwr=h. 1.6.4 read timing selection (nehrd/nstc[1]: pin) ? peripheral mode: this pin selects the read timing type. ? standalone mode: this is nst- carry -output-digit selection nstc[1]. [ in case of nmux=h,nehrd=h ] ncs a[5:0] read signal address sampling timing tie to hi for cpus with valid address before ncs and the read signal go low. [example: nmux = h and nehrd = l] ncs a[5:0] read signal address sampling timing 50ns tie to l for the cpu?s where ncs is enabled and addr esses are valid after the read signal goes low.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 20 smsc tmc2074 datasheet note: address acquisition timing in the circlin k delays about 50 ns (with 20 mhz-xtal). the read signal differs depending on the cpu type: nrwm = h: nds signal at dir = h nrwm = l: nrd signal note: refer to the ac timing specific ations (in another document) for deta ils (setup time, hold time, etc.). compare timing specificati ons for nehrd=l and nehrd=h. 1.6.5 data bus width selection (w16/scm[2]: pin) this pin selects the width of the dat a bus in the peripheral mode; h: 16-bit mode, l: 8-bit mode. in the 16- bit mode, the lsb address in the circlink is fixed to 0. in the standalone mode, this pin is the clock- master-id input pin scm[2]. 1.6.6 data bus byte swap (nswap/scm[3]: pin) in peripheral mode, this pin select s the data order at 8-bit access. al though the registers in the circlink are defined as 16-bit width, 8-bit a ccess is available, and in this case , the assignment of lower/upper byte of the register and odd/ev en number of addresses can be changed. t he nswap=l assigns the lower byte to even number address/ upper byte to odd number addre ss, and the nswap=h assigns the lower byte to odd number address /upper byte to ev en number address. in standalone mode, this pin is the clock master id input scm[3]. 1.6.7 data strobe polarity specification (ndsinv/cmierrmd: pin) in peripheral mode, this pin selects the pin polarity of data st robe (nds). it is active low with ndsinv = h and active high with ndsinv = l. in standalone mode, this pin is equivalent to cmierrmd (bit 12) in mode register. the packet receive stops upon the occurr ence of a cmi receive error correction (cmiecc) with cmierrmd = h.
dual mode circlink? controller datasheet smsc tmc2074 page 21 revision 0.1 (03-29-06) datasheet 1.6.8 page size selection (ps[1:0]: pin/register) select page size per packet. the maximum number of nodes depends on the page size selection since the packet buffer size is limited to 1 kbyte. page size c an be selected by settings using register bits inimode (bit 9); 0: selects pin, 1: se lects register (the default is 0). ps[1:0] page size max node number 00 256 byte 3 node 01 128 byte 7 node 10 64 byte 15 node 11 32 byte 31 node 1.6.9 maximum node (maxid) number setup (maxid[4:0]: pin/register) the maximum node id is set based on the number of nodes on the network. all nodes in each circlink network, therefore, should have t he same maximum node id. this minimizes the time required to reconfigure the network. there are two methods to specify the maxi mum node id, either through pin or register settings depending on inimode (bit 9); 0: selects pin, 1: selects register (the default is 0). if the ndiag pin is set to l as the exception, however, t he maximum node id is automatically set to the largest value. for more details, refer to section 2.11 - diagnostic mode. 1.6.10 node id setup (nid[4:0]: pin/register) set node id. a unique number must be assigned to each node in the network with ascending order starting from id=01. id = 00 and an id larger than the maxi mum node id are not valid. there are two methods to assign the node id, either through pin or register, setti ngs depending on inimode (bit 7) 0: selects pin, 1: select register (default is 0). maxid[4:0] determines the maximum node id value. the to ken will be passed only around the nodes whose ids are equal to or less than the maximum id value. . in the circlink network, a node whose maxid[4:0] and nid[ 4:0] matches is the node init iating the token passing.. even if this particular node is absent from the network, the network reconfiguration time is greatly reduced because the network will be only reconfigured by the nodes with ids less than ma xid[4:0]. since the maxi mum number of nodes is fixed to maxid[4:0] in a circlin k network, the original priority timer of arcnet, (255 ? id) x 146 s*, which determines the time required for network rec onfiguration, is modified to (maxid[4: 0]-id) x 146 s, greatly reducing network reconfi guration time. refer to section 2.4.2 - reduction of network reconfiguration time for more details. * 146 s is defined under operation at 2. 5 mbps based on arcnet protocol . that number is half at 5 mbps.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 22 smsc tmc2074 datasheet 1.6.11 nst resolution setup (nstpre[2:0]: pin) select resolution of network standar d time counter(nst) . refer to section 2.12 - network standard time (nst) for details. 1.6.12 standalone m ode specification (nstalone: pin) this pin enables the standalone mode operation of circlink. refer to section 2.10 - standalone mode for the details 1.6.13 warning timer resolution/st andalone sending schedule setup (wpre/spre[2:0]: pin) these pins select the warning timer resolution in peripheral mode and the transmit schedule (include setup trigger mode) in standalone mode. refer to sections 2.9.4 and 2.10 for more details. 1.6.14 diagnosis mode (ndiag: pin) this pin places circlink in diagnostic mode. it pulls ndiag low, and sets the maxid to ?1fh?. refer to section 2.11 - diagnostic mode for the details. 1.6.15 prescaler setup for communication speed communication speed can be selected either through pi n or register, depending on the specification of inimode (bit 9); 0: pin, 1: register (default is 0). (ckp[2:0]: pin/register)
dual mode circlink? controller datasheet smsc tmc2074 page 23 revision 0.1 (03-29-06) datasheet 40mhz xtal 20mhz xtal 32mhz xtal 16mhz xtal 000 8 5mbps 2.5mbps 4mbps 2mbps 001 16 2.5mbps 1.25mbps 2mbps 1mbps 010 32 1.25mbps 625kbps 1mbps 500kbps 011 64 625kbps 312.5kbps 500kbps 250kbps 100 128 312.5kbps 156.25kbps 250kbps 125kbps 101 256 156.25kbps 78.125kbps 125kbps 62.5kbps 110 reserved reserved reserved reserved reserved 111 reserved reserved reserved reserved reserved communication speed ckp2-0 prescale 1.6.16 nst carry output digit select (nstc[3], nehwr/nstc[2], nehrd/nstc[1], nstc[0]: pin) these pins are equivalent to the same-symbol signal nstc[3:0] (bit 7-4) of the carry register in standalone mode. the output timi ng of external pulse nnstcout is specified as an nst digit position. for the functions using peripheral mode, refer to sections 1.6.3 and 1.6.4. 1.6.17 cmi bypass specification (ncmibyp: pin) selects bypassing the cmi code/encodi ng. ncmibyp = l bypasses the cmi coding/decoding circuit so that encoding is rz form signal interface, equi valent to the arcnet back plane mode. 1.6.18 hub function on/off (nhubon: pin) selects on/off ; nhubon=h selects hub functi on off, nhubon=l selects hub function on and enables port 2 (rxin2 and txen2) ( in nhub on = h, rxin2 should be fixed to high). refer to section 2.14 - hub func tion for the detailed operations. 1.6.19 optical transceiver mode (nopmd: pin) selects the output mode of the sending-enable; nopmd = h ma kes the optical transceiver mode unavailable and allows the txen and txen2 output pi ns to function as ?sending-enable?. setting nopmd = l allows txen and txen2 output pins to func tion as ?sending-enable and sending pulse? to be able to be directly connected to the ttl input pin of the optical transceiver.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 24 smsc tmc2074 datasheet 1.6.20 txen polarity select (txenpol: pin) selects the output polarities of the txen and txen2 signal. txenpol = l selects negative logic and txenpol = h positive logic. 1.6.21 extension timer setting 1 (et1: pin/register) refer to section 2.14 - hub function for operational details. 1.6.22 test pins (ntest[3:0], ntmode: pin) all the pins must be connected to vdd.
dual mode circlink? controller datasheet smsc tmc2074 page 25 revision 0.1 (03-29-06) datasheet chapter 2 functional description 2.1 communication specification - data transfer bit rate 78.125 kbps to 2.5 mbps (with 20 mhz xtal, 5 mbps with 40 mhz xtal). - the max. number of nodes 31 (id = 00 is not available for use) - data transfer check only the destinati on node can check data transfer. other nodes, however, can receive (monitor) the same data. - protocol enhanced versi on of arcnet (token passing) - packet size 256 bytes max. (user area: 253 bytes max.) 2.2 message class the following five classes of messages are identical to those in the arcnet protocol. refer to the arcnet controller com20020 rev. d datasheet for more information. alert eot did did itt (token) alert enq did did fbe (free buffer enquiries) alert ack ack (acknowledgements) alert nak nak (negative acknowledgements) data x n alert soh sid did packet (data packets) did cp crc crc n : max253 (arcnet layer)
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 26 smsc tmc2074 datasheet 2.3 circlink network communication protocol overview circlink protocol is derived from the arcnet protocol. this sect ion explains the arcnet basic communication protocol. a token (itt: invitation to transmit) is a unique si gnaling sequence that is pass ed in an orderly fashion among all the active nodes in the network. when a particu lar node receives the token, it has the sole right to initiate a transmission sequence or it must pass t he token to it?s logical neighbor. this neighbor can be physically located anywhere on the network and has t he 2nd highest address. once the token is passed to the recipient, it has the right to initiate transmissi on. this token-passing sequenc e continues in a logical ring fashion serving all nodes equally. node addresses must be unique and can range from 0 ? 255 with 0 reserved for broadcast messages. in a transmissi on sequence the node with t he token becomes the source node and any other node select ed becomes the destination node. fi rst the source node inquires if the destination node is in a mode to receive a trans mission by sending out a free buffer enquiry (fbe). the destination node responds by returning an acknowledgement (ack) meaning that the buffer is available or by returning a negative acknowledgement (nak) meaning that no buffer is available. upon receiving the ack, the source node sends out the data transmission (pac) with ei ther 0 ? 507 bytes of data (pac). if the data was properly received by the destination node as evidenced by a successful crc test, the destination node sends another ack. if the transmission was unsuccessful, the destination node does nothing causing the source node to timeout. the sour ce node will therefore, in fer that the transmission failed and will retry after it receives the tok en on the next token pass. the transmission sequence terminates and the token is passed to the next node. if the desired message exceeds 507 bytes the message is sent in a series of packets-one packet every token pass. the arcnet protocol comprises the reconfiguration process to ensur e the complete token passing for every node linked to the network. arcnet has the ability to reconfigur e the network automatica lly if a node is either added or removed from the network. if a node joins the netwo rk it does not automatically participate in the token passing sequence. being excluded from receiving the token, t he new node will generate a rec onfiguration burst that destroys the token passing sequence. once the token is lost all nodes will cease transmitting and begin a timeout sequence (priorit y timer, (255-id) x 146 s ,based on their own node address. the node (node id=n) with the highest address will timeout first and pass the token to the next higher address (node id=n+1). if that node does not res pond, it is assumed t hat node does not exist. then the node address is incremented (node id=n+2) and the token resent. this process is repeated until a node responds. at that time the token is released to the responding node and the address of the res ponding node is noted as the logical neighbor of the originati ng node. this process is repeated by all nodes until each node learns its logical neighbor. this eliminates wasting time in sending datagrams to absent addresses once the network has been re-established. when a node leaves the network the re configuration process is slight ly different. when a node releases the token to its logical neighbor, it expects its logical neighbor will re spond within the response time out window (78 s) .if no response within the response time out window, it assumes that its neighbor has left the network and immediately begins a search for a new logical neighbor by incrementing the node address of its logical neighbor and initiating a token pass. ne twork activity is again monitored and the increment process and resending of the tok en continues until a new logical neighbor is found. once found the network returns to the normal logical ring r outine of passing token to logical neighbors. these reconfiguration sequenc es of the network are automatic and seamless wit hout software intervention required.
dual mode circlink? controller datasheet smsc tmc2074 page 27 revision 0.1 (03-29-06) datasheet 2.4 circlink protocol enhancement since arcnet communication is controlled by a token, token loss and the corresponding network reconfiguration significantly reduce network throughput. the circl ink controller design includes enhancements to and modifications of the arcnet pr otocol to increase reliability and performance. 2.4.1 reducing token loss the burst signal is the primary caus e of token loss. the burst signal is part of the sequence for new nodes joining the network as described in se ction 2.3. but with circlink all nodes join the network at system start- up. if a node leaves the network due to token loss it can readily rejoin t he network in the next polling with no burst necessary. in order to avoid this burst si gnal, the arcnet protocol has been modified to specify node ids as consecutive numbers st arting from 01. when a node other than the node having the largest node id (nid [4:0] and maxid[4:0]) sends a token with the starting address being the node id +1, the token can be received in the next polling, even if the node had previously dr opped out of the network. the token retry function added to circlink greatly reduc es the possibility of not receiving the response from the logical neighbor due to to ken corruption. circlink node ids ar e consecutive and since the retry does not occur under normal conditions, the token re try function does not degrade the total performance. this function can be set to on or off using software settings (default is on). another cause of token loss is the corruption of ack/nak. in the arcne t flow control (refer to page 12 in the arcnet controller com20020i dat asheet), if the source node re ceives signals other than the anticipated ack/nak response (suc h as noise or, data-deformed ac k/nak and the like) from the destination node, the source node returns to the receiv e-wait state with a to ken being held by the node. the network considers this token loss because the token disappears from the network. to avoid this problem, the arcnet protocol has been modified in circlink to send a token even after the detection of ack/nak corruption this function can be set to on or off (default is on). 2.4.2 reduction of networ k reconfiguration time to reduce the required time of (255 - id) x 146 s* during network reconfigur ation , circlink designates a node with the maximum id as the maximum node (ma x_node). this node imm ediately starts sending tokens with destination numbers star ting from 00. the token sent to 00 is not received by any node but triggers the other nodes to enter into t he receive state after the (255 - id) x 146 s* time is over. in addition, the (255 - id) x 146 s* timer formula, derived from arcnet, is modified to (the maximum number of nodes ?id) x 146 s depending on the maximum number of nodes , which is specified by the maxid [4:0] pin. this modification makes signifi cantly reduces the time required for network reconfiguration even in the absence of the node designated as max_node. * 146 s is defined under operation at 2. 5 mbps based on arcnet protocol. the time is half at 5 mbps..
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 28 smsc tmc2074 datasheet 2.4.3 reduction of reconfigur ation burst signal send time since the circlink maximum packet size is smaller t han arcnet, the reconfigurat ion burst signal is of shorter duration, thus reducing the ti me required for network reconfigurat ion (as listed in the table below). circlink ps[1:0] max packet size burst signal sending time 00 256(253)byte 1.63ms 01 128(125)byte 1.07ms 10 64(61)byte 0.79ms 11 32(29)byte 0.65ms a rcnet -- max packet size burst signal sending time -- 512(508)byte 2.75ms () : data size note: ?burst signal sending time? is the time under operat ion at 2.5 mbps. the time is half at 5 mbps. 2.5 ram page expansion the original arcnet buffer ram is divided into 256 or 512-bytes per page. this configuration has a maximum of four pages available in 1 kbyte increm ents, leaving the majori ty of the ram unused when small data packets are used. circlink ram addre ssing has been modified to significantly expand the number of pages available in ram and to store pages corresponding to the node ids on the network as listed in table 2. table 2 - the number of nodes and ram page size page size ps[1:0] node id(min) *1 node id(max) page address 256 byte 00 01h 03h 100h x id 128 byte 01 01h 07h 80h x id 64 byte 10 01h 0fh 40h x id 32 byte 11 01h 1fh 20h x id note: * 1 : node id = 00 is used only for the system development and is not available for users.
dual mode circlink? controller datasheet smsc tmc2074 page 29 revision 0.1 (03-29-06) datasheet 2.5.1 ram access the cpu accesses the packet buffer (ram) through the co mr4 register. prior to access, a read or write and the page number need to be specified using the comr2 register, as we ll as the address specification in the page using the comr3 register. the accessing method varies depending on the bit width of the data bus, word mode, and swap mode. (1) data bus = 16 bits (w16 pin=h) comr2 register : rddata, autoinc, nwrapar, page[4;0] a/ad[5:0] = 04h - - - - - - - - rd. a.i. nw.a 43210 comr3 register : address within a page ramadr[7:0] a/ad[5:0] = 06h - - - - - - - - 7 6 5 4 3 2 1 x com4 register : packet data ramdt[15:0] a/ad[5:0] = 08h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit0 is fixed in 0 in the inside. (2-a) data bus = 8 bits , word mode=off (w16 pin=l, wdmd=0 in mode reg.) comr2 register : rddata autoinc nwrapar page[4:0] a/ad[5:0] = 04h (05h) * rd. a.i. nw.a 43210 comr3 register : address within a page ramadr[7:0] a/ad[5:0] = 06h (07h) * 7 6 5 4 3 2 1 0 comr4 register : packet data ramdt[7:0] a/ad[5:0] = 08h or 09h 7 6 5 4 3 2 1 0 ( )*:nswap=l
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 30 smsc tmc2074 datasheet (2-b) data bus = 8 bits , word mode=on (w16 pin=l, wdmd=1 in mode reg.) comr2 register : rddata autoinc nwrapar page[4:0] a/ad[5:0] = 04h (05h) * rd. a.i. nw.a 43210 comr3 register : address within a page ramadr[7:0] a/ad[5:0] = 06h (07h) * 7 6 5 4 3 2 1 x comr4 register : packet data ramdt[15:0] a/ad[5:0] = 08h (09h) * 7 6 5 4 3 2 1 0 a/ad[5:0] = 09h (08h) * 151413121110 9 8 ( )*:nswap=l bit0 is fixed in 0 in the inside. note: in word mode = on, to preserve the upper and lowe r bytes of word data, comr4 must be accessed in order of 08h first and 09h second. this restriction applies to both read and wr ite. also, it is impossible to independently access the continuation pointer (cp address = 02h) in ram independently to access the cp, a dummy cycle is necessary. refer to sect ion 2.5.3 - packet data structure for detail.
dual mode circlink? controller datasheet smsc tmc2074 page 31 revision 0.1 (03-29-06) datasheet 2.5.2 packet buffer structure #00 (00h) #01 (01h) #31 (1fh) 00h 01h 1fh 32byte 1024byte 32page 32 byte mode page[4:0] ramadr[4:0] : : #0 (0h) #1 (1h) #15 (fh) 00h 01h 3fh 64 byte 1024 byte 16page 64 byte mode page[3:0] ramadr[5:0] : : #0 #1 #7 00h 01h 7fh 128 byte 1024 byte 8page 128 byte mode page[2:0] ramadr[6:0] : : 256 byte #0 #1 #3 00h 01h ffh 1024 byte 4page 256 byte mode page[1:0] ramadr[7:0] #2 :
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 32 smsc tmc2074 datasheet 2.5.3 packet data structure ps = [1:0] = example of 11 (32-byte mode) 8 bit constitution 16 bit constitution ramadr ramad r 10 7 0 15 8 7 0 00 sid 01 did 02 cp = 1a . . . 1a data #0 data #0 data #0 1b data #1 ( upper byte ) ( lower byte) 1c data #2 data #1 data #1 1d data #3 ( upper byte ) ( lower byte) 1e data #4 data #2 data #2 1f data #5 ( upper byte ) ( lower byte) cp=1a did dummy 1a 1c 1e (w16=l,wdmd=0) (w16=l,wdmd=1 or w16=h) . . 00 02 sid sid: source-id (source node id) did: destination-id (destination node id): did=0 means the broadcast packet. cp: continuation pointer writes the value (page size - n) for sending n-byte data. that is, it indi cates the top positi on of data in the page. the example shows the value is 1ah (32 - 6 bytes = 26 bytes = 1ah). note: limitations on the specifiable values for cp. 32b mode (ps [1:0] = 11) : values from 03h to 1fh 64b mode (ps [1:0] = 10) : values from 03h to 3fh 128b mode (ps [1:0] = 01) : values from 03h to 7fh 256b mode (ps [1:0] = 00) : values from 03h to ffh if a packet is sent with cp other than the specif ied value the destination node rejects the packet, and the session closes with a sending error (txerr). simultaneous ly the cp error (cperr) flag of the ec status register is set, which can issue an interrupt. the erro r flag, however, means a se tup or cp specification error to the circlink, and does not indicate a network error. sender: sending error (txerr) and cp error (cperr) flags ar e set and a token is passed to the next node. since ta flag is reset to 1 except in the remote buffe r mode (txm = 1) as well as the continuous send mode (rto = 0), a send command must be issued for re-sending.
dual mode circlink? controller datasheet smsc tmc2074 page 33 revision 0.1 (03-29-06) datasheet receiver: the receiver rejects the packet and goes back to idle state. 2.6 cpu interface 2.6.1 cpu identification and compatibility between intel and motorola processors the circlink controller can be connected to any combinat ion of cpus listed in table 3 - - cpu type. for more information on setup, refer to section 1.6 - setup pins. table 3 - cpu type connection cpu type item 16 bit cpu 8 bit cpu address multiplexed non-mux / mu ltiplexed non-mux / multiplexed data bus width 8 bit/16 bit 8 bit read / write nrd , nwrl or dir , nlds(lds) nrd , nwr or dir , nds(ds) table 4 - - distinction and matching of the cpu type descr ibes setup of pin functi ons of address bus/data, bus/read write controls by nrwm and nmux pins. table 4- distinction and matching of the cpu type intel (80xx) type motorola (68xx) type pin name nrwm = 0 nrwm=1 nmux=0 nmux=1 nmux=0 nmux=1 d15 - d6 d15-d6 d15-d6 d15-d6 d15-d6 d/ad5 - d/ad0 ad5-ad0 d5-d0 ad5-ad0 d5-d0 a5-a4 - a5-a4 - a5-a4 a3 alepol a3 alepol a3 a2 ale a2 ale a2 a1-a0 - a1-a0 - a1-a0 nwr/dir nwr nwr dir dir nrd/nds nrd nrd nds(ds) nds(ds) note: symbol definition in table 4: d data bus a address bus ad address / data bus nwr write signal (16 bit cpu is nwrl) nrd read signal dir read / write signal nds(ds) data strobe signal (16 bit cpu is nld s) (polarity is designated by ndsinv pin) ale address latch enable signal alepol designate ale polarity
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 34 smsc tmc2074 datasheet 2.6.2 interface restrictions data strobe signal using motorola 16-bit cpu when executing word (16 bit) access to odd addresse s by dir and data strobe si gnals, the motorola cpu does not discriminate between upper and lower data strobe signals. because of this, it is necessary to or the upper and lower data strobe signals to provide the data strobe input. data transmission when transmitting and receiving data of 8 bits and 16 bits, the transmitter node can send odd-numbered bytes but the receiving node can only implement word a ccess (which is 16-bit), the word is read with one invalid upper data byte. to use the re ceive data function in a system, s pecial care must be taken. this problem occurs only when the cp field value in the packet is an odd number.
dual mode circlink? controller datasheet smsc tmc2074 page 35 revision 0.1 (03-29-06) datasheet 2.7 circlink operation and communication modes circlink has two operation modes: peripheral mode, whic h carries out communications in partnership with a system cpu, and standalone mode, which enables communications by circlink without a cpu. these modes can be switched by the nstalo ne pin. in the standalone mode, t he pins for interfacing cpu are switched as ports for the external input/output and internal register s cannot be accessed. there are two communication modes in peripheral mode: free forma t mode, which is capable of handling a free format packet, and remote buffer mode, which uses circlink ram as a simple buffer. the register bits rxm01 to 31 specify the rx mode of each page and txm specifies the mode for tx mode. operation mode communication mode standalone mode rxmn *1 =0 receive *1: n = 01 to 31 rxmn *1 peripheral mode =1 *1: n = 01 to 31 txm =0 transmit txm =1 transmit of free format mode transmit of remote buffer mode nstalone pin = l nstalone pin = h receive of free format mode ( ever y pa g e ever y desi g nate ) receive of remote buffer mode ( ever y pa g e ever y desi g nate ) 2.7.1 operational mode peripheral mode peripheral mode acts as the system cpu's peri pheral circuit and has two communication modes, free format mode and remote buffer mode. the communi cation mode is independently selectable for send and receive; txm of mode register for sender and rxm01 to rxm31 of re ceive mode register for receive. the communication mode for sender and receiver must be identical and the co mmunication mode of the receiver page should be adjusted to match the communication mode of the sender.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 36 smsc tmc2074 datasheet standalone mode in standalone mode, circlink independently executes send and receive s equences without a cpu. refer to section 2.10 - standalone mode for more details. 2.7.2 communication mode free format mode free format mode is retained from the original arcnet specification. this mode is optimal for transferring large amounts of data at once. cpu controls a series of sequence such as "packet preparation issuing tx command interruption handling after the end of tx " at sender and "receive command issuing interrupt handling after the end of rx packet read" at receiver. since circlink initiates the actual tx upon receipt of a token addressed to t he node, the time between a tx command being issued and tx starting varies dependi ng on the line status. the free format mode is a "packet-oriented" transfer mode that assumes a co mpletion of packet preparation before issuing a tx cmd, so its real-time performance is not as high as that of the remo te buffer mode ?token-oriented? mode. on the other hand, the free format mode has no limitation on the packet data structure, and it can handle free format packets. moreover, communi cations in this mode are initia ted only by writing a tx cmd, thereby reducing traffic on the network. 8 bit constitution 16 bit constitution ram-adrs ram-adr s 10 7 0 15 8 7 0 00 sid 01 did 02 cp 03 04 05 .free . .format . . . . . 1e 1f 1e format (w16=l,wdmd=0) (w16=l,wdmd=1 or w16=h) dummy 04 free 00 did sid 02 cp figure 8 - packet structure of free format mode (example of 32 bytes/page) remote buffer mode remote buffer mode, a circlink enhancement, optimizes real-time performance. in this mode circlink can be handled as a simple data buffer like "write data in to the circlink at any time" at a transmit node and "read data from the circlink at any time" at a receiver node ?. since the remote buffer mode is a "token-oriented" mode that features automatic transmission each time a node receives a token (= sending ri ght), preparation of t he packet header portion (sid, did, and cp) is
dual mode circlink? controller datasheet smsc tmc2074 page 37 revision 0.1 (03-29-06) datasheet required prior to issuing a tx cmd. the data portion of a packet must be valid in 8 or 16 bits. this mode restricts the data structur e, but it is optimized in its real-time performance when compared to free format mode since it can always communicate with the packet data. setting rto to 1 (default = 0) in the mode register limits circlink to one packet per tx cmd write. if rto is switched to 1 while operating under rto = 0, the automatic send operat ion is disabled immediately after the completion of the packet delivery. 8 bit constitution 16bit constitution ram-adrs ram-adr s 10 7 0 15 8 7 0 00 sid 01 did 02 cp=1a :: :: : :: : 1a byte#0 word#0 word#0 1b byte#1 ( upper byte) ( lower byte ) 1c byte#2 word#1 word#1 1d byte#3 ( upper byte) ( lower byte ) 1e byte#4 word#2 word#2 1f byte#5 ( upper byte) ( lower byte ) 1c 1e : 1a 02 dummy cp=1a : (w16=l,wdmd=0) (w16=l,wdmd=1 or w16=h) 00 did sid figure 9 - packet structure of remote buffer mode (example of 32 bytes/page) in 16-bit constitution, upper and lower bytes in the same word are preserved as the same packet data (refer to section 3.2.5 - comr 5 register: sub-address register.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 38 smsc tmc2074 datasheet 2.8 sending in peripheral mode to send data using circlink, it is necessary to wr ite data being transmitted in the packet buffer regardless of the communication mode. for tx, the page correspondi ng to its node id in the packet buffer is assigned as the tx buffer. the cpu writes tx data on this page. 2.8.1 example of sending control from cpu in free format mode (mode register: txm = 0) the cpu manages all communication sequenc es such as "packet preparation issuing tx cmd handling interrupt after the end of tx". (nid=n) cpu side tmc2074/72 lan side 1 write to packet 2 transmit command ta = 1 --> 0 3 release interrupt mask ?? ? ?? ? transmit start token [did=n] (fbe) (ack) pac transmit end (ack) ta = 0 --> 1 token [did=n+1] 4 read status interrupt occurre 5 interrupt mask ( ): not executed in the case of broadcast transmit. note: when did set to 00h, it becomes the broadcast packet.
dual mode circlink? controller datasheet smsc tmc2074 page 39 revision 0.1 (03-29-06) datasheet 2.8.2 tx control from cpu in remote buffer mode (mode register: txm = 1) circlink can be treated as a simple data buffer so that the system cpu can writ e data to the circlink at any time. (nid=n) cpu side tmc2074/72 lan side 1 write hader 2 write data 3 tramsmit command ta = 1->0 ?? ? ?? ? start transmit token[did=n] (fbe) (ack) pac end transmit (ack) keep of ta = 0 (*1) token[did=n+1] ?? ? 4 write data 4 write data 4 write data ?? ? 5 repeatedly repeatedly ( ):not done for broadcast transmission automatic transmit at each time of the receive of self token note: when did is set to 00h, it becomes the broadcast packet. (*1) if the rto bit is 0 in the mode register, circlink cont inues sending packets with a single tx cmd. the ta bit that represents tx end, cont inues to be 0 unless rto is set to 1 (constant tx status). if the rto bit is 1, the ta bit returns to 1 after each packet is transmitted, as in free format mode. tx cmd must be issued every time but this does not signi ficantly increase traffic on the network, making it suitable for applications such as handling sensor information that remains fairly constant. 2.9 receive in peripheral mode circlink receives all packet data on the network. afte r receiving a packet without any errors, circlink stores the packets in the relevant page in ram according to the source id (sid) included in the packet. receiving the data packet addressed to the node has four steps: receiving fbe sending ack receiving packet sending ack. for receiving a data packet addressed to another node in the network, the packet is stored in the relevant page without sending an ack.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 40 smsc tmc2074 datasheet as described above, circlink const antly receives packets, with one exception: it abandons the received packets when the receive mode of the corresponding page is free format mode and the receive flag is set to 1 (receive inhibited). in this case, circlink does not return an ack even if the packet is addressed to the node (this case is handled as a receive error). if the receive mode of the corresponding page is set to remote buffer mode, circlink unconditionally stores packets in the corresponding page in the packe t ram as long as the received data is valid. the previous packet is overwritten and the newest pa cket is always stored in the packet ram. the meaning of the receive flag va ries depending on the receive mode: (1) free format receive mode 0: receive wait or receiving 1: receive is inhibited or receives is completed (2) remote buffer receive mode 0: no receive in a certain period 1: one or more receive in a certain period 2.9.1 temporary receive and direct receive packets received are stored in the pages partitioned by the received source id (received sid). there are two methods for storing packets: storing after erro r checking through a temporary buffer (#00), and storing directly. the decision of which process is used is automatically select ed in circlink based on the combination of page size and communication speed pre scaler setting. the smaller the page size or the larger the division ratio of the transfer rate presca ler, the more data packets will be received through the temporary buffer. ckp[2:0] bit rate : input clock communication speed 11:32b 10:64b 01:128b 00:256b 000 1:8 2.5 mbps : 20 mhz xtal oo % x 001 1:16 1.25 mbps : 20 mhz xtal ooo % 010 1:32 625 kbps : 20 mhz xtal oooo ckp>=011 1:64 over omission oooo o : receive through temporary buffer available x : receive through temporary buffer not available % : receive through temporary buffer available with condition see paragraph below. prescale page size setting ? ps[1:0] in the table above, ? % ? indicates ?temporary relay reception is not available in the default setting. however, by setting the farb bit = 1 in register, set up 2 temporary relay recepti on is available. the farb bit = 1 setting is possible when the farb bit default is 0 and only when the input clock is below 20 mhz.
dual mode circlink? controller datasheet smsc tmc2074 page 41 revision 0.1 (03-29-06) datasheet when the clock exceeds 20 mhz, it should not be set to 1. also, farb bit renewal must be carried out during software reset. in temporary buffer receive mode, the packet data cont aining any errors is left at page 00 if the receive terminates abnormally (crc error, etc.). the copy to "sid page" corresponding to the received source id (receive sid) is not executed (the received data is discarded). in direct receive mode, the packet dat a containing errors is left at ?sid page? even if the receive terminates abnormally (crc error, etc.). regardless of whether the receive is done through temporary buffer or di rect receive, the rxf# flag upon abnormal termination of receive is set to 0 (not comp leted). it does not matter which receive process is being used because free format mode assumes that the rece ive is always checked with the rxf# flag. * 1 on the contrary, the receive process is important in the remote buffer re ceive mode with direct receive. * 2. in the worst case, if sid is corrupted in the rece ived packet, the packet data may be written to the wrong page. receive structure 0: free format 1: remote buffer temporary routing receive o o direct receive o * 1 x * 2 o: receive data reliable x: receive data unreliable receive mode rxm[31:01]
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 42 smsc tmc2074 datasheet table 5 - page format of packet buffer [nid[4:0]=11110, ps[1:0]=11 : 32byte/page] ram address page usage 000 ? 01f 020 ? 03f : 3a0 ? 3bf 3c0 ? 3df 3e0 ? 3ff #01 #01 : #29 #30 #31 temporary buffer for receive data from node01 : data from node29 buffer for transmit data from node31 [nid[4:0]=x1110, ps[1:0]=10 : 64byte /page] ram address page usage 000 - 03f 040 - 07f : 340 ? 37f 380 ? 3bf 3c0 ? 3ff #00 #01 : #13 #14 #15 temporary buffer for receive data from node01 : data from node13 buffer for transmit data from node15 [nid[4:0]=xx110, ps[1:0]=01 : 128byte/page] ram address page usage 000 ? 07f 080 ? 0ff : 280 ? 2ff 300 ? 37f 380 ? 3ff #00 #01 : #05 #06 #07 temporary buffer for receive data from node01 : data from node05 buffer for transmit data from node07 [nid[4:0]=xxx10, ps[1:0]=00 : 256bye/page] ram address page usage 000 ? 0ff 100 ? 1ff 200 ? 2ff 300 ? 3ff #00 #01 #02 #03 temporary buffer for receive data from node01 buffer for transmit data from node03
dual mode circlink? controller datasheet smsc tmc2074 page 43 revision 0.1 (03-29-06) datasheet 2.9.2 example of receive flow in free format mode (rxmh/rxml register: when in rxm07 = 0) a cpu controls a series of s equence such as "issuing rx cmd handling interrupt after rx packet read": cpu side tmc2074/72 lan side 1 clear frcv bit frcv = 1->0 2 release interrupt mask 3 write receive flag rxf07 = 1->0 ?? ? ?? ? fbe (ack) pac [sid=07h] (ack) frcv,rxf07 = 0->1 4 read ec status interrupt occure 5 read receive flag 6 read packet 7 interrupt mask ( ): it is fbe, pac addressed to self after the receive completion in the free format mode, the frcv (free format receive end flag) in the ec interruption status register (intst a) changes from 0 to 1, permitting the flag to be an interrupt source.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 44 smsc tmc2074 datasheet 2.9.3 example of receive flow in remote buffer mode (rxmh/rxml register: when in rxm07 = 1) circlink can be treated as a simple data buffer such as "read data from the circlink at any timing". (nid=n) cpu side tmc2074/72 lan side 1 wartc clear command rxfn = x->0 2 release interrupt mask ?? ? 3 read data 3 read data 3 read data 3 read data ?? 3 read data ?? ? warterr = 1 4 read ec status interrupt occure 5 error processing 6 interrupt mask each time packet comes automatic receive after completing the receive of remote buffer mode, rrcv (remote buffer receive end flag) in the ec interrupts the status register (i ntsta) and changes from 0 to 1, pe rmitting the flag to be an interrupt source. this mode also monitors if a packet comes fr om applicable nodes within a ce rtain period. if there is a non-responsive node, the warterr fl ag changes from 0 to 1, permitting this change to be an interrupt source. refer to section 3.2.9 - ints ta register: ec interrupt status. 2.9.4 warning timer (wt) at remote buffer receive circlink checks the logical and rxf flags of all pages t hat are set to remote buffer mode. a result of 1 during a cycle indicates a normal state in which ther e is no silent node on the network. in this case the object flags are cleared after a certai n period of time (see table below). in contrast, if the result retains a 0, the condition is not in a normal state, and waterr in the ec interrupt status register changes from 0 to 1. this condition will generate an interrupt.. this function is initialized by writing a warning ti mer clear command into the ec command register. the monitoring time is set by the warning timer resoluti on setup pins: wpre [2:0] and wartc3-0 in the carry selection register. actually, the warning timer clear command only clear s waterr flag. the warning timer function starts automatically after releasing softwar e reset. so some initial settings fo r this function set before releasing software reset. procedure: step-1: turn on software reset (reset bit = 1 in comr6 register) step-2: set initial settings (rx -mode, carry-selection, etc..)
dual mode circlink? controller datasheet smsc tmc2074 page 45 revision 0.1 (03-29-06) datasheet step-3: set warterr flag = 0 in the ec interrupt mask register step-4: release software reset (r eset bit = 0 in comr6 register) step-5: start the warning ti mer function automatically step-6: write the warning timer clear command into the ec command register. step-7: set warterr flag = 1 in the ec interrupt mask register step-8: after step-7, an interrupt occu rs when a warning timer error occurs. carry selection wartc3-0 carry digit check period 0000 ------ illegal setting 0001 wt[1] wt resolution * 2^1 0010 wt[2] wt resolution * 2^2 :: : 1111 wt[15] wt resolution * 2^15 resolution selection 40mhz xtal 20mhz xtal 32mhz xtal 16mhz xtal 000 12.8us 25.6us 16.0us 32.0us 001 25.60us 51.2us 32.0us 64.0us 010 51.2us 102.4us 64.0us 128.0us 011 102.40us 204.8us 128.0us 256.0us 1xx resolution wpre2:0 setting prohibition
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 46 smsc tmc2074 datasheet action of the receive flag(rxfxx) at the remote buffer mode remote buffer remote buffer free format remote buffer remote buffer occure event rxf01 rxf02 rxf03 rxf04 rxf05 1 clear command host 00x00 ...... ...... 2 receive #01 lan 10x00 3 receive #05 lan 10x01 4 receive #02 lan 11x01 ...... ...... warning timer c.o. tmc warterr = 0 -> 1 2074/72 ...... ...... until the clear command is issued hold of condition example : case of maxid=05 x = don't care 5 communication mode / receive flag name 11x01 wani ng ti m e r fu n c ti on : t i mi ng chart exam pl e reset signal -> r el ease r eset flag clear flag clear warterr clear command detect control signal stop -> start st op - > r e - st a r t det ect period pulse warterr flag clear clear nor mal warni ng d eteced nor mal 1 111 1 1 rx flag: rxf01 c l ea r auto. c l ear c l ea r auto. c l ear 00 000 11 11 11 rx flag: rxf02 c l ea r auto. c l ear c l ea r auto. c l ear 00 000 11 not rx 11 rx flag: rxf05 c l ea r auto. c l ear c l ea r auto. c l ear 000 k eep 0 0 0 0 rx rx rx rx rx rx rx rx rx det ect period det ect period det ect period det ect period det ect period det ect period
dual mode circlink? controller datasheet smsc tmc2074 page 47 revision 0.1 (03-29-06) datasheet 2.10 standalone mode 2.10.1 general description of standalone mode the standalone mode allows circlink to execute send/receive commands without cpu support. the functions of the cpu interface signals need to be set as listed below setting the nstalone pin to low (0) enables standalone mode. pin peripheral mode direction standalone mode direction d[15:6]/pi[15:6] d[15:6] i/o input port pi[15:6] i d[5:0]/ad[5:0]/pi[5:0] d/ad[5:0] i/o inpu port pi[5:0] i po[15:8] hi-impedance --- output port po[15:8] o nwr/dir/po[7] nwr/dir i output port po[7] o nrd/nds/po[6] nrd/ncs i output port po[6] o a[5:4]/po[5:4] a[5:4] i output port po[5:4] o a[3]/alepol/po[3] a3/alepol i output port po[3] o a[2]/ale/po[2] a2/ale i output port po[2] o a[1:0]/po[1:0] a[1:0] i output port po[1:0] o ncs/scm[4] ncs i cmid designate (bit4) i nswap/scm[3] nswap i cmid designate (bit3) i w16/scm[2] w16 i cmid designate (bit2) i nrwn/scm[1] nrwm i cmid designate (bit1) i nmux/scm[0] nmux i cmid designate (bit0) i wpre[2:0]/spre[2:0] wpre[2:0] i spre[2:0] i nintr/nstunloc nintr o nstunloc o flasho flasho o flasho o (high) /nstc[3] fix high i nstc[3] i nehwr/nstc[2] nehwr i nstc[2] i nehrd/nstc[1] nehrd i nstc[1] i (high) nstc[0] fix high i nstc[0] i ndsinv/cmierrmd ndsinv i cmierrmd i operation mode in standalone mode, internal regist ers cannot be accessed. the txen bit in the standalone mode defaults to 1, allowing nodes to automatica lly join the network upon start-up (re set). since the default parameters such as page size, max. node id, and the node id are set with pins, this mode does not provide any software solutions for network malfunction caused by any improper pin settings. 2.10.2 sending in standalone mode in standalone mode the cont ents of input port can be sent as a broadcast packet. sending starts automatically upon any of the following events. (1) when the received packets are normally receiv ed with no crc error. the packet format does not have to be an output port contro ller packet (as stated later). (2) timer setup. (3) when tokens are received.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 48 smsc tmc2074 datasheet (4) when external trigger is entered. the scenarios above (transmission triggers) can be set in accordance with the spre2-0 pin as below. spre2-0 transmission trigger setting trigger mode name 000 001 (1) after receiving self - addressed packets , 010 or 011 (2) timer setup 100 101 (3) after receiving self-addressed tokens mode 2 110 reserved 111 (4) external trigger (word data security) mode 3 mode 1 - mode 1 (after receiving self-addressed packet + timer setup) in this mode, when self-addressed packets are no rmally received with no crc error and the timer has timed-out, the transmission trigger is activated. namely , the ?or? of these two c onditions is removed. the transmission period during timer set-up is selected in a ccordance with the spre2-0 pin as shown in table 6. table 6 - transmission period according to timer setup spre2-0 @40mhz xtal @20mhz xt al @32mhz xtal @16mhz xtal 000 1.6ms 3.3ms 2.0ms 4.1ms 001 3.3ms 6.6ms 4.1ms 8.2ms 010 6.6ms 13.1ms 8.2ms 16.4ms 011 13.1ms 26.2ms 16.4ms 32.8ms 100 52.4ms 108.4ms 65.6ms 131.2ms - mode 2 (after receiving self-addressed tokens) this mode carries out a transmission whenever tokens are received . it is the same procedure used in remote buffer mode as in peripheral mode. since self -addressed tokens are trans mitted once received, it is an effective method for trans mitting at frequent intervals. - mode 3 (external trigger) in this mode, the input port stat us is latched internally when trans mission strobes are entered from an external source, thus activating the transmission tr igger. the transmission strobe input pin is the input port?s least significant pin pi0 (npistr). at the beginning , it activates the data latch and transmission
dual mode circlink? controller datasheet smsc tmc2074 page 49 revision 0.1 (03-29-06) datasheet trigger. accordingly, data entered through the input port is 15-bit and the least significant bit (bit 0) is fixed at 0. transmission data in this mode is secured at 15-bit word units. the external strobe generator is needed. it is an effective mode when transmitting a/d converte r or counter output. (in the above-mentioned mode 1 and mode 2, only bit unit data security can be obtained). transmission trigger activation latched data pi [15:1] pi0 (npistr) internal transmission data figure 10 - data import timing in standalone mode and external trigger mode (mode 3) s i d d i d c p data0 data1 . . . nid [4:0] fixed to 00 last 4 th byte input port (pi [15:0]) (pi [7:0]) (pi [15:8]) page: #sid nst15-8 nst7-0 nst [15:0] internal clock chatter noise filter figure 11 - transmission packet buffe r configuration (mode 1, 2)
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 50 smsc tmc2074 datasheet in modes 1 and 2, data from the input port is sampled by the internal clock in each port (bit unit) in the chatter noise filter. accordingly, when data from t he input port is imported into the transmission packet buffer, data is not secured in byte units or word units . only bit unit security is available. neither the a/d converter nor the counter output c an be connected to the input port. s i d d i d c p data0 data1 . . . nid [4:0] fixed to 00 last 4 th byte input port (pi [15:1]) (pi [7:1]) (pi [15:8]) page: #s i d nst15-8 nst7-0 nst [15:0] npistr 15-bit register figure 12 - transmission packet bu ffer configuration (mode 3) in mode 3 the chatter noise filter is bypassed and a 15-bit register is connected to the input port. the input port?s least significant pin (npstr) is used in this r egister clock. when npistr starts, data from the input port (15-bit) is imported into the register and is used as transmission data. immediately after importing, data security in the word units (15-bit) is ava ilable due to the transmission trigger being activated. accordingly, output from the a/d c onverter or counter can be connected to the input port, and bit 0 of the transmission data is fixed to 0. 2.10.3 reception in standalone mode the standalone mode has the function of exporting the contents of receiv ed data packets to the output port. to prevent unnecessary updating of output port contents, there are restrictions for the format of received packets as discussed below: received packet format restri ctions for data port: 1) packet?s self-address should be (did = nid); 2) the contents of the final 5 th and 6 th byte word data (data 1) should be in accordance with the contents of the final 3 rd and 4 th byte word data. when the above requirements are met, as well as norma l reception without crc e rrors, the word data is latched to the output latch. latch output is export ed as it is in a normal way as external output. the initial high-impedance setting after hardware reset is main tained at high-impedance until the packet is received as normal.
dual mode circlink? controller datasheet smsc tmc2074 page 51 revision 0.1 (03-29-06) datasheet when the transmission trigger mode is set to exter nal trigger (mode 3, spre2 -0=111), the output port?s least significant pin is converted to the function of str obe output (npostr). when t he requirements of (1) and (2) (listed above) are met, as well as normal recept ion without crc errors, word data is latched to the output latch. when the output status is updated, a strobe signal is transmitted by the npostr pin. as with reception of data, only t he higher order 15-bits are effective. the po15-1 output port?s initial high- impedance setting immediately after hardware reset is maintained at high-impedance until the packet is received as normal. strobe output np ostr has regular output status, and the initial setting after hardware reset is ?high?. updated data tdr: transmission rate cycle (400 ns when 2.5 mbps ) tx: input clock cycle (50 ns when 20 mhz) 1.5*tdr-tx p0 [15:1] p00(npostr) tdr figure 13 - strobe output timing in standalone mode, external trigger mode (mode 3)
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 52 smsc tmc2074 datasheet figure 14 - reception packet buffer configuration (spre [2:0] = other than 111) s i d d i d c p data1-l data1-h . . . output port received packet po [15:1] 15bit output latch comparator data2-l data2-h rsv (00h) rsv (00h) 16 16 1 2 1 = 2 15 15 * final 2 bytes should be reserved in the 00h reserve area. strobe output npostr strobe generator (when data update is 16-bit synchronous)
dual mode circlink? controller datasheet smsc tmc2074 page 53 revision 0.1 (03-29-06) datasheet figure 15- reception packet buffer configuration (spre [2:0]=111) s i d d i d c p data1-l data1-h . . . output port received packet po [15:1] 15bit output latch comparator data2-l data2-h rsv (00h) rsv (00h) 16 16 1 2 1 = 2 15 15 * final 2 bytes should be reserved in the 00h reserve area. strobe output npostr strobe generator (when data update is 16-bit synchronous)
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 54 smsc tmc2074 datasheet 2.11 diagnostic mode diagnostic mode allows node number #31 (*1) to temporarily join a network consisting of 30 or less nodes. the diagnostic mode is set by setting the ndiag pin to 0. the diagnosis mode pin should be set only on the node with largest node number (#n) in the netwo rk; on the other nodes it should be tied to 1. diagnostic mode = off , node number n=5 node number ndiag pin node that gave token designated maxid #01 "1" #02 #05 #02 "1" #03 #05 #03 "1" #04 #05 #04 "1" #05 #05 #05 "1" #01 #05 diagnostic mode = on , node number n=5+1 node number ndiag pin node that gave token designated maxid #01 "1" #02 #05 #02 "1" #03 #05 #03 "1" #04 #05 #04 "1" #05 #05 #05 "0" #06 * #31(compulsion) #31 "1" #01 #31 * because the #06 node does not exist increment to 31 w receiving a packet from node number #31, circlink latc hes the last msb (bit 7) of the last byte and outputs it to the external output, flasho. this functi on is effective regardless of the ndiag pin status, and enables node #31 (*1) to control the flasho outputs of other nodes. after hardware reset, the external output flasho stays in high-impedanc e until a packet is received. (*1) changes depending on the page size setting (ps[1:0]: see below). page size node id for diagnosis 32b (ps[1:0]=11) #31(1fh) 64b (ps[1:0]=10) #15(fh) 128b (ps[1:0]=01) #7(7h) 256b (ps[1:0]=00) #3(3h)
dual mode circlink? controller datasheet smsc tmc2074 page 55 revision 0.1 (03-29-06) datasheet 2.12 network standard time (nst) network standard time (nst) is a 16-bit free-running c ounter. each node adjusts the time after receiving a packet from the clock master node (cm node), ensuri ng that all nodes share t he common standard time on the network. this minimizes phase deviation among nodes within about 100 s. the nst prescaler pin (nstpre2, 0) is used to set the count speed of the nst. the following table lists the relations among setting, re solution, and maximum time: nst prescale nstpre[2:0] prescale resolution max period resolution max period 000 1:32 0.8us 52.4ms 1.6us 105ms 001 1:64 1.6us 105ms 3.2us 210ms 010 1:128 3.2us 210ms 6.4us 419ms 011 1:256 6.4us 419ms 12.8us 839ms 100 1:512 12.8us 839ms 25.6us 1.68s 101 1:1024 25.6us 1.68s 51.2us 3.36s 110 1:2048 51.2us 3.36s 102.4us 6.71s 111 1:4096 102.4us 6.71s 204.8us 13.42s 40mhz xtal 20mhz xtal nst prescale nstpre[2:0] prescale resolution max period resolution max period 000 1:32 1.0us 0.07s 2.0us 0.13s 001 1:64 2.0us 0.13s 4.0us 0.26s 010 1:128 4.0us 0.26s 8.0us 0.52s 011 1:256 8.0us 0.52s 16.0us 1.05s 100 1:512 16.0us 1.05s 32.0us 2.10s 101 1:1024 32.0us 2.10s 64.0us 4.19s 110 1:2048 64.0us 4.19s 128.0us 8.39s 111 1:4096 128.0us 8.39s 256.0us 16.78s 32mhz xtal 16mhz xtal 2.12.1 functions provided by nst automatic generation of packet with time stamp setting one (1) to the nstsend bit in the mode register allows the last 2 bytes in a packet to be reserved for the nst area, and the newest value of nst is automatically sent in t hese 2 bytes (nothing is written in the sending buffer ram). in the case of the clock master node (described in a later section), the same operation is carried out regardless of the nstsend value. the value is used as the time st amp of the packet and also used to maintain synchronization of time on the network.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 56 smsc tmc2074 datasheet nst carry output the change of any digit in nst can be output as a periodic pulse to the nn stcout pin. nstc [3:0] in the carry register (external pin in t he standalone mode) is used to select the digit. the pulse width of the carry output is the same length as one cycle of the nst resolution. as long as nst is synchronized properly, every node can output the pulse with the same phase. time readout accessing the nst register can dynam ically provide the latest time data. since nst is a 16 bit wide counter, it is necessary to read the even address side (10h) first when an 8-bit bus is used. when the even address is read out, the remaining 8 bits of the nst are latched internally 2.12.2 time-synchronous sequence cm and cs nodes to synchronize nst, one clock master (cm) s hould be designated on the net work. the other nodes become clock slave nodes (cs node). the clock master id (cmid) must be set in the cmid register on every node (external pins in the standalone mode). all nodes on the network use the same value as cmid. cm node: cmid equals to its node id only one node on the network counts nst and notifies the cs nodes of the nst by sending packets. cs node: cmid not equal to its node id receives a packet from the node specified by cm id and synchronizes nst with its own clock. preset at first receive the nst counter of each node starts free running immediately after power-up. cs nodes preset the received nst as the nst of its own after receivi ng the first packet from the cm node. this preset operation is performed only once for the first receive. the preset operation is performed after power-up and also immediately after resetting nststop in the mode register from 1 to 0, after writ ing cmid register, and after software reset. phase tracking after second receive the cs nodes that are preset by t he first reception from the cm node sw itch into the time synchronization mode by pll. the cs nodes that switch into p ll operation keep comparing their ns t to the received nst at every receive from the cm node. if the phase is different, the cs nodes dynamically c ontrol the speed of their counters to adjust phase to correspond to the phase of the nst in the cm node. supplement: when the difference count val ue between the receiver?s nst and the received nst from cm node, is +2 and above, the receiver?s counter is slowed to compensat e. when the difference is ?1 and
dual mode circlink? controller datasheet smsc tmc2074 page 57 revision 0.1 (03-29-06) datasheet below, the receiver?s counter is speeded up. when the difference is 0 or +1, the local counter makes no adjustment. 2.12.3 phase error sending frequency and phase error in cm the nst once set in the cs node will gradually drift out of synchronization as time progresses. this is caused by differences between each xtal. the le ss frequently the cm node sends packets, in other words, the longer the sending interval is, the greater the phase deviates. the nst resolution for a 16-mhz xtal is 32 s with the prescaler set to the intermediate (nstpre = 100). for the xtal of precision 100 ppm, the phase error of maximum 200 s per second occurs between two nodes. the minimum period to cause the phase error of 32 s (equals to a lsb of nst) is 0.16 (32/200) seconds. that is to say, if the cm node keeps sending packets every 160 ms or shorter, the phase error of the cm and cs nodes can be kept within 32 s. the following table shows the sending intervals of the cm node that keeps t he phase error within one lsb of nst: nstpre[2:0] nst resolution tx cycle of cm node nst resolution tx cycle of cm node 000 2.0 ( 1.6 ) us =< 10 ( 8 ) ms 1.0 ( 0.8 ) us =< 5( 4 ) ms 001 4.0 ( 3.2 ) us =< 20 ( 16 ) ms 2.0 ( 1.6 ) us =< 10 ( 8 ) ms 010 8.0 ( 6.4 ) us =< 40 ( 32 ) ms 4.0 ( 3.2 ) us =< 20 ( 16 ) ms 011 16.0 ( 12.8 ) us =< 80 ( 64 ) ms 8.0 ( 6.4 ) us =< 40 ( 32 ) ms 100 32.0 ( 25.6 ) us =< 160 ( 128 ) ms 16.0 ( 12.8 ) us =< 80 ( 64 ) ms 101 64.0 ( 51.2 ) us =< 320 ( 256 ) ms 32.0 ( 25.6 ) us =< 160 ( 128 ) ms 110 128.0 ( 102.4 ) us =< 640 ( 512 ) ms 64.0 ( 51.2 ) us =< 320 ( 256 ) ms 111 256.0 ( 204.8 ) us =< 1280 ( 1024 ) ms 128.0 ( 102.4 ) us =< 640 ( 512 ) ms 16mhz( 20mhz ) xtal 32mhz( 40mhz ) xtal the interval that the cm node can s end packets (tx cycle of cm node) is less than the time required for all nodes to send full-size packets to the specific des tination nodes at the same token rotation. the time can be calculated with the following formula. [ calculation ] ( 352.5 br + 11 br b ) n br: bit cycle (br=400ns @2.5 mbps) b: number of data byte (exc ept header as sid, did and c.p) n: node number that is, if the rate is 2 mbps under the 32 page, 32 byte mode, the cm node has the opportunity of sending within 10.4 ms, which is calculated by (352.5 x 0.5 s + 11 x 0.5 s x 29b) x 31. that is frequent enough against 160 ms in the above table on this page.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 58 smsc tmc2074 datasheet communication speed (data rate) and phase error the time difference becomes longer as communicati on speed becomes slower. the reason for this is because some data processing in circlink such as crc check is dependent upon the data rate. the relation between the transfer speed and time differ ence from cm to cs is listed as follows. 16mhz( 20mhz ) xtal 32mhz( 40mhz ) xtal ckp[2:0] communication speed cm --> cs time difference communication speed cm --> cs time difference 000 2.0m ( 2.5m ) bps 27.5 ( 22 ) us 4.0m ( 5.0m ) bps 13.8 ( 11 ) us 001 1.0m ( 1.25m ) bps 55 ( 44 ) us 2.0m ( 2.5m ) bps 27.5 ( 22 ) us 010 500k ( 625k ) bps 110 ( 88 ) us 1.0m ( 1.25m ) bps 55 ( 44 ) us 011 250k ( 312.5k ) bps 220 ( 176 ) us 500k ( 625k ) bps 110 ( 88 ) us 100 125k ( 156.25k ) bps 440 ( 352 ) us 250k ( 312.5k ) bps 220 ( 176 ) us 101 62.5k ( 78.125k ) bps 880 ( 704 ) us 125k ( 156.25k ) bps 440 ( 352 ) us notes : "cm --> cs time difference" does not include cable propagation delay. circlink has an offset value built-in to abs orb the phase error depending on communication speed. moreover, the offset value can be manually set at the higher threshold of the carry register. note: only automatic setup is available in t he standalone mode and condition of nstpre2 = l(0). ofsmod (carry register: bit 15) 0: automatic offset (default) 1: manual offset nstofs4 -0 (carry register: bit 12 to 8) the offset value is selected among 0 to 31. the actual offset time is ?nst resolution x nstofs4-0?. unlock flag synchronization between the nst unlock flag in the cm node and the nst in any other node is tracked by the nstunloc signal in the intsta register. this flag can be used as an interrupt source. in the standalone mode, this flag is output to nintr pin. 0: synchronous lock state, 1: sy nchronous unlock state (default) *about approval condition for sy nchronous lock /unlock state - unlock to lock state (nstunloc=0) the difference between own nst and nst from cm node is within +/-2. and nst from cm node must be received three times or more continuously, and a ll of those differences must be within +/-2. - lock to unlock state (nstunloc=1) the difference between own nst and nst from cm node is not within +/-2. or nst from cm node must be received three times or more continuous ly, and all of those differences are not within +/-2.
dual mode circlink? controller datasheet smsc tmc2074 page 59 revision 0.1 (03-29-06) datasheet a possible cause of unlock status not being cancelled is t hat the cm node?s nst pre-scalar setting is not synchronized. a possible cause of sometimes falling in to unlock status is that the cm node?s transmission frequency is low. in the case of cm node, the flag becomes 0 in a steady state (syn chronous lock status) for no apparent reason. as the initial settings in this case depends on the function modes, listed below: in peripheral mode, the cm node id is set in a regist er after cancellation of hardware reset. after these values are imported, the output is 1 until the node bec omes a cm node (it becomes 0 after that). during software reset, due to the cm node id being immediat ely imported, the cm n ode id is fixed at 1and transitioning to 0 immediately afte r being set up in the register. in standalone mode, the cm node id is a pin setting; when it is the sa me setting as the cm node setting, output is 1 during hardware reset, and 0 when hardware reset is cancelled. unlock phase difference register the phase difference between the ns t in the cm node and the nst in the subject node can be monitored through the nstdif register. difdir (nstdif register: bit 15) indicates the direction of phase difference 0: ahead of cm node 1: behind of cm node nstdif 14-0 (nstdif register: bit 14-0) absolute difference from the cm node is indicated as a value from 0 to 32,768. accessing the nstdif register can dy namically provide the latest time data. since nstdif is a 16 bit value, it is necessary to read the even address si de (32h) first when 8-bit bus is used. when the even address is read out, the remaining 8 bits of the nst are latched internally.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 60 smsc tmc2074 datasheet 2.12.4 nnstcout pulse generation cycle 20mhz - xtal nstpre[2:0] resolution / max period nstc[3:0] cycle nstc[3:0] cycle 0000 3.2us 1000 819.2us 0001 6.4us 1001 1.6ms 0010 12.8us 1010 3.3ms 0011 25.6us 1011 6.6ms 0100 51.2us 1100 13.1ms 0101 102.4us 1101 26.2ms 0110 204.8us 1110 52.4ms 0111 409.6us 1111 104.9ms 0000 6.4us 1000 1.6ms 0001 12.8us 1001 3.3ms 0010 25.6us 1010 6.6ms 0011 51.2us 1011 13.1ms 0100 102.4us 1100 26.2ms 0101 204.8us 1101 52.4ms 0110 409.6us 1110 104.9ms 0111 819.2us 1111 209.7ms 0000 12.8us 1000 3.3ms 0001 25.6us 1001 6.6ms 0010 51.2us 1010 13.1ms 0011 102.4us 1011 26.2ms 0100 204.8us 1100 52.4ms 0101 409.6us 1101 104.9ms 0110 819.2us 1110 209.7ms 0111 1.6ms 1111 419.4ms 0000 25.6us 1000 6.6ms 0001 51.2us 1001 13.1ms 0010 102.4us 1010 26.2ms 0011 204.8us 1011 52.4ms 0100 409.6us 1100 104.9ms 0101 819.2us 1101 209.7ms 0110 1.6ms 1110 419.4ms 0111 3 . 3 ms 1111 838 . 9 ms 0000 51.2us 1000 13.1ms 0001 102.4us 1001 26.2ms 0010 204.8us 1010 52.4ms 0011 409.6us 1011 104.9ms 0100 819.2us 1100 209.7ms 0101 1.6ms 1101 419.4ms 0110 3.3ms 1110 838.9ms 0111 6.6ms 1111 1.68s 0000 102.4us 1000 26.2ms 0001 204.8us 1001 52.4ms 0010 409.6us 1010 104.9ms 0011 819.2us 1011 209.7ms 0100 1.6ms 1100 419.4ms 0101 3.3ms 1101 838.9ms 0110 6.6ms 1110 1.68s 0111 13.1ms 1111 3.35s 0000 204.8us 1000 52.4ms 0001 409.6us 1001 104.9ms 0010 819.2us 1010 209.7ms 0011 1.6ms 1011 419.4ms 0100 3.3ms 1100 838.9ms 0101 6.6ms 1101 1.68s 0110 13.1ms 1110 3.35s 0111 26.2ms 1111 6.71s 0000 409.6us 1000 104.9ms 0001 819.2us 1001 209.7ms 0010 1.6ms 1010 419.4ms 0011 3.3ms 1011 838.9ms 0100 6.6ms 1100 1.68s 0101 13.1ms 1101 3.35s 0110 26.2ms 1110 6.71s 0111 5 2 .4ms 1111 13 .4 2 s note: nnstcout outputs low pulse qual to the nst resolution pulse cycle of nnstcout 010 6.4us/419ms 011 12.8us/839ms 1.6us/105ms 000 nst resolution setting 001 3.2us/210ms 100 25.6us/1.68s 101 51.2us/3.35s 110 102.4us/6.71s 111 204.8us/13.42s
dual mode circlink? controller datasheet smsc tmc2074 page 61 revision 0.1 (03-29-06) datasheet 16mhz - xtal nstpre[2:0] resolution / max period nstc[3:0] cycle nstc[3:0] cycle 0000 4.0us 1000 1.0ms 0001 8.0us 1001 2.0ms 0010 16.0us 1010 4.1ms 0011 32.0us 1011 8.2ms 0100 64.0us 1100 16.4ms 0101 128.0us 1101 32.8ms 0110 256.0us 1110 65.5ms 0111 512.0us 1111 131.1ms 0000 8.0us 1000 2.0ms 0001 16.0us 1001 4.1ms 0010 32.0us 1010 8.2ms 0011 64.0us 1011 16.4ms 0100 128.0us 1100 32.8ms 0101 256.0us 1101 65.5ms 0110 512.0us 1110 131.1ms 0111 1.0ms 1111 262.1ms 0000 16.0us 1000 4.1ms 0001 32.0us 1001 8.2ms 0010 64.0us 1010 16.4ms 0011 128.0us 1011 32.8ms 0100 256.0us 1100 65.5ms 0101 512.0us 1101 131.1ms 0110 1.0ms 1110 262.1ms 0111 2.0ms 1111 524.3ms 0000 32.0us 1000 8.2ms 0001 64.0us 1001 16.4ms 0010 128.0us 1010 32.8ms 0011 256.0us 1011 65.5ms 0100 512.0us 1100 131.1ms 0101 1.0ms 1101 262.1ms 0110 2.0ms 1110 524.3ms 0111 4 . 1 ms 1111 1 . 0 5s 0000 64.0us 1000 16.4ms 0001 128.0us 1001 32.8ms 0010 256.0us 1010 65.5ms 0011 512.0us 1011 131.1ms 0100 1.0ms 1100 262.1ms 0101 2.0ms 1101 524.3ms 0110 4.1ms 1110 1.05s 0111 8.2ms 1111 2.10s 0000 128.0us 1000 32.8ms 0001 256.0us 1001 65.5ms 0010 512.0us 1010 131.1ms 0011 1.0ms 1011 262.1ms 0100 2.0ms 1100 524.3ms 0101 4.1ms 1101 1.05s 0110 8.2ms 1110 2.10s 0111 16.4ms 1111 4.19s 0000 256.0us 1000 65.5ms 0001 512.0us 1001 131.1ms 0010 1.0ms 1010 262.1ms 0011 2.0ms 1011 524.3ms 0100 4.1ms 1100 1.05s 0101 8.2ms 1101 2.10s 0110 16.4ms 1110 4.19s 0111 32.8ms 1111 8.39s 0000 512.0us 1000 131.1ms 0001 1.0ms 1001 262.1ms 0010 2.0ms 1010 524.3ms 0011 4.1ms 1011 1.05s 0100 8.2ms 1100 2.10s 0101 16.4ms 1101 4.19s 0110 32.8ms 1110 8.39s 0111 6 5.5ms 1111 16 .7 8 s note: nnstcout outputs low pules equal to the nst resolution pulse cycle of nnstcout 010 8.0us/524ms 011 16.0us/1.05s 2.0us/131ms 000 nst resolution setting 001 4.0us/262ms 100 32.0us/2.10s 101 64.0us/4.19s 110 128.0us/8.39s 111 256.0us/16.78s
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 62 smsc tmc2074 datasheet nst supplements setting nst send mode nullifies the last two-byte areas in the sending buffer. that is, the nst value is not written in the last two-byte areas. the nst value is directly loaded to the parallel-to-serial conversion register for transmit without using the buffer area ra m (not stored in a buffer). therefore, the circlink always sends the newest nst value. in addition, the clock master node (cm) sends nst, regardless of the nst send mode (cm node forcibly enters the nst sending mode). the nst value to be sent is the value immediately bef ore the last two bytes are sent to the parallel to serial conversion register. in the other words, the nst value shows t he time immediately after sending the third data from the last. from the viewpoint of the receiver , the nst value is stored at the la st two bytes area in the buffer page corresponding to the sid value of the received packet. if the sid value in the rece ive packet is the id of the clock master node, its nst val ue is automatically adjus ted. the received nst becomes available for time adjustment at the time when ending ?0? bec omes ok after crc error check completion. 2.13 cmi modem refer to appendix a - cmi modem at the end of this document. 2.14 hub function circlink integrates a 3-port hub function to expand the network. the hub function enables conversion of different communication media among twist-pair cable, fiber optics, and the lik e. in addition, the hub function expands the connection node number and cable lengt h limitations caused by transceiver performance limitations. the hub function is enabled by nhubon pin. among th ree ports, one is used internally for the connection to circlink main unit and the remaini ng two are used as external ports.
dual mode circlink? controller datasheet smsc tmc2074 page 63 revision 0.1 (03-29-06) datasheet cmi cmi 3-port hub port-1 port-2 circlink core case of nhubon=h rxin , txen , txd rxin2 , txen2 , txd (shared) nhubon=h nhubon=l off on port1 port1,port2 hub function communication port figure 16 - internal 3 port hub block diagram
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 64 smsc tmc2074 datasheet 2.14.1 operation example of hub function 1. dividing bus connection the bus can be electrically divided by setting the hub function on. circlink (hub= on ) port1 port2 port1 circlink (hub= off ) port1 circlink (hub= off ) port1 circlink (hub= off ) port1 circlink (hub= off ) bus topology-2 bus topology-1 t t :terminator tr. tr. t :transceiver tr. tr. tr. tr. tr. t 2. cascade connection fiber optics can be connected as ca scade by using the hub function. circlink (hub= on ) port1 port2 tr. tr. circlink (hub= on ) port1 port2 tr. tr. tr. tr. circlink (hub= on ) port1 port2 tr. tr. peer to peer peer to peer peer to peer : transceiver tr. t t t t t t t t : terminator t (in optical fiber unnecessary) circlink (hub= on ) port1 port2 circlink (hub= on ) port1 port2 peer to peer tr. t tr. t
dual mode circlink? controller datasheet smsc tmc2074 page 65 revision 0.1 (03-29-06) datasheet 2.14.2 timer expansion in mu lti-stage cascade connection an extra delay of 0.5 s is added to the message when hub is set to on. a delay of 2.0 s is also added in the cmi coding/decoding processing when cmi is set to on. when configuring a cascade connection and setting both hub and cmi to on, a 2.5 s (2.0 s + 0.5 s) delay is added to a message every time the message passes a node. this delay may make the response timer timeout in the circlink, causing communication failure. the response timer monitors responses from the nodes and is normally set to 74.6 s. the one way propagation delay time permitted for cable, hub circuit, and cmi decoding/coding circuit is 31 s, which is calculated by (74.6 s - 12.6 s)/2; where 12.6 s is the circlink response time. this is equivalent to the delay time of a 12-stage cascade connection hub/cmi circuit. (31 s / 2.5 s = 12.4 -> 12-stage) if the sum of cable delay and hub/cmi delay is over 31 s, set et1 to 0 to extend the response timeout time to 298.4 s, which is four times longer than the normal delay time. taking this measures, the one way propagation delay time is extended to (298.4 s ? 12.6 s) /2 = 142.9 s. (142.9 s / 2.5 s = 57.2 -> 57- stage). response timer idle timer configuration timer 74.6us 82us 52ms 298.4us 328us 104ms the timer can be set by the et1 pin or internal regist er and has a structure of a nd logic in the circlink as shown below. (default"1") et1 et1 :pin et1 :register remarks: the typical time delay added in on state hub is 0.5 s. however, it is extended to 1.0 s if the optical mode is on (nopmd = l) and cmi is off (ncmibyp = l). note: values in text and table are bas ed on a 2.5 mbps network speed. w hen circlink operates at 1.25 mbps, the value should be doubled. when oper ating at 5 mbps, the value s hould be half. to be precise, the propagation delay time of the cable and the transceiver should also be added.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 66 smsc tmc2074 datasheet 2.15 8-bit general-purpose i/o port (new function) when circlink is used in the peripher al mode, 11* or more general- purpose i/o ports (gpio) are utilized as the cpu interface with circlink. (* for 8-bit data bus and multiplex bus mode). eight gpios are added to the circlink side as the substitution (gpio7-0 pins). two registers named "direction cont rol register" and "data register" are added for the gp-i/o control. moreover, to allocate these registers in comr 7 (address=0eh), the subaddress is enhanced by one bit (subad3). - sub address register -> sub address : subad3-0 (address=0ah) the subaddress is enhanced by subad3 bit - direction control register -> gp-i/o direc tion : ngpoe7-0 (address=0eh, subad=1011) gp-i/o direction control register --- the direction can be set by every one bit. ngpoex = 0 : output mode ngpoex = 1 : input mode - data register -> gp-i/o data : gpd7-0 (address=0eh, subad=1010) gp-i/o data register gpd7-0 : write operation ---- writ e data which outputs to gpip7-0 pin : read operation ---- read t he state of the gpio7-0 pin s d q d q r gp-i/o direction ? control register ngpoe x (0: output , 1: input) gp-i/o data register gpd x gpio x pins 4ma ttl gp-i/o diagram (per 1bit) vdd (x : 0-7) (x : 0-7)
dual mode circlink? controller datasheet smsc tmc2074 page 67 revision 0.1 (03-29-06) datasheet chapter 3 description of registers 3.1 register map table 7 shows the circlink regist er map. all registers are 16 bi ts wide and can be word-accessed and byte-accessed in 16-bit mode (w16 = h) and 8-bit mode (w16 = l) respectively. in the case of byte access, the lower byte (bits 7 to 0) is assigned to an even address and the upper byte (bits 15 to 8) to an odd address by default. this assignment can be reversed by setting the nswap pin to l. table 7 - circlink register map adr. : cpu address a[5:0] in hex value. (addre ss 00h to 0fh are registers specific to arcnet) - word access (w16=high) adr. d15 - d0 adr. d15 - d0 adr. d15 - d0 adr. d15 - d0 00 comr0 10 nst 20 cmid 30 ckp 02 comr1 12 intsta 22 mode 32 nstdif 04 comr2 14 intmsk 24 carry 34 pininfo 06 comr3 16 eccmd 26 rxmh 36 not used 08 comr4 18 rsid 28 rxml 38 not used 0a comr5 1a ssid 2a maxid 3a errinfo 0c comr6 1c rxfh 2c nid 3c reserved 0e comr7 1e rxfl 2e ps 3e reserved - byte access and no swap (w16=low, nswap=high) adr. d7 - d0 adr. d7 - d0 adr. d7 - d0 adr. d7 - d0 00 comr0 10 nst - l 20 cmid 30 ckp 01 (all zero) 11 nst - h 21 (all zero) 31 (all zero) 02 comr1 12 intsta - l 22 mode - l 32 nstdif - l 03 (all zero) 13 intsta - h 23 mode - h 33 nstdif - h 04 comr2 14 intmsk - l 24 carry - l 34 pininfo - l 05 (all zero) 15 intmsk - h 25 carry - h 35 pininfo - h 06 comr3 16 eccmd 26 rxmh - l 36 not used 07 (all zero) 17 (all zero) 27 rxmh - h 37 not used 08 comr4 18 rsid 28 rxml - l 38 not used 09 (all zero) * 19 mrsid 29 rxml - h 39 not used 0a comr5 1a ssid 2a maxid 3a errinfo- l 0b (all zero) 1b (all zero) 2b (all zero) 3b errinfo- h 0c comr6 1c rxfh - l 2c nid 3c reserved 0d (all zero) 1d rxfh - h 2d (all zero) 3d reserved 0e comr7 1e rxfl - l 2e ps 3e reserved 0f (all zero) 1f rxfl - h 2f (all zero) 3f reserved *: when the word-mode is enabled (wdmd _ bit=1), this address is mapped another comr4.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 68 smsc tmc2074 datasheet - byte access and swap (w16=low, nswap=low) adr. d7 - d0 adr. d7 - d0 adr. d7 - d0 adr. d7 - d0 00 (all zero) 10 nst - h 20 (all zero) 30 (all zero) 01 comr0 11 nst - l 21 cmid 31 ckp 02 (all zero) 12 intsta - h 22 mode - h 32 nstdif - h 03 comr1 13 intsta ? l 23 mode - l 33 nstdif - l 04 (all zero) 14 intmsk - h 24 carry - h 34 pininfo - h 05 comr2 15 intmsk - l 25 carry - l 35 pininfo - l 06 (all zero) 16 (all zero) 26 rxmh - h 36 not used 07 comr3 17 eccmd 27 rxmh - l 37 not used 08 (all zero) * 18 mrsid 28 rxml - h 38 not used 09 comr4 19 rsid 29 rxml - l 39 not used 0a (all zero) 1a (all zero) 2a (all zero) 3a errinfo- h 0b comr5 1b ssid 2b maxid 3b errinfo- l 0c (all zero) 1c rxfh - h 2c (all zero) 3c reserved 0d comr6 1d rxfh - l 2d nid 3d reserved 0e (all zero) 1e rxfl - h 2e (all zero) 3e reserved 0f comr7 1f rxfl - l 2f ps 3f reserved *: when the word-mode is enabled (wdmd _ bit=1), this address is mapped another comr4. initial value of each register the value under ?init.value? in each regist er list indicates the initial value when hardware reset is applied to circlink via the nreset pin. with some exceptions, software reset does not initialize them . exceptions (software reset available) circlink internal communication protocol controller comr0 register (r) : all status information comr0 register (w) : all interrupt masks comr1 register (r) : all diagnostic information comr1 register (w) : all commands issued eccmd register : all commands issued intsta register : all ec status information intmsk register : all ec interrupt masks rxfh, rxfl registers : all receive flags errinfo register : all error information hardware reset : resets entire circlink unit. performed by nreset pin set to l.
dual mode circlink? controller datasheet smsc tmc2074 page 69 revision 0.1 (03-29-06) datasheet software reset : resets only the units related to communication functions. the reset method is described as below. how to do software reset 1) permanent software reset set the reset bit of the comr6 register to 1 (retains until the bit is changed to 0) set the node id set to 00h (retains until the setting is changed to other than 00h) 2) temporary software reset software reset occurs for 100 ns (at 20 mhz clk i nput) immediately after rewriting the object bits or writing the object registers. this reset is automatically released. rewriting inimode bit of the mode register rewriting txen bit of comr6 or mode register from 0 to 1 rewriting the following registers for inimode = 1 maxid register nid register ps register ckp register notes: ? the communication function unit w ill start operation within 1.0 s (at 2.5 mbps) after releasing software reset. it is therefore necessary to wait for at least 1.0 s (at 2.5 mbps) after releasing software reset before writing data to a register re set by software (see previous page). the writing can be ignored. after 10 s (at 2.5 mbps) following the software reset, d 1h is written to address = 0 in page #00 of the ram and node id value is written to the address = 1. ? values in text are at 2.5 mbps. when 1.25 m bps, the value should be doubled accordingly. when 5 mbps, the value should be half of the 2.5mbps? respectively.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 70 smsc tmc2074 datasheet 3.2 details of register 3.2.1 comr0 register: stat us/interrupt mask register comr0 (status register) address:00h [read] bit name init. value description 15-8 -------- 0 reserved (all "0") *1 7 -------- 1 reserved 6,5 -------- 1,1 reserved 4 por 1 power on reset 3 -------- 0 reserved 2 recon 0 reconfiguration 1 tma 0 transmitter message acknowledged 0 ta 1 transmitter available comr0 (mask register) address:00h [write] bit name init. value description 15-8 -------- 0 reserved (all "0") *1 7 -------- 0 reserved ("0") 6-4 -------- 0,0,0 reserved (all "0") 3 excnak 0 excessive nak 2 recon 0 reconfiguration *1 1 nxtiderr 0 next id error 0 ta 0 transmitter available *1 not equivalent to the arcnet original specifications. - when reading: arcnet status register por (bit 4) when this bit is 1, it indicates t hat a hardware or software reset has occurred.. this bit can be cleared by writing the por clear command (0eh). recon (bit 2) when this bit is 1 it indicates that a reconfiguration has occurred. this bit can be cleared by software reset or by writing the recon clear command (16h). tma (bit 1) when this bit is 1, it indicates that a trans mission has been performed correctly (except broadcast messages). this bit is valid only after the ta bit has been set to 1 and can be cleared by a software reset or by writing the send command (03h). ta (bit 0) when this bit is 1, it indicates that sending is comple te, and 0 indicates that sending is in progress. this bit becomes 0 when a write or send co mmand (03h) is executed. in free buffer mode (txm = 0) or a one-
dual mode circlink? controller datasheet smsc tmc2074 page 71 revision 0.1 (03-29-06) datasheet packet send at remote buffer mode (txm = 1 and rto = 1), this bit becomes 1 by the completion of the one-packet send or written send-cancellation command (01h) . this bit also becomes 0 after the first send command and remains 0 until the tx cancel command is issued. under this condition the node will automatically continue to send. this bit becomes 1 when the mode exit s from the consec utive automatic send with the writing of the send c ancellation command (01h) or rto bit = 1.the same ta bit also exists in bit 0 of the ec interrupt status register. this bit can also be set by a software reset. - when writing: arcnet mask register (cleared by software reset) excnak (bit 3) this bit is set to 1 and the excnak bit in the co mr1 (diagnostic register) becomes 1 to generate the interrupt. (the com bit in the ec interrupt mask register = 1) recon (bit 2) this bit is set to 1 and the recon bit in the status register (comr0) becomes 1 to generate the interrupt. (the com bit in the ec interrupt mask register = 1) nxtiderr (bit 1) this bit is set to 1 and the nxtiderr bit in the diagnostic register (comr1) becomes 1 to generate the interrupt. (the com bit in the ec interrupt mask register = 1) ta (bit 0) this bit is set to 1 and the ta bit in the status register (comr0) becomes 1 to generate the interrupt. (the com bit in the ec interrupt mask register = 1)
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 72 smsc tmc2074 datasheet 3.2.2 comr1 register: di agnostic/command register comr1 (diagnostic register) address:02h [read] bit name init. value description 15-8 -------- 0 reserved (all "0") 7 my-recon 0 my reconfiguration 6 dupid 0 duplicate id 5 rcvact 0 receive activity 4 token 0 token seen 3 excnak 0 excessive nak 2 tentid 0 tentative id *1 1 nxtiderr 0 new next id 0 -------- 0 reserved comr1 (command register) address:02h [write] bit name init. value description 15-8 -------- -- reserved (all "0") 7-0 d7-0 -- d7-0 *1 not equivalent to the arcne t original specifications. - when reading: arcnet diagnostic register my-recon (bit 7) when this bit is 1, it indicates that the local rec onfiguration timer has timed out. this timeout sends a reconfiguration burst signal. it is read after an in terrupt has been generated by setting recon bit = 1. (recon bit = 1 is set after my-rec on bit is set to 1.) the bit is cleared when read or by software reset. dupid (bit 6) when this bit is 1 in the offline state (txen = 0), it indicates that a duplicate node id exists on the network. in this state, the netwo rk cannot be accessed (txen = 1). check t hat all the node id settings are correct. in the online state (txen = 1), dupid is set to 1 every time a token addressed to it is received**. this bit is cleared when read or by software reset. ** disregard this first setting of dupid=0 -> 1. the second setting indicates a token addressed to its own circlink. rcvact (bit 5) when this bit is 1, it indicates that activity has been detected at the circlink re ceive input. this bit is cleared when read or by software reset. token (bit 4) when this bit is 1, it indicates that a token signal on the network has been detect ed. note that the token signal sent by this bit cannot be detected. this bit is cleared when read or by software reset.
dual mode circlink? controller datasheet smsc tmc2074 page 73 revision 0.1 (03-29-06) datasheet excnak (bit 3) when this bit is 1, it indicates that a ?nak? wa s received 4 or 128 times from the receiving node (four naks is determined by a bit setting) in response to ?free buffer enquiry? during the send. it is possibly caused by the blind state (ecri = 1) of the destinat ion node. this bit can not be cleared by a bit-read but can be cleared by software reset or by writing the excnak clear command (0eh). tentid (bit 2) when this bit is 1, it indicates t hat the comr7-000 (tent ative id register) matches the id value in a token signal in the network. note that the id value in a to ken signal sent by this bi t itself cannot be compared. with the function in normal online state (txen = 1), a node id map of the network can be created. this bit is cleared when read or by software reset. nxtiderr (bit 1) this bit is set when receiving no response from the token passed to the node with the id of node id + 1 *2 and the token is passed to another node. this bit can be cleared by a software reset or by the writing of nxtiderr clear command (09h), but is not cleared when read. *2: node 01 when the node is maxid node. note: to detect the dupid and tentid bits, wait for the ma ximum polling cycle time of token after the nid or tentid value is changed. - when writing: arcnet command register this command register is not used in circlink: the ec command regist er in 3.2.12 must be used. the commands described there include all valid circlink commands.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 74 smsc tmc2074 datasheet 3.2.3 comr2 register: page register comr2 (page register) address:04h [read/write] bit name init. value description 15-8 -------- 0 reserved (all "0") 7 rddata x read data 6 autoinc x auto increment *1 5 nwrapar 0 wrap-around mode *1 4-0 page4-0 x page 4-0 *1: not equivalent to the arcnet original specifications. (bit length variable) - when reading/writing: arcnet addre ss pointer upper register (new) rddata (bit 7) this bit specifies the type of acce ss to data register (comr4) handled. 1: read from data register 0: write to data register autoinc (bit 6) this specifies an automatic incr ement mode of the ramadr accessi ng data register (comr4). the incremental value is +1 for 8-bit bus width and 0 wo rd mode (w16 = l, wdmd = 0), and +2 for 8-bit bus width and 1 word mode (w16=l, wdmd=1) or 16-bit bus width (w16=1). 1: automatically incremented 0: not automatically incremented nwrapar (bit 5) this bit specifies internal operati on mode when the most significant bit (msb) of ramadr is carried over. 1: move to the top of the next page 0: go back to the top of the current page page 4-0 (bits 4 to 0) these bits specify the page num bers of the packet buffers. rewriting thes e five bits is not valid before the address in the page (comr3) is written. note that the upper lim it of the specifiable value is restricted by the page size, and unnecessary higher bits are deleted.
dual mode circlink? controller datasheet smsc tmc2074 page 75 revision 0.1 (03-29-06) datasheet 3.2.4 comr3 register: page -internal address register comr3 (address register) address:06h [read/write] bit name init. value description 15-8 -------- 0 reserved (all "0") *1 7-0 ramadr7-0 x ram address 7-0 *1: not equivalent to arcnet original specifications. (the bit length variable) - when reading/writing: arcnet addre ss pointer lower register (new) ramadr 7-0 (bits 7 to 0) these bits specify addresses in t he pages of the packet buffers. when t he autoinc bit of comr2 is 1, the value increments every time the data register (com4) is accessed. the upper limit of the specifiable value is restricted by the size of the page. the comr2 page (page) and comr3 page- internal address (ramadr) registers actually comprise one 10-bit register. the boundary differs depending on the s pecification of the page size, as shown below: page + ramadr (10bit reg.) 9876543210 ps=11: 32page , 32byte ps=10: 16page , 64byte ps=01: 8page ,128byte ps=00: 4page ,256byte references of 2.5.1 chapter "ram access" about the structure of a/the packet buffe r ramadr4-0 ramadr-5-0 ramadr6-0 ramadr7-0 page4-0 page3-0 page2-0 page1-0 in continuously accessing data register with aut oinc = 1 set, you can specify how to carry out overflowing ramadr with nwrapar bit of comr2. zero (0) set-up carries it out to the top of the current page and one (1) set-up move it to the top of the next page (or to #00 if t he current is the final page). an example of the operation at ps = 11 is shown below. nwrapar=1 nwrapar=0 page4-0=00001, ramadr4-0=11111 page4-0=00001, ramadr4-0=11111 page4-0=00010, ramadr4-0=00000 page4-0=00001, ramadr4-0=00000
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 76 smsc tmc2074 datasheet comr4 register: data register (1) 16 bit mode (w16=h) comr4 (data register) address:08h [read/write] bit name init. value description *1 15-0 ramdt15-0 x ram data 15-0 (2) 8 bit mode and word mode=on (w16=l, wdmd=1) comr4 (data register) address:08h/09h [read/write] bit name init. value description *1 15-8 ramdt15-8 x ram data 15-8 *1 7-0 ramdt7-0 x ram data 7-0 note: to preserve the upper and lower bytes of word data in the same packet, comr4 must be accessed in the order of 08h access 09h access. (access in the order of 09h 08h, 08h 08h, or 09h 09h will not preserve this data). this restriction applies to both reading and writing. the upper/lower relationship is selected by the nswap pin. (3) 8 bit mode and word mode=off (w16=l, wdmd=0) comr4 (data register) address:08h or 09h [read/write] bit name init. value description 15-8 -------- 0 reserved (all "0") *1 7-0 ramdt7-0 x ram data 7-0 *1 not equivalent to the arcne t original specifications. - when reading/writing: arcnet data register(new) writing/ reading out the address in the 1 kbyte ram is indicated by the page register and intra-page address register. data access to packet bu ffer is performed via the data register. reading/writing is set by the rddata bit of comr2. note: data can be accessed using settings in the rddata regi ster only. for example, dat a register writing with rddata = 1 setting, or data register reading with rddata = 0 setting will not normally be completed.
dual mode circlink? controller datasheet smsc tmc2074 page 77 revision 0.1 (03-29-06) datasheet 3.2.5 comr5 register: sub-address register comr5 (sub-address reg.) address:0ah [read/write] bit name init. value description 15-4 -------- 0 reserved (all "0") 3-0 subad3-0 0,0,0, 0 sub address 3-0 note: do not set the value ?5-9h, c-fh? to subad3-0. - when reading/writing: a rcnet sub-address register subad [2:0] (bits 2 to 0) specifying sub-addresses for selecting seven regist ers assigned to comr7. be sure to set the sub- address first, and then access to comr7. subad3-0 = 0000 (0h) : selection of tentative id register subad3-0 = 0001 (1h) : selection of node id register subad3-0 = 0010 (2h) : selection of setup1 register subad3-0 = 0011 (3h) : selection of next id register (only read) subad3-0 = 0100 (4h) : selection of setup2 register subad3-0 = 1010 (ah) : selection of gpio data register subad3-0 = 1011 (bh) : selection of gpio direction control register
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 78 smsc tmc2074 datasheet 3.2.6 comr6 register: c onfiguration register comr6 (configurati on reg.) address:0ch [read/write] bit name init. value description 15-8 -------- 0 reserved (all "0") 7 reset 0 reset *1 6 -------- 0 reserved ("0") *3 5 txen 0/1 *4 transmit enable 4 et1 1 extended timeout 1 3 et2 1 extended timeout 2 *2 2 backplan 1 back plane *5 1-0 -------- 0,0 reserved (all "0") *1 not equivalent to the arcne t original specifications. (function elimination) *2 not equivalent to the arcne t original specifications. (change initial value) *3 not equivalent to the arcne t original specifications. (additional function) *4 the initial value changes by operation mode. 0 (off line) at the time of peripheral mode 1 (on line) at the ti me of standalone mode. *5 these specification are not equal with arcnet specification. (subad1-0 be integration to the comr5 register ) - when reading/writing: arcne t configuration register reset (bit 7) this bit sets a software reset. se tting this bit to 1 causes softwar e reset and setting 0 releases it. txen (bit 5) this bit sets access to the network (online and offli ne respectively); setting 1 to this bit is on-line and setting 0 is off-line. a temporary software reset is applied when the bit is changed from 0 to 1. (the software reset is released automatically.) the softwar e reset is not applied when the bit is changed from 1 to 0. this bit is the same as the txen bit in the mode regi ster described in 3.2.18, whic h is the bit usually used.
dual mode circlink? controller datasheet smsc tmc2074 page 79 revision 0.1 (03-29-06) datasheet et1, et2 (bits 4 and 3) these bits set the timeout time of the response and idle timers. the fo llowing timeout times are the values applicable when the transfer rate is 2.5 m bps (the values become half at 5 mbps). et2,et1 = 0,0 response timer = 1193.6 us idle timer = 1312 us max distances = 118.4 km et2,et1 = 0,1 response timer = 596.8 us idle timer = 656 us max distances = 57.6 km et2,et1 = 1,0 response timer = 298.4 us idle timer = 328 us max distances = 28.8 km et2,et1 = 1,1 response timer = 74.7 us idle timer = 82 us max distances = 6.4 km these timeout times must be identical in every node on the network. refer to the description of the rcntm1, 0 bits in the setup2 register. backplan (bit 2) this bit selects back plane mode and normal (dipulse) mode; setting 1 to the bit selects back plane mode and setting 0 selects normal (dipulse) mode. back plane mode is usually used (default).
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 80 smsc tmc2074 datasheet 3.2.7 comr7 register seven registers are defined for comr 7, selected by the selection of the subad [3:0] bits of comr5. comr7-0000 (tent. id register) address:0eh [read/write] subad=0000 bit name init. value description 15-5 -------- 0 reserved (all "0") *1 4-0 tid4-0 all "0" tentative node id *1 not equivalent to the arcne t original specifications. (reduction in a the number of bits) - when reading/writing: arcne t tentative id register tid [4:0] (bits 4 to 0) the id value specified by this regi ster is compared with the id value in a token signal in the network and the results indicated by the tentid bit of the diagnostic register. te ntid becomes 1 if the comparison result matches. comr7-0001 (node id register) address:0eh [read/write] subad=0001 bit name init. value description 15-5 -------- 0 reserved (all "0") *1 4-0 nid4-0 all "0" my node id *1 not equivalent to the arcne t original specifications. (reduction the number of bits) - when reading/writing: arcnet node id register nid [4:0] (bits 4 to 0) when inimode = 1, this bit specifies the node id. this function is the same as t hat of the nid register described in 3.2.23, which is usua lly used instead of this register.
dual mode circlink? controller datasheet smsc tmc2074 page 81 revision 0.1 (03-29-06) datasheet comr7-0010 (setup1 register) address:0eh [read/write] subad=0010 bit name init. value description 15-8 -------- 0 reserved (all "0") *1 7 -------- 1 reserved ("1") 6 fournaks 0 four nacks 5 -------- 0 reserved ("0") 4 -------- 0 reserved ("0") 3-1 ckp2-0 0,0,0 clock prescaler bits 2,1,0 0 -------- 0 reserved ("0") *1: not equivalent to the arcnet original specifications. (func tion elimination) - when reading/writing: arcnet setup1 register fournaks (bit 6) this bit specifies the number of nak responses to t he "free buffer enquiry", func tion of the excnak bit of the diagnostic register. setting 1 to this bit s pecifies 4 times, and to 0 specifies 128 times. ckp [2:0] (bits 3 to 1) inimode = 1 specifies the communication speed (transfer ra te). this function is t he same as that of the ckp register described in 3.2.25, which is usually used instead of this register. comr7-0011 (next id register) address:0eh [read only] subad=0011 bit name init. value description 15-5 -------- 0 reserved (all "0") *1 4-0 nextid4-0 all "0" next node id *1: not equivalent to the arcnet original specifications. (reduction the number of bits and function modifications) note: do not write to this register. - when reading: arcnet next id register nextid [4:0] ( bit 4 to 0) it is possible for the node to read out value of the node id from a sending node. in circlink, the following id value is fixed to the id value of the node + 1. in case of no response after sending the token to the node of id value equaling to the node id + 1 (absent re ceiver) and the token is passed to another node, the nxtiderr bit of the diagnostic register will be set to 1.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 82 smsc tmc2074 datasheet comr7-0100 (setup2 register) address:0eh [read/write] subad=0100 bit name init. value description 15-8 -------- 0 reserved (all "0") *1 7 -------- 0 reserved ("0") *3 6 farb 0 reserved ("0") *1 5,4 -------- 0,0 reserved (all "0") *1 3 -------- 1 reserved ("0") *1 2 -------- 1 reserved ("0") *2 1-0 rcntm1-0 1,1 reconfiguration (recon) timer 1,0 *1 not equivalent to the arcnet origi nal specifications. (reduction function ) *2 not equivalent to the arcnet original specifications. (change initial value) *3 not equivalent to the arcnet original specifications. (addition of new function) - when reading/writing: arcnet setup2 register farb (bit 6) increases the speed of the ram access controller. in default setting, it se ts the yes/no setting of temporary relay reception of 128 byte/page during ckp=000 setting. fo r further details, please refer to section 2.9.1 - temporary receive and direct receive. 0: 128-byte/page temporary relay reception denied (default), ram access controller input clock has a single-sided function. 1: 128-byte/page temporary relay reception allowed ram access controller input clock has a double-sided function. accordingly, the input clock must be below 20 mhz . note: the farb bit switch must be operated during software reset. rcntm1, rcntm0 (bits 1 and 0) these bits set the timeout time of the reconfiguration timer. the following timeout times are applicable when the transfer rate is 2.5 mbps. (the values become half at 5 mbps) rcntm1-0 00 : timeout = 840 ms 01 : timeout = 210 ms 10 : timeout = 105 ms 11 : timeout = 52 ms (default) the timeout times above are values for comr6: reconfiguration regist er?s et1 and et2 = 1,1 respectively. if et1 and et2 are other than the above va lue, the timeout time is doubled. (this includes the case of et1 pin=low.) refer to section 2.14.2 et1 pin and 3.2.7 et1, et2 bit for details.
dual mode circlink? controller datasheet smsc tmc2074 page 83 revision 0.1 (03-29-06) datasheet comr7-1010 (gpio data register) address:0eh [read/write] subad=1010 bit name init. value description 15-8 -------- 0 reserved (all "0") *1 7-0 gpd7-0 all ?0? gp-i/o data *1 not exist in the arcnet original specifications. - when reading/writing: gpio data register gpd[7:0] (bit 7-0) write : write data which outputs to gpip7-0 pin read : read the state of the gpio7-0 pin gpd7 corresponds to the gpio7 pi n. (refer to section 2.15.) comr7-1011 (gpio direction register) address:0eh [read/write] subad=1011 bit name init. value description 15-8 -------- 0 reserved (all "0") *1 7-0 ngpoe7-0 all ?1? gp-i/o output enable *1 not exist in the arcnet original specifications. - when reading/writing: gpio direction register ngpoe[7:0] (bit 7-0) set the direction of gpio7-0 pin. the direction can be set by every one bit. ngpoe7 corresponds to the gpio7 pin. (refer to section 2.15.) 0 : output mode 1 : input mode supplement: refer to the arcnet controller com20020 rev.d da ta sheet for further details on each bit of comr0 to comr7.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 84 smsc tmc2074 datasheet 3.2.8 nst register: network standard time nst address:10h (read only) bit name init. value description 15-0 nst15-0 0000h network standard time nst15-0 (bits 15 to 0) these bits indicate the standard time in t he network. refer to section 2.12 for details. accessing the nst register can dynamic ally provide the latest time data. since nst is a 16 bit counter, it is necessary to read the even address side (10h) fi rst when an 8-bit bus is used. when the even address side (11h) is read out, the remaining 8 bi ts of the nst are latched internally. 3.2.9 intsta register: ec interrupt status intsta address:12h (read only, read/write) bit name dir. init. value description 15 rxerr r/w 0 receiver error 14 cmiecc r/w 0 cmi rx error correction occurred 13 nstunloc r 1 or 0 nst unlock 12 warterr r 0 warning timer error 11 frcv r/w 0 free-format mode received 10 rrcv r/w 0 remote-buffer mode received 9 mrcv r/w 0 my received 8 sidf r/w 0 sid found 7 tknretf r/w 0 token retry occurred 6 acknakf r/w 0 corrupt ack/nak recovered 5 hubwdto r/w 0 hub watch dog timer time-out 4 cperr r/w 0 tx cp error 3 com r 0 arcnet core interrupt 2 fbenr r/w 0 fbe no reply 1 txerr r/w 0 transmitter error 0 ta r 1 transmitter available the upper 8 bits indicate the receive status, and the lower 8 bits indicate the send status. every bit in this register can be used to generate an interrupt. rxerr (bit 15) this bit indicates that receive has stopped due to an erro r during packet receive. as soon as this bit is set, the details of the error are indicat ed by the rxec 2-0 (bits 7 to 5) in the errinfo register, and the id of the sending node is stored to resid 4-0 (b its 4 to 0) in the same register. note that this bit is not set by any message other than a packet (token, fbe, ack, or nak). this bit is cleared by writing 1 or by a software reset.
dual mode circlink? controller datasheet smsc tmc2074 page 85 revision 0.1 (03-29-06) datasheet cmiecc (bit 14) this bit indicates that error correction of receiv ed data has been performed in the cmi decoding circuit. as soon as this bit is set, the details of the error are stored in cmiei3-0 (bit s 11 to 8) of the errinfo register. this bit is cleared by writing a 1 or by software reset. nstunloc (bit 13) indicates synchronizing with the cm node?s nst. this bit is set by software reset. for further details, please refer to section 2.12. 0: synchronous lock status 1: synchronous unlock status (initial value) in the cm node, this flag goes into steady state 0 (synchronous lock st atus). accordingly, the initial settings are as detailed below: in peripheral mode, the cm node id is set in a regist er after cancellation of hardware reset. after these values are imported, the out put is 1 until it assumes itself as a cm node (it becomes 0 after that). during software reset, due to the cm node id being immediat ely imported, the cm n ode id is fixed at 1 0 immediately after set-up in the register. in standalone mode, the cm node id is the pin setting when it is the sa me setting as the cm node setting. the output is 1 during hardware reset, and 0 when hardware reset is cancelled. warterr (bit 12) this bit is set if data is not received by any page set in remote buffer receive mode within a fixed period. this bit is cleared by the warterr clear command or by a software reset. 1: no receive within a fixed period, 0: receive within a fixed period frcv (bit 11) this bit is set if the reception by any page set in fr ee format receive mode is completed normally. this bit is cleared by writing a 1 or by a software reset. 1: receive complete, 0: receive in progress rrcv (bit 10) this bit is set if the reception of any page set in re mote buffer receive mode is completed normally. this bit is cleared by writing a 1 or by a software reset. 1: receive complete, 0: receive in progress mrcv (bit 9) this bit is set if the reception of a packet sent to this node (did = nid) is completed normally. this bit is cleared by writing a 1 or by a software reset. 1: receive complete, 0: receive in progress sidf (bit 8) this bit is set if a packet sent from the sid specified by the ssid register is received. this bit is cleared by writing a 1or by a software reset.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 86 smsc tmc2074 datasheet tknretf (bit 7) this bit indicates that a token retry is performed. re fer to section 2.4.1 - reducing token loss for details. this bit is cleared by writing a 1or by a software reset. acknakf (bit 6) this bit indicates that counter measures to handle corrupted ack/nak data have been implemented. refer to section 2.4.1 for details. this bit is cleared by writing a 1 or by a software reset. hubwdto (bit 5) this bit indicates that the hub unit has been reset whic h was caused by timeout of watchdog timer. this is done to prevent the direction contro l circuit of the hub unit from hangi ng-up. a timeout occurs if the transmit signal from hub is continuously active for 3. 27 ms or more. (when using 2.5 mbps. at 5 mbps, the value is half -> 1.64 ms) this timeout causes the hub unit and two cmi units to be automatically reset. (if the hub unit is off, the cmi units are not reset.) this bit is cleared by writing a 1or by a software reset. cperr (bit 4) this bit is set if the cp field of the preceding packet is of a val ue that exceeded the page boundary, or is between 00h and 02h, both of which are invalid cp settings. refer to section 2.5.3, packet data structure for details. this bit is cl eared by writing a 1 or by a software reset. 1: packet including invalid cp field is sent, 0: normal packet is sent com (bit 3) this bit is set to 1 if there is an interrupt from t he arcnet core. be sure to set the comr0 mask register bits when required. this bit is set to 1 when the interrupt is generat ed by excnak, recon, nxtiderr and ta bit in the mask register of comr0. fbenr (bit 2) both fbenr and txerr bits are set if there is no re sponse to fbe . if fbenr is set, it is possible to determine that data is transmitted to a node that is not receiving proper ly, thus identifying failures based on deformed packet data. this bit is cleared by writing a 1, issuing a send command, or by a software reset. txerr (bit 1) this bit is set if sending fails. be aware that this function is the opposite of t hat of the arcnet-original tma bit. this bit is cleared by writing a 1 , issuing the send command, or by a software reset. ta (bit 0) this bit is the same as the ta bi t of the comr0: arcnet status regist er. (refer to that register for details.) this bit becomes 0 only wh ile the send command is being issued. combination and meaning of transmission status ta txerr fbenr meaning
dual mode circlink? controller datasheet smsc tmc2074 page 87 revision 0.1 (03-29-06) datasheet 0 x x transmitting 1 0 0 transmit complete 1 1 0 transmit error by data error 1 1 1 transmit error by fbe unanswer 3.2.10 intmsk register: ec interrupt mask intmsk address:14h (read/write) bit name init. value description 15 rxerr 0 receiver error 14 cmiecc 0 cmi rx error correction occurred 13 nstunloc 0 nst unlock 12 warterr 0 warning timer error 11 frcv 0 free-format mode received 10 rrcv 0 remote-buffer mode received 9 mrcv 0 my received 8 sidf 0 sid found 7 tknretf 0 token retry occurred 6 acknakf 0 corrupt ack/nak recovered 5 hubwdto 0 hub watch dog timer time-out 4 cperr 0 tx cp error 3 com 0 arcnet core interrupt 2 fbenr 0 fbe no reply 1 txerr 0 transmitter error 0 ta 0 transmitter available this register corresponds to interr upt status, and being set to 1, the in terrupt signal becomes active when the corresponding status becomes 1.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 88 smsc tmc2074 datasheet 3.2.11 eccmd register: ec command register eccmd address:16h (read/write) bit name init. value description 15-8 -------- 0 reserved (all "0") 7-0 eccmd7-0 00h ec command eccmd 7-0 (bits 7 to 0) this command is unique to circlink. when the bus widt h is 8 bits (w16 = 0), access to higher bytes is invalid; the command accesses the lower bytes. when t he bus width is 16 bits (w16 = 1), ?00h? should be specified for the higher bytes. the readable value fr om this register is the prior write command. 03h: send command this command instructs the circlink to start sending. after issuing the send co mmand, sending is started upon receipt of token to the node. in continuous send mode (txm = 1, rto = 0) or in remote buffer sending mode, an automatic send operation repeats whenever a node rece ives the token after the first send command has been issued. in free format send mode (txm = 0) or the remo te buffer send mode, a send command must be issued each time in single send mode (txm = 1, rto =1). 01h: sending cancellation command this command cancels the prior send command . after canc ellation, the ta bit is set to 1. if this command is issued before the node receiv es the token , cancellation of the send is possible. it is necessary to confirm tta bit =1 because the canc ellation is actually execut ed when the token arrives. in continuous send mode (txm = 1, rto = 0) in t he remote buffer send mode, continuous send operation can be stopped. (to restart, a send command is necessary.) 09h: nxtiderr clear command this command clears the nxtiderr bit in comr1 (diagnostic register) . 0ah: warterr clear command this command instructs initializati on and start of the warning timer f unction. in addition, this command clears the warterr bit and the intsta register as well as the receive flag in t he page that is set to the remote buffer mode. 0eh: por, excnak clear command this command clears the por bit in comr0 (status register) and the excnak bit in comr1 (diagnostic register). these bits cannot be cleared individually. 16h: recon clear command this command clears the recon bit in comr0 (status register). 1eh: concurrent operati on of por, excnak clear and recon clear command
dual mode circlink? controller datasheet smsc tmc2074 page 89 revision 0.1 (03-29-06) datasheet these commands clear all por, excnak, and recon bits. 3.2.12 rsid register: receive sid rsid address:18h (read only) bit name init. value description 15-13 -------- -- reserved (all "0") 12-8 mrsid4-0 all "0" my received sid 7-5 -------- -- reserved (all "0") 4-0 rsid4-0 all "0" received sid mrsid 4-0 (bits 12 to 8) sid of the packet to the node received last. rsid 4-0 (bits 4 to 0) sid of packet received last. 3.2.13 ssid register: sid ssid address:1ah (read/write) bit name init. value description 15-5 -------- -- reserved (all "0") 4-0 ssid4-0 all "0" search sid ssid 4-0 (bits 4 to 0) when a packet having sid as defined in section 3.2.13, is rece ived, the sidf bit of the interrupt status register is set.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 90 smsc tmc2074 datasheet 3.2.14 rxfh register: receive flag (higher side) rxfh address:1ch (read/write) bit name init. value description 15 rxf31 1 receive flag (page #31) 14 rxf30 1 receive flag (page #30) 13 rxf29 1 receive flag (page #29) 12 rxf28 1 receive flag (page #28) 11 rxf27 1 receive flag (page #27) 10 rxf26 1 receive flag (page #26) 9 rxf25 1 receive flag (page #25) 8 rxf24 1 receive flag (page #24) 7 rxf23 1 receive flag (page #23) 6 rxf22 1 receive flag (page #22) 5 rxf21 1 receive flag (page #21) 4 rxf20 1 receive flag (page #20) 3 rxf19 1 receive flag (page #19) 2 rxf18 1 receive flag (page #18) 1 rxf17 1 receive flag (page #17) 0 rxf16 1 receive flag (page #16) rxf31-16 (bits 15 to 0) this is a flag that indicates the receive status of pages from 16 to 31. the definition is different depending on the receive mode of the corres ponding page. in the free format receiv e mode, the regi ster becomes a writable register. this register is effective only when page size is set to the 32-byte mode due to ram size; in other sizes, the readout is always ?1?. free format receive mode [flag definition] 1: receiv e completed/u nauthorized state 0: receive authorized [clear condition] writing ?1?, or last dat a readout of corresponding page only in naclr = 0 remote buffer receive mode [flag definition] 1: receive within a fixed time period 0: no receive within a fixed time period. [clear condition] writing 0ah (warterr clear co mmand) in the eccmd register, or ok in the warning monitoring result if the all-receive-inhibit bit, ecri, in the mode register is returned from 1 to 0, all the receive flags return to 1 regardless of their receive mode.
dual mode circlink? controller datasheet smsc tmc2074 page 91 revision 0.1 (03-29-06) datasheet 3.2.15 rxfl register: receive flag (lower side) rxfl address:1eh (read/write) bit name init. value description 15 rxf15 1 receive flag (page #15) 14 rxf14 1 receive flag (page #14) 13 rxf13 1 receive flag (page #13) 12 rxf12 1 receive flag (page #12) 11 rxf11 1 receive flag (page #11) 10 rxf10 1 receive flag (page #10) 9 rxf09 1 receive flag (page #09) 8 rxf08 1 receive flag (page #08) 7 rxf07 1 receive flag (page #07) 6 rxf06 1 receive flag (page #06) 5 rxf05 1 receive flag (page #05) 4 rxf04 1 receive flag (page #04) 3 rxf03 1 receive flag (page #03) 2 rxf02 1 receive flag (page #02) 1 rxf01 1 receive flag (page #01) 0 -------- 0 reserved ("0") rxf15-01 (bits 15 to 1) this is flag indicates the receive status of pages 01 to 15. the definition is different depending on the receive mode of the corresponding page. in the free format receive mode, the register bec omes a writable register. bits from 15 to 4 are not effective when t he page size is 128/256 and bits 15 to 4 are not effective when the page size is 256 bytes (the readout is always ?1?). free format receive mode [flag definition] 1: re ceive completed/unauthorized 0: receive authorized [clear condition] writing ?1?, or last dat a readout of corresponding page only in naclr = 0 remote buffer receive mode [flag definition] 1: receive within a fixed time period 0: no receive within a fixed time period. [clear condition] writing 0ah (warterr clear co mmand) in the eccmd register, or ok in the warning monitoring result if the all-receive-inhibit bit, ecri, in the mode register is returned from 1 to 0, all the receive flags return to 1 regardless of their receive mode.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 92 smsc tmc2074 datasheet supplement: clearing the receive flag by writing 1 in free format receive mode receive flags rxf31 to rxf1 become 1 after receive completion and must be cleared (0) after being read. the clearance is executed by writing ?1? in object bits to clear only the receive flag bits. for example, if the readout data of the rxfh register (higher receive flag) is 01h; in this case, the data means receive completion of page #16. if this readout data (01h) is writt en back to the rxfh register, only the rxf 16 bit is cleared. therefore, t he bit in the rxfh register that is set after the rxfh register readout is not cleared by mistake. the important point is that the bits subject to be clear ed are the bits of which the cpu recognizes as ?1.? this description is also applicable to cleari ng flags in the interrupt status register. 3.2.16 cmid register: clock master node id cmid address:20h (read/write) bit name init. value description 15-5 -------- -- reserved (all "0") 4-0 cmid4-0 all "0" clock master node id cmid 4-0 (bits 4 to 0) these bits specify ids of the clock master node and the standard node of t he network standard time (nst). if a packet is received from the node set, the nst is loaded. if 0 is set, loading is not executed.
dual mode circlink? controller datasheet smsc tmc2074 page 93 revision 0.1 (03-29-06) datasheet 3.2.17 mode register: operat ion mode setup register address:22h (read/write) bit name init. value description 15-13 -------- -- reserved (all "0") -> must write 000 12 cmierrmd 0 cmi rx error mode 11 nstsend 0 network standard time send 10 nststop 0 network standard timer stop 9 inimode 0 initialize mode 8 txen 0 or 1 tx enable 7 ecri 0 circlink receive inhibit 6 bre 0 broadcast receive enable 5 txm 0 transmitter mode 4 rto 0 remote buffer tx once mode 3 wdmd 0 packet data word mode 2 ntknrty 0 token retry 1 nacknak 0 acknack mode 0 naclr 0 receive flag auto clear cmierrmd (bit12) this bit sets the operation mode in the event of error correction dur ing data packet receive in the cmi decoding circuit. when error correction (cmiecc = 1) is performed during a receiv e, if the receive is terminated this bit is set to 1. the receive terminat ion process should follow 2.9.1 ?temporary receive and direct receive.? 1: terminates packet receive , 0: does not terminate packet receive nstsend (bit11) this bit has a function that allows the nodes to alter nate clock master to add the nst value to the last two bytes of packet similar to the function in clock master node. when this bit is set to 1, nst is sent instead of the last two bytes that are written in packet ram. 1: adds nst , 0: dose not add nst nststop (bit10) this bit stops nst at the current count value. 1: stops nst count , 0: dose not stop nst count inimode (bit 9) this bit selects whether the circl ink initialization, which includes the maxid number setup, page size setup, the node number setup, and communication rate prescaler setup, are set via an external input pin or by register specification. since this bit is important in network se ttings, this bit must be rewritten in the condition of txen = 0 (offline). when this bit is rewr itten, software reset is aut omatically executed. (the software reset is released automatically.) 1: sets via register, 0: sets via external input pin
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 94 smsc tmc2074 datasheet txen (bit 8) setting this bit to 1 in circlink enables network par ticipation. the initial value differs depending on the operation mode; the starti ng status is 0 = offline and 1 = onli ne in the peripheral mode and the standalone mode, respectively. this bit is the same as the txen bi t in the comr6 register. if this bit is rewritten from 0 to 1, software reset is automat ically executed. (the software rese t is released automatically.) the software reset is not applied when the bit is changed from 1 to 0. 1: online state, 0: offline state ecri (bit 7) this bit stops automatic issuing of receive commands to the arcnet core. the circlink always receives; to stop receiving, set this bit to 1. moreover, this bit returns nak to the free buffer enquiry (fbe) to the bit. returning this bit from 1 to 0 sets the receive flag r egisters rxf01 to rxf31 to the (initial) value of 1. when circlink receives a token issued by itself, ecri is set. this causes a delay because setting/clearing ecri affects reception flags rxf0-rxf3. the delay is 52 ms; when the network data rate is 2.5 mbps, and scales accordingly for other rates. 1: normal stop, 0: normal operation note: the delay will be caused by the time the result of changing ecri reflected inter nally. ecri is reflected when the token to oneself is received, and do the followi ng processing, please after inserting the weight of maximum value (52ms @2.5mbps) at the time of token surroundings cycle when you change ecri. 52ms or less is delayed to the initializ ation operation of reception flag r egister rxf01-rxf31 when ecri is returned to 1 0. 52ms is a value for 2.5mbps. this time depends on transfer rate. if it is 5mbps, this time is half (26ms). if it?s 1.25mbps, it is two time (104ms). bre (bit 6) 1: receives broadcast packet, 0: not receive txm (bit 5) 1: remote buffer sending mode, 0: free format sending mode rto (bit 4) this bit specifies the sending count in the remote buffer sending mode 1: only one packet sending, 0: continuous auto-sending wdmd (bit 3) this bit specifies the data structur e mode to access data register (comr4) through 8-bit bus. when this bit is set to 1, to protect the higher and lower bytes of word data as one packet, it is necessary to perform an access to comr4 in the order of 08h to 09h. (protect ion is unavailable in the order of 09h to 08h, 08h to 08h, and 09h to 09h) the rule is app licable for both write and read. 1: 16-bit data batch, 0: 8-bit data batch
dual mode circlink? controller datasheet smsc tmc2074 page 95 revision 0.1 (03-29-06) datasheet ntknrty (bit 2) setting this bit to 1 disables token re-send. (original operation of arcnet) nacknak (bit 1) setting this bit to 1 generates reconfiguration in ack/nak deformation. (original operation of arcnet) naclr (bit 0) setting this bit to 1 disables automatic clearance of re ceive flag in the readout of the last data in the free format receive mode. 3.2.18 carry register: carry sel ection for external output carry address:24h (read/write) bit name init. value description 15 ofsmod 0 offset mode 14,13 -------- -- reserved (all "0") 12-8 nstofs4-0 all "0" nst offset 7-4 nstc3-0 8h nst carry select 3-0 wartc3-0 8h wart carry select ofsmod (carry register: bit 15) 0: automatic offset (default) 1: manual offset note: do not set ofsmod bit = 1, when nstpre2 pin = low nstofs4-0 (carry register: bits 12 to 8) these bit selects an offset from 0 to 31. t he offset is ?nst resolution * nstofs4-0?. nstc3-0 (bits 7 to 4) these bits specify the generation ti ming of external pulse output, nn stcout, by means of the digit position of nst. nstc3-0 carry digit check output cycle 0000 nst[0] nst resolution * 2^1 0001 nst[1] nst resolution * 2^2 0010 nst[2] nst resolution * 2^3 : : : 1111 nst[15] nst resolution* 2^16 refer to section 2.12 for the nst resolution.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 96 smsc tmc2074 datasheet wartc3-0 (bits 3 to 0) these bits specify the warning monitoring time at remo te buffer receive by means of the digit position of timer (wt). refer to secti on 2.9.4 for details of wt. wartc3-0 carry digit check period 0000 ------ illegal setting 0001 wt[1] wt resolution * 2^1 0010 wt[2] wt resolution * 2^2 : : : 1111 wt[15] wt resolution * 2^15 3.2.19 rxmh register: receive mode (higher side) rxmh address:26h (read/write) bit name init. value description 15 rxm31 0 receive mode (page #31) 14 rxm30 0 receive mode (page #30) 13 rxm29 0 receive mode (page #29) 12 rxm28 0 receive mode (page #28) 11 rxm27 0 receive mode (page #27) 10 rxm26 0 receive mode (page #26) 9 rxm25 0 receive mode (page #25) 8 rxm24 0 receive mode (page #24) 7 rxm23 0 receive mode (page #23) 6 rxm22 0 receive mode (page #22) 5 rxm21 0 receive mode (page #21) 4 rxm20 0 receive mode (page #20) 3 rxm19 0 receive mode (page #19) 2 rxm18 0 receive mode (page #18) 1 rxm17 0 receive mode (page #17) 0 rxm16 0 receive mode (page #16) rxm31-16 (bits 15 to 0) these bits specify the receive mode of page 16 to 31. the spec ification is effectiv e only in the 32-byte mode of page size. if the page size is set to 64, 128, or 256 bytes, the mode is tied to the free format receive mode (0). 1: remote buffer receive mode 0: free format receive mode note: if the number of nodes in the netwo rk is small, the receive mode of unused nodes (pages) should be set to the free format receive mode (0). if the mode is set to the remote buffer mode (1) by mistake, the unused pages undergo warning timer response moni toring (except for the self node).
dual mode circlink? controller datasheet smsc tmc2074 page 97 revision 0.1 (03-29-06) datasheet 3.2.20 rxml register: receive mode (lower side) rxml address:28h (read/write) bit name init. value description 15 rxm15 0 receive mode (page #15) 14 rxm14 0 receive mode (page #14) 13 rxm13 0 receive mode (page #13) 12 rxm12 0 receive mode (page #12) 11 rxm11 0 receive mode (page #11) 10 rxm10 0 receive mode (page #10) 9 rxm09 0 receive mode (page #09) 8 rxm08 0 receive mode (page #08) 7 rxm07 0 receive mode (page #07) 6 rxm06 0 receive mode (page #06) 5 rxm05 0 receive mode (page #05) 4 rxm04 0 receive mode (page #04) 3 rxm03 0 receive mode (page #03) 2 rxm02 0 receive mode (page #02) 1 rxm01 0 receive mode (page #01) 0 -------- -- reserved (?0?) rxm15-08 (bits 15 to 8) these bits specify the receive mode of pages 08 to 15. the s pecification is effectiv e only in the 32- or 64- byte mode of page size. if the page size is set to 128, or 256 bytes, the mode is tied to the free format receive mode (0). 1: remote buffer receive mode 0: free format receive mode rxm07-04 (bits 7 to 4) these bits specify the receive mode of pages 04 to 07. the specification is effective only in the 32-, 64-, or 128-byte mode of page size. if the page size is set to 256- bytes, the mode is tied to the free format receive mode (0). 1: remote buffer receive mode 0: free format receive mode rxm03-01 (bit 3-1) these bits specify the receive mode of pages 01 to 03. the specification is effective in any page sizes. 1: remote buffer receive mode 0: free format receive mode note: if the number of nodes in the netwo rk is small, the receive mode of unused nodes (pages) should be set to the free format receive mode (0). if the mode is set to the remote buffer receive mode (1) by mistake, the unused pages undergo warning timer response m onitoring (except for the self node).
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 98 smsc tmc2074 datasheet 3.2.21 maxid register: se lection of max. id maxid address:2ah (read/write) bit name init. value description 15-5 -------- -- reserved (all "0") 4-0 maxid4-0 all "1" maxid maxid 4-0 (bits 4 to 0) these bits specify the max. node id. when inimode in the mode register and ndiag pin are set to 1, the value set in this register is selected as the max. node id. when inimode is set to 0, val ues in maxid 4-0 of the external input pin become readable. refer to section 1.6.9. note: to change these bits, be sure to set txen to 0 (off-line) before hand. if thes e bits change during the on- line state, it executes a softwar e reset automatically (the software reset is released automatically). 3.2.22 nid register: sel ection of the node id nid address:2ch (read/write) bit name init. value description 15-5 -------- -- reserved (all "0") 4-0 nid4-0 all "0" my node id nid4-0 (bits 4 to 0) these bits specify the node id. when inimode of the mode register is set to 1, the value set in this register is selected as the node id. when inimode is set to 0, values in nid 4-0 of t he external input pin become readable. refer to section 1.6.10. note: to change these bits, be sure to set txen to 0 (off-line) before hand. if thes e bits change during the on- line state, it executes a software reset automatically. (the software re set is released automatically.)
dual mode circlink? controller datasheet smsc tmc2074 page 99 revision 0.1 (03-29-06) datasheet 3.2.23 ps register: page size selection ps address:2eh (read/write) bit name init. value description 15-2 -------- -- reserved (all "0") 1-0 ps1-0 0,0 page size ps1-0 (bits 1 to 0) these bits specify the page size. when inimode of the mode register is set to 1, the value set in this r egister is selected as the page size. when inimode is set to 0, values in ps1-0 of the external input pin become readable. refer to section 1.6.8. note: to change these bits, be sure to set txen to 0 (off-line) beforehand. if thes e bits change during the on- line state, a software reset will be ex ecuted automatically (the software re set is released automatically). 3.2.24 ckp register: comm unication rate selection ckp address:30h (read/write) bit name init. value description 15-5 -------- -- reserved (all "0") 2-0 ckp2-0 0,0,0 clock prescaler bits 2,1,0 ckp (bits 2 to 0) these bits specify the communication ra te of the circlink. when inimode of the mode register is set to 1, the value set in this register is selected as the communication rate. when inimode is set to 0, values in ckp2-0 of the external input pin becom e readable. refer to section 1.6.15. note: to change these bits, be sure to set txen to 0 (off-line) beforehand. if thes e bits change during the on- line state a software reset will be ex ecuted automatically (the software re set is released automatically).
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 100 smsc tmc2074 datasheet 3.2.25 nstdif register: nst phase difference nstdif address:32h (read only) bit name init. value description 15 difdir 1 differential direction 14-0 nstdif14-0 all?0? nst differential difdir (nstdif register: bit 15) this bit indicates a direction of nst phase difference. this bit is not applicable for the clock master node. 0: ahead of cm node 1: behind cm node nstdif14-0 (nstdif register: bit 14-0) these bits are used to express the absolute val ue of the phase difference between a cm node and nst in 0 to 32, 768. these bits are not applic able if the node is a clock master node. supplement: if the node is a clock master node, t he nstdif register is tied to 0000h. accessing the nst register can dynamica lly provide the latest time data. si nce nst is a 16 bit value, it is necessary to read the even address side (32h) first when 8-bit bus is used. when the even address side (13h) is read out, the remaining 8 bits of the nst are latched internally.
dual mode circlink? controller datasheet smsc tmc2074 page 101 revision 0.1 (03-29-06) datasheet 3.2.26 pininfo register : pin setup information pininfo address:34h (read only) bit name init. value description *1 15 nswap -- status of nswap pin *1 14 w16 -- status of w16 pin 13 nopmd -- status of nopmd pin 12 nhubon -- status of nhubon pin 11 nehwr -- status of nehwr pin 10 nehrd -- status of nehrd pin 9 ncmibyp -- status of ncmibyp pin 8 chktstp -- status of chktstp (test pins) *1 7 nswap -- status of nswap pin *1 6 w16 -- status of w16 pin 5 ndiag -- status of ndiag pin 4 txenpol -- status of txenpol pin 3 nstpre1 -- status of nstpre1 pin 2 nstpre0 -- status of nstpre0 pin 1 wpre1 -- status of wpre1 pin 0 wpre0 -- status of wpre0 pin current status of several circlin k setup pins except for nmux, nrwm, nstalone, ndsinv, alepol, nstpre2, and wpre2 can be read. it is useful to find pin setup errors by readi ng the current status. chktstp (bit 8) becomes 1 when one of the test pins (ntest[3:0 ], ntmode) becomes low, thereby notifying the circlink being in some test mode. *1: the nswap and w16 pins used to set the cp u bus can read out bit 7 and 6 in either accesses of 16 bit, 8 bit without swap or 8 bit with swap.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 102 smsc tmc2074 datasheet 3.2.27 errinfo register: error information errinfo address:3ah (read only) bit name init. value description 15 -------- 0 reserved ("0") 14-12 rcncd2-0 0 reconfiguration error code 11-8 cmiei3-0 0 cmi rx e rror correction information code 7-5 rxec2-0 0 rx error code 4-0 resid 0 rx error sid rcncd2-0 (bits 14 to 12) these bits represent the re configuration-generati on-cause code, which is the c ause of the recon bit (bit 2) of comr0, in three bits. issuing clear flag s command to comr1 or software reset clears these bits. rcncd2-0 000 : received garbage data (noise) during the wait per iod after token sending (other than 000 to 101) 001 : received a signal other than ack duri ng the wait period after packet sending 010 : generated trailing 0 error after ack receiv e during the wait period after packet sending 011 : received a signal other than nak/ack dur ing the wait period after f.b.e sending 100 : generated trailing 0 error after ack receiv e during the wait period after f.b.e sending 101 : generated trailing 0 error after nak receiv e during the wait period after f.b.e sending 11x : undefined 001 to 101 do not generate reconfigur ation since they are saved by nak/ack counter-deformation function (nacknak = 0: default). the reconfigurat ion generation cause at na cknak = 0 is only 000. cmiei3-0 (bits 11 to 8) these bits represent the cmi receive error correction code, which is the cause of cmiecc bit (bit 14) = 1 in the intsta register in bits cmie2-0-0. in cmiei3, it indicates which port is the generation port. however, if hub is turned off, the status is re tained to 0. (0: port 1 side, 1: port 2 side) writing 1 to the cmiecc bit or software reset clears these bits. cmiei3 0: port 1 1: port 2
dual mode circlink? controller datasheet smsc tmc2074 page 103 revision 0.1 (03-29-06) datasheet cmiei2-0 000 : corrected error data 10 to 00 in state#11 (s11) 001 : corrected error data 11 to 01 in state#11 (s11) 010 : corrected error data 10 to 11 in state#00 (s00) 011 : corrected error data 00 to 01 in state#00 (s00) 100 : corrected error data 10 to 00 in state#01a (s01a) 101 : corrected error data 11 to 01 in state#01a (s01a) 110 : corrected error data 10 to 10 in state#01b (s01b) 111 : corrected error data 00 to 01 in state#01b (s01b) for state numbers, refer to t he state transition of the state machine in a-5 cmirx block in appendix a cmi modem. rxec2-0 (bits 7 to 5) these bits represent the packet receive error code, wh ich is the cause of rxerr bit (bit 15) = 1 in the intsta register in three bits. writing 1 to the rxe rr bit or software reset clears the setting. (default is 000.) rxec2-0 000 : frame error or broadcast receiving when broadcast receiving prohibition is set. (bre=0) 001 : cp error (other than cp=0: 0 is long packet and it is not sent) 010 : crc error 011 : length error (trailing 0 error) 100 : mismatch of two did (other than in broadcast and addressed to the other node) 101 : receive stop caused by cmiecc generation 110 : receive in receive-unauthorized page (only in free format mode) 111 : two or more simultaneously occur among 011, 101, and 110 resid4-0 (bits 4 to 0) these bits represent the sid value in receive packet, which causes rxerr bit (bit 15) = 1 in the intsta register, in five bits. writing 1 to rxe rr bit or software reset clears these bits.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 104 smsc tmc2074 datasheet appendix a cmi modem a-1 outline isolation by pulse transformers is widely used in this network. however, because in standard arcnet transmission the presence or abs ence of a pulse is indicated by 0 or 1, in data consisti ng of a sequence of zeros such as 0x00 a prolonged succession of no pulses re sults in magnetic satura tion of the transformer. as a countermeasure, an external circuit on t he standard arcnet is desi gned to prevent magnetic saturation (e.g. hyc4000). because su ch an external component is not av ailable in the circlink external circuit, where only a normal rs485 transceiver and pulse transformer are installed, a cmi modem circuit is built in and converts the arcnet into cmi coding. a-2 cmi code in the cmi code the same value c annot continue for more than 2 bits. the state it can take is decided, so it has a self-restoring function. in cmi coding, input data is transiti oned in 1-bit portions. bits are indica ted either as 11, 00, or 01. cmi coding is carried out by making these into cmi codi ng symbols. at decoding, t he process is the exact opposite. the cmi coding state transiti on diagram is shown below. 00 01 01 11 0 0 0 0 1 1 1 1 cmi code data example: figure 17 - cmi coding state transition diagram
dual mode circlink? controller datasheet smsc tmc2074 page 105 revision 0.1 (03-29-06) datasheet a-3 cmi modem configuration enable ntxin ntxenin clk nreset ntxout ntxenout enable nrxin clk nreset nrxout cmitx cmirx ntxin ntxenin enable nrxin clk nreset ntxout ntxenout nrxout figure 18 - cmi modem block diagram ntxin input, negative-logic, arcnet controller pulse1output ntxenin input, negative-logic, arcnet controller txen output nrxin input, negative-logic, li ne receiver reception output clk input, start up detection, same clock as arcnet controller nreset input, negative-logic, reset signal enable input, positive-logic, clo ck division signal in synchronizer ntxout output, negative-logic*, input to line driver data pin ntxenout output, negative-logic, input to line driver txenable pin nrxout output, negative-logic, input to the arcnet controller rxin pin *: cmi code in appendix a is stated as positive logic (active high).
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 106 smsc tmc2074 datasheet a-4 cmitx block state machine state_reset: reset status state_txewait: wait for txenable state_txstart: wait for start of data output state_s11: data ?1? output state_s00: data ?1? output state_s01a: data ?0? output state_s01b: data ?0? output state_s12: 10 bit output with ?0 ? ending after txenable termination txstart s00 s12 s01b txewait s01a s11 reset reset data ?1? output 11 ntxenin = 0 ntxenin = 1 ntxind = 000 function outline ? after reset, stand by with txewait, enter txstar t by ntxenin = 0 and star t output of ntxenout = 0. then, enter s11 by ntxi nd = 000 and start output of data fr om cmi code symbol 11. (the arcnet message header is ntxind = 00001111). ? when ntxenin = 1 is detected, s upplementary output of 10 bit ?0? data (symbol 01) is carried out, and then terminated.
dual mode circlink? controller datasheet smsc tmc2074 page 107 revision 0.1 (03-29-06) datasheet a-5 cmirx block state machine state_reset: reset status state_wait10: dete ct line status 1 ? 0 state_wait01: dete ct line status 0 ? 1 state_rxstart: detect symbol 01100110, start data reception state_s11: received data ?1? symbol 11 state_s00: received data ?1? symbol 00 state_s01a: received data ?0? symbol 01 state_s01b: received data ?0? symbol 01 rxstart s00 s01b wait10 s01a s11 reset wait10 wait01 function outline ? after waiting for symbol transition 11 ? 00 in wait10, wait for symbol transition 00 ? 11 in wait 01. then finish without receiving instable action from the network after dataf low termination. then in rxstart, start reception after detecting an alert pattern from the message header. ? after receiving ?0? data in s01 in 10 consecutive bi ts, then terminate reception and return to wait 10.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 108 smsc tmc2074 datasheet a-6 details regarding reception reception data analysis reception data is sampled one bit at a time by an 8 clk analysis function, and is entered into the shiftd 32-bit shift register. normally, this is a data bit 1 proce ss in shift register bit 8. because jitter is contained in the actual reception data, synchronization is achieved. starting reception reception data is set in accordance with the arcnet controller: various messages start with a bit ?1? sequence (alert), and no data exists on the line prior to the first bit ?1?. because t he output of the reception comparator in non-dataflow (non-driving period) within a message is unst able, those changes are warded off in wait 10 and wait 01. afterwards, rec eption is started when the alert starting pattern is detected. because the first bit ?1? in alert reception is set, the start symbol is 01100110 and 1 ? 0 is the rxstart point. 0101010101010101010111111111111111111111 1 1 1 0 0 0 000 000 0 0 0 1 1 1 10011001100110001 1101 alert pattern rxstart period of non-driving ending ?0? wait10 wait01 figure 19 - example of unstable comparator output recovery if the symbol is 11 or 00, data is ?1 ?, and if the symbol is 01, data is ?0?. this output is sequencer output, and reflects the sequencer state. da ta length is set to a standard of 8 clk, but this can be expanded or contracted by 2 clk for synchronization purposes. error correction if symbols not occurring in the cmi transition diagr am are received, they will be read as the nearest matching symbol. for example, if sym bol 10 not present in the cmi is rece ived, it is read as either symbol 11 or symbol 00, which will trigger an error. if sym bol 11 were received immedi ately before, it will be corrected to 00, because 11 cannot be repeated in the sequence. conversely , if 00 is received immediately before, it is corrected to 11. howe ver, if a repeated sequence of 11 is received immediately after receiving symbol 11, or if a repeated sequence of 00 is received immediately after symbol 00, it is corrected to 01. ending in acrnet, a ?0? ending is attached in final bit 9 of message transmissions. the arcnet ?0? is non- dataflow 0 and has no function. however, in the cmi, this ?0? is active data, flowed as ?0? in symbol 01. due to this, the ?0? ending expected by the arcnet controller is transmitted as cmi code. however, because the cmi code bit ?0? is displayed in symbol 01, what follows the final bit ?0? retains the same state and the symbol becomes ?0111111....?. it is then read at the receiving end as bit ?010*0*...? (0* is the result of misreading 11 as a 01). this is to say that the noise immediately a fter the bit 9 ending ?0? becomes bit 1 reception. since the arcnet contro ller is immediately after recepti on termination, this noise has no effect. there are two countermeasures available:
dual mode circlink? controller datasheet smsc tmc2074 page 109 revision 0.1 (03-29-06) datasheet measure 1 the transmitting end transmits ?0? as a bit 10 ending. if the receiving end receives a 10-bit ?0? sequence, it ends reception and enters an alert pattern. measure 2 a restriction is set to read symbol 01111111 not as bit ?0100? but as ?0000?. this works by automatically transitioning to s11 subsequent symbols that are 0 when symbol 11 is detec ted in s01b state. however, if they remain as 1, they stay in the s01b and are read as bit ?0?. on the other hand, as a countermeasure against silent nodes like the arcnet not actively data flowing sym bol ?01? during ?0? ending, when reception data is fixed at eit her 0 or 1, they are not read as bit ?1? but as bit ?0?. due to this, measures are taken even if there is a node with temporary non-dataflow ?0? ending output. due to the highest consecutive value after a single symbol in the cm i being 3 symbols, fixed symbol 0 or 1 sequence is separated from normal cmi code and can be read as non-dataflow bit ?0?.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 110 smsc tmc2074 datasheet appendix b crystal oscillator circuit symbol value rfb 51k ohm rout 51 ohm cin 22pf cout 22pf r and c values as an example f = 10m to 40mhz (in case of fundamental oscillation) internal clock mckin internal of lsi x1 x2 v dd r fb r out c out c in note: above r, c values may not be correct for a crysta l you select. you may have to determine the correct values. if you use an overtone type crystal, follo w the manufacturer?s recommendations for connection details.
dual mode circlink? controller datasheet smsc tmc2074 page 111 revision 0.1 (03-29-06) datasheet appendix c diagram of package external measurement www m d1 d n e e1 1 ze zd e w a a2 a1 ccc t h l l1 r2 r1 0. 25m m figure 20 - tmc2074 128 pin package outline table 8 - tmc2074 128 pin package parameters symbol items min typ max a overall package height - - 1.2 a1 standoff 0.05 - 0.15 a2 body thickness 0.95 - 1.05 d x span 15.8 - 16.2 d1 x body size 13.8 - 14.2 e y span 15.8 - 16.2 e1 y body size 13.8 - 14.2 h lead frame thickness 0.09 - 0.2 l lead foot length 0.45 0.6 0.75 l1 lead length - 1.0 - e lead pitch 0.4 basic t lead foot angle 0 o - 7 o w lead width 0.13 0.18 0.23 www lead position tolerance -0.035 - 0.035 r1 lead shoulder radius 0.08 - - r2 lead foot radius 0.08 - 0.2 ccc coplanarity - - 0.08 n pin count 128 notes: 1) controlling unit: millimeter. 2) package body dimensions d1 and e1 do not include the mold protrusion. maximum mold protrusion is 0.25 mm.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 112 smsc tmc2074 datasheet appendix d marking specifications 1 tmc2074- xx we e k l y _c ode - l ot _c ode 1 lot_code2 e2
dual mode circlink? controller datasheet smsc tmc2074 page 113 revision 0.1 (03-29-06) datasheet appendix e electrical characteristics maximum rated values(vss=0v) item symbol values unit power supply voltage vdd -0.3 to +5.0 v input voltage (x1 pin) -0.3 to vdd+0.3 v input voltage (except x1 pin) -0.3 to +7.0 v output voltage vout -0.3 to vdd+0.3 v input current iin 10 ma storage temperature tstg -55 to +125 o c conditions of standard function (vss=0v) item symbol value unit power supply voltage vdd 3.0 to 3.6 v operating temperature ta 0 to +70 o c input voltage (except x1 pin) *1 vin -0.3 to +5.5 v input rising/falling time *2 dt/dv 0 to 5 ns/v input clock frequency f x1 10 to 40 mhz input clock frequency tolerance df x1 100 ppm *1 : apply to 3-state output pins when hi-impedance(hi-z) state. *2 : apply to ncs,nwr,nrd,ale,npistr,rxin,rxin2,mckin pins. vin
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 114 smsc tmc2074 datasheet dc characteristics symbol item condition min typ max unit high level input voltage 2.0 vih * v low level input voltage 0.8 vil * v iih high level input current vin = vdd -10 10 a low level input current -10 10 iil pull-up attached vin = vss -200 10 a output off leak current vout = vdd -10 10 ioz pull-up attached or vss -200 10 a vh schmitt trigger hysteresis voltage 0.5 v ioh = -4ma 2.4 4 ma buffer ioh = -1ma vdd-0.5 voh * high level output voltage v 4 ma buffer iol = 4ma 0.4 vol * low level output voltage v fx1 = 20mhz 25ma idd operating current (all outputs open) fx1 = 40mhz 40ma ma * except x1 and x2 pins
dual mode circlink? controller datasheet smsc tmc2074 page 115 revision 0.1 (03-29-06) datasheet ac characteristics 2 . 0v 0 . 8v 2 . 0v 0 . 8v input signal output signal 1 . 4v figure 21 - timing measurement points note: detailed ac-timing specifications are provided in another document.
dual mode circlink? controller datasheet revision 0.1 (03-29-06) page 116 smsc tmc2074 datasheet appendix f appendix f: circlink controller product comparative table tmc2072 tmc2074 tmc2084 3.3v +/-0.3v 3.3v +/-0.3v 3.3v +/-0.3v 5v tolerant i/o 5v tolerant i/o 5v tolerant i/o temperature range 0 to +70c 0 to +70c 0 to +70c tqfp-100pin vtqfp-128pin tqfp-48pin 14x14x1.4mm body 14x14x1.0mm body 7x7x1.4mm body 0.5mm pitch 0.4mm pitch 0.5mm pitch max. data rate 5mbps 5mbps 5mbps hub function external 2 ports external 2 ports none transmission code cmi / rz code cmi / rz code cmi / rz code txen polarity setting pin setting pin setting active-high only nodeid, maxid, pagesize setting pin / bit setting pin / bit setti ng shared pins data rate prescaler setting pin / bit setting pin / bit setting no ne page-size 32/64/128/256 bytes 32/64/128/256 bytes 64/128 bytes max. node count 31/15/ 7/ 3 nodes 31/15/ 7/ 3 n odes 15/ 7 nodes operation mode peripheral mode only peripheral/standalone mode sta ndalone mode only internal ram size 1k bytes 1k bytes - data bus width 8/16bit 8/16bit - cpu type: nrd&nwr/dir&nds cpu type: nrd&nwr/dir&nds - bus type: mux/non-mux bus type: mux/non-mux - new flag for warrning timer none none - general poupose-i/o 8bit 8bit - in : 16 in : 0/ 8/16 out : 16 out : 32/24/16 verious setting by - pins shared pins and a packet tx trigger - 7 kinds 10 kinds receive broadcast - no yes send status - no yes anti-chatter sampling freq. - 2.44khz 1.22khz/19.1hz items * common circlink - * peripheral mode (with cpu mode) * standalone mode (cpu less mode) power supply voltage package support cpu number of i/o port

▲Up To Search▲

Price & Availability of TMC2074-NE

	To Download TMC2074-NE Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .