(preliminary) pl611s-26 1.8v-3.3v picopll tm programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 12/12/06 page 1 features ? advanced one time programmable (otp) pll design ? programmable pll or direct oscillation operation ? very low jitter and phase noise (30-70ps pk-pk typical) ? output frequency up to o 133mhz @ 1.8v operation o 166mhz @ 2.5v operation o 200mhz @ 3.3v operation ? reference input frequency: 1mhz to 200mhz ? accepts >0.1v reference signal input voltage ? low current consumption, <10>a when pdb is activated ? one programmable i/o pin can be configured as output enable (oe),power down (pdb) input or an additional clock output (clk1). ? frequency switching (fsel) capability ? single 1.8v, 2.5v, or 3.3v 10% power supply ? operating temperature range from -40 c to 85 c ? available in 6-pin sot23 and dfn green /rohs compliant packaging description the pl611s-26 is a general purpose frequency synthesizer and a member of phaselinks picopll tm product family. designed to fit in a small 6-pin d fn or 6-pin sot package for high performance applications, the pl611s-26 offers very low phase noise, jitter, and power consumption, while offerin g up to 2 clock outputs.. the frequency switching (fsel) capability of pl611s-26 allows for programming two sets of frequencies, while the power down feature of pl611s-26, when activated, allows the ic to consume less than 10>a of power. pl611s-26s programming flexibility allows generating any output using reference input signal. block diagram phase detector charge pump loop filter vco fin r-counter (8-bit) f vco = f ref * (2 * m/r) f out = f vco / (2 * p) clk0 f ref programming logic oe, pdb, clk1 m-counter (11-bit) p-counter (5-bit) programmable function fsel
(preliminary) pl611s-26 1.8v-3.3v picopll tm programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 12/12/06 page 2 key programming parameters clk output frequency output drive strength programmable input/output f out = f ref * m / (r * p) where m = 11 bit r = 8 bit p = 5 bit clk0 = f out , f ref or f ref / (2*p) clk1 = f ref , f ref /2, clk0 or clk0/2 three optional drive strengths to choose from: ? low: 4ma ? std: 8ma (default) ? high: 16ma one output pin can be configured as: ? oe - input ? pdb - input ? clk1 C output package pin configuration and description pin description pin assignment name dfn pin# sot pin # type description oe, pdb, clk1 2 1 i/o this programmable i/o pin can be configured as an o utput enable (oe) input, power down input (pdb) or clk1 clock output. this pin has an internal 60kl pull up resistor (oe and pdb function s only). pin state oe pdb 0 disable clk power down mode 1 (default) normal mode normal mode gnd 3 2 p gnd connection fin 1 3 i reference input pin fsel 6 4 i frequency switching input pin. this pin has an int ernal 60kl pull up resistor. fsel state 0 frequency 2 1 (default) frequency 1 vdd 5 5 p vdd connection clk0 4 6 o programmable clock output 1 2 3 4 5 6 oe, pdb, clk1 gnd fin vdd fsel clk0 sot sot sot sot23 2323 23- -- -6 66 6l l l l ( (( (3 33 3. .. .0 00 0mmx mmx mmx mmx3 33 3. .. .0 00 0mmx mmx mmx mmx1 11 1. .. .35 3535 35mm mmmm mm) )) ) p p p p l l l l 6 6 6 6 1 1 1 1 1 1 1 1 s s s s - - - - 2 2 2 2 6 6 6 6 dfn dfn dfn dfn- -- -6 66 6l l l l ( (( (2 22 2. .. .0 00 0mmx mmx mmx mmx1 11 1. .. .3 33 3mmx mmx mmx mmx0 00 0. .. .6 66 6mm mmmm mm) )) ) fin gnd fsel vdd clk0 12 3 oe,pdb,clk1 65 4
(preliminary) pl611s-26 1.8v-3.3v picopll tm programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 12/12/06 page 3 functional description pl611s-26 is a highly featured, very flexible, adva nced programmable pll design for high performance, low- power, small form-factor applications. the pl611s- 26 accepts a reference clock input of 1mhz to 200mh z and is capable of producing two outputs up to 200mhz. thi s flexible design allows the pl611s-26 to deliver a ny pll generated frequency, f ref (ref clk) frequency or f ref /(2*p) to clk0 and/or clk1. some of the design fe atures of the pl611s-26 are mentioned below: pll programming the pll in the pl611s-26 is fully programmable. the pll is equipped with an 8-bit input frequency divider (r-counter), and an 11-bit vco frequency feedback loop divider (m-counter). the output of the pll is transferred to a 5-bit post vco divider (p- counter). the output frequency is determined by the following formula [f out = f ref * m / (r * p) ]. clock output (clk0) clk0 is the main clock output. the pl611s-26 can also be programmed to provide a second clock output, clk1, on the programmable i/o pin (see oe/pdb/clk1 pin description below). the output of clk0 can be configured as the pll output (f vco /(2*p)), f ref (ref clk frequency) output, or f ref /(2*p) output. the output drive level can be programmed to low drive (4ma), standard drive (8ma) or high drive (16ma). the maximum output frequency is determined by the power supply voltage as shown below: clock output (clk1) the clk1 feature allows the pl611s-26 to have an additional clock output. this output can be programmed to one of the following: f ref - reference (ref clk ) frequency f ref / 2 clk0 clk0 / 2 frequency select (fsel) the frequency select (fsel) feature allows the pl611s-26 to switch between two pre-programmed outputs allowing the device on the fly frequency switching. the fsel pin incorporates a 60kl pull up resistor giving a default condition of logic 1 . output enable (oe) the output enable feature allows the user to enable and disable the clock output(s) by toggling the oe pin. the oe pin incorporates a 60kl pull up resistor giving a default condition of logic 1. power-down control (pdb) the power down (pdb) feature allows the user to put the pl611s-26 into sleep mode. when activated (logic 0), pdb disables the pll, the oscillator circuitry, counters, and all other activ e circuitry. in power down mode the ic consumes <10>a of power. the pdb pin incorporates a 60kl pull up resistor giving a default condition of logi c 1.
(preliminary) pl611s-26 1.8v-3.3v picopll tm programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 12/12/06 page 4 electrical specifications absolute maximum ratings parameters symbol min. max. units supply voltage range v dd - 0.5 7 v input voltage range v i - 0.5 v dd + 0.5 v output voltage range v o - 0.5 v dd + 0.5 v soldering temperature (green package) 260 c data retention @ 85 c 10 year storage temperature t s -65 150 c ambient operating temperature* -40 85 c exposure of the device under conditions beyond the limits specified by maximum ratings for extended pe riods may cause permanent damage to the device and affect product reliability. these conditions r epresent a stress rating only, and functional opera tions of the device at these or any other condition s above the operational limits noted in this specification is not implied. *operating temperature is guarante ed by design. parts are tested to commercial grade only. ac specifications parameters conditions min. typ. max. units @ v dd =3.3v 200 @ v dd =2.5v 166 input (fin) frequency @ v dd =1.8v 1 133 mhz input (fin) signal amplitude internally ac coupled (high frequency) 0.9 v dd vpp input (fin) signal amplitude internally ac coupled (low frequency) 3.3v < 50mhz, 2.5v < 40mhz, 1.8v < 15mhz 0.1 v dd v pp @ v dd =3.3v 200 mhz @ v dd =2.5v 166 mhz output frequency @ v dd =1.8v 133 mhz settling time at power-up (after v dd increases over 1.62v) 2 ms oe function; ta=25 o c, 15pf load 10 ns output enable time pdb function; ta=25 o c, 15pf load 2 ms output rise time 15pf load, 10/90% v dd , high drive, 3.3v 1.2 1.7 ns output fall time 15pf load, 90/10% v dd , high drive, 3.3v 1.2 1.7 ns duty cycle v dd /2 45 50 55 % period jitter,pk-to-pk* (measured from 10,000 samples) with capacitive decoupling between v dd and gnd. 70 ps * note: jitter performance depends on the programmi ng parameters.
(preliminary) pl611s-26 1.8v-3.3v picopll tm programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 12/12/06 page 5 dc specifications parameters symbol conditions min. typ. max. units supply current, dynamic, with loaded cmos outputs i dd @ v dd =3.3v, 27mhz, load=15pf 5.5 ma supply current, dynamic, with loaded cmos outputs i dd @ v dd =2.5v, 27mhz, load=15pf 3.8 ma supply current, dynamic with loaded cmos outputs i dd @ v dd =1.8v, 27mhz, load=15pf 1.8* ma stand by current, with loaded outputs i dd when pdb=0 <10 >a operating voltage v dd 1.62 3.63 v output low voltage v ol i ol = +4ma standard drive 0.4 v output high voltage v oh i oh = -4ma standard drive v dd C 0.4 v output current, low drive i osd v ol = 0.4v, v oh = 2.4v 4 ma output current, standard drive i osd v ol = 0.4v, v oh = 2.4v 8 ma output current, high drive i ohd v ol = 0.4v, v oh = 2.4v 16 ma * note: please contact phaselink, if super low-powe r is required.
(preliminary) pl611s-26 1.8v-3.3v picopll tm programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 12/12/06 page 6 layout recommendations the following guidelines are to assist you with a p erformance optimized pcb design: - keep all the pcb traces to the pl611s-26 as short as possible, as well as keeping all other traces as far away from it as possible. - place a 0.01>f~0.1>f decoupling capacitor between vdd and gnd, on the component side of the pcb, close to the vdd pin. it is not recommended to place this component on the backside of the pcb. going through vias will reduce the signal integrity, causing additional jitter and phase noise. - it is highly recommended to keep the vdd and gnd traces as short as possible. - when connecting long traces (> 1 inch) to a cmos output, it is important to design the traces as a transmission line or stripline, to avoid reflecti ons or ringing. in this case, the cmos output needs to be matched to the trace impedance. usually striplines are designed for 50l impedance and cmos outputs usually have lower than 50 l impedance so matching can be achieved by adding a resistor in series with the cmos output pin to the stripline trace. - please contact phaselink for additional informati on on how to design outputs driving long traces or for the gerber files for the pl611s-26 eval board shown. dfn-6l evaluation board
(preliminary) pl611s-26 1.8v-3.3v picopll tm programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 12/12/06 page 7 d e pin1 dot d1 b e e1 l a3 a a1 pin 6 id chamfer package drawings ( green package compliant) sot23-6l dfn-6l dimension in mm symbol min. max. a 1.05 1.35 a1 0.05 0.15 a2 1.00 1.20 b 0.30 0.50 c 0.08 0.20 d 2.80 3.00 e 1.50 1.70 h 2.60 3.0 l 0.35 0.55 e 0.95 bsc dimension in mm symbol min. max. a 0.50 0.60 a1 0.00 0.05 a3 0.152 0.152 b 0.15 0.25 e 0.40bsc d 1.25 1.35 e 1.95 2.05 d1 0.75 0.85 e1 0.95 1.05 l 0.20 0.30 c l a2 e h d a1 e b a
(preliminary) pl611s-26 1.8v-3.3v picopll tm programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 12/12/06 page 8 ordering information ( green package compliant) for part ordering, please contact our sales departm ent: 47745 fremont blvd., fremont, ca 94538, usa tel: (510) 492-0990 fax: (510) 492-0991 part number the order number for this device is a combination of the following: part number, package type and operating temperature range pl611 s-26-xxx x x x part/order number marking ? package option pl611s-26-xxxgc-r xxx 6-pin dfn (tape and ree l) pl611s-26-xxxtc-r 26xxx 6-pin sot23 (tape and reel) ? note: xxx designates marking identifier that, at times, could be independent of the part number. pl ease consult your phaselink sales f or marking information. phaselink corporation, reserves the right to make c hanges in its products or specifications, or both a t any time without notice. the information furnished by phaselink is believed to be accurate a nd reliable. however, phaselink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any lo ss or damage of whatever nature resulting from the use of, or reliance upon this product. life support policy : phaselinks products are not authorized for use a s critical components in life support devices or sy stems without the express written approval of the president of phasel ink corporation. solder reflow profile available at www.phaselink.com/qa/solderinggreen.pdf part number temperature c=commercial i = industrial package type g=dfn-6l t=sot23-6l 3 digit id code * (will be assigned at programming time) n one= tube r=tape and reel
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