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copyright ? cirrus logic, inc. 2010 (all rights reserved) cs8900a product data sheet crystal lan ? ethernet controller features ? single-chip ieee 802.3 ethernet controller with direct isa-bus interface ? maximum current consumption = 55 ma (5v supply ) ? 3v or 5v operation ? industrial temperature range ? comprehensive suite of software drivers available ? efficient packetpage? architecture operates in i/o and memory space, and as dma slave ? full duplex operation ? on-chip ram buffers transmit and receive frames ? 10base-t port with analog filters, provides: - automatic polarity de tection and correction ? aui port for 10base2, 10base5 and 10base-f ? programmable transmit features: - automatic re-transmission on collision - automatic padding and crc generation ? programmable receive features: - stream transfer? for reduced cpu overhead - auto-switch between dma and on-chip memory - early interrupts for frame pre-processing - automatic rejection of erroneous packets ? eeprom support for jumperless configuration ? boot prom support for diskless systems ? boundary scan and loopback test ? led drivers for link status and lan activity ? standby and suspend sleep modes description the cs8900a is a low-cost ethernet lan controller op- timized for the industry standa rd architecture (isa) bus and general purpose microcontroller busses. its highly- integrated design eliminates the need for costly external components required by other ethernet controllers. the cs8900a includes on-chip ram, 10base-t transmit and receive filters, and a di rect isa-bus interface with 24 ma drivers. in addition to high integration, the cs8900a offers a broad range of performance features and configura- tionoptions. its unique packetpage architecture automatically adapts to changing network traffic pat- terns and available system resources. the result is increased system efficiency. the cs8900a is available in a 100-pin lqfp package ideally suited for small form -factor, cost-sensitive ether- net applications. with the cs8900a, system engineers can design a complete ethernet circuit that occupies less than 1.5 square inches (10 sq. cm) of board space. ordering information CS8900A-CQZ 0 to 70 c 5v lqfp-100 lead free cs8900a-iqz -40 to 85 c 5v lqfp-100 lead free cs8900a-cq3z 0 to 70 c 3.3v lqfp-100 lead free cs8900a-iq3z -40 to 85 c 3.3v lqfp-100 lead free crd8900a-1 evaluation kit eeprom rj-45 10base-t attachment unit interface (aui) 20 mhz xtal ram bus logic memory manager 802.3 mac engine eeprom control encoder/ decoder & pll 10base-t rx filters & receiver 10base-t tx filters & transmitter aui transmitter aui collision aui receiver clock power manager boundary scan test logic led control cs8900a isa ethernet controller host host bus ds271f5 sep ?10
2 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet table of contents 1.0 introduction .............................................................................................................. ........8 1.1 general description ...................................................................................................... .....8 1.1.1 direct isa-bus interface .......................................................................................8 1.1.2 integrated memory ...............................................................................................8 1.1.3 802.3 ethernet mac engine .................................................................................8 1.1.4 eeprom interfac e .............. ................ ................ ............. ............. ............. ..........8 1.1.5 complete analog front end ................ .................................................................8 1.2 system applications ...................................................................................................... ....8 1.2.1 motherboard lans ...............................................................................................8 1.2.2 ethernet adapter cards ........................................................................................9 1.3 key features and benefits ..............................................................................................10 1.3.1 very low cost ....................................................................................................10 1.3.2 high performance ...............................................................................................10 1.3.3 low power and low noise .................................................................................10 1.3.4 complete support ...............................................................................................10 2.0 pin description ........................................................................................................ .....12 3.0 functional description ...............................................................................................17 3.1 overview ................................................................................................................. ........17 3.1.1 configuration ......................................................................................................17 3.1.2 packet transmis sion ..........................................................................................17 3.1.3 packet reception ...............................................................................................17 3.2 isa bus interface ........................................................................................................ ....18 3.2.1 memory mode operation ....................................................................................18 3.2.2 i/o mode operation ............................................................................................18 3.2.3 interrupt request signals ...................................................................................18 3.2.4 dma signals .......................................................................................................18 3.3 reset and initialization ................................................................................................. ...19 3.3.1 reset .................................................................................................................. 19 3.3.1.1 external reset, or isa reset ...............................................................19 3.3.1.2 power-up reset ..................................................................................19 3.3.1.3 power-down reset ..............................................................................19 3.3.1.4 eeprom reset ................ ................. ................ ............. ............. ........19 3.3.1.5 software initiated reset ........... ............................................................19 3.3.1.6 hardware (hw) standby or suspend ..................................................19 3.3.1.7 software (sw) suspend ............. .........................................................19 3.3.2 allowing time for reset operation .. ...................................................................20 3.3.3 bus reset considerations ..................................................................................20 3.3.4 initialization ......................................................................................................... 20 3.4 configurations with eeprom ................ ................ ................ ................ ................. ........21 3.4.1 eeprom interfac e .............. ................ ................ ............. ............. ............. ........21 3.4.2 eeprom memory organi zation .......... ................ ............. ............. ............. ........21 3.4.3 reset configuration block ..................................................................................21 3.4.3.1 reset configuration block struct ure ....................................................22 3.4.3.2 reset configuration block header ......................................................22 3.4.3.3 determining the eeprom type . ................ ................ ................. ........23 3.4.3.4 checking eeprom for presence of reset configuration block ..........23 3.4.3.5 determining number of bytes in the reset configuration block .........23 3.4.4 groups of configuration data .............................................................................23 3.4.4.1 group header ......................................................................................23 3.4.5 reset configuration block checksum . ...............................................................24 3.4.6 eeprom example .............. ................ ................ ............. ............. ............. ........24 3.4.7 eeprom read-out ...... ................ ................ ................. ................ ............. ........24
ds271f5 3 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 3.4.7.1 determining eeprom size .......... ................ ................. ............ ..........24 3.4.7.2 loading configuration data .................................................................24 3.4.8 eeprom read-out comp letion ......... ................ ............. ............. ............ .......... 24 3.5 programming the eeprom .. ................ ................ ................ ................ ................ .......... 25 3.5.1 eeprom command s .............. ................ ................ ................ ................ .......... 25 3.5.2 eeprom command execut ion ............ ................ ................ ................ ............. 25 3.5.3 enabling access to the eeprom ......... ................ ................ ................ ............. 26 3.5.4 writing and erasing the eeprom ..... ................ ............. ............. ............ .......... 26 3.6 boot prom operation .................................................................................................... 26 3.6.1 accessing the boot prom ................................................................................. 26 3.6.2 configuring the cs8900a for boot prom operation ........................................ 26 3.7 low-power modes .......................................................................................................... 27 3.7.1 hardware standby ..............................................................................................27 3.7.2 hardware susp end ............................................................................................. 27 3.7.3 software suspend ..............................................................................................27 3.8 led outputs .............................................................................................................. ...... 29 3.8.1 lanled ............................................................................................................. 29 3.8.2 linkled or hc0 ................................................................................................ 29 3.8.3 bstatus or hc1 ..............................................................................................29 3.8.4 led connection ................................................................................................. 29 3.9 media access control ..................................................................................................... 29 3.9.1 overview ............................................................................................................ 29 3.9.2 frame encapsulation and decapsulation ........................................................... 30 3.9.2.1 transmission ....................................................................................... 30 3.9.2.2 reception ............................................................................................ 30 3.9.2.3 enforcing minimum frame size .......................................................... 31 3.9.3 transmit error detect ion and handling .............................................................. 31 3.9.3.1 loss of carrier ..................................................................................... 31 3.9.3.2 sqe error ............................................................................................ 31 3.9.3.3 out-of-windo w (late) collision ............................................................ 31 3.9.3.4 jabber erro r ........................................................................................ 31 3.9.3.5 transmit collision ................................................................................ 31 3.9.3.6 transmit un derrun .............................................................................. 32 3.9.4 receive error detection and handling ............................................................... 32 3.9.4.1 crc error ............................................................................................ 32 3.9.4.2 runt frame ......................................................................................... 32 3.9.4.3 extra data ........................................................................................... 32 3.9.4.4 dribble bits and alignment error ......................................................... 32 3.9.5 media access management ............................................................................... 32 3.9.5.1 collision avoidance ............................................................................. 32 3.9.5.2 two-part deferral ................................................................................ 33 3.9.5.3 simple defe rral .................................................................................... 33 3.9.5.4 collision resolution ............................................................................. 34 3.9.5.5 normal collisions ................................................................................ 34 3.9.5.6 late collisions ..................................................................................... 34 3.9.5.7 backoff ................................................................................................ 34 3.9.5.8 standard backoff ................................................................................. 34 3.9.5.9 modified backoff .................................................................................. 35 3.9.5.10 sqe test ........................................................................................... 35 3.10 encoder/decoder (endec) .......................................................................................... 35 3.10.1 encoder ............................................................................................................ 35 3.10.2 carrier detect ion ..............................................................................................36 3.10.3 clock and data recovery ................................................................................. 36
4 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 3.10.4 interface selection ............................................................................................36 3.10.4.1 10base-t only .. ................ ................ ............. ............. ............. ........36 3.10.4.2 aui only ............................................................................................36 3.10.4.3 auto-select ......... ...............................................................................36 3.11 10base-t transceiver ...... ................ ................ ................ ................ ................ ............36 3.11.1 10base-t filter s ............... ................ ................ ............. ............. ............. ........37 3.11.2 transmitter ........... ............................................................................................37 3.11.3 receiver ...........................................................................................................37 3.11.3.1 squelch circuit ...................................................................................37 3.11.3.2 extended range . ...............................................................................38 3.11.4 link pulse detection .........................................................................................38 3.11.5 receive polarity detection and correction .......................................................38 3.11.6 collision detection ............................................................................................39 3.12 attachment unit interfac e (aui) ....................................................................................39 3.12.1 aui transmitter ..... ............................................................................................39 3.12.2 aui receiver ....................................................................................................39 3.12.3 collision detection ............................................................................................39 3.13 external clock oscillator ............................................................................................... 40 4.0 packetpage architecture..........................................................................................41 4.1 packetpage overview .....................................................................................................4 1 4.1.1 integrated memory .............................................................................................41 4.1.2 bus interface registers ................... ...................................................................41 4.1.3 status and control registers ..............................................................................41 4.1.4 initiate transmit registers ..................................................................................41 4.1.5 address filter regist ers .....................................................................................41 4.1.6 receive and transmit frame locations .............................................................41 4.2 packetpage memory map ...............................................................................................42 4.3 bus interface registers .................................................................................................. .44 4.4 status and control registers ................. .........................................................................49 4.4.1 configuration and control registers ...................................................................49 4.4.2 status and event registers ................................................................................49 4.4.3 status and control bit definitions .......................................................................50 4.4.3.1 act-once bits .......................................................................................50 4.4.3.2 temporal bits .......................................................................................50 4.4.3.3 interrupt enable bits and events .........................................................50 4.4.3.4 accept bits ...........................................................................................51 4.4.4 status and control register summary ...............................................................51 4.5 initiate transmit registers .............................................................................................. .69 4.6 address filter registers ................................................................................................. .71 4.7 receive and transmit frame locations .... ......................................................................72 4.7.1 receive packetpage locations ........... ...............................................................72 4.7.2 transmit locations .............................................................................................72 4.8 eight and sixteen bit transfers .......................................................................................72 4.8.1 transferring odd-byte-aligned data ..................................................................73 4.8.2 random access to cs 8900a memory ...............................................................73 4.9 memory mode operation .................................................................................................73 4.9.1 accesses in memory mode .................................................................................73 4.9.2 configuring the cs8900a for memory mode ......................................................74 4.9.3 basic memory mode tr ansmit ............................................................................74 4.9.4 basic memory mode receive .......... ...................................................................75 4.9.5 polling the cs8900a in memory mode ...............................................................75 4.10 i/o space operation ..................................................................................................... .75 4.10.1 receive/transmit da ta ports 0 and 1 ...............................................................75
ds271f5 5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 4.10.2 txcmd port ...................................................................................................... 75 4.10.3 txlength port ................................................................................................... 76 4.10.4 interrupt status queue port ............................................................................. 76 4.10.5 packetpage pointer port .................................................................................. 76 4.10.6 packetpage data ports 0 and 1 ....................................................................... 76 4.10.7 i/o mode operation .......................................................................................... 76 4.10.8 basic i/o mode transmit .................................................................................. 76 4.10.9 basic i/o mode receive ................................................................................... 77 4.10.10 accessing internal registers ...... .................................................................... 77 4.10.11 polling the cs8900a in i/o mode ................................................................... 77 5.0 operation ................................................................................................................. ......... 78 5.1 managing interrupts and se rvicing the interrupt status queue ...................................... 78 5.2 basic receive operation ................................................................................................. 7 8 5.2.0.1 overview ............................................................................................. 78 5.2.1 terminology: packet, frame, and transfer ........................................................ 80 5.2.1.1 packet ................................................................................................. 80 5.2.1.2 frame .................................................................................................. 80 5.2.1.3 transfer ............................................................................................... 80 5.2.2 receive configuration ........................................................................................ 80 5.2.2.1 configuring the physical interf ace ....................................................... 81 5.2.2.2 choosing which frame types to accept ............................................. 81 5.2.2.3 selecting which events cause interrupts ............................................ 81 5.2.2.4 choosing how to transfer frames ...................................................... 81 5.2.3 receive frame pre-proc essing ......................................................................... 82 5.2.3.1 destination address filtering .............................................................. 82 5.2.3.2 early interrupt generation ................................................................... 82 5.2.3.3 acceptance filtering ............................................................................ 83 5.2.3.4 normal interrupt generation ................................................................ 83 5.2.4 held vs. dmaed receiv e frames ...................................................................... 83 5.2.5 buffering held receive frames ......... ................................................................ 85 5.2.6 transferring held receive frames .................................................................... 85 5.2.7 receive frame visibility ..................................................................................... 85 5.2.8 example of memory mode receive op eration ................................................... 86 5.2.9 receive frame byte counter ............................................................................. 86 5.2.10 receive frame addre ss filtering ..................................................................... 87 5.2.10.1 individual address frames ... ............................................................. 87 5.2.10.2 multicast frames ............................................................................... 87 5.2.10.3 broadcast frames ................... .......................................................... 87 5.2.11 configuring the dest ination address filter ....................................................... 87 5.2.12 hash filter ........................................................................................................ 88 5.2.12.1 hash filter oper ation ........................................................................ 88 5.2.13 broadcast frame hashing exception ............................................................... 88 5.3 receive dma .............................................................................................................. .... 90 5.3.1 overview ............................................................................................................ 90 5.3.2 configuring the cs8900a for dma operation ....................................................90 5.3.3 dma receive buffer size ................................................................................... 91 5.3.4 receive-dma-on ly operation ............................................................................ 91 5.3.5 committing buffer space to a dmae d frame ....................................................92 5.3.6 dma buffer organization ................................................................................... 92 5.3.7 rxdmaframe bit ............................................................................................... 92 5.3.8 receive dma example without wrap-ar ound ................................................... 92 5.3.9 receive dma operation for rxdma-on ly mode ............................................... 92 5.4 auto-switch dma .......................................................................................................... .. 94
6 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 5.4.1 overview .............................................................................................................94 5.4.2 configuring the cs8900a for auto-swit ch dma .................................................94 5.4.3 auto-switch dm a operation ...............................................................................94 5.4.4 dma channel speed vs. missed frames ...........................................................95 5.4.5 exit from dma ...................................................................................................96 5.4.6 auto-switch dma exampl e .................................................................................96 5.5 streamtransfer ........................................................................................................... ....96 5.5.1 overview .............................................................................................................96 5.5.2 configuring the cs8900a for streamtr ansfer ....................................................96 5.5.3 streamtransfer operation ..................................................................................96 5.5.4 keeping streamtransfer mode active ................................................................98 5.5.5 example of streamtransfer ................................................................................98 5.5.6 receive dma summary .....................................................................................99 5.6 transmit operation ....................................................................................................... ...99 5.6.1 overview .............................................................................................................99 5.6.2 transmit configuration .......................................................................................99 5.6.2.1 configuring the physical interfac e .......................................................99 5.6.2.2 selecting which events cause interrupts ..........................................100 5.6.3 changing the configuration ..............................................................................100 5.6.4 enabling crc generati on and padding ...........................................................101 5.6.5 individual packet tran smission ........................................................................101 5.6.6 transmit in poll mode .......................................................................................101 5.6.7 transmit in interrupt mode ................................................................................102 5.6.8 completing transmissi on .................................................................................103 5.6.9 rdy4txnow vs. rdy4tx ..................................................................................104 5.6.10 committing buffer space to a transm it frame ..............................................105 5.6.11 transmit frame length ................. .................................................................105 5.7 full duplex considerations ............................................................................................105 5.8 auto-negotiation considerations ...................................................................................105 6.0 test...................................................................................................................... ...............107 6.1 test modes ............................................................................................................... 107 6.1.1 loopback & collision diagnostic tests .............................................................107 6.1.2 internal tests ....................................................................................................107 6.1.3 external tests ...................................................................................................107 6.1.4 loopback tests ................................................................................................107 6.1.5 10base-t loopback and collision tests ..... ................. ................ ............. ......107 6.1.6 aui loopback and collision tests ....................................................................107 6.2 boundary scan ............................................................................................................ ..108 6.2.1 output cycle .....................................................................................................108 6.2.2 input cycle ........................................................................................................108 6.2.3 continuity cycle ................................................................................................109 7.0 characteristics/specifications - commer cial ............ ................ ............. ......112 8.0 characteristics/specifications - indust rial ........... ................ ................. ......123 9.0 physical dimensions ....................................................................................................134 10.0 glossary of terms ...... ..............................................................................................135 10.1 acronyms ................................................................................................................ ....135 10.2 definitions ............................................................................................................. .......136 10.3 acronyms specific to the cs8900a ............................................................................137 10.4 definitions specific to the cs8900a ............................................................................137 10.5 suffixes specific to the cs8900a. ...............................................................................138
ds271f5 7 cs8900a crystal lan? ethernet controller cirrus logic product datasheet table 1. revision history release date changes pp1 nov 1997 preliminary release, revision 1 pp2 dec 1998 preliminary release, revision 2 pp3 mar 1999 preliminary release, revision 3 pp4 apr 2001 preliminary release, revision 4 page 13: intrq[0:2] changed to intrq[0..3] page 41: added bit definitions for revisions c and d page 56: packetpage base + 0218h changed to packetpage base + 0128h page 81: table 19: register 5, lrxctl changed to register 5, rxctl page 86: table 23: 0410h to 011h changed to 0410h to 0411h f1 jan 2004 final release, revision 1 page 1: changed package option from tqfp to lqfp . page 134: changed package drawing and from tqfp to lqfp , and updated dimensions. f2 jul 2004 added ordering information for the -cq3z lead free part f3 sep2004 added ordering information for the -cqz lead free part f4 aug 2007 added industrial temperature range pb-free devices. f5 sep 2010 page 1: removed lead-containg dev ice ordering information.page 112: updated hardware standby mode current. page 113, 124: updated power supply cu rrent & aui interface dc characteristics. page 119, 130: updated aui inte rface switching characteristics. contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find one nearest you go to www.cirrus.com iimportant notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the information is sub- ject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products a re sold subject to the terms and con- ditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limi tation of liability. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the pr operty of cirrus and by furnishing this information, cirrus gr ants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns t he copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization w ith respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, a dvertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental dama ge ("critical applications"). cirrus products are not designed, authorized or warranted for use in products surgically implanted into the body, automotive safety or security devices, life support products or other critical applicati ons. inclusion of cirrus products in such applications is unde rstood to be fu lly at the cus- tomer's risk and cirrus disclaims and ma kes no warranty, express, statutory or implied, including th e implied warranties of merchantability and fi tness for particular purp ose, with regard to an y cirrus product that is used in such a manner. if the customer or customer's customer uses or permits th e use of cirrus products in cr itical applications, customer agrees, by such use, to fully indemnify cirrus, its of ficers, directors, employees, di stributors and other agents from any and all liability, including attorneys' fees and costs, th at may result from or arise in connection with these uses. cirrus logic, cirrus, the cirrus logic logo designs and crystal lan are trademarks of cirrus logic, inc. all other brand and pr oduct names in this document may be trademarks or service marks of their respective owners. i 2 c is a registered trademark of philips semiconductor.
8 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 1.0 introduction 1.1 general description the cs8900a is a true si ngle-chip, full-duplex, ethernet solution, incor porating all of the ana- log and digital circuitr y needed for a complete ethernet circuit. majo r functional blocks in- clude: a direct isa-bu s interface; an 802.3 mac engine; int egrated buffer memory; a seri- al eeprom interface; and a complete analog front end with bo th 10base-t and aui. 1.1.1 general purpose and isa-bus inter- face included in the cs8900a is a direct isa-bus in- terface with full 24 ma drive capability. its con- figuration options incl ude a choice of four interrupts and three dma channels (one of each selected during init ialization). in memory mode, it supports sta ndard or ready bus cy- cles without introducing additional wait states. the bus can be configured to support many microcontroller and mi crocomputer busses. 1.1.2 integrated memory the cs8900a incorporat es a 4-kbyte page of on-chip memory, elim inating the cost and board area associated wi th external memory chips. unlike most othe r ethernet controllers, the cs8900a buffers entire transmit and re- ceive frames on chip, eliminating the need for complex, inefficient memory management schemes. in addition, the cs8900a operates in either memory space, i/o space, or with ex- ternal dma controller s, providing maximum design flexibility. 1.1.3 802.3 ethe rnet mac engine the cs8900a?s ethernet media access con- trol (mac) engine is full y compliant with the ieee 802.3 ethernet st andard (iso/iec 8802- 3, 1993), and su pports full-duplex operation. it handles all aspects of ethernet frame trans- mission and reception, in cluding: collision de- tection, preamble gener ation and detection, and crc generation and te st. programmable mac features include automatic retransmis- sion on collision, and automatic padding of transmitted frames. 1.1.4 eeprom interface the cs8900a provides a simple and efficient serial eeprom interface that allows configu- ration information to be stored in an optional eeprom, and then loaded automatically at power-up. this eliminat es the need for costly and cumbersome switches and jumpers. 1.1.5 complete analog front end the cs8900a?s analog fr ont end incorporates a manchester encoder/decoder, clock recov- ery circuit, 10base-t transceiver, and com- plete attachment unit interface (aui). it provides manual and autom atic selection of ei- ther 10base-t or aui, and offers three on- chip led drivers for link status, bus status, and ethernet line activity. the 10base-t transceiv er includes drivers, receivers, and analog fi lters, allowing direct connection to low-cost isolation transformers. it supports 100, 120, and 150 shielded and unshielded cables, extended cable lengths, and automatic receive pol arity reversal detec- tion and correction. the aui port provides a direct interface to 10base-2, 10base-5, an d 10base-fl net- works, and is capable of driving a full 50-meter aui cable. 1.2 system applications the cs8900a is designed to work well in ei- ther motherboard or a dapter applications. 1.2.1 motherboard lans the cs8900a requires the minimum number of external components needed for a full ethernet node. its small- footprint package and
ds271f5 9 cs8900a crystal lan? ethernet controller cirrus logic product datasheet high level of integrat ion allow system engi- neers to design a complete ethernet circuit that occupies as little as 1.5 square inches of pcb area (figure 1) . in addition, the cs8900a?s power-saving features and cmos design make it a perfect fit for power-sensitive portable and desktop pcs. motherboard de- sign options include: ? an eeprom can be used to store node- specific information, such as the ethernet individual address and node configuration. ? the 20 mhz crystal oscillator may be re- placed by a 20 mhz clock signal. 1.2.2 ethernet adapter cards the cs8900a?s highly efficient packetpage architecture, with streamtransfer? and auto- switch dma options, make it an excellent choice for high-performance, low-cost isa adapter cards (figure 2). the cs8900a?s wide range of configuration options and perfor- mance features allo w engineers to design ethernet solutions that meet their particular system requirements. adap ter card design op- tions include: ? a boot prom can be added to support diskless applications. ? the 10base-t transmitter and receiver impedance can be adjus ted to support 100, 120, or 150 ohm twis ted pair cables. ? an external latchable-address-bus de- code circuit can be added to operate the cs8900a in upper -memory space. rj-45 10base-t cs8900a i s a eeprom 20 mhz xtal (2.0 sq. in.) figure 1. complete ethernet motherboard solution cs8900a eeprom boot prom '245 20 mhz xtal rj-45 led attachment unit interface (aui) figure 2. full-featured isa adapter solution
10 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet ? on-chip led ports can be used for either optional leds, or as programmable out- puts. 1.3 key features and benefits 1.3.1 very low cost the cs8900a is designed to provide the low- est-cost ethernet solu tion available for embed- ded applications, port able motherboards, non- isa bus systems and adapter cards. cost-sav- ing features include: ? integrated ram elimi nates the need for ex- pensive external memory chips. ? on-chip 10base-t filters allow designers to use simple isolation transformers in- stead of more costly filter/transformer packages. ? the serial eeprom por t, used for configu- ration and initializati on, eliminates the need for expensive switches and jumpers. ? the cs8900a is designed to be used on a 2-layer circuit board instead of a more ex- pensive multilayer board. ? the 8900a-based solution offers the small- est footprint avail able, saving valuable printed circuit board area. ? a set of certified software drivers is avail- able at no charge, elim inating the need for costly software development. 1.3.2 high performance the cs8900a is a full 16-bit ethernet control- ler designed to provide optimal system perfor- mance by minimizing ti me on the isa bus and cpu overhead per frame. it offers equal or su- perior performance for less money when com- pared to other ethernet controllers. the cs8900a?s packetpage architecture allows software to select whichever access method is best suited to each particular cpu/isa-bus configuration. when co mpared to older i/o- space designs, packetpage is faster, simpler and more efficient. to boost performance further, the cs8900a includes several key f eatures that increase throughput and lower cpu overhead, includ- ing: ? streamtransfer cuts up to 87% of inter- rupts to the host cpu during large block transfers. ? auto-switch dma allows the cs8900a to maximize throughput while minimizing missed frames. ? early interrupts allow the host to prepro- cess incoming frames. ? on-chip buffering of full frames cuts the amount of host bandwid th needed to man- age ethernet traffic. 1.3.3 low power and low noise for low power needs, the cs8900a offers three power-down options: hardware stand- by, hardware suspend, and software sus- pend. in standby mode, the chip is powered down with the excepti on of the 10base-t re- ceiver, which is enabled to listen for link activ- ity. in either hardwa re or software suspend mode, the receiver is disabled and power con- sumption drops to the micro-ampere range. in addition, the cs 8900a has been designed for very low noise emi ssion, thus shortening the time required for em i testing and qualifica- tion. 1.3.4 complete support the cs8900a comes with a suite of software drivers for immediate us e with most industry standard network operat ing systems. in addi- tion, complete evaluati on kits and manufactur- ing packages are available, significantly reducing the cost and ti me required to produce new ethernet produc ts.
ds271f5 11 cs8900a crystal lan? ethernet controller cirrus logic product datasheet eecs eedataout eesk sa[0:19] memw memr iow ior refresh sbhe sd[0:15] intrq0 intrq1 rxd- rxd+ txd- txd+ do- do+ ci- ci+ di- di+ lanled linkled csout eedatain aen reset intrq2 intrq3 dmarq0 dmack0 dmarq1 dmack1 dmarq2 dmack2 memcs16 iochrdy t c 1 3 6 8 1% t r1 1% 92 91 88 87 100 , 1% rj45 16 14 11 9 6 3 2 1 1:1 1 4 5 8 84 82 81 79 16 13 12 9 10 10 9 2 5 83 80 2 7 15 3 12 1:1 1:1 0.1 f 680 680 ce oe oe dir 20 22 19 1 74ls245 xtal 1 xtal 2 sleep test res cs do di clk 1 3 2 4 3 5 4 6 93c46 28 62 61 29 7 irq10 irq11 irq12 irq5 drq5 dack5 drq6 dack6 drq7 dack7 16 20 sa[0:19] la[20:23] bale 4 97 98 93 4.99 k ,1% 12 v 4, 6 20 mhz 0.1 f 39.2 ,1% 5v 4.7 k cs8900a chipsel iocs16 49 63 75 36 34 64 33 32 30 35 31 15 13 14 16 11 12 99 100 17 39.2 ,1% 39.2 ,1% 39.2 ,1% eeprom address decoder pal 27c256 elcs isa bus 10 base t isolation transformer 1:1 15 pin d aui isolation transformer bstatus/hci boot-prom pd[0:7] sa[0:14] sd[0:7] 15 8 5v 13 77 76 78 0.1 f 7 t r2 ttr figure 3. typical isa bus connection diagram 5 volt 3 volt ttr 1 : 1.414 1 : 2.5 t r1 and t r2 24.3 8.0 t c 69 pf 560 pf
12 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 2.0 pin description 36 40 41 46 47 48 49 50 26 27 28 29 30 31 33 32 34 35 37 38 39 42 43 44 45 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 76 77 78 79 80 2 1 3 16 5 4 6 8 7 9 10 11 12 13 14 15 17 18 20 19 21 22 23 24 53 54 55 56 57 58 59 60 61 62 63 64 51 52 65 66 68 67 69 70 71 72 73 74 75 25 eedataout eesk eecs eedatain chipsel dmack2 dmack1 dmack0 dmarq2 dmarq1 dmarq0 sd15 sd14 sd13 sd12 dvdd2 dvss2 sd11 csout sd10 sd08 sa3 sa4 sa15 sa14 avss4 bstatus or hc1 txd + txd - avss1 avdd1 rxd - rxd + avss2 avdd2 test sleep xtal1 xtal2 res avss3 sa0 intrq2 intrq1 iocs16 intrq0 memcs16 sbhe sa1 sa2 intrq3 sa9 sa10 sa8 sa11 sa5 sa6 sa7 refresh sa19 sa18 sa17 dvdd3 dvss3 sa16 sd0 aen iow ior iochrdy sd1 sd5 sd4 sd3 sd2 dvss4 dvdd4 sd6 sd7 linkled or hc0 reset sa13 memw memr dvss1 dvdd1 elcs avss0 dvss1a sd09 sa12 dvss3a avdd3 lanled do- do+ di- di+ ci- ci+ cs8900a 100-pin tqfp (q) top view
ds271f5 13 cs8900a crystal lan? ethernet controller cirrus logic product datasheet isa bus interface sa[0:19] - system address bus, input pins 37-48, 50-54, 58-60. lower 20 bits of the 24-bit system addr ess bus used to decode accesses to cs8900a i/o and memory space, and attached boot prom. sa0- sa15 are used for i/o read and write operations. sa0-sa19 are used in conj unction with external decode logic for memory read and wr ite operations. sd[0:15] - system data bus, bi-directional with 3-state ou tput pins 65- 68, 71-74, 27- 24, 21-18. bi-directional 16-bit system data bus us ed to transfer data bet ween the cs8900a and the host. reset - reset, input pin 75. active-high asynchronous input used to reset the cs8900a. must be stable for at least 400 ns before the cs8900a recognize s the signal as a valid reset. aen - address enable, input pin 63. when test is high, this active-h igh input indicates to the cs8900a that the system dma controller has control of the isa bus. when aen is high, the cs8900a will not perform slave i/o spac e operations. when test is low, this pin becomes the shift clock input for the boundary scan test. ae n should be inactive when performing an io or memory access and it s hould be active during a dma cycle. memr - memory read, input pin 29. active-low input indicates that the host is execut ing a memory read operation. memw - memory write, input pin 28. active-low input indicates that the host is executin g a memory write operation. memcs16 - memory chip select 16-bi t, open drain output pin 34. open-drain, active-low outpu t generated by the cs8900a when it recognizes an address on the isa bus that corresponds to its assi gned memory space (cs8900a must be in memory mode with the memorye bit (register 17, busc tl, bit a) set for memcs16 to go active). 3- stated when not active. refresh - refresh, input pin 49. active-low input indicates to the cs8900a that a dram refresh cycle is in progress. when refresh is low, memr , memw , ior , iow , dmack0 , dmack1 , and dmack2 are ignored. ior - i/o read, input pin 61. when ior is low and a valid addr ess is detected, the cs 8900a outputs the contents of the selected 16-bit i/o register onto the system data bus. ior is ignored if refresh is low.
14 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet iow - i/o write, input pin 62. when iow is low and a valid addre ss is detected, the cs8900a writes the data on the system data bus into the selected 16-bit i/o register. iow is ignored if refresh is low. iocs16 - i/o chip select 16-bit, open drain output pin 33. open-drain, active-low outpu t generated by the cs8900a when it recognizes an address on the isa bus that corresponds to its assigned i/o space. 3-stated when not active. iochrdy - i/o channel ready, open drain output pin 64. when driven low, this open-drain, active -high output extends i/o read and memory read cycles to the cs8900a. th is output is functional w hen the iochrdye bit in the bus control register (register 17) is clea r. this pin is alwa ys 3-stated when the iochrdye bit is set. sbhe - system bus high enable, input pin 36. active-low input indicates a data transfer on the high byte of the system data bus (sd8-sd15). after a hardware or a software reset, the cs8900a will be in 8-bit mode. provide a high to lo w and then low to high transition on the sbhe signal before any 16-bit io or memory access is done to the cs8900a. intrq[0:3] - interrupt requ est, 3-state pi ns 30-32, 35. active-high output indicates the presence of an interrupt event. interrupt request goes low once the interrupt status queue (isq) is read as all 0's. only one interrupt request output is used (one is selected during conf iguration). all non-selected interrupt request outputs are placed in a high-impedance state. (section 3.2 on page 18 and section 5.1 on page 78.) dmarq[0:2] - dma request, 3-state pins 11, 13, and 15. active-high, 3-stateable output used by the cs8900a to request a dma transfer. only one dma request out put is used ( one is selected during configuratio n). all non- selected dma request outputs are pl aced in a high-impedance state. dmack [0:2] - dma acknowledge, input pins 12, 14, and 16. active-low input indicates acknowledgment by the host of the corresponding dma request output. chipsel - chip select , input pin 7. active-low input generated by external latchable addr ess bus decode logic when a valid memory address is present on the isa bus. if memory mode operation is not needed, chipsel should be tied low. the chipsel is ignored for io and dma mode of the cs8900a. eeprom and boot prom interface eesk - eeprom seri al clock, pin 4. serial clock used to clock dat a into or out of the eeprom.
ds271f5 15 cs8900a crystal lan? ethernet controller cirrus logic product datasheet eecs - eeprom chip select, pin 3. active-high output used to select the eeprom. eedatain - eeprom data in, input internal weak pullup pin 6. serial input used to receiv e data from the eepro m. connects to th e do pin on the eeprom. eedatain is also used to sense the presence of the eeprom. elcs - external logic chip sel ect, internal weak pullup pin 2. bi-directional signal used to configure exte rnal latchable address (la) decode logic. if external la decode logi c is not needed, elcs should be tied low. eedataout - eeprom data out, pin 5. serial output used to send data to the eeprom. connects to the di pin on the eeprom. when test is low, this pin becomes the output for the boundary scan test. csout - chip select for external boot prom, pin 17. active-low output used to select an exte rnal boot prom w hen the cs8900a decodes a valid boot prom memory address. 10base-t interface txd+/txd- - 10base-t tran smit, differential out put pair pins 87 and 88. differential output pair drives 10 mb/s manchester-encoded data to the 10base-t transmit pair. rxd+/rxd- - 10base-t recei ve, differential input pair pins 91 and 92. differential input pair receives 10 mb/s manchester-encoded data from the 10base-t receive pair. attachment unit interface (aui) do+/do- - aui data out, differenti al output pair pins 83 and 84. differential output pair drives 10 mb/s manchester-encoded data to the aui transmit pair. di+/di- - aui data in, differentia l input pair pi ns 79 and 80. differential input pair rece ives 10 mb/s manchester-enc oded data from t he aui receive pair. ci+/ci- - aui collision in, differ ential input pair pins 81 and 82. differential input pair connects to the aui collision pair. a co llision is indicated by the presence of a 10 mhz 15% signal with duty cycl e no worse than 60/40.
16 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet general pins xtal[1:2] - crystal, input/o utput pins 97 and 98. a 20 mhz crystal should be connected across these pins. if a crystal is not used, a 20 mhz signal should be conn ected to xtal1 an d xtal2 should be left open. (see section 7.3 on page 112 and section 7.7 on page 122.) sleep - hardware sleep, input internal weak pullup pin 77. active-low input used to enable the tw o hardware sleep modes: hardware suspend and hardware standby. (see section 3.7 on page 27.) linkled or hc0 - link good led or ho st controlled output 0, open drain output pin 99. when the hce0 bit of t he self control regist er (register 15) is clear, this active-low output is low when the cs8900a detects the presence of valid link pulses. when the hc0e bit is set, the host may drive this pin low by se tting the hcbo in the self control register. bstatus or hc1 - bus status or host controlled output 1, open drain output pin 78. when the hc1e bit of t he self control regist er (register 15) is clear, this active-low output is low when receive activity caus es an isa bus access. when the hc1e bit is set, the host may driv e this pin low by setti ng the hcb1 in the se lf control register. lanled - lan activity led, op en drain output pin 100. during normal operation, this active-low output goes low fo r 6 ms whenever there is a receive packet, a transm it packet, or a collision. duri ng hardware st andby mode, this output is driven low w hen the receiver detects network activity. test - test enable, input in ternal weak pullup pin 76. active-low input used to put the cs8900a in boundary scan test mode. for normal operation, this pin should be high. res - reference resistor, input pin 93. this input should be connected to a 4.99k 1% resistor needed for biasing of internal analog circuits. dvdd[1:4] - digital power, po wer pins 9, 22, 56, and 69. provides 5 v 5% power to the digital circ uits of the cs8900a. dvss[1:4} and dvss1a, dvss3a - digital groun d, ground pins 8, 10, 23, 55, 57, and 70. provides ground reference (0 v) to t he digital circuits of the cs8900a. avdd[1:3] - analog power, power pins 90 , 85, and 95. provides 5 v 5% power to t he analog circuits of the cs8900a. avss[0:4] - analog ground, gr ound pins 1, 89, 86, 94, 96. provide ground reference (0 v) to t he analog circuits of the cs8900a.
ds271f5 17 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 3.0 functional description 3.1 overview during normal operation, the cs8900a per- forms two basic functions: ethernet packet transmission and recepti on. before transmis- sion or reception is possible, the cs8900a must be configured. 3.1.1 configuration the cs8900a must be configured for packet transmission and recepti on at power-up or re- set. various parameters must be written into its internal configurat ion and control registers such as memory base address; ethernet physical address; what frame types to re- ceive; and which media interface to use. con- figuration data can eit her be written to the cs8900a by the host (across the isa bus), or loaded automatically from an external ee- prom. operation can begin after configura- tion is complete. section 3.3 on page 19 and section 3.4 on page 21 describe the configuration process in detail. section 4.4 on page 49 provides a de- tailed description of the bits in the configura- tion and contro l registers. 3.1.2 packet transmission packet transmission occu rs in two phases. in the first phase, the hos t moves the ethernet frame into the cs8900a?s buffer memory. the first phase begins with the host issuing a transmit command. this informs the cs8900a that a frame is to be transmitted and tells the chip when to start transmission (i.e. af- ter 5, 381, 1021 or a ll bytes have been trans- ferred) and how the fram e should be sent (i.e. with or without crc , with or with out pad bits, etc.). the host foll ows the transmit command with the transmit length, indicating how much buffer space is required. when buffer space is available, the host wr ites the ethernet frame into the cs8900a?s inter nal memory, either as a memory or i/o space operation. in the second phase of transmission, the cs8900a converts the frame into an ethernet packet then transmits it onto the network. the second phase begins with the cs8900a trans- mitting the preamble a nd start-of-frame de- limiter as soon as the pr oper number of bytes has been transferred into it s transmit buffer (5, 381, 1021 bytes or full frame, depending on configuration). the pr eamble and start-of- frame delimiter are followed by the destina- tion address, source address, length field and llc data (all supplied by the host). if the frame is less than 64 bytes, including crc, the cs8900a adds pad bits if configured to do so. finally, the cs8900a appends the proper 32- bit crc value. the section 5.6 on page 99 provides a de- tailed description of packet transmission. 3.1.3 packet reception like packet transmission , packet reception oc- curs in two phases. in the first phase, the cs8900a receives an ethernet packet and stores it in on-chip me mory. the first phase of packet reception begins with the receive frame passing through the analog front end and manchester decoder w here manchester data is converted to nrz data. next, the preamble and start-of-frame delim iter are stripped off and the receive frame is sent through the ad- dress filter. if the fram e?s destination address matches the criteria pr ogrammed into the ad- dress filter, the packet is stored in the cs8900a?s internal memory. the cs8900a then checks the crc, and depending on the configuration, informs the processor that a frame has been received. in the second phas e, the host tr ansfers the re- ceive frame across the isa bus and into host memory. receive frames can be transferred
18 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet as memory space operat ions, i/o space oper- ations, or as dma ope rations using host dma. also, the cs8900a provides the capability to switch between memory or i/o operation and dma operation by usin g auto-switch dma and streamtransfer. the section 5.2 on page 78 through section 5.5 on page 96 pr ovide a detailed de- scription of packet reception. 3.2 isa bus interface the cs8900a provides a direct interface to isa buses running at clo ck rates from 8 to 11 mhz. its on-chip bus dr ivers are capable of de- livering 24 ma of drive current, allowing the cs8900a to drive the isa bus directly, without added external ?glue logic?. the cs8900a is optim ized for 16-bit data transfers, operating in either memory space, i/o space, or as a dma slave. note that isa-bus o peration below 8 mhz should use the cs8900a?s receive dma mode to minimize missed frames. see section 5.3 on page 90 fo r a description of re- ceive dma operation. 3.2.1 memory mode operation when configured for memory mode operation, the cs8900a?s internal registers and frame buffers are mapped into a contiguous 4-kbyte block of host memory, providing the host with direct access to the cs 8900a?s internal regis- ters and frame buffers. the host initiates read operations by driving the memr pin low and write operations by driving the memw pin low. for additional information about memory mode, see section 4.9 on page 73. 3.2.2 i/o mode operation when configured for i/o mode operation, the cs8900a is accessed th rough eight, 16-bit i/o ports that are mapped in to sixteen contiguous i/o locations in the host system?s i/o space. i/o mode is the default configuration for the cs8900a and is always enabled. for an i/o read or writ e operation, the aen pin must be low, and the 16-bit i/o address on the isa system addr ess bus (sa0 - sa15) must match the address space of the cs8900a. for a read, ior must be low, and for a write, iow must be low. for additional informat ion about i/o mode, see section 4.10 on page 75. 3.2.3 interrupt request signals the cs8900a has four interrupt request out- put pins that can be connected directly to any four of the isa bus in terrupt request signals. only one interrupt output is used at a time. it is selected during initializa tion by writing the in- terrupt number (0 to 3) into packetpage mem- ory base + 0022h. unused interrupt request pins are placed in a high-impedance state. the selected interrupt request pin goes high when an enabled interrup t is triggered. the pin goes low after the in terrupt status queue (isq) is read as all 0? s (see section 5.1 on page 78 for a description of the isq). table 2 presents one po ssible way of connect- ing the interrupt request pins to the isa bus that utilizes commonly available interrupts and facilitates board layout. 3.2.4 dma signals the cs8900a interfaces directly to the host dma controller to provi de dma transfers of re- ceive frames from cs8900a memory to host cs8900a interrupt request pin isa bus interrupt packetpage base + 0022h intrq3 (pin 35) irq5 0003h intrq0 (pin 32) irq10 0000h intrq1 (pin 31) irq11 0001h intrq2 (pin 30) irq12 0002h table 2. interrupt assignments
ds271f5 19 cs8900a crystal lan? ethernet controller cirrus logic product datasheet memory. the cs8900a has three pairs of dma pins that can be conn ected directly to the three 16-bit dma channel s of the isa bus. only one dma channel is used at a time. it is selected during initiali zation by writing the number of the desired c hannel (0, 1 or 2) into packetpage memory base + 0024h. unused dma pins are placed in a high-impedance state. the selected dma request pin goes high when the cs8900a has received frames to transfer to the host memory via dma. if the dmaburst bit (register 17, busctl, bit b) is clear, the pin goes low after the dma operation is complete. if the dmabur st bit is set, the pin goes low 32 s after the start of a dma trans- fer. the dma pin pairs are arranged on the cs8900a to facilitat e board layout. crystal recommends the confi guration in table 3 when connecting these pins to the isa bus. for a description of dma mode, see section 5.3 on page 90. 3.3 reset and initialization 3.3.1 reset seven different conditions cause the cs8900a to reset its inte rnal registers and cir- cuits. 3.3.1.1 external re set, or isa reset there is a chip-wide reset whenever the re- set pin is high for at least 400 ns. during a chip-wide reset, all ci rcuitry and registers in the cs8900a are reset. 3.3.1.2 power-up reset when power is applied, the cs8900a main- tains reset until the voltage at the supply pins reaches approximately 2.5 v. the cs8900a comes out of reset once vcc is greater than approximately 2.5 v and the crystal oscillator has stabilized. 3.3.1.3 power-down reset if the supply voltage dr ops below approximate- ly 2.5 v, there is a chip-wide reset. the cs8900a comes out of reset once the power supply returns to a level greater than approxi- mately 2.5 v and the crystal oscillator has sta- bilized. 3.3.1.4 eeprom reset there is a chip-wi de reset if an eeprom checksum error is detected (see section 3.4 on page 21). 3.3.1.5 software initiated reset there is a chip-wide reset whenever the re- set bit (register 15, se lfctl, bit 6) is set. 3.3.1.6 hardware (h w) standby or suspend the cs8900a goes though a chip-wide reset whenever it enters or exits either hw standby mode or hw suspend mo de (see section 3.7 on page 27 for more information about hw standby and suspend). 3.3.1.7 software (sw) suspend whenever the cs8900a enters sw suspend mode, all registers and circuits are reset ex- cept for the isa i/o base address register (lo- cated at packetpage base + 0020h) and the selfctl register (regi ster 15). upon exit, there is a chip-wide reset (see section 3.7 on page 27 for more information about sw sus- pend). cs8900a dma signal (pin #) isa dma signal packetpage base + 0024h dmarq0 (pin 15) drq5 0000h dmack0 (pin 16) dack5 dmarq1 (pin 13) drq6 0001h dmack1 (pin 14) dack6 dmarq2 (pin 11) drq7 0002h dmack2 (pin 12) dack7 table 3. dma assignments
20 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 3.3.2 allowing time for reset operation after a reset, the cs 8900a goes through a self configuration. this incl udes calibrating on-chip analog circuitry, and r eading eeprom for va- lidity and configuration. time required for the reset calibration is ty pically 10 ms. software drivers should not access registers internal to the cs8900a during this time. when calibra- tion is done, bit initd in the self status regis- ter (register 16) is set indicating that initialization is comple te, and the sibusy bit in the same register is cleared indicating the ee- prom is no longer being read or pro- grammed. 3.3.3 bus reset considerations after reset, the cs8 900a packet page pointer register (iobase+0ah) is set to 3000h. the 3000h value can be us ed as part of the cs8900a signature when the system scans for the cs8900a. see section 4.10 on page 75. after a reset, the isa bus outputs intrx and dmarqx are 3-stated, thus avoiding any in- terrupt or dma channel conflicts on the isa bus at power-up time. 3.3.4 initialization after each reset (except eeprom reset), the cs8900a checks the sense of the eedatain pin to see if an exter nal eeprom is present. if eedi is high, an eeprom is present and the cs8900a automatically loads the configura- tion data stored in the eeprom into its inter- nal registers (see next se ction). if eedi is low, an eeprom is not pr esent and the cs8900a comes out of reset with the default configura- tion shown in table 4. a low-cost serial eeprom can be used to store configuration inform ation that is automat- ically loaded into the cs8900a after each re- set (except eeprom reset). the use of an eeprom is optional. the cs8900a operates with any of six stan- dard eeprom?s shown in table 5.
ds271f5 21 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 3.4 configurations with eeprom 3.4.1 eeprom interface the interface to the eeprom consists of the four signals shown in table 6. 3.4.2 eeprom memory organization if an eeprom is used to store initial configu- ration information for the cs8900a, the ee- prom is organized in one or more blocks of 16-bit words. the first block in eeprom, re- ferred to as the configur ation block, is used to configure the cs8900a af ter reset. an exam- ple of a typical configuration block is shown in table 7. additional blo cks containing user data may be stored in the e eprom. however, the configuration block must always start at ad- dress 00h and be stored in contiguous memo- ry locations. 3.4.3 reset configuration block the first block in eeprom, referred to as the reset configuration block, is used to automat- ically program the cs8900a with an initial con- figuration after a reset. additional user data may also be stored in th e eeprom if space is available. the additional data are stored as 16-bit words and can occupy any eeprom address space beginning immediately after the end of the reset c onfiguration block up to address 7fh, depending on eeprom size. this additional data can only be accessed through software contro l (refer to section 3.5 on page 25 for more info rmation on accessing packetpage address register contents register descriptions 0020h 0300h i/o base address* 0022h xxxx xxxx xxxx x100 interrupt number 0024h xxxx xxxx xxxx xx11 dma channel 0026h 0000h dma start of frame offset 0028h x000h dma frame count 002ah 0000h dma byte count 002ch xxx0 0000h memory base address 0030h xxx0 0000h boot prom base address 0034h xxx0 0000h boot prom address mask 0102h 0003h register 3 - rxcfg 0104h 0005h register 5 - rxctl 0106h 0007h register 7 - txcfg 0108h 0009h register 9 - txcmd 010ah 000bh register b - bufcfg 010ch undefined reserved 010eh undefined reserved 0110h undefined reserved 0112h 00013h register 13 - linectl 0114h 0015h register 15 - selfctl 0116h 0017h register 17 - busctl 0118h 0019h register 19 - testctl * i/o base address is unaffected by software suspend mode. table 4. d efault configuration eeprom type size (16-bit words) ?c46 (non-sequential) 64 ?cs46 (sequential) 64 ?c56 (non-sequential) 128 ?cs56 (sequential) 128 ?c66 (non-sequential) 256 ?cs66 (sequential) 256 table 5. suppor ted eeprom types cs8900a pin (pin #) cs8900a function eeprom pin eecs (pin 3) eeprom chip select chip select eesk (pin 4) 1 mhz eeprom serial clock output clock eedo (pin 5) eeprom data out (data to eeprom) data in eedi (pin 6) eeprom data in (data from eeprom) data out table 6. eeprom interface
22 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet the eeprom). address space 80h to afh is reserved. 3.4.3.1 reset configur ation block structure the reset configuration block is a block of contiguous 16-bit words starting at eeprom address 00h. it can be divi ded into three logi- cal sections: a header, one or more groups of configuration data word s, and a checksum val- ue. all of the words in the reset configuration block are read sequentia lly by the cs8900a after each reset, starti ng with the header and ending with the checksum. each group of con- figuration data is used to program a packet- page register (or set of packetpage registers in some cases) with an initial non-default val- ue. 3.4.3.2 reset confi guration block header the header (first word of the block located at eeprom address 00h) s pecifies the type of eeprom used, whether or not a reset con- figuration block is pres ent, and if so, how many word address value description first word in data block 00h a120h configuration block header. the high byte, a1h, indi cates a ?c46 eeprom is at tached. the link byte, 20h, indicates the number of bytes to be used in this block of configuration data. first group of words 01h 2020h group header for first group of words. three words to be loaded, beginning at 0020h in packetpage memory. 02h 0300h i/o base address 03h 0003h interrupt number 04h 0001h dma channel number second group of words 05h 502ch group header for second group of words. six words to be loaded, beginning at 002ch in packetpage memory. 06h e000h memory base address - low word 07h 000fh memory base address - high word 08h 0000h boot prom base address - low word 09h 000dh boot prom base address - high word 0ah c000h boot prom address mask - low word 0bh 000fh boot prom address mask - high word third group of words 0ch 2158h group header for third group of words. three words to be loaded, beginning at 0158 in packetpage memory. 0dh 0010h individual address - octet 0 and 1 0eh 0000h individual address - octet 2 and 3 0fh 0000h individual address - octet 4 and 5 checksum value 10h 2800h the high byte, 28h, is the checksum value. in this example, the checksum includes word addresses 00h through 0fh. the hexadecimal sum of the bytes is d8h, resulting in a 2?s comple ment of 28h. the low byte, 00h, pro- vides a pad to the word boundary. * ffffh is a special code indicating that there are no more words in the eeprom. table 7. eeprom config uration block example
ds271f5 23 cs8900a crystal lan? ethernet controller cirrus logic product datasheet bytes of configuration data are stored in the reset configuration block. 3.4.3.3 determin ing the eeprom type the lsb of the high by te of the header indi- cates the type of ee prom attached: sequen- tial or non-sequential. an lsb of 0 (xxxx- xxx0) indicates a s equential eeprom. an lsb of 1 (xxxx-xxx1) indicates a non-se- quential eeprom. the cs8900a works equally well with either type of eeprom. the cs8900a will automatic ally generate sequen- tial addresses while re ading the reset config- uration block if a non-sequential eeprom is used. 3.4.3.4 checking eeprom for presence of reset configuration block the read-out of either a binary 101x-xxx0 or 101x-xxx1 (x = do not care) from the high byte of the header indi cates the presence of configuration data. an y other readout value terminates initializati on from the eeprom. if an eeprom is attached but not used for con- figuration, crystal re commends that the high byte of the first word be programmed with 00h in order to ensure that the cs8900a w ill not at- tempt to read configur ation data from the ee- prom. 3.4.3.5 determining nu mber of bytes in the reset configuration block the low byte of the re set configuration block header is known as the link byte. the value of the link byte represent s the number of bytes of configuration data in the reset configura- tion block. the two bytes used for the header are excluded when calculating the link byte value. for example, a reset configuration block header of a104h indica tes a non-sequential eeprom programmed with a reset configu- ration block containing 4 bytes of configuration data. this reset configuration block occupies 6 bytes (3 words) of eeprom space (2 bytes for the header and 4 bytes of configuration da- ta). 3.4.4 groups of configuration data configuration data are arranged as groups of words. each group co ntains one or more words of data that are to be loaded into pack- etpage registers. the first word of each group is referred to as the group header. the group header indicates the nu mber of words in the group and the address of the packetpage reg- ister into which the first data word in the group is to be loaded. any remaining words in the group are stored in successive packetpage registers. 3.4.4.1 group header bits f through c of th e group header specify the number of words in each group that are to be transferred to pack etpage registers (see figure 4). this value is two less than the total number of words in th e group, including the group header. for example, if bits f through c contain 0001, there ar e three words in the group (a group header and two words of con- figuration data). 10 3 2 5 4 76 first word of a group of words 98 ba dc f e number of words in group 0 0 9-bit packetpage address 0 figure 4. group header
24 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet bits 8 through 0 of the group header specify a 9-bit packetpage addre ss. this address de- fines the packetpage regist er that will be load- ed with the first word of configuration data from the group. bits b t hough 9 of the group head- er are forced to 0, rest ricting the destination address range to the firs t 512 bytes of packet- page memory. figure 4 shows the format of the group header. 3.4.5 reset configuration block check- sum a checksum is stored in the high byte position of the word immediat ely following the last group of data in the re set configuration block. (the eeprom address of the checksum val- ue can be determined by dividing the value stored in the link byte by two). the checksum value is the 2?s complement of the 8-bit sum (any carry out of eighth bi t is ignored) of all the bytes in the reset conf iguration block, ex- cluding the checksum byte. this sum includes the reset configurati on block header at ad- dress 00h. since the checksum is calculated as the 2?s complement of the sum of all pre- ceding bytes in the reset configuration block, a total of 0 should re sult when the checksum value is added to the sum of the previous bytes. 3.4.6 eeprom example table 7 shows an example of a reset config- uration block stored in a c46 eeprom. note that little-endian word ordering is used, i.e., the least significant word of a multiword datum is located at the lowest address. 3.4.7 eeprom read-out if the eedi pin is a sserted high at the end of reset, the cs8900a reads the firs t word of ee- prom data by: 1) asserting eecs 2) clocking out a read- register-00h com- mand on eedo (eesk provides a 1mhz serial clock signal) 3) clocking the data in on eedi. if the eedi pin is low at the end of the reset sig- nal, the cs8900a does no t perform an ee- prom read-out (uses its default configuration). 3.4.7.1 determin ing eeprom size the cs8900a determines the size of the ee- prom by checking the sense of eedi on the tenth rising edge of eesk. if eedi is low, the eeprom is a ?c46 or ?c s46. if eedi is high, the eeprom is a ?c56, ?cs56, ?c66, or ?cs66. 3.4.7.2 loading configuration data the cs8900a reads in the first word from the eeprom to determine if configurat ion data is contained in the eepr om. if configuration data is not stored in the eeprom, the cs8900a terminates init ialization from ee- prom and operates using its default configu- ration (see table 4). if configuration data is stored in eeprom, the cs8900a automati- cally loads all configurat ion data stored in the reset configuration block into its internal packetpage registers. 3.4.8 eeprom read-out completion once all the configuration data are transferred to the appropriate packe tpage registers, the cs8900a performs a checksum calculation to verify the reset configur ation blocks data are valid. if the resulting to tal is 0, the read-out is considered valid. other wise, the cs8900a ini- tiates a partial reset to restore the default con- figuration. if the read-out is va lid, the eepromok bit (register 16, selfst, bi t a) is set. eepro- mok is cleared if a checksum error is detect- ed. in this case, the cs8900a performs a partial reset and is rest ored to its default. once
ds271f5 25 cs8900a crystal lan? ethernet controller cirrus logic product datasheet initialization is complete (configuration loaded from eeprom or rese t to default configura- tion) the initd bit is se t (register 16, selfst, bit 7). 3.5 programmi ng the eeprom after initialization, t he host can access the ee- prom through the cs8900a by writing one of seven commands to the eeprom command register (packetpage base + 0040h). figure 5 shows the format of the eeprom command register. 3.5.1 eeprom commands the seven commands used to access the ee- prom are: read, write, erase, erase/write enable, erase/write dis able, erase-all, and write-all. they are described in table 8. 3.5.2 eeprom command execution during the execution of a command, the two opcode bits, followed by the six bits of address (for a ?c46 or ?cs46) or eight bits of address f x e x d x c x b xelselop1op0 a98 ad5 ad4 54 76 ad7 ad6 10 32 ad1 ad0 ad3 ad2 ad5 - ad0 used with 'c46 and 'cs46 ad7 - ad0 used with 'c56, 'cs56, 'c66 and 'cs66 figure 5. eeprom command register format bit name description [f:b] reserved [a] elsel external logic select: when clear, th e eecs pin is used to select the eeprom. when set, the elcs pin is used to select the external la decode circuit. [9:8] op1, op0 opcode: indicates what comma nd is being executed (see next section). [7:0] ad7 to ad0 eeprom address: address of eepr om word being accessed. command opcode (bits 9,8) eeprom address (bits 7 to 0) data eeprom type execution time read register 1,0 word address yes all 25 s write register 0,1 word address yes all 10 ms erase register 1.1 word address no all 10 ms erase/write enable 0,0 x x11-xxxx no ?cs46, ?c46 9 s 11xx-xxxx no ?cs56, ?c56, ?cs66, ?c66 9 s erase/write disable 0,0 0,0 xx00-xxxx no ?cs46, ?c46 9 s 00xx-xxxx no ?cs56, ?c56, ?cs66, ?c66 9 s erase-all registers 0,0 0,0 xx10-xxxx no ?cs46, ?c46 10 ms 10xx-xxxx no ?cs56, ?c56, ?cs66, ?c66 9 s write-all register 0,0 0,0 xx01-xxxx yes ?cs46, ?c46 10 ms 01xx-xxxx yes ?cs56, ?c56, ?cs66, ?c66 10 ms table 8. eeprom commands
26 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet (for a ?c56, ?cs56, ?c66 or ?cs66), are shifted out of the cs8900a, into the eeprom. if the command is a write, t he data in the eeprom data register (packe tpage base + 0042h) fol- lows. if the command is a read, the data in the specified eeprom location is written into the eeprom data register. if the command is an erase or erase-all, no dat a is transferred to or from the eeprom data register. before issu- ing any command, the hos t must wait for the sibusy bit (register 16, selfst, bit 8) to clear. after each co mmand has been issued, the host must wait agai n for sibusy to clear. 3.5.3 enabling access to the eeprom the erase/write e nable command provides protection from accident al writes to the ee- prom. the host must write an erase/write enable command before it attempts to write to or erase any eeprom memory location. once the host has finished altering the con- tents of the eeprom , it must write an erase/write disable command to prevent un- wanted modification of the eeprom. 3.5.4 writing and erasing the eeprom to write data to the eeprom, the host must execute the following series of commands: 1) issue an erase/wr ite enable command . 2) load the data into t he eeprom data reg- ister. 3) issue a write command. 4) issue an erase/wr ite disable command. during the erase command, the cs8900a writes ffh to the spec ified eeprom location. during the erase-all command, the cs8900a writes ffh to all locations. 3.6 boot prom operation the cs8900a supports an optional boot prom used to store c ode for remote booting from a network server. 3.6.1 accessing the boot prom to retrieve the data st ored in the boot prom, the host issues a read command to the boot prom as a memory space access. the cs8900a decodes th e command and drives the csout pin low, causing the data stored in the boot prom to be shifted into the bus transceiver. the bus transceiver then drives the data out onto the isa bus. 3.6.2 configuring the cs8900a for boot prom operation figure 6 shows how the cs8900a should be connected to the boot prom and ?245 driver. to configure the cs8900a?s internal registers for boot prom operat ion, the boot prom base address must be loaded into the boot prom base address register (packetpage base + 0030h) and the boot prom address mask must be loaded into the bootprom ad- dress mask register (packetpage base + 0034h). the boot prom base address pro- vides the starting lo cation in host memory where the boot prom is mapped. the boot prom address mask indicates the size of the attached boot prom and is limited to 4-kbyte increments. the lower 12 bits of the address mask are ignored and shoul d be 000h. in the eeprom example shown in table 7, the boot prom starting address is d0000h oe dir b1 . . . b8 a1 . . . a8 74ls245 sd(0:7) isa bus sa(0:14) 27c256 ce oe 20 22 19 cs8900a csout (pin 17) figure 6. boot prom connection diagram
ds271f5 27 cs8900a crystal lan? ethernet controller cirrus logic product datasheet and the address mask is fc000h. this config- uration describes a 16 -kbyte (128 kbit) prom mapped into host me mory from d0000h to d3fffh. 3.7 low-power modes for power-sensitive applications, the cs8900a supports thre e low-power modes: hardware standby, hardware suspend, and software suspend. all three low-power modes are controlled throug h the selfctl register (register 15). see also section 4.4.4 on page 51. an internal reset occurs when the cs8900a comes out of any suspend or standby mode. after a reset (internal or external), the cs8900a goes through a self configuration. this includes calibrat ing on-chip analog cir- cuitry, and reading eeprom for validity and configuration. when the ca libration is done, bit initd in register 16 (self status register) is set indicating that initiali zation is complete, and the sibusy bit in the same regi ster is cleared (indicating that the eeprom is no longer be- ing read or programmed. time required for the reset calibration is ty pically 10 ms. software drivers should not access registers internal to cs8900a during this time. 3.7.1 hardware standby hardware (hw) standby is designed for use in systems, such as port able pc?s, that may be temporarily disconnect ed from the 10base-t cable. it allows the system to conserve power while the lan is not in use, and then automat- ically restore ethernet operation once the ca- ble is reconnected. in hw standby mode, all analog and digital cir- cuitry in the cs8900a is turned off, except for the 10base-t receiver which remains active to listen for link activity . if link activity is detect- ed, the lanled pin is driven low, providing an indication to the host t hat the network connec- tion is active. the host can then activate the cs8900a by deasse rting the sleep pin. dur- ing this mode, all isa bus accesses are ig- nored. to enter hw standby mode, the sleep pin must be low and the hwsleepe bit (register 15, selfctl, bit 9) and the hwstandbye bit (register 15, selfctl, bit a) must be set. when the cs8900a enters hw standby, all registers and circuits ar e reset except for the selfctl register. upon ex it from hw standby, the cs8900a performs a complete reset, and then goes through normal initialization. 3.7.2 hardware suspend during hardware suspend mode, the cs8900a uses the least amount of current of the three low-power modes. all internal circuits are turned off and the cs 8900a?s core is elec- tronically isolated from the rest of the system. accesses from the isa bu s and ethernet activ- ity are both ignored. hw suspend mode is entered by driving the sleep pin low and setti ng the hwsleepe bit (register 15, selfctl, bit 9) while the hw- standbye bit (register 15 , selfctl, bit a) is clear. to exit from this mode, the sleep pin must be driven high. u pon exit, the cs8900a performs a complete reset, and then goes through a normal init ialization procedure. 3.7.3 software suspend software (sw) suspend mode can be used to conserve power in appl ications, like adapter cards, that do not ha ve power management circuitry available. duri ng this mode, all inter- nal circuits are shut off except the i/o base ad- dress register (packetpage base + 0020h) and the selfctl regist er (register 15). to enter sw suspend mode, the host must set the swsuspend bit (regis ter 15, selfctl, bit
28 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 8). to exit sw suspend, the host must write to the cs8900a?s assigned i/o space (the write is only used to wake the cs8900a, the write itself is ignored). upon exit, the cs8900a per- forms a complete rese t, and then goes through a normal initialization procedure. any hardware reset takes the chip out of any sleep mode. table 9 summarizes the operation of the three low-power modes. cs8900a configuration cs8900a operation sleep (pin 77) hwstandbye (selfctl, bit a) hwsleepe (selfctl, bit 9) swsuspend (selfctl, bit 8) link activity low 1 1 n/a not present hw standby mode: 10base-t receiver listens for link activity low 1 1 n/a present hw standby mode: lanled low low 0 1 n/a n/a hw suspend mode low to high n/a 1 0 n/a cs8900a resets and goes through initialization high n/a n/a 0 n/a not in low-power mode high n/a n/a n/a sw suspend mode low n/a 0 1 n/a sw suspend mode low n/a 0 0 n/a not in low-power mode notes: 1. both hw and hw suspend take precedence over sw suspend. table 9. low-power mode operation
ds271f5 29 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 3.8 led outputs the cs8900a provides th ree output pins that can be used to control le ds or external logic. 3.8.1 lanled lanled goes low whenever the cs8900a transmits or receives a frame, or when it de- tects a collision. lanled remains low until there has been no activity for 6 ms (i.e. each transmission, reception, or collision produces a pulse lasting a minimum of 6 ms). 3.8.2 linkled or hc0 linkled or hc0 can be controlled by either the cs8900a or the host. when controlled by the cs8900a, linkled is low whenever the cs8900a receives vali d 10base-t link puls- es. to configure this pin for cs8900a control, the hc0e bit (register 15, selfctl, bit c) must be clear. when controlled by the host, linkled is low whenever the hcb0 bit (reg- ister 15, selfctl, bit e) is set. to configure it for host control, the hc0e bit must be set. ta- ble 10 summarizes this operation. 3.8.3 bstatus or hc1 bstatus or hc1 can be controlled by either the cs8900a or the host. when controlled by the cs8900a, bstatus is low whenever the host reads the rxevent register (packetpage base + 0124h), signaling t he transfer of a re- ceive frame across the isa bus. to configure this pin for cs8900a c ontrol, the hc1e bit (register 15, selfctl, bit d) must be clear. when controlled by the host, bstatus is low whenever the hcb1 bit (register 15, selfctl, bit f) is set. to configure it for host control, hc1e must be set. tabl e 11 summarizes this operation. 3.8.4 led connection each led output is c apable of sinking 10 ma to drive an led directly through a series resis- tor. the output voltage of each pin is less than 0.4 v when the pin is low. figure 7 shows a typical led circui t. 3.9 media access control 3.9.1 overview the cs8900a?s ethernet media access con- trol (mac) engine is full y compliant with the ieee 802.3 ethernet sta ndard (iso/iec 8802- 3, 1993). it handles all aspects of ethernet frame transmission and reception, including: hc0e (bit c) hcb0 (bit e) pin function 0n/a pin configured as linkled : output is low when valid 10 base-t link pulses are detected. output is high if valid link pulses are not detected 10 pin configured as hc0 : output is high 11 pin configured as hc0 : output is low table 10. linkled /hc0 pin operation hc1e (bit d) hcb1 (bit f) pin function 0n/a pin configured as bstatus : output is low when a receive frame begins trans- fer across the isa bus. output is high otherwise 10 pin configured as hc1 : output is high 11 pin configured as hc1 : output is low table 11. bstatus /hci pin operation +5v lanled linkled figure 7. led connection diagram
30 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet collision detection, preamble generation and detection, and crc gener ation and test. pro- grammable mac features include automatic retransmission on col lision, and padding of transmitted frames. figure 8 shows how the mac engine interfac- es to other cs8900a f unctions. on the host side, it interfaces to the cs8900a?s internal data/address/control bus. on the network side, it interfaces to the internal manchester encoder/decoder (endec). the primary func- tions of the mac are: frame encapsulation and decapsulation; error detection and handling; and, media access ma nagement. 3.9.2 frame encaps ulation and decapsu- lation the cs8900a?s mac engine automatically as- sembles transmit packets and disassembles receive packets. it also determines if transmit and receive frames are of legal minimum size. 3.9.2.1 transmission once the proper number of bytes have been transferred to the cs8900a ?s memory (either 5, 381, 1021 bytes, or full frame), and provid- ing that access to the ne twork is permitted, the mac automatically tran smits the 7-byte pre- amble (1010101b...) , followed by the start-of- frame delimiter (s fd, 10101011b), and then the serialized frame data. it then transmits the frame check sequence (f cs). the data after the sfd and before the fcs (destination ad- dress, source address, length, and data field) is supplied by the host. fcs generation by the cs8900a may be disabled by setting the in- hibitcrc bit (register 9, txcmd, bit c). figure 9 shows the ether net frame format. 3.9.2.2 reception the mac receives the in coming packet as a serial stream of nrz data from the manches- ter encoder/decoder. it begi ns by checking for the sfd. once the sfd is detected, the mac assumes all subsequent bi ts are frame data. it reads the da and compar es it to the criteria programmed into the address filter (see section 5.2.10 on page 87 for a description of address filtering). if the da passes the ad- dress filter, the fram e is loaded into the cs8900a?s memory. if the buffercrc bit (register 3, rxcfg, bit b) is set, the received fcs is also loaded into memory. once the en- 802.3 mac engine encoder/ decoder & pll led logic cs8900a internal bus 10base-t & aui figure 8. mac interface 1 byte up to 7 bytes 6 bytes 6 bytes 2 bytes llc data pad fcs 4 bytes preamble frame length min 64 bytes max 1518 bytes alternating 1s / 0s sfd da sa sfd = start of frame delimiter da = destination address sa = source address direction of transmission frame packet llc = logical link control fcs = frame check sequence (also called cyclic redundancy check, or crc) length field figure 9. ethernet frame format
ds271f5 31 cs8900a crystal lan? ethernet controller cirrus logic product datasheet tire packet has been received, the mac vali- dates the fcs. if an er ror is detected, the crcerror bit (register 4, rxevent, bit c) is set. 3.9.2.3 enforcing minimum frame size the mac provides minimum frame size en- forcement of both tr ansmit and receive pack- ets. when the txpadd is bit (register 9, txcmd, bit d) is clear, transmit fram es will be padded with ad- ditional bits to ensure that the receiving station receives a legal fram e (64 bytes, including crc). when txpaddis is set, the cs8900a will not add pad bits and will transmit frames less that 64 bytes. if a frame is received that is less than 64 bytes (inc luding crc), the runt bit (register 4, rxevent, bit d) will be set indi- cating the arrival of an illegal frame. 3.9.3 transmit error detection and han- dling the mac engine monitors ethernet activity and reports and recovers from a number of er- ror conditions. for trans mission, the mac re- ports the following er rors in the txevent register (register 8) and bufevent register (register c): 3.9.3.1 loss of carrier whenever the cs8900a is transmitting on the aui port, it expects to see its own transmission ?looped back? to its receiv er. if it is unable to monitor its transmission after the end of the preamble, the mac reports a loss-of-carrier error by setting the loss-of-crs bit (register 8, txevent, bit 6). if the loss-of-crsie bit (register 7, txcfg, bit 6) is set, the host will be interrupted. 3.9.3.2 sqe error after the end of trans mission on the aui port, the mac expects to see a collision within 64 bit times. if no collision is detected, the sqeerror bit (register 8, txevent, bit 7) is set. if the sqeerrorie bit is set (r egister 7, txcfg, bit 7), the host is interrupted. an sqe error may indicate a fault on the aui cable or a faulty transceiver (it is assu med that the attached transceiver supports this function). 3.9.3.3 out-of-window (late) collision if a collision is detecte d after the first 512 bits have been transmitted, t he mac reports a late collision by setting the out-of-window bit (reg- ister 8, txevent, bit 9). the mac then forces a bad crc and terminates the transmission. if the out-of-windowie bi t (register 7, txcfg, bit 9) is set, the host is interrupted. a late col- lision may indicate an illegal network configu- ration. 3.9.3.4 jabber error if a transmission conti nues longer than about 26 ms, the mac disables the transmitter and sets the jabber bit (regist er 8, txevent, bit a). the output of the transmitter returns to idle and remains there until th e host issues a new transmit command. if t he jabberie bit (regis- ter 7, txcfg, bit a) is set, the host is interrupt- ed. a jabber condition indicates that there may be something wro ng with the cs8900a transmit function. to pr event possible network faults, the host should clear the transmit buf- fer. possible options include: reset the chip with eit her software or hard- ware reset (see section 3.3 on page 19). issue a force transmit command by setting the force bit (registe r 9, txcmd, bit 8). issue a transmit comma nd with the txlength field set to zero. 3.9.3.5 transmit collision the mac counts the number of times an indi- vidual packet must be retransmitted due to
32 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet network collisions. t he collision count is stored in bits b through e of the txevent reg- ister (register 8). if the packet collides 16 times, transmission of t hat packet is terminat- ed and the 16coll bit (regi ster 8, txevent, bit f) is set. if the 16collie bit (register 7, txcfg, bit f) is set, the host will be interrupted on the 16th collision. a running count of transmit col- lisions is recorded in the txcol register. 3.9.3.6 transmit underrun if the cs8900a starts tr ansmission of a packet but runs out of data bef ore reaching the end of frame, the txunderrun bi t (register c, bufe- vent, bit 9) is set. t he mac then forces a bad crc and terminates t he transmission. if the txunderrunie bit (regist er b, bufcfg, bit 9) is set, the host is interrupted. 3.9.4 receive error detection and han- dling the following receive erro rs are reported in the rxevent register (register 4): 3.9.4.1 crc error if a frame is receiv ed with a bad crc, the crcerror bit (register 4, rxevent, bit c) is set. if the crcerrora bit (register 5, rxctl, bit c) is set, the fr ame will be buffered by cs8900a. if the crcerrorie bit (register 3, rxcfg. bit c) is set, the host is interrupted. 3.9.4.2 runt frame if a frame is received t hat is shorter than 64 bytes, the runt bit (register 4, rxevent, bit d) is set. if the runta bit (register 5, rxctl, bit d) is set, the frame will still be buffered by cs8900a. if the runtie bit (register 3, rx- cfg. bit d) is set, the host is interrupted. 3.9.4.3 extra data if a frame is received th at is longer than 1518 bytes, the extradata bit (register 4, rxevent, bit e) is set. if the ex tradataa bit (register 5, rxctl, bit e) is set, the first 1518 bytes of the frame will still be buff ered by cs8900a. if the extradataie bit (register 3, rxcfg. bit e) is set, the host is interrupted. 3.9.4.4 dribble bits and alignment error under normal operating conditions, the mac may detect up to 7 additi onal bits after the last full byte of a receive packet. these bits, known as dribble bits, are ignor ed. if dribble bits are detected, the dribblebit bit (register 4, rx- event, bit 7) is set. if both the dribblebits bit and crcerror bit (regist er 4, rxevent, bit c) are set at the same ti me, an alignment error has occurred. 3.9.5 media access management the ethernet network topology is a single shared medium with seve ral attached stations. the ethernet protocol is designed to allow each station equal acce ss to the network at any given time. any node can attempt to gain access to the network by first completing a de- ferral process (descri bed below) after the last network activity, and then transmitting a pack- et that will be received by all other stations. if two nodes transmit simult aneously, a collision occurs and the colliding packets are corrupted. two primary tasks of the mac are to avoid net- work collisions, and then recover from them when they occur. in addition, when the cs8900a is using the aui, the mac must sup- port the sqe test func tion described in sec- tion 7.2.4.6 of the ethernet standard. 3.9.5.1 collision avoidance the mac continually moni tors network traffic by checking for the presen ce of carrier activity (carrier activity is indi cated by the assertion of the internal carrier sense signal generated by the endec). if carrier ac tivity is detected, the network is assumed busy and the mac must wait until the current pa cket is finished before
ds271f5 33 cs8900a crystal lan? ethernet controller cirrus logic product datasheet attempting transmission. the cs8900a sup- ports two schemes for determining when to ini- tiate transmission: tw o-part deferral, and simple deferral. selection of the deferral scheme is determined by the 2-partdefdis bit (register 13, linectl, bi t d). if the 2-partdef- dis bit is clear, the ma c uses a two-part defer- ral process defined in se ction 4.2.3.2.1 of the ethernet standard (iso /iec 8802-3, 1993). if the 2-partdefdis bit is set, the mac uses a simplified deferral scheme. both schemes are described below: 3.9.5.2 two-part deferral in the two-part deferral pr ocess, the 9.6 s in- ter packet gap (ipg) ti mer is started whenev- er the internal carr ier sense signal is deasserted. if activity is detected during the first 6.4 s of the ipg ti mer, the timer is reset and then restarted once the activity has stopped. if there is no ac tivity during the first 6.4 s of the ipg timer, the ipg timer is al- lowed to time out (even if network activity is detected during the final 3.2 s). the mac then begins transmission if a transmit packet is ready and if it is not in backoff (backoff is de- scribed later in this section). if no transmit packet is pending, the mac continues to mon- itor the network. if acti vity is detected before a transmit frame is ready, the mac defers to the transmitting station a nd resumes monitoring the network. the two-part deferral scheme was developed to prevent the possibi lity of the ipg being shortened due to a tem porary loss of carrier. figure 10 diagrams the two-part deferral pro- cess. 3.9.5.3 simple deferral in the simple deferral scheme, the ipg timer is started whenever carrie r sense is deasserted. once the ipg timer is finished (after 9.6 s), if a transmit frame is pending and if the mac is not in backoff, transmission begins the 9.6 s ipg). if no transmit packet is pending, the mac continues to monito r the network. if activ- ity is detected before a transmit frame is ready, the mac defers to the transmitting station and resumes monitoring the network. figure 11 di- agrams the simple deferra l process. transmit frame start monitoring network activity ipg timer = 6.4 s? network active? network active? start ipg timer network active? yes no yes yes yes no no no no wait 3.2 s yes tx frame ready and not in backoff? figure 10. two-part deferral
34 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 3.9.5.4 collision resolution if a collision is detec ted while the cs8900a is transmitting, the mac re sponds in one of three ways depending on whether it is a normal col- lision (within the first 512 bits of transmission) or a late collision (after the first 512 bits of transmission): 3.9.5.5 normal collisions if a collision is detect ed before the end of the preamble and sfd, the mac finishes the pre- amble and sfd, transmi ts the jam sequence (32-bit pattern of all 0?s), and then initiates backoff. if a collision is detected after the transmission of the pr eamble and sfd but be- fore 512 bit times, t he mac immediately termi- nates transmission, transmits the jam sequence, and then initia tes backoff. in either case, if the onecoll bit (register 9, txcmd, bit 9) is clear, the mac wi ll attempt to transmit a packet a total of 16 time s (the initial attempt plus 15 retransmissions ) due to normal colli- sions. on the 16th collision, it sets the 16coll bit (register 8, txevent , bit f) and discards the packet. if the onecol l bit is set, the mac discards the packet without attempting any re- transmission. 3.9.5.6 late collisions if a collision is detect ed after the first 512 bits have been transmitted, the mac immediately terminates transmission, transmits the jam se- quence, discards the packe t, and sets the out- of-window bit (register 8, txevent, bit 9). the cs8900a does not initiate backoff or attempt to retransmit the frame. for additional informa- tion about late collisions, see out-of-window error in this section. 3.9.5.7 backoff after the mac has comple ted transmitting the jam sequence, it must wa it, or ?back off?, be- fore attempting to trans mit again. the amount of time it must wait is determined by one of two backoff algorithms: the standard backoff algo- rithm (iso/iec 4.2.3.2. 5) or the modified backoff algorithm. the hos t selects which al- gorithm through the modb ackoffe bit (register 13, linectl, bit b). 3.9.5.8 standard backoff the standard backoff algorithm, also called the ?truncated binary exponential backoff?, is described by the equation: 0 r 2 k where r (a random int eger) is the number of slot times the mac must wait (1 slot time = 512 t x fra m e ready and not i n b ac k off? transmit frame start monitoring network activity network active? network active? yes no yes no no yes wait 9.6 s figure 11. simple deferral
ds271f5 35 cs8900a crystal lan? ethernet controller cirrus logic product datasheet bit times), and k is the sm aller of n or 10, where n is the number of re transmission attempts. 3.9.5.9 modified backoff the modified backoff is described by the equation: 0 r 2 k where r (a random in teger) is the number of slot times the mac must wait, and k is 3 for n < 3 and k is the smalle r of n or 10 for n 3, where n is the number of retransmission at- tempts. the advantage of the modified backoff algo- rithm over the standar d backoff algorithm is that it reduces the possi bility of mult iple colli- sions on the first three retries. the disadvan- tage is that it extends the maximum time needed to gain access to the network for the first three retries. the host may choose to disable the backoff al- gorithm altogether by setting the disableback- off bit (register 19, testctl, bit b). when disabled, the cs8900a on ly waits the 9.6 s ipg time before star ting transmission. 3.9.5.10 sqe test if the cs8900a is trans mitting on the aui, the external transceiver should generate an sqe test signal on the ci+/ci- pair following each transmission. the sqe te st is a 10 mhz sig- nal lasting 5 to 15 bit times and starting within 0.6 to 1.6 s after t he end of transmission. during this period, the cs8900a ignores re- ceive carrier activity (see sqe error in this section for more information). 3.10 encoder/ decoder (endec) the cs8900a?s integrated encoder/decoder (endec) circuit is comp liant with the relevant portions of section 7 of the ethernet standard (iso/iec 8802-3, 1993). its primary functions include: manchester encodi ng of transmit da- ta; informing the mac when valid receive data is present (carrier de tection); and, recovering the clock and nrz data from incoming man- chester-encoded data. figure 12 provides a block diagram of the en- dec and how it interfaces to the mac, aui and 10base-t transceiver. 3.10.1 encoder the encoder converts nr z data from the mac and a 20 mhz transmit clock signal into a se- rial stream of manchester data. the transmit clock is produced by an on-chip oscillator cir- cuit that is driven by either an external 20 mhz quartz crystal or a ttl-level cmos clock in- put. if a cmos input is used, the clock should be 20 mhz 0.01% with a duty cycle between encoder carrier detector decoder & pll rx mux tx mux rxsql auisql rx tx auirx auitx auicol clock carrier sense rx clk rx nrz txclk tx nrz ten port select collision mac endec 10base-t transceiver aui figure 12. endec
36 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 40% and 60%. the specifications for the crys- tal are described in section 7.7 on page 122. the encoded signal is ro uted to either the 10base-t transceiver or aui, depending on configuration. 3.10.2 carrier detection the internal carrier detection circuit informs the mac that valid rece ive data is present by asserting the internal carrier sense signal as soon it detects a vali d bit pattern (1010b or 0101b for 10base-t, and 1b or 0b for aui). during normal packet rece ption, carrier sense remains asserted while the frame is being re- ceived, and is deassert ed 1.3 to 2.3 bit times after the last low-to-hig h transition of the end- of-frame (eof) sequenc e. whenever the re- ceiver is idle (no receive activity), carrier sense is deasserted. the crs bit (register 14, linest, bit e) reports the state of the car- rier sense signal. 3.10.3 clock and data recovery when the receiver is idle, the phase-lock loop (pll) is locked to the in ternal clock signal. the assertion of the carrier sense signal interrupts the pll. when it rest arts, it locks on the in- coming data. the receiv e clock is then com- pared to the incomi ng data at the bit cell center and any phase difference is corrected. the pll remains locked as l ong as the receiver in- put signal is valid. on ce the pll has locked on the incoming data, t he endec converts the manchester data to nrz and passes the de- coded data and the recovered clock to the mac for further processing. 3.10.4 interface selection physical interface sele ction is determined by auionly bit (bit 8) and the autoaui/10bt (bit 9) in the linectl regist er (register 13). table 12 describes the possible configurations. 3.10.4.1 10base-t only when configured for 10base-t only opera- tion, the 10base-t tran sceiver and its inter- face to the endec are active, and the aui is powered down. 3.10.4.2 aui only when configured for aui- only operation, the aui and its interface to the endec are active, and the 10base-t transce iver is powered down. 3.10.4.3 auto-select in auto-select mode, the cs8900a automati- cally selects the 10base -t interface and pow- ers down the aui if valid packets or link pulses are detected by the 10b ase-t receiver. if val- id packets and link pulse s are not detected, the cs8900a selects the au i. whenever the aui is selected, the 10base -t receiver remains active to listen for li nk pulses or packets. if 10base-t activity is detected, the cs8900a switches back to 10base-t. 3.11 10base-t transceiver the cs8900a includes an integrated 10base-t transceiver t hat is compliant with the relevant portions of section 14 of the ether- net standard (iso/iec 8802-3, 1993). it in- cludes all analog and digital circuitry needed to interface the cs8900a dire ctly to a simple iso- lation transformer (see section 7.5 on page 121 for a connection diagram). figure 13 provides a block diagram of the 10base-t transceiver. auionly (bit 8) autoaui/10bt (bit 9) physical interface 0 0 10base-t only 1 n/a aui only 01auto-select table 12. interface selection
ds271f5 37 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 3.11.1 10base-t filters the cs8900a?s 10base-t transceiver in- cludes integrated low- pass transmit and re- ceive filters, eliminat ing the need for external filters or a filter/transfo rmer hybrid. on-chip fil- ters are gm/c implemen tations of fifth-order butterworth low-pass filter s. internal tuning cir- cuits keep the gm/c ratio tightly controlled, even when large temperature, supply, and ic process variations o ccur. the nominal 3 db cutoff frequency of the filters is 16 mhz, and the nominal att enuation at 30 mhz (3rd har- monic) is -27 db. 3.11.2 transmitter when configured for 10base-t operation, manchester encoded data from the endec is fed into the trans mitter?s predis tortion circuit where initial wave shaping and preequaliza- tion is performed. the output of the predistor- tion circuit is fed into the transmit filter where final wave shaping occurs and unwanted noise is removed. the signal then passes to the dif- ferential driver where it is amplified and driven out of the txd+/txd- pins. in the absence of transmit packets, the trans- mitter generates link pulses in accordance with section 14.2.1.1. of the ethernet standard. transmitted link pulses are positive pulses, one bit time wide, typica lly generated at a rate of one every 16 ms. t he 16 ms timer starts whenever the transmit ter completes an end- of-frame (eof) sequenc e. thus, there is a link pulse 16 ms afte r an eof unless there is another transmitted packet. figure 14 dia- grams the operation of the link pulse genera- tor. if no link pulses are being received on the re- ceiver, the 10base-t tran smitter is internally forced to an inactive state unless bit disablelt in register 19 (test c ontrol register) is set to one. 3.11.3 receiver the 10base-t receive section consists of the receive filter, squelch circ uit, polarity detection and correction circuit, and link pulse detector. 3.11.3.1 squelch circuit the 10base-t squelch circuit determines when valid data is present on the rxd+/rxd- pair. incoming signals passing through the re- ceive filter are tested by the squelch circuit. any signal with amplitude less than the rxsql rx tx link pulse detector tx pre- distortion rx squelch rx comparator tx filters filter tuning rx filters tx drivers rxd- rxd+ txd- txd+ endec linkok (to mac) 10base-t transceiver figure 13. 10base-t transceiver
38 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet squelch threshold (eit her positive or negative, depending on polarity) is rejected. 3.11.3.2 extended range the cs8900a suppor ts an extended range feature that reduces the 10base-t receive squelch threshold by a pproximately 6 db. this allows the cs8900a to operate with 10base- t cables that are longer than 100 meters (100 meters is the maximum length specified by the ethernet standard). the exact additional dis- tance depends on the qua lity of the cable and the amount of electrom agnetic noise in the surrounding environment. to activate this fea- ture, the host must set the lorxsquelch bit (register 13, li nectl, bit e). 3.11.4 link pulse detection to prevent disruption of network operation due to a faulty link segment , the cs8900a continu- ally monitors the 10base-t receive pair (rxd+/ rxd-) for packets and link pulses. af- ter each packet or link pu lse is received, an in- ternal link-loss timer is started. as long as a packet or link pulse is received before the link- loss timer finishes (between 25 and 150 ms), the cs8900a maintains normal operation. if no receive activity is detected, the cs8900a disables packet transmis sion to prevent ?blind? transmissions onto the network (link pulses are still sent while packet transmission is dis- abled). to reactivate transmission, the receiv- er must detect a single packet (the packet itself is ignored), or two link pulses separated by more than 2 to 7 ms an d no more than 25 to 150 ms (see section 7.4 on page 114 for 10base-t timing). the state of the link se gment is reported in the linkok bit (register 14, linest, bit 7). if the hc0e bit (register 15, se lfctl, bit d) is clear, it is also indicated by the output of the lin- kled pin. if the link is ?good?, the linkok bit is set and the linkled pin is driven low. if the link is ?bad? the linkok bit is clear and the lin- kled pin is high. to dis able this feature, the host must set the disabl elt bit (register 19, testctl, bit 7). if disablelt is set, the cs8900a will transmit and receive packets in- dependent of the link segment. 3.11.5 receive polarity detection and cor- rection the cs8900a automatically checks the polar- ity of the receive half of the twisted pair cable. if the polarity is corre ct, the polarityok bit (register 14, linest, bit c) is set. if the polar- ity is reversed, the polari tyok bit is clear. if the polaritydis bit (register 13, linectl, bit c) is clear, the cs8900a automatically corrects a reversal. if the polari tydis bit is set, the cs8900a does not correct a reversal. the po- larityok bit and the polaritydis bit are inde- pendent. to detect a reversed pair, the receiver exam- ines received link pulses and the end-of- frame (eof) sequence of incoming packets. if it detects at least one reversed link pulse and time link pulse link pulse 16ms 16ms less than 16ms packet packet figure 14. link pulse transmission
ds271f5 39 cs8900a crystal lan? ethernet controller cirrus logic product datasheet at least four frames in a row with negative po- larity after the eof, the receive pair is consid- ered reversed. any dat a received before the correction of the reversal is ignored. 3.11.6 collision detection if half-duplex operatio n is selected (register 19, bit e, fdx), the cs8900a detects a 10base-t collision whenev er the receiver and transmitter are active simultaneously. when a collision is present, the collision detection cir- cuit informs the mac by asserting the internal collision signal (s ee section 3.9 on page 29 for collision handling). 3.12 attachment un it interface (aui) the cs8900a attachment unit interface (aui) provides a direct in terface to external 10base2, 10base5, and 10base-fl ether- net transceivers. it is fully compliant with sec- tion 7 of the ethernet standard (iso/iec 8802- 3), and as such, is capabl e of driving a full 50- meter aui cable. the aui consists of thr ee pairs of signals: data out (do+/do-), data in (di+/di-), and colli- sion in (ci+/ci-). to se lect the aui, the host should set the aui bit (register 13, linectl, bit 8). the aui can also be selected automati- cally as described in the previous section (section 3.10.4 on page 36). figure 15 pro- vides a block diagram of the aui. (for a con- nection diagram, see section 7.6 on page 122). 3.12.1 aui transmitter the aui transmitter is a differential driver de- signed to drive a 78 cable. it accepts data from the endec and transmits it directly on the do+/do- pins. after transmission has started, the cs8900a ex pects to see the pack- et ?looped-back? (or ec hoed) to the receiver, causing the carrier sens e signal to be assert- ed. this carrier sense presence indicates that the transmit signal is getting through to the transceiver. if the carrier sense signal re- mains deasserted throughout the transmis- sion, or if the ca rrier sense signal is deasserted before the end of the transmission, there is a loss-of-carrier error and the loss- of-crs bit (register 8, tx event, bit 6) is set. 3.12.2 aui receiver the aui receiver is a di fferential pair circuit that connects directly to the di+/di- pins. it is designed to distinguis h between transient noise pulses and inco ming ethernet packets. incoming packets with proper amplitude and pulse width are passed on to the endec sec- tion, while unwanted noise is rejected. 3.12.3 collision detection the aui collision circuit is a differential pair re- ceiver that detects th e presence of collision signals on the ci+/ci- pi ns. the collision signal is generated by an external ethernet trans- ceiver whenever a collis ion is detected on the ethernet segment. (section 7.3.1.2 of iso/iec 8802-3, 1993, defines the collision signal as a 10 mhz 15% signal with a duty cycle no worse than 60/40). when a collision is present, the aui collision circ uit informs the mac by asserting the internal collision signal. di+ di- do+ do- endec cl+ cl- collision detect auicol (to mac) auirx auisql auitx aui - + - + figure 15. aui
40 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 3.13 external clock oscillator a 20-mhz quartz crystal or cmos clock input is required by the cs 8900a. if a cmos clock input is used, it should be connected the to xtal1 pin, with the xt al2 pin left open. the clock signal should be 20 mhz 0.01% with a duty cycle between 40% and 60%. the speci- fications for the crystal are described in section 7.7 on page 122.
ds271f5 41 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 4.0 packetpage architecture 4.1 packetpage overview the cs8900a architecture is based on a unique, highly-efficien t method of accessing internal registers and buffer memory known as packetpage. packetpage provides a unified way of controlling the cs8900a in memory or i/o space that mini mizes cpu overhead and simplifies software. it pr ovides a flexible set of performance features and configuration op- tions, allowing designers to develop ethernet circuits that meet th eir particular system re- quirements. 4.1.1 integrated memory central to the cs8900a architecture is a 4- kbyte page of integrated ram known as pack- etpage memory. packetp age memory is used for temporary storage of transmit and receive frames, and for internal registers. access to this memory is done directly, through memory space operations (sec tion 4.9 on page 73), or indirectly, through i/o space operations (section 4.10 on page 75). in most cases, memory mode will provid e the best overall per- formance, because is a memory operations require fewer cycles than i/o operations. i/o mode is the cs8900a?s default configuration and is used when memory space is not avail- able or when special operations are required (e.g. waking the cs8900a from the software suspend state requires the host to write to the cs8900a?s assigned i/o space). the user-accessible por tion of packetpage memory is organized into the following six sec- tions: 4.1.2 bus interface registers the bus interface regist ers are used to config- ure the cs8900a?s isa-bus interface and to map the cs8900a into the host system?s i/o and memory space. most of these registers are written only during initialization, remaining unchanged while the cs8 900a is in normal operating mode. the exceptions to this are the dma registers which are modified continually whenever the cs8900a is using dma. these registers are described in more detail in section 4.3 on page 44. 4.1.3 status and control registers the status and control registers are the pri- mary means of control ling and getting status of the cs8900a. they are de scribed in more de- tail in section 4.4 on page 49. 4.1.4 initiate transmit registers the txcmd/txlength registers are used to initiate ethernet fram e transmission. these registers are described in more detail in section 4.5 on page 69. (see section 5.6 on page 99 for a description of frame transmis- sion.) 4.1.5 address filter registers the filter registers st ore the individual ad- dress filter and logical address filter used by the destination address (da) filter. these reg- isters are described in more detail in section 4.6 on page 71. for a description of the da filter, see se ction 5.2.10 on page 87. 4.1.6 receive and transmit frame loca- tions the receive and transmit frame packetpage locations are used to tr ansfer ethernet frames packetpage address contents 0000h - 0045h bus interface registers 0100h - 013fh status and control registers 0140h - 014fh initiate transmit registers 0150h - 015dh address filter registers 0400h receive frame location 0a00h transmit frame location packetpage address contents
42 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet to and from the host. t he host simply writes to and reads from these lo cations and internal buffer memory is dynamically allocated be- tween transmit and receive as needed. this provides more efficien t use of buffer memory and better overall network performance. as a result of this dynamic allocation, only one re- ceive frame (starting at packetpage base + 0400h) and one transmit frame (starting at packetpage base + 0a00h) are directly acces- sible. see section 4.7 on page 72. 4.2 packetpage memory map table 13 shows the cs8900a packetpage memory address map: s packetpage address # of bytes type description cross reference bus interface registers 0000h 4 read-only product identification code section 4.3 on page 44 0004h 28 - reserved note 2 0020h 2 read/write i/o base address section 4.3 on page 44, section 4.7 on page 72 0022h 2 read/write interrupt number (0,1,2,or 3) section 3.2 on page 18, section 4.3 on page 44 0024h 2 read/write dma channel number (0, 1, or 2) section 3.2 on page 18, section 4.3 on page 44 0026h 2 read-only dma start of frame section 4.3 on page 44, section 5.3 on page 90 0028h 2 read-only dma frame count (12 bits) sections section 4.3 on page 44, ?receive dma? 002ah 2 read-only rxdma byte count section 4.3 on page 44, section 5.3 on page 90 002ch 4 read/write memory base address register (20 bit) section 4.3 on page 44, section 4.9 on page 73 0030h 4 read/write boot prom base address section 3.6 on page 26, section 4.3 on page 44 0034h 4 read/write boot prom address mask section 3.6 on page 26, section 4.3 on page 44 0038h 8 - reserved note 2 0040h 2 read/write eeprom command section 3.5 on page 25, section 4.3 on page 44 0042h 2 read/write eeprom data section 3.5 on page 25, section 4.3 on page 44 0044h 12 - reserved note 2 0050h 2 read only received frame byte counter section 4.3 on page 44, section 5.2.9 on page 86 0052h 174 - reserved note 2 status and control registers notes: 1. all registers are accessed as words only. 2. read operation from the reserved location provides undefined data. writing to a reserved location or undefined bits may result in unpredictable operation of the cs8900a. table 13. packetpage memory address map
ds271f5 43 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 0100h 32 read/write configuration & control registers (2 bytes per register) section 4.4 on page 49 0120h 32 read-only status & event registers (2 bytes per register) section 4.4 on page 49 0140h 4 - reserved note 2 initiate transmit registers 0144h 2 write-only txcmd (transmit command) section 4.5 on page 69, section 5.6 on page 99 0146h 2 write-only txlength (transmit length) section 4.5 on page 69, section 5.6 on page 99 0148h 8 - reserved note 2 address filter registers 0150h 8 read/write logical address filter (hash table) section 4.6 on page 71, section 5.2.10 on page 87 0158h 6 read/write individual address section 4.6 on page 71, section 5.2.10 on page 87 015eh 674 - reserved note 2 frame location 0400h 2 read-only rxstatus (receive status) section 4.7 on page 72, section 5.2 on page 78 0402h 2 read-only rxlength (receive length, in bytes) section 4.7 on page 72, section 5.2 on page 78 0404h - read-only receive frame location section 4.7 on page 72, section 5.2 on page 78 0a00 - write-only transmit frame location section 4.7 on page 72, section 5.6 on page 99 packetpage address # of bytes type description cross reference notes: 1. all registers are accessed as words only. 2. read operation from the reserved location provides undefined data. writing to a reserved location or undefined bits may result in unpredictable operation of the cs8900a. table 13. packetpage memory address map (continued)
44 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 4.3 bus interface registers 4.3.1 product identification code (read only, address: packetpage base + 0000h) the product identification code register is located in th e first four bytes of the packetpage (0000h to 0003h). the register contains a unique 32-bit produc t id code that identifies the chip as a cs8900a. the host can use this num- ber to determine which software driver to load and to check which features are available. reset value is: 0000 1110 01 10 0011 0000 0000 000x xxxx the x xxxx codes for the cs8900a are: rev b: 0 0111 rev c: 0 1000 rev d: 0 1001 rev f: 0 1010 4.3.2 i/o base address (read/write, address: packetpage base + 0020h) the i/o base address register describes the base address for the sixteen contiguous locations in the host system's i/o space, which are used to access the packetpage regist ers. see section 4.10 on page 75. the default location is 0300h. after reset, if no eeprom is found by the cs8900a, then the register has th e following initial st ate. if an eeprom is found, then the register's initial value may be set by the eeprom. see section 3.3 on page 19. reset value is: 0000 0011 0000 0000 4.3.3 interrupt number (read/write, address: packetpage base + 0022h) the interrupt number register defines the interrupt pin selected by the cs8900a. in a typical application the follow- address 0000h address 0001h address 0002h address 00003h first byte of eisa registration number for crystal semiconductor second byte of eisa registration number for crystal semiconductor first 8 bits of product id number last 3 bits of the product id number (5 ?x? bits are the revision number) address 0021h address 0020h most significant byte of i/o base address least significant byte of i/o base address address 0023h address 0022h 00h interrupt number assignment: 0000 0000b= pin intrq0 0000 0001b= pin intrq1 0000 0010b= pin intrq2 0000 0011b= pin intrq3 0000 01xxb= all intrq pins high-impedance
ds271f5 45 cs8900a crystal lan? ethernet controller cirrus logic product datasheet ing bus signals are tied to the following pins: see section 3.2 on page 18. after reset, if no eeprom is found by the cs8900a, then t he register has the following initial state, which corre- sponds to placing all the intrq pins in a high-impedance state. if an eeprom is found, then the register's initial value may be set by the eeprom. see section 3.3 on page 19. reset value is: xxxx xxxx xxxx x100 4.3.4 dma channel number (read/write, address: packetpage base + 0024h) the dma channel register defines the dm a pins selected by the cs8900a. in the typical application, the following bus signals are tied to the following pins: see section 3.2 on page 18 and section 5.3 on page 90. after reset, if no eeprom is found by the cs8900a, then the register has the following initial state which corre- sponds to setting all dmrq pins to hi gh-impedance. if a eeprom is found, then the register's initial value may be set by the eeprom. see section 3.3 on page 19. reset value is: xxxx xxxx xxxx xx11 4.3.5 dma start of frame (read only, address: packetpage base + 0026h) the dma start of frame register contains a 16-bit value which defines the offset from the dma base address to the start of the most recently transferred received frame. see section 5.3 on page 90. bus signal typical pin connection irq5 intrq3 irq10 intrq0 irq11 intrq1 irq12 intrq2 address 0025h address 0024h 00h dma channel assignment: 0000 0000b= pin dmrq0 and dmack0 0000 0001b= pin dmrq1 and dmack1 0000 0010b= pin dmrq2 and dmack2 0000 0011b= all dmrq pins high-impedance bus signal typical pin connection drq5 dack5 dmrq0 dmack0 drq6 dack6 dmrq1 dmack1 drq7 dack7 dmrq2 dmack2 address 0027h address 0026h most significant byte of offset value least significant byte of offset value
46 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet reset value is: 0000 0000 0000 0000 4.3.6 dma frame count (read only, address: packetpage base + 0028h) the lower 12 bits of the dma frame count register define the number of valid frames transferred via dma since the last readout of this register. the upper 4 bits are reserved. see section 5.3 on page 90. reset value is: xxxx 0000 0000 0000 4.3.7 rxdma byte count (read only, address: packetpage base + 002ah) the rxdma byte count register describes the valid number of bytes dmaed since the last readout. see section 5.3 on page 90. reset value is: 0000 0000 0000 0000 4.3.8 memory base address (read/write, address: packetpage base + 002ch) memory base address: the lower three bytes (002ch, 002d h, and 002eh) are used for the 20-bit memory base address. the upper three nibbles are reserved. after reset, if no eeprom is found by the cs8900a, then the register has th e following initial st ate. if an eeprom is found, then the register's initial value may be set by the eeprom. see section 3.3 on page 19. reset value is: xxxx xxxx xxxx 0000 0000 0000 0000 0000 4.3.9 boot prom base address (read/write, address: packetpage base + 0030h) address 0029h address 0028h most significant byte of frame count (most-significant nibble always 0h) least significant byte of frame count address 002bh address 002ah most significant byte of byte count least significant byte of byte count address 002fh address 002eh address 002dh address 002ch reserved the most significant nibble of memory base address. the high-order nibble is reserved. contains portion of memory base address. the least significant byte of the memory base address. address 0033h address 0032h address 0031h address 0030h reserved the most significant nibble of boot prom base address. the high-order nibble is reserved. contains portion of boot prom base address. the least significant byte of the boot prom base address.
ds271f5 47 cs8900a crystal lan? ethernet controller cirrus logic product datasheet the lower three bytes (0030h, 0031h, and 0032h) of the boot prom base address register are used for the 20-bit boot prom base address. the upper three nibbles are reserved. see section 3.6 on page 26. after reset, if no eeprom is found by the cs8900a, then the register has th e following initial st ate. if an eeprom is found, then the register's initial value may be set by the eeprom. see section 3.3 on page 19. reset value is: xxxx xxxx xxxx 0 000 0000 0000 0000 0000 4.3.10 boot prom address mask (read/write, address: packetpage base + 0034h) the boot prom address mask register indicates the size of the attached boot prom and is limited to 4k bit incre- ments. the lower 12 bits of the address mask are ignored, and should be 000h. the next lowest-order bits describe the size of the prom. the upper three nibbles are reserved. for example: see section 3.6 on page 26. after reset, if no eeprom is found by the cs8900a, then the register has th e following initial st ate. if an eeprom is found, then the register's initial value may be set by the eeprom. see section 3.3 on page 19. reset value is: xxxx xxxx xxxx 0 000 0000 0000 0000 0000 4.3.11 eeprom command (read/write, address: packetpage base + 0040h) this register is used to control the reading, writing and erasing of the eeprom. see section 3.5. add7-add0 address of the eepr om word being accessed. ob1,ob0 indicates the opcode of the command being executed. see table 8. elsel external logic select: when clear, the eecs pin is used to select the eeprom . when set, the elcs pin is used to select the external la decode circuit. reserved reserved and must be written as 0. address 0037h address 0036h address 0035h address 0034h reserved the most significant nibble of boot prom mask address. the high-order nibble is reserved. contains portion of boot prom mask address. the lower-order nibble must be written as 0h. the least significant byte of the boot prom mask address. must be written as 00h. size of boot prom register value 4k bits xxxx xxxx xxxx 1111 1111 0000 0000 0000 8k bits xxxx xxxx xxxx 1111 1110 0000 0000 0000 16k bits xxxx xxxx xxxx 1111 1100 0000 0000 0000 76543210 add7 to add0 fedcba9 8 reserved elsel ob1 ob0
48 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet reset value is: xxxx xxxx xxxx xxxx 4.3.12 eeprom data (read/write, address: packetpage base + 0042h) this register contains t he word being written to, or read from, the eeprom. see section 3.5 on page 25. reset value is: xxxx xxxx xxxx xxxx 4.3.13 receive frame byte counter (read only, address: packetpage base + 0050h) this register contains the count of the total number bytes received in the current receiv ed frame. this count contin- uously increments as more bytes in this frame are received. see section 5.2.9 on page 86. reset value is: xxxx xxxx xxxx xxxx address 0043h address 0042h most significant byte of the eeprom data. least significant byte of the eeprom data. address 0051h address 0050h most significant byte of the byte count. least significant byte of the byte count.
ds271f5 49 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 4.4 status and control registers the status and control registers are the pri- mary registers used to control and check the status of the cs8900a . they are organized into two groups: confi guration/control regis- ters and status/event registers. all status and control registers are 16-bit words as shown in figure 16. bit 0 indicates whether it is a configuration/cont rol register (bit 0 = 1) or a status/event register (bit 0 = 0). bits 0 through 5 prov ide an internal address code that describes the exac t function of the regis- ter. bits 6 thr ough f are the ac tual configura- tion/control and status /event bits. 4.4.1 configuration and control registers configuration and contro l registers are used to setup the following: ? how frames will be transmitted and re- ceived; ? which frames will be transmitted and re- ceived; ? which events will cause interrupts to the host processor; and, ? how the ethernet physi cal interface will be configured. these registers are r ead/write and are desig- nated by odd numbers (e.g . register 1, regis- ter 3, etc.). the transmit command register (txcmd) is a special type of regist er. it appears in two separate locations in the packetpage memory map. the first locati on, packetpage base + 0108h, is within the block of configura- tion/control registers and is read-only. the second location, packetpage base + 0144h, is where the actual tran smit commands are is- sued and is write-only . see section 4.4.4 on page 51 (register 9) and section 5.6 on page 99 for a more detail ed description of the txcmd register. 4.4.2 status and event registers status and event registers report the status of transmitted and received frames, as well as in- formation about the c onfiguration of the cs8900a. they are read- only and are desig- nated by even numbers (e.g. register 2, reg- ister 4, etc.). the interrupt status q ueue (isq) is a special type of status/event r egister. it is located at packetpage base + 0120h and is the first reg- ister the host reads when responding to an in- terrupt. a more detailed descrip tion of the isq can be found in section 5.1 on page 78. three 10-bit counters are included with the status and event regist ers. rxmiss counts missed receive frames, txcol counts trans- mit collisions, and tdr is a time domain reflec- 1 0 32 54 76 10 register bits 1 = control/configuration 0 = status/event internal address (bits 0 - 5) 16-bit register word bit number 98 ba dc f e figure 16. status and control register format
50 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet tometer useful in locating cable faults. the following sections contain more information about these counters. table 14 provides a summary of packetpage register types. 4.4.3 status and co ntrol bit definitions this section provides a description of the spe- cial bit types used in the status and control registers. section 4.4.4 on page 51 provides a detailed description of the bits in each register. 4.4.3.1 act-once bits there are four bits t hat cause the cs8900a to take a certain action only once when set. these ?act-once? bits ar e: skip_1 (register 3, rxcfg, bit 6), reset (register 15, selfctl, bit 6), resetrxdma (regi ster 17, busctl, bit 6), and swint-x (register b, bufcfg, bit 6). to cause the action again, the host must set the bit again. act-once bits are always read as clear. 4.4.3.2 temporal bits temporal bits are bits that are set and cleared by the cs8900a without intervention of the host processor. this incl udes all status bits in the three status regist ers (register 14, lin- est; register 16, selfst; and, register 18, busst), the rxdest bit (register c, bufevent, bit f), and the rx128 bi t (register c, bufe- vent, bit b). li ke all event bi ts, rxdest and rx128 are cleared w hen read by the host. 4.4.3.3 interrupt enable bits and events interrupt enable bits end with the suffix ie and are located in three co nfiguration registers: rxcfg (register 3), txcfg (register 7), and bufcfg (register b). each interrupt enable bit corresponds to a specific event. if an inter- rupt enable bit is se t and its corresponding event occurs, the cs8900a generates an in- terrupt to the host processor. the bits that report w hen various events occur are located in three ev ent registers and two counters. the event r egisters are rxevent (register 4), txevent (register 8), and bufe- vent (register c). the counters are rxmiss (register 10) and txco l (register 12). each interrupt enable bit and its associated event are identified in table 15. an event bit will be set whenever the specified event happens, whether or not the associated interrupt enable bit is se t. all event registers are cleared upon read -out by the host. suffix type description comments cmd read/write command: written once per frame to initiate transmit. cfg read/write configuration: written at setup and used to determine what frames will be transmi tted and receiv ed and what events will cause interrupts. ctl read/write control: written at setup and used to determine what frames will be trans mitted and received and how the physi- cal interface will be configured. event read-only event: reports the status of transmitted and received frames. cleared when read st read-only status: reports information about the configuration of the cs8900a. read-only counters: counts missed receive frames and collisions. provides time domain for locating coax cable faults. cleared when read table 14. packetpage register types
ds271f5 51 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 4.4.3.4 accept bits there are nine accept bi ts located in the rx- ctl register (register 5) , each of which is fol- lowed by the suffix a. accept bits indicate which types of frames will be accepted by the cs8900a. (a frame is sa id to be ?accepted? by the cs8900a when the frame data are placed in either on-chip memo ry, or in host memory by dma.) four of these bits have correspond- ing interrupt enable (ie) bits. an accept bit and an interrupt enable bit are independent opera- tions. it is possible to set either, neither, or both bits. the four corr esponding pairs of bits are: if one of the above interr upt enable bits is set and the corresponding accept bit is clear, the cs8900a generates an in terrupt when the as- sociated receive even t occurs, but then does not accept the receive frame (the length of the receive frame is set to zero). the other five accept bits in rxctl are used for destination addr ess filtering (see section 5.2.10 on page 87). the accept mechanism is explained in more detail in section 5.2 on page 78. 4.4.4 status and c ontrol register sum- mary the table on the followi ng page (table 16) pro- vides a summary of th e status and control registers. section 4.4.4 on page 51 gives a de- tailed description of each status and control register. interrupt enable bit (register name) event bit or counter (register name) extradataie (rxcfg) extradata (rxevent) runtie (rxcfg) runt (rxevent) crcerrorie (rxcfg) crcerror (rxevent) rxokie (rxcfg) rxok (rxevent) 16collie (txcfg) 16coll (txevent) anycollie (txcfg) ?numb er-of tx-collisions? counter is incremented (txevent) jabberie (txcfg) jabber (txevent) out-of-windowie (txcfg) out-of-window (txevent) txokie (txcfg) txok (txevent) sqeerrorie (txcfg) sqeerror (txevent) loss-of-crsie (txcfg) l oss-of-crs (txevent) missovfloie (bufcfg) rxmiss counter over- flows past 1ffh txcolovfloie (bufcfg) txcol counter overflows past 1ffh rxdestie (bufcfg) rxdest (bufevent) rx128ie (bufcfg) rx128 (bufevent) rxmissie (bufcfg) rxmiss (bufevent) txunderrunie (bufcfg) txunderrun (bufevent) rdy4txie (bufcfg) rdy4tx (bufevent) rxdmaie (bufcfg) rxdmaframe (bufevent) table 15. interrupt enable bits and events ie bit in rxcfg a bit in rxctl extradataie extradataa runtie runta crcerrorie crcerrora rxokie rxoka
52 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet control and configuration bits register fedcba9 876number (offset) name reserved (register contents undefined) 1 extra dataie runtie crc errorie buffer crc autorx dmae rxdma only rxokie streame skip_1 3 (0102h) rxcfg extra dataa runta crc errora broad casta individ uala multi casta rxoka promis cuousa iaha- sha 5 (0104h) rxctl 16colli e anycollie jab berie out-of- windowie txokie sqerro- rie loss-of- crsie 7 (0106h) txcfg txpad- dis inhibit- crc onecoll force txstart 9 (0108h) txcmd rxde stie miss ovfloie txcol ovfloie rx128ie rxmis- sie txunder- runie rdy4txi e rxd- maie swint-x b (010ah) bufcfg reserved (register contents undefined) d-11 lorx squelch 2-part defdis polarity dis mod backoffe auto- aui/10b t auionly ser txon ser rxon 13 (0112h) line ctl hcb1 hcb0 hc1e hc0e hwstan dbye hw sleepe sw sus- pend reset 15 (0114h) selfctl enabl e irq rxdma size ioch rdye dma burst memo- rye usesa dmaex- tend reset rxdma 17 (0116) busctl fdx disable backoff auiloop endec loop disable lt 19 (0118) testctl reserved (register contents undefined) 1b -1f table 16. status and control register descriptions
ds271f5 53 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 4.4.5 register 0: in terrupt status queue (isq, read-only, address: packetpage base + 0120h) the interrupt status queue register is used in both memory mode and i/o mo de to provide the host with interrupt information. whenever an event occurs that triggers an enabled interrupt, the cs8900a sets the appropriate bit(s) in one of five registers, maps the cont ents of that register to the isq regist er, and drives an irq pin high. three of the registers mapped to isq are event registers: rxevent (register 4), txevent (register 8), and bufevent (register c). the other two registers are counter-overflow reports : rxmiss (register 10) and txcol (register 12). in mem- ory mode, isq is located at packetpage base + 120h. in i/o mode, isq is located at i/o base + 0008h. see section 5.1 on page 78. status and event bits register fedcba9 876number (offset) name interrupt status queue 0 (0120h) isq reserved (register contents undefined) 2 extra data runt crc error broad- cast individ- ual adr hashed rxok dribble bits iahash 4 (0124h) rx event hash table index (alternate rxevent meaning if hashed = 1 and rxok = 1) hashed rxok dribble bits iahash 4 (0124h) rx eventalt reserved (register contents undefined) 6 16coll number-of-tx-co llisions jabber out-of- window txok sqe error loss-of- crs 8 (0128h) txevent reserved (register contents undefined) a rx dest rx128 rxmiss txunder- run rdy4tx rxdma frame swint c (012ch) buf event reserved (register contents undefined) e 10-bit receive miss (rxmiss) counter, cleared when read 10 (0130h) rxmiss 10-bit transmit collision (txcol ) counter, cleared when read 12 (0132h) txcol crs polarity ok 10bt aui linkok 14 (0134h) linest eesize el pres- ent eepro m ok eepro mpresent sibusy initd 3.3 v active 16 (0136h) selfst rdy4tx now txbid err 18 (0138h) busst reserved (register contents undefined) 1a 10-bit aui time domain reflectometer (tdr) counter, cleared when read 1c (013ch) tdr reserved (register contents undefined) 1e 76543210 regcontent regnum fedcba9 8 regcontent table 16. status and control register descriptions (continued)
54 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet regnum the lower six bits describe which register (4, 8, c, 10 or 12) is contained in the isq. regcontent the upper ten bits cont ain the register data contents. reset value is: 0000 0000 0000 0000 4.4.6 register 3: receiver configuration (rxcfg, read/write, address: packetpage base + 0102h) rxcfg determines how frames will be transferred to the ho st and what frame ty pes will cause interrupts. 000011 these bits provide an internal address used by the cs8900a to identify this as the receiver configuration register. skip_1 when set, this bit causes th e last committed received frame to be deleted from the receive buf- fer. to skip another frame, the host must rewrite a ?1? to this bit. this bit is not to be used if rxdmaonly (bit 9) is set. skip_1 is an act-once bit. see section 5.2.5 on page 85. streame when set, streamtransfer mode is used to transfer receive frames that are back-to-back and that pass the destination addr ess filter (see section 5.2.10 on page 87). when streame is clear, streamtransfer mode is not used. this bit must not be set unless either bit autorxdma or bit rxdmaonly is set. rxokie when set, there is an rxok interrupt if a frame is received without errors . rxok interrupt is not generated when dma mode is used for frame reception. rxdmaonly the receive-dma mode is used for all receive frames when this bit is set. autorxdmae when set, the cs8900a will automatically switch to receive- dma mode if the conditions spec- ified in section 5.4 on page 94 are met. rxdmaonly (bit 9) has precedence over autorxd- mae. buffercrc when set, the received crc is included with the data stored in the receive-frame buffer, and the four crc bytes are included in the receive-frame length (packetpage base + 0402h). when clear, neither the receive buffer nor the receive length include the crc. crcerrorie when set, there is a crcerror inte rrupt if a frame is received with a bad crc. runtie when set, there is a runt interrupt if a fram e is received that is shorter than 64 bytes. the cs8900a always discards any frame that is shorter than 8 bytes. extradataie when set, there is an extradata interrupt if a frame is received that is longer than 1518 bytes. the operation of this bit is independent of th e received packet integrity (good or bad crc). after reset, if no eeprom is found by th e cs8900a, then the register has the following in itial state. if an eeprom is found, then the register?s in itial value may be set by the eeprom. see section 3.3 on page 19. reset value is: 0000 0000 0000 0011 76543210 streame skip_1 000011 fedcba9 8 extradataie runtie crcerrorie buffercrc autorx dmae rxdma only rxokie
ds271f5 55 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 4.4.7 register 4: receiver event (rxevent, read-only, address: packetpage base + 0124h) alternate meaning if bits 8 and 9 are both set (see se ction 5.2.10 on page 87 for exception regarding broadcast frames). rxevent reports the status of the current received frame. 000100 these bits identify this as the receiver event register. when reading this register, these bits will be 000100, where the l sb corresponds to bit 0. iahash if the received frame's destinat ion address is accepted by the hash filter, then this bit is set if, and only if iahasha (register 5, rxctl, bit 6) is set, and hashed (bit 9) is set. see section 5.2.10 on page 87. dribblebits if set, the received frame had from one to seven bits after the last received full byte. an "align- ment error" occurs when dribblebits and crcerror (bit c) are both set. rxok if set, the received frame had a good crc and va lid length (i.e., there is not a crc error, runt error, or extradata error). when rxok is set, t hen the length of the received frame is contained at packetpage base + 0402h. if rxokie (register 3, rxcfg, bit 8) is set, there is an interrupt. hashed if set, the received frame had a destination ad dress that was accepted by the hash filter. if hashed and rxok (bit 8) are set, bits f thro ugh a of rxevent become the hash table index for this frame [see section 5.2 .10 on page 87 for an exception regarding broadcast frames!].if hashed and rxok are not both set, then bits f through a are individual event bits as defined below. individualadr if the received frame had a destination address which matched the individual address found at packetpage base + 0158h, then this bit is set if, and only if, rxok (bit 8) is set and individ- uala (register 5, rxctl, bit a) is set. broadcast if the received frame had a broadcast address (ffff ffff ffffh) as the destination ad- dress, then this bit is set if, and only if, rxok is set and broadcasta (register 5, rxctl, bit b) is set. crcerror if set, the received frame had a bad crc. if crce rrorie (register 3, rxcfg, bit c) is set, there is an interrupt runt if set, the received frame was shorter than 64 by tes. if runtie (register 3, rxcfg, bit d) is set, there is an interrupt. extradata if set, the received frame was longer than 1518 bytes. all bytes beyond 1518 are discarded. if extradataie (register 3, rxcfg, bit e) is set, there is an interrupt. reset value is: 0000 0000 0000 0100 notes: 3. all rxevent bits are cleared upon readout. th e host is responsible for processing all event bits. 4. rxstatus register (packetpage base + 0400h) is th e same as the rxevent register except rxstatus is not cleared when rxevent is read. see section 5.2 on page 78 . the value in the rxevent register is undefined when rxdmaonly bit (bit 9, register 3, rxcfg) is set. 76543210 dribblebits iahash 000100 fedcba9 8 extradata runt crcerror broadcast individual adr hashed rxok 76543210 dribblebits iahash 000100 fedcba9 8 hash table index (see section 5.2.10 on page 87) hashed = 1 rxok = 1
56 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 4.4.8 register 5: receiver control (rxctl, read/write, address: packetpage base +0104h) rxctl has two function s: bits 8, c, d, and e define what types of fram es to accept. bits 6, 7, 9, a, and b configure the destination address filter. see section 5.2.10 on page 87. 000101 these bits provide an internal address used by the cs8900a to identify this as the receiver control register. for a received frame to be accepted, the destination address of that frame must pass the filter criteria found in bits 6, 7, 9, a, and b (see section 5.2.10 on page 87). iahasha when set, receive frames are accepted when the destination address is an individual address that passes the hash filter. promiscuousa frames with any address are accepted when this bit is set. rxoka when set, the cs8900a accepts frames with corr ect crc and valid length (valid length is: 64 bytes <= length <= 1518 bytes). multicasta when set, receive frames are accepted if the destination address is an multicast address that passes the hash filter. individuala when set, receive frames are accepted if the destination address ma tches the individual ad- dress found at packetpage base + 0158h to packetpage base + 015dh. broadcasta when set, receive frames are accepted if the destination address is ffff ffff ffffh. crcerrora when set, receive frames that pass the destination address filter , but have a bad crc, are ac- cepted. when clear, frames with bad crc are discarded. see note 5. runta when set, receive frames that are smaller than 64 bytes, and that pass the destination address filter are accepted. when clear, received frames less that 64 bytes in length are discarded. the cs8900a discards any frame that is less than 8 bytes. see note 5. extradataa when set, receive frames longer than 1518 bytes and that pass the destination address filter are accepted. the cs8900a accepts only the first 1518 bytes and ignores the rest. when clear, frames longer than 1518 bytes are discarded. see note 5. after reset, if no eeprom is found by the cs8900a, then the register has th e following initial st ate. if an eeprom is found, then the register's initial value may be set by the eeprom. see section 5.2.10 on page 87. reset value is: 0000 0000 0000 0101 notes: 5. typically, when bits crcerrora, runta and ex tradataa are cleared (meaning bad frames are being discarded), then the corresponding bits crcerrorie, ru ntie and extradataie should be set in register 3 (receiver configuration register) to allow the device driver to keep track of discarded frames. 76543210 promiscuousa iahasha 000101 fedcba9 8 extradataa runta crcerrora broadcasta individuala multicasta rxoka
ds271f5 57 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 4.4.9 register 7: transmit configuration (txcfg, read/write, address: packetpage base + 0106h) each bit in txcfg is an interrupt enable. when set, the interrupt is enabled as described below. when clear, there is no interrupt. 000111 these bits provide an internal address used by the cs8900a to identify this as the transmit configuration register. loss-of-crsie if the cs8900a starts transmitting on the aui and does not see the ca rrier sense signal at the end of the preamble, an interrupt is generated if th is bit is set. carrier sense activity is reported by the crs bit (register 14, linest, bit e). sqerrorie when set, an interrupt is generated if ther e is an sqe error. (at the end of a transmission on the aui, the cs8900a expects to see a collisio n within 64 bit times. if this does not happen, there is an sqe error.) txokie when set, an interrupt is genera ted if a packet is completely transmitted. out-of-windowie when set, an interrupt is gene rated if a late collision occurs (a late collision is a collision which occurs after the first 512 bit times). when this occurs, the cs8900a forces a bad crc and ter- minates the transmission. jabberie when set, an interrupt is generated if a transmission is longer than approximately 26 ms. anycollie when set, if one or more collisions occur during th e transmission of a packet, an interrupt oc- curs at the end of the transmission 16collie if the cs8900a encounters 16 normal collisions while attempting to transmit a particular packet, the cs8900a stops attempting to transmit that pack et. when this bit is set, there is an interrupt upon detecting the 16th collision. after reset, if no eeprom is found by the cs8900a, then the register has th e following initial st ate. if an eeprom is found, then the register's initial value may be set by the eeprom. see section 3.3 on page 19. reset value is: 0000 0000 0000 0111 notes: bit 8 (txokie) and bit b (anyco llie) are interrupts for norma l transmit operation. bi ts 6, 7, 9, a, and f notes:are interrupts for abnormal transmit operation. 4.4.10 register 8: transmitter event (txevent, read-only, address: packetpage base + 0128h) txevent gives the even t status of the last packet transmitted. 76543210 sqe errorie loss-of-crsie 000111 fedcba9 8 16collie anycollie jabberie out-of-window txokie 76543210 sqeerror loss-of-crs 001000 fedcba9 8 16coll number-of-tx-collisions jabber out-of-window txok
58 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 001000 these bits provide an internal address used by the cs8900a to identify this as the transmitter event register. loss-of-crs if the cs8900a is transmitting on the aui and doesn't see carrier sense (crs) at the end of the preamble, there is a loss-of-carrier error and this bit is set. if lo ss-of-crsie (register 7, txcfg, bit 6) is set, there is an interrupt. sqeerror at the end of a transmi ssion on the aui, the cs8900a expect s to see a collision within 64 bit times. if this does not happen, there is an sqe er ror and this bit is set. if sqeerrorie (register 7, txcfg, bit 7) is se t, there is an interrupt. txok this bit is set if the last packet was comple tely transmitted (jabber (b it a), out-of -window-colli- sion (bit 9), and 16coll (b it f) must all be clear). if txokie (register 7, txcfg, bit 8) is set, there is an interrupt. out-of-window this bit is set if a collisio n occurs more than 512 bit times afte r the first bit of the preamble. when this occurs, the cs8900a forces a bad crc and terminates the transmissi on. if out-of-window- ie (register 7, txcfg, bit 9) is set, there is an interrupt jabber if the last transmission is longer than 26 ms ec, then the packet output is terminated by the jab- ber logic and this bit is set. if jabberie (register 7, txcfg, bit a) is set, there is an interrupt. #-of-tx-collisions these bits give the number of transmit collisions that occurred on the last transmitted packet. bit b is the lsb. if anycollie (register 7, txcfg, bit b) is set, there is an interrupt when any collision occurs. 16coll this bit is set if the cs89 00a encounters 16 normal collisions while a ttempting to transmit a particular packet. when this happens, the cs8900 a stops further attempts to send that packet. if 16collie (register 7, txcfg, bit f) is set, there is an interrupt. reset value is: 0000 0000 0000 1000 notes: 1.in any event register, like txevent, a ll bits are cleared upon readout. the host is responsible for processing all event bits. 2.txok (bit 8) and the nu mber-of-tx-collisions (bits e-b) are us ed in normal pack et transmission.all other bits (6, 7, 9, a, and f) give th e status of abnormal transmit operation. 4.4.11 register 9: transmit command status (txcmd, read-only, address: packetpage base + 0108h) this register contains the latest tr ansmit command which tells the cs8900a how the next packet should be sent. the command must be written to packetpage base + 0144h in order to initiate a transmission. the host can read the command from register 9 (packetpage base + 0108h). see section 5.6 on page 99. 001001 these bits provide an internal address used by the cs8900a to identify this as the transmit command register. when reading this register, these bits will be 001001, where the lsb cor- responds to bit 0. txstart this pair of bits determines how many bytes are transferred to the cs8900a before the mac starts the packet transmit process. 76543210 txstart 001001 fedcba9 8 txpaddis inhibitcrc onecoll force
ds271f5 59 cs8900a crystal lan? ethernet controller cirrus logic product datasheet bit 7 bit 6 0 0 start transmission after 5 bytes are in the cs8900a 0 1 start transmission after 381 bytes are in the cs8900a 1 0 start transmission after 1021 bytes are in the cs8900a 1 1 start transmissi on after the entire frame is in the cs8900a force when set in conjunction with a new transmit co mmand, any transmit frames waiting in the trans- mit buffer are deleted. if a previous packet has started transmission, that packet is terminated within 64 bit times with a bad crc. onecoll when this bit is set, any transmission will be terminated after only one collision. when clear, the cs8900a allows up to 16 normal collisio ns before terminating the transmission. inhibitcrc when set, the crc is not appended to the transmission. txpaddis when txpaddis is clear, if the host gives a transmit length less than 60 bytes and inhibitcrc is set, then the cs8900a pads to 60 bytes. if t he host gives a transmit length less than 60 bytes and inhibitcrc is clear, then the cs8900a pads to 60 bytes and appends the crc. when txpaddis is set, the cs8900a allows the transmission of runt frames (a frame less than 64 bytes). if inhibitcrc is clear, the cs89 00a appends the crc. if i nhibitcrc is set, the cs8900a does not append the crc after reset, if no eeprom is found by the cs8900a, then the register has th e following initial st ate. if an eeprom is found, then the register's initial value may be set by the eeprom. see section 3.3 on page 19. register value is: 0000 0000 0000 1001 notes: the cs8900a does not transmit a frame if txlength < 3 4.4.12 register b: buffer co nfiguration (bufcfg, read/write, address: packetpage base + 010ah) each bit in bufcfg is an interrupt enable. when set, the in terrupt described below is enabled. when clear, there is no interrupt. 001011 these bits provide an internal address used by the cs8900a to identify this as the buffer con- figuration register. swint-x when set, there is an interrupt requested by the host software. the cs8900a provides the in- terrupt, and sets the swint (register c, bufevent , bit 6) bit. the cs8900a acts upon this com- mand at once. swint-x is an act-once bit. to generate another interrupt, rewrite a "1" to this bit. rxdmaie when set, there is an interrupt when a frame has been received and dma is complete. with this interrupt, the rxdmaframe bit (r egister c, bufevent, bit 7) is set. rdy4txie when set, there is an inte rrupt when the cs8900a is ready to accept a frame from the host for transmission. (see section 5.6 on page 99 for a description of the transmit bid process.) txunderrunie when set, there is an interrupt if the cs890 0a runs out of data before it reaches the end of the frame (called a transmit underrun). when this happens, event bit txunderrun (register c, bufevent, bit 9) is set and the cs8900a makes no further attempts to transmit that frame. if the 76543210 rxdmaie swint-x 001011 fedcba9 8 rxdestie miss ovfloie txcol ovfloie r x128ie rxmissie txunder runtie rdy4txie
60 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet host still wants to transmit that particular frame, the host must go through the tr ansmit request process again. rxmissie when set, there is an interr upt if one or more received frames is lost due to slow movement of receive data out of the receive buffer (called a receive miss). when this happens, the rxmiss bit (register c, bufevent, bit a) is set. rx128ie when set, there is an interrupt after the first 128 bytes of a frame have been received. this al- lows a host processor to exam ine the destination address, source address, length, sequence number, and other information before the entire frame is received. this interrupt should not be used with dma. thus, if either autorxdma (register 3, rxcfg, bit a) or rxdmaonly (register 3, rxcfg, bit 9) is set, the rx128ie bit must be clear. txcolovfie if set, there is an interrupt when the txcol counter increments from 1ffh to 200h. (the txcol counter (register 18) is incremented whenever the cs8900a sees that the rxd+/rxd- pins (10base-t) or the ci+/ ci- pins (aui) go active while a packet is being transmitted.) missovfloie if missovfloie is set, ther e is an interrupt when the rxmiss counter increments from 1ffh to 200h. (a receive miss is said to have occurred if packets are lost due to slow movement of re- ceive data out of the receive bu ffers. when this happens, the rxmiss bit (register c, bufevent, bit a) is set, and the rxmiss counter (register 10) is incremented.) rxdestie when set, there is an in terrupt when a receive frame passes the destination address filter cri- teria defined in the rxctl register (register 5). th is bit provides an early indication of an in- coming frame. it is earlier than rx128 (registe r c, bufevent, bit b). if rxdestie is set, the bufevent could be rxdest or rx128. after 128 bytes are received, the bufevent changes from rxdest to rx128. after reset, if no eeprom is found by the cs8900a, then th e register has the following init ial state after reset. if an eeprom is found, then the register 's initial value may be set by the eeprom. see section 3.3 on page 19. reset value is: 0000 0000 0000 1011 4.4.13 register c: buffer event (bufevent, read-only, address: packetpage base + 012ch) bufevent gives the status of the transmit and receive buffers. 001100 these bits provide an internal address used by the cs8900a to identify this as the buffer event register. when reading this register, these bits will be 00110 0, where the lsb corresponds to bit 0. swint if set, there has been a software initiated interr upt. this bit is used in conjunction with the swint- x bit (register b, bufcfg, bit 6). rxdmaframe if set, one or more received frames have been transferred by slave dma. if rxdmaie (register b, bufcfg, bit 7) is set, there is an interrupt. rdy4tx if set, the cs8900a is ready to accept a fr ame from the host for transmission. if rdy4txie (reg- ister b, bufcfg, bit 8) is set, there is an interrupt. (see section 5.6 on page 99 for a description of the transmit bid process.) 76543210 rxdma frame swint 001100 fedcba9 8 rxdest rx128 rxmiss txunder run rdy4tx
ds271f5 61 cs8900a crystal lan? ethernet controller cirrus logic product datasheet txunderrun this bit is set if cs8900a runs out of data before it reaches the end of the frame (called a trans- mit underrun). if txunderrunie (register b, bu fcfg, bit 9) is set, there is an interrupt. rxmiss if set, one or more receive frames have been lost due to slow movement of data out of the re- ceive buffers. if rxmissie (reg ister b, bufcfg, bit a) is set, there is an interrupt. rx128 this bit is set after the first 128 bytes of an incoming frame have been received. this bit will allow the host the option of preprocessing frame data before the entire frame is received. if rx128ie (register b, bufcfg, bit b) is set, there is an interrupt. rxdest when set, this bit sh ows that a receive frame has passed the destination address filter criteria as defined in the rxctl register (register 5). this bit is useful as an early indication of an in- coming frame. it will be earlier than rx128 (register c, bufevent, bit b). if rxdestie (register b, bufcfg, bit f) is set, there is an interrupt. reset value is: 0000 0000 0000 1100 notes: with any event register, like bufevent, all bits are cleared upon readout. the host is responsible for processing all event bits. 4.4.14 register 10: receiver miss counter (rxmiss, read-only, address: packetpage base + 0130h) the rxmiss counter (bits 6 through f) records the number of receive frames that are lost (missed) due to the lack of available buffer space. if the missovfloie bit (register b, bufcfg, bit d) is set, th ere is an interrupt when rxmiss increments from 1ffh to 200h. this interrupt provides the host with an early warning that the rxmiss counter should be read before it reaches 3ffh and starts over (by interrup ting at 200h, the host has an additional 512 counts before rxmiss actually overflows). the rx miss counter is cleared when read. 010000 these bits provide an internal address used by the cs8900a to identify this as the receiver miss counter. when reading this register, th ese bits will be 010000, where the lsb corre- sponds to bit 0. misscount the upper ten bits contain the number of missed frames. register?s value is: 0000 0000 0001 0000 4.4.15 register 12: transmit collision counter (txcol, read-only, address: packetpage base + 0132h) the txcol counter (bits 6 th rough f) is incremented w henever the 10base-t receive pair (rxd+ / rxd-) or aui collision pair (ci+ / ci-) beco mes active while a packet is be ing transmitted. if the txco lovfie bit (register b, buf- 76543210 misscount 010000 fedcba9 8 misscount 76543210 colcount 010010 fedcba9 8 colcount
62 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet cfg, bit c) is set, there is an interrupt when txcol increments from 1ffh to 200h. this interrupt provides the host with an early warning that the txcol counter should be read before it reaches 3ffh and starts over (by interrupting at 200h, the host has an additional 512 counts before txcol actually overflows). th e txcol counter is cleared when read. 010010 these bits provide an internal address used by the cs8900a to identify this as the transmit collision counter. when reading th is register, these bits will be 010010, where the lsb corre- sponds to bit 0. colcount the upper ten bits cont ain the number of collisions. reset value is: 0000 0000 0001 0010 4.4.16 register 13: line control (linectl, read/write, address: packetpage base + 0112h) linectl determines the configuration of the mac engine and physical interface. 010011 these bits provide an internal address used by the cs8900a to identify this as the line control register. serrxon when set, the receiver is enabled. when clear, no incoming packets pass through the receiver. if serrxon is cleared while a packet is being re ceived, reception is completed and no subse- quent receive packets are allowe d until serrxon is set again. sertxon when set, the transmitter is enabled. when cl ear, no transmissions are allowed. if sertxon is cleared while a packet is being transmitted, transmission is completed and no subsequent packets are transmitted until sertxon is set again. auionly bits 8 and 9 are used to select either the aui or the 10base-t interface according to the fol- lowing: [note: 10base-t transmitter will be inacti ve even when se lected unless link pulses are detected or bit disablelt (register 19) is set. auionly (bit 8) autoaui/10bt (bit 9) physical interface 1n/a aui 0> 0 0base-t 0 1 auto-select autoaui/10bt see auionly (bit 8) description above. modbackoffe when clear, th e iso/iec standard backoff algorithm is used (see section 3.9 on page 29). when set, the modified backoff algorithm is used. (the modified backoff algorithm extends the backoff delay after each of the first three tx collisions.) polaritydis the 10base-t rece iver automatically determines the polar ity of the received signal at the rxd+/rxd- input (see section 3.11 on page 36). wh en this bit is clear, the polarity is correct- ed, if necessary. when set, no effort is made to correct the polarity. this bit is independent of the polarityok bit (register 14, linest, bit c), wh ich reports whether the polarity is normal or reversed. 76543210 sertxon serrxon 010011 fedcba9 8 lorx squelch 2-part defdis polaritydis mod backoffe auto aui/10bt auionly
ds271f5 63 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 2-partdefdis before a transmission can begin, the cs 8900a follows a deferral procedure. with the 2-part- defdis bit clear, the cs8900a uses the standard two-part deferral as defined in iso/iec 8802- 3 paragraph 4.2.3.2.1. with the 2-partdefdis bit set, the two-part deferral is disabled. lorxsquelch when clear, the 10base-t re ceiver squelch thresholds are set to levels define d by the iso/iec 8802-3 specification. when set, the thresholds are reduced by approximately 6db. this is use- ful for operating with "quiet" cables that are longer than 100 meters. after reset, if no eeprom is found by the cs8900a, then the register has th e following initial st ate. if an eeprom is found, then the register's initial value may be set by the eeprom. see section 3.3 on page 19. reset value is: 0000 0000 0001 0011 4.4.17 register 14: line status (linest, read-only, address: packetpage base + 0134h) linest reports the status of th e ethernet physical interface. 010100 these bits provide an internal address used by the cs8900a to i dentify this as the line status register. when reading this register, these bits will be 01010 0, where the lsb corresponds to bit 0. linkok if set, the 10base-t link has not failed. when clear, the link has faile d, either because the cs8900a has just come out of reset, or because the receiver has not detected any activity (link pulses or received packets) for at least 50 ms. aui if set, the cs8900a is using the aui. 10bt if set, the cs8900a is using the 10base-t interface. polarityok if set, the polarity of the 10base-t receive signal (at the rxd+ / rx d- inputs) is corr ect. if clear, the polarity is reversed. if polaritydis (register 13 , linectl, bit c) is clea r, the polarity is auto- matically corrected, if needed. the polarityok status bit shows the true state of the incoming polarity independent of the polaritydis control bit. thus, if polaritydis is clear and polarityok is clear, then the receive polarity is inverted, and corrected. crs this bit tells the host the status of an incoming frame. if crs is set, a frame is currently being received. crs remains asserted un til the end of frame (eof). at eof, crs goes inactive in about 1.3 to 2.3 bit times after the last lo w-to-high transition of the recovered data. reset value is: 0000 0000 0001 0100 76543210 linkok 010100 fedcba9 8 crs polarityok 10bt aui
64 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 4.4.18 register 15: self control (selfctl, read/write, address: packetpage base + 0114h) selfctl controls the operation of the led outputs and the lower-power modes. 010101 these bits provide an internal address used by the cs8900a to identify this as the chip self control register. reset when set, a chip-wid e reset is initiated immediately. reset is an act-once bit. this bit is cleared as a result of the reset. swsuspend when set, the cs8900a enters the software initiated suspend mode. upon entering this mode, there is a partial reset. all registers and circui ts are reset except for the isa i/o base address register and the selfctl register. there is no transmit nor receive activity in this mode. to come out of software suspend, the host issues an i/o write within the cs8900a's assigned i/o space (see section 3.7 on page 27 for a complete description of the cs8900a's low-power modes). hwsleepe when set, the sleep input pin is enabled. if sleep is high, the cs8900a is "awake", or oper- ative (unless in swsuspend mode, as shown above). if sleep is low, the cs8900a enters ei- ther the hardware standby or hardware suspend mode. when clear, the cs8900a ignores the sleep input pin (see section 3.7 on page 27 for a complete description of the cs8900a's low- power modes). hwstandbye if hwsleepe is set and the sleep input pin is low, then when hwstandbye is set, the cs8900a enters the hardware standby mode. wh en clear, the cs8900a enters the hardware suspend mode (see section 3.7 on page 27 for a complete description of the cs8900a's low- power modes). hc0e the linkled or hc0 output pin is selected with this cont rol bit. when hc0e is clear, the output pin is linkled . when hc0e is set, the output pin is hc0 and the hcb0 bit (bit e) controls the pin. hc1e the bstatus or hc1 output pin is selected with this co ntrol bit. when hc1e is clear, the out- put pin is bstatus and indicates receiver isa bus activi ty. when hc1e is set, the output pin is hc1 and the hcb1 bit (bit f) controls the pin. hcb0 when hc0e (bit c) is set, this bit controls the hc0 pin. if hcb0 is set, hc0 is low. if hcb0 is clear, hc0 is high. hc0 may drive an led or a logic ga te. when hc0e (bit c) is clear, this con- trol bit is ignored. hcb1 when hc1e (bit d) is set, this bit controls the hc1 pin. if hcb1 is set, hc1 is low. if hcb1 is clear, hc1 is high. hc1 may drive an led or a logic gate. wh en hc1e (bit d) is clear, this con- trol bit is ignored. after reset, if no eeprom is found by the cs8900a, then the register has th e following initial st ate. if an eeprom is found, then the register's initial value may be set by the eeprom. see section 3.3 on page 19. reset value is: 0000 0000 0001 0101 76543210 reset 010101 fedcba9 8 hcb1 hcb0 hc1e hc0e hw standby hwsleepe sw suspend
ds271f5 65 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 4.4.19 register 16: self status (selfst, read-only, address: packetpage base + 0136h) selfst reports the status of the eeprom interface and the initialization process. 010110 these bits provide an internal address used by the cs8900a to identify this as the chip self status register. when reading this register, these bits will be 010110, wher e the lsb corre- sponds to bit 0. 3,3vactive if the cs8900a is operating on a 3.3v supply, this bit is set. if the cs8900a is operating on a 5v supply, this bit is clear. initd if set, the cs8900a initialization, incl uding read-in of the eeprom, is complete. sibusy if set, the eecs output pin is high indicating that the eeprom is currently bein g read or pro- grammed. the host must not write to packetpage base + 0040h nor 0042h until sibusy is clear. eeprompresent if the eedatain pin is low after reset, th ere is no eeprom present, and the ee prompresent bit is clear. if the eedatain pin is high after reset, the cs8900a "assumes" that an eeprom is present, and this bit is set. eepromok if set, the checksum of the eeprom readout was ok. elpresent if set, external logic for latchable address bus decode is present. eesize this bit shows the size of the attached eep rom and is valid only if the eeprompresent bit (bit 9) and eepromok bit (bit a) are both set. if clear, the eeprom size is either 128 words ('c56 or 'cs56) or 256 words (c66 or 'cs66). if set, the eeprom size is 64 words ('c46 or 'cs46). reset value is: 0000 0000 0001 0110 4.4.20 register 17: bus control (busctl, read/write, address: packetpage base + 0116h) busctl controls the operation of the isa-bus interface. 010111 these bits provide an internal address used by the cs8900a to identify this as the bus control register. 76543210 initd 3.3v active 010110 fedcba9 8 eesize elpresent eeprom ok eeprom present sibusy 76543210 reset rxdma 010111 fedcba9 8 enableirq rxdma size ioch rdye dmaburst memorye usesa dmaextend
66 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet resetrxdma when set, the rxdma offs et pointer at packetpage base + 0026h is reset to zero. when the host sets this bit, the cs8900a does the following: 1.terminates the current receive dma activity, if any. 2.clears all in ternal receive buffers. 3.zeroes the rxdma offset pointer. dmaextend when set, dmarqx goes in active on the falling edge of ior n instead of the rising edge of ior n -1 . see switching characteristics, dma read, t dmar5 . setting this bit also enables single transfer mode dma. normal operation is demand mode dma in which dmackx cannot deas- sert until after dmarqx deasserts, i.e. until a full ethernet frame is transferred. single transfer mode allows dmackx to deassert between each dma read. usesa when set, the memcs16 pin goes low whenever the address on sa bus [12..19] match the cs8900a's assigned memory base address and the chipsel pin is low (internal address de- code). when clear, memcs16 is driven low whenever chipsel goes low. (external address decode). see section 4.9 on page 73. for memcs16 pin to be enabled, the cs8900a must be in memory mode with the memorye bit (register 17, busctl, bit a) set. memorye when set, the cs8900a may operate in memory mode. when clear, memory mode is disabled. i/o mode is always enabled. dmaburst when clear, the cs8900a performs continuo us dma until the receiv e frame is completely transferred from the cs8900a to host memory. when set, each dma access is limited to 28us, after which time the cs8900a gives up the bus for 1.3us before making a new dma request. iochrdye when set, the cs8900a does not use the iochrdy ou tput pin, and the pi n is always high-im- pedance. this allows external pull-up to force t he output high. when clea r, the cs8900a drives iochrdy low to request additional time duri ng i/o read and memory read cycles. iochrdy does not affect i/o write, memory write, nor dma read. rxdmasize this bit determines the size of the receive dm a buffer (located in host memory). when set, the dma buffer size is 64 kbytes. when clear, it is 16 kbytes. enablerq when set, the cs8900a will generate an interrupt in response to an interrupt event (section 5.1). when cleared, the cs890 0a will not generate any interrupts. after reset, if no eeprom is found by the cs8900a, then the register has th e following initial st ate. if an eeprom is found, then the register's initial value may be set by the eeprom. see section 3.3 on page 19. reset value is: 0000 0000 0001 0111 4.4.21 register 18: bus status (busst, read-only, address: packetpage base + 0138h) busst describes the status of the current transmit operation. 011000 these bits provide an internal address used by the cs8900a to identify this as the bus status 76543210 txbiderr 011000 fedcba9 8 rdy4tx now
ds271f5 67 cs8900a crystal lan? ethernet controller cirrus logic product datasheet register. when reading this register, these bits will be 01100 0, where the lsb corresponds to bit 0. txbiderr if set, the host has command ed the cs8900a to transmit a frame that the cs8900a will not send. frames that the cs8900a will not send are: 1) any frame greater than 1514 bytes, provided that inhibitcrc (register 9, txcmd, bit c) is clear. 2) any frame greater than 1518 bytes. note that this bit is not set wh en transmit frames are too short. rdy4txnow rdy4txnow signals the host that the cs890 0a is ready to accept a frame from the host for transmission. this bit is similar to rdy4tx (register c, bufevent, bit 8) except that there is no interrupt associated with rdy4txnow. th e host can poll the cs8900a and check rdy4txnow to determine if the cs8900a is ready for transmit. (see section 5.6 on page 99 for a description of the transmit bid process.) reset value is: 0000 0000 0001 1000 4.4.22 register 19: test control (testctl, read/write, address: packetpage base + 0118h) testctl controls the diagnostic test modes of the cs8900a. 011001 these bits provide an internal address used by the cs8900a to identify this as the test control register. disablelt when set, the 10base-t interf ace allows packet tran smission and receptio n regardless of the link status. disablelt is used in conjunction with the linkok (register 14, linest, bit 7) as fol- lows: linkok disablelt 0 0 no packet transmission or reception allowed. transmitter sends link pulses. 0 1 disablelt overrides linkok to allow packet transmission and reception. 1 x disable has no meaning if linkok = 1. endecloop when set, the cs8900a enters internal loopback mode where the internal manchester encoder output is connected to the decoder input. th e 10base-t and aui transmitters and receivers are disabled. when clear, the cs8900a is configured for normal operation. auiloop when set, the cs8900a allows reception while transmitting. th is facilitates loopback tests for the aui. when clear, the cs8900a is configured for normal aui operation. 76543210 disablelt 011001 fedcba9 8 fdx disable back- off auiloop endec loop
68 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet disable backoff when set, the backoff algorithm is disabl ed. the cs8900a transmitter looks only for completion of the inter packet gap before starting transmission . when clear, the backoff algorithm is used. fdx when set, 10base-t full duplex mode is enabled and crs (register 14, linest, bit e) is ig- nored. this bit must be set wh en performing loopback tests on the 10base-t port. when clear, the cs8900a is configured for stan dard half-duplex 10base-t operation. at reset, if no eeprom is found by the cs8900a, then the register has the follo wing initial state. if an eeprom is found, then the register?s init ial value may be set by the eepr om. see section 3.3 on page 19. reset value is: 0000 0000 0001 1001 4.4.23 register 1c: aui time domain reflectometer (read-only, address: packetpage base + 013ch) the tdr counter (bits 6 through f) is a time domain reflec tometer useful in locating cable faults in 10base-2 and 10base-5 coax networks. it counts at a 10 mhz rate fr om the beginning of transmissi on on the aui to when a col- lision or loss-of-carrier error occurs. the tdr counter is cleared when read. 011100 these bits provide an internal address used by the cs8900a to identify this as the bus status register. when reading this register, these bits will be 01110 0, where the lsb corresponds to bit 0. aui-delay the upper ten bits contains the number of 10 mhz clock periods between the beginning of transmission on the aui to when a collis ion or loss-of-carr ier error occurs. reset value is: 0000 0000 0001 1100 76543210 aui delay 011100 fedcba9 8 aui delay
ds271f5 69 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 4.5 initiate transmit registers 4.5.1 transmit comm and request - txcmd (write-only, address: packetpage base + 0144h) the word written to packetpage base + 0144h tells the cs8900a how the ne xt packet should be transmitted. this packetpage location is write-only, and the written word can be read from register 9, at packetpage base + 0108h. the cs8900a does not transmit a frame if txlength (at packetpage location base + 0146h) is less than 3. see section 5.6 on page 99. 001001 these bits provide an internal address used by the cs8900a to identify this as the transmit command register. when reading this register, these bits will be 001001, where the lsb cor- responds to bit 0. txstart this pair of bits determines how many bytes are transferred to the cs8900a before the mac starts the packet transmit process. bit 7 bit 6 0 0 start transmissi on after 5 bytes are in the cs8900a 0 1 start transmission after 381 bytes are in the cs8900a 1 0 start transmission after 1021 bytes are in the cs8900a 1 1 start transmission after the entire frame is in the cs8900a force when set in conjunction with a new transmit co mmand, any transmit frames waiting in the trans- mit buffer are deleted. if a previous packet has started transmission, that packet is terminated within 64 bit times with a bad crc. onecoll when this bit is set, any transmission will be terminated after only one collision. when clear, the cs8900a allows up to 16 normal collisio ns before terminating the transmission. inhibitcrc when set, the crc is not appended to the transmission. txpaddis when txpaddis is clear, if the host gives a transmit length less than 60 bytes and inhibitcrc is set, then the cs8900a pads to 60 bytes. if t he host gives a transmit length less than 60 bytes and inhibitcrc is clear, then the cs8900a pads to 60 bytes and appends the crc. when txpaddis is set, the cs8900a allows the transmission of runt frames (a frame less than 64 bytes). if inhibitcrc is clear, the cs89 00a appends the crc. if i nhibitcrc is set, the cs8900a does not append the crc. since this register is wr ite-only, it?s initial stat e after reset is undefined. 4.5.2 transmit length (write-only, address: packetpage base + 0146h) this register is used in conjunction with register 9, txcmd. when a transm ission is initiated via a command in tx- 76543210 txstart 001001 fedcba9 8 txpaddis inhibitcrc onecoll force address 0147h address 0146h most-significant byte of transmit frame length lea st-significant byte of transmit frame length
70 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet cmd, the length of the transm itted frame is written into th is register. the length of the transmitted frame may be modified by the configuration of th e txpaddis and inhibitcrc bits in th e txcmd register. see table 36, and section 5.6 on page 99. txlength must be >3 and < 1519. since this register is wr ite-only, it?s initial stat e after reset is undefined.
ds271f5 71 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 4.6 address filter registers 4.6.1 logical address filter (hash table) (read/write, address: packetpage base + 0150h) the cs8900a hashing decoder circuitry compares its output with one bit of the logical address filter register. if the decoder output and the logical address filter bit ma tch, the frame passes the hash filter and the hashed bit (register 4, rxevent, bit 9) is set. see section 5.2.10 on page 87. reset value is: 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4.6.2 individual a ddress (ieee address) (read/write, address: packetpage base + 0158h) the unique, ieee 48 -bit individual addr ess (ia) begins at 0158h. the first bit of the ia (bit ia[00]) must be "0". see section 5.2.10 on page 87. the value of this register must be lo aded from external storag e, for example, from t he eeprom. see section 3.3 on page 19. if the cs8900a is not able to load the ia from the eeprom, then afte r a reset this register is undefined, and the driver must write an address to this register. address 0157h address 0156h address 0155h address 0154h address 0153h address 0152h address 0151h address 0150h most-signifi- cant byte of hash filter. least-signifi- cant byte of hash filter. address 0015dh address 0015ch address 0015bh address 0015ah address 0159h address 00158h octet 5 of ia octet 0 of ia
72 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 4.7 receive and transmit frame locations the receive and transmit frame packetpage locations are used to tr ansfer ethernet frames to and from the host. the host sequentially writes to and reads from these locations, and internal buffer memory is dynamically allocat- ed between transmit and receive as needed. one receive frame and one transmit frame are accessible at a time. 4.7.1 receive packetpage locations in io mode, the receiv e status/length/frame lo- cations are read through repetitive reads from one io port at the io base address. see section 4.10 on page 75. in memory mode, the receive sta- tus/length/frame locations are read using memory reads of a block of memory starting at memory base address + 0400h. typically the memory locations are read sequentially using repetitive move inst ructions (rep movs). see section 4.9 on page 73. random access is not needed. however, the first 118 bytes of the re ceive frame can be ac- cessed randomly if wo rd reads, on even word boundaries, are used. bey ond 118 bytes, the memory reads must be s equential. byte reads, or reads on odd-word boundaries, can be per- formed only in sequential read mode. see section 4.8 on page 72. the rxstatus word repor ts the status of the current received frame. rxevent register 4 (packetpage base + 0124h) has the same contents as the rxstatus register, except rx- event is cleared when rxevent is read. the rxlength (receive length) word is the length, in bytes, of t he data to be transferred to the host across the isa bus. the register de- scribes the length from the start of destination address to the end of crc, assuming that crc has been selected (v ia register 3 rx- cfg, bit buffercrc). if crc has not been se- lected, then the length does not include the crc, and the crc is not present in the re- ceive buffer. after the rxlength has been read, the receive frame can be read. when some portion of the frame is read, the enti re frame should be read before reading the rxevent register either di- rectly or through the is q register. reading the rxevent register signals to the cs8900a that the host is finished with the current frame, and wants to start processing the next frame. in this case, the current fr ame will no longer be accessible to the host. the current frame will also become inaccessi ble if a skip command is issued, or if the entire frame has been read. see section 5.2 on page 78. 4.7.2 transmit locations the host can write frames into the cs8900a buffer using memory wr ites using rep movs to the txframe locati on. see section 5.6 on page 99. 4.8 eight and sixt een bit transfers a data transfer to or fr om the cs8900a can be done in either i/o or memory space, and can be either 16 bits wide (w ord transfers) or 8 bits wide (byte transfers). because the cs8900a?s internal architecture is based on a 16-bit data bus, word transfers ar e the most efficient. to transfer transmit fr ames to the cs8900a and receive frames from the cs8900a, the host may mix word and byte transfers, provid- ed it follows three rules: 1) the primary method used to access cs8900a memo ry is word access. 2) word accesses to the cs8900a?s internal memory are kept on even-byte boundaries. 3) when switching from byte accesses to word accesses, a byte access to an even
ds271f5 73 cs8900a crystal lan? ethernet controller cirrus logic product datasheet byte address must be followed by a byte access to an odd-byte address before the host may execute a word access (this will realign the word trans fers to even-byte boundaries). on the other hand, a byte ac- cess to an odd-byte address may be fol- lowed by a word access. failure to observe t hese three rules may cause data corruption. 4.8.1 transferring odd-byte-aligned data some applications ga ther transmit data from more than one section of host memory. the boundary between the vari ous memory loca- tions may be either ev en- or odd-byte aligned. when such a boundary is odd-byte aligned, the host should transfer the last byte of the first block to an even address, followed by the first byte of the second bl ock to the following odd address. it can then resume word transfers. an example of this is shown in figure 17. 4.8.2 random access to cs8900a mem- ory the first 118 bytes of a receive frame held in the cs8900a?s on-chip memory may be ran- domly accessed in memory mode. after the first 118 bytes, only s equential access of re- ceived data is allowed. either byte or word ac- cess is permitted, as long as all word accesses are executed to even-byte boundaries. 4.9 memory mode operation to configure the cs89 00a for memory mode, the packetpage memory must be mapped into a contiguous 4-kbyte block of host memory. the block must start at an x000h boundary, with the packetpage base address mapped to x000h. when the cs8900a comes out of re- set, its default configur ation is i/o mode. once memory mode is sele cted (by setting the memory e bit (busctl r egister)), all of the cs8900a?s registers can be accessed directly. in memory mode, t he cs8900a supports standard or ready bus cycles without intro- ducing additional wait states. memory moves can use movd (double-word transfers) as long as the cs8900a?s memory base address is on a double word boundary. since 286 processors don?t support the movd instruction, word and byte transfers must be used with a 286. 4.9.1 accesses in memory mode the cs8900a allows read/write access to the internal packetp age memory, and read access of the optional boot prom. (see section 3.7 on page 27 fo r a description of the optional boot prom.) a memory access occurs when all of the fol- lowing are true: word transfer word transfer byte transfer word transfer word transfer byte transfer word transfer word transfer first block of data second block of data figure 17. odd-byte aligned data description mnemonic read/write location: pocketpage base + receive status rxstatus read-only 0400h-0401h receive length rxlength read-only 0402h-0403h receive frame rxframe read-only starts at 0404h transmit frame txframe write-only starts at 0a00h table 17. receive/transmit memory locations
74 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet ? the address on the is a system address bus (sa0 - sa19) is within the memory space range of the cs8900a or boot prom. ? the chipsel input pin is low. ? either the memr pin or the memw pin is low. 4.9.2 configuring the cs8900a for mem- ory mode there are two different methods of configuring the cs8900a for memory mode operation. one method allows the cs8900a's internal memory to be mapped anywhere within the host system's 24-bit memo ry space. the other method limits memory ma pping to the first 1 mbyte of host memory space. general memory mode operation: configuring the cs8900a so that its internal memory can be mapped anywhere within host memory space requires the following: ? a simple circuit must be added to decode the latchable addre ss bus (la20 - la23) and the bale signal. ? the host must configur e the external logic with the correct address range as follows: 1) check to see if t he initd bit (register 16,selfst, bit 7) is set, indicating that initialization is complete. 2) check to see if t he elpresent bit (reg- ister 16, selfst, bit b) is set. this bit in- dicates that external logic for the la bus decode is present. 3) set the elsel bit of the eeprom command register to activate the elcs pin for use with the external de- code circuit. 4) configure the exter nal logic serially. ? the host must write the memory base ad- dress into the memory base address reg- ister (packetpage base + 002ch); ? the host must set the memorye bit (regis- ter 17, busctl, bit a); and ? the host must set the usesa bit (register 17, busctl, bit 9). limiting memory mode to the first 1 mbyte of host memory space: configuring the cs8900a so that its in ternal memory can be mapped only within the first 1 mbyte of host memory space requi res the following: ? the chipsel pin must be tied low; ? the isa-bus smemr si gnal must be con- nected to the memr pin; ? the isa-bus smemw signal must be con- nected to the memw pin; ? the host must write the memory base ad- dress into the memory base address reg- ister (packetpage base + 002ch); ? the host must set the memorye bit (regis- ter 17, busctl, bit a); and ? the host must clear the usesa bit (register 17, busctl, bit 9). 4.9.3 basic memory mode transmit memory mode transmit oper ations occur in the following order (using interrupts): 1) the host bids for storage of the frame by writing the transmit command to the txc- md register (memory base + 0144h) and the transmit frame l ength to the txlength register (memory base + 0146h). if the transmit length is erroneous, the command is discarded and the tx biderr bit (register 18, busst, bit 7) is set. 2) the host reads the bu sst register (regis- ter 18, memory base + 0138h). if the rdy4txnow bit (bit 8) is set, the frame
ds271f5 75 cs8900a crystal lan? ethernet controller cirrus logic product datasheet can be written. if cl ear, the host must wait for cs8900a buffer memory to become available. if rdy4txie (register b, buf- cfg, bit 8) is set, t he host will be interrupt- ed when rdy4tx (regist er c, bufevent, bit 8) becomes set. 3) once the cs8900a is ready to accept the frame, the host execut es repetitive memo- ry-to-memory move instructions (rep movs) to memory base + 0a00h to trans- fer the entire frame from host memory to cs8900a memory. for a more detailed de scription of transmit, see section 5.6 on page 99. 4.9.4 basic memory mode receive memory mode receive operations occur in the following order (interrupts used to signal the presence of a valid receive frame): 1) a frame is received by the cs8900a, trig- gering an enabled interrupt. 2) the host reads the in terrupt status queue (memory base + 0120h) and is informed of the receive frame. 3) the host reads rxstatus (memory base + 0400h) to learn the status of the receive frame. 4) the host reads rxlength (memory base + 0402h) to learn the frame's length. 5) the host reads the frame data by execut- ing repetitive memory-to-memory move in- structions (rep movs) from memory base + 0404h to transfer t he entire frame from cs8900a memory to host memory. for a more detailed desc ription of receive, see section 5.2 on page 78. 4.9.5 polling the cs8900a in memory mode if interrupts are not us ed, the host can poll the cs8900a to check if receive frames are pres- ent and if memory space is available for trans- mit. however, this is beyond the scope of this data sheet. 4.10 i/o space operation in i/o mode, packetpag e memory is accessed through eight 16-bit i/ o ports that are mapped into 16 contiguous i/o locations in the host system's i/o space. i/o mode is the default configuration for the cs8900a and is always enabled. on power up, the default value of the i/o base address is se t at 300h. (note that 300h is typically assigne d to lan peripherals). the i/o base address may be changed to any available xxx0h location, either by loading configuration data from the eeprom, or dur- ing system setup. table 18 shows the cs8900a i/o mode mapping. 4.10.1 receive/transm it data ports 0 and 1 these two ports are used when transferring transmit data to the cs8900a and receive data from the cs8900a. po rt 0 is used for 16- bit operations and ports 0 and 1 are used for 32-bit operations (lower-o rder word in port 0). 4.10.2 txcmd port the host writes the transmit command (txc- md) to this port at the st art of each transmit op- offset type description 0000h read/write receive/transmit data (port 0) 0002h read/write receive/transmit data (port 1) 0004h write-only txcmd (transmit command) 0006h write-only txlength (transmit length) 0008h read-only interrupt status queue 000ah read/write packetpage pointer 000ch read/write packetpage data (port 0) 000eh read/write packetpage data (port 1) table 18. i/o mode mapping
76 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet eration. the transmi t command tells the cs8900a that the hos t has a frame to be transmitted, as well as how that frame should be transmitted. this por t is mapped into pack- etpage base + 0144h. se e register 9 in section 4.4 on page 49 for more information. 4.10.3 txlength port the length of the fram e to be transmitted is written here immediatel y after the transmit command is written. this port is mapped into packetpage base + 0146h. 4.10.4 interrupt status queue port this port contains the current value of the in- terrupt status queue (isq ). the isq is located at packetpage base + 0120h. for a more de- tailed description of the isq, see section 5.1 on page 78. 4.10.5 packetpage pointer port the packetpage pointer port is written when- ever the host wishes to access any of the cs8900a's internal regist ers. the first 12 bits (bits 0 through b) prov ide the internal address of the target register to be accessed during the current operation. the next three bits (c, d, and e) are read-only and will always read as 011b. any convenient value may be written to these bits when writing to the packetpage pointer port. the last bit (bit f) indicates whether or not the pa cketpage pointer should be auto-incremented to the next word location. figure 18 shows the st ructure of the packet- page pointer. 4.10.6 packetpage data ports 0 and 1 the packetpage data ports are used to trans- fer data to and from an y of the cs8900a's in- ternal registers. port 0 is used for 16-bit operations and port 0 an d 1 are used for 32-bit operations (lower-order word in port 0). 4.10.7 i/o mode operation for an i/o read or writ e operation, the aen pin must be low, and the 16-bit i/o address on the isa system addr ess bus (sa0 - sa15) must match the address space of the cs8900a. for a read, the ior pin must be low, and for a write, the iow pin must be low. note: the isa latchable address bus (la17 - la23) is not needed for applications that use only i/o mode and receive dma operation. 4.10.8 basic i/ o mode transmit i/o mode transmit operatio ns occur in the fol- lowing order (using interrupts): 1) the host bids for storage of the frame by writing the transmit command to the txc- md port (i/o base + 0004h) and the trans- mit frame length to the txlength port (i/o base + 0006h). 2) the host reads the bu sst register (regis- ter 18) to see if the rdy4txnow bit (bit 8) is set. to read the busst register, the host must first set the packetpage pointer at the correct location by writing 0138h to the packetpage pointer port (i/o base + 000ah). it can then r ead the busst regis- ter from the packetpage data port (i/o 10 32 5 4 76 packetpage register address 98 ba dc f e i/o base + 000bh i/o base + 000ah bit f: 0 = pointer remains fixed 1 = auto-increments to next word location figure 18. packetpage pointer
ds271f5 77 cs8900a crystal lan? ethernet controller cirrus logic product datasheet base + 000ch). if rdy4txnow is set, the frame can be written. if clear, the host must wait for cs8900a buffer memory to be- come available. if rdy4txie (register b, bufcfg, bit 8) is set, the host will be inter- rupted when rdy4tx (register c, bufe- vent, bit 8) becomes set. if the txbiderr bit (register 18, busst, bit 7) is set, the trans- mit length is not valid. 3) once the cs8900a is ready to accept the frame, the host executes repetitive write in- structions (rep ou t) to the re- ceive/transmit data port (i/o base + 0000h) to transfer t he entire frame from host memory to cs8900a memory. for a more detailed de scription of transmit, see section 5.6 on page 99. 4.10.9 basic i/ o mode receive i/o mode receive operati ons occur in the fol- lowing order (in this ex ample, interrupts are enabled to signal the presence of a valid re- ceive frame): 1) a frame is received by the cs8900a, trig- gering an enabled interrupt. 2) the host reads the in terrupt status queue port (i/o base + 0008h) and is informed of the receive frame. 3) the host reads the frame data by execut- ing repetitive read inst ructions (rep in) from the receiv e/transmit da ta port (i/o base + 0000h) to tran sfer the frame from cs8900a memory to host memory. pre- ceding the frame data are the contents of the rxstatus register (packetpage base + 0400h) and the rxlength register (packet- page base + 0402h). for a more detailed description of receive, see section 5.2 on page 78. 4.10.10 accessing in ternal registers to access any of the cs8900a's internal reg- isters in i/o mode, the host must first setup the packetpage pointer. it do es this by writing the packetpage address of th e target register to the packetpage pointer port (i/o base + 000ah). the contents of the target register is then mapped into the packetpage data port (i/o base + 000ch). if the host needs to a ccess a sequential block of registers, the msb of the packetpage ad- dress of the first word to be accessed should be set to "1". the packetpage pointer will then move to the next word location automatically, eliminating the need to setup the packetpage pointer between successive accesses (see figure 18). 4.10.11 polling the cs8900a in i/o mode if interrupts are not us ed, the host can poll the cs8900a to check if receive frames are pres- ent and if memory space is available for trans- mit.
78 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 5.0 operation 5.1 managing interrupts and servicing the interrupt status queue the interrupt status queue (isq) is used by the cs8900a to communica te event reports to the host processor. whenever an event occurs that triggers an enabled interrupt, the cs8900a sets the appropria te bit(s) in one of five registers, maps the contents of that regis- ter to the isq, and drives the selected interrupt request pin high (if an earli er interrupt is wait- ing in the queue, the inte rrupt request pin will already be high). when t he host services the interrupt, it must first read the isq to learn the nature of the interrupt. it can then process the interrupt (the first read to the isq causes the interrupt request pin to go low.) three of the registers mapped to the isq are event registers: rxeven t (register 4), txevent (register 8), and bufeve nt (register c). the other two registers ar e counter-overflow re- ports: rxmiss (register 10) and txcol (reg- ister 12). there may be more than one rxevent report and/or more than one txevent report in the isq at a time. however, there may be only one bufevent report, one rxmiss report and one txcol repo rt in the isq at a time. event reports stored in the isq are read out in the order of priority, with rxevent first, fol- lowed by txevent, bufevent, rxmiss, and then txcol. the host only needs to read from one location to get the interrupt currently at the front of the queue. in memory mode, the isq is located at packetpage base + 0120h. in i/o mode, it is located at i/o base + 0008h. each time the host reads the is q, the bits in the cor- responding register are cleared and the next report in the queue mo ves to the front. when the host starts r eading the isq, it must read and process all event reports in the queue. a read-out of a nul l word (0000h) indi- cates that all interr upts have been read. the isq is read as a 16- bit word. the lower six bits (0 through 5) cont ain the register number (4, 8, c, 10, or 12). the upper ten bits (6 through f) contain the register contents. the host must always read th e entire 16-bit word. the active interrupt pi n (intrqx) is selected via the interrupt number register (packetpage base + 22h). as an additional option, all of the interrupt pins can be 3-stated using the same register. see section 4.3 on page 44. an event triggers an in terrupt only when the enableirq bit of the bus control register (bit f of register 17) is set. after the cs8900a has generated an interrupt, the first read of the isq makes the intrq output pin go low (inactive). intrq remains low until the null word (0000h) is read from the isq, or for 1.6us, whichever is longer. 5.2 basic receive operation 5.2.0.1 overview once an incoming packet has passed through the analog front end and manchester decoder, it goes through the fo llowing three-step re- ceive process: 1) pre-processing 2) temporary buffering 3) transfer to host figure 20 shows the steps in frame reception. as shown in the figure, all receive frames go through the same pre-processing and tempo- rary buffering phases, regardless of transfer method once a frame has been pre-processed and buffered, it can be acce ssed by the host in ei- ther memory or i/o space. in addition, the cs8900a can transfer rece ive frames to host
ds271f5 79 cs8900a crystal lan? ethernet controller cirrus logic product datasheet an enabled interrupt occurs. the selected interrupt request pin is driven high (active) if not already high. isq = 0000h? yes the host reads the isq. the selected interrupt request pin is driven low. no process applicable rxevent bits: extradata, runt, crcerror, rxok. process applicable txevent bits: 16coll, jabber, out-of-window, txok. process applicable bufevent bits: rxdest, rx128, rxmiss, txunderrun, rdy4tx, rxdmaframe, swint. process rxmiss counter. process txcol counter. which event report type? rxevent txevent bufevent rxmiss txcol none of the above service default exit. interrupts re-enabled. (interrupts will be disabled for at least 1.6 us.) figure 19. interrupt status queue
80 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet memory via host dma. this section describes receive frame pre-processing and memory and i/o space receive operation. section 5.3 on page 90 through section 5.4 on page 94 describe dma operation. 5.2.1 terminology: packet, frame, and transfer the terms packet, fram e, and transfer are used extensively in the following sections. they are defined below for clarity: 5.2.1.1 packet the term "packet" refers to the entire serial string of bits transmit ted over an ethernet net- work. this includes th e preamble, start-of- frame delimiter (sfd), destination address (da), source address (s a), length field, data field, pad bits (if necessary), and frame check sequence (fcs, also ca lled crc). figure 9 shows the format of a packet. 5.2.1.2 frame the term "frame" refers to the portion of a packet from the da to the fcs. this includes the destination address (da), source address (sa), length field, data fi eld, pad bits (if nec- essary), and frame c heck sequence (fcs, also called crc). figure 9 shows the format of a frame. the term "frame data" refers to all the data from the da to the fc s that is to be trans- mitted, or that has been received. 5.2.1.3 transfer the term "transfer" refers to moving data across the isa bus, to and from the cs8900a. during receive operations, only frame data are transferred from the cs 8900a to the host (the preamble and sfd are stripped off by the cs8900a's mac engine). the fcs may or may not be transferred, depending on the con- figuration. all transfe rs to and from the cs8900a are counted in bytes, but may be padded for double word alignment. 5.2.2 receive configuration after each reset, the cs890 0a must be config- ured for receive operat ion. this can be done automatically using an attached eeprom or by writing configuration commands to the cs8900a's internal regi sters (see section 3.4 on page 21). the items that must be config- ured include: ? which physical interface to use; ? which types of frames to accept; ? which receive even ts cause interrupts; and, ? how received frames are transferred. yes no use dma? frame held on chip frame dmaed to host memory host reads frame from host memory frame pre- processed frame temporarily buffered packet received preamble and start-of-frame delimiter removed host reads frame from cs8900a memory figure 20. frame reception
ds271f5 81 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 5.2.2.1 configuring the physical interface configuring the physical interface consists of determining which ether net interface should be active, and enabling t he receive logic for serial reception. this is done via the linectl register (register 13 ) and is described in table19. 5.2.2.2 choosing whic h frame types to ac- cept the rxctl register (regi ster 5) is used to de- termine which frame type s will be accepted by the cs8900a (a receive frame is said to be "accepted" when the fram e is buffered, either on chip or in host memo ry via dma). table 20 describes the configuration bits in this register. refer to section 5.2.10 on page 87 for a de- tailed description of dest ination address filter- ing. 5.2.2.3 selecting which events cause inter- rupts the rxcfg register (register 3) and the buf- cfg register (register b) are used to deter- mine which receive events will cause interrupts to the host processor. table 22 de- scribes the interrupt enable (ie) bits in these registers. 5.2.2.4 choosing ho w to transfer frames the rxcfg register (regi ster 3) and the bus- ctl register (register 17) are used to deter- register 13, linectl bit bit name operation 6 serrxon when set, reception enabled. 8 auionly when set, aui selected (takes precedence over autoaui/10bt). 9 autoaui/10bt when set, automatic interface selection enabled. when both bits 8 and 9 are clear, 10base-t selected. e lorx squelch when set, receiver squelch level reduced by approximately 6 db. table 19. physical interface configuration register 5, rxctl bit bit name operation 6 iahasha when set, individual address frames that pass the hash filter are accepted*. 7promis cuousa when set, all frames are accepted*. 8 rxoka when set, frames with valid length and crc and that pass the da filter are accepted. 9 multicasta when set, multicast frames that pass the hash filter are accepted*. * must also meet the criteria programmed into bits 8, c, d, and e. table 20. frame acceptance criteria a individuala when set, frames with da that matches the ia at packetpage base + 0158h are accepted*. bbroad- casta when set, all broadcast frames are accepted*. c crcerrora when set, frames with bad crc that pass the da filter are accepted. d runta when set, frames shorter than 64 bytes that pass the da filter are accepted. e extradataa when set, frames longer than 1518 bytes that pass the da filter are accepted (only the first 1518 bytes are buffered). register 3, rxcfg bit bit name operation 8 rxokie when set, there is an interrupt if a frame is received with valid length and crc*. c crcerrorie when set, ther e is an interrupt if a frame is received with bad crc*. d runtie when set, there is an interrupt if a frame is received th at is shorter than 64 bytes*. e extradataie when set, there is an interrupt if a frame is received that is longer than 1518 bytes*. * must also pass the da filter before there is an interrupt. table 21. register 5, rxctl bit bit name operation * must also meet the criteria programmed into bits 8, c, d, and e. table 20. frame acceptance criteria
82 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet mine how frames will be transferred to host memory, as described in table 23. 5.2.3 receive fram e pre-processing the cs8900a pre-processes all receive frames using a f our step process: 1) destination a ddress filtering; 2) early interrupt generation; 3) acceptance f iltering; and, 4) normal interrupt generation. figure 21 provides a diagram of frame pre- processing. 5.2.3.1 destination address filtering all incoming frames are passed through the destination address filt er (da filter). if the frame's da passes the da filter, the frame is passed on for further pre-processing. if it fails the da filter, the frame is discarded. see section 5.2.10 on page 87 for a more detailed description of da filtering. 5.2.3.2 early in terrupt generation the cs8900a support the following two early interrupts that can be used to inform the host that a frame is being received: ? rxdest: the rxdest bit (register c, bufe- vent, bit f) is set as soon as the destina- tion address (da) of the incoming frame passes the da filter. if the rxdestie bit (register b, bufcfg, bit f) is set, the cs8900a generates a co rresponding inter- rupt. once rxdest is set, the host is al- lowed to read the incoming frame's da (the first 6 bytes of the frame). ? rx128: the rx128 bit (register c, bufe- vent, bit b) is set as soon as the first 128 bytes of the incoming frame have been re- ceived. if the rx128ie bit (register b, buf- cfg, bit b) is set, the cs8900a generates a corresponding interrupt. once the rx128 bit is set, the rxdest bit is cleared and the host is allowed to read the first 128 bytes of the incoming frame. the rx128 bit is cleared by the host reading the bufevent register (either direct ly or through the inter- rupt status queue) or by the cs8900a de- register b, bufcfg bit bit name operation 7 rxdmaie when set, there is an interrupt if one or more frames are trans- ferred via dma. a rxmissie when set, there is an interrupt if a frame is missed due to insufficient receive buffer space. b rx128ie when set, there is an interrupt after the first 128 bytes of receive data have been buffered. d missovfloie when set, th ere is an interrupt if the rxmiss counter overflows. f rxdestie when set, there is an interrupt after the da of an incoming frame has been buffered. table 22. registers 3 and b interrupt configuration register 3, rxcfg bit bit name operation 7 streame when set, stream transfer enabled. 9 rxdmaonly when set, dma slave opera- tion used for all receive frames. a autorx dmae when set, auto-switch dma enabled. b buffercrc when set, the received crc is buffered. register 17, busctl bit bit name operation b dmaburst when set, dma operations hold the bus for up to approx- imately 28 s. when clear, dma operations are continu- ous. d rxdmasize when set, dma buffer size is 64 kbytes. when clear, dma buffer size is 16 kbytes. table 23. receive frame pre-processing
ds271f5 83 cs8900a crystal lan? ethernet controller cirrus logic product datasheet tecting the incoming frame's end-of-frame (eof) sequence. like all event bits, rxdest and rx128 are set by the cs8900a whenever the appropriate event occurs. unlike ot her event bits, rxdest and rx128 may be clear ed by the cs8900a without host intervention. all other event bits are cleared only by the host reading the appro- priate event register, either directly or through the interrupt status qu eue (isq). (rxdest and rx128 can also be clea red by the host reading the bufevent register, eith er directly or through the interrupt status queue). figure 22 pro- vides a diagram of the earl y interrupt process. 5.2.3.3 acceptance filtering the third step of pre-processing is to deter- mine whether or not to accept the frame by comparing the frame wi th the criteria pro- grammed into the rxctl register (register 5). if the receive frame pa sses the acceptance fil- ter, the frame is buffered , either on chip or in host memory via dma. if the frame fails the acceptance filter, it is discarded. the results of the acceptance filter ar e reported in the rx- event register (register 4). 5.2.3.4 normal interrupt generation the final step of pre-pr ocessing is to generate any enabled interrupts t hat are triggered by the incoming frame. interrupt generation oc- curs when the entire fr ame has been buffered (up to the first 1518 by tes). for more informa- tion about interrupt generation, see section 5.1 on page 78. 5.2.4 held vs. dmaed receive frames all accepted frames are ei ther held in on-chip ram until processed by the host, or stored in host memory via dma. a receive frame that is held in on-chip ram is re ferred to as a held re- ceive frame. a frame that is stored in host memory via dma is a dmaed receive frame. pass da filter? discard frame destination address filter check: - promiscuousa? - iahasha? - multicasta? - individuala? - broadcasta? receive frame yes no yes no generate interrupts check: - rxokie? - extradataie? - crcerrorie? - runtie? - rxdmaie? pre-processing complete generate early interrupts if enabled (see next figure) acceptance filter check: - rxoka? - extradataa? - runta? - crcerrora? status of receive frame reported in rxevent register, frame discarded. status of receive frame reported in rxevent register, frame accepted into on-chip ram pass accept. filter? figure 21. receive frame pre-processing
84 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet eof received? 128 bytes received? eof received? 64 bytes received? eof received? receive frame rxdest cleared and runt set. if runta is set, frame accepted and host may read frame. rxdest cleared and rxok or crcerror set, as appropriate. if rxoka or crcerrora is set, frame accepted and host may read frame. rx128 cleared and rxok, crcerror or extradata set, as appropriate. if extradataa, rxoka or crcerrora is set, frame is accepted and host may read frame. da filter passed? yes no yes no no yes yes no no yes rx128 set and rxdest cleared. host may read first 128 received bytes. yes no discard frame rxdest set. host may read the da (first 6 received bytes). figure 22. early interrupt generation
ds271f5 85 cs8900a crystal lan? ethernet controller cirrus logic product datasheet this section describes buffering and transfer- ring held receive fr ames. section 5.3 on page 90 through section 5.5 on page 96 de- scribe dmaed receive frames. 5.2.5 buffering held receive frames if space is available, an incoming frame will be temporarily stored in on-chip ram, where it awaits processing by the host. although this receive frame now occu pies on-chip memory, the cs8900a does not commit the memory space to it until one of the following two condi- tions is true: 1) the entire frame has been received and the host has learned about the frame by reading the rxevent regi ster (register 4), either directly or through the isq. or: 2) the frame has been partially received, causing either the rx dest bit (register c, bufevent, bit f) or the rx128 bit (register c, bufevent, bit b) to become set, and the host has learned about the receive frame by reading the bufevent register (register c), either directly or through the isq. when the cs8900a commits buffer space to a particular held receive frame (termed a com- mitted received frame), no data from subse- quent frames can be writ ten to that buffer space until the frame is freed from commit- ment. (the committed received frame may or may not have been received error free.) a received frame is freed from commitment by any one of the foll owing conditions: 1) the host reads the ent ire frame sequential- ly in the order that it was received (first byte in, first byte out). or: 2) the host reads part or none of the frame, and then issues a skip command by set- ting the skip_1 bit (regi ster 3, rxcfg, bit 6). or: 3) the host reads part of the frame and then reads the rxevent register (register 5), ei- ther directly or thr ough the isq, and learns of another receive frame. this condition is called an "implied skip". ensure that the host does not do ?implied skips.? both early interrupts are disabled whenever there is a committed re ceive frame waiting to be processed by the host. 5.2.6 transferring held receive frames the host can read-out held receive frames in memory or i/o space. to transfer frames in memory space, the host executes repetitive move instructions (rep movs) from packet- page base + 0404h. to transfer frames in i/o space, the host executes repetitive in instruc- tions (rep in) from i/ o base + 0000h, with status and length preceding the frame. there are three possibl e ways that the host can learn the status of a particular frame. it can: 1) read the interrupt status queue; 2) read the rxevent register directly (register4); or 3) read the rxstatus register (packetpage base + 0400h). 5.2.7 receive frame visibility only one receive frame is visible to the host at a time. the receive fram e's status can be read from the rxstatus re gister (packetpage base + 0400h), and its length can be read from the rxlength register (packetpage base + 0402h). for more information about memory space operation, see section 4.9 on page 73. for more information about i/o space opera- tion, see section 4.10 on page 75.
86 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 5.2.8 example of memory mode receive operation a common length for short frames is 64 bytes, including the 4-byte c rc. suppose that such a frame has been received with the cs8900a configured as follows: ? the buffercrc bit (reg ister 3, rxcfg, bit b) is set causing the 4-byte crc to be buff- ered with the rest of the receive data. ? the rxoka bit (register 5, rxctl, bit 8) is set, causing the cs8900a to accept good frames (a good frame is one with le- gal length and valid crc). ? the rxokie bit (register 3, rxcfg, bit 8) is set, causing an interrupt to be generated whenever a good fram e is received. then the transfer to the host would proceed as follows: 1) the cs8900a generates an rxok inter- rupt to the host to si gnal the arrival of a good frame. 2) the host reads the isq (packetpage base + 0120h) to assess the status of the re- ceive frame and sees the contents of the rxevent register (regi ster 4) with the rxok bit (bit 8) set. 3) the host reads the re ceive frame's length from the rxlength r egister (packetpage base + 0402h). 4) the host reads the frame data by execut- ing 32 consecutive mov instructions start- ing with packetpage base + 0404h. the memory map of the 64-byte frame is given in table 24. 5.2.9 receive frame byte counter the receive frame byte counter describes the number of bytes received for the current frame. the counter is incremented in real time as bytes are received from the ethernet. the byte counter can be used by the driver to de- termine how many bytes are available for reading out of the cs 8900a. maximum ether- net throughput can be ac hieved by using i/o or memory modes, and by dedicating the cpu to reading this counter, and using the count to read the frame out of the cs8900a at the same time it is being received by the cs8900a from the ethernet (par allel frame-reception and frame-read-out tasks). the byte count register resides at packetpage base + 50h. following an rxdest or rx128 interrupt the register contains the number of bytes which are available to be read by the cpu. when the end of frame is reached, the count contains the final count value for the frame, including the al- lowance for the buffer crc option. when this final count is read by the cpu the count regis- ter is set to zero. ther efore to read a complete frame using the byte c ount register, the regis- ter can be read and the data moved until a count of zero is detec ted. then the rxevent memory space word offset description of data stored in on- chip ram 0400h rxstatus register (the host may skip reading 0400h since rxevent was read from the isq.) table 24. example memory map 0402h rxlength register (in this example, the length is 40h bytes. the frame starts at 0404h, and runs through 0443h.) 0404h to 0409h 6-byte source address. 040ah to 040fh 6-byte destination address. 0410h to 0411h 2-byte length or type field. 0412h to 043fh 46 bytes of data. 0440h crc, bytes 1 and 2 0442h crc, bytes 3 and 4 memory space word offset description of data stored in on- chip ram table 24. example memory map
ds271f5 87 cs8900a crystal lan? ethernet controller cirrus logic product datasheet register can be read to determine the final frame status. the sequence is as follows: 1) at the start of a fr ame, the byte counter matches the incoming character counter. the byte counter will have an even value prior to the end of the frame. 2) at the end of the fram e, the final count, in- cluding the allowance for the crc (if the buffercrc option is e nabled), is held until the byte counter is read. 3) when a read of the by te counter returns a count of zero, the previous count was the fi- nal count. the count may now have an odd value. 4) rxevent should be re ad to obtain a final status of the frame, followed by a skip command to complete the operation. note that all rxevent's should be processed before using the byte c ounter. the byte coun- ter should be used following a bufevent when rxdest or rx128 in terrupts are enabled. 5.2.10 receive fram e address filtering the cs8900a is equipped with a destination address (da) filter used to determine which receive frames will be accepted. (a receive frame is said to be "accepted" by the cs8900a when the frame data ar e placed in either on- chip memory, or in host memory by dma). the da filter can be confi gured to accept the fol- lowing frame types: 5.2.10.1 indivi dual address frames for all individual address frames, the first bit of the da is a "0" (da[0] = 0), indicating that the address is a physical address. the address filter accepts individual address frames whose da matches the individu al address (ia) stored at packetpage base + 0158h, or whose hash- filtered da matches one of the bits pro- grammed into the logica l address filter (the hash filter is described later in this section). 5.2.10.2 multicast frames for multicast frames, the first bit of the da is a "1" (da[0] = 1), indicati ng that the frame is a logical address. the ad dress filter accepts multicast frames whose hash-filtered da matches one of the bits programmed into the logical address filter (the hash filter is de- scribed later is this sect ion). as shown in table 26, broadcast frames can be accepted as multicast frames under a very specific set of conditions. 5.2.10.3 broadcast frames frames with da equal to ffff ffff ffffh are broadcast frames . in addition, the cs8900a can be config ured for promiscuous mode, in which case it will accept all receive frames, irrespective of da. 5.2.11 configuring the destination address filter the da filter is configured by programming five da filter bits in the rxctl register (regis- ter 5): iahasha, promiscuousa, multicasta, individuala, and broadcasta. four of these bits are associated with f our status bits in the rxevent register (r egister 4): iahash, hashed, individualadr, and broadcast. the rxevent register reports the results of the da filter for a given receiv e frame. the bits asso- ciated with da filterin g are summarized below: bit # rxctl register 5 rxevent register 4 6 iahasha iahash (used only if iahasha = 1) 7 promiscuousa 9 multicasta hashed a individuala individualadr (used only if individuala = 1) b broadcasta broadcast (used only if broadcasta = 1)
88 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet the iahasha, multicasta, individuala, and broadcasta bits are used independently. as a result, many da filter combinations are possi- ble. for example, if mu lticasta and individuala are set, then all frames that are either multicast or individual address frames are accepted. the promiscuousa bit, wh en set, overrides the other four da bits, and allows all valid frames to be accepted. table 25 summarizes the con- figuration options avail able for da filtering. it may become necessary for the host to change the destination addr ess (da) filter cri- teria without resetting the cs8900a. this can be done as follows: 1) clear serrxon (regist er 13, linectl, bit 6) to prevent any add itional receive frames while the filter is being changed. 2) modify the da filter bi ts (b, a, 9, 7, and 6) in the rxctl register . modify the logical address filter at packetpage base + 0150h, if necessary. m odify the individual address at packet page base + 0158h, if necessary. 3) set serrxon to re -enable the receiver. because the receiver has been disabled, the cs8900a will ignore fram es while the host is changing the da filter. 5.2.12 hash filter the hash filter is used to help determine which multicast frames and which individual address frames should be acc epted by the cs8900a. 5.2.12.1 hash filter operation see figure 23. the da of the incoming frame is passed through the cr c logic, generating a 32-bit crc value. the si x most-significant bits of the crc are latched into the 6-bit hash reg- ister (hr). the contents of the hr are passed through a 6-to-64-bit decoder, asserting one of the decoder's outputs. the asserted output is compared with a corres ponding bit in the 64- bit logical address filt er, located at packet- page base + 0150h. if the decoder output and the logical addres s filter bit match, the frame passes the hash filter and the hashed bit (register 4, rxevent, bit 9) is set. if the two do not match, the frame fails the filter and the hashed bit is clear. whenever the hash filter is passed by a "good" frame, the rxok bit (r egister 4, rxevent, bit 8) is set and the bits in the hr are mapped to the hash table index bits (register 4, rx- event, bits a through f). iahasha promiscuousa multicasta individuala broadcasta frames accepted 0 0 0 1 0 individual a ddress frames with da matching the ia at packet- page base + 0158h 1 0 0 0 0 individual a ddress frames with da that pass the hash filter (da[0] must be ?0?) 0 0 1 0 0 multicast frames with da that pass the hash filter (da[0] must be ?1?) 0 0 0 0 1 broadcast frames x 1 x x x all frames table 25. da filtering options
ds271f5 89 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 5.2.13 broadcast frame hashing excep- tion table 26 describes in det ail the content of the rxevent register for each output of the hash and address filters, and describes an excep- tion to normal processing. that exception can occur when the hash-filt er broadcast address matches a bit in the lo gical address filter. to properly account for this exception, the soft- ware driver should use the following test to de- termine if the rxevent register contains a normal rxevent (meaning bits e-a are used for extra data, runt, crc error, broadcast and individualadr) or a hash-table rxevent (meaning bits f-a contain the hash table in- dex). if bit hashed =0, or bi t rxok=0, or (bits f-a = 02h and the destination ad dress is all ones) then rxevent contains a normal rxevent, else rxevent contained a hash rxevent. 64-bit logical address filter (laf) written into packetpage base + 150h 6-to-64 decoder 1 64 cs8900a crc logic destination address (da) from incoming frame 32-bit crc value (msb) (lsb) 6-bit hash register (hr) [hash table index] 64-input or gate to hashed bit figure 23. hash filter operation address type of received frame erred frame? passes hash filter? contents of rxevent bits f-a bit 9 hashed bit 8 rxok bit 6 iahash individual address no yes hash table index 1 1 1 no no extradata runt crc error broadcast individual adr 0 1 0 yes don?t care extradata runt crc error broadcast individual adr 0 0 0 multicast address no yes hash table index 1 1 0 no no extradata runt crc error broadcast individual adr 0 1 0 yes don?t care extradata runt crc error broadcast individual adr 0 0 0 notes: 6. broadcast frames are accepted as multicast frames if and only if all the fo llowing conditions are met simultaneously: a) the logical address filter is programmed as: (msb) 0000 8000 0000 0000h (lsb). note that this laf value corresponds to a multicast addresses of both all 1s and 03-00-00-00-00-01. b) the rx control register (register 5) is progra mmed to accept individual a, multicasta, rxok-only, and the following address filters were enabled: iahasha and broadcasta. 7. not (note 1). table 26. contents of rxevent upon various conditions
90 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 5.3 receive dma 5.3.1 overview the cs8900a supports a direct interface to the host dma controller allowing it to transfer receive frames to host memory via slave dma. the dma option applies only to receive frames, and not trans mit operation. the cs8900a offers three possible receive dma modes: 1) receive-dma-only mode: all receive frames are trans ferred via dma. 2) auto-switch dma: dma is used only when needed to help prevent missed frames. 3) streamtransfer: dma is used to minimize the number of inte rrupts to the host. this section provides a description of receive- dma-only mode. section 5.4 on page 94 de- scribes auto-switch dm a and section 5.5 on page 96 describes streamtransfer. 5.3.2 configuring the cs8900a for dma operation the cs8900a interfaces to the host dma con- troller through one pair of the dma request/ac- knowledge pins (see section 3.2 on page 18 for a description of the cs8900a's dma inter- face). four 16-bit registers are used for dma opera- tion. these are describ ed in table 27. receive-dma-only mode is enabled by setting the rxdmaonly bit (regis ter 3, rxcfg, bit 9). note: if the rxdmaonly bit and the autorxd- mae bit (register 3, rx cfg, bit a) are both set, then rxdmaonly takes precedence, and the cs8900a is in dma mode for all receive frames. broad- cast address no yes (note 6) extradata runt crc error broadcast individual adr 1 1 0 (actual value x00010) no yes (note 7) extradata runt crc error broadcast individual adr 0 1 0 no no extradata runt crc error broadcast individual adr 0 1 0 yes don?t care extradata runt crc error broadcast individual adr 0 0 0 address type of received frame erred frame? passes hash filter? contents of rxevent bits f-a bit 9 hashed bit 8 rxok bit 6 iahash notes: 6. broadcast frames are accepted as multicast frames if and only if all the fo llowing conditions are met simultaneously: a) the logical address filter is programmed as: (msb) 0000 8000 0000 0000h (lsb). note that this laf value corresponds to a multicast addresses of both all 1s and 03-00-00-00-00-01. b) the rx control register (register 5) is progra mmed to accept individual a, multicasta, rxok-only, and the following address filters were enabled: iahasha and broadcasta. 7. not (note 1). table 26. contents of rxevent upon various conditions packetpage address register description 0024h dma channel number: dma chan- nel number (0, 1, or 2) that defines the dmarq/dmack pin pair used. 0026h dma start of frame: 16-bit value that defines the offset from the dma base address to the start of the most recently transferred received frame. table 27. receive dma registers
ds271f5 91 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 5.3.3 dma receive buffer size in receive dma mode, the cs8900a stores re- ceived frames (along with their status and length) in a circular buffer located in host mem- ory space. the size of the circular buffer is de- termined by the rxdmas ize bit (register 17, busctl, bit d). when rx dmasize is clear, the buffer size is 16 kbytes. when rxdmasize is set, the buffer is 64 kbyt es. it is the host's task to locate and keep track of the dma receive buffer's base address. the dma start-of- frame register is the only circuit affected by this bit. application note: as a result of the pc architecture, dma cannot occur across a 128k boundary in memory. thus, the dma buffer re- served for the cs8900a must not cross a 128k boundary in host me mory if dma opera- tion is desired. requesting a 64k, rather than a 16k buffer, increa ses the probability of crossing a 128k boundary. after the driver re- quests a dma buffer, the driver must check for a boundary crossing. if the boundary is crossed, then the driv er must disable dma functionality. 5.3.4 receive-dma-only operation if space is available, an incoming frame is tem- porarily stored in on-ch ip ram. when the en- tire frame has been rece ived, pre-processed, and accepted, the cs 8900a signals the dma controller that a frame is to be transferred to host memory by driving the selected dma re- quest pin high. the dma controller acknowl- edges the request by driving the dma acknowledge pin low. the cs8900a then transfers the contents of the rxstatus register (packetpage base + 0400h) and the rxlength register (packetpage base + 0402h) to host memory, followed by th e frame data. if the dmaburst bit (register 17, busctl, bit b) is clear, the dma request pin remains high until the entire frame is transf erred. if the dmaburst bit is set, the dma request pin (dmarq) re- mains high for approximately 28 s then goes low for approximately 1.3 s to give the cpu and other peripherals access to the bus. when the transfer is co mplete, the cs8900a does the following: ? updates the dma start-of-frame register (packetpage base + 0026h); ? updates the dma frame count register (packetpage base + 0028h); ? updates dma byte count register (packet- page base + 002ah); ? sets the rxdmaframe bit (register c, bufevent, bit 7); and, ? deallocates the buffer space used by the transferred frame. in addition, if the rxdmaie bit (register b, bufcfg, bit 7) is set, a corresponding inter- rupt occurs. when the host processes dmaed frames, it must read the dma fr ame count register. whenever a receive frame is missed (lost) due to insufficient receive buffer space, the rx- miss counter (register 10) is incremented. a missed receive frame causes the counter to in- crement in either dm a or non-dma modes. 0028h dma frame count: the lower 12 bits define the number of valid frames transferred via dma since the last read-out of this register. the upper 4 bits are reserved and not applicable. 002ah dma byte count: defines the num- ber of bytes that have been transferred via dma since the last read-out of this register. packetpage address register description table 27. receive dma registers
92 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet note that when in dma mode, reading the con- tents of the rxevent r egister will return 0000h. status information sh ould be obtained from the dma buffer. 5.3.5 committing bu ffer space to a dmaed frame although a receive frame may occupy space in the host memory's circular dma buffer, the cs8900a's memory manager does not com- mit the buffer s pace to the rece ive frame until the entire frame has b een transferred and the host learns of the fram e's existence by reading the frame count register (packetpage base + 0028h). when the cs8900a commits dma buffer space to a particular dmaed receive frame (termed a committed re ceived frame), no data from subsequent frames can be written to that buffer space until the committed received frame is freed from co mmitment. (the commit- ted received frame may or may not have been received error free.) a committed dmaed receive frame is freed from commitment by an y one of the following conditions: 1) the host rereads the dma frame count register (packetpage base + 0028h). 2) new frames have been transferred via dma, and the host reads the bufevent reg- ister (either directly or from the isq) and sees that the rxdmaframe bit is set (this condition is termed an "implied skip"). 3) the host issues a reset-dma command by setting the resetrxdma bit (register 17, busctl, bit 6). 5.3.6 dma buffer organization when dma is used to tr ansfer receive frames, the dma start-of-frame register (packetpage base + 0026h) defines t he offset from the dma base to the start of the most recently transferred received frame. frames stored in the dma buffer are transferred as words and maintain double-word (32-bit) alignment. un- filled memory space between successive frames stored in the dma buffer may result from double-word ali gnment. these "holes" may be 1, 2, or 3 bytes, depending on the length of the fram e preceding the hole. 5.3.7 rxdmaframe bit the rxdmaframe bit (r egister c, bufevent, bit 7) is controlled by the cs8900a and is set whenever the value in the dma frame count register is non-zero. t he host cannot clear rx- dmaframe by reading t he bufevent register (register c). table 28 su mmarizes the criteria used to set and clear rxdmaframe. 5.3.8 receive dma example without wrap-around figure 24 shows three frames stored in host memory by dma without wr ap-around. 5.3.9 receive dma op eration for rxdma- only mode in an rxdmaonly m ode, a system dma moves all the received frames from the on- chip memory to an external 16- or 64-kbyte buffer memory. the rece ived frame must have passed the destination add ress filter, and must non-stream transfer mode stream transfer mode (see section 5.5) to s e t r x d - maframe the rxdmaframe bit is set whenever the dma frame count register (packetpage base + 0028h) transitions to non-zero. the rxdmaframe bit is set at the end of a stream transfer cycle. to clear rxdma- frame the dma frame count is zero. the dma frame count is zero. table 28. rxdmaframe bit
ds271f5 93 cs8900a crystal lan? ethernet controller cirrus logic product datasheet be completely received. usually, the dma re- ceive frame interrupt (r xdmaie, bit 7, regis- ter b, bufcfg) is se t so that the cs8900a generates an interrupt when a frame is trans- ferred by dma. figure 25 shows how a dma receive frame interrupt is processed. in the interrupt servic e routine, the bufevent register (register c), bit rxdma frame (bit 7) indicates that one or more receive frames were transferred usi ng dma. the software driver should maintain a pointer (e.g. pdma_start) that will point to the beginning of a new frame. after the cs8900a is initial- ized and before any fram e is received, pointer pdma_start points to the beginning of the dma buffer memory area. the first read of the dma frame count, cdma , commits the mem- ory covered by the cdm a count, and the dma cannot overwrite this committed space until the space is freed. the driver then processes the frames described by the cdma count and makes a second read of the dma frame count. this second read frees the buffer memory space described by th e cdma counter. during the frame proc essing, the software should advance the pdma_start pointer. at the end of processing a frame, pointer pdma_start should be made to align with a double-word boundary. the software remains in the loop until the dma frame count read is zero. rxstatus - frame 1 rxlength - frame 1 rxstatus - frame 2 rxlength - frame 2 frame 2 rxstatus - frame 3 rxlength - frame 3 frame 3 dma buffer base address frame 1 dma byte count (packetpage base + 012ah) dma start of frame register (packetpage base + 0126h) points here. "holes" due to double-word alignment figure 24. example of frames stored in dma
94 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 5.4 auto-switch dma 5.4.1 overview the cs8900a supports a unique feature, auto-switch dma, that allows it to switch be- tween memory or i/o mode and receive dma automatically. auto-swi tch dma allows the cs8900a to realize the performance advan- tages of memory or i/o mode while minimizing the number of missed fr ames that could result due to slow processing by the host. 5.4.2 configuring the cs8900a for auto- switch dma auto-switch dma mode requires the same configuration as receive-dma-only mode, with one exception: the autorxdmae bit (register 3, rxcfg, bi t a) must be set, and the rxdmaonly bit (regist er 3, rxcfg, bit 9) must be clear (see se ction 5.3 on page 90, configuring the cs8900a for dma operation). in auto-switch dma mode, the cs8900a op- erates in non-dma mo de if possible, only switching to slave dma if necessary. note that if the autorxdmae bit and the rxd- maonly bit (register 3, rxcfg, bit 9) are both set, the cs8900a uses dma for all receive frames. 5.4.3 auto-switch dma operation whenever a frame begins to be received in auto-switch dma mode, the cs8900a checks to see if there is enough on-chip buffer space to store a maximum lengt h frame. if there is, the incoming frame is pre-processed and buff- process the c dma frames read the dma frame count (c dma ) (packetpage base + 0028h) no c dma = 0 ? host enters interrupt routine process other events that caused interrupt yes no rxdma frame bit set? process other events that caused interrupt yes figure 25. rxdma only operation
ds271f5 95 cs8900a crystal lan? ethernet controller cirrus logic product datasheet ered as normal. if t here isn't, the cs8900a's mac engine compares the frame's destina- tion address (da) to th e criteria programmed into the da filter. if the incoming da fails the da filter, the frame is discarded. if the da passes the da filter , the cs8900a automati- cally switches to dma mode and starts trans- ferring the frame(s) cu rrently being held in the on-chip buffer into host memory. this frees up buffer space for the incoming frame. figure 26 shows the steps the cs8900a goes through in determining when to automatically switch to dma. whenever the cs8900a automatically enters dma, at least one comp lete frame is already stored in the on-chip buffer. because frames are transferred to the hos t in the same order as received (first in, first out), the beginning of the received frame that tr iggered the switch to dma is not the first fram e to be transferred. in- stead, the oldest noncom mitted frame in the on-chip buffer is the fi rst frame to use dma. when dma begins, any pending rxevent re- ports in the interrupt status queue are dis- carded because the host cannot process those events until t he corresponding frames have been completely dmaed. auto-switch dma works only on entire re- ceived frames. the cs8900a does not use auto-switch dma to transfer partial frames. also, when a frame ha s been committed (see section 5.2.5 on page 85) , the cs8900a will not switch to dma mode until the committed frame has been transferred completely or skipped. after a complete frame has been moved to host memory, the cs8900a updates the dma start-of-frame register (packetpage base + 0126h), the dma frame co unt register (pack- etpage base + 0128h), and the dma byte count register, then sets the rxdmaframe bit (register c, bufevent , bit 7). if rxdmaie (register b, bufcfg, bit 7) is set, a corre- sponding interrupt occurs. 5.4.4 dma channel speed vs. missed frames when the cs8900a starts dma, the entire old- est, noncommitted fram e must be placed in host memory before on-chip buffer space will be freed for the next incomi ng frame. if the old- est frame is relatively large, and the next in- all frames use dma yes yes no no yes no no yes frame discarded frame buffered in on-chip ram auto-switch dma disabled packet received auto-switch to dma frame passed the da filter? rxdma only bit=1 more buffer space available? autorxdma bit=1? figure 26. conditions for switching to dma
96 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet coming frame also large, the incoming frame may be missed, depending on the speed of the dma channel. if this happens, the cs8900a will increment the rxmiss counter (register 10) and clear any event reports (rxevent and bufevent) associated with the missed frame. 5.4.5 exit from dma when the cs8900a has activated receive dma, it remains in dma mode until all of the following are true: ? the host processes all rxevent and bufe- vent reports pending in the isq. ? the host reads a zero value from the dma frame count register (packetpage base + 0028h). ? the cs8900a is not in the process of transferring a frame via dma. 5.4.6 auto-switch dma example figure 27 shows how the cs8900a enters and exits auto-switch dm a mode. 5.5 streamtransfer 5.5.1 overview the cs8900a supports an optional feature, streamtransfer, that can reduce the amount of cpu overhead associated with frame re- ception. streamtransf er works during periods of high receive activity by grouping multiple re- ceive events into a single interrupt, thereby re- ducing the number of re ceive interrupts to the host processor. during periods of peak load- ing, streamtransfer will eliminate 7 out of ev- ery 8 interrupts, cutting interrupt overhead by up to 87%. 5.5.2 configuring th e cs8900a for stream- transfer streamtransfer is enabled by setting the streame bit along with either the autorxd- mae bit or the rxdmaonl y bit in register re- ceiver configurat ion (register 3). (streamtransfer must not be selected unless either one of autorx dmae or rxdma-only is selected.)streamtransfer only applies to "good" frames (frames of legal length with val- id crc). therefore, the rxoka bit and the rxokie bit must both be set. finally, stream- transfer works on whole packets and is not compatible with early interrupts. this requires that the rxdestie bit and the rx128ie bit both be clear. table 29 summarizes how to configure the cs8900a for stre amtransfer. 5.5.3 streamtransfer operation when streamtransfer is enabled, the cs8900a will initiate a streamtransfer cycle whenever two or more fr ames with the follow- ing characteristics are received: 1) pass the destination address filter; 2) are of legal length with valid crc; and, 3) are spaced "back-to-back" (between 9.6 and 52 s apart). during a streamtransf er cycle the cs8900a does the following: ? delays the normal rxok interrupt associat- ed with the first receive frame; ? switches to receive dma mode; ? transfers up to eight receive frames into host memory via dma; register name bit bit name value register 3, rxcfg 7 streame 1 8rxokie 1 9 or a rxdmaonly or autorxdma 1 or 1 register 5, rxctl 8 rxoka 1 register b, bufcfg 7 rxdmaie 1 frxdestie 0 b rx128ie 0 table 29. stream transfer configuration
ds271f5 97 cs8900a crystal lan? ethernet controller cirrus logic product datasheet f r a m e 1 f r a m e 2 frame 3 starts to be received and passes the da filter. this activates auto-switch dma. f r a m e 3 frame 1 is placed in host memory via dma freeing space for the incoming frame 3. the cs8900a updates the dma frame count, dma start of frame and dma byte count registers. it then sets the rxdma dmaframe bit and generates an interrupt. frame 2 is placed in host memory via dma and the cs8900a updates the dma registers. the host responds to the rxdmaframe interrupt, and reads the frame count register, which is cleared when read. since there are no receive interrupts pending, the cs8900a exits dma (assumes frame 3 is still coming in). receive dma used during this time. at this point, the cs8900a does not have sufficient buffer space for another complete large frame (1518 bytes). frame 1 received and completely stored in on-chip ram. frame 2 received and completely stored in on-chip ram. enter example here exit example time frame 3 is completely buffered in on-chip ram, and awaits processing by the host. entering this example, the receive buffer is empty and the dma frame count (packetpage base + 0028h) is zero. figure 27. example of auto-switch dma
98 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet ? updates the dma star t-of-frame register (packetpage base + 0026h); ? updates the dma frame count register (packetpage base + 0028h); ? updates dma byte count register (packet- page base + 002ah); ? sets the rxdmaframe bit (register c, bufevent, bit 7); and, ? generates an rxdmaframe interrupt. 5.5.4 keeping streamtransfer mode active when the cs8900a initia tes a streamtransfer cycle, it will continue to execute cycles as long as the following c onditions hold true: ? all packets received ar e of legal length with valid crc; ? each packet follows its predecessor by less than 52 ms; and, ? the da of each packet passes the da filter. if any of these conditi ons are not met, the cs8900a exits streamtr ansfer by generating rxok and rxdma interrupts. the cs8900a then returns to either memory, i/o, or dma mode, depending on configuration. 5.5.5 example of streamtransfer figure 28 shows how four back-to-back frames, followed by five back-to-back frames, would be received with out streamtransfer. figure 29 shows how the same sequence of frames would be received with streamtrans- fer. 4 back-to-back frames 5 back-to-back frames interrupt request 9 interrupts for 9 "good" packets time t > 52 us figure 28. receive example without stream transfer 4 back-to-back frames 5 back-to-back frames interrupt request 2 interrupts for 9 "good" packets time t > 52 us figure 29. receive dma configuration options
ds271f5 99 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 5.5.6 receive dma summary table 30 summarize the receive dma config- uration options suppor ted by the cs8900a. 5.6 transmit operation 5.6.1 overview packet transmission occu rs in two phases. in the first phase, the hos t moves the ethernet frame into the cs8900a's buffer memory. the first phase begins with the host issuing a transmit command. this informs the cs8900a that a frame is to be transmitted and tells the ch ip when (i.e. after 5, 381, or 1021 bytes ha ve been transferred or after the full frame has been transferred to the cs8900a) and how the frame should be sent (i.e. with or without crc, with or without pad bits, etc.). the host fo llows the transmit com- mand with the transmit length, indicating how much buffer space is required. when buffer space is available, the host writes the ethernet frame into the cs8900a's internal memory, using either memo ry or i/o space. in the second phase of transmission, the cs8900a converts the frame into an ethernet packet then transmits it onto the network. the second phase begins with the cs8900a trans- mitting the preamble an d start-of-frame de- limiter as soon as the proper number of bytes has been transferred into its transmit buffer (5, 381, 1021 bytes or full frame, depending on configuration). the pr eamble and start-of- frame delimiter are follow ed by the data trans- ferred into the on-chip bu ffer by the host (des- tination address, source address, length field and llc data). if the frame is less than 64 bytes, including crc, the cs8900a adds pad bits if configured to do so. finally, the cs8900a appends the prope r 32-bit crc val- ue. 5.6.2 transmit configuration after each reset, the cs890 0a must be config- ured for transmit operation. this can be done automatically using an attached eeprom, or by writing configuration commands to the cs8900a's internal regi sters (see section 3.4 on page 21). the items that must be config- ured include which physical interface to use and which transmit event s cause interrupts. 5.6.2.1 configuring the physical interface configuring the physical interface consists of determining which ether net interface should be active (10base-t or aui), and enabling the transmit logic for serial transmission. configur- ing the physical interf ace is accomplished via rxdmaonly (register 3, rxcfg,bit 9) autorxdmaie (register 3, rxcfg, bit a) rxdmaie (register b, bufcfg, bit 7) rxokie (register 3, rxcfg, bit 8) cs8900a configuration 1 na 0 na receive dma used for a ll receive fram es, without interrupts. 1 na 1 na receive dma used for all receive frames, with bufevent interrupts. 0 1 0 0 auto-switch dma used if necessary, without inter- rupts. 0 1 1 1 auto-switch dma used if necessary, with rxevent and bufevent interrupts possible. 0 0 na na memory or i/o mode only. table 30. receive dma configuration options
100 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet the linectl register (register 13) and is de- scribed in table 31. note that the cs8900a transmits in 10base- t mode when no link pu lses are being re- ceived only if bit disabl elt is set in register test control (register 19). 5.6.2.2 selecting which events cause inter- rupts the txcfg register (register 7) and the buf- cfg register (register b) are used to deter- mine which transmit events will cause interrupts to the host pr ocessor. tables 32 and 33 describe the interrup t enable (ie) bits in these registers. 5.6.3 changing the configuration when the host configur es these registers it does not need to change them for subsequent packet transmissions. if the host does choose to change the txcfg or bufcfg registers, it may do so at any time. the effects of the change are noticed immedi ately. that is, any changes in the interrupt enable (ie) bits may affect the packet current ly being transmitted. if the host chooses to change bits in the linectl register after initialization, the mod- backoffe bit and any rece ive related bit (lorx- squelch, serrxon) may be changed at any time. however, the auto aui/10bt and auion- ly bits should not be changed while the sertx- on bit is set. if any of these three bits are to be changed, the host should first clear the sertx- on bit (register 13, li nectl, bit 7), and then set it when the ch anges are complete. register 13, linectl bit bit name operation 7 sertxon when set, transmission enabled. 8 auionly when set, aui selected (takes precedence over autoaui/10bt). when clear, 10base-t selected. 9 autoaui/10bt when set, automatic interface selection enabled. bmod backoffe when set, the modified backoff algorithm is used. when clear, the standard backoff algorithm is used. d2-part defdis when set, two-part deferral is disabled. table 31. physical interface configuration register b, bufcfg bit bit name operation 8 rdy4txie when set, there is an interrupt whenever buffer space becomes available for a transmit frame (used with a transmit request). 9 txunder runie when set, there is an interrupt whenever the cs8900a runs out of data after transmit has started. ctxcol ovfloie when set, there is an interrupt whenever the txcol counter overflows. table 33. transmit interrupt configuration register 7, txcfg bit bit name operation 6 loss-of- crsie when set, there is an interrupt whenever the cs8900a fails to detect carrier sense after trans- mitting the preamble (applies to the aui only). 7 sqerrorie when set, there is an interrupt whenever there is an sqe error. 8 txokie when set, there is an interrupt whenever a frame is transmitted successfully.. 9out-of- windowie when set, there is an interrupt whenever a late collision is detected. a jabberie when set, there is an interrupt whenever there is a jabber condi- tion. b anycollie when set, ther e is an interrupt whenever there is a collision. f 16collie when set, there is an interrupt whenever the cs8900a attempts to transmit a single frame 16 times. table 32. transmitting interrupt configuration
ds271f5 101 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 5.6.4 enabling crc generation and pad- ding whenever the host iss ues a transmit request command, it must indica te whether or not the cyclic redundancy check (crc) value should be appended to the transmit frame, and whether or not pad bits should be added (if needed). table 34 describes how to configure the cs8900a for crc generating and pad- ding. 5.6.5 individual packet transmission whenever the host has a packet to transmit, it must issue a transmit request to the cs8900a consisting of the following three op- erations in the exact order shown: 1) the host must write a transmit command to the txcmd register (packetpage base + 0144h). the contents of the txcmd regis- ter may be read back from the txcmd reg- ister (register 9). 2) the host must write the frame's length to the txlength register (packetpage base + 0146h). 3) the host must read the busst register (register 18) the information written to the txcmd register tells the cs8900a how to transmit the next frame. the bits that must be programmed in the txcmd register are described in table 35. for each individual packet transmission, the host must issue a complete transmit request. furthermore, the host must write to the txc- md register before ea ch packet transmission, even if the contents of the txcmd register does not change. the transmit request de- scribed above may be in either memory space or i/o space. 5.6.6 transmit in poll mode in poll mode, rdy4txie bit (register b, buf- cfg, bit 8) must be clea r (interrupt disabled). the transmit operation occurs in the following order and is shown in figure 30. register 9, txcmd inhibit crc (bit c) txpad dis (bit d) operation 0 0 pad to 64 bytes if necessary (including crc). 1 0 send a runt frame if specified length less th an 60 bytes. 0 1 pad to 60 bytes if necessary (with- out crc). 1 1 send runt if specified length less than 64. the cs8900a will not transmit a frame that is less than 3 bytes. table 34. crc and padd ling configuration register 9, txcmd bit bit name operation 67 tx start clear clear start preamble after 5 bytes have been transferred to the cs8900a. clear set start preamble after 381 bytes have been trans- ferred to the cs8900a. set clear start preamble after 1021 bytes have been trans- ferred to the cs8900a. set set start preamble after entire frame has been transferred to the cs8900a. 8 force when set, the cs8900a dis- cards any frame data cur- rently in the transmit buffer. 9 onecoll when set, the cs8900a will not attempt to retransmit any packet after a collision. c inhibitcrc when set, the cs8900a does not append the 32-bit crc value to the end of any transmit packet. d txpaddis when set, the cs8900a will not add pad bits to short frames. table 35. tx command configuration
102 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 1) the host bids for fram e storage by writing the transmit command to the txcmd reg- ister (memory base+ 0144h in memory mode and i/o base + 0004h in i/o mode). 2) the host writes the transmit frame length to the txlength register (memory base + 0146h in memory mode and i/o base + 0006h in i/o mode). if the transmit length is erroneous, the comm and is discarded and the txbiderr bit (regis ter 18, busst, bit 7) is set. 3) the host reads the busst register. this read is performed in memory mode by reading register 18, at memory base + 0138h. in i/o mode, the host must first set the packetpage pointer at the correct loca- tion by writin g 0138h to the packetpage pointer port (i/o base + 000ah). the host can then read the busst register from the packetpage data port (i/o base + 000ch). 4) after reading the regi ster, the rdy4txnow bit (bit 8) is checked. if the bit is set, the frame can be written. if the bit is clear, the host must continue r eading the busst reg- ister (register 18) and checking the rdy4txnow bit (bit 8) until the b i t i s s e t . when the cs8900a is re ady to accept the frame, the host transfers the entire frame from host memory to cs8900a memory using ?rep? instruction (r ep movs starting at memory base + 0a00h in memory mode, and rep out to receive/transmit data port (i/o base + 0000h) in i/o mode). 5.6.7 transmit in interrupt mode in interrupt mode, rdy4 txie bit (register b, bufcfg, bit 8) must be set for transmit opera- tion. transmit operation o ccurs in the following order and is show n in figure 31. 1) the host bids for fr ame storage by writing the transmit command to the txcmd reg- ister (memory base + 0144h in memory mode and i/o base + 0004h in i/o mode). 2) the host writes the transmit frame length to the txlength register (memory base + 0146h in memory mode and i/o base + 0006h in i/o mode). if the transmit length is erroneous, the comm and is discarded and the txbiderr, bit 7, in busst register is set. 3) the host reads the busst register. this read is performed in memory mode by reading register 18 , at memory base + 0138h. in i/o mode, t he host must first set the packetpage pointer at the correct loca- tion by writing 0 138h to the packetpage pointer port (i/o base + 000ah), it than can read the busst regist er from the packet- page data port (i/o base + 000ch).after reading the register, the rdy4txnow bit is checked. if the bit is set, the frame can be written to cs8900a memory. if rdy4txnow is clear, the host will have to wait for the cs8900a buffer memory to be- come available at which time the host will be interrupted. on interrupt, the host enters the interrupt service routine and reads isq register (memory base + 0120h in memory mode and i/o base + 0008h in i/o) and checks the rdy4tx bit (b it 8). if rdy4tx is clear then the cs8900a waits for the next interrupt. if rdy4tx is set, then the cs8900a is ready to accept the frame. 4) when the cs8900a is ready to accept the frame, the host transfe rs the entire frame from host memory to cs8900a memory using rep instruct ion (rep movs to memory base + 0a00h in memory mode, and rep out to receive/transmit data port (i/o base + 0000h) in i/o mode).
ds271f5 103 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 5.6.8 completing transmission when the cs8900a succe ssfully completes transmitting a frame, it sets the txok bit (reg- ister 8, txevent, bit 8). if the txokie bit (reg- ister 7, txcfg, bit 8) is set, the cs8900a generates a corresponding interrupt. cs8900a commits buffer space to transmit frame host reads the busst register (register 18) transmit request host writes transmit frame to cs8900a host writes transmit command to the txcmd register host writes transmit frame length to the txlength register exit transmit process yes no enter packet transmit process rdy4 txnow bit = 1? polling loop no yes is txcmd pending? exit: can't issue command note: issuing a command at this point will cause previous transmit frame to be lost. cs8900a transmits frame figure 30. transmit operation in polling mode
104 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 5.6.9 rdy4txnow vs. rdy4tx the rdy4txnow bit (regi ster 18, busst, bit 8) is used to tell t he host that the cs8900a is ready to accept a fram e for transmission. this bit is used during t he transmit request pro- cess or after the transm it request process to signal the host that space has become avail- able when interrupts are not being used (i.e. the rdy4txie bit (registe r b, bufcfg, bit 8) is cs8900a commits buffer space to transmit frame host reads isq host reads the busst register (register 18) transmit request host writes transmit frame to cs8900a host writes transmit command to the txcmd register host writes transmit frame length to the txlength register rdy4tx bit = 1? exit transmit process no yes no yes rdy4 txnow bit = 1? host enters interrupt routine exit wait-for-interrupt process other events that caused interrupt no yes is txcmd pending? exit: can't issue command note: issuing a command at this point will cause previous transmit frame to be lost. enter packet transmit process cs8900a transmits frame figure 31. transmit op eration in interrupt mode
ds271f5 105 cs8900a crystal lan? ethernet controller cirrus logic product datasheet not set). also, the rdy4tx bit is used with in- terrupts and requires the rdy4txie bit be set. figure 30 provides a diagram of error free transmission without collision. 5.6.10 committing buffer space to a transmit frame when the host issues a transmit request, the cs8900a checks the l ength of the transmit frame to see if there is sufficient on-chip buffer space. if there is, the cs8900a sets the rdy4txnow bit. if no t, and the rdy4txie bit is set, the cs8900a wa its for buffer space to free up and then sets the rdy4tx bit. if rdy4txie is not set, the cs8900a sets the rdy4txnow bit when space becomes avail- able. even though transmit buffer space may be available, the cs8900a does not commit buf- fer space to a transmit frame until all of the fol- lowing are true: 1) the host must issues a transmit request; 2) the transmit request must be successful; and, 3) either the host read s that the rdy4txnow bit (register 18, busst, bit 8) is set, or the host reads that the rd y4tx bit (register c, bufevent, bit 8) is set. if the cs8900a commits bu ffer space to a par- ticular transmit frame, it will not allow subse- quent frames to be writt en to that buffer space as long as the transmi t frame is committed. after buffer space is committed, the frame is subsequently transmitted unless any of the fol- lowing occur: 1) the host completely writes the frame data, but transmission failed on the ethernet line. there are three such failures, and these are indicated by three transmit error bits in the txevent register (register 8): 16coll, jabber, or out-of-window. or: 2) the host aborts the transmission by setting the force (register 9, txcmd, bit 8) bit. in this case, the commit ted transmit frame, as well as any yet-to-be-transmitted frames queued in the on-chip memory, are cleared and not transmitted. the host should make txlength = 0 when using the force bit. or: 3) there is a transmit under-run, and the tx- underrun bit (register c, bufevent, bit 9) is set. successful transmission is indicated when the txok bit (register 8, txevent, bit 8) is set. 5.6.11 transmit frame length the length of the fram e transmitted is deter- mined by the value writ ten into the txlength register (packetpage base + 0146h) during the transmit request. the length of the trans- mit frame may be modified by the configura- tion of the txpaddis bi t (register 9, txcmd, bit d) and the in hibitcrc bit (register 9, txc- md, bit c). table 36 defi nes how these bits af- fect the length of the transmit frame. in addition, it shows whic h frames the cs8900a will send. 5.7 full duplex considerations the driver should not bid to transmit a long frame (i.e., a frame great er than 118 bytes) if the prior transmit frame is still being transmit- ted. the end of the trans mission of this prior frame is indicated by a txok bit being set in the txevent register (register 8). 5.8 auto-negotiation considerations when the cs8900a is connected to an auto negotiation hub, and if au to-media detection is selected (bits 8 and 9 of register 13), then the
106 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet cs8900a may not auto- select the 10base-t media. the cause of this situation is described in the following paragraphs. the original ieee 802.3 specification requires the mac to wait until 4 valid link-pulses are re- ceived before asserting link-ok. any time an invalid link-pulse is rece ived, the count is re- started. when auto-negotiation occurs, a transmitter sends flps (auto-negotiation fast link pulses) bursts instead of the original ieee 802.3 nlp (norma l link pulses). if the hub is attempting to auto-negotiate with the cs8900a, the cs8900a will never get more than 1 "valid" link pulse (valid nlp). this is not a problem if the cs8900a is already sending link-pulses, becaus e when the hub re- ceives nlps from the cs8900a, the hub is re- quired to stop sending flps and start sending nlps. the nlp transmitte d by the hu b will put the cs8900a into link-ok. however, if the cs8900a is in auto-switch mode, the cs8900a will never send any link- pulses, and the hub will never change from sending flps to sending nlps. register 9, txcmd host specified transmit length at 0146h (in bytes) txpad- dis (bit d) inhibitcrc (bit c) 3 < txlength < 60 60 < txlength < 1514 1514 < txlength < 1518 txlength > 1518 0 0 pad to 60 and add crc send frame and add crc [normal mode] will not send will not send 0 1 pad to 60 and send without crc send frame without crc send frame without crc will not send 1 0 send without pads, and add crc send frame and add crc will not send will not send 1 1 send without pads and without crc send frame without crc send frame without crc will not send notes: 8. if the txpaddis bit is clear and inhibitcrc is set and the cs8900a is comm anded to send a frame of length less than 60 bytes, the cs8900a pads. 9. the cs8900a will not send a frame with txlength le ss than 3 bytes. table 36. transmit frame length
ds271f5 107 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 6.0 test 6.1 test modes 6.1.1 loopback & co llision diagnostic tests internal and external loopback and collision tests can be used to verify the cs8900a's functionality when conf igured for either 10base-t or aui operation. 6.1.2 internal tests internal tests allow t he major digital functions to be tested, independent of the analog func- tions. during these tests, the manchester en- coder is connected to the decoder. all digital circuits are operational, and the transmitter and receiver are disabled. 6.1.3 external tests external test modes allo w the complete chip to be tested without connectin g it directly to an ethernet network. 6.1.4 loopback tests during loopback tests, the internal carrier sense (crs) signal, used to detect collisions, is ignored, allowing pa cket reception during packet transmission. 6.1.5 10base-t loopba ck and collision tests 10base-t loopback and co llision tests are controlled by two bits in the test control regis- ter: fdx (register 19, te stctl, bit e) and en- decloop (register 19, testctl, bit 9). table 37 describes these tests. 6.1.6 aui loopback and collision tests aui loopback and collisi on tests are con- trolled by two bits in t he test control register: auiloop (register 19, test ctl, bit a) and en- decloop (register 19, testctl, bit 9). table 38 describes these tests. test mode fdx endecloop description of test 10base-t inter- nal loopback 1 1 transmit a frame and verify that the frame is received without error. 10base-t inter- nal collision 0 1 transmit frames and verify th at collisions ar e detected and that the internal counters functi on properly. after 16 collisions, verify that 16coll (register 8, txevent, bit f) is set. 10base-t external loop- back 1 0 connect txd+ to rxd+ and txd- to rxd-. transmit a frame and verify that the frame is received without error. 10base-t external collision 0 0 connect txd+ to rxd+ and tx d- to rxd-. transmit frames and verify that collis ions are detected and that internal coun- ters function proper ly. after 16 collisions, verify that 16coll (register 8, txevent, bit f) is set. table 37. 10base-t loopback and collision tests test mode auiloop endecloop description of test aui internal loopback 1 1 transmit a frame and verify that the frame is received without error. aui external loopback 1 0 connect do+ to di+ and do- to di-. transmit a frame and verify that the frame is received without error (since there is no collision signal, an sqe error will occur). aui collision 0 0 start transmission and obs erve do+/do- activi ty. input a 10 mhz sine wave to cl+/cl- pins and observe collisions. table 38. aui loopback and collision tests
108 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 6.2 boundary scan boundary scan test mode provides an easy and efficient boar d-level test for verifying that the cs8900a has been installed properly. boundary scan will check to see if the orienta- tion of the chip is corr ect, and if there are any open or short circuits. boundary scan is controlled by the test pin. when test is high, the cs8900a is config- ured for normal operation. when test is low, the following occurs: ? the cs8900a enter s boundary scan test mode and stays in this mode as long as test is low; ? the cs8900a goes through an internal re- set and remains in inte rnal reset as long as test is low; ? the aen pin, normally the isa bus address enable, is redefined to become the bound- ary scan shift clock input; and ? all digital outputs and bi-directional pins are placed in a high-impedance state (this electrically isolates the cs8900a digital outputs from the rest of the circuit board). for boundary scan to be enabled, aen must be low before test is driven low. a complete boundary scan test is m ade up of two separate cycles. the first cycle, known as the output cycle, test s all digital output pins and all bi-directional pins. the second cycle, known as the input cycle, tests all digital input pins and all bi-directional pins. 6.2.1 output cycle during the output cycle, the falling edge of aen causes each of th e 17 digital output pins and each of the 17 bi-directional pins to be driven low, one at a time. the cycle begins with linkled and advances in order counter- clockwise around the chip through all 34 pins. this test is referred to as a "walking 0" test. the following is a list of output pins and bi-di- rectional pins that are tested during the output cycle: the output pins not included in this test are: 6.2.2 input cycle during the input cycle, the falling edge of aen causes the state of each selected pin to be transferred to eedataout (that is, eedataout will be high or low depe nding on the input level of the selected pin). this cycle begins with sleep and advances clockwise through each of 33 input pins (all digi tal input pins except for aen) and each of the 17 bi-directional pins, one pin at a time. the following is a list of input pins and bi-direc- tional pins that are test ed during the input cy- cle: pin name pin # pin name pin # elcs 2 intrq1 31 eecs 3 intrq0 32 eesk 4 iocs16 33 eedataout 5 memcs16 34 dmarq2 11 intrq3 35 dmarq1 13 iochrdy 64 dmarq0 15 sd0 - sd7 65-68, 71-74 csout 17 bstatus 78 sd08-sd15 27-24, 21-18 linkled 99 intrq2 30 lanled 100 table 39. pin name pin # pin name pin # do+ 83 txd- 88 do- 84 res 93 txd+ 87 xtal2 98 table 40. pin name pin # pin name pin # elcs 2 sbhe 36 eedatain 6 sa0 - sa11 37-48 chipsel 7 refresh 49 dmack2 12 sa12 - sa19 50-54, 58-60 table 41.
ds271f5 109 cs8900a crystal lan? ethernet controller cirrus logic product datasheet the input pins not incl uded in this test are: after the input cycle is complete, one more cy- cle of aen returns all di gital output pins and bi- directional pins to a high-impedance state. 6.2.3 continuity cycle the combination of a complete output cycle, a complete input cycle, and an additional aen cycle is called a continui ty cycle. each conti- nuity cycle lasts for 85 aen clock cycles. the first continuity cycle can be followed by addi- tional continuity cycl es by keeping test low and continuing to cycle aen. when test is driven high, the cs8900a exits boundary scan mode and aen is again used as the isa- bus address enable. figure 32 shows a complete boundary scan continuity cycle. figure 33 shows boundary scan timing. dmack1 14 ior 61 dmack0 16 iow 62 sd08-sd15 27-24, 21-18 sd0 - sd7 65-68, 71-74 memw 28 reset 75 memr 29 sleep 77 pin name pin # pin name pin # aen 63 cl- 82 test 76 rxd+ 91 dl+ 79 rxd- 92 dl- 80 xtal1 97 cl+ 81 table 42. pin name pin # pin name pin # table 41. (continued)
110 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet enter boundary scan: cs8900a resets, all digital output pins and bi-directional pins enter high-z state, and aen becomes shift clock aen switches high output cycle aen switches low selected output goes low aen switches high 34 cycles input cycle aen switches low selected input copied out to the eedataout pin aen switches high 50 cycles all digital output pins and bi-directional pins enters high-z state test switches low (aen must be low) not in boundary scan test mode aen switches low aen switches high exit boundary scan: aen becomes isa bus address enable test switches high figure 32. boundary scan continuity cycle
ds271f5 111 cs8900a crystal lan? ethernet controller cirrus logic product datasheet testsel aen outputs all outputs tri-state lanled low bstatus low eedataout reset copied out elcs copied out outputs hi z output test 34 clocks input test 50 clocks outputs hi z 1 clock complete continuity cycle 85 clocks linkled low sleep copied out figure 33. boundary scan timing
112 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 7.0 characteristics/specifications - commercial 7.1 absolute maximum ratings (avss, dvss = 0 v, all volt ages with respect to 0 v.) warning: normal operation is no t guaranteed at these extremes. 7.2 recommended operating conditions (avss, dvss = 0 v, all voltages with respect to 0 v.) 7.3 dc characteristics (t a = 25 c; vdd = 5.0 v or vdd = 3.3v) notes: 1. with digital outputs connected to cmos loads. parameter symbol min max unit power supply digital analog d v dd a v dd -0.3 -0.3 6.0 6.0 v v input current (except supply pins) - 10.0 ma analog input voltage -0.3 ( a v dd +) + 0.3 v digital input voltage -0.3 ( d v dd ) + 0.3 v ambient temperature (power applied) -55 +125 c storage temperature -65 +150 c parameter symbol min max unit 5.0v power supply cs8900a-cq, -cqz & -iq, -iqz digital analog d v dd a v dd 4.75 4.75 5.25 5.25 v v 3.3v power supply cs8900a-cq3, -cq3z & -iq3, -iq3z digital analog d v dd a v dd 3.135 3.135 3.465 3.465 v v operating ambient temperature cs8900a-cq, -cqz & -cq3, -cq3z t a 0+70c operating ambient temperature cs 8900a-iq, -iqz & -iq3, -iq3z t a -40 +85 c parameter symbol min max unit crystal (when using external clock - square wave) xtal1 input low voltage v ixh -0.5 0.4 v xtal1 input high voltage v ixh 3.5 d v dd + 0.5 v xtal1 input low current i ixl -40 - a xtal1 input high current i ixh -40a power supply hardware standby mode current (note 1) i ddstndby -2.0ma hardware suspend mode current (note 1) i ddhwsus -100a software suspend mode current (note 1) i ddswsus -1.0ma
ds271f5 113 cs8900a crystal lan? ethernet controller cirrus logic product datasheet dc characteristics (continued) notes: 2. od24: open drain output with 24 ma drive od10: open drain output with 10 ma drive b24: bi-directional with 3-state output and 24 ma drive b4w: bi-directional with 3-state output , internal weak pullup, and 4 ma drive o24ts: 3-state output with 24 ma drive o4: output with 4 ma drive i: input iw: input with internal weak pullup parameter symbol min typ max unit digital inputs and outputs (note 2) power supply current while active 5.0v i dd -60-ma power supply current while active 3.3v i dd -50-ma output low voltage i ol = 24 ma od24, b24, o24ts i ol = 10 ma od10 i ol = 4 ma b4w, o4 v ol - - - - - - 0.4 0.4 0.4 v v v output low voltage (all outputs) v dd = 3.3v and t a = >70c v ol 0.425 v output high voltage i oh = -12 ma b24 i oh = -2 ma b4w, o24ts, o4 v oh 2.4 2.4 - - - - v v output leakage current 0 v out v cc od24, od10, b24, o24ts b4w i ll -10 -20 - - 10 10 a input low voltage i, iw v il --0.8v input high voltage i, iw v ih 2.4 - - v input leakage current 0 v in v cc i iw i l -10 -20 - - 10 10 a 10base-t interface transmitter differential output voltage (peak) v od 2.2 - 2.8 v receiver normal squelch level (peak) v isq 300 - 525 mv receiver low squelch level (lorxsquelch bit set) v sql 125 - 290 mv aui interface transmitter differential output voltage (do+/do- peak) v aod -0.8-v transmitter undershoot voltage v aodu -75-mv transmitter differential idle voltage (do+/do- peak) v idle -30-mv receiver squelch level (di+/di- peak) v aisq -240-mv
114 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 7.4 switching characteristics (t a = 25 c; v dd = 5.0 v or vdd = 3.3v) parameter symbol min typ max unit 16-bit i/o read , iochrdy not used address, aen, sbhe active to iocs16 low t ior1 - - 35 ns address, aen, sbhe active to ior active t ior2 10 - - ns ior low to sd valid t ior3 --135ns address, aen, sbhe hold after ior inactive t ior4 0- -ns ior inactive to active t ior5 35 - - ns ior inactive to sd 3-state t ior6 -30-ns 16-bit i/o read, with iochrdy ior active to iorchrdy inactive t ior7 -30-ns iochrdy low pulse width t ior8 125 - 175 ns iochrdy active to sd valid t ior9 --0ns sa [15:0], aen, sbhe valid address iocs16 in direction: in or out of chip ior sd [15:0] valid data out in out t ior1 t ior2 t ior3 t ior4 t ior5 t ior6 figure 34. 16-bit i/o read, iochrdy not used sa [15:0], aen, sbhe valid address iocs16 in direction: in or out of chip ior sd [15:0] valid data out in out iochrdy out t ior7 t ior8 t ior9 figure 35. 16-bit i /o read, with iochrdy
ds271f5 115 cs8900a crystal lan? ethernet controller cirrus logic product datasheet switching char acteristics (continued) parameter symbol min typ max unit 16-bit memory read, iochrdy not used sa [19:0], sbhe , chipsel , active to memcs16 low t memr1 - - 30 ns address, sbhe , chipsel active to memr active t memr2 10 - - ns memr low to sd valid t memr3 --135ns address, sbhe , chipsel hold after memr inactive t memr4 0- -ns memr inactive to sd 3-state t memr5 -30-ns memr inactive to active t memr6 35 - - ns 16-bit memory r ead, with iochrdy memr low to iochrdy inactive t memr7 -35-ns iochrdy low pulse width t memr8 125 - 175 ns iochrdy active to sd valid t memr9 --0ns sa [19:0], sbhe, chipsel valid address memcs16 in direction: in or out of chip memr sd [15:0] valid data out in out t memr1 t memr2 t memr3 t memr4 t memr5 t memr6 figure 36. 16-bit memory read, iochrdy not used sa [19:0], sbhe, chipsel valid address memcs16 in direction: in or out of chip memr sd [15:0] valid data out in out iochrdy out t memr7 t memr8 t memr9 figure 37. 16-bit memo ry read, with iochrdy
116 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet switching characteristics (continued) parameter symbol min typ max unit dma read dmackx active to ior active t dmar1 60 - - ns aen active to ior active t dmar2 10 - - ns ior active to data valid t dmar3 --135ns ior inactive to sd 3-state t dmar4 -30-ns ior n-1 high to dmarqx inactive t dmar5 - - 20 ns dmackx , aen hold after ior high t dmar6 20 ns 16-bit i/o write address, aen, sbhe valid to iocs16 low t iow1 - - 35 ns address, aen, sbhe valid to iow low t iow2 20 - - ns iow pulse width t iow3 110 - - ns sd hold after iow high t iow4 0- -ns iow low to sd valid t iow5 - - 10 ns iow inactive to active t iow6 35 - - ns address hold after iow high t iow7 0- -ns direction: in or out of chip sd[15:0] out ior dmarqx out in dmackx in aen in t dma1 ior n ior n-1 t dma2 valid data valid data valid data t dma3 t dma5 t dma4 t dma6 figure 38. 16-bit dma read figure 39. 16-bit i/o write sa [15:0], aen, sbhe valid address iocs16 in direction: in or out of chip iow sd [15:0] valid data in out in in t iow1 t iow2 t iow3 t iow4 t iow5 t iow6 t iow7
ds271f5 117 cs8900a crystal lan? ethernet controller cirrus logic product datasheet switching char acteristics (continued) parameter symbol min typ max unit 16-bit memory write address, sbhe , chipsel valid to memcs16 low t memw1 - - 30 ns address, sbhe , chipsel valid to memw low t memw2 20 - - ns memw pulse width t memw3 110 - - ns memw low to sd valid t memw4 - - 40 ns sd hold after memw high t memw5 0- -ns address hold after memw inactive t memw6 0- -ns memw inactive to active t memw7 35 - - ns 10base-t transmit txd pair jitter into 100 load t ttx1 --8ns txd pair return to 50 mv after last positive transition t ttx2 --4.5s txd pair positive hold time at end of packet t ttx3 250 - - ns sa [19:0], sbhe, chipsel valid address memcs16 in direction: in or out of chip memw sd [15:0] valid data in out in in t memw3 t memw4 t memw5 t memw6 t memw7 t memw2 t memw1 figure 40. 16-bit memory write txd t ttx1 t ttx3 t ttx2 figure 41. 10base-t transmit
118 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet switching characteristics (continued) parameter symbol min typ max unit 10base-t receive allowable received jitter at bit cell center t trx1 --13.5ns allowable received jitter at bit cell boundary t trx2 --13.5ns carrier sense assertion delay t trx3 -540-ns invalid preamble bits after assertion of carrier sense t trx4 1-2bits carrier sense deassertion delay t trx5 -270-ns 10base-t link integrity first transmitted link pulse after last transmitted packet t ln1 81624ms time between transmitted link pulses t ln2 81624ms width of transmitted link pulses t ln3 60 100 200 ns minimum received link pulse separation t ln4 2-7ms maximum received link pulse separation t ln5 25 - 150 ms last receive activity to link fail (link loss timer) t ln6 50 - 150 ms t trx3 rxd t trx5 t trx4 t trx1 t trx2 carrier sense (internal) figure 42. 10base-t receive rxd linkled txd t ln1 t ln2 t ln3 t ln4 t ln5 t ln6 figure 43. 10base-t link integrity
ds271f5 119 cs8900a crystal lan? ethernet controller cirrus logic product datasheet switching char acteristics (continued) parameter symbol min typ max unit aui transmit do pair rise and fall times t atx1 -4-ns do pair jitter at bit cell center t atx2 -0.4-ns do pair positive hold time at start of idle t atx3 -250-ns do pair return to 40 mvp after last positive transition t atx4 -6.0-s aui receive di pair rise and fall time t arx1 -8-ns allowable bit cell center and boundary jitter in data t arx2 -14-ns carrier sense assertion delay t arx3 -240-ns invalid preamble bits after carrier sense asserts t arx4 -2-bits carrier sense deassertion delay t arx5 -200-ns aui collision ci pair cycle time t acl1 -100-ns ci pair rise and fall times t acl2 -8-ns ci pair return to zero from last positive transition t acl3 -200-ns collision assertion delay t acl4 -125-ns collision deassertion delay t acl5 -225-ns do t atx1 t atx1 t atx2 t atx4 t atx3 1 0 0 0 figure 44. aui transmit di t arx1 t arx2 1 0 1 0 t arx3 t arx4 t arx5 t arx1 carrier sense (internal) figure 45. aui receive t acl1 ci t acl4 t acl5 collision (internal) t acl2 t acl2 t acl3 figure 46. aui collision
120 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet switching characteristics (continued) parameter symbol min typ max unit external boot prom access address active to memr t bprom1 20 - - ns memr active to csout low t bprom2 - - 35 ns memr inactive to csout high t bprom3 - - 40 ns eeprom eesk setup time relative to eecs t sks 100 - - ns eecs/elcs _b setup time wrt eesk t ccs 250 - - ns eedataout setup time wrt eesk t dis 250 - - ns eedataout hold time wrt eesk t dih 500 - - ns eedatain hold time wrt eesk t dh 10 - - ns eecs hold time wrt eesk t csh 100 - - ns min eecs low time during programming t cs 1000 - - ns sa [19:0] memr t bprom1 csout cs t bprom3 t bprom2 figure 47. external boot prom access t csh t cs t sks t css t dis t dih t dh eesk eecs eedata out eedata in (read) figure 48. eeprom
ds271f5 121 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 7.5 10base-t wiring ? if a center tap transformer is used on the rxd+ and rx d- inputs, replace the pair of rr re- sistors with a singl e 2xrr resistor. ? the rt and rr resist ors are 1% tolerance. ? the cs8900a suppor ts 100, 120, and 150 unshielded twisted pair c ables. the proper val- ues of rt and rr, for a given cable impedance, are shown below: ? note: for 3.3v operation the turns ratio on txd+ and txd- is 1:2.5, rt is 8 for 100 cable and the 68pf cap changes to 560pf. cable impedance ( )rt ( ) rr ( ) 100 24.3 49.9 120 30.1 60.4 150 37.4 75 rt rt cs8900a td + td - txd + txd - 1 : 2 rj45 1 2 1 : 1 rd + rd - 3 6 0.01 f + rxd+ rxd- rr rr 0.01 f - 68 pf
122 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 7.6 aui wiring 7.7 quartz crystal requirements (if a 20 mhz quartz crystal is used, it must meet the fol- lowing specifications) parameter min typ max unit parallel resonant frequency - 20 - mhz resonant frequency error (c l = 18 pf) -50 - +50 ppm resonant frequency change over operating temperature -40 - +40 ppm crystal capacitance - - 18 pf motional crystal capacitance - 0.022 - pf series resistance - - 50 ohm shunt capacitance - - 7 pf cs8900a do + do - 1 : 1 db15 3 10 tx 4 1 : 1 5 12 13 6 +12 v + ci + ci - 1 : 1 2 9 39.2 39.2 col 0.01 uf - + di + di - 39.2 39.2 rx 0.01 uf -
ds271f5 123 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 8.0 characteristics/spec ifications - industrial 8.1 absolute maximum ratings (avss, dvss = 0 v, all volt ages with respect to 0 v.) warning: normal operation is no t guaranteed at these extremes. 8.2 recommended operating conditions (avss, dvss = 0 v, all voltages with respect to 0 v.) 8.3 dc characteristics (t a = 25 c; vdd = 5.0 v or vdd = 3.3v) notes: 1. with digital outputs connected to cmos loads. parameter symbol min max unit power supply digital analog d v dd a v dd -0.3 -0.3 6.0 6.0 v v input current (except supply pins) - 10.0 ma analog input voltage -0.3 ( a v dd +) + 0.3 v digital input voltage -0.3 ( d v dd ) + 0.3 v ambient temperature (power applied) -55 +125 c storage temperature -65 +150 c parameter symbol min max unit 5.0v power supply cs8900a-cq, -cqz & -iq, -iqz digital analog d v dd a v dd 4.75 4.75 5.25 5.25 v v 3.3v power supply cs8900a-cq3, cq3z & -iq3, -iq3z digital analog d v dd a v dd 3.135 3.135 3.465 3.465 v v operating ambient temperature cs8900a-cq, -cqz & -cq3, -cq3z t a 0+70c operating ambient temperature cs 8900a-iq, -iqz & -iq3, -iq3z t a -40 +85 c parameter symbol min max unit crystal (when using external clock - square wave) xtal1 input low voltage v ixh -0.5 0.4 v xtal1 input high voltage v ixh 3.5 d v dd + 0.5 v xtal1 input low current i ixl -40 - a xtal1 input high current i ixh -40a power supply hardware standby mode current (note 1) i ddstndby -1.0ma hardware suspend mode current (note 1) i ddhwsus -100a software suspend mode current (note 1) i ddswsus -1.0ma
124 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet dc characteristics (continued) notes: 2. od24: open drain output with 24 ma drive od10: open drain output with 10 ma drive b24: bi-directional with 3-state output and 24 ma drive b4w: bi-directional with 3-state output , internal weak pullup, and 4 ma drive o24ts: 3-state output with 24 ma drive o4: output with 4 ma drive i: input iw: input with internal weak pullup parameter symbol min typ max unit digital inputs and outputs (note 2) power supply current while active 5.0v i dd -60-ma power supply current while active 3.3v i dd -50-ma output low voltage i ol = 24 ma od24, b24, o24ts i ol = 10 ma od10 i ol = 4 ma b4w, o4 v ol - - - - - - 0.4 0.4 0.4 v v v output low voltage (all outputs) v dd = 3.3v and t a = >70c v ol 0.425 v output high voltage i oh = -12 ma b24 i oh = -2 ma b4w, o24ts, o4 v oh 2.4 2.4 - - - - v v output leakage current 0 v out v cc od24, od10, b24, o24ts b4w i ll -10 -20 - - 10 10 a input low voltage i, iw v il --0.8v input high voltage i, iw v ih 2.4 - - v input leakage current 0 v in v cc i iw i l -10 -20 - - 10 10 a 10base-t interface transmitter differential output voltage (peak) v od 2.2 - 2.8 v receiver normal squelch level (peak) v isq 300 - 525 mv receiver low squelch level (lorxsquelch bit set) v sql 125 - 290 mv aui interface transmitter differential output voltage (do+/do- peak) v aod -0.8-v transmitter undershoot voltage v aodu -75-mv transmitter differential idle voltage (do+/do- peak) v idle -30-mv receiver squelch level (di+/di- peak) v aisq -240-mv
ds271f5 125 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 8.4 switching characteristics (t a = 25 c; v dd = 5.0 v or vdd = 3.3v) parameter symbol min typ max unit 16-bit i/o read , iochrdy not used address, aen, sbhe active to iocs16 low t ior1 - - 35 ns address, aen, sbhe active to ior active t ior2 10 - - ns ior low to sd valid t ior3 --135ns address, aen, sbhe hold after ior inactive t ior4 0- -ns ior inactive to active t ior5 35 - - ns ior inactive to sd 3-state t ior6 -30-ns 16-bit i/o read, with iochrdy ior active to iorchrdy inactive t ior7 -30-ns iochrdy low pulse width t ior8 125 - 175 ns iochrdy active to sd valid t ior9 --0ns sa [15:0], aen, sbhe valid address iocs16 in direction: in or out of chip ior sd [15:0] valid data out in out t ior1 t ior2 t ior3 t ior4 t ior5 t ior6 figure 49. 16-bit i/o read, iochrdy not used sa [15:0], aen, sbhe valid address iocs16 in direction: in or out of chip ior sd [15:0] valid data out in out iochrdy out t ior7 t ior8 t ior9 figure 50. 16-bit i /o read, with iochrdy
126 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet switching characteristics (continued) parameter symbol min typ max unit 16-bit memory read, iochrdy not used sa [19:0], sbhe , chipsel , active to memcs16 low t memr1 - - 30 ns address, sbhe , chipsel active to memr active t memr2 10 - - ns memr low to sd valid t memr3 --135ns address, sbhe , chipsel hold after memr inactive t memr4 0- -ns memr inactive to sd 3-state t memr5 -30-ns memr inactive to active t memr6 35 - - ns 16-bit memory r ead, with iochrdy memr low to iochrdy inactive t memr7 -35-ns iochrdy low pulse width t memr8 125 - 175 ns iochrdy active to sd valid t memr9 --0ns sa [19:0], sbhe, chipsel valid address memcs16 in direction: in or out of chip memr sd [15:0] valid data out in out t memr1 t memr2 t memr3 t memr4 t memr5 t memr6 figure 51. 16-bit memory read, iochrdy not used sa [19:0], sbhe, chipsel valid address memcs16 in direction: in or out of chip memr sd [15:0] valid data out in out iochrdy out t memr7 t memr8 t memr9 figure 52. 16-bit memo ry read, with iochrdy
ds271f5 127 cs8900a crystal lan? ethernet controller cirrus logic product datasheet switching char acteristics (continued) parameter symbol min typ max unit dma read dmackx active to ior active t dmar1 60 - - ns aen active to ior active t dmar2 10 - - ns ior active to data valid t dmar3 --135ns ior inactive to sd 3-state t dmar4 -30-ns ior n-1 high to dmarqx inactive t dmar5 - - 20 ns dmackx , aen hold after ior high t dmar6 20 ns 16-bit i/o write address, aen, sbhe valid to iocs16 low t iow1 - - 35 ns address, aen, sbhe valid to iow low t iow2 20 - - ns iow pulse width t iow3 110 - - ns sd hold after iow high t iow4 0- -ns iow low to sd valid t iow5 - - 10 ns iow inactive to active t iow6 35 - - ns address hold after iow high t iow7 0- -ns direction: in or out of chip sd[15:0] out ior dmarqx out in dmackx in aen in t dma1 ior n ior n-1 t dma2 valid data valid data valid data t dma3 t dma5 t dma4 t dma6 figure 53. 16-bit dma read figure 54. 16-bit i/o write sa [15:0], aen, sbhe valid address iocs16 in direction: in or out of chip iow sd [15:0] valid data in out in in t iow1 t iow2 t iow3 t iow4 t iow5 t iow6 t iow7
128 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet switching characteristics (continued) parameter symbol min typ max unit 16-bit memory write address, sbhe , chipsel valid to memcs16 low t memw1 - - 30 ns address, sbhe , chipsel valid to memw low t memw2 20 - - ns memw pulse width t memw3 110 - - ns memw low to sd valid t memw4 - - 40 ns sd hold after memw high t memw5 0- -ns address hold after memw inactive t memw6 0- -ns memw inactive to active t memw7 35 - - ns 10base-t transmit txd pair jitter into 100 load t ttx1 --8ns txd pair return to 50 mv after last positive transition t ttx2 --4.5s txd pair positive hold time at end of packet t ttx3 250 - - ns sa [19:0], sbhe, chipsel valid address memcs16 in direction: in or out of chip memw sd [15:0] valid data in out in in t memw3 t memw4 t memw5 t memw6 t memw7 t memw2 t memw1 figure 55. 16-bit memory write txd t ttx1 t ttx3 t ttx2 figure 56. 10base-t transmit
ds271f5 129 cs8900a crystal lan? ethernet controller cirrus logic product datasheet switching char acteristics (continued) parameter symbol min typ max unit 10base-t receive allowable received jitter at bit cell center t trx1 --13.5ns allowable received jitter at bit cell boundary t trx2 --13.5ns carrier sense assertion delay t trx3 -540-ns invalid preamble bits after assertion of carrier sense t trx4 1-2bits carrier sense deassertion delay t trx5 -270-ns 10base-t link integrity first transmitted link pulse after last transmitted packet t ln1 81624ms time between transmitted link pulses t ln2 81624ms width of transmitted link pulses t ln3 60 100 200 ns minimum received link pulse separation t ln4 2-7ms maximum received link pulse separation t ln5 25 - 150 ms last receive activity to link fail (link loss timer) t ln6 50 - 150 ms t trx3 rxd t trx5 t trx4 t trx1 t trx2 carrier sense (internal) figure 57. 10base-t receive rxd linkled txd t ln1 t ln2 t ln3 t ln4 t ln5 t ln6 figure 58. 10base-t link integrity
130 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet switching characteristics (continued) parameter symbol min typ max unit aui transmit do pair rise and fall times t atx1 -4-ns do pair jitter at bit cell center t atx2 -0.4-ns do pair positive hold time at start of idle t atx3 -250-ns do pair return to 40 mvp after last positive transition t atx4 -6.0-s aui receive di pair rise and fall time t arx1 -8-ns allowable bit cell center and boundary jitter in data t arx2 -14-ns carrier sense assertion delay t arx3 -240-ns invalid preamble bits after carrier sense asserts t arx4 -2-bits carrier sense deassertion delay t arx5 -200-ns aui collision ci pair cycle time t acl1 -100-ns ci pair rise and fall times t acl2 -8-ns ci pair return to zero from last positive transition t acl3 -200-ns collision assertion delay t acl4 -125-ns collision deassertion delay t acl5 -225-ns do t atx1 t atx1 t atx2 t atx4 t atx3 1 0 0 0 figure 59. aui transmit di t arx1 t arx2 1 0 1 0 t arx3 t arx4 t arx5 t arx1 carrier sense (internal) figure 60. aui receive t acl1 ci t acl4 t acl5 collision (internal) t acl2 t acl2 t acl3 figure 61. aui collision
ds271f5 131 cs8900a crystal lan? ethernet controller cirrus logic product datasheet switching char acteristics (continued) parameter symbol min typ max unit external boot prom access address active to memr t bprom1 20 - - ns memr active to csout low t bprom2 - - 35 ns memr inactive to csout high t bprom3 - - 40 ns eeprom eesk setup time relative to eecs t sks 100 - - ns eecs/elcs _b setup time wrt eesk t ccs 250 - - ns eedataout setup time wrt eesk t dis 250 - - ns eedataout hold time wrt eesk t dih 500 - - ns eedatain hold time wrt eesk t dh 10 - - ns eecs hold time wrt eesk t csh 100 - - ns min eecs low time during programming t cs 1000 - - ns sa [19:0] memr t bprom1 csout cs t bprom3 t bprom2 figure 62. external boot prom access t csh t cs t sks t css t dis t dih t dh eesk eecs eedata out eedata in (read) figure 63. eeprom
132 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 8.5 10base-t wiring ? if a center tap transformer is used on the rxd+ and rx d- inputs, replace the pair of rr re- sistors with a singl e 2xrr resistor. ? the rt and rr resist ors are 1% tolerance. ? the cs8900a supports 100, 120, and 150 unshielded twisted pair c ables. the proper val- ues of rt and rr, for a given cable impedance, are shown below: ? note: for 3.3v operation the turns ratio on txd+ and txd- is 1:2.5, rt is 8 for 100 cable and the 68pf cap changes to 560pf. cable impedance ( )rt ( ) rr ( ) 100 24.3 49.9 120 30.1 60.4 150 37.4 75 rt rt cs8900a td + td - txd + txd - 1 : 2 rj45 1 2 1 : 1 rd + rd - 3 6 0.01 f + rxd+ rxd- rr rr 0.01 f - 68 pf
ds271f5 133 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 8.6 aui wiring 8.7 quartz crystal requirements (if a 20 mhz quartz crystal is used, it must meet the fol- lowing specifications) parameter min typ max unit parallel resonant frequency - 20 - mhz resonant frequency error (c l = 18 pf) -50 - +50 ppm resonant frequency change over operating temperature -40 - +40 ppm crystal capacitance - - 18 pf motional crystal capacitance - 0.022 - pf series resistance - - 50 ohm shunt capacitance - - 7 pf cs8900a do + do - 1 : 1 db15 3 10 tx 4 1 : 1 5 12 13 6 +12 v + ci + ci - 1 : 1 2 9 39.2 39.2 col 0.01 uf - + di + di - 39.2 39.2 rx 0.01 uf -
134 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 9.0 physical dimensions millimeters dim min nom max a --- 1.60 a1 0.05 0.15 b 0.170.220.27 d 16.00 d1 14.00 e 16.00 e1 14.00 e* 0.50 l 0.450.600.75 0.00 7.00 * nominal pin pitch is 0.50 mm controlling dimension is mm. jedec designation: ms026 100l lqfp package drawing e1 e d1 d 1 e l b a1 a
ds271f5 135 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 10.0 glossary of terms 10.1 acronyms aui attachment unit interface crc cyclic redundancy check cs carrier sense csma/cd carrier sense multiple access with collision detection da destination address eeprom electrically erasable programmable read only memory eof end-of-frame fcs frame check sequence fdx full duplex ia individual address ipg inter-packet gap isa industry standard architecture la isa latchable addres s bus (la17 - la23) llc logical link control mac media access control mau medium attachment unit mib management information base rx receive sa source address or isa system addres s bus (sa0 - sa19) sfd start-of-frame delimiter snmp simple network management protocol sof start-of-frame sqe signal quality error tdr time domain reflectometer tx transmit utp unshielded twisted pair
136 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 10.2 definitions cyclic redundancy check the method used to compute t he 32-bit frame check sequence (fcs). frame check sequence the 32-bit field at the end of a frame that contains the result of the cyclic redundancy check (crc). frame an ethernet string of data bits that includes the dest ination address (da), source address (sa), optional length fi eld, logical link control data (llc data), pad bits (if needed) and frame c heck sequence (fcs). individual address the specific ethernet addre ss assigned to a device attac hed to the ethernet media. inter-packet gap time interval between packets on t he ethernet. minimum in terval is 9.6 s. jabber a condition that results when a ethernet node transmits longer than between 20 ms and 150 ms. packet an ethernet string of data bits that includes the preamble, start- of-frame delimiter (sfd), destination address (da), source address (sa), optional length field, logical link control data (llc data) , pad bits (if needed) and frame check sequence (fcs). a packet is a frame pl us the preamble and sfd. receive collision a receive collision occurs w hen the ci+/ci- inputs are ac tive while a packet is being received. applies only to the aui. signal quality error when transmitting on the aui, the mac ex pects to see a collision signal on the ci+/ci- pair wi thin 64 bit times after the end of a tr ansmission. if no collision occurs, there is said to be an "sqe er ror". applies only to the aui. slot time time required for an ethernet frame to cross a maximum length ethernet network. one slot time equals 512 bit times. transmit collision a transmit collision occurs when the receive inputs, rxd+/rxd- (10base-t) or ci+/ci- (aui) are acti ve while a packet is being transmitted.
ds271f5 137 cs8900a crystal lan? ethernet controller cirrus logic product datasheet 10.3 acronyms spec ific to the cs8900a bufcfg buffer configur ation - register b bufevent buffer event - register c busctl bus control - register 17 busst bus state - register 18 endec manchester encoder/decoder isq interrupt status queue - register 0 linectl ethernet line c ontrol - register 13 linest ethernet line st atus - register 14 rxcfg receive configur ation - register 3 rxctl receive control - register 5 rxevent receive event - register 4 selfctl self control - register 15 selfst self status - register 16 testctl test control - register 19 txcfg transmit configur ation - register 7 txcmd transmit command txevent transmit ev ent - register 8 10.4 definitions specific to the cs8900a act-once bit a control bit that causes t he cs8900a to take a certain ac tion once when a logic "1" is written to that bit. to cause the acti on again, the host must rewrite a "1". committed receive frame a receive frame is said to be "committed" after the fr ame has been buffered by the cs8900a, and the host has been not ified, but the frame has not yet been transferred by the host. committed transmit frame a transmit frame is said to be "committed" after th e host has issued a transmit command, and the cs8900a has reserved buffer space and no tified the host that it is ready for transmit. event or interrupt event the term "event" is used in this document to refer to something that can trigger an interrupt. items that are cons idered "events" are reported in the three event registers (rxevent, txevent, or bufevent) and in two counter-overflow bits (rxmiss and txcol). streamtransfer a method used to significant ly reduce the number of inte rrupts to the host processor during block data tran sfers (patent pending). packetpage a unified, highly-effi cient method of cont rolling and getting st atus of a peripheral controller in i/o or memory space.
138 ds271f5 cs8900a crystal lan? ethernet controller cirrus logic product datasheet standby a feature of the cs8900a used to conserve power. wh en in standby mode, the cs8900a can be awakened either by 10b ase-t activity or host command. suspend a feature of the cs 8900a used to conserve power. when in suspend mode, the cs8900a can be awakened only by host command. transfer the term "transfer" refers to moving fram e data across the isa bus to or from the cs8900a. transmit request a transmit request is issued by the host to initiate the st art of a new packet transmission. a transmit request consists of the following three steps in exactly the order shown: 1) the host writes a transmit command to the txcmd register (pa cketpage base + 0144h). 2) the host writes the transmit frame's lengt h to the txlength regist er (packetpage base + 0146h). 3) the host reads busst (register 18) to s ee in the rdy4txnow bi t (bit 8) is set. 10.5 suffixes speci fic to the cs8900a. these terms have meaning only at the end of a term: a accept cmd command cfg configure ctl control dis disable e enable h indicates the number is hexadecimal ie interrupt enable st status

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