memory array 512 x 2048 package details pin count description package type 32 lcc (0.45 x 0.55" nom) w package details on pages 8 & 9. see page 9 for x pinout pin functions a0-a16 address inputs d0-7 data input/output cs1 chip select 1 cs2 chip select 2 oe output enable we write enable nc no connect v cc power (+5v) gnd ground 128k x 8 sram msm8128a - 85/10/12 issue 1.0 april 2001 block diagram 131,072 x 8 cmos static ram features access times of 85/100/120 ns jedec standard dual cs footprints. operating power 605 mw (max) low power standby (-l) 2.53 mw (max) low voltage data retention. completely static operation directly ttl compatible. may be processed in accordance with mil-std-883 description the msm8128 is a 1mbit monolithic sram organised as 128k x 8. it is available in with access times of 85, 100 & 120ns. it has a low power standby version and has 3.0v battery backup capability. it is directly ttl compatible and has common data inputs and outputs. two pinout variants (single and dual cs) are available. all versions may be screened in accordance with mil-std-883. elm road, west chirton, north shields, tyne & wear ne29 8se, england tel. +44 (0191) 2930500 fax. +44 (0191) 2590997 pin definition top view j d1 d2 d4 gnd d3 d5 d6 a12 a14 vcc a16 nc a15 cs2 14 15 18 16 17 19 20 4 3 32 2 1 31 30 d 0 a 0 a 3 a1 a 2 a 4 a 5 a 6 a 7 d7 cs1 a11 a10 oe a9 a8 a13 we 21 22 25 23 24 26 27 28 29 13 12 9 11 10 8 7 6 5 trailing edge product - minimum order applies product may be made obsolete without notice
msm8128 - 70/85/10/12 issue 1.0 april 2001 2 absolute maximum ratings voltage on any pin relative to v ss v t -0.5v to +7.0 v power dissipation p t 1w storage temperature t stg -55 to +150 o c notes : (1) stresses above those listed may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions min typ max supply voltage v cc 4.5 5.0 5.5 v input high voltage v ih 2.2 - 5.8 v input low voltage v il -0.3 - 0.8 v operating temperature t a 0-70 o c t ai -40 - 85 o c ( i suffix) t am -55 - 125 o c ( m , mb suffix) dc operating conditions capacitance (v cc =5v10%,t a =25 o c) parameter symbol test condition typ max unit i/p capacitance c in v in =0v - 8 pf i/o capacitance c i/o v i/o =0v - 10 pf note: this parameter is sampled and not 100% tested. dc electrical characteristics (v cc = 5.0v10%, t a =-55c to +125c) parameter symbol test condition min typ max unit input leakage current i li v ih =0v to v cc -1 - 1 a output leakage current i l/o cs1=v ih , cs2 =v il , v i/o =0v to v cc ,oe=v ih -1 - 1 a average supply current i cc1 min. cycle, v in =v il or v ih - - 110 ma standby supply current i sb1 cs1=v ih ,cs2 = v il , i/p's static - - 3.5 ma -l part i sb2 cs1 v cc -0.2v, 0.2v cs2 v cc -0.2v , v in 0.2v - - 460 ua output voltage v ol i ol = 2.1 ma - - 0.4 v v oh i oh = -1.0 ma 2.4 - - v
msm8128 - 70/85/10/12 issue 1.0 april 2001 3 operating modes the table below shows the logic inputs required to control the msm8128 sram. mode cs1 cs2 oe we v cc current i/o pin reference cycle not selected 1 x x x i sb1 ,i sb2 high z power down not selected x 0 x x i sb ,i sb1 high z power down output disable 0 1 1 1 i cc high z read 0 1 0 1 i cc d out read cycle write 0 1 x 0 i cc d in write cycle 1 = v ih ,0 = v il , x = don't care low v cc data retention characteristics - l version only (t a =-55 c to +125 o c) parameter symbol test condition min typ max unit v cc for data retention v dr cs1 v cc -0.2v, cs2 v cc -0.2v or 0v cs2 0.2v. v in 0v 2.0 - - v data retention current i ccdr v cc =3.0v,v in 0v, cs1 v cc -0.2v, cs2 v cc -0.2v or 0v cs2 0.2v. - - 700 a chip deselect to data retention t cdr see retention waveform 0--ns operation recovery time t r see retention waveform 5--ms notes (1) cs2 controls address buffer, we buffer, cs1 buffer and oe buffer. if cs2 controls data retention mode, vin levels (we,oe,cs1,i/o) can be in the high impedance state. if cs1 controls data retention mode, cs2 must be v cc - 0.2v or 0v cs2 0.2v. the other input levels (address, we,oe,i/o) can be in the high impedance state. ac test conditions output load * input pulse levels: 0v to 3.0v * input rise and fall times: 5ns * input and output timing reference levels: 1.5v * output load: see load diagram * v cc =5v10% 166 30pf i/o pin 1.76v ?
msm8128 - 70/85/10/12 issue 1.0 april 2001 4 1234567890123456789 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1234567890123456789 1234567890123456789 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1 23456789012345678 9 1234567890123456789 ac operating conditions read cycle 70 85 10 12 parameter symbol min max min max min max min max unit read cycle time t rc 70 - 85 - 100 - 120 - ns address access time t aa - 70 - 85 - 100 - 120 ns chip select (cs1) access time (2) t acs1 - 70 - 85 - 100 - 120 ns chip select (cs2) access time (2) t acs2 - 70 - 85 - 100 - 120 ns output enable to output valid t oe -35-45-50-60ns output hold from address change t oh 5-5-10-10-ns chip selection (cs1) to output in low z t clz1 10 - 10 - 10 - 10 - ns chip selection (cs2) to output in low z t clz2 10 - 10 - 10 - 10 - ns output enable to output in low z t olz 5-5-5-5-ns chip disable (cs1) to output in high z (3) t chz1 035035035045ns chip disable (cs2) to output in high z (3) t chz2 035035035045ns output disable to output in high z (3) t ohz 030030035045ns write cycle 70 85 10 12 parameter symbol min max min max min max min max unit write cycle time t wc 70 - 85 - 100 - 120 - ns chip selection to end of write t cw 60 - 75 - 85 - 100 - ns address valid to end of write t aw 60 - 75 - 85 - 100 - ns address setup time t as 0-0-0-0-ns write pulse width t wp 50 - 60 - 70 - 70 - ns write recovery time (we, cs1) t wr1 5-5-5-5-ns (cs2) t wr2 5-5-5-5-ns write to output in high z t whz 030030035040ns data to write time overlap t dw 30 - 35 - 40 - 45 - ns data hold from write time t dh 0-0-0-0-ns output active from end of write t ow 5-5-5-5-ns 123456789012345 1 2345678901234 5 1 2345678901234 5 1 2345678901234 5 1 2345678901234 5 123456789012345 consult factory
msm8128 - 70/85/10/12 issue 1.0 april 2001 5 notes: (1) we is high for read cycle. (2) address valid prior to or coincident with cs1 transition low or cs2 high. (3) t chz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. at any given temperature and voltage condition, t chz max is less than t clz min both for a given device and from device to device. this parameter is sampled and not 100% tested. read cycle timing waveform (1,2 ) t t t t rc aa oe oh address oe cs1 data valid t t acs2 (2) t clz2 ohz (3) t chz2 (3) dout t olz t acs1 (2) t clz1 t chz1 (3) cs2
msm8128 - 70/85/10/12 issue 1.0 april 2001 6 write cycle no.1 timing waveform t t t t wc as (3) aw address cs1 t t t wp(1) dw dh we din t wr1,2 (2) high - z data valid oe (6) ohz(3,9) t dout cs2 (6) cw (4) t wr1,2 (2) cs1 t cw (4) t t t wp (1) dw dh we dout din t as (3) t aw t wc address high - z data valid (6) t whz(3,9) high - z t ow t oh (7) (8) (6) cs2 write cycle no.2 timing waveform (5)
msm8128 - 70/85/10/12 issue 1.0 april 2001 7 low v cc data retention timing waveform 1 (cs1 controlled) low v cc data retention timing waveform 2 (cs2 controlled) t r t cdr 4.5v 2.2v 4.5v 2.2v 0v data retention mode vcc cs1 v dr cs1 vcc-0.2v 4.5v 4.5v 0v data retention mode vcc cs2 v dr2 0.4v t r t cdr cs2 0.2v ac characteristics notes (1) a write occurs during the overlap of a low cs1, a high cs2 and a low we. a write begins at the latest transition among cs1 going low, cs2 going high and we going low. a write ends at the earliest transition among cs1 going high, cs2 going low and we going high. t wp is measured from the beginning of write to the end of write. (2) t wr is measured from the earlier of cs1 or we going high or cs2 going high to the end of write cycle. (3) during this period, i/o pins are in the output state. input signals out of phase must not be applied. (4) if cs1 goes low simultaneously with we going low or after we going low, outputs remain in high impedance state. (5) oe is continuously low. (oe=v il ) (6) dout is in the same phase as written data of this write cycle. (7) dout is the read data of next address. (8) if cs1 is low and cs2 is high during this period, i/o pins are in the output state. input signals out of phase must not b e applied to i/o pins. (9) t whz is defined as the time at which the outputs achieve the open circuit conditions and is not referenced to output voltage levels. these parameters are sampled and not 100% tested.
msm8128 - 70/85/10/12 issue 1.0 april 2001 8 32 pad lcc -'w' package 14.22 (0.560) 13.84 (0.545) no. 1 index 11.70 (0.460) 11.30 (0.445) 2.03 (0.080) max 1.27 (0.050) typ 0.64 (0.025) typ 1.27 (0.050) typ 7.87 (0.310) 7.37 (0.290) 10.42 (0.410) 9.92 (0.390)
msm8128 - 70/85/10/12 issue 1.0 april 2001 9 military screening procedure component screening flow for high reliability product is in accordance with mil-883 method 5004 visual and mechanical internal visual 2010 condition b or manufacturers equivalent 100% temperature cycle 1010 condition c (10 cycles,-65 o c to +150 o c) 100% constant acceleration 2001 condition e (y, only) (30,000g) 100% pre-burn-in electrical per applicable device specifications at t a =+25 o c 100% burn-in method 1015,condition d,t a =+125 o c,160hrs min 100% final electrical tests per applicable device specification static (dc) a) @ t a =+25 o c and power supply extremes 100% b) @ temperature and power supply extremes 100% functional a) @ t a =+25 o c and power supply extremes 100% b) @ temperature and power supply extremes 100% switching (ac) a) @ t a =+25 o c and power supply extremes 100% b) @ temperature and power supply extremes 100% percent defective allowable (pda) calculated at post-burn-in at t a =+25 o c 5% hermeticity 1014 fine condition a 100% gross condition c 100% external visual 2009 per vendor or customer specification 100% screen test method level mb component screening flow alternate pin definition - x variant top view j,w d1 d2 d4 gnd d3 d5 d6 a12 a15 vcc a16 nc a14 nc 14 15 18 16 17 19 20 4 3 32 2 1 31 30 d 0 a 0 a 3 a1 a 2 a 4 a 5 a 6 a 7 d7 cs a11 a10 oe a9 a8 a13 21 22 25 23 24 26 27 28 29 13 12 9 11 10 8 7 6 5 we
msm8128 - 70/85/10/12 issue 1.0 april 2001 10 although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. our products are subjected to a constant process of development. data may be changed at any time without notice. products are not authorised for use as critical components in life support devices without the express written approval of a company director. these devices are not recommended for new designs and may be made obsolete without notice.... msm8128walmb-85 access time 70 = 70ns 85 = 85ns 10 = 100ns 12 = 120ns temperature grade blank = commercial i = industrial m = military mb = screened in accordance with mil-std-883 power rating blank = standard l = low power package variant a = 0.45 x 0.55" (nom) dimensions package w = lcc package density 8128 = 128k x 8 sram msm = sram monolithic
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