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| products and specifications discussed herein ar e subject to change by micron without notice. 1gb: x4, x8, x16 ddr2 sdram features pdf: 09005aef821ae8bf/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr2_x4x8x16_d1.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 1 ?2004 micron technology, inc. all rights reserved. ddr2 sdram mt47h256m4 ? 32 meg x 4 x 8 banks mt47h128m8 ? 16 meg x 8 x 8 banks mt47h64m16 ? 8 meg x 16 x 8 banks features ?rohs compliant ?v dd = +1.8v 0.1v, v dd q = +1.8v 0.1v ? jedec-standard 1.8v i/ o (sstl_18-compatible) ? differential data strobe (dqs, dqs#) option ?4 n -bit prefetch architecture ? duplicate output strobe (rdqs) option for x8 ? dll to align dq and dqs transitions with ck ? 8 internal banks for concurrent operation ? programmable cas latency (cl) ? posted cas additive latency (al) ? write latency = read latency - 1 t ck ? selectable burst lengths (bl): 4 or 8 ? adjustable data-output drive strength ? 64ms, 8,192-cycle refresh ? on-die termination (odt) ? industrial temperature (it) option ? supports jedec clock jitter specification notes: 1. not recommended for new designs. options marking ? configuration ? 256 meg x 4 (32 meg x 4 x 8 banks) 256m4 ? 128 meg x 8 (16 meg x 8 x 8 banks) 128m8 ? 64 meg x 16 (8 meg x 16 x 8 banks) 64m16 ? fbga package (pb-free) ? 92-ball fbga (11mm x 19mm) rev. a bt ? 84-ball fbga (8mm x 12.5mm) rev. e, g hr ? 60-ball fbga (8mm x 11.5mm) rev. e, g hq ? fbga package (lead solder) ? 84-ball fbga (8mm x 12.5mm) rev. e, g hw ? 60-ball fbga (8mm x 11.5mm) rev. e, g hv ? timing ? cycle time ? 1.875ns @ cl = 7 (ddr2-1066) -187e ? 2.5ns @ cl = 5 (ddr2-800) -25e ? 2.5ns @ cl = 6 (ddr2-800) -25 ? 3.0ns @ cl = 4 (ddr2-667) -3e ? 3.0ns @ cl = 5 (ddr2-667) -3 ? 3.75ns @ cl = 4 (ddr2-533) -37e 1 ? 5.0ns @ cl = 3 (ddr2-400) -5e 1 ? self refresh ? standard none ? low-power l ? operating temperature ? commercial (0c t c 85c) none ? industrial (?40c t c 95c; ?40c t a 85c) it ? revision :a 1 /:e/:g table 1: key timing parameters speed grade data rate (mt/s) t rc (ns) cl = 3 cl = 4 cl = 5 cl = 6 cl = 7 -187e n/a n/a 667 800 1066 54 -25e n/a 533 800 800 n/a 55 -25 n/a 533 667 800 n/a 55 -3e n/a 667 667 n/a n/a 54 -3 400 533 667 n/a n/a 55 -37e 400 533 n/a n/a n/a 55 -5e 400 400 n/a n/a n/a 55
pdf: 09005aef821ae8bf/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr2_x4x8x16_d1.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 2 ?2004 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram features figure 1: 1gb ddr2 part numbers notes: 1. not all speeds and configurat ions are available in all packages. fbga part number system due to space limitations, fbga-packaged components have an abbreviated part marking that is different from the part number. for a quick conversion of an fbga code, see the fbga part marking decoder on micron?s web site: www.micron.com . table 2: addressing parameter 256 meg x 4 128 meg x 8 64 meg x 16 configuration 32 meg x 4 x 8 banks 16 meg x 8 x 8 banks 8 meg x 16 x 8 banks refresh count 8k 8k 8k row address a0?a13 (16k) a0?a13 (16k) a0?a12 (8k) bank address ba0?ba2 (8) ba0?ba2 (8) ba0?ba2 (8) column address a0?a9, a11 (2k) a0?a9 (1k) a0?a9 (1k) package pb-free 92-ball 11mm x 19mm fbga 84-ball 8mm x 12.5mm fbga 60-ball 8mm x 11.5mm fbga lead solder 84-ball 8mm x 12.5mm fbga 60-ball 8mm x 11.5mm fbga bt hr hq hw hv example part number: mt47h128m8bt-37e configuration 256 meg x 4 128 meg x 8 64 meg x 16 256m4 128m8 64m16 speed grade t ck = 1.875ns, cl = 7 t ck = 2.5ns, cl = 5 t ck = 2.5ns, cl = 6 t ck = 3ns, cl = 4 t ck = 3ns, cl = 5 t ck = 3.75ns, cl = 4 t ck = 5ns, cl = 3 -187e -25e -25 -3e -3 -37e -5e - configuration mt47h package speed revision revision :a/:e/:g : low power industrial temperature l it { pdf: 09005aef821ae8bf/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr2_x4x8x16toc.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 3 ?2004 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram table of contents table of contents fbga part number system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 industrial temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 automotive temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 general notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 functional block diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 ball assignments and descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 electrical specifications ? absolute rati ngs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 temperature and thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 electrical specifications ? i dd parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 i dd specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 i dd 7 conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 ac timing operating specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 ac and dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 odt dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 input electrical characteristics and operat ing conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 output electrical charac teristics and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 output driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 power and ground clamp characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 ac overshoot/undershoot specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 input slew rate derating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 deselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 no operation (nop). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 load mode (lm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 activate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 mode register (mr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 extended mode register (emr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 extended mode register 2 (emr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 extended mode register 3 (emr 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 activate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 precharge power-down clock frequency change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 odt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mrs command to odt update delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core1.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 4 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram state diagram state diagram figure 2: simplified state diagram notes: 1. this diagram provides th e basic command flow. it is not co mprehensive and does not iden- tify all timing requirem ents or possible command restrictions such as multibank interaction, power down, entry/exit, etc. automati c s e q uen c e c omman d s e q uen c e pre initialization se q uen c e s elf refreshin g c ke l refreshin g pre c har g e power- d own s ettin g mr s emr s s r c ke h refre s h i d le all b anks pre c har g e d c ke l c ke l c ke l (e)mr s o c d d efault a c tivatin g a c t bank a c tive rea d in g read writin g write a c tive power- d own c ke l c ke l c ke h c ke l writin g with auto pre c har g e rea d in g with auto pre c har g e read ap write ap pre, pre a write ap read ap read write pre c har g in g c ke h write read pre, pre a a c t = a c tivate c ke h = c ke hi g h, exit power- d own or self refresh c ke l = c ke low, enter power- d own (e)mr s = (exten d e d ) mo d e re g ister set pre = pre c har g e pre a = pre c har g e all read = read read ap = read with auto pre c har g e refre s h = refre s h s r = s elf refre s h write = write write ap = write with auto pre c har g e write ap rea d ap pre, pre a pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core1.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 5 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram functional description functional description the ddr2 sdram uses a double data rate architecture to achieve high-speed operation. the double data rate architecture is essentially a 4 n -prefetch architecture, with an inter- face designed to transfer two data words per clock cycle at the i/o balls. a single read or write access for the ddr2 sdram effectively consists of a single 4 n -bit-wide, one-clock- cycle data transfer at the internal dram core and four corresponding n -bit-wide, one- half-clock-cycle data transfers at the i/o balls. a bidirectional data strobe (dqs, dqs#) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr2 sdram during reads and by the memory controller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. the x16 offering has two data strobes, one for the lower byte (ldqs, ld qs#) and one for the upper byte (udqs, udqs#). the ddr2 sdram operates from a differentia l clock (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. commands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dq s, and output data is referenced to both edges of dqs as well as to both edges of ck. read and write accesses to the ddr2 sdram are burst-oriented; accesses start at a selected location and continue for a prog rammed number of locations in a programmed sequence. accesses begin with the registration of an activate command, which is then followed by a read or write command. the address bits registered coincident with the activate command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access. the ddr2 sdram provides for programmable read or write burst lengths of four or eight locations. ddr2 sdram supports interrup ting a burst read of eight with another read or a burst write of eight with anot her write. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. as with standard ddr sdrams, the pipelined, multibank architecture of ddr2 sdrams allows for concurrent operation, thereby pr oviding high, effective bandwidth by hiding row precharge and activation time. a self refresh mode is provided, along with a power-saving, power-down mode. all inputs are compatible with the jedec st andard for sstl_18. all full drive-strength outputs are sstl_ 18-compatible. industrial temperature the industrial temperature (it) option, if offered, has two simultaneous requirements: ambient temperature surrounding the device ca nnot be less than ?40c or greater than +85c, and the case temperature cannot be less than ?40c or greater than +95c. jedec specifications require the refresh rate to double when t c exceeds +85c; this also requires use of the high-temperature self refresh option. additionally, odt resistance and the input/output impedance must be derated when t c is < 0c or > +85c. pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core1.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 6 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram functional description automotive temperature the automotive temperature (at) option, if offered, has two simultaneous require- ments: ambient temperature surrounding the device cannot be less than ?40c or greater than +105c, and the case temperature cannot be less than ?40c or greater than +105c. jedec specifications require the refresh rate to double when t c exceeds +85c; this also requires use of the high-temperature self refresh option. additionally, odt resistance and the input/output impedance must be derated when t c is < 0c or > +85c. general notes ? the functionality and the timi ng specifications discussed in this data sheet are for the dll-enabled mode of operation. ? throughout the data sheet, the various figures and text refer to dqs as ?dq.? the dq term is to be interpreted as any and all dq collectively, unless specifically stated otherwise. additionally, the x16 is divided into 2 bytes: the lower byte and the upper byte. for the lower byte (dq0?dq7), dm refers to ldm and dqs refers to ldqs. for the upper byte (dq8?dq15), dm refers to udm and dqs refers to udqs. ? complete functionality is described th roughout the document, and any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. ? any specific requirement takes precedence over a general statement. pdf: 09005aef821ae8bf/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr2_x4x8x16_d2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 7 ?2004 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram functional block diagrams functional block diagrams the ddr2 sdram is a high-speed cmos, dyna mic random access memory. it is inter- nally configured as a multi-bank dram. figure 3: 256 meg x 4 functional block diagram bank 5 bank 6 bank 7 bank 4 bank 7 bank 4 bank 5 bank 6 row- addre ss mux c ontrol lo g i c c olumn- addre ss c ounter/ lat c h mode re g i s ter s 11 a0-a14, ba0-ba2 15 addre ss re g i s ter 18 512 (x1 6 ) 8,192 c olumn de c oder bank 0 memory array (32,7 6 8 x 512 x 1 6 ) bank 0 row- addre ss lat c h & de c oder 32,7 6 8 s en s e amplifier s bank c ontrol lo g i c 18 bank 1 bank 2 bank 3 15 9 3 2 refre s h c ounter 4 4 4 2 r c vr s 1 6 1 6 1 6 c k out data dq s , dq s # c k, c k# c k, c k# c ol0, c ol1 c ol0, c ol1 c k in drvr s dll mux dq s g enerator 4 4 4 4 4 2 read lat c h write fifo & driver s data 4 4 4 4 1 6 1 1 1 1 ma s k 1 1 1 1 1 4 4 4 2 bank 1 bank 2 bank 3 input re g i s ter s dm dq0?dq3 ra s # c a s # c k cs # we# c k# c ommand de c ode c ke odt i/o g atin g dm ma s k lo g i c dq s , dq s # v dd q r1 r1 r2 r2 sw1 sw2 vssq sw1 sw2 odt c ontrol sw3 r3 r3 sw3 r1 r1 r2 r2 sw1 sw2 r3 r3 sw3 r1 r1 r2 r2 sw1 sw2 r3 r3 sw3 pdf: 09005aef821ae8bf/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr2_x4x8x16_d2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 8 ?2004 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram functional block diagrams figure 4: 128 meg x 8 functional block diagram figure 5: 64 meg x 16 functional block diagram bank 5 bank 6 bank 7 bank 4 bank 7 bank 4 bank 5 bank 6 row- addre ss mux c ontrol lo g i c c olumn- addre ss c ounter/ lat c h mode re g i s ter s 10 a0-a14, ba0-ba2 15 addre ss re g i s ter 18 25 6 (x32) 8,192 c olumn de c oder bank 0 memory array (32,7 6 8 x 25 6 x 32) bank 0 row- addre ss lat c h & de c oder 32,7 6 8 s en s e amplifier s bank c ontrol lo g i c 18 bank 1 bank 2 bank 3 15 8 3 2 refre s h c ounter 8 8 8 2 32 32 32 c k out data udq s , udq s # ldq s , ldq s # c k, c k# c k, c k# c ol0, c ol1 c ol0, c ol1 c k in drvr s dll mux dq s g enerator 8 8 8 8 8 2 read lat c h write fifo & driver s data 8 8 8 8 32 2 2 2 2 ma s k 2 2 2 2 2 4 8 8 2 bank 1 bank 2 bank 3 input re g i s ter s dm dq0?dq7 ra s # c a s # c k cs # we# c k# c ommand de c ode c ke odt i/o g atin g dm ma s k lo g i c dq s , dq s # rdq s # rdq s v dd q r1 r1 r2 r2 sw1 sw2 vssq sw1 sw2 odt c ontrol sw3 r3 r3 sw3 r1 r1 r2 r2 sw1 sw2 r3 r3 sw3 r1 r1 r2 r2 sw1 sw2 r3 r3 sw3 r c vr s bank 5 bank 6 bank 7 bank 4 bank 7 bank 4 bank 5 bank 6 14 row- addre ss mux c ontrol lo g i c c olumn- addre ss c ounter/ lat c h mode re g i s ter s 10 a0?a13, ba0?ba2 14 addre ss re g i s ter 25 6 (x 6 4) 1 6 ,384 c olumn de c oder bank 0 memory array (1 6 ,324 x 25 6 x 6 4) bank 0 row- addre ss lat c h & de c oder 1 6 ,324 s en s e amplifier s bank c ontrol lo g i c 18 bank 1 bank 2 bank 3 13 8 3 2 refre s h c ounter 1 6 1 6 1 6 4 r c vr s 6 4 6 4 6 4 c k out data udq s , udq s # ldq s , ldq s # c k, c k# c k, c k# c ol0, c ol1 c ol0, c ol1 c k in drvr s dll mux dq s g enerator 1 6 1 6 1 6 1 6 1 6 udq s , udq s # ldq s , ldq s # 4 read lat c h write fifo & driver s data 1 6 1 6 1 6 1 6 6 4 2 2 2 2 ma s k 2 2 2 2 2 8 1 6 1 6 2 bank 1 bank 2 bank 3 input re g i s ter s udm, ldm dq0?dq15 v dd q r1 r1 r2 r2 sw1 sw2 vssq sw1 sw2 odt c ontrol ra s # c a s # c k cs # we# c k# c ommand de c ode c ke odt i/o g atin g dm ma s k lo g i c 18 sw3 r3 r3 sw3 r1 r1 r2 r2 sw1 sw2 r3 r3 sw3 r1 r1 r2 r2 sw1 sw2 r3 r3 sw3 pdf: 09005aef821ae8bf/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr2_x4x8x16_d2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 9 ?2004 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram ball assignments and descriptions ball assignments and descriptions figure 6: 60-ball fbga ? x4, x8 ball assignments (top view) 4 6 5 a b c d e f g h j k l 9 v dd q nf,dq7 v dd q nf,dq5 v dd odt v dd v ss 1 v dd nf,dq 6 v dd q nf,dq4 v dd l ba2 v ss v dd 2 n c , rdq s #/nu v ss q dq1 v ss q v ref c ke ba0 a10 a3 a7 a12 7 v ss q dq s v dd q dq2 v ss dl ra s # c a s # a2 a 6 a11 rfu 8 dq s #/nu v ss q dq0 v ss q c k c k# cs # a0 a4 a8 a13 3 v ss dm, dm/rdq s v dd q dq3 v ss we# ba1 a1 a5 a9 rfu pdf: 09005aef821ae8bf/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr2_x4x8x16_d2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 10 ?2004 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram ball assignments and descriptions figure 7: 84-ball fbga ? x16 ball assignments (top view) v dd q dq15 v dd q dq13 v dd q dq7 v dd q dq5 v dd odt v dd v ss udq s #/nu v ss q dq8 v ss q ldq s #/nu v ss q dq0 v ss q c k c k# cs # a0 a4 a8 rfu v ss q udq s v dd q dq10 v ss q ldq s v dd q dq2 v ss dl ra s # c a s # a2 a 6 a11 rfu v ss udm v dd q dq11 v ss ldm v dd q dq3 v ss we# ba1 a1 a5 a9 rfu n c v ss q dq9 v ss q n c v ss q dq1 v ss q v ref c ke ba0 a10 a3 a7 a12 v dd dq14 v dd q dq12 v dd dq 6 v dd q dq4 v dd l ba2 v ss v dd a b c d e f g h j k l m n p r 1234 6 789 5 pdf: 09005aef821ae8bf/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr2_x4x8x16_d2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 11 ?2004 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram ball assignments and descriptions figure 8: 92-ball fbga ? x4, x8 ball assignments (top view) 234 6 789 5 1 n c n c n c n c n c nf, rdq s #/nu v ss q dq1 v ss q v ref c ke ba0 a10 a3 a7 a12 n c n c v dd n c n c n c v dd nf,dq 6 v dd q nf,dq4 v dd l ba2 v ss v dd n c v ss n c n c n c v ss dm/rdq s v dd q dq3 v ss we# ba1 a1 a5 a9 rfu v ss q n c n c n c v ss q dq s v dd q dq2 v ss dl ra s # c a s # a2 a 6 a11 rfu n c n c n c n c n c dq s #/nu v ss q dq0 v ss q c k c k# cs # a0 a4 a8 a13 n c n c v dd q n c n c n c v dd q nf,dq7 v dd q nf,dq5 v dd odt v dd v ss n c a b c d e f g h j k l m n p r t u v w y aa pdf: 09005aef821ae8bf/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr2_x4x8x16_d2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 12 ?2004 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram ball assignments and descriptions figure 9: 92-ball fbga ? x16 ball assignments (top view) 234 6 789 5 1 n c n c v ss q dq9 v ss q n c v ss q dq1 v ss q v ref c ke ba0 a10 a3 a7 a12 n c n c v dd dq14 v dd q dq12 v dd dq 6 v dd q dq4 v dd l ba2 v ss v dd n c v ss udm v dd q dq11 v ss ldm v dd q dq3 v ss we# ba1 a1 a5 a9 rfu v ss q udq s v dd q dq10 v ss q ldq s v dd q dq2 v ss dl ra s # c a s # a2 a 6 a11 rfu n c udq s #/nu v ss q dq8 v ss q ldq s #/nu v ss q dq0 v ss q c k c k# cs # a0 a4 a8 rfu n c n c v dd q dq15 v dd q dq13 v dd q dq7 v dd q dq5 v dd odt v dd v ss n c a b c d e f g h j k l m n p r t u v w y aa pdf: 09005aef821ae8bf/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr2_x4x8x16_d2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 13 ?2004 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram ball assignments and descriptions table 3: fbga 60-ball ? x4, x8 and 84-ball ? x16 descriptions x16 ball number x4, x8 ball number symbol type description m8, m3, m7, n2, n8, n3, n7, p2, p8, p3, m2, p7, r2 ? a0?a2, a3?a5, a6?a8, a9, a10, a11, a12 input address inputs: provide the row address for activate commands, and the column addr ess and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge command determin es whether the precharge applies to one bank (a10 low, bank selected by ba0?ba2) or all banks (a10 high). the address in puts also prov ide the op-code during a load mode command. ? h8, h3, h7, j 2, j 8, j 3, j 7, k2, k8, k3, h2, k7, l2, l8 a0?a2, a3?a5, a6?a8, a9, a10, a11, a12, a13 input address inputs: provide the row address for activate commands, and the column addr ess and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge command determin es whether the precharge applies to one bank (a10 low, bank selected by ba0?ba2) or all banks (a10 high). the address in puts also prov ide the op-code during a load mode command. l2, l3, l1 g2, g3, g1 ba0?ba2 input bank address inputs: ba0?ba2 define to which bank an activate, read, write, or precharge command is being applied. ba0?ba2 define which mode register including mr, emr, emr(2), and emr(3) is loaded during the load mode command. j 8, k8 e8, f8 ck, ck# input clock: ck and ck# are differential clock inputs. all address and control input signals ar e sampled on the crossi ng of the positive edge of ck and negative edge of ck#. output data (dq and dqs/dqs#) is referenced to the crossings of ck and ck#. k2 f2 cke input clock enable: cke (registered high) activates and cke (registered low) deactivates cl ocking circuitry on the ddr2 sdram. the specific circuitry that is enabled/disabled is dependent on the ddr2 sdram configuration and operating mode. cke low provides precharge power-down and self refresh operations (all banks idle), or active power-down (row active in any bank). cke is synchronous for power-down entry, power-down exit, output disable, and for self refresh entry. cke is asynchronous for self refresh exit. input buffers (excluding ck, ck#, cke, and odt) are disabled during power-down. input buffers (excluding cke) are disabl ed during self refresh. cke is an sstl_18 input but will detect a lvcmos low level after v dd is applied during first power-up. after v ref has become stable during the power-on and initialization sequence, it must be maintained for proper operation of the cke receiver. for proper self refresh operation, v ref must be maintained. l8 g8 cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs# is registered hi gh. cs# provides for external bank selection on systems with multiple ranks. cs# is considered part of the command code. pdf: 09005aef821ae8bf/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr2_x4x8x16_d2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 14 ?2004 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram ball assignments and descriptions f3, b3 b3 ldm, udm dm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access . dm is sampled on both edges of dqs. although dm balls are input-only, the dm loading is designed to match that of dq and dqs balls. ldm is dm for lower byte dq0?dq7 and udm is dm for upper byte dq8?dq15. k9 f9 odt input on-die termination: odt (registered high) enables termination resistance internal to the ddr2 sdram. when enabled, odt is only applied to each of the following balls: dq0?dq15, ldm, udm, ldqs, ld qs#, udqs, and udqs# for the x16; dq0?dq7, dqs, dqs#, rdqs, rdqs#, and dm for the x8; dq0?dq3, dqs, dqs#, and dm for the x4. the odt input will be ignored if disabled via the load mode command. k7, l7, k3 f7, g7, f3 ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered. g8, g2, h7, h3, h1, h9, f1, f9, c8, c2, d7, d3, d1, d9, b1, b9 ? dq0?dq2, dq3?dq5, dq6?dq8, dq9?dq11, dq12?dq14, dq15 i/o data input/output: bidirectional data bus for 64 meg x 16. ? c8, c2, d7, d3, d1, d9, b1, b9 dq0?dq2, dq3?dq5, dq6?dq7 i/o data input/output: bidirectional data bus for 128 meg x 8. ? c8, c2, d7, d3 dq0?dq2, dq3 i/o data input/output: bidirectional data bus for 256 meg x 4. ? b7, a8 dqs, dqs# i/o data strobe: output with read data, input with wr ite data for source synchronous operation. edge-aligned with read data, center-aligned with write data. dqs# is only used when differential data strobe mode is enabled via the load mode command. f7, e8 ? ldqs, ldqs# i/o data strobe for lower byte: output with read data, input with write data for source sync hronous operation. edge-aligned with read data, center-aligned with write data. ldqs# is only used when differential data strobe mode is enabled via the load mode command. b7, a8 ? udqs, udqs# i/o data strobe for upper byte: output with read data, input with write data for source sync hronous operation. edge-aligned with read data, center-aligned with write data. udqs# is only used when differential data strobe mode is enabled via the load mode command. ? b3, a2 rdqs, rdqs# output redundant data strobe: for 128 meg x 8 only. rdqs is enabled/disabled via the load mode command to the extended mode register (emr). when rdqs is enabled, rdqs is output with read data only an d is ignored during write data. when rdqs is disabled, ball b3 becomes data mask (see dm ball). rdqs# is only used when rdqs is enabled and differential data strobe mode is enabled. a1, e1, m9, r1, j 9 a1, e9, l1, h9 v dd supply power supply: 1.8v 0.1v. table 3: fbga 60-ball ? x4, x8 and 84-ball ? x16 descriptions (continued) x16 ball number x4, x8 ball number symbol type description pdf: 09005aef821ae8bf/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr2_x4x8x16_d2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 15 ?2004 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram ball assignments and descriptions a9, c1, c3, c7, c9, g3, e9, g1, g7, g9, a9, c1, c3, c7, c9 v dd q supply dq power supply: 1.8v 0.1v. isolated on the device for improved noise immunity. j 1e1v dd l supply dll power supply: 1.8v 0.1v. j 2e2v ref supply sstl_18 reference voltage (v dd q/2). a3, e3, j 3, n1, p9 a3, e3, j 1, k9 v ss supply ground. j 7e7v ss dl supply dll ground : isolated on the device from v ss and v ss q. a7, b2, b8, d2, d8, e7, f2, f8, h2, h8 a7, b2, b8, d2, d8 v ss q supply dq ground: isolated on the device for improved noise immunity. a2, e2 ? nc ? no connect: these balls should be left unconnected. ? b1, b9, d1, d9 nf ? no function: x8: these balls are used as dq4?dq7; x4: they are no function. a8, e8 ? nu ? not used: for x16 only. if emr(e10) = 0, a8 and e8 are udqs# and ldqs#. if emr(e10) = 1, then a8 and e8 are not used. ? a2, a8 nu ? not used: for x8 only. if emr(e10) = 0, a2 and e8 are rdqs# and dqs#. if emr(e10) = 1, th en a2 and e8 are not used. r8, r3, r7 l3, l7 rfu ? reserved for future use: row address bits a13 (x16 only), a14, and a15. table 3: fbga 60-ball ? x4, x8 and 84-ball ? x16 descriptions (continued) x16 ball number x4, x8 ball number symbol type description pdf: 09005aef821ae8bf/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr2_x4x8x16_d2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 16 ?2004 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram ball assignments and descriptions table 4: 92-ball ? x4, x8, x16 descriptions x16 ball number x4, x8 ball number symbol type description r8, r3, r7, t2, t8, t3, t7, u2, u8, u3, r2, u7, v2 ? a0?a2, a3?a6, a7?a9, a10?a12 input address inputs: provide the row address for activate commands, and the column addre ss and auto precharge bit (a10) for read/write commands , to select one location out of the memory array in the respective bank. a10 sampled during a precharge command determin es whether the precharge applies to one bank (a10 low, bank selected by ba0?ba2) or all banks (a10 high). the address inputs also provide the op-code during a load mode command. ? r8, r3, r7, t2, t8, t3, t7, u2, u8, u3, r2, u7, v2, v8 a0?a3, a4?a7, a8?a10, a11?a13 input address inputs: provide the row address for activate commands, and the column addre ss and auto precharge bit (a10) for read/write commands , to select one location out of the memory array in the respective bank. a10 sampled during a precharge command determin es whether the precharge applies to one bank (a10 low, bank selected by ba0?ba2) or all banks (a10 high). the address inputs also provide the op-code during a load mode command. p2, p3, p1 p2, p3, p1 ba0?ba2 input bank address inputs: ba0?ba2 define to which bank an activate, read, write, or precharge command is being applied. ba0?ba2 define which mo de register including mr, emr, emr(2), and emr(3) is loaded during the load mode command. m8, n8 m8, n8 ck, ck# input clock: ck and ck# are differential clock inputs. all address and control input signals ar e sampled on the crossi ng of the positive edge of ck and negative edge of ck#. output data (dq and dqs/ dqs#) is referenced to th e crossings of ck and ck#. n2 n2 cke input clock enable: cke (registered high) activates and cke (registered low) deactivates clocking circ uitry on the ddr2 sdram. the specific circuitry that is enable d/disabled is dependent on the ddr2 sdram configuration and operating mode. cke low provides precharge power-down an d self refresh operation (all banks idle), or active power-down (row active in any bank). cke is synchronous for power-down entry, power-down exit, output disable, and self refresh entry. ck e is asynchronous for self refresh exit. input buffers (excluding ck, ck#, cke, and odt) are disabled during power-down. input buffers (excluding cke) are disabled during self refresh. cke is an sstl_18 input but will detect a lvcmos low level after v dd is applied during first power-up. after v ref has become stable during the power-on and initialization sequence, it mu st be maintained for proper operation of the cke receiver. fo r proper self refr esh operation, v ref must be maintained. p8 p8 cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs# is registered high. cs# provides for external bank selection on systems with multiple ranks. cs # is considered part of the command code. j 3, e3 j 3 ldm, udm, (dm) input input data mask: dm is an input mask signal for write data. input data is masked when dm is conc urrently sampled high during a write access. dm is sampled on both edges of dqs. although dm balls are input-only, th e dm loading is design ed to match that of dq and dqs balls. ldm is dm for lower byte dq0?dq7 and udm is dm for upper byte dq8?dq15. pdf: 09005aef821ae8bf/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr2_x4x8x16_d2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 17 ?2004 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram ball assignments and descriptions n9 n9 odt input on-die termination: odt (registered high) enables termination resistance internal to the ddr2 sdram. when enabled, odt is only applied to each of the fo llowing balls: dq0?dq15, ldm, udm, ldqs, ldqs#, udqs, and udq s# for the x1 6; dq0?dq7, dqs, dqs#, rdqs, rdqs#, and dm for the x8; dq0?dq3, dqs, dqs#, and dm for the x4. the odt input will be ignored if disabled via the load mode command. n7, p7, n3 n7, p7, n3 ras#, cas#, we# input command inputs: ras#, cas#, and we# (alo ng with cs#) define the command being entered. k8, k2, l7, l3, l1, l9, j 1, j 9, f8, f2, g7, g3, g1, g9, e1, e9 ? dq0?dq3, dq4?dq7, dq8?dq10, dq11?dq13, dq14?dq15 i/o data input/output: bidirectional data bus for 64 meg x 16. ? k8, k2, l7, l3, l1, l9, j 1, j 9 dq0?dq3, dq4?dq7 i/o data input/output: bidirectional data bus for 128 meg x 8. ? k8, k2, l7, l3 dq0?dq3 i/o data input/output: bidirectional data bus for 256 meg x 4. ? j 7, h8 dqs, dqs# i/o data strobe: output with read data, input with write data for source synchronous operation. edge-aligned with read data, center-aligned with write data. dqs# is only used when differential data strobe mode is enabled via the load mode command. j 7, h8 ?ldqs, ldqs# i/o data strobe for lower byte: output with read data, input with write data for source synchronou s operation. edge -aligned with read data, center-aligned with wr ite data. ldqs# is only used when differential data strobe mode is enabled via the load mode command. e7, d8 ? udqs, udqs# i/o data strobe fo r upper byte: output with read data, input with write data for source synchronou s operation. edge -aligned with read data, center-aligned with wr ite data. udqs# is only used when differential data strobe mode is enabled via the load mode command. ? j 3, h2 rdqs, rdqs# output redundant data strobe: for x8 only. rdqs is enabled/disabled via the load mode command to the extended mode register (emr). when rdqs is enabled, rdqs is output with read data only and is ignored during write data. when rdqs is disabled, ball j 3 becomes data mask (see dm ball). rdqs# is only used when rdqs is enabled and differential data s trobe mode is enabled. d1, h1, m9, r9, v1 d1, h1, m9, r9, v1 v dd supply power supply: 1.8v 0.1v. d9, f1, f3, f7, f9, h9, k1, k3, k7, k9 d9, h9, k1, k3, k7, k9 v dd q supply dq power supply: 1.8v 0.1v. isolated on the device for improved noise immunity. m1 m1 v dd l supply dll power supply: 1.8v 0.1v. m2 m2 v ref supply sstl_18 reference voltage (v dd q/2). d3, h3, m3, t1, u9 d3, h3, m3, t1, u9 v ss supply ground. m7 m7 v ss dl supply dll ground: isolated on the device from v ss and v ss q. table 4: 92-ball ? x4, x8, x16 descriptions (continued) x16 ball number x4, x8 ball number symbol type description pdf: 09005aef821ae8bf/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr2_x4x8x16_d2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 18 ?2004 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram ball assignments and descriptions d7, e2, e8, g2, g8, h7, j 2, j 8, l2, l8 d7, h7, j 2, j 8, l2, l8 v ss q supply dq ground: isolated on the device for improved noise immunity. a1, a2, a8, a9, d2, h2, aa1, aa2, aa8, aa9 a1, a2, a8, a9, d2, d8, e1?e3, e7?e9, f1?f3, f7?f9, g1?g3, g7?g9, aa1, aa2, aa8, aa9 nc ? no connect: these balls should be left unconnected. ? j 1, j 9, l1, l9, h2 nf ? no function: x8: these balls are used as dq4?dq7; x4, they are no function. d8, h8 ? nu ? not used: for x16 only. if emr(e10) = 0, d8 and h8 are udqs# and ldqs#. if emr(e10) = 1, then d8 and h8 are not used. ? h2, h8 nu ? not used: for x8 only. if emr(e10) = 0, h2 and h8 are rdqs# and dqs#. if emr(e10) = 1, then h2 and h8 are not used. v3, v7, v8 v3, v7 rfu ? reserved for future use: row address bits a13 (v8), a14 (v3), and a15 (v7) are reserved. table 4: 92-ball ? x4, x8, x16 descriptions (continued) x16 ball number x4, x8 ball number symbol type description pdf: 09005aef821ae8bf/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr2_x4x8x16_d2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 19 ?2004 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram package dimensions package dimensions figure 10: 60-ball fbga package ? x4, x8 notes: 1. all dimensions are in millimeters. ball a1 id 1.20 max 0.25 min 0.8 typ 8 0.15 987 321 a b c d e f g h j k l 0.8 0.1 seating plane a 8 6.4 0.12 a 60x ?0.45 dimensions apply to solder balls post reflow. 11.5 0.15 ball a1 id 0.8 typ pdf: 09005aef821ae8bf/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr2_x4x8x16_d2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 20 ?2004 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram package dimensions figure 11: 84-ball fbga package ? x16 notes: 1. all dimensions are in millimeters. ball a1 id 1.2 max 0.8 typ 8 0.15 0.8 0.1 0.25 min seating plane a 11.2 ctr 6.4 ctr 0.12 a 84x ?0.45 12.5 0.15 ball a1 id 987 321 a b c d e f g h j k l m n p r dimensions apply to solder balls post reflow on ?0.33 nsmd ball pads. 0.8 typ exposed gold-plated pad 1.0mm (max) x 0.7mm (nom) pdf: 09005aef821ae8bf/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr2_x4x8x16_d2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 21 ?2004 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram package dimensions figure 12: 92-ball fbga package ? x4, x8, x16 notes: 1. all dimensions are in millimeters. ball a1 id solder ball diameter refers to post reflow condition. 0.80 typ 16 1.20 max ball a1 id 0.80 typ 11 0.15 6.40 92x ? 0.45 c l c l 2.40 19 0.15 0.8 0.1 seating plane a 0.12 a 0.25 min pdf: 09005aef821ae8bf/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr2_x4x8x16_d2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 22 ?2004 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram fbga package capacitance fbga package capacitance notes: 1. this parameter is sampled. v dd = +1.8v 0.1v, v dd q = +1.8v 0.1v, v ref = v ss , f = 100 mhz, t c = 25c, v out ( dc ) = v dd q/2, v out (peak-to-peak) = 0.1v. dm input is grouped with i/o balls, reflecting the fact that they are matched in loading. 2. the input capacitance per ball group will not di ffer by more than th is maximum amount for any given device. 3. c are not pass/fail parameters but rather targets. 4. reduce max limit by 0.25pf fo r -25, -25e, -187e speed devices. 5. reduce max limit by 0.5pf for -3, -3e, -25, -25e, -187e speed devices. 6. the i/o capacitance per dqs and dq byte/group will not differ by more than this maximum amount for any given device. table 5: input capacitance parameter symbol min max units notes input capacitance: ck, ck# c ck 1.0 2.0 pf 1 delta input capacitance: ck, ck# c dck ?0.25pf2, 3 input capacitance: address balls, bank address balls, cs#, ras#, cas#, we#, cke, odt c i 1.0 2.0 pf 1, 4 delta input capacitance: addr ess balls, bank address balls, cs#, ras#, cas#, we#, cke, odt c di ?0.25pf2, 3 input/output capacitance: dq, dqs, dm, nf c io 2.5 4.0 pf 1, 5 delta input/output capacitance: dq, dqs, dm, nf c dio ? 0.5 pf 3, 6 pdf: 09005aef821ae8bf/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr2_x4x8x16_d2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 23 ?2004 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram electrical specifications ? absolute ratings electrical specificatio ns ? absolute ratings stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condit ions for extended periods may affect reli- ability. notes: 1. v dd , v dd q, and v dd l must be within 300mv of each other at all times. 2. v ref 0.6 v dd q; however, v ref may be v dd q provided that v ref 300mv. 3. voltage on any i/o may not exceed voltage on v dd q. temperature and thermal impedance it is imperative that the ddr2 sdram devi ce?s temperature specifications, shown in table 7 on page 24, be maintained in order to ensure the junction temperature is in the proper operating range to meet data sheet specifications. an important step in main- taining the proper junction temperature is using the device?s thermal impedances correctly. the thermal impedances are listed in table 8 on page 24 for the applicable and available die revision and packages. incorrectly using thermal impedances can produce significant errors. read micron tech- nical note tn-00-08, ?thermal applications? prior to using the thermal impedances listed in table 8 on page 24. for designs that are expected to last several years and require the flexibility to use several dram di e shrinks, consider using final target theta values (rather than existing values) to account for increased thermal impedances from the die size reduction. the ddr2 sdram device?s safe junction temperature range can be maintained when the t c specification is not exceeded. in applic ations where the device?s ambient temper- ature is too high, use of forced air and/or he at sinks may be required in order to satisfy the case temperature specifications. table 6: absolute maximum dc ratings parameter symbol min max units notes v dd supply voltage relative to v ss v dd ?1.0 2.3 v 1 v dd q supply voltage relative to v ss q v dd q ?0.5 2.3 v 1, 2 v dd l supply voltage relative to v ss l v dd l?0.5 2.3 v 1 voltage on any ball relative to v ss v in , v out ?0.5 2.3 v 3 input leakage current; any input 0v v in v dd ; all other balls not under test = 0v i i ?5 5 a output leakage current; 0v v out v dd q; dq and odt disabled i oz ?5 5 a v ref leakage current; v ref = valid v ref level i vref ?2 2 a pdf: 09005aef821ae8bf/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr2_x4x8x16_d2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 24 ?2004 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram electrical specifications ? absolute ratings notes: 1. max storage case temperature; t stg is measured in the center of the package, as shown in figure 13. this case temperatur e limit is allowed to be exce eded briefly during package reflow, as noted in micron technical note tn-00-15, ?recommended soldering parameters.? 2. max operating case temperature; t c is measured in the center of the package, as shown in figure 13. 3. device functionality is not guarant eed if the device exceeds maximum t c during operation. 4. both temperature specific ations must be satisfied. 5. operating ambient temperat ure surrounding the package. figure 13: example temperature test point location notes: 1. thermal resistance data is based on a numb er of samples from multiple lots and should be viewed as a typical number. ta bl e 7 : te mp er a t ure l im it s parameter symbol min max units notes storage temperature t stg ?55 150 c 1 operating temperature: commercial t c 085c2, 3 operating temperature: industrial t c ?40 95 c 2, 3, 4 t a ?40 85 c 4, 5 table 8: thermal impedance die revision package substrate ja (c/w) airflow = 0m/s ja (c/w) airflow = 1m/s ja (c/w) airflow = 2m/s jb (c/w) jc (c/w) a 1 92-ball 2-layer 38.3 25.3 21.3 11.8 1.7 4-layer 24.7 18.1 16.0 10.8 e 1 60-ball 2-layer 56.7 42.1 36.8 22.7 2.5 4-layer 40.2 32.8 29.9 22.1 84-ball 2-layer 52.9 41.3 35.7 21.6 2.5 4-layer 38.4 32 28.9 21.5 g 1 60-ball 2-layer 66.5 49.6 43.1 30.3 5.9 4-layer 49.2 40.4 36.4 30 84-ball 2-layer 60.2 44.5 39.3 26.1 5.6 4-layer 44 35.7 32.8 26.1 test point 0.5 (w) 0.5 (l) len g th (l) wi d th (w) pdf: 09005aef821ae8bf/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr2_x4x8x16_d2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 25 ?2004 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram electrical specifications ? i dd parameters electrical specifications ? i dd parameters i dd specifications and conditions ta bl e 9 : ge ne r a l i dd parameters i dd parameters -187e -25e -25 -3e -3 -37e -5e units cl (i dd ) 7564543 t ck t rcd (i dd ) 13.125 12.5 15 12 15 15 15 ns t rc (i dd ) 58.125 57.5 60 57 60 60 55 ns t rrd (i dd ) - x4/x8 (1kb) 7.5 7.5 7.5 7.5 7.5 7.5 7.5 ns t rrd (i dd ) - x16 (2kb) 10 10 10 10 10 10 10 ns t ck (i dd ) 1.875 2.5 2.5 3 3 3.75 5 ns t ras min (i dd ) 45 45 45 45 45 45 40 ns t ras max (i dd ) 70,000 70,000 70,000 70,000 70,000 70,000 70,000 ns t rp (i dd ) 13.125 12.5 15 12 15 15 15 ns t rfc (i dd - 256mb) 75 75 75 75 75 75 75 ns t rfc (i dd - 512mb) 105 105 105 105 105 105 105 ns t rfc (i dd - 1gb) 127.5 127.5 127.5 127.5 127.5 127.5 127.5 ns t rfc (i dd - 2gb) 195 195 195 195 195 195 195 ns t faw (i dd ) - x4/x8 (1kb) defined by pattern in table 10 on page 26 ns t faw (i dd ) - x16 (2kb) defined by pattern in table 10 on page 26 ns pdf: 09005aef821ae8bf/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr2_x4x8x16_d2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 26 ?2004 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram electrical specifications ? i dd parameters i dd 7 conditions the detailed timings are shown below for i dd 7. where general i dd parameters in table 9 on page 25 conflict with pattern requirements of table 10, then table 10 requirements take precedence. notes: 1. a = active; ra = read auto precharge; d = deselect. 2. all banks are being interleaved at t rc (i dd ) without violating t rrd (i dd ) using a bl = 4. 3. control and address bus inputs are stable during deselects. table 10: i dd 7 timing patterns (8-bank interleave read operation) speed grade i dd 7 timing patterns timing patterns for 8-bank x4/x8 devices -5e a0 ra0 a1 ra1 a2 ra2 a3 ra3 a4 ra4 a5 ra5 a6 ra6 a7 ra7 -37e a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d a4 ra4 a5 ra5 a6 ra6 a7 ra7 d d -3 a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d a4 ra4 d a5 ra5 d a6 ra6 d a7 ra7 d d -3e a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d a4 ra4 d a5 ra5 d a6 ra6 d a7 ra7 d d -25 a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d a4 ra4 d a5 ra5 d a6 ra6 d a7 ra7 d d d -25e a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d a4 ra4 d a5 ra5 d a6 ra6 d a7 ra7 d d d -187e a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d d d d timing patterns for 8-bank x16 devices -5e a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d a4 ra4 a5 ra5 a6 ra6 a7 ra7 d d -37e a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d a4 ra4 d a5 ra5 d a6 ra6 d a7 ra7 d d d -3 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d d -3e a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d d -25 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d d d -25e a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d d d -187e a0 ra0 d d d d a1 ra1 d d d d a2 ra2 d d d d a3 ra3 d d d d a4 ra4 d d d d a5 ra5 d d d d a6 ra6 d d d d a7 ra7 d d d d pdf: 09005aef821ae8bf/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr2_x4x8x16_d2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 27 ?2004 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram electrical specifications ? i dd parameters table 11: ddr2 i dd specifications and conditions (die revision a) notes: 1?7 (page 30) appl y to the entire table parameter/condition symbol configuration -25e/ -25 -3e/-3 -37e -5e units operating one bank active-precharge current: t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd 0 x4, x8 100 90 80 70 ma x16 150 135 110 110 operating one bank active-read-precharge current: i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address bus inputs are switching; data pattern is same as i dd 4w i dd 1 x4, x8 110 100 95 80 ma x16 175 160 130 125 precharge power-down current: all banks idle; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stab le; data bus inputs are floating i dd 2px4, x8, x167777ma precharge quiet standby current: all banks idle; t ck = t ck (i dd ); cke is high, cs# is high; other control and address bus inpu ts are stable; data bus inputs are floating i dd 2q x4, x8 65 55 41 35 ma x16 75654540 precharge standby current: all banks idle; t ck = t ck (i dd ); cke is high, cs# is high; other control and address bus inpu ts are switching; data bus inputs are switching i dd 2n x4, x8 70 60 45 40 ma x16 80705040 active power-down current: all banks open; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stab le; data bus inputs are floating i dd 3p fast pdn exit mr12 = 0 50 45 40 35 ma slow pdn exit mr12 = 1 18 18 18 18 active standby current: all banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching i dd 3n x4, x8 75 70 60 45 ma x16 85756055 operating burst write current: all banks open, continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd 4w x4, x8 185 160 140 110 ma x16 315 210 180 160 operating burst read current: all banks open, continuous burst reads, i out = 0ma; bl = 4, cl=cl(i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between vali d commands; address bus inputs are switching; data bus inputs are switching i dd 4r x4, x8 190 160 145 110 ma x16 320 220 180 160 burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval; cke is high, cs# is high between va lid commands; other control and address bus inpu ts are switching; data bus inputs are switching i dd 5 x4, x8 280 270 250 220 ma x16 280 270 250 240 pdf: 09005aef821ae8bf/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr2_x4x8x16_d2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 28 ?2004 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram electrical specifications ? i dd parameters self refresh current: ck and ck# at 0v; cke 0.2v; other control an d address bus inputs are floating; data bus inputs are floating i dd 6x4, x8, x167777ma i dd 6l 5555 operating bank interleave read current: all bank interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) - 1 t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address bus inputs are stable during deselects; data bu s inputs are switching; see ?idd7 conditions? on page 26 for details i dd 7 x4, x8 335 300 290 260 ma x16 440 350 340 330 table 11: ddr2 i dd specifications and conditions (die revision a) (continued) notes: 1?7 (page 30) appl y to the entire table parameter/condition symbol configuration -25e/ -25 -3e/-3 -37e -5e units pdf: 09005aef821ae8bf/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr2_x4x8x16_d2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 29 ?2004 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram electrical specifications ? i dd parameters table 12: ddr2 i dd specifications and conditions (die revision e and g) notes: 1?7 (page 30) appl y to the entire table parameter/condition symbol configuration -187e -25e/ -25 -3e/ -3 -37e -5e units operating one bank active-precharge current: t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, cs# is high between valid commands; address bus inputs are switch ing; data bus inputs are switching i dd 0 x4, x8 115 90 85 70 70 ma x16 180 150 135 110 110 operating one bank active-read-precharge current: i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address bus inputs are switchin g; data pattern is same as i dd 4w i dd 1 x4, x8 130 110 100 95 90 ma x16 210 175 130 120 115 precharge power-down current: all banks idle; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating i dd 2p x4, x8, x16 7 7 7 7 7 ma precharge quiet standby current: all banks idle; t ck = t ck (i dd ); cke is high, cs# is high; other control and address bus inputs are sta ble; data bus inputs are floating i dd 2q x4, x8 60 50 40 40 35 ma x16 90 75 65 45 40 precharge standby current: all banks idle; t ck = t ck (i dd ); cke is high, cs# is high; other control and address bus inputs are sw itching; data bus inputs are switching i dd 2n x4, x8 60 50 40 40 35 ma x16 95 80 70 50 40 active power-down current: all banks open; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating i dd 3p fast exit mr12 = 0 50 40 30 30 30 ma slow exit mr12 = 1 10 10 10 10 10 active standby current: all banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching i dd 3n x4, x8 70 60 55 45 40 ma x16 95 85 75 60 55 operating burst write current: all banks open, continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are switch ing; data bus inputs are switching i dd 4w x4 190 145 120 110 90 ma x8 210 160 135 125 105 x16 405 315 200 180 160 operating burst read current: all banks open, continuous burst reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bu s inputs are switching i dd 4r x4 190 145 120 110 105 ma x8 210 160 135 125 90 x16 420 320 220 180 160 burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval; cke is high, cs# is high between valid comma nds; other control and address bus inputs are switching; data bus inputs are switching i dd 5 x4, x8 265 235 215 210 205 ma x16 300 280 270 250 240 pdf: 09005aef821ae8bf/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr2_x4x8x16_d2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 30 ?2004 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram electrical specifications ? i dd parameters notes: 1. i dd specifications are tested after the device is properly initialized. 0c t c +85c. v dd = +1.8v 0.1v, v dd q = +1.8v 0.1v, v dd l = +1.8v 0.1v, v ref = v dd q/2. 2. input slew rate is specified by ac pa rametric test conditions (table 9 on page 25). 3. i dd parameters are specified with odt disabled. 4. data bus consists of dq, dm, dqs, dqs#, rdqs, rdqs#, ldqs, ldqs#, udqs, and udqs#. i dd values must be met with all comb inations of emr bits 10 and 11. 5. definitions for i dd conditions: 6. i dd 1, i dd 4r, and i dd 7 require a12 in emr to be enabled during testing. 7. the following i dd s must be derated (i dd limits increase) on it-option and at-option devices when operated outsid e of the range 0c t c 85c: self refresh current: ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating i dd 6 x4, x8, x16 7 7 7 7 7 ma i dd 6l 5 5 5 5 5 operating bank interleave read current: all bank interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) - 1 t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address bus inputs are stable during de selects; data bus inputs are switching; see ?idd7 conditions? on page 26 for details i dd 7 x4, x8 425 335 280 270 260 ma x16 520 440 350 330 300 low v in v il ( ac ) max high v in v ih ( ac ) min stable inputs stable at a high or low level floating inputs at v ref = v dd q/2 switching inputs changing between high and low every other clock cycle (once per two clocks) for address and control signals switching inputs changing between high and low every other data transfer (once per clock) for dq signals, not including masks or strobes when t c 0c i dd 2p and i dd 3p (slow) must be derated by 4 percent; i dd 4r and i dd 5w must be derated by 2 percent; and i dd 6 and i dd 7 must be derated by 7 percent when t c 85c i dd 0, i dd 1, i dd 2n, i dd 2q, i dd 3n, i dd 3p (fast), i dd 4r, i dd 4w, and i dd 5w must be derated by 2 percent; i dd 2p must be derated by 20 percent; i dd 3pslow must be derated by 30 percent; and i dd 6 must be derated by 80 percent (i dd 6 will increase by this amount if t c < 85c and the 2x refresh option is still enabled) table 12: ddr2 i dd specifications and conditions (d ie revision e and g) (continued) notes: 1?7 (page 30) appl y to the entire table parameter/condition symbol configuration -187e -25e/ -25 -3e/ -3 -37e -5e units pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 31 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram ac timing operating specifications ac timing operating specifications table 13: ac operating specifications and conditions for -187e, -25e, -3e, -3, -37e, and -5e speeds (sheet 1 of 7) not all speed grades listed may be su pported for this device; refer to th e title page for speeds supported; notes: 1?5 (page 38) apply to the entire table; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -187e -25e -25 -3e -3 -37e -5e units notes parameter symbol min max min max min max min max min max min max min max clock clock cycle time cl = 7 t ck (avg) 1.8758.0????????????ns6, 7, 8, 9 cl = 6 t ck (avg) 2.58.02.58.02.58.0???????? cl = 5 t ck (avg) 3.0 8.0 2.5 8.0 3.0 8.0 3.0 8.0 3.0 8.0 ? ? ? ? cl = 4 t ck (avg) ? ? 3.75 8.0 3.75 8.0 3.0 8.0 3.75 8.0 3.75 8.0 5.0 8.0 cl = 3 t ck (avg) ? ? ??????5.08.05.08.05.08.0 ck high-level width t ch (avg) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 t ck 10 ck low-level width t cl (avg) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 t ck half clock period t hp min = lesser of t ch and t cl max = n/a ps 11 absolute t ck t ck (abs) min = t ck (avg) min + t j it per (min) max = t ck (avg) max + t j it per (max) ps absolute ck high- level width t ch (abs) min = t ck (avg) min t ch (avg) min + t j it dty (min) max = t ck (avg) max t ch (avg) max + t j it dty (max) ps absolute ck low- level width t cl (abs) min = t ck (avg) min t cl (avg) min + t j it dty (min) max = t ck (avg) max t cl (avg) max + t j it dty (max) ps pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 32 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram ac timing operating specifications clock j itter period jitter t j it per ?90 90 ?100 100 ?100 100 ?125 125 ?125 125 ?125 125 ?125 125 ps 12 half period t j it dty ?75 75 ?100 100 ?100 100 ?125 125 ?125 125 ?125 125 ?150 150 ps 13 cycle to cycle t j it cc 180 200 200 250 250 250 250 ps 14 cumulative error, 2 cycles t err 2 per ?132 132 ?150 150 ?150 150 ?175 175 ?175 175 ?175 175 ?175 175 ps 15 cumulative error, 3 cycles t err 3 per ?157 157 ?175 175 ?175 175 ?225 225 ?225 225 ?225 225 ?225 225 ps 15 cumulative error, 4 cycles t err 4 per ?175 175 ?200 200 ?200 200 ?250 250 ?250 250 ?250 250 ?250 250 ps 15 cumulative error, 5 cycles t err 5 per ?188 188 ?200 200 ?200 200 ?250 250 ?250 250 ?250 250 ?250 250 ps 15, 16 cumulative error, 6?10 cycles t err 6? 10 per ?250 250 ?300 300 ?300 300 ?350 350 ?350 350 ?350 350 ?350 350 ps 15, 16 cumulative error, 11?50 cycles t err 11? 50 per ?425 425 ?450 450 ?450 450 ?450 450 ?450 450 ?450 450 ?450 450 ps 15 table 13: ac operating specifications and conditions for -187e, -25e, -3e, -3, -37e, and -5e speeds (sheet 2 of 7) not all speed grades listed may be su pported for this device; refer to th e title page for speeds supported; notes: 1?5 (page 38) apply to the entire table; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -187e -25e -25 -3e -3 -37e -5e units notes parameter symbol min max min max min max min max min max min max min max pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 33 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram ac timing operating specifications data strobe-out dqs output access time from ck/ck# t dqsck ?300 +300 ?350 +350 ?350 +350 ?400 +400 ?400 +400 ?450 +450 ?500 +500 ps 19 dqs read preamble t rpre min = 0.9 t ck max = 1.1 t ck t ck 17, 18, 19 dqs read postamble t rpst min = 0.4 t ck max = 0.6 t ck t ck 17, 18, 19, 20 ck/ck# to dqs low-z t lz 1 min = t ac (min) max = t ac (max) ps 19, 21, 22 data strobe-in dqs rising edge to ck rising edge t dqss min = ?0.25 t ck max = +0.25 t ck t ck 18 dqs input-high pulse width t dqsh min = 0.35 t ck max = n/a t ck 18 dqs input-low pulse width t dqsl min = 0.35 t ck max = n/a t ck 18 dqs falling to ck rising: setup time t dss min = 0.2 t ck max = n/a t ck 18 dqs falling from ck rising: hold time t dsh min = 0.2 t ck max = n/a t ck 18 write preamble setup time t wpres min = 0 max = n/a ps 23, 24 dqs write preamble t wpre min = 0.35 t ck max = n/a t ck 18 dqs write postamble t wpst min = 0.4 t ck max = 0.6 t ck t ck 18, 25 write command to first dqs transition ? min = wl - t dqss max = wl + t dqss t ck table 13: ac operating specifications and conditions for -187e, -25e, -3e, -3, -37e, and -5e speeds (sheet 3 of 7) not all speed grades listed may be su pported for this device; refer to th e title page for speeds supported; notes: 1?5 (page 38) apply to the entire table; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -187e -25e -25 -3e -3 -37e -5e units notes parameter symbol min max min max min max min max min max min max min max pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 34 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram ac timing operating specifications data-out dq output access time from ck/ck# t ac ?350 +350 ?400 +400 ?400 +400 ?450 +450 ?450 +450 ?500 +500 ?600 +600 ps 19 dqs?dq skew, dqs to last dq valid, per group, per access t dqsq ? 175 ? 200 ? 200 ? 240 ? 240 ? 300 ? 350 ps 26, 27 dq hold from next dqs strobe t qhs ? 250 ? 300 ? 300 ? 340 ? 340 ? 400 ? 450 ps 28 dq?dqs hold, dqs to first dq not valid t qh min = t hp - t qhs max = n/a ps 26, 27, 28 ck/ck# to dq, dqs high-z t hz min = n/a max = t ac (max) ps 19, 21, 29 ck/ck# to dq low-z t lz 2 min = 2 t ac (min) max = t ac (max) ps 19, 21, 22 data valid output window dvw min = t qh - t dqsq max = n/a ns 26, 27 data-in dq and dm input setup time to dqs t ds b 0 ? 50 ? 50 ? 100 ? 100 ? 100 ? 150 ? ps 26, 30, 31 dq and dm input hold time to dqs t dh b 75 ? 125 ? 125 ? 175 ? 175 ? 225 ? 275 ? ps 26, 30, 31 dq and dm input setup time to dqs t ds a 200 ? 250 ? 250 ? 300 ? 300 ? 350 ? 400 ? ps 26, 30, 31 dq and dm input hold time to dqs t dh a 200 ? 250 ? 250 ? 300 ? 300 ? 350 ? 400 ? ps 26, 30, 31 dq and dm input pulse width t dipw min = 0.35 t ck max = n/a t ck 18, 32 table 13: ac operating specifications and conditions for -187e, -25e, -3e, -3, -37e, and -5e speeds (sheet 4 of 7) not all speed grades listed may be su pported for this device; refer to th e title page for speeds supported; notes: 1?5 (page 38) apply to the entire table; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -187e -25e -25 -3e -3 -37e -5e units notes parameter symbol min max min max min max min max min max min max min max pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 35 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram ac timing operating specifications command and address input setup time t is b 125 ? 175 ? 175 ? 200 ? 200 ? 250 ? 350 ? ps 31, 33 input hold time t ih b 200 ? 250 ? 250 ? 275 ? 275 ? 375 ? 475 ? ps 31, 33 input setup time t is a 325 ? 375 ? 375 ? 400 ? 400 ? 500 ? 600 ? ps 31, 33 input hold time t ih a 325 ? 375 ? 375 ? 400 ? 400 ? 500 ? 600 ? ps 31, 33 input pulse width t ipw 0.6 ? 0.6 ? 0.6 ? 0.6 ? 0.6 ? 0.6 ? 0.6 ? t ck 18, 32 activate-to- activate delay, same bank t rc 54 ? 55 ? 55 ? 54 ? 55 ? 55 ? 55 ? ns 18, 34 activate-to-read or write delay t rcd 13.125 ? 12.5 ? 15 ? 12 ? 15 ? 15 ? 15 ? ns 18 activate-to- precharge delay t ras 40 70k 40 70k 40 70k 40 70k 40 70k 40 70k 40 70k ns 18, 34, 35 precharge period t rp 13.125 ? 12.5 ? 15 ? 12 ? 15 ? 15 ? 15 ? ns 18, 36 prechar ge all period <1gb t rpa 13.125 ? 12.5 ? 15 ? 12 ? 15 ? 15 ? 15 ? ns 18, 36 > 1gb t rpa 15 ? 15 ? 17.5 15 18 18.75 20 ns 18, 36 activate- to- activate delay different bank x4, x8 t rrd 7.5 ? 7.5 ? 7.5 ? 7.5 ? 7.5 ? 7.5 ? 7.5 ? ns 18, 37 x16 t rrd10 ? 10?10?10?10?10?10?ns18, 37 4-bank activate period x4, x8 t faw 35 ? 35 ? 35 ? 37.5 ? 37.5 ? 37.5 ? 37.5 ? ns 18, 38 x16 t faw45 ? 45?45?50?50?50?50?ns18, 38 internal read-to- precharge delay t rtp 7.5 ? 7.5 ? 7.5 ? 7.5 ? 7.5 ? 7.5 ? 7.5 ? ns 18, 37, 39 cas#-to-cas# delay t ccd2 ? 2?2?2?2?2?2? t ck 18 write recovery time t wr 15 ? 15 ? 15 ? 15 ? 15 ? 15 ? 15 ? ns 18, 37 write ap recovery + precharge time t dal t wr + t rp ? t wr + t rp ? t wr + t rp ? t wr + t rp ? t wr + t rp ? t wr + t rp ? t wr + t rp ?ns40 internal write-to- read delay t wtr 7.5 ? 7.5 ? 7.5 ? 7.5 ? 7.5 ? 7.5 ? 10 ? ns 18, 37 load mode cycle time t mrd2 ? 2?2?2?2?2?2? t ck 18 table 13: ac operating specifications and conditions for -187e, -25e, -3e, -3, -37e, and -5e speeds (sheet 5 of 7) not all speed grades listed may be su pported for this device; refer to th e title page for speeds supported; notes: 1?5 (page 38) apply to the entire table; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -187e -25e -25 -3e -3 -37e -5e units notes parameter symbol min max min max min max min max min max min max min max pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 36 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram ac timing operating specifications refresh refresh- to- activate or to- refresh interval 256mb t rfc75 757575757575ns18, 41 512mb 105 105 105 105 105 105 105 1gb 127.5 127.5 127.5 127.5 127.5 127.5 127.5 2gb 197.5 197.5 197.5 197.5 197.5 197.5 197.5 average periodic refresh (commercial) t refi ? 7.8 ? 7.8 ? 7.8 ? 7.8 ? 7.8 ? 7.8 ? 7.8 s 18, 41 average periodic refresh (industrial) t refi it ? 3.9 ? 3.9 ? 3.9 ? 3.9 ? 3.9 ? 3.9 ? 3.9 s 18, 41 average periodic refresh (automotive) t refi at ? 3.9 ? 3.9 ? 3.9 ? 3.9 ? 3.9 ? 3.9 ? 3.9 s 18, 41 cke low to ck, ck# uncertainty t delay min limit = t is + t ck + t ih max limit = n/a ns 42 self refresh exit self refresh to nonread command t xsnr min limit = t rfc (min) + 10 max limit = n/a ns exit self refresh to read command t xsrd min limit = 200 max limit = n/a t ck 18 exit self refresh timing reference t isxr min limit = t is max limit = n/a ps 33, 43 power-down exit active power- down to read command mr12 = 0 t xard3 ? 2?2?2?2?2?2? t ck 18 mr12 = 1 10 - al ? 8 - al?8 - al?7 - al?7 - al?6 - al?6 - al? t ck 18 exit precharge power-down to any nonread command t xp 3 ? 2?2?2?2?2?2? t ck 18 cke min high/ low time t cke min = 3 max = n/a t ck 18, 44 table 13: ac operating specifications and conditions for -187e, -25e, -3e, -3, -37e, and -5e speeds (sheet 6 of 7) not all speed grades listed may be su pported for this device; refer to th e title page for speeds supported; notes: 1?5 (page 38) apply to the entire table; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -187e -25e -25 -3e -3 -37e -5e units notes parameter symbol min max min max min max min max min max min max min max pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 37 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram ac timing operating specifications odt odt to power- down entry latency t anpd4 ? 3?3?3?3?3?3? t ck 18 odt power-down exit latency t axpd11 ?10?10?8?8?8?8? t ck 18 odt turn-on delay t aond 2 t ck 18 odt turn-off delay t aofd 2.5 t ck 18, 45 odt turn-on t aon t ac (min) t ac (max) + 2,575 min = t ac (min) max = t ac (max) + 600 min = t ac (min) max = t ac (max) + 700 min = t ac (min) max = t ac (max) + 1,000 ps 19, 46 odt turn-off t aof min = t ac (min) max = t ac (max) + 600 ps 47, 48 odt turn-on (power-down mode) t aonpd t ac (min) + 2,000 2 t ck + t ac (max) + 1,000 min = t ac (min) + 2,000 max = 2 t ck + t ac (max) + 1,000 ps 49 odt turn-off (power-down mode) t aofpd min = t ac (min) + 2,000 max = 2.5 t ck + t ac (max) + 1,000 ps odt enable from mrs command t mod min = 12 max = n/a ns 18, 50 table 13: ac operating specifications and conditions for -187e, -25e, -3e, -3, -37e, and -5e speeds (sheet 7 of 7) not all speed grades listed may be su pported for this device; refer to th e title page for speeds supported; notes: 1?5 (page 38) apply to the entire table; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -187e -25e -25 -3e -3 -37e -5e units notes parameter symbol min max min max min max min max min max min max min max pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 38 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram ac timing operating specifications notes 1. all voltages are referenced to v ss . 2. tests for ac timing, i dd , and electrical ac and dc ch aracteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and the operation of the device are warranted for the full voltage range specified. odt is dis- abled for all measurements that are not odt-specific. 3. outputs measured with equivalent load (see figure 17 on page 46). 4. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.0v in the test environ- ment, and parameter specificat ions are guaranteed for the specified ac input levels under normal use conditions. the slew rate for the input signals used to test the device is 1.0 v/ns for signals in the range between v il ( ac ) and v ih ( ac ). slew rates other than 1.0 v/ns may require the timing parameters to be derated as specified. 5. the ac and dc input level specifications ar e as defined in the sstl_18 standard (that is, the receiver will effectively switch as a result of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above [below] the dc input low [high] level). 6. ck and ck# input slew rate is referenced at 1 v/ns (2 v/ns if measured differentially). 7. operating frequency is only allowed to chan ge during self refresh mode (see figure 80 on page 117), precharge power-down mode, or system reset condition (see "reset" on page 118). ssc allows for small deviations in operating frequency, provided the ssc guidelines are satisfied. 8. the clock?s t ck (avg) is the average clock over any 200 consecutive clocks and t ck (avg) min is the smallest clock rate allowed (except for a deviation due to allowed clock jitter). input clock jitter is allowed provided it does not exceed values specified. also, the jitter must be of a random gaussian distribution in nature. 9. spread spectrum is not included in the ji tter specification values. however, the input clock can accommodate spread spectrum at a sweep rate in the range 20?60 khz with an additional one percent t ck (avg); however, the spread spectrum may not use a clock rate below t ck (avg) min or above t ck (avg) max. 10. min ( t cl, t ch) refers to the smaller of the actual clock low time and the actual clock high time driven to the device. the clock?s half period must also be of a gaussian dis- tribution; t ch (avg) and t cl (avg) must be met with or without clock jitter and with or without duty cycle jitter. t ch (avg) and t cl (avg) are the average of any 200 con- secutive ck falling edges. 11. t hp (min) is the lesser of t cl and t ch actually applied to the device ck and ck# inputs; thus, t hp (min) the lesser of t cl (abs) min and t ch (abs) min. 12. the period jitter ( t jit per ) is the maximum deviation in the clock period from the aver- age or nominal clock allowed in either the positive or negative direction. jedec spec- ifies tighter jitter numbers during dll lock ing time. during dll lock time, the jitter values should be 20 percent less thos e than noted in the table (dll locked). 13. the half-period jitter ( t jit dty ) applies to either the high pulse of clock or the low pulse of clock; however, the two cumulatively can not exceed t jit per . 14. the cycle-to-cycle jitter ( t jit cc ) is the amount the clock pe riod can deviate from one cycle to the next. jedec specifies tighter jitter numbers during dll locking time. during dll lock time, the jitter values should be 20 percent less than those noted in the table (dll locked). 15. the cumulative jitter error ( t err n per ), where n is 2, 3, 4, 5, 6?10, or 11?50 is the amount of clock time allowe d to consecutively accumula te away from the average clock over any number of clock cycles. 16. jedec specifies using t err 6?10 per when derating clock-related output timing (see notes 19 and 48). micron requires less derating by allowing t err 5 per to be used. pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 39 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram ac timing operating specifications 17. this parameter is not referenced to a specific voltage level but is specified when the device output is no longer driving ( t rpst) or beginning to drive ( t rpre). 18. the inputs to the dram must be aligned to the associated clock, that is, the actual clock that latches it in. however, the input timing (in ns) references to the t ck (avg) when determining the required number of clocks. the following input parameters are determined by taking the specified percentage times the t ck (avg) rather than t ck: t ipw, t dipw, t dqss, t dqsh, t dqsl, t dss, t dsh, t wpst, and t wpre. 19. the dram output timing is aligned to the nominal or average clock. most output parameters must be derated by the actual jitter error when input clock jitter is present; this will result in each parameter becoming larger. the following parameters are required to be derated by subtracting t err 5 per (max): t ac (min), t dqsck (min), t lz dqs (min), t lz dq (min), t aon (min); while the following parameters are required to be derated by subtracting t err 5 per (min): t ac (max), t dqsck (max), t hz (max), t lz dqs (max), t lz dq (max), t aon (max). the parameter t rpre (min) is derated by subtracting t jit per (max), while t rpre (max), is derated by subtracting t jit per (min). the parameter t rpst (min) is derated by subtracting t jit dty (max), while t rpst (max), is derated by subtracting t jit dty (min). output timings that require t err 5 per derating can be observed to have offsets relative to the clock; how- ever, the total window will not degrade. 20. when dqs is used single-ended, th e minimum limit is reduced by 100ps. 21. t hz and t lz transitions occur in the same access time windows as valid data transi- tions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving ( t hz) or begins driving ( t lz). 22. t lz (min) will prevail over a t dqsck (min) + t rpre (max) condition. 23. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turnaround. 24. it is recommended that dqs be valid (high or low) on or before the write com- mand. the case shown (dqs going from high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss. 25. the intent of the ?don?t care? state after completion of the postamble is that the dqs- driven signal should either be high, low, or high-z, and that any signal transition within the input switching region must follow valid input requirements. that is, if dqs transitions high (above v ih [ dc ] min), then it must not transition low (below v ih [ dc ]) prior to t dqsh (min). 26. referenced to each output group: x4 = dqs with dq0?dq3; x8 = dqs with dq0?dq7; x16 = ldqs with dq0?dq7; and udqs with dq8?dq15. 27. the data valid window is derive d by achieving other specifications: t hp ( t ck/2), t dqsq, and t qh ( t qh = t hp - t qhs). the data valid window derates in direct propor- tion to the clock duty cycle and a practical data valid window can be derived. 28. t qh = t hp - t qhs; the worst case t qh would be the lesser of t cl (abs) max or t ch (abs) max times t ck (abs) min - t qhs. minimizing the amount of t ch (avg) offset and value of t jit dty will provide a larger t qh, which in turn will provide a larger valid data out window. 29. this maximum value is derived from the referenced test load. t hz (max) will prevail over t dqsck (max) + t rpst (max) condition. 30. the values listed are for the differential dqs strobe (dqs and dqs#) with a differen- tial slew rate of 2 v/ns (1 v/ns for each signal). there are two sets of values listed: t ds a , t dh a and t ds b , t dh b . the t ds a , t dh a values (for reference only) are equivalent to the baseline values of t ds b , t dh b at v ref when the slew rate is 2 v/ns, differentially. the baseline values, t ds b , t dh b , are the jedec-defined values, referenced from the logic pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 40 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram ac timing operating specifications trip points. t ds b is referenced from v ih ( ac ) for a rising signal and v il ( ac ) for a falling signal, while t dh b is referenced from v il ( dc ) for a rising signal and v ih ( dc ) for a fall- ing signal. if the differential dqs slew rate is not equal to 2 v/ns, then the baseline val- ues must be derated by adding the values from tables 32 and 33 on pages 58?59. if the dqs differential strobe feature is not enab led, then the dqs strobe is single-ended and the baseline values must be derated using table 34 on page 60. single-ended dqs data timing is referenced at dqs crossing v ref . the correct timing values for a single- ended dqs strobe are listed in tables 35?37 on pages 60?61; listed values are already derated for slew rate variations and converted from baseline values to v ref values. 31. v il /v ih ddr2 overshoot/undershoot. see ?ac overshoot/undershoot specification? on page 52. 32. for each input signal?not the group collectively. 33. there are two sets of values listed for co mmand/address: t is a , t ih a and t is b , t ih b . the t is a , t ih a values (for reference only) are equivalent to the baseline values of t is b , t ih b at v ref when the slew rate is 1 v/ns. the baseline values, t is b , t ih b , are the jedec- defined values, referenced from the logic trip points. t is b is referenced from v ih ( ac ) for a rising signal and v il ( ac ) for a falling signal, while t ih b is referenced from v il ( dc ) for a rising signal and v ih ( dc ) for a falling signal. if the command/address slew rate is not equal to 1 v/ns, then the baseline values must be derated by adding the values from tables 30 and 31 on page 55. 34. this is applicable to read cycles only. write cycles generally require additional time due to t wr during auto precharge. 35. reads and writes with auto precharge are allowed to be issued before t ras (min) is satisfied because t ras lockout feature is su pported in ddr2 sdram. 36. when a single-bank precharge command is issued, t rp timing applies. t rpa timing applies when the precharge (all) command is issued, regardless of the number of banks open. for 8-bank devices ( 1gb), t rpa (min) = t rp (min) + t ck (avg) (table 13 on page 31 lists t rp [min] + t ck [avg] min). 37. this parameter has a two cloc k minimum requirement at any t ck. 38. the t faw (min) parameter applies to all 8-bank ddr2 devices. no more than four bank-activate commands may be issued in a given t faw (min) period. t rrd (min) restriction still applies. 39. the minimum internal read-to-precharge time. this is the time from which the last 4-bit prefetch begins to when the precharge command can be issued. a 4-bit prefetch is when the read command internal ly latches the read so that data will output cl later. this parameter is only applicable when t rtp/(2 t ck) > 1, such as frequencies faster than 533 mhz when t rtp = 7.5ns. if t rtp/(2 t ck) 1, then equa- tion al + bl/2 applies. t ras (min) has to be satisfied as well. the ddr2 sdram will automatically delay the intern al precharge command until t ras (min) has been satisfied. 40. t dal = ( n wr) + ( t rp/ t ck). each of these terms, if not already an integer, should be rounded up to the next integer. t ck refers to the application clock period; n wr refers to the t wr parameter stored in the mr 9?mr11 for example, -37e at t ck = 3.75ns with t wr programmed to four clocks would have t dal = 4 + (15ns/3.75ns) clocks = 4 + (4) clocks = 8 clocks. 41. the refresh period is 64ms (commercial) or 32ms (industrial and automotive). this equates to an average refresh rate of 7 .8125s (commercial) or 3.9607s (industrial and automotive). to ensure all rows of all banks are properly refreshed, 8,192 refresh commands must be issued every 64ms (commercial) or 32ms (industrial and automotive). the jedec t rfc max of 70,000ns is not required as bursting of auto refresh commands is allowed. pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 41 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram ac and dc operating conditions 42. t delay is calculated from t is + t ck + t ih so that cke registration low is guaranteed prior to ck, ck# being removed in a system reset condition (see "reset" on page 118). 43. t isxr is equal to t is and is used for cke setup time during self refresh exit, as shown in figure 70 on page 109. 44. t cke (min) of three clocks means cke must be registered on three consecutive posi- tive clock edges. cke must remain at the va lid input level the entire time it takes to achieve the three clocks of registration. thus, after any cke transition, cke may not transition from its valid level during the time period of t is + 2 t ck + t ih. 45. the half-clock of t aofd?s 2.5 t ck assumes a 50/50 clock duty cycle. this half-clock value must be derated by the amount of half-clock duty cycle error. for example, if the clock duty cycle was 47/53, t aofd would actually be 2.5 - 0.03, or 2.47, for t aof (min) and 2.5 + 0.03, or 2.53, for t aof (max). 46. odt turn-on time t aon (min) is when the device leaves high-z and odt resistance begins to turn on. odt turn-on time t aon (max) is when the odt resistance is fully on. both are measured from t aond. 47. odt turn-off time t aof (min) is when the device star ts to turn off odt resistance. odt turn off time t aof (max) is when the bus is in high-z. both are measured from t aofd. 48. half-clock output parameters must be derated by the actual t err 5 per and t jit dty when input clock jitter is present; this will result in each parameter becoming larger. the parameter t aof (min) is required to be derated by subtracting both t err 5 per (max) and t jit dty (max). the parameter t aof (max) is required to be der- ated by subtracting both t err 5 per (min) and t jit dty (min). 49. the -187e maximum limit is 2 t ck + t ac (max) + 1,000 but it will likely be 3x t ck + t ac (max) + 1,000 in the future. 50. should use 8 t ck for backward compatibility. ac and dc operating conditions notes: 1. v dd and v dd q must track each other. v dd q must be v dd . 2. v ss q = v ss l = v ss . 3. v dd q tracks with v dd ; v dd l tracks with v dd . 4. v ref is expected to equal v dd q/2 of the transmitting device and to track variations in the dc level of the same. peak-to-pe ak noise (noncommon mode) on v ref may not exceed 1 percent of the dc value. peak-to-peak ac noise on v ref may not exceed 2 percent of v ref ( dc ). this measurement is to be taken at the nearest v ref bypass capacitor. 5. v tt is not applied direct ly to the device. v tt is a system supply for signal termination resis- tors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . table 14: recommended dc op erating conditions (sstl_18) all voltages referenced to v ss parameter symbol min nom max units notes supply voltage v dd 1.7 1.8 1.9 v 1, 2 v dd l supply voltage v dd l 1.7 1.8 1.9 v 2, 3 i/o supply voltage v dd q 1.7 1.8 1.9 v 2, 3 i/o reference voltage v ref ( dc ) 0.49 v dd q 0.50 v dd q 0.51 v dd qv 4 i/o termination voltage (system) v tt v ref ( dc ) - 40 v ref ( dc )v ref ( dc ) + 40 mv 5 pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 42 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram odt dc electrical characteristics odt dc electrical characteristics notes: 1. r tt 1( eff ) and r tt 2( eff ) are determined by separately applying v ih ( ac ) and v il ( ac ) to the ball being tested, and then measuring current, i(v ih ( ac )), and i(v il ( ac )), respectively. (eq 1) 2. minimum it and at device values are dera ted by six percent when the devices operate between ?40c and 0c (t c ). 3. measure voltage (vm) at tested ball with no load. (eq 2) input electrical characterist ics and operating conditions notes: 1. v dd q + 300mv allowed provided 1.9v is not exceeded. notes: 1. v dd q + 300mv allowed provided 1.9v is not exceeded. table 15: odt dc electrical characteristics all voltages are referenced to v ss parameter symbol min nom max units notes r tt effective impedance value for 75 setting emr (a6, a2) = 0, 1 r tt 1( eff )607590 1, 2 r tt effective impedance value for 150 setting emr (a6, a2) = 1, 0 r tt 2( eff ) 120 150 180 1, 2 r tt effective impedance value for 50 setting emr (a6, a2) = 1, 1 r tt 3( eff )405060 1, 2 deviation of vm with respect to v dd q/2 vm ?6 6 % 3 table 16: input dc logic levels all voltages are referenced to v ss parameter symbol min max units input high (logic 1) voltage v ih ( dc )v ref ( dc ) + 125 v dd q 1 mv input low (logic 0) voltage v il ( dc ) ?300 v ref ( dc ) - 125 mv table 17: input ac logic levels all voltages referenced to v ss parameter symbol min max units input high (logic 1) voltage (-37e/-5e) v ih ( ac )v ref ( dc ) + 250 v dd q 1 mv input high (logic 1) volt age (-187e/-25e/-25/-3e/-3) v ih ( ac )v ref ( dc ) + 200 v dd q 1 mv input low (logic 0) voltage (-37e/-5e) v il ( ac )?300v ref ( dc ) - 250 mv input low (logic 0) voltage (-187e/-25e/-25/-3e/-3) v il ( ac )?300v ref ( dc ) - 200 mv r tt eff () v ih ac () v il ac () ? iv ih ac () () iv il ac () () ? ------------------------------------------------------------- = vm 2 vm v dd q ----------------- - 1 ? ?? ?? 100 = pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 43 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram input electrical characteristics and operating conditions figure 14: single-ended input signal levels notes: 1. numbers in diagram reflec t nominal ddr2-400/ddr2-533 values. 650mv 775mv 864mv 882mv 900mv 918mv 936mv 1,025mv 1,150mv v il(ac) v il(dc) v ref - ac noise v ref - dc error v ref + dc error v ref + ac noise v ih(dc) v ih(ac) pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 44 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram input electrical characteristics and operating conditions notes: 1. v in ( dc ) specifies the allowable dc execution of each input of differential pair such as ck, ck#, dqs, dqs#, ldqs, ldqs#, udqs, udqs#, and rdqs, rdqs#. 2. v id ( dc ) specifies the input differential voltage |v tr - v cp | required for sw itching, where v tr is the true input (such as ck, dqs, ldqs, udqs) level and v cp is the complementary input (such as ck#, dqs#, ldqs#, udqs#) le vel. the minimum value is equal to v ih ( dc ) - v il ( dc ). differential input signal levels are shown in figure 15. 3. v id ( ac ) specifies the input differential voltage |v tr - v cp | required for sw itching, where v tr is the true input (such as ck, dq s, ldqs, udqs, rdqs) level and v cp is the complementary input (such as ck#, dqs#, ldqs#, udqs#, rdqs #) level. the minimu m value is equal to v ih ( ac ) - v il ( ac ), as shown in table 17 on page 42. 4. the typical value of v ix ( ac ) is expected to be about 0.5 v dd q of the transmitting device and v ix ( ac ) is expected to track variations in v dd q. v ix ( ac ) indicates the voltage at which differential input si gnals must cross, as shown in figure 15. 5. v mp ( dc ) specifies the input differen tial common mode voltage (v tr + v cp )/2 where v tr is the true input (ck, dqs) level and v cp is the complementary input (ck#, dqs#). v mp ( dc ) is expected to be approximately 0.5 v dd q. 6. v dd q + 300mv allowed provided 1.9v is not exceeded. figure 15: differential input signal levels notes: 1. tr and cp may not be more positive than v dd q + 0.3v or more negative than v ss - 0.3v. 2. tr represents the ck, dqs, rdqs, ldqs, and udqs signals; cp represents ck#, dqs#, rdqs#, ldqs#, and udqs# signals. 3. this provides a minimum of 850mv to a maximum of 950mv and is expected to be v dd q/2. 4. tr and cp must cross in this region. 5. tr and cp must meet at least v id ( dc ) min when static and is centered around v mp ( dc ). 6. tr and cp must have a mini mum 500mv peak-to-peak swing. 7. numbers in diagram re flect nominal values (v dd q = 1.8v). table 18: differential input logic levels all voltages referenced to v ss parameter symbol min max units notes dc input signal voltage v in ( dc )?300 v dd qmv1, 6 dc differential input voltage v id ( dc ) 250 v dd qmv2, 6 ac differential input voltage v id ( ac ) 500 v dd qmv3, 6 ac differential cr oss-point voltage v ix ( ac ) 0.50 v dd q - 175 0.50 v dd q + 175 mv 4 input midpoint voltage v mp ( dc ) 850 950 mv 5 tr 2 cp 2 2.1v v dd q = 1.8v v in ( dc ) max 1 v in ( dc ) min 1 ?0.30v 0.9v 1.075v 0.725v v mp ( dc ) 3 x x v ix ( ac ) 4 v id ( ac ) 6 v id ( dc ) 5 pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 45 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram output electrical characteristics and operating conditions output electrical characteris tics and operating conditions notes: 1. the typical value of v ox ( ac ) is expected to be about 0.5 v dd q of the transmitting device and v ox ( ac ) is expected to track variations in v dd q. v ox ( ac ) indicates the voltage at which differential output signals must cross. figure 16: differential output signal levels notes: 1. for i oh ( dc ); v dd q = 1.7v, v out = 1,420mv. (v out - v dd q)/i oh must be less than 21 for val- ues of v out between v dd q and v dd q - 280mv. 2. for i ol ( dc ); v dd q = 1.7v, v out = 280mv. v out /i ol must be less than 21 for values of v out between 0v and 280mv. 3. the dc value of v ref applied to the receiving device is set to v tt . 4. the values of i oh ( dc ) and i ol ( dc ) are based on the conditions given in notes 1 and 2. they are used to test device drive current capability to ensure v ih (min) plus a noise margin and v il (max) minus a noise ma rgin are delivered to an sstl_18 receiver. the actual current val- ues are derived by shifting the desired driver operating point (see output iv curves) along a 21 load line to define a convenient driver current for measurement. table 19: differential ac output parameters parameter symbol min max units notes ac differential cr oss-point voltage v ox ( ac ) 0.50 v dd q - 125 0.50 v dd q + 125 mv 1 ac differential voltage swing v swing 1.0 mv table 20: output dc current drive parameter symbol value units notes output min source dc current i oh ?13.4 ma 1, 2, 4 output min sink dc current i ol 13.4 ma 2, 3, 4 crossing point v ox v ss q v swing v dd q v tr v cp pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 46 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram output electrical characteristics and operating conditions notes: 1. absolute specifications: 0c t c +85c ; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v. 2. impedance measurement conditions for output source dc current: v dd q = 1.7v; v out = 1,420mv; (v out - v dd q)/i oh must be less than 23.4 for values of v out between v dd q and v dd q - 280mv. the impedance measurement condition for output sink dc cur- rent: v dd q = 1.7v; v out = 280mv; v out /i ol must be less than 23.4 for values of v out between 0v and 280mv. 3. mismatch is an absolute value between pull- up and pull-down; both are measured at the same temperature and voltage. 4. output slew rate for falling and rising edges is measured between v tt - 250mv and v tt + 250mv for single-ended signals. for differen tial signals (dqs, dqs# ), output slew rate is measured between dqs - dqs# = ?500mv and dqs# - dqs = +500mv. ou tput slew rate is guaranteed by design but is not ne cessarily tested on each device. 5. the absolute value of the sl ew rate as measured from v il ( dc ) max to v ih ( dc ) min is equal to or greater than the slew rate as measured from v il ( ac ) max to v ih ( ac ) min. this is guaran- teed by design and characterization. 6. it and at devices require an additional 0.4 v/ns in the max limit when t c is between ?40c and 0c. figure 17: output slew rate load table 21: output characteristics parameter min nom max units notes output impedance see ?output driver characteristics? on page 47 1, 2 pull-up and pull-down mismatch 04 1, 2, 3 output slew rate 1.5 5 v/ns 1, 4, 5, 6 output (v out ) referen c e point 25 v tt = v dd q/2 pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 47 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram output driver characteristics output driver characteristics figure 18: full strength pull-down characteristics table 22: full strength pull-down current (ma) voltage (v) min nom max 0.0 0.000.000.00 0.1 4.305.637.95 0.2 8.60 11.30 15.90 0.3 12.90 16.52 23.85 0.4 16.90 22.19 31.80 0.5 20.40 27.59 39.75 0.6 23.28 32.39 47.70 0.7 25.44 36.45 55.55 0.8 26.79 40.38 62.95 0.9 27.67 44.01 69.55 1.0 28.38 47.01 75.35 1.1 28.96 49.63 80.35 1.2 29.46 51.71 84.55 1.3 29.90 53.32 87.95 1.4 30.29 54.9 90.70 1.5 30.65 56.03 93.00 1.6 30.98 57.07 95.05 1.7 31.31 58.16 97.05 1.8 31.64 59.27 99.05 1.9 31.96 60.35 101.05 v out (v) 0.0 0.5 1.0 1.5 120 100 80 6 0 40 20 0 i out ( m a) pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 48 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram output driver characteristics figure 19: full strength pull-up characteristics table 23: full strength pull-up current (ma) voltage (v) min nom max 0.0 0.000.000.00 0.1 ?4.30 ?5.63 ?7.95 0.2 ?8.60 ?11.30 ?15.90 0.3 ?12.90 ?16.52 ?23.85 0.4 ?16.90 ?22.19 ?31.80 0.5 ?20.40 ?27.59 ?39.75 0.6 ?23.28 ?32.39 ?47.70 0.7 ?25.44 ?36.45 ?55.55 0.8 ?26.79 ?40.38 ?62.95 0.9 ?27.67 ?44.01 ?69.55 1.0 ?28.38 ?47.01 ?75.35 1.1 ?28.96 ?49.63 ?80.35 1.2 ?29.46 ?51.71 ?84.55 1.3 ?29.90 ?53.32 ?87.95 1.4 ?30.29 ?54.90 ?90.70 1.5 ?30.65 ?56.03 ?93.00 1.6 ?30.98 ?57.07 ?95.05 1.7 ?31.31 ?58.16 ?97.05 1.8 ?31.64 ?59.27 ?99.05 1.9 ?31.96 ?60.35 ?101.05 v dd q - v out (v) 0 ?20 ?40 ? 6 0 ?80 ?100 ?120 0 0.5 1.0 1.5 i out (ma) pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 49 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram output driver characteristics figure 20: reduced strength pull-down characteristics table 24: reduced strength pull-down current (ma) voltage (v) min nom max 0.0 0.000.000.00 0.1 1.722.984.77 0.2 3.445.999.54 0.3 5.16 8.75 14.31 0.4 6.76 11.76 19.08 0.5 8.16 14.62 23.85 0.6 9.31 17.17 28.62 0.7 10.18 19.32 33.33 0.8 10.72 21.40 37.77 0.9 11.07 23.32 41.73 1.0 11.35 24.92 45.21 1.1 11.58 26.30 48.21 1.2 11.78 27.41 50.73 1.3 11.96 28.26 52.77 1.4 12.12 29.10 54.42 1.5 12.26 29.70 55.80 1.6 12.39 30.25 57.03 1.7 12.52 30.82 58.23 1.8 12.66 31.41 59.43 1.9 12.78 31.98 60.63 70 6 0 50 40 30 20 10 0 0.0 0.5 1.0 1.5 v out (v) i out (mv) pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 50 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram output driver characteristics figure 21: reduced strength pull-up characteristics table 25: reduced strength pull-up current (ma) voltage (v) min nom max 0.0 0.000.000.00 0.1 ?1.72 ?2.98 ?4.77 0.2 ?3.44 ?5.99 ?9.54 0.3 ?5.16 ?8.75 ?14.31 0.4 ?6.76 ?11.76 ?19.08 0.5 ?8.16 ?14.62 ?23.85 0.6 ?9.31 ?17.17 ?28.62 0.7 ?10.18 ?19.32 ?33.33 0.8 ?10.72 ?21.40 ?37.77 0.9 ?11.07 ?23.32 ?41.73 1.0 ?11.35 ?24.92 ?45.21 1.1 ?11.58 ?26.30 ?48.21 1.2 ?11.78 ?27.41 ?50.73 1.3 ?11.96 ?28.26 ?52.77 1.4 ?12.12 ?29.10 ?54.42 1.5 ?12.26 ?29.69 ?55.8 1.6 ?12.39 ?30.25 ?57.03 1.7 ?12.52 ?30.82 ?58.23 1.8 ?12.66 ?31.42 ?59.43 1.9 ?12.78 ?31.98 ?60.63 0 ?10 ?20 ?30 ?40 ?50 ? 6 0 ?70 0.0 0.5 1.0 1.5 v dd q - v out (v) i out (mv) pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 51 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram power and ground clamp characteristics power and ground clamp characteristics power and ground clamps are provided on the following input-only balls: address balls, bank address balls, cs#, ras#, cas#, we#, odt, and cke. figure 22: input clamp characteristics table 26: input clamp characteristics voltage across clamp (v) minimum power clamp current (ma) minimum ground clamp current (ma) 0.0 0.0 0.0 0.1 0.0 0.0 0.2 0.0 0.0 0.3 0.0 0.0 0.4 0.0 0.0 0.5 0.0 0.0 0.6 0.0 0.0 0.7 0.0 0.0 0.8 0.1 0.1 0.9 1.0 1.0 1.0 2.5 2.5 1.1 4.7 4.7 1.2 6.8 6.8 1.3 9.1 9.1 1.4 11.0 11.0 1.5 13.5 13.5 1.6 16.0 16.0 1.7 18.2 18.2 1.8 21.0 21.0 volta g e a c ross c lamp (v) minimum c lamp c urrent (ma) 25 20 15 10 5 0 0.0 0.1 0.2 0.3 0.4 0.5 0. 6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1. 6 1.7 1.8 pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 52 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram ac overshoot/undershoot specification ac overshoot/undershoot specification some revisions will support the 0.9v maxi mum average amplitude instead of the 0.5v maximum average amplitude shown in tables 27 and 28. figure 23: overshoot figure 24: undershoot table 27: address and control balls applies to address balls, bank address balls, cs#, ras#, cas#, we#, cke, odt parameter specification -187e -25/-25e -3/-3e -37e -5e maximum peak amplitude allowe d for overshoot area (see figure 23) 0.50v 0.50v 0.50v 0.50v 0.50v maximum peak amplitude allowed for undershoot area (see figure 24) 0.50v 0.50v 0.50v 0.50v 0.50v maximum overshoot area above v dd (see figure 23) 0.5 vns 0.66 vns 0.80 vns 1.00 vns 1.33 vns maximum undershoot area below v ss (see figure 24) 0.5 vns 0.66 vns 0.80 vns 1.00 vns 1.33 vns table 28: clock, data, strobe, and mask balls applies to dq, dqs, dqs#, rdqs, rdqs#, udqs, udqs#, ldqs, ldqs#, dm, udm, ldm parameter specification -187e -25/-25e -3/-3e -37e -5e maximum peak amplitude allowed for overshoot area (see figure 23) 0.50v 0.50v 0.50v 0.50v 0.50v maximum peak amplitude allowed for undershoot area (see figure 24) 0.50v 0.50v 0.50v 0.50v 0.50v maximum overshoot area above v dd q (see figure 23) 0.19 vns 0.23 vns 0.23 vns 0.28 vns 0.38 vns maximum undershoot area below v ss q (see figure 24) 0.19 vns 0.23 vns 0.23 vns 0.28 vns 0.38 vns maximum amplitu d e overshoot area v dd /v dd q v ss /v ss q v olt s (v) time (ns) v ss /v ss q maximum amplitu d e un d ershoot area time (ns) volts (v) pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 53 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram ac overshoot/undershoot specification notes: 1. all voltages referenced to v ss . 2. input waveform setup timing ( t is b ) is referenced from the input signal crossing at the v ih ( ac ) level for a rising signal and v il ( ac ) for a falling signal applied to the device under test, as shown in figure 33 on page 64. 3. see ?input slew rate derating? on page 54. 4. the slew rate for single-ended inpu ts is measured from dc level to ac level, v il ( dc ) to v ih ( ac ) on the rising edge and v il ( ac ) to v ih ( dc ) on the falling edge. for signals referenced to v ref , the valid intersection is where the ?tangent? line intersects v ref , as shown in figures 26, 28, 30, and 32. 5. input waveform hold ( t ih b ) timing is referenced from the input signal crossing at the v il ( dc ) level for a rising signal and v ih ( dc ) for a falling signal applied to the device under test, as shown in figure 33 on page 64. 6. input waveform setup timing ( t ds) and hold timing ( t dh) for single-ended data strobe is referenced from the crossing of dqs, udqs, or ldqs through the v ref level applied to the device under test, as shown in figure 35 on page 65. 7. input waveform setup timing ( t ds) and hold timing ( t dh) when differential data strobe is enabled is referenced from the cross-point of dqs/dqs#, udqs/udqs#, or ldqs/ldqs#, as shown in figure 34 on page 64. 8. input waveform timing is referenc ed to the crossi ng point level (v ix ) of two input signals (v tr and v cp ) applied to the device under test, where v tr is the true input signal and v cp is the complementary input signal, as shown in figure 36 on page 65. 9. the slew rate for differentia lly ended inputs is measured from twice the dc level to twice the ac level: 2 v il ( dc ) to 2 v ih ( ac ) on the rising edge and 2 v il ( ac ) to 2 v ih ( dc ) on the falling edge. for example, the ck/ck# would be ?250mv to +5 00mv for ck rising edge and would be +250mv to ?500mv for ck falling edge. table 29: ac input test conditions parameter symbol min max units notes input setup timing measurement reference level address balls, bank address balls, cs#, ras#, cas#, we#, odt, dm, udm, ldm, and cke v rs see note 2 1, 2, 3, 4 input hold timing measurem ent reference level address balls, bank address balls, cs#, ras#, cas#, we#, odt, dm, udm, ldm, and cke v rh see note 5 1, 3, 4, 5 input timing measurement refe rence level (single-ended) dqs for x4, x8; udqs, ldqs for x16 v ref ( dc )v dd q 0.49 v dd q 0.51 v 1, 3, 4, 6 input timing measurement refe rence level (d ifferential) ck, ck# for x4, x8, x16; dqs, dqs# for x4, x8; rdqs, rdqs# for x8; udqs, udqs#, ldqs, ldqs# for x16 v rd v ix ( ac ) v 1, 3, 7, 8, 9 pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 54 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram input slew rate derating input slew rate derating for all input signals, the total t is (setup time) and t ih (hold time) required is calculated by adding the data sheet t is (base) and t ih (base) value to the t is and t ih derating value, respectively. example: t is (total setup time) = t is (base) + t is. t is, the nominal slew rate for a rising signal, is defined as the slew rate between the last crossing of v ref ( dc ) and the first crossing of v ih ( ac ) min. setup nominal slew rate ( t is) for a falling signal is defined as the slew rate between the last crossing of v ref ( dc ) and the first cros sing of v il ( ac ) max. if the actual signal is always earlier than the nominal slew rate line between shaded ?v ref ( dc ) to ac region,? use the nominal slew ra te for the derating value (figure 25 on page 56). if the actual signal is later than the nomina l slew rate line anywhere between the shaded ?v ref ( dc ) to ac region,? the slew rate of a tangent line to the actual signal from the ac level to dc level is used for the derating value (see figure 26 on page 56). t ih, the nominal slew rate for a rising signal, is defined as the slew rate between the last crossing of v il ( dc ) max and the first crossing of v ref ( dc ). t ih, nominal slew rate for a falling signal, is defined as the slew rate between the last crossing of v ih ( dc ) min and the first cros sing of v ref ( dc ). if the actual signal is always later than the nominal slew rate line between shaded ?dc to v ref ( dc ) region,? use the nominal slew rate for the derating value (figure 27 on page 57). if the actual signal is earlier than the nomi nal slew rate line anywhere between shaded ?dc to v ref ( dc ) region,? the slew rate of a tangent line to the actual signal from the dc level to v ref ( dc ) level is used for the derating value (figure 28 on page 57). although the total setup time might be negative for slow slew rates (a valid input signal will not have reached v ih [ ac ]/v il [ ac ] at the time of the rising clock transition), a valid input signal is still required to complete the transition and reach v ih ( ac )/v il ( ac ). for slew rates in between the values listed in tables 30 and 31 on page 55, the derating values may obtained by linear interpolation. pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 55 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram input slew rate derating table 30: ddr2-400/533 setup and hold time derating values ( t is and t ih) command/ address slew rate (v/ns) ck, ck# differential slew rate units 2.0 v/ns 1.5 v/ns 1.0 v/ns t is t ih t is t ih t is t ih 4.0 +187 +94 +217 +124 +247 +154 ps 3.5 +179 +89 +209 +119 +239 +149 ps 3.0 +167 +83 +197 +113 +227 +143 ps 2.5 +150 +75 +180 +105 +210 +135 ps 2.0 +125 +45 +155 +75 +185 +105 ps 1.5 +83 +21 +113 +51 +143 +81 ps 1.0 0 0 +30 +30 +60 +60 ps 0.9 ?11 ?14 +19 +16 +49 +46 ps 0.8 ?25 ?31 +5 ?1 +35 +29 ps 0.7 ?43 ?54 ?13 ?24 +17 +6 ps 0.6 ?67 ?83 ?37 ?53 ?7 ?23 ps 0.5 ?110 ?125 ?80 ?95 ?50 ?65 ps 0.4 ?175 ?188 ?145 ?158 ?115 ?128 ps 0.3 ?285 ?292 ?255 ?262 ?225 ?232 ps 0.25 ?350 ?375 ?320 ?345 ?290 ?315 ps 0.2 ?525 ?500 ?495 ?470 ?465 ?440 ps 0.15 ?800 ?708 ?770 ?678 ?740 ?648 ps 0.1 ?1,450 ?1,125 ?1,420 ?1,095 ?1,390 ?1,065 ps table 31: ddr2-667/800/1066 setup and hold time derating values ( t is and t ih) command/ address slew rate (v/ns) ck, ck# differential slew rate units 2.0 v/ns 1.5 v/ns 1.0 v/ns t is t ih t is t ih t is t ih 4.0 +150 +94 +180 +124 +210 +154 ps 3.5 +143 +89 +173 +119 +203 +149 ps 3.0 +133 +83 +163 +113 +193 +143 ps 2.5 +120 +75 +150 +105 +180 +135 ps 2.0 +100 +45 +160 +75 +160 +105 ps 1.5 +67 +21 +97 +51 +127 +81 ps 1.0 0 0 +30 +30 +60 +60 ps 0.9 ?5 ?14 +25 +16 +55 +46 ps 0.8 ?13 ?31 +17 ?1 +47 +29 ps 0.7 ?22 ?54 +8 ?24 +38 +6 ps 0.6 ?34 ?83 ?4 ?53 +36 ?23 ps 0.5 ?60 ?125 ?30 ?95 0 ?65 ps 0.4 ?100 ?188 ?70 ?158 ?40 ?128 ps 0.3 ?168 ?292 ?138 ?262 ?108 ?232 ps 0.25 ?200 ?375 ?170 ?345 ?140 ?315 ps 0.2 ?325 ?500 ?295 ?470 ?265 ?440 ps 0.15 ?517 ?708 ?487 ?678 ?457 ?648 ps 0.1 ?1,000 ?1,125 ?970 ?1,095 ?940 ?1,065 ps pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 56 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram input slew rate derating figure 25: nominal slew rate for t is figure 26: tangent line for t is v ss c k# c k t ih t i s t ih s etup slew rate risin g si g nal s etup slew rate fallin g si g nal d tf d tr tf = v ih ( a c ) min - v ref ( d c ) tr = v dd q t i s nominal slew rate v ref to a c re g ion v ref to a c re g ion v ref ( d c ) - v il ( a c ) max v ih ( d c ) min v ref ( d c ) v il ( a c ) max v il ( d c ) max v ih ( a c ) min nominal slew rate s etup slew rate risin g si g nal tf tr tan g ent line (v ih [ a c ] min - v ref [ d c ]) tr = tan g ent line tan g ent line v ref to a c re g ion nominal line t ih t i s t ih t i s v ss c k# c k v dd q v ih ( a c ) min v ih ( d c ) min v ref ( d c ) v il ( d c ) max v il ( a c ) max v ref to a c re g ion nominal line pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 57 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram input slew rate derating figure 27: nominal slew rate for t ih figure 28: tangent line for t ih tr tf nominal slew rate d c to v ref re g ion t ih t i s t i s v ss c k# c k v dd q v ih ( d c ) min v ref ( d c ) v il ( a c ) max v il ( d c ) max v ih ( a c ) min d c to v ref re g ion nominal slew rate t ih tan g ent line d c to v ref re g ion t ih t i s t i s v ss v dd q v ih ( d c ) min v ref ( d c ) v il ( a c ) max v il ( d c ) max v ih ( a c ) min d c to v ref re g ion tan g ent line t ih c k c k# hol d slew rate fallin g si g nal tf tr tan g ent line (v ih [ d c ] min - v ref [ d c ]) tf = nominal line hol d slew rate risin g si g nal tan g ent line (v ref [ d c ] - v il [ d c ] max) tr = nominal line pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 58 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram input slew rate derating notes: 1. for all input signals, the total t ds and t dh required is calculated by adding the data sheet value to the derating value listed in table 32. 2. t ds nominal slew rate for a rising signal is defi ned as the slew rate be tween the last crossing of v ref ( dc ) and the first crossing of v ih ( ac ) min. t ds nominal slew rate for a falling signal is defined as the slew rate betw een the last crossing of v ref ( dc ) and the first crossing of v il ( ac ) max. if the actual signal is always earlier than the no minal slew rate line between the shaded ?v ref ( dc ) to ac region,? use the nominal slew rate for the derating value (see figure 29 on page 62). if the actual signal is la ter than the nominal slew rate line anywhere between the shaded ?v ref ( dc ) to ac region,? the slew rate of a tangent line to the actual signal from the ac level to dc level is used for the derating value (see figure 30 on page 62). 3. t dh nominal slew rate for a rising signal is de fined as the slew rate between the last cross- ing of v il ( dc ) max and the first crossing of v ref ( dc ). t dh nominal slew rate for a falling sig- nal is defined as the slew rate between the last crossing of v ih ( dc ) min and the first crossing of v ref (dc). if the actual signal is always later than the nominal slew rate line between the shaded ?dc level to v ref ( dc ) region,? use the nominal slew ra te for the derating value (see figure 31 on page 63). if the actual signal is earlier than the nominal slew rate line any- where between shaded ?dc to v ref ( dc ) region,? the slew rate of a tangent line to the actual signal from the dc level to v ref ( dc ) level is used for the dera ting value (see figure 32 on page 63). 4. although the total setup time might be negative for slow sl ew rates (a valid input signal will not have reached v ih [ ac ]/v il [ ac ] at the time of the rising clock transition), a valid input signal is still requir ed to complete the transition and reach v ih ( ac )/v il ( ac ). 5. for slew rates between the values listed in th is table, the derating values may be obtained by linear interpolation. 6. these values are typically not subject to production test. they are verified by design and characterization. 7. single-ended dqs requires special derating. the values in table 34 on page 60 are the dqs single-ended slew ra te derating with dqs referenced at v ref and dq referenced at the logic levels t ds b and t dh b . converting the derated ba se values from dqs referenced to the ac/dc trip points to dqs referenced to v ref is listed in table 36 on page 61 and table 37 on page 61. table 36 on page 61 provides the v ref -based fully derated values for the dq ( t ds a and t dh a ) for ddr2-533. table 37 on page 61 provides the v ref -based fully derated values for the dq ( t ds a and t dh a ) for ddr2-400. table 32: ddr2-400/ddr2-533 t ds, t dh derating values with differential strobe all units are shown in picoseconds dq slew rate (v/ns) dqs, dqs# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh 2.0125451254512545???????????? 1.5 8321832183219533 ? ? ? ? ? ? ? ? ? ? 1.0 00000012122424???????? 0.9 ? ? ?11 ?14 ?11 ?14 1 ?2 13 10 25 22 ? ? ? ? ? ? 0.8 ? ? ? ? ?25 ?31 ?13 ?19 ?1 ?7 11 5 23 17 ? ? ? ? 0.7 ? ? ? ? ? ? ?31 ?42 ?19 ?30 ?7 ?18 5 ?6 17 6 ? ? 0.6 ? ? ? ? ? ? ? ? ?43 ?59 ?31 ?47 ?19 ?35 ?7 ?23 5 ?11 0.5 ? ? ? ? ? ? ? ? ? ? ?74 ?89 ?62 ?77 ?50 ?65 ?38 ?53 0.4 ? ? ? ? ? ? ? ? ? ? ? ? ?127 ?140 ?115 ?128 ?103 ?116 pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 59 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram input slew rate derating notes: 1. for all input signals the total t ds and t dh required is calculated by adding the data sheet value to the derating value listed in table 33. 2. t ds nominal slew rate for a rising signal is defi ned as the slew rate be tween the last crossing of v ref ( dc ) and the first crossing of v ih ( ac ) min. t ds nominal slew rate for a falling signal is defined as the slew rate betw een the last crossing of v ref ( dc ) and the first crossing of v il ( ac ) max. if the actual signal is always earlier than the no minal slew rate line between the shaded ?v ref ( dc ) to ac region,? use the nominal slew rate for the derating value (see figure 29 on page 62). if the actual signal is la ter than the nominal slew rate line anywhere between shaded ?v ref ( dc ) to ac region,? the slew rate of a tangent line to the actual signal from the ac level to dc level is used for th e derating value (see figure 30 on page 62). 3. t dh nominal slew rate for a rising signal is de fined as the slew rate between the last cross- ing of v il ( dc ) max and the first crossing of v ref ( dc ). t dh nominal slew rate for a falling sig- nal is defined as the slew rate between the last crossing of v ih ( dc ) min and the first crossing of v ref ( dc ). if the actual signal is always later than the nomina l slew rate line between the shaded ?dc level to v ref ( dc ) region,? use the nominal slew ra te for the derating value (see figure 31 on page 63). if the actual signal is earlier than the nominal slew rate line any- where between the shaded ?dc to v ref ( dc ) region,? the slew rate of a tangent line to the actual signal from the dc level to v ref ( dc ) level is used for the dera ting value (see figure 32 on page 63). 4. although the total setup time might be negative for slow sl ew rates (a valid input signal will not have reached v ih [ ac ]/v il [ ac ] at the time of the rising clock transition), a valid input signal is still requir ed to complete the transition and reach v ih ( ac )/v il ( ac ). 5. for slew rates between the values listed in th is table, the derating values may be obtained by linear interpolation. 6. these values are typically not subject to production test. they are verified by design and characterization. 7. single-ended dqs requires special derating. the values in table 34 on page 60 are the dqs single-ended slew ra te derating with dqs referenced at v ref and dq referenced at the logic levels t ds b and t dh b . converting the derated ba se values from dqs referenced to the ac/dc trip points to dqs referenced to v ref is listed in table 35 on page 60. table 35 on page 60 provides the v ref -based fully derated values for the dq ( t ds a and t dh a ) for ddr2-667. it is not advised to operate ddr2-8 00 and ddr2-1066 devices with single-ended dqs; however table 34 on page 60 would be used with the base values. table 33: ddr2-667/ddr2-800/ddr2-1066 t ds, t dh derating values with differential strobe all units are shown in picoseconds dq slew rate (v/ns) dqs, dqs# differential slew rate 2.8 v/ns 2.4 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh 2.0 100 63 100 63 100 63 112 75 124 87 136 99 148 111 160 123 172 135 1.5 67 42 67 42 67 42 79 54 91 66 103 78 115 90 127 102 139 114 1.0 0 0 0 0 0 0 121224243636484860607272 0.9 ?5?14?5?14?5?147 ?219103122433455466758 0.8 ?13 ?31 ?13 ?31 ?13 ?31 ?1 ?19 11 ?7 23 5 35 17 47 29 59 41 0.7 ?22 ?54 ?22 ?54 ?22 ?54 ?10 ?42 2 ?30 14 ?18 26 ?6 38 6 50 18 0.6 ?34 ?83 ?34 ?83 ?34 ?83 ?22 ?71 ?10 ?59 2 ?47 14 ?35 26 ?23 38 ?11 0.5 ?60 ?125 ?60 ?125 ?60 ?125 ?48 ?113 ?36 ?101 ?24 ?89 ?12 ?77 0 ?65 12 ?53 0.4 ?100 ?188 ?100 ?188 ?100 ?188 ?88 ?176 ?76 ?164 ?64 ?152 ?52 ?140 ?40 ?128 ?28 ?116 pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 60 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram input slew rate derating table 34: single-ended dqs slew rate derating values using t ds b and t dh b reference points indicated in bold; derati ng values are to be used with base t ds b - and t dh b -specified values dq (v/ns) dqs single-ended slew rate derated (at v ref ) 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns 0.6 v/ns 0.4v/ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh 2.0 130 53 130 53 130 53 130 53 130 53 145 48 155 45 165 41 175 38 1.5 97 32 97 32 97 32 97 32 97 32 112 27 122 24 132 20 142 17 1.0 30 ?10 30 ?10 30 ?10 30 ?10 30 ?10 45 ?15 55 ?18 65 ?22 75 ?25 0.9 25 ?24 25 ?24 25 ?24 25 ?24 25 ?24 40 ?29 50 ?32 60 ?36 70 ?39 0.8 17 ?41 17 ?41 17 ?41 17 ?41 17 ?41 32 ?46 42 ?49 52 ?53 61 ?56 0.7 5 ?64 5 ?64 5 ?64 5 ?64 5 ?64 20 ?69 30 ?72 40 ?75 50 ?79 0.6 ?7 ?93 ?7 ?93 ?7 ?93 ?7 ?93 ?7 ?93 8 ?98 18 ?102 28 ?105 38 ?108 0.5 ?28 ?135 ?28 ?135 ?28 ?135 ?28 ?135 ?28 ?135 ?13 ?140 ?3 ?143 7 ?147 17 ?150 0.4 ?78 ?198 ?78 ?198 ?78 ?198 ?78 ?198 ?78 ?198 ?63 ?203 ?53 ?206 ?43 ?210 ?33 ?213 table 35: single-ended dqs slew rate fully derated (dqs, dq at v ref ) at ddr2-667 reference points indicated in bold dq (v/ns) dqs single-ended slew rate derated (at v ref ) 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns 0.6 v/ns 0.4v/ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh 2.0 330 291 330 291 330 291 330 291 330 291 345 286 355 282 365 29 375 276 1.5 330 290 330 290 330 290 330 290 330 290 345 285 355 282 365 279 375 275 1.0 330 290 330 290 330 290 330 290 330 290 345 285 355 282 365 278 375 275 0.9 347 290 347 290 347 290 347 290 347 290 362 285 372 282 382 278 392 275 0.8 367 290 367 290 367 290 367 290 367 290 382 285 392 282 402 278 412 275 0.7 391 290 391 290 391 290 391 290 391 290 406 285 416 281 426 278 436 275 0.6 426 290 426 290 426 290 426 290 426 290 441 285 451 282 461 278 471 275 0.5 472 290 472 290 472 290 472 290 472 290 487 285 497 282 507 278 517 275 0.4 522 289 522 289 522 289 522 289 522 289 537 284 547 281 557 278 567 274 pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 61 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram input slew rate derating table 36: single-ended dqs slew rate fully derated (dqs, dq at v ref ) at ddr2-533 reference points indicated in bold dq (v/ns) dqs single-ended slew rate derated (at v ref ) 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns 0.6 v/ns 0.4v/ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh 2.0 355 341 355 341 355 341 355 341 355 341 370 336 380 332 390 329 400 326 1.5 364 340 364 340 364 340 364 340 364 340 379 335 389 332 399 329 409 325 1.0 380 340 380 340 380 340 380 340 380 340 395 335 405 332 415 328 425 325 0.9 402 340 402 340 402 340 402 340 402 340 417 335 427 332 437 328 447 325 0.8 429 340 429 340 429 340 429 340 429 340 444 335 454 332 464 328 474 325 0.7 463 340 463 340 463 340 463 340 463 340 478 335 488 331 498 328 508 325 0.6 510 340 510 340 510 340 510 340 510 340 525 335 535 332 545 328 555 325 0.5 572 340 572 340 572 340 572 340 572 340 587 335 597 332 607 328 617 325 0.4 647 339 647 339 647 339 647 339 647 339 662 334 672 331 682 328 692 324 table 37: single-ended dqs slew rate fully derated (dqs, dq at v ref ) at ddr2-400 reference points indicated in bold dq (v/ns) dqs single-ended slew rate derated (at v ref ) 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns 0.6 v/ns 0.4v/ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh 2.0 405 391 405 391 405 391 405 391 405 391 420 386 430 382 440 379 450 376 1.5 414 390 414 390 414 390 414 390 414 390 429 385 439 382 449 379 459 375 1.0 430 390 430 390 430 390 430 390 430 390 445 385 455 382 465 378 475 375 0.9 452 390 452 390 452 390 452 390 452 390 467 385 477 382 487 378 497 375 0.8 479 390 479 390 479 390 479 390 479 390 494 385 504 382 514 378 524 375 0.7 513 390 513 390 513 390 513 390 513 390 528 385 538 381 548 378 558 375 0.6 560 390 560 390 560 390 560 390 560 390 575 385 585 382 595 378 605 375 0.5 622 390 622 390 622 390 622 390 622 390 637 385 647 382 657 378 667 375 0.4 697 389 697 389 697 389 697 389 697 389 712 384 722 381 732 378 742 374 pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 62 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram input slew rate derating figure 29: nominal slew rate for t ds notes: 1. dqs, dqs# signals must be monotonic between v il ( dc ) max and v ih ( dc ) min. figure 30: tangent line for t ds notes: 1. dqs, dqs# signals must be monotonic between v il ( dc ) max and v ih ( dc ) min. v ref to a c re g ion v ref to a c re g ion s etup slew rate risin g si g nal s etup slew rate fallin g si g nal tf tr v ref ( d c ) - v il ( a c ) max tf = v ih ( a c ) min - v ref ( d c ) tr = nominal slew rate v ss dq s # 1 dq s 1 v dd q v ih ( d c ) min v ref ( d c ) v il ( a c ) max v il ( d c ) max v ih ( a c ) min t dh t d s nominal slew rate t dh t d s tf tr s etup slew rate risin g si g nal s etup slew rate fallin g si g nal tan g ent line (v ref [ d c ] - v il [ a c ] max) tf = tan g ent line (v ih [ a c ] min - v ref [ d c ]) tr = t dh t d s t dh t d s v ss dq s # 1 dq s 1 v dd q v ih ( d c ) min v ref ( d c ) v il ( a c ) max v il ( d c ) max v ih ( a c ) min nominal line tan g ent line nominal line tan g ent line v ref to a c re g ion v ref to a c re g ion pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 63 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram input slew rate derating figure 31: nominal slew rate for t dh notes: 1. dqs, dqs# signals must be monotonic between v il ( dc ) max and v ih ( dc ) min. figure 32: tangent line for t dh notes: 1. dqs, dqs# signals must be monotonic between v il ( dc ) max and v ih ( dc ) min. hol d slew rate fallin g si g nal hol d slew rate risin g si g nal v ref ( d c ) - v il ( d c ) max tr = v ih ( d c ) min - v ref ( d c ) tf = tr tf nominal slew rate d c to v ref re g ion t ih t i s t i s v ss dq s # 1 dq s 1 v dd q v ih ( d c ) min v ref ( d c ) v il ( a c ) max v il ( d c ) max v ih ( a c ) min d c to v ref re g ion nominal slew rate t ih tan g ent line d c to v ref re g ion t ih t i s t i s v ss v dd q v ih ( d c ) min v ref ( d c ) v il ( a c ) max v il ( d c ) max v ih ( a c ) min d c to v ref re g ion tan g ent line t ih dq s 1 dq s # 1 hol d slew rate fallin g si g nal tf tr tan g ent line (v ih [ d c ] min - v ref [ d c ]) tf = nominal line hol d slew rate risin g si g nal tan g ent line (v ref [ d c ] - v il [ d c ] max) tr = nominal line pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 64 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram input slew rate derating figure 33: ac input test signal waveform command/address balls figure 34: ac input test signal wavefor m for data with dqs, dqs# (differential) t is a logic levels v ref levels t ih a t is a t ih a t is b t ih b t is b t ih b ck# ck v dd q v ih ( ac ) min v ih ( dc ) min v ref ( dc ) v il ( dc ) min v il ( ac ) min v ss q v swing (max) dqs# dqs t ds a t dh a t ds a t dh a t ds b t dh b t ds b t dh b logic levels v ref levels v ref ( dc ) v il ( dc ) max v il ( ac ) max v ss q v ih ( dc ) min v ih ( ac ) min v dd q v swing (max) pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 65 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram input slew rate derating figure 35: ac input test signal waveform for data with dqs (single-ended) figure 36: ac input test signal waveform (differential) dqs v ref v ref ( dc ) v il ( dc ) max v il ( ac ) max v ss q v ih ( dc ) min v ih ( ac ) min v dd q v swing (max) logic levels v ref levels t ds a t dh a t ds a t dh a t ds b t dh b t ds b t dh b v tr v s win g v c p v dd q v ss q v ix c rossin g point pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 66 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram commands commands truth tables the following tables provide a quick reference of available ddr2 sdram commands, including cke power-down modes and bank-to-bank commands. notes: 1. all ddr2 sdram commands are defined by st ates of cs#, ras#, cas#, we#, and cke at the rising edge of the clock. 2. the state of odt does not affect the states de scribed in this table. the odt function is not available during self re fresh. see ?odt timing? on page 120 for details. 3. ?x? means ?h or l? (but a defined logic level) for valid i dd measurements. 4. ba2 is only applicable for densities > 1gb. 5. a n is the most significant address bit for a gi ven density and configur ation. some larger address bits may be ?don?t care? during colu mn addressing, depending on density and con- figuration. 6. bank addresses (ba) determine which bank is to be operated upon. ba during a load mode command selects which mode register is programmed. 7. self refresh exit is asynchronous. 8. burst reads or writes at bl = 4 cannot be terminated or interrupted. see figure 50 on page 90 and figure 62 on page 101 for other restrictions and details. 9. the power-down mode does not perform any refresh operations. the duration of power- down is limited by the refresh requiremen ts outlined in the ac parametric section. table 38: truth table ? ddr2 commands notes: 1?3 apply to the entire table function cke cs# ras# cas# we# ba2? ba0 a n ?a11 a10 a9?a0 notes previous cycle current cycle load mode h h l l l l ba op code 4, 6 refresh hhlllhxxxx self refresh entry hllllhxxxx self refresh exit lhhxxxxxxx4, 7 lhhh single bank precharge hhllhlbaxlx 6 all banks precharge hhllhlxxhx bank activate h h l l h h ba row address 4 write hhlhllbacolumn address l column address 4, 5, 6, 8 write with auto precharge hhlhllbacolumn address h column address 4, 5, 6, 8 read hhlhlhbacolumn address l column address 4, 5, 6, 8 read with auto precharge hhlhlhbacolumn address h column address 4, 5, 6, 8 no operation hxlhhhxxxx device deselect hxhxxxxxxx power-down entry hlhxxxxxxx 9 lhhh power-down exit lhhxxxxxxx9 lhhh pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 67 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram commands notes: 1. this table applies when cke n - 1 was high and cke n is high and after t xsnr has been met (if the previous state was self refresh). 2. this table is bank-specific, except where note d (the current state is for a specific bank and the commands shown are those allo wed to be issued to that bank when in that state). exceptions are covered in the notes below. 3. current state definitions: 4. the following states must not be interrupted by a command issu ed to the same bank. issue deselect or nop commands, or allowable commands to the other bank, on any clock edge occurring during these states. allowable commands to the ot her bank are determined by its current state and this table, and according to table 40 on page 69. table 39: truth table ? current state bank n ? command to bank n notes: 1?6 apply to the entire table current state cs# ras# cas# we# command/action notes any hxxx deselect (nop/continue previous operation) l hhh no operation (nop/continue previous operation) idle llhh activate (select and activate row) lllh refresh 7 llll load mode 7 row active lhlh read (select column and start read burst) 8 lhl l write (select column an d start write burst) 8 llhl precharge (deactivate row in bank or banks) 9 read (auto- precharge disabled) lhlh read (select column and start new read burst) 8 lhl l write (select column and start write burst) 8, 10 llhl precharge (start precharge) 8 write (auto- precharge disabled) lhlh read (select column and start read burst) 8 lhl l write (select column and start new write burst) 8 llhl precharge (start precharge) 9 idle: the bank has been precharged, t rp has been met, and any read burst is complete. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled and has not yet terminated. write: a write burst has been initiate d with auto precha rge disabled and has not yet terminated. precharge: starts with registration of a precharge command and ends when t rp is met. after t rp is met, the bank will be in the idle state. read with auto precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. after t rp is met, the bank will be in the idle state. row activate: starts with registration of an activate command and ends when t rcd is met. after t rcd is met, the bank will be in the row active state. write with auto precharge enabled: starts with registration of a wri te command with auto precharge enabled and ends when t rp has been met. after t rp is met, the bank will be in the idle state. pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 68 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram commands 5. the following states must not be interrupt ed by any executable command (deselect or nop commands must be applied on each pos itive clock edge during these states): 6. all states and sequences not sh own are illegal or reserved. 7. not bank-specific; requires that all bank s are idle and bursts are not in progress. 8. reads or writes listed in the command/action column includ e reads or writes with auto precharge enabled and reads or writ es with auto precharge disabled. 9. may or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging. 10. a write command may be applied after the comple tion of the read burst. refresh: starts with registration of a refresh command and ends when t rfc is met. after t rfc is met, the ddr2 sdram will be in the all banks idle state. accessing mode register: starts with registration of the load mode command and ends when t mrd has been met. after t mrd is met, the ddr2 sdram will be in the all banks idle state. precharge all: starts with registration of a precharge all command and ends when t rp is met. after t rp is met, all banks will be in the idle state. pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 69 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram commands notes: 1. this table applies when cke n - 1 was high and cke n is high and after t xsnr has been met (if the previous state was self refresh). 2. this table describes an altern ate bank operation, except where noted (the current state is for bank n and the commands shown are those allowed to be issued to bank m , assuming that bank m is in such a state that the given comma nd is allowable). exceptions are covered in the notes below. 3. current state definitions: table 40: truth table ? current state bank n ? command to bank m notes: 1?6 apply to the entire table current state cs# ras# cas# we# command/action notes any hxxx deselect (nop/continu e previous operation) lhhh no operation (nop/conti nue previous operation) idle xxxx any command otherwise allowed to bank m row active, active, or precharge llhh activate (select and activate row) lhlh read (select column and start read burst) 7 lhl l write (select column and start write burst) 7 llhl precharge read (auto precharge disabled) llhh activate (select and activate row) lhlh read (select column and start new read burst) 7 lhl l write (select column and start write burst) 7, 8 llhl precharge write (auto precharge disabled) llhh activate (select and activate row) lhlh read (select column and start read burst) 7, 9, 10 lhl l write (select column an d start new write burst) 7 llhl precharge read (with auto- precharge) llhh activate (select and activate row) lhlh read (select column and start new read burst 7 lhl l write (select column and start write burst) 7, 8 llhl precharge write (with auto- precharge) llhh activate (select and activate row) lhlh read (select column and start read burst) 7, 10 lhl l write (select column an d start new write burst) 7 llhl precharge idle: the bank has been precharged, t rp has been met, and any read burst is complete. row active: a row in the bank has been activated and t rcd has been met. no data bursts/ accesses and no register accesses are in progress. read: a read burst has been initiated with auto precharge disabled and has not yet terminated. write: a write burst has been initiated with auto precharge disabled and has not yet terminated. pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 70 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram commands the minimum delay from a read or write co mmand with auto precharge enabled to a command to a different bank is summarized in table 41: 4. refresh and load mode commands may only be issued when all banks are idle. 5. not used. 6. all states and sequences not sh own are illegal or reserved. 7. reads or writes listed in the command/actio n column include reads or writes with auto precharge enabled and reads or writ es with auto pr echarge disabled. 8. a write command may be applied afte r the completion of the read burst. 9. requires appropriate dm. 10. the number of clock cycles required to meet t wtr is either two or t wtr/ t ck, whichever is greater. deselect the deselect function (cs# high) prevents new commands from being executed by the ddr2 sdram. the ddr2 sdram is effectively deselected. operations already in progress are not affected. deselect is also referred to as command inhibit. no operation (nop) the no operation (nop) command is used to instruct the select ed ddr2 sdram to perform a nop (cs# is low; ras#, cas#, and we are high). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. read with auto precharge enabled/ write with auto precharge enabled: the read with auto precharge enab led or write with auto precharge enabled states can each be broken into two parts: the access period and the precharge period. for read with auto precharge, the precharge period is defined as if the same burst was execut ed with auto prec harge disabled and then followed with the earliest poss ible precharge command that still accesses all of the data in the burst. for write with au to precharge, the precharge period begins when t wr ends, with t wr measured as if auto precharge was disabled. the access pe riod starts with registration of the command and ends where th e precharge period (or t rp) begins. this device supports concurrent auto precharge such that when a read with auto precharge is enabled or a write with auto precharge is enabled, any command to other banks is allowed, as long as that command does not interrupt the read or write data transfer already in process. in either case, all other related limitations apply (contention between read data and write data must be avoided). table 41: minimum delay with auto precharge enabled from command (bank n ) to command (bank m ) minimum delay (with concurrent auto precharge) units write with auto precharge read or read with auto precharge (cl - 1) + (bl/2) + t wtr t ck write or write with auto precharge (bl/2) t ck precharge or activate 1 t ck read with auto precharge read or read with auto precharge (bl/2) t ck write or write with auto precharge (bl/2) + 2 t ck precharge or activate 1 t ck pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 71 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram commands load mode (lm) the mode registers are loaded via bank address and address inputs. the bank address balls determine which mode register will be programmed. see ?mode register (mr)? on page 76. the lm command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until t mrd is met. activate the activate command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the bank ad dress inputs determines the bank, and the address inputs select the row. this row re mains active (or open) for accesses until a precharge command is issued to that ba nk. a precharge command must be issued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the bank address inputs determine the bank, and the address provided on address inputs a0?a i (where a i is the most significant column address bit for a given configura- tion) selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. ddr2 sdram also supports the al feature, which allows a read or write command to be issued prior to t rcd (min) by delaying the actual registration of the read/write command to the internal device by al clock cycles. write the write command is used to initiate a burst write access to an active row. the value on the bank select inputs selects the bank , and the address provided on inputs a0?a i (where a i is the most significant column address bit for a given configuration) selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. ddr2 sdram also supports the al feature, which allows a read or write command to be issued prior to t rcd (min) by delaying the actual registration of the read/write command to the internal device by al clock cycles. input data appearing on the dq is written to the memory array subject to the dm input logic level appearing coincident with the data. if a given dm signal is registered low, the corresponding data will be written to memory ; if the dm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location (see figure 67 on page 106). precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row activation a specified time ( t rp) after the precharge command is issued, except in the case of concurrent auto precharge, where a read or write command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 72 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram commands not violate any other timing pa rameters. after a bank has been precharged, it is in the idle state and must be activa ted prior to any read or write commands being issued to that bank. a precharge command is allowed if there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. however, the precharge period will be determined by the last precharge command issued to the bank. refresh refresh is used during normal operatio n of the ddr2 sdram and is analogous to cas#-before-ras# (cbr) refresh. all banks must be in the idle mode prior to issuing a refresh command. this command is nonpersisten t, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits a ?don?t care? during a refresh command. self refresh the self refresh command can be used to re tain data in the ddr2 sdram, even if the rest of the system is powered down. when in the self refresh mode, the ddr2 sdram retains data without external clocki ng. all power supply inputs (including v ref ) must be maintained at valid levels upon entry/exit and during self refresh opera- tion. the self refresh command is initiated like a refresh command except cke is low. the dll is automatically disabled upon entering self refresh and is automatically enabled upon exiting self refresh. pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 73 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations operations initialization ddr2 sdrams must be powered up and initia lized in a predefined manner. operational procedures other than those specified may resu lt in undefined operation. figure 37 illus- trates and the notes outline the sequence of progression required for power-up and initialization. pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 74 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 37: ddr2 power-up and initialization notes: 1. applying power; if cke is maintained below 0.2 v dd q, outputs remain disabled. to guarantee r tt (odt resistance) is off, v ref must be valid and a low level must be applied to the odt ball (all other inputs may be undefined; i/os and outputs must be less than v dd q during voltage ramp time to avoid ddr2 sdram device latch-up). v tt is not applied directly to the device; however, t vtd should be 0 to avoid device latch-up. at least one of the following two sets of conditions (a or b) must be met to obtain a stable supply state (stable supply defined as v dd , v dd l, v dd q, v ref , and v tt are between their minimum and maximu m values as stated in table 14 on page 41): t vtd 1 c ke r tt power-up: v dd an d sta b le c lo c k ( c k, c k#) t = 200s (min) 3 hi g h-z dm 15 dq s 15 hi g h-z a dd ress 1 6 c k c k# t c l v tt 1 v ref v dd q c omman d nop 3 pre t0 ta0 don ? t c are t c l t c k v dd odt dq 15 hi g h-z t b 0 200 c y c les of c k are re q uire d b efore a read c omman d c an b e issue d mr with dll re s et t rf c lm 8 pre 9 lm 7 ref 10 ref 10 lm 11 t g 0 th0 ti0 tj0 mr without dll re s et emr with o c d d efault tk0 tl0 tm0 te0 tf0 emr(2) emr(3) t mrd lm 6 lm 5 a10 = 1 t rpa t c 0t d 0 ss tl_18 low level 2 vali d 14 vali d in d i c ates a break in time sc ale lm 12 emr with o c d exit lm 13 normal operation see note 10 c o d e c o d e a10 = 1 c o d e c o d e c o d e c o d e c o d e t mrd t mrd t mrd t mrd t rpa t rf c v dd l t mrd t mrd emr t = 400ns (min) 4 lv c mo s low level 2 pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 75 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations a. single power source: the v dd voltage ramp from 300mv to v dd (min) must take no longer than 200ms; during the v dd voltage ramp, |v dd - v dd q| 0.3v. once supply volt- age ramping is complete (when v dd q crosses v dd [min]), table 14 on page 41 specifica- tions apply. ? v dd , v dd l, and v dd q are driven from a sing le power converter output ? v tt is limited to 0.95v max ? v ref tracks v dd q/2; v ref must be within 0.3v with respect to v dd q/2 during sup- ply ramp time ? v dd q v ref at all times b. multiple power sources: v dd v dd l v dd q must be maintained du ring supply voltage ramping, for both ac and dc levels, un til supply voltage ramping completes (v dd q crosses v dd [min]). once supply voltage ramping is complete, table 14 on page 41 speci- fications apply. ? apply v dd and v dd l before or at the same time as v dd q; v dd /v dd l voltage ramp time must be 200ms from when v dd ramps from 300mv to v dd (min) ? apply v dd q before or at the same time as v tt ; the v dd q voltage ramp time from when v dd (min) is achieved to when v dd q (min) is achieved must be 500ms; while v dd is ramping, current can be supplied from v dd through the device to v dd q ? v ref must track v dd q/2; v ref must be within 0.3 v with respect to v dd q/2 during supply ramp time; v dd q v ref must be met at all times ? apply v tt ; the v tt voltage ramp time from when v dd q (min) is achieved to when v tt (min) is achieved must be no greater than 500ms 2. cke requires lvcmos input levels prior to sta te t0 to ensure dqs are high-z during device power-up prior to v ref being stable. after state t0, cke is required to have sstl_18 input levels. once cke transitions to a high level, it must stay high for the duration of the initial- ization sequence. 3. for a minimum of 200s after stable power and clock (ck, ck#), apply nop or deselect commands, then take cke high. 4. wait a minimum of 400ns then issue a precharge all command. 5. issue a load mode command to the emr(2). to issue an em r(2) command, provide low to ba0, and provide high to ba1; set register e7 to ?0? or ?1? to select appropriate self refresh rate; remaining emr(2) bits must be ?0? (see "extended mode register 2 (emr2)" on page 84 for all em r(2) requirements). 6. issue a load mode comma nd to the emr(3). to issue an emr(3) command, provide high to ba0 and ba1; remaining emr(3) bits must be ?0.? see ?extended mode register 3 (emr 3)? on page 85 for al l emr(3) requirements. 7. issue a load mode comma nd to the emr to enable dll. to issue a dll enable command, provide low to ba1 and a0; provide high to ba 0; bits e7, e8, and e9 can be set to ?0? or ?1;? micron recommends setting them to ?0; ? remaining emr bits must be ?0.? see ?extended mode register (emr)? on page 80 for all emr requirements. 8. issue a load mode command to the mr for dll reset. 200 cy cles of clock input is required to lock the dll. to issue a dll reset, provid e high to a8 and provide low to ba1 and ba0; cke must be high the entire time the dll is resetting; remaining mr bits must be ?0.? see ?mode register (mr)? on page 76 for all mr requirements. 9. issue precharge all command. 10. issue two or more refresh commands. 11. issue a load mode command to the mr with low to a8 to initialize device operation (that is, to program operating parameters with out resetting the dll). to access the mr, set ba0 and ba1 low; remaining mr bits must be set to desired settings. see ?mode register (mr)? on page 76 for all mr requirements. 12. issue a load mode comma nd to the emr to enable ocd defa ult by setting bits e7, e8, and e9 to ?1,? and then setting all other desired parameters. to access the emr, set ba0 low and ba1 high (see "extended mode register (emr)" on page 80 for all emr requirements. 13. issue a load mode command to the emr to enab le ocd exit by setting bits e7, e8, and e9 to ?0,? and then setting all other desired pa rameters. to access the extended mode regis- ters, emr, set ba0 low and ba 1 high for all emr requirements. pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 76 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations 14. the ddr2 sdram is now initialized and ready for normal operation 20 0 clock cycles after the dll reset at tf0. 15. dm represents dm for the x4, x8 configurations and udm, ldm for the x16 configuration; dqs represents dqs, dqs#, udqs, udqs#, ldqs , ldqs#, rdqs, rdqs# for the appropriate configuration (x4, x8, x16); dq represents dq 0?dq3 for x4, dq?dq7 for x8 and dq0?dq15 for x16. 16. a10 = precharge all, code = desired valu es for mode registers (bank addresses are required to be decoded). mode register (mr) the mode register is used to define the sp ecific mode of operation of the ddr2 sdram. this definition includes the selection of a burst length, burst type, cas latency, oper- ating mode, dll reset, write recovery, and power-down mode, as shown in figure 38 on page 77. contents of the mode register can be altered by reexecuting the load mode (lm) command. if the user chooses to modify only a subset of the mr variables, all variables must be programmed when the command is issued. the mr is programmed via the lm command and will retain the stored information until it is programmed again or until the de vice loses power (excep t for bit m8, which is self-clearing). reprogramming the mode register will not alter the contents of the memory array, provided it is performed correctly. the lm command can only be issued (or reissued) when all banks are in the precharged state (idle state) and no bursts are in prog ress. the controller must wait the specified time t mrd before initiating any subsequent oper ations such as an activate command. violating either of these requirements wi ll result in an unspecified operation. burst length burst length is defined by bits m0?m2, as shown in figure 38 on page 77. read and write accesses to the ddr2 sdram are burst-oriented, with the burst length being program- mable to either four or eight. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses fo r that burst take place within this block, meaning that the burst will wrap within the bl ock if a boundary is reached. the block is uniquely selected by a2?a i when bl = 4 and by a3?a i when bl = 8 (where a i is the most significant column address bit for a given configuration). the remaining (least signifi- cant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to both read and write bursts. pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 77 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 38: mode register (mr) definition notes: 1. m16 (ba2) is only applicable for densities > 1gb, reserved for future use, and must be pro- grammed to ?0.? 2. mode bits (m n ) with corresponding address balls (a n ) greater than m12 (a12) are reserved for future use and must be programmed to ?0.? 3. not all listed wr and cl options are supported in any indi vidual speed grade. burst type accesses within a given burst may be programmed to be either sequential or interleaved. the burst type is selected via bit m3, as shown in figure 38. the ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in table 42 on page 78. ddr2 sdram supports 4-bit burst mode and 8-bit burst mode only. for 8-bit burst mode, full interleaved address ordering is supported; however, sequential address ordering is nibble-based. burst length cas# bt pd a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 97 6 5 43 8 2 10 a10 a12 a11 ba0 ba1 10 11 12 n 0 0 14 burst length reserved reserved 4 8 reserved reserved reserved reserved m0 0 1 0 1 0 1 0 1 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 0 1 burst type sequential interleaved m3 cas latency (cl) reserved reserved reserved 3 4 5 6 7 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 0 1 mode normal test m7 15 dll tm 0 1 dll reset no yes m8 write recovery reserved 2 3 4 5 6 7 8 m9 0 1 0 1 0 1 0 1 m10 0 0 1 1 0 0 1 1 m11 0 0 0 0 1 1 1 1 wr a n 2 mr m14 0 1 0 1 mode register definition mode register (mr) extended mode register (emr) extended mode register (emr2) extended mode register (emr3) m15 0 0 1 1 m12 0 1 pd mode fast exit (normal) slow exit (low power) latency 16 ba2 1 pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 78 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations operating mode the normal operating mode is selected by issuing a command with bit m7 set to ?0,? and all other bits set to the desired values, as sh own in figure 38 on page 77. when bit m7 is ?1,? no other bits of the mode register are programmed. programming bit m7 to ?1? places the ddr2 sdram into a test mode that is only used by the manufacturer and should not be used. no operation or functional ity is guaranteed if m7 bit is ?1.? dll reset dll reset is defined by bit m8, as shown in figure 38 on page 77. programming bit m8 to ?1? will activate the dll reset function. bi t m8 is self-clearing, meaning it returns back to a value of ?0? after the dll reset function has been issued. anytime the dll reset function is used, 200 clock cycles must occur before a read command can be issued to allow time for the internal clock to be synchronized with the external clock. failing to wait for synchroniz ation to occur may result in a violation of the t ac or t dqsck parameters. write recovery write recovery (wr) time is defined by bits m9?m11, as shown in figure 38 on page 77. the wr register is used by the ddr2 sdram during write with auto precharge opera- tion. during write with auto precharge operation, the ddr2 sdram delays the internal auto precharge operation by wr cl ocks (programmed in bits m9?m11) from the last data burst. an example of write with auto precharge is shown in figure 66 on page 105. wr values of 2, 3, 4, 5, 6, 7, or 8 clocks ma y be used for programming bits m9?m11. the user is required to program the value of wr, which is calculated by dividing t wr (in nanoseconds) by t ck (in nanoseconds) and rounding up a noninteger value to the next integer; wr (cycles) = t wr (ns)/ t ck (ns). reserved states should not be used as an unknown operation or incompatibility with future versions may result. table 42: burst definition burst length starting column address (a2, a1, a0) order of accesses within a burst burst type = sequential burst type = interleaved 4 0 0 0, 1, 2, 3 0, 1, 2, 3 0 1 1, 2, 3, 0 1, 0, 3, 2 1 0 2, 3, 0, 1 2, 3, 0, 1 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 79 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations power-down mode active power-down (pd) mode is defined by bit m12, as shown in figure 38 on page 77. pd mode allows the user to determine the active power-down mode, which determines performance versus power savings. pd mode bit m12 does not apply to precharge pd mode. when bit m12 = 0, standard active pd mode, or ?fast-exit? active pd mode, is enabled. the t xard parameter is used for fast-exit active pd exit timing. the dll is expected to be enabled and running during this mode. when bit m12 = 1, a lower-power active pd mode, or ?slow-exit? active pd mode, is enabled. the t xards parameter is used for slow-exit active pd exit timing. the dll can be enabled but ?frozen? during active pd mode because the exit-to-read command timing is relaxed. the power difference expected between i dd 3p normal and i dd 3p low- power mode is defined in table 11 on page 27. cas latency (cl) the cas latency (cl) is defined by bits m4 ?m6, as shown in figure 38 on page 77. cl is the delay, in clock cycles, between the regi stration of a read command and the avail- ability of the first bit of outp ut data. the cl can be set to 3, 4, 5, 6, or 7 clocks, depending on the speed grade option being used. ddr2 sdram does not support any half-clock latencies. reserved states should not be used as an unknown operation otherwise incompatibility with future versions may result. ddr2 sdram also supports a feature called posted cas additive latency (al). this feature allows the read command to be issued prior to t rcd (min) by delaying the internal command to the ddr2 sdram by al clocks. the al feature is described in further detail in ?posted cas additive latency (al)? on page 83. examples of cl = 3 and cl = 4 are shown in figure 39 on page 80; both assume al = 0. if a read command is registered at clock edge n , and the cl is m clocks, the data will be available nominally coincident with clock edge n + m (this assumes al = 0). pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 80 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 39: cas latency (cl) notes: 1. bl = 4. 2. posted cas# additive latency (al) = 0. 3. shown with nominal t ac, t dqsck, and t dqsq. extended mode register (emr) the extended mode register controls functions beyond those controlled by the mode register; these additional functions are dll enable/disable, output drive strength, on- die termination (odt), posted al, off-chip driver impedance calibration (ocd), dqs# enable/disable, rdqs/rdqs# enable/disable, and output disable/enable. these func- tions are controlled via the bits shown in figure 40 on page 81. the emr is programmed via the lm command and will retain the stored information until it is programmed again or the device loses power. reprogramming the emr will not alter the contents of the memory array, provided it is performed correctly. the emr must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time t mrd before initiating any subsequent opera- tion. violating either of these requirements could result in an unspecified operation. do n + 3 do n + 2 do n + 1 ck ck# command dq dqs, dqs# cl = 3 (al = 0) read t0 t1 t2 don?t care transitioning data nop nop nop do n t3 t4 t5 nop nop t6 nop do n + 3 do n + 2 do n + 1 ck ck# command dq dqs, dqs# cl = 4 (al = 0) read t0 t1 t2 nop nop nop do n t3 t4 t5 nop nop t6 nop pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 81 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 40: extended mode register definition notes: 1. e16 (ba2) is only applicable for densities > 1gb, reserved for future use, and must be pro- grammed to ?0.? 2. mode bits (e n ) with corresponding address balls (a n ) greater than e12 (a12) are reserved for future use and must be programmed to ?0.? 3. not all listed al opti ons are supported in any individual speed grade. 4. as detailed on page 74, during initialization of the odc operation, all three bits must be set to ?1? for the ocd default state, then set to ?0? before initialization is finished. dll enable/disable the dll may be enabled or disabled by programming bit e0 during the lm command, as shown in figure 40. the dll must be enab led for normal operation. dll enable is required during power-up initialization an d upon returning to normal operation after having disabled the dll for the purpose of debugging or evaluation. enabling the dll should always be followed by resetting the dll using the lm command. the dll is automatically disabled when ente ring self refresh operation and is auto- matically reenabled and reset upon exit of self refresh operation. anytime the dll is enabled (and subsequently reset), 200 cloc k cycles must occur before a read command can be issued to allow time for the internal clock to synchronize with the external clock. failing to wait for synchronization to occur may result in a violation of the t ac or t dqsck parameters. dll posted cas# r tt out a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 n 0 14 e1 0 1 output drive strength full reduced posted cas# additive latency (al) 0 1 2 3 4 5 6 reserved e3 0 1 0 1 0 1 0 1 e4 0 0 1 1 0 0 1 1 e5 0 0 0 0 1 1 1 1 0 1 dll enable enable (normal) disable (test/debug) e0 15 e11 0 1 rdqs enable no yes ocd program a n 2 ods r tt dqs# e10 0 1 dqs# enable enable disable rdqs r tt (nominal) r tt disabled 75 150 50 e2 0 1 0 1 e6 0 0 1 1 0 1 outputs enabled disabled e12 0 1 0 1 mode register set mode register (mr) extended mode register (emr) extended mode register (emr2) extended mode register (emr3) e15 0 0 1 1 e14 mrs ba2 1 16 0 ocd operation ocd exit reserved reserved reserved enable ocd defaults e7 0 1 0 0 1 e8 0 0 1 0 1 e9 0 0 0 1 1 pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 82 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations anytime the dll is disabled and the device is operated below 25 mhz, any auto refresh command should be followed by a precharge all command. output drive strength the output drive strength is defined by bit e1, as shown in figure 40 on page 81. the normal drive strength for all outputs is spec ified to be sstl_18. programming bit e1 = 0 selects normal (full strength) drive strength for all outputs. selecting a reduced drive strength option (e1 = 1) will reduce all ou tputs to approximately 45 to 60 percent of the sstl_18 drive strength. this option is intend ed for the support of lighter load and/or point-to-point environments. dqs# enable/disable the dqs# ball is enabled by bit e10. when e10 = 0, dqs# is the complement of the differential data strobe pair dqs/dqs#. when disabled (e10 = 1), dqs is used in a single-ended mode and the dqs# ball is disabled. when disabled, dqs# should be left floating. this function is also used to enable/disable rdqs#. if rdqs is enabled (e11 = 1) and dqs# is enabled (e10 = 0), then both dqs# and rdqs# will be enabled. rdqs enable/disable the rdqs ball is enabled by bit e11, as shown in figure 40 on page 81. this feature is only applicable to the x8 configuration. when enabled (e11 = 1), rdqs is identical in function and timing to data strobe dqs during a read. during a write operation, rdqs is ignored by the ddr2 sdram. output enable/disable the output enable function is defined by bit e12, as shown in figure 40 on page 81. when enabled (e12 = 0), all outputs (dq, dqs, dqs#, rdqs, rdqs#) function normally. when disabled (e12 = 1), all outputs (dq, dq s, dqs#, rdqs, rdqs#) are disabled, thus removing output buffer current. the output disable feature is intended to be used during i dd characterization of read current. on-die termination (odt) odt effective resistance, r tt (eff), is defined by bits e2 and e6 of the emr, as shown in figure 40 on page 81. the odt feature is desi gned to improve signal integrity of the memory channel by allowing the ddr2 sdram controller to independently turn on/off odt for any or all devices. r tt effective resistance values of 50 , 75 , and 150 are selectable and apply to each dq, dqs/dqs#, rdqs/rdqs#, udqs/udqs#, ldqs/ ldqs#, dm, and udm/ldm signals. bits (e 6, e2) determine what odt resistance is enabled by turning on/off ?sw1,? ?sw2,? or ?sw3.? the odt effective resistance value is selected by enabling switch ?sw1,? wh ich enables all r1 values that are 150 each, enabling an effectiv e resistance of 75 (r tt 2 [ eff ] = r2/2). similarly, if ?sw2? is enabled, all r2 values that are 300 each, enable an effective odt resistance of 150 (r tt 2 [ eff ] = r2/2). switch ?sw3? enables r1 values of 100 , enabling effective resis- tance of 50 . reserved states should not be used, as an unknown operation or incom- patibility with future versions may result. the odt control ball is used to determine when r tt (eff) is turned on and off, assuming odt has been enable d via bits e2 and e6 of the emr. the odt feature and odt input ball are only used during active, active power-down (both fast-exit and slow- exit modes), and precharge power-down modes of operation. pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 83 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations odt must be turned off prior to entering self refresh mode. during power-up and initial- ization of the ddr2 sdram, odt should be disabled until the emr command is issued. this will enable the odt feature, at whic h point the odt ball will determine the r tt (eff) value. anytime the emr enables the odt function, odt may not be driven high until eight clocks after the emr has been enabled (see figure 82 on page 121 for odt timing diagrams). off-chip driver (ocd) impedance calibration the off-chip driver function is an opti onal ddr2 jedec feature not supported by micron and thereby must be set to the defa ult state. enabling ocd beyond the default settings will alter the i/o drive characterist ics and the timing and output i/o specifica- tions will no longer be valid (see "initialization" on page 73 for proper setting of ocd defaults). posted cas additive latency (al) posted cas additive latency (al) is supported to make the command and data bus effi- cient for sustainable bandwidths in ddr2 sdram. bits e3?e5 define the value of al, as shown in figure 40 on page 81. bits e3?e5 allow the user to program the ddr2 sdram with an al of 0, 1, 2, 3, 4, 5, or 6 clocks . reserved states should not be used as an unknown operation or incompatibility with future versions may result. in this operation, the ddr2 sdram allows a read or write command to be issued prior to t rcd (min) with the requirement that al t rcd (min). a typical application using this feature would set al = t rcd (min) - 1 t ck. the read or write command is held for the time of the al before it is issued internally to the ddr2 sdram device. rl is controlled by the sum of al and cl; rl = al + cl. write latency (wl) is equal to rl minus one clock; wl = al + cl - 1 t ck. an example of rl is shown in figure 41 on page 83. an example of a wl is shown in figure 42 on page 84. figure 41: read latency notes: 1. bl = 4. 2. shown with nominal t ac, t dqsck, and t dqsq. 3. rl = al + cl = 5. do n + 3 do n + 2 do n + 1 ck ck# command dq dqs, dqs# al = 2 active n t0 t1 t2 don?t care transitioning data read n nop nop do n t3 t4 t5 nop t6 nop t7 t8 nop nop cl = 3 rl = 5 t rcd (min) nop pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 84 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 42: write latency notes: 1. bl = 4. 2. cl = 3. 3. wl = al + cl - 1 = 4. extended mode register 2 (emr2) the extended mode register 2 (emr2) controls functions beyond those controlled by the mode register. currently all bits in emr2 ar e reserved, except for e7, which is used in commercial or high-temperature operations, as shown in figure 43. the emr2 is programmed via the lm command and will re tain the stored information until it is programmed again or until the device loses power. reprogramming the emr will not alter the contents of the memory array, provided it is performed correctly. bit e7 (a7) must be programmed as ?1? to provide a faster refresh rate on it and at devices if t c exceeds 85c. emr2 must be loaded when all banks are id le and no bursts are in progress, and the controller must wait the specified time t mrd before initiating any subsequent opera- tion. violating either of these requirements could result in an unspecified operation. figure 43: extended mode register 2 (emr2) definition notes: 1. e16 (ba2) is only applicable for densities > 1gb, reserved for future use, and must be pro- grammed to ?0.? 2. mode bits (e n ) with corresponding address balls (a n ) greater than e12 (a12) are reserved for future use and must be programmed to ?0.? ck ck# command dq dqs, dqs# active n t0 t1 t2 don?t care transitioning data nop nop t3 t4 t5 nop t6 nop di n + 3 di n + 2 di n + 1 wl = al + cl - 1 = 4 t7 nop di n t rcd (min) nop al = 2 cl - 1 = 2 write n a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 n 0 14 15 a n 2 e14 0 1 0 1 mode register set mode register (mr) extended mode register (emr) extended mode register (emr2) extended mode register (emr3) e15 0 0 1 1 mrs 00 000 srt0 000 0 0 0 ba2 1 16 0 e7 0 1 srt enable 1x refresh rate (0c to 85c) 2x refresh rate (>85c) pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 85 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations extended mode regi ster 3 (emr 3) the extended mode register 3 (emr3) controls functions beyond those controlled by the mode register. currently all bits in emr3 are reserved, as shown in figure 44 on page 85. the emr3 is programmed via the lm command and will retain the stored information until it is programmed again or until the device loses power. reprogramming the emr will not alter the contents of the memory array, provided it is performed correctly. emr3 must be loaded when all banks are id le and no bursts are in progress, and the controller must wait the specified time t mrd before initiating any subsequent opera- tion. violating either of these requirements could result in an unspecified operation. figure 44: extended mode register 3 (emr3) definition notes: 1. e16 (ba2) is only applicable for densities > 1gb, is reserved for future use, and must be pro- grammed to ?0.? 2. mode bits (e n ) with corresponding address balls (a n ) greater than e12 (a12) are reserved for future use and must be programmed to ?0.? activate before any read or write commands can be issued to a bank within the ddr2 sdram, a row in that bank must be opened (activated), even when additive latency is used. this is accomplished via the activate command, which selects both the bank and the row to be activated. after a row is opened with an activate command, a read or write command may be issued to that row subject to the t rcd specification. t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the activate command on which a read or write command can be entered. the same procedure is used to convert other specification limits from time units to clock cycles. for example, a t rcd (min) specification of 20ns with a 266 mhz clock ( t ck = 3.75ns) results in 5.3 clocks, rounded up to 6. this is shown in figure 45 on page 86, which covers any case where 5 < t rcd (min)/ t ck 6. figure 45 also shows the case for t rrd where 2 < t rrd (min)/ t ck 3. e14 0 1 0 1 mode register set mode register (mr) extended mode register (emr) extended mode register (emr2) extended mode register (emr3) e15 0 0 1 1 a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus a10 a12 a11 ba0 ba1 a n 2 mrs 0 0 00 00 000 0 0 0 ba2 1 0 0 0 976543 8210 10 11 12 n 14 15 16 pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 86 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 45: example: meeting t rrd (min) and t rcd (min) a subsequent activate command to a different row in the same bank can only be issued after the previous active row has been closed (precharged). the minimum time interval between successive activate commands to the same bank is defined by t rc. a subsequent activate command to another ba nk can be issued whil e the first bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval between successive activate commands to different banks is defined by t rrd. ddr2 devices with 8-banks (1gb or lar ger) have an additional requirement: t faw. this requires no more than four activate commands may be issued in any given t faw (min) period, as shown in figure 46. figure 46: multi-bank activate restriction notes: 1. ddr2-533 (-37e, x4 or x8), t ck = 3.75ns, bl = 4, al = 3, cl = 4, t rrd (min) = 7.5ns, t faw (min) = 37.5ns. c omman d don ? t c are t1 t0 t2 t3 t4 t5 t 6 t7 t rrd t rrd row row c ol bank x bank y row bank z bank y nop a c t nop nop a c t nop nop rd/wr t r c d c k# a dd ress bank a dd ress c k t8 t9 nop nop command don?t care t1 t0 t2 t3 t4 t5 t6 t7 t rrd (min) row row read act act nop bank address ck# address ck t8 t9 col bank a act read read read act nop row col row col col bank c bank b bank d bank c bank e act row t10 bank d bank b bank a t faw (min) pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 87 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations read read bursts are initiated with a read command. the starting column and bank addresses are provided with the read command, and auto precharge is either enabled or disabled for that burst access. if auto pr echarge is enabled, the row being accessed is automatically precharged at the completion of the burst. if auto precharge is disabled, the row will be left open after the completion of the burst. during read bursts, the valid data-out elem ent from the starting column address will be available read latency (rl) clocks later. rl is defined as the sum of al and cl: rl = al + cl. the value for al and cl are programmable via the mr and emr commands, respectively. each subsequent data -out element will be valid nominally at the next positive or negative clock edge (at the next crossing of ck and ck#). figure 47 on page 88 shows examples of rl based on different al and cl settings. dqs/dqs# is driven by the ddr2 sdram alon g with output data. the initial low state on dqs and the high state on dqs# are known as the read preamble ( t rpre). the low state on dqs and the high state on dqs# coin cident with the last data-out element are known as the read postamble ( t rpst). upon completion of a burst, assuming no ot her commands have been initiated, the dq will go high-z. a detailed explanation of t dqsq (valid data-out skew), t qh (data-out window hold), and the valid data window are depicted in figure 56 on page 95 and figure 57 on page 96. a detailed explanation of t dqsck (dqs transition skew to ck) and t ac (data-out transition skew to ck) is shown in figure 58 on page 97. data from any read burst may be concatenated with data from a subsequent read command to provide a continuous flow of data. the first data element from the new burst follows the last element of a complete d burst. the new read command should be issued x cycles after the first read command, where x equals bl/2 cycles (see figure 48 on page 89). nonconsecutive read data is illustrated in figure 49 on page 90. full-speed random read accesses within a page (or pages) can be performed. ddr2 sdram supports the use of concurrent auto precharge timing (see table 43 on page 93). ddr2 sdram does not allow interrupting or truncating of any read burst using bl = 4 operations. once the bl = 4 read command is registered, it must be allowed to complete the entire read burst. however, a read (with auto precharge disabled) using bl = 8 operation may be interrupted and truncated only by another read burst as long as the interruption occurs on a 4-bit boundary due to the 4 n prefetch architecture of ddr2 sdram. as shown in figure 50 on page 90, read burst bl = 8 operations may not be interrupted or truncated with any ot her command except another read command. data from any read burst must be completed before a subsequent write burst is allowed. an example of a read burst followed by a write burst is shown in figure 51 on page 91. the t dqss (nom) case is shown ( t dqss [min] and t dqss [max] are defined in figure 59 on page 99.) pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 88 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 47: read latency notes: 1. do n = data-out from column n . 2. bl = 4. 3. three subsequent elements of data-out ap pear in the programmed order following do n . 4. shown with nominal t ac, t dqsck, and t dqsq. read nop nop nop nop nop bank a , col n ck ck# command address dq dqs, dqs# do n do n t0 t1 t2 t3 t4n t5n t4 t5 ck ck# command read nop nop nop nop nop address bank a, col n rl = 3 (al = 0, cl = 3) dq dqs, dqs# do n t0 t1 t2 t3 t3n t4n t4 t5 ck ck# command read nop nop nop nop nop address bank a, col n rl = 4 (al = 0, cl = 4) dq dqs, dqs# t0 t1 t2 t3 t3n t4n t4 t5 al = 1 cl = 3 rl = 4 (al = 1 + cl = 3) don?t care transitioning data pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 89 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 48: consecutive read bursts notes: 1. do n (or b ) = data-out from column n (or column b ). 2. bl = 4. 3. three subsequent elements of data-out ap pear in the programmed order following do n . 4. three subsequent elements of data-out ap pear in the programmed order following do b . 5. shown with nominal t ac, t dqsck, and t dqsq. 6. example applies only when read co mmands are issued to same device. ck ck# command read nop read nop nop nop nop address bank, col n bank, col b command read nop read nop nop nop address bank, col n bank, col b rl = 3 ck ck# dq dqs, dqs# rl = 4 dq dqs, dqs# do n do b do n do b t0 t1 t2 t3 t3n t4n t4 t5 t6 t5n t6n t0 t1 t2 t3 t2n nop t3n t4n t4 t5 t6 t5n t6n don?t care transitioning data t ccd t ccd pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 90 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 49: nonconsecutive read bursts notes: 1. do n (or b ) = data-out from column n (or column b ). 2. bl = 4. 3. three subsequent elements of data-out ap pear in the programmed order following do n . 4. three subsequent elements of data-out ap pear in the programmed order following do b . 5. shown with nominal t ac, t dqsck, and t dqsq. 6. example applies when read co mmands are issued to differen t devices or nonconsecutive reads. figure 50: read interrupted by read notes: 1. bl = 8 required; auto precha rge must be disabl ed (a10 = low). 2. nop or command inhibit commands are valid. precharge command cann ot be issued to banks used for reads at t0 and t2. 3. interrupting read command mu st be issued exactly 2 t ck from previous read. 4. read command can be issued to any valid bank and row ad dress (read command at t0 and t2 can be either same ba nk or different bank). 5. auto precharge can be either enabled (a10 = high) or disabled (a10 = low) by the inter- rupting read command. 6. example shown uses al = 0; cl = 3, bl = 8, shown with nominal t ac, t dqsck, and t dqsq. command read nop nop nop nop nop nop nop read t0 t1 t2 t3 t3n t4 t5 t7 t8 t6 t4n t6n t7n ck ck# t5 t7 t8 t5n t6 t4n t7n command nop nop nop nop read nop nop nop read t0 t1 t2 t3 t4 dq do n do b don?t care transitioning data address bank, col n bank, col b address bank, col n bank, col b ck ck# cl = 4 cl = 3 dq do n do b dqs, dqs# dqs, dqs# t0 t1 t2 don?t care transitioning data t3 t4 t5 t6 command read 1 nop 2 nop 2 valid valid valid read 3 valid valid valid t7 t8 t9 ck ck# cl = 3 (al = 0) t ccd address valid 4 valid 4 cl = 3 (al = 0) dq do do do do do do do do do do do a10 dqs, dqs# valid 5 do pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 91 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 51: read-to-write notes: 1. bl = 4; cl = 3; al = 2. 2. shown with nominal t ac, t dqsck, and t dqsq. read with precharge a read burst may be followed by a precha rge command to the same bank, provided auto precharge is not activated. th e minimum read-to-precharge command spacing to the same bank has two requirements that must be satisfied: al + bl/2 clocks and t rtp. t rtp is the minimum time from the rising clock edge that initiates the last 4-bit prefetch of a read command to the precharg e command. for bl = 4, this is the time from the actual read (al after the read command) to precharge command. for bl = 8, this is the time from al + 2 ck after the read-to-precharge command. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. however, part of the row precharge time is hidden during the access of the last data elements. examples of read-to-precharge for bl = 4 are shown in figure 52 and in figure 53 on page 92 for bl = 8. the delay from read-to- precharge period to the same bank is al + bl/2 - 2ck + max ( t rtp/ t ck or 2 ck) where max means the larger of the two. figure 52: read-to-precharge ? bl = 4 notes: 1. rl = 4 (al = 1, cl = 3); bl = 4. 2. t rtp 2 clocks. 3. shown with nominal t ac, t dqsck, and t dqsq. c k c k# t0 t1 t2 don ? t c are transitionin g data t3 t4 t5 t 6 t7 t8 t9 t10 t11 al = 2 c l = 3 rl = 5 c omman d a c t n nop nop nop nop nop nop nop nop read n write dq s , dq s # dq do n do n + 1 do n + 2 do n + 3 di n di n + 1 di n + 2 di n + 3 t r c d = 3 wl = rl - 1 = 4 nop ck ck# t0 t1 t2 don?t care transitioning data t3 t4 t5 t6 t7 address bank a bank a bank a t ras (min) t rtp (min) al + bl/2 - 2ck + max ( t rtp/ t ck or 2ck) command read nop pre act nop nop nop nop 4-bit prefetch dq do do do do a10 valid valid cl = 3 al = 1 dqs, dqs# t rc (min) t rp (min) pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 92 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 53: read-to-precharge ? bl = 8 notes: 1. rl = 4 (al = 1, cl = 3); bl = 8. 2. t rtp 2 clocks. 3. shown with nominal t ac, t dqsck, and t dqsq. read with auto precharge if a10 is high when a read command is issued, the read with auto precharge function is engaged. the ddr2 sdram starts an auto precharge operation on the rising clock edge that is al + (bl/2) cycles later th an the read with auto precharge command provided t ras (min) and t rtp are satisfied. if t ras (min) is not satisfied at this rising clock edge, the start point of the auto precharge operation will be delayed until t ras (min) is satisfied. if t rtp (min) is not satisfied at this ri sing clock edge, the start point of the auto precharge operation will be delayed until t rtp (min) is satisfied. when the internal precharge is pushed out by t rtp, t rp starts at the point where the internal precharge happens (not at the next rising clock edge after this event). when bl = 4, the minimum time from read with auto precharge to the next activate command is al + ( t rtp + t rp)/ t ck. when bl = 8, the minimum time from read with auto precharge to the next activa te command is al + 2 clocks + ( t rtp + t rp)/ t ck. the term ( t rtp + t rp)/ t ck is always rounded up to the next integer. a general purpose equa- tion can also be used: al + bl/2 - 2ck + ( t rtp + t rp)/ t ck. in any event, the internal precharge does not start earlier than two clocks after the last 4-bit prefetch. read with auto precharge command may be a pplied to one bank while another bank is operational. this is referred to as concur rent auto precharge operation, as noted in table 43 on page 93. examples of read with precharge and read with auto precharge with applicable timing requirements are shown in figure 54 on page 93 and figure 55 on page 94, respectively. ck ck# t0 t1 t2 don?t care transitioning data t3 t4 t5 t6 t7 t8 cl = 3 al = 1 dqs, dqs# first 4-bit prefetch second 4-bit prefetch address bank a bank a bank a t ras (min) valid valid al + bl/2 - 2ck + max ( t rtp/ t ck or 2ck) dq do do do do do do do command read nop nop nop nop nop nop act pre a10 t rp (min) t rtp (min) t rc (min) do pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 93 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 54: bank read ? without auto precharge notes: 1. nop commands are shown for ease of illus tration; other commands may be valid at these times. 2. bl = 4 and al = 0 in the case shown. 3. the precharge command can only be applied at t6 if t ras (min) is met. 4. read-to-precharge = al + bl/2 -2ck + max ( t rtp/ t ck or 2ck). 5. disable auto precharge. 6. ?don?t care? if a10 is high at t5. 7. i/o balls, when entering or exiting high-z, are not referenced to a spec ific voltage level, but to when the device begins to drive or no longer drives, respectively. 8. do n = data-out from column n ; subsequent elements are applied in the programmed order. table 43: read using concurrent auto precharge from command (bank n ) to command (bank m ) minimum delay (with concurrent auto precharge) units read with auto precharge read or read with auto precharge bl/2 t ck write or write with auto precharge (bl/2) + 2 t ck precharge or activate 1 t ck ck ck# cke a10 bank address t ck t ch t cl ra t rcd t ras 3 cl = 3 dm t0 t1 t2 t3 t4 t5 t7n t8n t6 t7 t8 dq 8 dqs, dqs# case 1: t ac (min) and t dqsck (min) case 2: t ac (max) and t dqsck (max) dq 8 dqs, dqs# t rpre t dqsck (min) t lz (min) t lz (max) t ac (min) t lz (min) do n t hz (max) t ac (max) t lz (min) do n nop 1 nop 1 command act ra col n pre 3 bank x ra ra bank x bank x 6 7 7 77 act bank x nop 1 nop 1 nop 1 nop 1 t hz (min) one bank all banks don?t care transitioning data read 2 address 5 t rtp 4 t rpst t dqsck (max) t9 t rp t rc t rpre t rpst pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 94 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 55: bank read ? with auto precharge notes: 1. nop commands are shown for ease of illus tration; other commands may be valid at these times. 2. bl = 4, rl = 4 (al = 1, cl = 3) in the case shown. 3. the ddr2 sdram internally dela ys auto precha rge until both t ras (min) and t rtp (min) have been satisfied. 4. enable auto precharge. 5. i/o balls, when entering or exiting high-z, ar e not referenced to a sp ecific voltage level, but to when the device begins to driv e or no longer drives, respectively. 6. do n = data-out from column n ; subsequent elements are applied in the programmed order. 4-bit prefetch ck ck# cke a10 bank address t ck t ch t cl ra t rcd t ras t rc t rp cl = 3 dm t0 t1 t2 t3 t4 t5 t7n t8n t6 t7 t8 dq 6 dqs, dqs# case 1: t ac (min) and t dqsck (min) case 2: t ac (max) and t dqsck (max) dq 6 dqs, dqs# t rpre t rpre t rpst t rpst t dqsck (min) t dqsck (max) t lz (min) t lz (max) t ac (min) t lz (min) t hz (max) t ac (max) t lz (max) do n nop 1 nop 1 command 1 act ra col n bank x ra ra bank x act bank x nop 1 nop 1 nop 1 nop 1 nop 1 t hz (min) don?t care transitioning data read 2,3 address al = 1 t rtp internal precharge 4 5 5 55 do n pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 95 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 56: x4, x8 data output timing ? t dqsq, t qh, and data valid window notes: 1. t hp is the lesser of t cl or t ch clock transitions collectively when a bank is active. 2. t dqsq is derived at each dqs clock edge, is not cumulative over time, begins with dqs transitions, and ends with the last valid transition of dq. 3. dq transitioning after the dqs transition defines the t dqsq window. dqs transitions at t2 and at t2n are ?early dqs,? at t3 are ?n ominal dqs,? and at t3n are ?late dqs.? 4. dq0, dq1, dq2, dq3 fo r x4 or dq0?dq7 for x8. 5. t qh is derived from t hp: t qh = t hp - t qhs. 6. the data valid window is derived for each dqs transition and is defined as t qh - t dqsq. dq (last data valid) dq 4 dq 4 dq 4 dq 4 dq 4 dq 4 dqs, dqs# 3 dq (last data valid) dq (first data no longer valid) dq (first data no longer valid) all dqs and dqs collectively 6 earliest signal transition latest signal transition t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n ck ck# t1 t2 t3 t4 t2n t3n t qh 5 t hp 1 t hp 1t hp 1 t qh 5 t qhs t qh 5 t hp 1 t hp 1 t hp 1 t qh 5 t dqsq 2t dqsq 2t dqsq 2t dqsq 2 data valid window data valid window data valid window data valid window t qhs t qhs t qhs pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 96 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 57: x16 data output timing ? t dqsq, t qh, and data valid window notes: 1. t hp is the lesser of t cl or t ch clock transitions collectively when a bank is active. 2. t dqsq is derived at each dqs clock edge, is not cumulative over time, begins with dqs transitions, and ends with the last valid transition of dq. 3. dq transitioning after the dqs transitions define the t dqsq window. ldqs defines the lower byte, and udqs defines the upper byte. 4. dq0, dq1, dq2, dq3, dq4, dq5, dq 6, or dq7. 5. t qh is derived from t hp: t qh = t hp - t qhs. 6. the data valid window is derive d for each dqs transition and is t qh - t dqsq. 7. dq8, dq9, dq10, d11, dq12, dq13, dq14, or dq15. dq (last d ata vali d ) 4 dq 4 dq 4 dq 4 dq 4 dq 4 dq 4 ldq s , ld s q# 3 dq (last d ata vali d ) 4 dq (first d ata no lon g er vali d ) 4 dq (first d ata no lon g er vali d ) 4 dq0?dq7 an d ldq s c olle c tively 6 t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n c k c k# t1 t2 t3 t4 t2n t3n t qh 5 t qh 5 t dq s q 2 t dq s q 2 t dq s q 2 t dq s q 2 data vali d win d ow data vali d win d ow dq (last d ata vali d ) 7 dq 7 dq 7 dq 7 dq 7 dq 7 dq 7 udq s , udq s # 3 dq (last d ata vali d ) 7 dq (first d ata no lon g er vali d ) 7 dq (first d ata no lon g er vali d ) 7 dq8?dq15 an d udq s c olle c tively 6 t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n t qh 5 t qh 5 t qh 5 t qh 5 t dq s q 2 t dq s q 2 t dq s q 2 t hp 1 t hp 1 t hp 1 t hp 1 t hp 1 t hp 1 t qh 5 data vali d win d ow data vali d win d ow data vali d win d ow data vali d win d ow data vali d win d ow upper b yte lower b yte data vali d win d ow t qh s t qh s t qh s t qh s t qh s t qh s t qh s t qh s t qh 5 t dq s q 2 pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 97 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 58: data output timing ? t ac and t dqsck notes: 1. read command with cl = 3, al = 0 issued at t0. 2. t dqsck is the dqs output window relative to ck and is the long-term component of dqs skew. 3. dq transitioning after dqs transitions define t dqsq window. 4. all dq must transition by t dqsq after dqs transitions, regardless of t ac. 5. t ac is the dq output window relative to ck and is the ?long term? component of dq skew. 6. t lz (min) and t ac (min) are the first valid signal transitions. 7. t hz (max) and t ac (max) are the latest va lid signal transitions. 8. i/o balls, when entering or exiting high-z, are not referenced to a spec ific voltage level, but to when the device begins to drive or no longer drives, respectively. write write bursts are initiated with a write command. ddr2 sdram uses wl equal to rl minus one clock cycle (wl = rl - 1ck) (see "read" on page 71). the starting column and bank addresses are prov ided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. note: for the write commands used in the following illustrations, auto precharge is dis- abled. during write bursts, the first valid data-in element will be registered on the first rising edge of dqs following the write command, and subsequent data elements will be registered on successive edges of dqs. the low state on dqs between the write command and the first rising edge is known as the write preamble; the low state on dqs following the last data-in element is known as the write postamble. the time between the write command and the first rising dqs edge is wl t dqss. subsequent dqs positive rising edges are timed, relative to the associated clock edge, as t dqss. t dqss is specified with a relatively wide range (25 percent of one clock cycle). all of the write diagrams show the nominal case, and where the two extreme cases ( t dqss [min] and t dqss [max]) might not be intuitive, they have also been included. figure 59 on page 99 shows the no minal case and the extremes of t dqss for bl = 4. upon completion of a burst, assuming no other commands have been initiated, the dq will remain high-z and any additional input data will be ignored. ck ck# dqs, dqs# or ldqs, ldqs#/udq, udqs# 3 t0 1 t1 t2 t3 t3n t4 t4n t5 t5n t6 t6n t7 t rpst t dqsck 2 (min) t dqsck 2 (max) dq (last data valid) dq (first data valid) all dqs collectively 4 t ac 5 (min) t ac 5 (max) t lz (min) t hz (max) t3n t3n t4n t5n t6n t5 t3 t4 t5 t6 t hz (max) t lz (min) t rpre t3 t4 t4n t5 t5n t6 t6n t6n t6 t5n t4n t4 t3n t3 pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 98 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations data for any write burst may be concatenat ed with a subsequent write command to provide continuous flow of input data. the first data element from the new burst is applied after the last element of a comple ted burst. the new write command should be issued x cycles after the first write command, where x equals bl/2. figure 60 on page 100 provides examples of co ncatenated bursts of bl = 4 and how full- speed random write accesses within a page or pages can be performed. an example of nonconsecutive writes is shown in fi gure 61 on page 100. ddr2 sdram supports concurrent auto precharge options, as shown in table 44 on page 98. ddr2 sdram does not allow interrupting or truncating any write burst using bl = 4 operation. once the bl = 4 write command is registered, it must be allowed to complete the entire write burst cycle. howe ver, a write bl = 8 operation (with auto precharge disabled) might be interrupted and truncated only by another write burst as long as the interruption occurs on a 4-bit boundary due to the 4 n -prefetch architecture of ddr2 sdram. write burst bl = 8 operations may not be interrupted or truncated with any command except another write command, as shown in figure 62 on page 101. data for any write burst may be followed by a subsequent read command. to follow a write, t wtr should be met, as shown in figure 63 on page 102. the number of clock cycles required to meet t wtr is either 2 or t wtr/ t ck, whichever is greater. data for any write burst may be followed by a subsequent precharge command. t wr must be met, as shown in figure 64 on page 103. t wr starts at the end of the data burst, regard- less of the data mask condition. table 44: write using concurrent auto precharge from command (bank n ) to c o m m a n d (bank m ) minimum delay (with concurrent auto precharge) units write with auto precharge read or read with auto precharge (cl - 1) + (bl/2) + t wtr t ck write or writ e with auto precharge (bl/2) t ck precharge or activate 1 t ck pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 99 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 59: write burst notes: 1. subsequent rising dqs signal s must align to the clock within t dqss. 2. di b = data-in for column b . 3. three subsequent elements of data-in are applied in the programmed order following di b . 4. shown with bl = 4, al = 0, cl = 3; thus, wl = 2. 5. a10 is low with the write comm and (auto precharge is disabled). dqs, dqs# t dqss (max) t dqss (nom) t dqss (min) dm dq ck ck# command write nop nop address bank a , col b nop nop t0 t1 t2 t3 t2n t4 t3n dqs, dqs# 5 dm dq dqs, dqs# dm dq di b don?t care transitioning data t dqss 5 wl t dqss wl - t dqss t dqss 5 wl + t dqss di b di b pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 100 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 60: consecutive write-to-write notes: 1. subsequent rising dqs signal s must align to the clock within t dqss. 2. di b , etc. = data-i n for column b , etc. 3. three subsequent elements of data-in are applied in the programmed order following di b . 4. three subsequent elements of data-in are applied in the programmed order following di n . 5. shown with bl = 4, al = 0, cl = 3; thus, wl = 2. 6. each write command may be to any bank. figure 61: nonconsecutive write-to-write notes: 1. subsequent rising dqs signal s must align to the clock within t dqss. 2. di b (or n ), etc. = data-in for column b (or column n ). 3. three subsequent elements of data-in are applied in the programmed order following di b . 4. three subsequent elements of data-in are applied in the programmed order following di n . 5. shown with bl = 4, al = 0, cl = 3; thus, wl = 2. 6. each write command may be to any bank. ck ck# command write nop write nop nop nop address bank, col b nop bank, col n t0 t1 t2 t3 t2n t4 t5 t4n t6 t5n t3n t1n dq dqs, dqs# dm di n di b don?t care transitioning data wl t dqss t dqss (nom) wl = 2 t ccd wl = 2 1 1 1 ck ck# command write nop nop nop nop nop address bank, col b write bank, col n t0 t1 t2 t3 t2n t4 t5 t4n t3n t5n t6 t6n dq dqs, dqs# dm di b t dqss (nom) wl t dqss don?t care transitioning data wl = 2 wl = 2 1 11 di n pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 101 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 62: write interrupted by write notes: 1. bl = 8 required and auto precharge must be disabled (a10 = low). 2. the nop or command inhibit commands are valid. th e precharge command cannot be issued to banks used for writes at t0 and t2. 3. the interrupti ng write command must be issued exactly 2 t ck from previous write. 4. the earliest write-to-precharge timi ng for write at t0 is wl + bl/2 + t wr where t wr starts with t7 and not t5 (because bl = 8 from mr and not the truncated length). 5. the write command can be issu ed to any valid bank and row address (write command at t0 and t2 can be either same bank or different bank). 6. auto precharge can be either enabled (a10 = high) or disabled (a10 = low) by the inter- rupting write command. 7. subsequent rising dq s signals must align to the clock within t dqss. 8. example shown uses al = 0; cl = 4, bl = 8. ck ck# command dq dqs, dqs# wl = 3 t0 t1 t2 don?t care transitioning data t3 t4 t5 t6 t7 t8 t9 wl = 3 2-clock requirement address a10 valid 4 valid 4 valid 4 nop 2 nop 2 nop 2 nop 2 nop 2 7 7777 di a + 1 di a + 3 di a + 2 di b + 1 di b + 2 di b + 3 di b + 4 di b + 5 di b + 6 di b + 7 di b di a valid 6 valid 5 valid 5 write 1 a write 3 b pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 102 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 63: write-to-read notes: 1. t wtr is required for any read following a write to the same device, but it is not required between module ranks. 2. subsequent rising dq s signals must align to the clock within t dqss. 3. di b = data-in for column b ; do n = data-out from column n . 4. bl = 4, al = 0, cl = 3; thus, wl = 2. 5. one subsequent element of data-in is ap plied in the programme d order following di b . 6. t wtr is referenced from the first positive ck edge after the last data-in pair. 7. a10 is low with the write comm and (auto precharge is disabled). 8. the number of clock cycles required to meet t wtr is either 2 or t wtr/ t ck, whichever is greater. t dqss (nom) ck ck# command write nop nop nop nop nop nop nop address bank a , col b bank a , col n read t0 t1 t2 t3 t2n t4 t5 t9n t3n t6 t7 t8 t9 t wtr 1 cl = 3 cl = 3 cl = 3 dq dqs, dqs# dm t dqss (min) dq dqs, dqs# dm t dqss (max) dq dqs, dqs# dm di b di di don?t care transitioning data wl t dqss wl - t dqss wl + t dqss nop di 2 2 2 di b di b pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 103 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 64: write-to-precharge notes: 1. subsequent rising dqs signal s must align to the clock within t dqss. 2. di b = data-in for column b . 3. three subsequent elements of data-in are ap plied in the programmed order following di b . 4. bl = 4, cl = 3, al = 0; thus, wl = 2. 5. t wr is referenced from th e first positive ck edge af ter the last data-in pair. 6. the precharge and write commands are to the same bank. however, the precharge and write commands may be to different banks, in which case t wr is not required and the precharge command coul d be applied earlier. 7. a10 is low with the write comm and (auto precharge is disabled). t dqss (nom) ck ck# command write nop nop nop nop nop address bank a , col b bank, ( a or all ) nop t0 t1 t2 t3 t2n t4 t5 t3n t6 t7 t wr t rp dq dqs#, dqs dm t dqss (min) dq dqs#, dqs dm t dqss (max) dq dqs#, dqs dm don?t care transitioning data wl + t dqss wl - t dqss wl + t dqss di b pre 1 1 1 di b di b pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 104 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 65: bank write ? without auto precharge notes: 1. nop commands are shown for ease of illus tration; other commands may be valid at these times. 2. bl = 4 and al = 0 in the case shown. 3. disable auto precharge. 4. ?don?t care? if a10 is high at t9. 5. subsequent rising dq s signals must align to the clock within t dqss. 6. di n = data-in for column n ; subsequent elements are ap plied in the programmed order. 7. t dsh is applicable during t dqss (min) and is referenced from ck t5 or t6. 8. t dss is applicable during t dqss (max) and is referenced from ck t6 or t7. ck ck# cke a10 t ck t ch t cl ra t rcd t ras t rp t wr t0 t1 t2 t3 t5 t6 t6n t7 t8 t9 t5n nop 1 nop 1 command 3 5 act ra col n write 2 nop 1 one bank all banks bank x pre bank x nop 1 nop 1 nop 1 t dqsl t dqsh t wpst bank x 4 dq 6 dm di n don?t care transitioning data wl t dqss (nom) t wpre dqs, dqs# address nop 1 wl = 2 t4 bank address pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 105 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 66: bank write ? with auto precharge notes: 1. nop commands are shown for ease of illus tration; other commands may be valid at these times. 2. bl = 4 and al = 0 in the case shown. 3. enable auto precharge. 4. wr is programmed via mr9?mr11 and is calculated by dividing t wr (in ns) by t ck and rounding up to the next integer value. 5. subsequent rising dq s signals must align to the clock within t dqss. 6. di n = data-in from column n ; subsequent elements are applied in the programmed order. 7. t dsh is applicable during t dqss (min) and is referenced from ck t5 or t6. 8. t dss is applicable during t dqss (max) and is referenced from ck t6 or t7. ck ck# cke a10 bank address t ck t ch t cl ra t rcd t rp wr 4 t0 t1 t2 t3 t4 t5 t5n t6 t7 t8 t6n nop 1 nop 1 command 3 act ra col n write 2 nop 1 bank x nop 1 bank x nop 1 nop 1 nop 1 t dqsl t dqsh t wpst dq 6 dm wl t dqss (nom) don?t care transitioning data t wpre dqs, dqs# address t9 nop 1 wl = 2 di n 5 t ras pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 106 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 67: write ? dm operation notes: 1. nop commands are shown for ease of illus tration; other commands may be valid at these times. 2. bl = 4, al = 1, and wl = 2 in the case shown. 3. disable auto precharge. 4. ?don?t care? if a10 is high at t11. 5. t wr starts at the end of the data burst regardless of the data mask condition. 6. subsequent rising dq s signals must align to the clock within t dqss. 7. di n = data-in for column n ; subsequent elements are ap plied in the programmed order. 8. t dsh is applicable during t dqss (min) and is referenced from ck t6 or t7. 9. t dss is applicable during t dqss (max) and is referenced from ck t7 or t8. ck ck# cke a10 bank address t ck t ch t cl ra t rcd t ras t rpa t wr 5 t0 t1 t2 t3 t4 t5 t7n t6 t7 t8 t6n nop 1 nop 1 command 3 act ra col n write 2 nop 1 one bank all banks bank x bank x nop 1 nop 1 nop 1 nop 1 nop 1 nop 1 t dqsl t dqsh t wpst bank x 4 dq 7 dm don?t care transitioning data wl t dqss (nom) t wpre pre dqs, dqs# address t9 t10 t11 wl = 2 di n 6 al = 1 pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 107 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 68: data input timing notes: 1. t dsh (min) generally occurs during t dqss (min). 2. t dss (min) generally occurs during t dqss (max). 3. subsequent rising dq s signals must align to the clock within t dqss. 4. write command issued at t0. 5. for x16, ldqs controls the lower byte and udqs controls the upper byte. 6. write command with wl = 2 (cl = 3, al = 0) issued at t0. precharge precharge can be initiated by either a ma nual precharge command or by an auto precharge in conjunction with either a read or write command. precharge will deactivate the open row in a particular bank or the open row in all banks. the precharge operation is shown in the prev ious read and write operation sections. during a manual precharge command, the a10 input determines whether one or all banks are to be precharged. in the case wher e only one bank is to be precharged, bank address inputs determine the bank to be precharged. when all banks are to be precharged, the bank address inputs are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. when a single-bank precharge command is issued, t rp timing applies. when the precharge (all) command is issued, t rpa timing applies, regardless of the number of banks opened. dqs, dqs# t dqsh t wpst t dqsl t dss 2t dsh 1 t dsh 1t dss 2 dm dq ck ck# t1 t0 t1n t2 t2n t3 t4 t3n di don?t care transitioning data t wpre 3 wl - t dqss (nom) pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 108 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations refresh the commercial temperature ddr2 sdram re quires refresh cycles at an average interval of 7.8125s (max) and al l rows in all banks must be refreshed at least once every 64ms. the refresh period begins when the refresh command is registered and ends t rfc (min) later. the average interval mu st be reduced to 3.9s (max) when t c exceeds +85c. figure 69: refresh mode notes: 1. nop commands are shown for ease of illus tration; other valid commands may be possible at these times. cke must be active during clock positive transitions. 2. the second refresh is not required and is on ly shown as an example of two back-to-back refresh commands. 3. ?don?t care? if a10 is high at this point; a10 must be high if more than one bank is active (must precharge all active banks). 4. dm, dq, and dqs signals are all ?don ?t care?/high-z for operations shown. ck ck# command nop 1 nop 1 nop 1 pre cke ra address a10 bank address bank(s) 3 ba ref nop 1 ref 2 nop 1 act nop 1 one bank all banks t ck t ch t cl ra dq 4 dm 4 dqs, dqs# 4 t rfc 2 t rp t rfc (min) t0 t1 t2 t3 t4 ta0 tb0 ta1 tb1 tb2 don?t care indicates a break in time scale pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 109 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations self refresh the self refresh command is initiated with cke is low. the differential clock should remain stable and meet t cke specifications at least 1 t ck after entering self refresh mode. the procedure for exiting self refresh re quires a sequence of commands. first, the differential clock must be stable and meet t ck specifications at least 1 t ck prior to cke going back to high. once cke is high ( t cke [min] has been satisfied with three clock registrations), the ddr2 sdram must have nop or deselect commands issued for t xsnr. a simple algorithm for meeting both refresh and dll requirements is to apply nop or deselect commands for 200 clock cycles before applying any other command. figure 70: self refresh notes: 1. clock must be stable and meeting t ck specifications at least 1 t ck after entering self refresh mode and at least 1 t ck prior to exiting self refresh mode. 2. self refresh exit is asynchronous; however, t xsnr and t xsrd timing starts at the first rising clock edge where cke high satisfies t isxr. 3. cke must stay high until t xsrd is met; however, if self refresh is being reentered, cke may go back low after t xsnr is satisfied. 4. nop or deselect commands are required prior to exiting self refresh until state tc0, which allows any nonread command. 5. t xsnr is required before any nonread command can be applied. 6. odt must be disabled and r tt off ( t aofd and t aofpd have been satisfied) prior to entering self refresh at state t1. 7. t xsrd (200 cycles of ck) is required before a read command can be applied at state td0. 8. device must be in the all banks idle sta te prior to entering self refresh mode. 9. after self refresh has been entered, t cke (min) must be satisfied prior to exiting self refresh. 10. upon exiting self refresh, odt must remain low until t xsrd is satisfied. c k 1 c k# c omman d nop ref a dd ress c ke 1 vali d dq dm dq s #, dq s nop 4 t rp 8 t c h t c l t c k 1 t c k 1 t x s nr 2, 5, 10 t i s xr 2 enter self refresh mo d e (syn c hronous) exit self refresh mo d e (asyn c hronous) t0 t1 ta2 ta1 don ? t c are ta0 t c 0 t b 0 t x s rd 2, 7 vali d 5 nop 4 t c ke (min) 9 t2 odt 6 t aofd/ t aofpd 6 t d 0 vali d 7 vali d 5 in d i c ates a break in time sc ale t ih t ih t c ke 3 pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 110 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations power-down mode ddr2 sdrams support multiple power-do wn modes that allow significant power savings over normal operating modes. cke is used to enter and exit different power- down modes. power-down entry and exit timings are shown in figure 71 on page 111. detailed power-down entry conditions are shown in figures 72?79. the cke truth table, table 45, is shown on page 112. ddr2 sdrams require cke to be registered high (active) at all times that an access is in progress?from the issuing of a read or write command until completion of the burst. thus, a clock suspend is not supported. for reads, a burst completion is defined when the read postamble is satisfied; for writes, a burst completion is defined when the write postamble and t wr (write-to-precharge command) or t wtr (write-to- read command) are satisfied, as shown in figures 74 and 75 on page 114. the number of clock cycles required to meet t wtr is either two or t wtr/ t ck, whichever is greater. power-down mode (see figure 71 on page 111) is entered when cke is registered low coincident with a nop or deselect command . cke is not allowed to go low during a mode register or extended mode register command time, or while a read or write operation is in progress. if power-down occu rs when all banks are idle, this mode is referred to as precharge power-down. if power-down occurs when there is a row active in any bank, this mode is referred to as acti ve power-down. entering power-down deacti- vates the input and output buffers, excluding ck, ck#, odt, and cke. for maximum power savings, the dll is frozen during precharge power-down. exiting active power- down requires the device to be at the same voltage and frequency as when it entered power-down. exiting precharge power-down requires the device to be at the same voltage as when it entered power-down; however, the clock frequency is allowed to change (see "precharge power-down clock frequency change" on page 116). the maximum duration for either active or precharge power-down is limited by the refresh requirements of the device t rfc (max). the minimum duration for power-down entry and exit is limited by the t cke (min) parameter. the following must be main- tained while in power-down mode: cke low, a stable clock signal, and stable power supply signals at the inputs of the ddr2 sdram. all other input signals are ?don?t care? except odt. detailed odt ti ming diagrams for different power-down modes are shown in figure 82 on page 121?figure 89 on page 125. the power-down state is synchronously exited when cke is registered high (in conjunction with a nop or deselect command), as shown in figure 71 on page 111. pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 111 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 71: power-down notes: 1. if this command is a precharge (or if the device is already in th e idle state), then the power-down mode shown is precharge power-down . if this command is an activate (or if at least one row is already ac tive), then the power-down mode shown is active power- down. 2. t cke (min) of three clocks means cke must be re gistered on three consecutive positive clock edges. cke must remain at the va lid input level the en tire time it takes to achieve the three clocks of registration. thus, after any cke tr ansition, cke may not tr ansition from its valid level during the time period of t is + 2 t ck + t ih. cke must not transition during its t is and t ih window. 3. t xp timing is used for exit precharge power- down and active power-down to any nonread command. 4. t xard timing is used for exit active power-do wn to read command if fast exit is selected via mr (bit 12 = 0). 5. t xards timing is used for exit active power-do wn to read command if slow exit is selected via mr (bit 12 = 1). 6. no column accesses ar e allowed to be in progress at the ti me power-down is entered. if the dll was not in a locked state when cke went low, the dll must be reset after exiting power-down mode for proper read operation. ck ck# command nop nop nop address cke dq dm dqs, dqs# valid t ch t cl enter power-down mode 6 exit power-down mode don?t care t cke (min) 2 t cke (min) 2 valid valid 1 valid t xp 3 , t xard 4 t xards 5 valid valid t is t ih t ih t1 t2 t3 t4 t5 t6 t7 t8 t ck pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 112 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations notes: 1. cke ( n ) is the logic state of cke at clock edge n ; cke ( n - 1) was the state of cke at the pre- vious clock edge. 2. current state is the state of the ddr2 sdram immediately prior to clock edge n . 3. command ( n ) is the command registered at clock edge n , and action ( n ) is a result of com- mand ( n ). 4. the state of odt does not affect the states de scribed in this table. the odt function is not available during self refresh (see "odt timing" on page 120 for more details and specific restrictions). 5. power-down modes do not perform any refresh operations. the duration of power-down mode is therefore limited by the refresh requirements. 6. ?x? means ?don?t care? (inc luding floating around v ref ) in self refresh and power-down. however, odt must be driven high or low in power-down if the odt function is enabled via emr. 7. all states and sequences not shown are illegal or reserved unless exp licitly described else- where in this document. 8. valid commands for power-down entry and exit are nop and deselect only. 9. on self refresh exit, deselect or nop comman ds must be issued on every clock edge occur- ring during the t xsnr period. read commands may be issued only after t xsrd (200 clocks) is satisfied. 10. valid commands for self refresh exit are nop and deselect only. 11. power-down and self refresh can not be entered while read or write operations, load mode operations, or precharge operations are in progress. see ?self refresh? on page 109 and ?self refresh? on page 72 for a list of detailed restrictions. 12. minimum cke high time is t cke = 3 t ck. minimum cke low time is t cke = 3 t ck. this requires a minimum of 3 cl ock cycles of registration. 13. self refresh mode can only be en tered from the all banks idle state. 14. must be a legal command, as defined in table 38 on page 66. table 45: truth table ? cke notes 1?4 apply to the entire table current state cke command ( n ) cs#, ras#, cas#, we# action ( n ) notes previous cycle ( n - 1) current cycle ( n ) power-down l l x maintai n power-down 5, 6 l h deselect or nop power-down exit 7, 8 self refresh l l x maintain self refresh 6 l h deselect or nop self refresh exit 7, 9, 10 bank(s) active h l deselect or nop act ive power-down entry 7, 8, 11, 12 all banks idle h l deselect or nop pre charge power-down entry 7, 8, 11 h l refresh self refresh entry 10, 12, 13 h h shown in table 38 on page 66 14 pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 113 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 72: read-to-power-down or self refresh entry notes: 1. in the example shown, read burst completes at t5; earliest power-down or self refresh entry is at t6. 2. power-down or self refresh entry ma y occur after the read burst completes. figure 73: read with auto precha rge-to-power-down or self refresh entry notes: 1. in the example shown, read burst completes at t5; earliest power-down or self refresh entry is at t6. 2. power-down or self refresh entry ma y occur after the read burst completes. do ck ck# command dq dqs, dqs# rl = 3 t0 t1 t2 don?t care transitioning data nop nop t3 t4 t5 valid t6 t7 t cke (min) address a10 nop cke read valid power-down 2 or self refresh entry nop 1 valid do do do ck ck# command dq dqs, dqs# rl = 3 t0 t1 t2 don?t care transitioning data nop nop t3 t4 t5 valid valid t6 t7 t cke (min) address a10 nop cke read valid power-down or self refresh 2 entry nop 1 do do do do pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 114 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 74: write-to-power-down or self-refresh entry notes: 1. power-down or self refresh entry may occur after the write burst completes. figure 75: write with auto precharge-to-power-down or self refresh entry notes: 1. internal precharge occurs at ta0 when wr has completed; power-down entry may occur 1x t ck later at ta1, prior to t rp being satisfied. 2. wr is programmed through mr9?mr11 and represents ( t wr [min]ns/ t ck) rounded up to next integer t ck. ck ck# command dq dqs, dqs# wl = 3 t 0 t1 t 2 don?t care transitioning data nop nop do t 3 t4 t5 valid valid t 6 valid t7 t 8 t cke (min) address a10 nop write valid power-down or self refresh entry 1 t wtr nop 1 do do do cke ck ck# command dq dqs, dqs# wl = 3 t 0 t1 t 2 don?t care transitioning data nop nop do t 3 t4 t5 valid valid ta 0 valid 1 nop ta1 ta 2 t cke (min) address a10 nop cke write valid power-down or self refresh entry wr 2 do do do indicates a break in time scale pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 115 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 76: refresh command-to-power-down entry notes: 1. the earliest precharge power-down entry may occur is at t2, which is 1 t ck after the refresh command. precharge power- down entry occurs prior to t rfc (min) being satisfied. figure 77: activate command-to-power-down entry notes: 1. the earliest active power-down en try may occur is at t2, which is 1 t ck after the activate command. active power-down entry occurs prior to t rcd (min) being satisfied. ck ck# command don?t care t0 t1 valid refresh t2 t3 t cke (min) cke power-down 1 entry 1 x t ck nop ck ck# command don?t care t0 t1 valid act t2 nop t3 t cke (min) cke power-down 1 entry 1 t ck address valid pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 116 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 78: precharge command-to-power-down entry notes: 1. the earliest precharge power-down entry may occur is at t2, which is 1 t ck after the pre- charge command. precharge power-down entry occurs prior to t rp (min) bein g satisfied. figure 79: load mode command-to-power-down entry notes: 1. valid address for lm command includ es mr, emr, emr(2), and emr(3) registers. 2. all banks must be in the precharged state and t rp met prior to issuing lm command. 3. the earliest precharge power-down entry is at t3, which is after t mrd is satisfied. precharge power-down clock frequency change when the ddr2 sdram is in precharge power-down mode, odt must be turned off and cke must be at a logic low level. a minimum of two differential clock cycles must pass after cke goes low before clock frequency may change. the device input clock frequency is allowed to change only within minimum and maximum operating frequen- cies specified for the particular speed grade. during input clock frequency change, odt and cke must be held at stable low levels. when the input clock frequency is changed, ck ck# command don?t care t0 t1 valid pre t2 nop t3 t cke (min) cke power-down 1 entry 1 x t ck address a10 valid all banks vs. single bank ck ck# command don?t care t0 t1 valid lm t2 nop t3 t4 t cke (min) cke power-down 3 entry t mrd address valid 1 t rp 2 nop pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 117 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations new stable clocks must be provided to the device before precharge power-down may be exited, and dll must be reset via mr after precharge power-down exit. depending on the new clock frequency, additional lm comm ands might be required to adjust the cl, wr, al, and so forth. settings to account for the frequency change. depending on the new clock frequency, an additional lm comma nd might be required to appropriately set the wr mr9, mr10, mr11. during the dll relock period of 200 cycles, odt must remain off. after the dll lock time, the dram is ready to operate with a new clock frequency. figure 80: input clock frequency change during precharge power-down mode notes: 1. a minimum of 2 t ck is required after entering prec harge power-down prior to changing clock frequencies. 2. when the new clock frequency has chan ged and is stable, a minimum of 1 t ck is required prior to exiting precharge power-down. 3. minimum cke high time is t cke = 3 t ck. minimum cke low time is t cke = 3 t ck. this requires a minimum of three clock cycles of registration. 4. if this command is a precharge (or if the de vice is already in the idle state), then the power-down mode shown is precharge power-do wn, which is required prior to the clock frequency change. ck ck# command valid 4 nop address cke dq dm dqs, dqs# nop t ck enter precharge power-down mode exit precharge power-down mode t0 t1 t3 ta0 t2 don?t care valid t cke (min) 3 t xp lm dll reset valid valid nop t ch t cl ta1 ta2 tb0 ta3 2 x t ck (min) 1 1 x t ck (min) 2 t ch t cl t ck odt 200 x t ck nop ta4 previous clock frequency new clock frequency frequency change indicates a break in time scale high-z high-z t cke (min) 3 pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 118 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations reset cke low anytime ddr2 sdram applications may go into a rese t state anytime during normal operation. if an application enters a reset condition, cke is used to ensure the ddr2 sdram device resumes normal operation after reinitializing. all data will be lost during a reset condition; however, the ddr2 sdram device will continue to operate properly if the following conditions outlined in this section are satisfied. the reset condition defined here assumes all supply voltages (v dd , v dd q, v dd l, and v ref ) are stable and meet all dc specifications prior to, during, and after the reset operation. all other input ba lls of the ddr2 sdram device are a ?don?t care? during reset with the exception of cke. if cke asynchronously drops low during any valid operation (including a read or write burst), the memory controller must satisfy the timing parameter t delay before turning off the clocks. stable clocks must exis t at the ck, ck# inputs of the dram before cke is raised high, at which time the normal initialization sequence must occur (see "initialization" on page 73). the ddr2 sdra m device is now ready for normal operation after the initialization sequence. figure 81 on page 119 shows the proper sequence for a reset operation. pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 119 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 81: reset function notes: 1. v dd , v dd l, v dd q, v tt , and v ref must be valid at all times. 2. either nop or deselect command may be applied. 3. dm represents dm for x4/x8 configuration an d udm, ldm for x16 configuration. dqs rep- resents dqs, dqs#, udqs, udqs #, ldqs, ldqs#, rdqs, rdqs# for the appropriate configu- ration (x4, x8, x16). 4. in certain cases where a read cycle is interrupted, cke going high may result in the com- pletion of the burst. 5. initialization timing is shown in figure 37 on page 74. cke r tt bank address high-z dm 3 dqs 3 high-z address a10 ck ck# t cl command nop 2 pre all banks ta0 don?t care transitioning data t rpa t cl t ck odt dq 3 high-z t = 400ns (min) tb0 read nop 2 t0 t1 t2 col n bank a t delay 1 do do read nop 2 col n bank b high-z high-z unknown r tt on system reset t3 t4 t5 start of normal 5 initialization sequence nop 2 indicates a break in time scale 4 do t cke (min) pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 120 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations odt timing once a 12ns delay ( t mod) has been satisfied, and af ter the odt function has been enabled via the emr load mode command, odt can be accessed under two timing categories. odt will operate either in synchronous mode or asynchronous mode, depending on the state of cke. odt can switch anytime except during self refresh mode and a few clocks after being enabled via emr, as shown in figure 82 on page 121. there are two timing categories for odt?tu rn-on and turn-off. during active mode (cke high) and fast-exit power-down mode (any row of any bank open, cke low, mr[12 = 0]), t aond, t aon, t aofd, and t aof timing parameters are applied, as shown in figure 84 on page 122. during slow-exit power-down mode (any row of any bank open, cke low, mr[12] = 1) and precharge power-down mode (all bank s/rows precharged and idle, cke low), t aonpd and t aofpd timing parameters are applied, as shown in figure 85 on page 122. odt turn-off timing, prior to entering any power-down mode, is determined by the parameter t anpd (min), as shown in figure 86 on page 123. at state t2, the odt high signal satisfies t anpd (min) prior to entering power-down mode at t5. when t anpd (min) is satisfied, t aofd and t aof timing parameters apply. figure 86 on page 123 also shows the example where t anpd (min) is not satisfied because odt high does not occur until state t3. when t anpd (min) is not satisfied, t aofpd timing parameters apply. odt turn-on timing prior to entering any power-down mode is determined by the parameter t anpd, as shown in figure 87 on page 123. at state t2, the odt high signal satisfies t anpd (min) prior to entering power-down mode at t5. when t anpd (min) is satisfied, t aond and t aon timing parameters apply. figure 87 also shows the example where t anpd (min) is not satisfied because odt high does not occur until state t3. when t anpd (min) is not satisfied, t aonpd timing parameters apply. odt turn-off timing after exiting any power- down mode is determined by the parameter t axpd (min), as shown in figure 88 on page 124. at state ta1, the odt low signal satis- fies t axpd (min) after exiting power-down mode at state t1. when t axpd (min) is satis- fied, t aofd and t aof timing parameters apply. figure 88 also shows the example where t axpd (min) is not satisfied because odt low occurs at state ta0. when t axpd (min) is not satisfied, t aofpd timing parameters apply. odt turn-on timing after exiting either slow-exit power-down mode or precharge power-down mode is determined by the parameter t axpd (min), as shown in figure 89 on page 125. at state ta1, the odt high signal satisfies t axpd (min) after exiting power-down mode at state t1. when t axpd (min) is satisfied, t aond and t aon timing parameters apply. figure 89 also shows the example where t axpd (min) is not satisfied because odt high occurs at state ta0. when t axpd (min) is not satisfied, t aonpd timing parameters apply. pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 121 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 82: odt timing for ente ring and exiting power-down mode mrs command to odt update delay during normal operation, the value of th e effective termination resistance can be changed with an emrs set command. t mod (max) updates the r tt setting. figure 83: timing for mrs command to odt update delay notes: 1. the lm command is directed to the mode register, which updates the information in emr (a6, a2), that is, r tt (nominal). 2. to prevent any impedance glitch on the channe l, the following conditions must be met: t aofd must be met before issuing the lm co mmand; odt must remain low for the entire duration of the t mod window until t mod is met. t anpd (3 t c ks) first c ke lat c he d low t axpd (8 t c ks) first c ke lat c he d hi g h s yn c hronous appli c a b le mo d es appli c a b le timin g parameters s yn c hronous s yn c hronous or asyn c hronous any mo d e ex c ept self refresh mo d e any mo d e ex c ept self refresh mo d e a c tive power- d own fast (syn c hronous) a c tive power- d own slow (asyn c hronous) pre c har g e power- d own (asyn c hronous) t aond/ t aofd (syn c hronous) t aonpd/ t aofpd (asyn c hronous) t aond/ t aofd t aond/ t aofd c ke c k# c k odt 2 internal r tt settin g c omman d ol d settin g un d efine d new settin g 0ns 2 t i s t aofd in d i c ates a break in time sc ale t0 ta0 ta1 ta2 ta3 ta4 ta5 emr s 1 nop nop nop nop nop t mod pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 122 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 84: odt timing for acti ve or fast-exit power-down mode figure 85: odt timing for slow- exit or precharge power-down modes t1 t0 t2 t3 t4 t5 t 6 vali d vali d vali d vali d vali d vali d vali d c k# c k odt r tt t aof (max) t aon (min) t aond a dd ress t aofd t aon (max) t aof (min) vali d vali d vali d vali d vali d vali d vali d c omman d t c h t c l don ? t c are r tt unknown r tt on t c k c ke don ? t c are t1 t0 t2 t3 t4 t5 t 6 vali d vali d vali d vali d vali d vali d vali d c k# c k c ke odt a dd ress vali d vali d vali d vali d vali d vali d vali d c omman d t c h t c l t aonpd (min) t aonpd (max) t aofpd (min) t aofpd (max) transitionin g r tt t7 vali d vali d r tt unknown r tt on t c k r tt pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 123 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 86: odt turn-off timings when entering power-down mode figure 87: odt turn-on timing when entering power-down mode t1 t0 t2 t3 t4 t5 t6 nop nop nop nop nop nop nop ck# ck command cke odt r tt t aof (min) t aof (max) t aofd odt r tt t aofpd (min) don?t care r tt unknown r tt on t aofpd (max) t anpd (min) t1 t0 t2 t3 t4 t5 t6 nop nop nop nop nop nop nop ck# ck r tt t aon (min) t aon (max) odt r tt t aonpd (min) t aonpd (max) don?t care transitioning r tt r tt unknown r tt on odt t anpd (min) command t aond cke pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 124 ?2003 micron technology, inc. all rights reserved. 1gb: x4, x8, x16 ddr2 sdram operations figure 88: odt turn-off timing when exiting power-down mode transitioning r tt t1 t0 t2 t3 t4 ta0 ta1 nop nop nop nop nop nop nop ck# ck cke t axpd (min) odt r tt t aof (max) odt r tt t aofpd (min) t aofpd (max) command ta2 ta3 ta4 ta5 nop nop nop nop don?t care r tt unknown t aof (min) indicates a break in time scale r tt on t cke (min) t aofd ? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo ar e trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits spec ified over the power supply an d temperature range set forth herein. although considered final, these specifications ar e subject to change, as furthe r product development and data characterization sometimes occur. 1gb: x4, x8, x16 ddr2 sdram operations pdf: 09005aef8117c187/source: 09005aef821aed36 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_x4x8x16_core2.fm - 1gb ddr2: rev. n; core ddr2: rev. c 4/08 en 125 ?2003 micron technology, inc. all rights reserved. figure 89: odt turn-on timing when exiting power-down mode t1 t0 t2 t3 t4 ta0 ta1 nop nop nop nop nop nop nop ck# ck cke t axpd (min) command ta2 ta3 ta4 ta5 nop nop nop nop t aon (min) t aon (max) r tt t aonpd (min) t aonpd (max) don?t care r tt unknown r tt on indicates a break in time scale t ransitioning r tt t aond t cke (min) r tt odt odt |
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