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1 file number 2808.8 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 407-727-9207 | copyright intersil corporation 1999 hsp43168 dual fir filter the hsp43168 dual fir filter consists of two independent 8-tap fir ?ters. each ?ter supports decimation from 1 to 16 and provides on-board storage for 32 sets of coef?ients. the block diagram shows two fir cells each fed by a separate coef?ient bank and one of two separate inputs. the outputs of the fir cells are either summed or multiplexed by the mux/adder. the compute power in the fir cells can be con?ured to provide quadrature ?tering, complex ?tering, 2-d convolution, 1-d/2-d correlations, and interpolating/decimating ?ters. the fir cells take advantage of symmetry in fir coef?ients by pre-adding data samples prior to multiplication. this allows an 8-tap fir to be implemented using only 4 multipliers per ?ter cell. these cells can be con?ured as either a single 16-tap fir ?ter or dual 8-tap fir ?ters. asymmetric ?tering is also supported. decimation of up to 16 is provided to boost the effective number of filter taps from 2 to 16 times. further, the decimation registers provide the delay necessary for fractional data conversion and 2-d filtering with kernels to 16 x16. the ?xibility of the dual is further enhanced by 32 sets of user programmable coef?ients. coef?ient selection may be changed asynchronously from clock to clock. the ability to toggle between coef?ient sets further simpli?s applications such as polyphase or adaptive ?tering. the hsp43168 is a low power fully static design implemented in an advanced cmos process. the con?uration of the device is controlled through a standard microprocessor interface. features two independent 8-tap fir filters con?urable as a single 16-tap fir 10-bit data and coef?ients on-board storage for 32 programmable coefficient sets up to: 256 fir taps, 16 x 16 2-d kernels, or 10 x 19-bit data and coef?ients programmable decimation to 16 programmable rounding on output standard microprocessor interface applications quadrature, complex filtering image processing polyphase filtering adaptive filtering block diagram ordering information part number temp. range ( o c) package pkg. no. hsp43168vc-33 0 to 70 100 ld mqfp q100.14x20 hsp43168vc-40 0 to 70 100 ld mqfp q100.14x20 hsp43168vc-45 0 to 70 100 ld mqfp q100.14x20 HSP43168JC-33 0 to 70 84 ld plcc n84.1.15 hsp43168jc-40 0 to 70 84 ld plcc n84.1.15 hsp43168jc-45 0 to 70 84 ld plcc n84.1.15 hsp43168ji-40 -40 to 85 84 ld plcc n84.1.15 hsp43168gc-45 0 to 70 84 ld cpga g84.a fir cell a coefficient bank a cin0 - 9 a0 - 8 wr ina0 - 9 out9 - 27 control/ configuration mux / adder 10 919 inb0 - 9/ out0 - 8 oeh oel csel0 - 4 mux mux fir cell b coefficient bank b 10 10 9 data sheet november 1999
2 pinouts 84 lead cpga bottom view 84 lead cpga top view 84 lead plcc top view 11 10 9 8 7 6 5 4 3 2 1 11 10 9 8 7 6 5 4 3 2 1 b a c d e f g h j k l b a c d e f g h j k l csel0 csel2 cin9 v cc a4 a1 gnd out15 out14 out12 out10 out11 inb1 inb4 inb5 inb6 ina1 inb7 gnd inb2 out13 inb0 out16 out9 accen mux0 mux1 gnd a0 a5 a7 csel1 csel3 csel4 cin5 cin6 cin4 gnd v cc v cc inb3 ina2 ina3 ina4 ina7 ina5 ina8 ina9 cin2 cin1 ina6 cin0 v cc cin3 a8 a6 a2 a3 v cc r vrs wr cin7 shften txfr fwrd oeh gnd clk out27 out22 out26 out24 out23 out25 out21 out20 out19 out17 oel out18 inb9 inb8 ina0 hsp43168 bottom view pin 'a1' id cin8 csel0 csel2 cin9 v cc a4 a1 gnd out15 out14 out12 out10 out11 inb1 inb4 inb5 inb6 ina1 inb7 gnd inb2 out13 inb0 out16 out9 gnd accen mux0 mux1 gnd a0 a5 a7 csel1 csel3 csel4 cin5 cin6 cin4 gnd v cc 11 10 9 8 7 6 5 4 3 2 1 v cc inb3 ina2 ina3 ina4 ina7 ina5 ina8 ina9 cin2 cin1 ina6 cin0 v cc cin3 a8 a6 a2 a3 v cc out21 out19 b a c d e f g h j k l 11 10 9 8 7 6 5 4 3 2 1 inb9 out18 inb8 ina0 out17 out20 out24 out23 out25 out27 out22 out26 oeh clk fwrd txfr shften r vrs wr cin7 hsp43168 top view oel pin 'a1' id cin8 b a c d e f g h j k l 66 67 68 69 70 71 72 73 74 58 59 60 61 62 63 64 65 54 55 56 57 20 19 18 17 16 15 14 13 12 28 27 26 25 24 23 22 21 32 31 30 29 inb 2 inb 3 inb 4 inb 5 inb 6 inb 8 inb 7 gnd out 13 out 12 out 11 out 9 inb 1 inb 0 out 10 v cc out 14 out 15 gnd out 16 oel r vrs fwd txfr out 27 out 26 out 25 out 24 out 23 out 22 out 21 out 20 out 19 out 17 v cc v cc oeh gnd accen clk out 18 shften cin 6 cin 2 ina 9 ina 7 ina 6 ina 5 ina 3 cin 7 cin 4 gnd cin 3 cin 0 v cc ina 2 ina 1 ina 0 inb 9 cin 5 cin 1 ina 8 ina 4 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 11 10 9 8 7 6 5 4 3 2 1 848382818079 76 77 78 75 a 4 a 6 a 7 csel 3 a 5 a 3 a 0 csel 4 cin 9 a 2 cin 8 csel 1 csel 0 a 8 a 1 gnd mux 1 mux 0 csel 2 v cc wr hsp43168
3 100 lead mqfp top view pinouts (continued) 99 98 97 96 95 94 93 91 89 87 85 84 83 81 82 86 88 90 92 100 79 80 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 32 33 34 35 36 37 38 40 42 44 46 47 48 50 49 45 43 41 39 31 wr v cc v cc cin9 gnd gnd a0 a1 a2 a3 a4 a5 a6 a7 a8 csel0 csel1 csel2 csel3 csel4 ina5 cin0 ina9 ina8 ina7 ina6 v cc v cc ina4 ina3 cin1 ina1 ina0 ina2 nc cin7 nc cin6 cin5 gnd cin4 gnd cin3 cin2 cin8 nc nc inb7 inb9 inb8 out18 out17 nc v cc gnd gnd v cc out19 gnd oeh out27 out26 out24 out23 out22 out21 out20 out25 gnd mux0 r vrs nc fwrd txfr accen v cc v cc clk shiften mux1 inb6 gnd gnd inb5 inb4 inb3 inb2 inb1 inb0 oel out9 out10 v cc v cc out11 out12 out13 out14 out15 out16 hsp43168
4 pin description symbol type description v cc v cc : +5v power supply pin. gnd ground. cin0-9 i control/coefficient data bus. processor interface for loading control data and coefficients. cin0 is the lsb. a0-8 i control/coefficient address bus. processor interface for addressing control and coefficient registers. a0 is the lsb. wr i control/coefficient write clock. data is latched into the control and coefficient registers on the rising edge of wr. csel0-4 i coefficient select. this input determines which of the 32 coefficient sets are to be used by fir a and b. this input is registered and csel0 is the lsb. ina0-9 i input to fir a. ina0 is the lsb. inb0-9 i/o bidirectional input for fir b. inb0 is the lsb and is input only. when used as output, inb1-9 are the lsbs of the output bus, and inb9 is the msb of these bits. out9-27 o 19 msbs of output bus. data format is either unsigned or two's complement depending on configuration. out27 is the msb. shften i shift enable. this active low input enables clocking of data into the part and shifting of data through the decimation registers. fwrd i forward alu input enable. when active low, data from the forward decimation path is input to the alus through the ??input. when high, the ??inputs to the alus are zeroed. r vrs i reverse alu input enable. when active low, data from the reverse decimation path is input to the alus through the ??input. when high, the ??inputs to the alus are zeroed. txfr i data transfer control. this active low input switches the lifo being read into the reverse decimation path with the lifo being written from the forward decimation path (see figure 1). mux0-1 i adder/mux control. this input controls data flow through the output adder/mux. table 5 lists the various configurations. clk i clock. all inputs except those associated with the processor interface (cin0-9, a0-8, wr) and the output enables ( oel, oeh) are registered by the rising edge of clk. oel i output enable low. this three-state control enables the lsbs of the output bus to inb1-9 when oel is low. oeh i output enable high. this three-state control enables out9-27 when oeh is low. accen i accumulate enable. this active high input allows accumulation in the fir cell accumulator. a low on this input latches the fir accumulator contents into the output holding registers while zeroing the feedback pass in the accumulator. hsp43168
5 hsp43168 delay 1-16 ?? delay 1-16 ?? delay 3 alu ab alu ab alu ab alu ab ina0-9 inb1-9/ lifo a lifo b delay 1-16 ?? m u x m u x d e m u x m u x m u x delay 1-16 ?? delay 1-16 ?? delay 1-16 ?? delay 1-16 ?? delay 1-16 ?? delay 1-16 ?? delay 1-16 ?? alu ab alu ab alu ab alu ab lifo a lifo b delay 1-16 m u x m u x d e m u x delay 1-16 ?? delay 3 delay 4 m u x delay 3 delay 3 delay 3 reg x coef bank reg reg x coef bank reg reg x reg reg x coef bank reg reg x coef bank reg reg x coef bank reg reg x coef bank reg reg x coef bank reg delay 4 adder m u x reg 0 delay 5 mux/ adder delay 2 control out9-27 delay 6 oel oeh a0-8 wr mux0-1 accen cin0-9 csel0-4 fwrd r vrs shften txfr ? odd/even ? mode select ? odd/even ? odd/even ? mode select fir cell a fir cell b 10 9 10 5 9 2 19 9 ? round enable out0-8 inb0 r e g adder m u x reg 0 r e g fir a accumulator fir b accumulator data feedback circuitry data feedback circuitry output holding register output holding register decimation registers decimation registers 3 2 1 0 3 2 1 0 delay 1-16 ?? delay 1-16 ?? delay 1-16 ?? delay 3 number of delay 4 m u x delay 3 figure 1. dual fir filter coef bank ? odd even symmetry ? fir a odd/even # taps ? fir b odd/even # taps ? fir b input source ? data reversal enable ? round enable ? decimation factor ? processor control words ? fir b input source symmetry ? fir a odd/even # taps fir a reverse path fir a forward path fir b reverse path fir b forward path symmetry ? fir b odd/even # taps ? odd/even symmetry ? mode select ? data reversal enable ? data reversal enable ?? decimation factor 28 11 10 21 11 10 10 22 clk 1 0 1 0 taps
6 functional description as shown in figure 1, the hsp43168 consists of two 4-multiplier fir ?ter cells which process 10-bit data and coef?ients. the fir cells can operate as two independent 8-tap fir ?ters or two 4-tap asymmetric ?ters at maximum i/o rates. a single ?ter mode is provided which allows the fir cells to operate as one 16-tap fir ?ter or one 8-tap asymmetric ?ter. on board coef?ient storage for up to 32 sets of 8 coef?ients is provided. the coef?ient sets are user selectable and are programmed through a microprocessor interface. programmable decimation to 16 is also provided. by utilizing decimation registers together with the coef?ient sets, polyphase ?ters are realizable which allow the user to trade data rate for ?ter taps. the mux/adder can be con?ured to either add or multiplex the outputs of the ?ter cells depending upon whether the cells are operating in single or dual ?ter mode. in addition, a shifter in the mux/adder is provided for implementation of ?ters with 10-bit data and 20-bit coef?ients or vice versa. preparing the dual fir for operation two con?uration steps are required to prepare the dual fir filter for normal operation: 1) loading the con?uration control registers, and 2) loading the fir filter coef?ients. con?uration control registers are loaded by placing the control register address on address lines a0-8, placing the con?uration data on the con?uration input lines cin0-9, and asserting the wr line (followed by a release of the assertion). this action creates a rising edge on the wr line, which clocks the address and configuration data into the part. the details of the ?oad configuration process are outlined in the microprocessor interface section. fir coefficients are loaded by placing the address of the coefficient data bank on the address lines a0-8, placing the fir 10-bit coefficient values on the configuration input lines cin0-9 and then asserting the wr line (followed by a release of the assertion). this action creates a rising edge on the wr line, which clocks the fir coefficient band address and fir coefficient data into the part. the details of the ?oad fir coefficient?process are outlined in the fir filter cells section, coefficient bank subsection. both the configuration load and fir coefficient load can be done as a sequence of asynchronous write commands to the dual fir filter. once these actions are complete, the part is ready for normal filter operation. the clk, txfr, fwrd, r vrs, accen, and shften signals must be asserted in a manner determined by the application. mux0-1 must meet the setup and hold times with respect to clock for proper filter operation. details of the mux1-0 control can be found in the output mux/adder section. details of the accen control can be found in the fir cell accumulator section. bit locations for the various filter control/configuration signals can be found in the input/output formats section. the dual fir filter has a ?ipeline?delay of 8 clk periods, once normal ?tering operations begin. five typical ?tering operation examples are provided in the applications examples section as a guide to con?uration and control of the dual fir filter. during normal ?ter operations, the location and duration of the txfr signal assertions are determined by the ?ter con?uration and operation mode. once set, these signal parameters must be maintained during normal operation to ensure proper data alignment in the part. once the part is reset, do not change txfr unless you load the con?uration again. note: the ?ed or periodic relationship between the txfr signal and clk must be maintained for valid ?ter operation. this relationship can only change when clk is halted and new con?uration control words are loaded into the device. microprocessor interface the dual fir has a 20 pin write only microprocessor interface for loading data into the control block and coefficient banks. the interface consists of a 10-bit data bus (cin0-9), a 9-bit address bus (a0-8), and a write input ( wr) to latch the data into the on-board registers on a rising edge. the configuration control and coefficient data loading is asynchronous to clk. control block the dual fir is con?ured by writing to the registers within the control block. figure 2 shows the timing diagram for writing to the con?uration control registers. these control registers are memory mapped to address 000h (h = hexadecimal) and 001h on a0-8. the filter coef?ient registers are mapped to 1xxh (x = value described in the ?oef?ient banks?chapter of the alu section). the format of the control registers is shown in table 1 and table 2. writing to any of the control/con?uration registers causes a reset which lasts for 6 clk cycles following the assertion of wr. the reset caused by writing registers in the control block will not clear the contents of the coef?ient wr a8-0 c9-0 000h figure 2. latching c9-0 values into address a8-0 registers reset 001h hsp43168
7 bank. as shown in figure 2, either con?uration control register can be written to during reset. the 4 lsbs of the control word loaded at address 000h are used to select the decimation factor. the decimation factor is programmed to one less than the number of delays between ?ter taps for example, if the 4 lsbs are programmed with a value of 0010, the forward and reverse shifting decimation registers are each configured with a delay of 3. bit 4 is used to select whether the fir cells operate as two independent filters or one extended length filter. dual filter mode assumes filter a and filter b are separate independent filters. in the single filter mode, the data is routed through the forward paths of filters a and b before entering the reverse paths of filters a and b (see figure 1). coefficient symmetry is selected by bit 5. bits 6 and 7 are programmed to configure the fir cells for odd or even filter lengths (number of taps). bit 8 selects the fir b input source when the fir cells are configured for independent operation. bit 9 must be programmed to 0. note: when the filter is programmed for even-taps, the txfr signal is delayed by only three clks (see figure 1). for odd-taps, the txfr signal is delayed by four clks. the 4 lsbs of the control word loaded at address 001h are used to con?ure the format of the fir cell's data and coef?ients. bit 4 is programmed to enable or disable the reversal of data sample order prior to entering the reverse path decimation registers. data reversal is required for symmetric ?ter coef?ient sets of both even or odd numbers of ?ter taps. asymmetric ?ters and some decimated symmetric ?ters require the data reversal to be off. bits 5-9 are used to support programmable rounding on the output. fir filter cells each fir filter cell is based on an array of four 11x10-bit two's complement multipliers. one input of the multipliers comes from the alus which combine data shifting through the forward and reverse decimation registers. the second multiplier input comes from the user programmable coefficient bank. the multiplier outputs are fed to an accumulator whose result is passed to the output section where it is multiplexed or added with the result from the other fir cell. decimation registers the forward and reverse decimation shift registers can be con?ured for decimation factors from 1 to 16 (see table 1, bits 0-3). note: setting the decimation factor only affects the delay registers between ?ter taps, not the ?ter control multiplexers. example 4 and example 5 in the applications section discuss how to con?ure the part for actual decimation applications. the reverse shifting registers with the data reversal logic are used to take advantage of symmetry in linear phase filters by aligning data at the alus for pre-addition prior to multiplication by the common coefficient. when the fir cells are configured in single filter mode, the decimation registers in fir cell a and fir cell b are cascaded. this extended filter tap delay path allows computation of a filter which is twice the size of that capable using a single cell. the decimation registers also provide data storage for polyphase or 2-d filtering applications (see applications examples section). the data feedback circuitry in each fir cell is responsible for transferring data from the forward to the reverse shifting decimation registers. this circuitry feeds blocks of samples into the reverse shifting decimation path in either reversed or non-reversed sample order. the mux/demux structure at the input to the feedback circuitry routes data to the lifos or the delay stage depending on the selected table 1. configuration/control word 0 bit definitions control address 000h bits function description 3-0 decimation factor (n) r = n + 1 0000 = no decimation. 1111 = decimation by 16. 4 mode select 0 = single filter mode. 1 = dual filter mode. (also 20-bit coefficient filter) 5 odd/even filter coefficient symmetry 0 = even symmetric coefficients. 1 = odd symmetric coefficients. 6 fir a odd/even number of taps 0 = odd number of taps in filter. 1 = even number of taps in filter. 7 fir b odd/even number of taps (defined same as fir a above). 8 fir b input source 0 = input from ina0-9. 1 = input from inb0-9. 9 not used set to 0 for proper operation. note: address locations 002h to 011h are reserved, and writing to these locations will have unpredictable effects on part con?uration. table 2. configuration/control word 1 bit definitions control address 001h bits function description 0 fir a input format 0 = unsigned. 1 = two's complement. 1 fir a coefficient format (defined same as fir a input). 2 fir b input format (defined same as fir a input). 3 fir b coefficient (defined same as fir a input). 4 data re v ersal enab le 0 = enabled. 1 = disabled. 8-5 round position 0000 = 2 -10. 1011 = 2 1. (see figure 4) 9 round enable 0 = enabled. 1 = disabled. note: address locations 002h to 011h are reserved, and writing to these locations will have unpredictable effects on part con?uration. df clk delays between taps () 1 = (eq. 1) hsp43168
8 configuration. the mux on the feedback circuitry output selects which storage element feeds the reverse shifting decimation registers. in applications requiring reversal of sample order, the fir cells are configured with data reversal enabled (see table 2, cw5, bit 4 = 0). in this mode, data is transferred from the forward to the backward shifting registers through a pingponged lifo structure. while one lifo is being read into the backward shifting path, the other lifo is written with data samples. the mux/demux controls which lifo is being written, and the mux on the feedback circuitry output controls which lifo is being read. a low on txfr and shiften, switches the lifos being read and written, which causes the block of data to be read from the structure in reversed in sample order (see example 4 in the application examples section). the frequency with which txfr is asserted determines size of the data blocks in which sample order is reversed. for example, if txfr is asserted once every three clks, blocks of 3 data samples with order reversed, would be fed into the backward decimation registers. note: altering the frequency or phase of txfr assertion once a ?tering operation has begun will invalidate the ?tering result. in applications which do not require sample order reversal, the fir cells must be configured with data reversal disabled (see table 2, cw5, bit 4 = 1). in addition, txfr must be asserted to ensure proper data flow. in this configuration, data to the backward shifting decimation path is routed though a delay stage instead of the pingpong lifos. the number of registers in the delay stage is based on the programmed decimation factor. note: data reversal must be disabled and txfr must be asserted for filtering applications which do not use decimation. the shifting of data through the forward and reverse decimation registers is enabled by asserting the shften input. when shften is high, data shifting is disabled, and the data sample latched into the part on the previous clock is the last input to the ?ter structure. the data sample at the ?ter input when shften is asserted, will be the next data sample into the forward decimation path. when operating the fir cells as two independent ?ters, fir a receives input data via ina0-9 and fir b receives data from either ina0-9 or inb0-9 depending on the application (see table 1). when the fir cells are con?ured as a single extended length ?ter, the forward and reverse decimation paths of the two fir cells are cascaded. in this mode, data is transferred from the forward decimation path to the reverse decimation path by the data feedback circuitry in fir b. thus, the manner in which data is read into the reverse decimation path is determined by fir b's con?uration. when the decimation paths are cascaded, data is routed through the fourth delay stage in fir a's forward path to fir b. the configuration of the fir cells as even or odd length filters determines the point in the forward decimation path from which data is multiplexed to the data feedback circuitry. for example, if the fir cell is configured as an odd length filter, data prior to the last register in the third forward decimation stage is routed to the feedback circuitry. if the fir cell is configured as an even length filter, data output from the third forward decimation stage is multiplexed to the feedback circuitry. this is required to ensure proper data alignment with symmetric filter coefficients (see application examples). alus data shifting through the forward and reverse decimation paths feed the ??and ??inputs of the alus respectively. the alus perform an ?+a?operation if the fir cell is con?ured for even symmetric coef?ients or an ?-a operation if con?ured for odd symmetric coef?ients. control word 0, bit 5 is used to set the alu operation. for applications in which a pre-add or subtract is not required, the ??or ??input can be zeroed by disabling fwrd or r vrs respectively. this has the effect of producing an alu output which is either ?? ?a? or ??depending on the filter symmetry chosen. for example, if the fir cell is configured for an even symmetric filter with fwrd low and r vrs high, the data shifting through the forward decimation registers would appear on the alu output. table 3 details the alu con?urations, where ? is the alu data input from the front decimation delay registers and ? is the alu data from the back decimation delay registers. coef?ient bank the output of the alu is multiplied by a coef?ient from one of 32 user programmable coef?ient sets. each set consists of 8 coef?ients (4 coef?ients for fir a and 4 for fir b). csel0-4 is used to select a coef?ient set to be used. coef?ient sets may be switched every clock to support polyphase ?tering operations. the coef?ients are loaded into on-board registers using the microprocessor interface, cin0-9, a0-8, and wr. each multiplier within the fir cells is driven by a coef?ient bank table 3. alu configurations alu out symmetry fwd r vs description a+b 0 (even) 0 0 even number of taps, even symmetry (example 1) +b 0 (even) 0 1 even symmetry +a 0 (even) 1 0 even symmetry - 0 (even) 1 1 even symmetry b-a 1 (odd) 0 0 even number of taps, odd symmetry (example 2) +b 1 (odd) 0 1 odd symmetry -a 1 (odd) 1 0 odd symmetry - 1 (odd) 1 1 odd symmetry hsp43168
9 with one of 32 coef?ients. these coef?ients are addressed as shown in table 4. the inputs a0-1 specify the coef?ient bank for one of the four multipliers in each fir cell; a2 speci?s fir cell a or b; bits a7-3 specify one of 32 sets in which the coef?ient is to be stored. for example, an address of 10dh would access the coef?ient for the second multiplier in fir b in the second coef?ient set. fir cell accumulator the registered outputs from the multipliers in each fir cell feed an accumulator. the accen input controls each accumulator's running sum and the latching of data from the accumulator into the output holding registers. when accen is low, feedback from the accumulator adder is zeroed which disables accumulation. also, output from the accumulator is latched into the output holding registers. when accen is asserted, accumulation is enabled and the contents of the output holding registers remain unchanged. output mux/adder the contents of each fir cell's output holding register is summed or multiplexed in the mux/adder. the operation of the mux/adder is controlled by the mux1-0 inputs as shown in table 5. applications requiring 10-bit data and 20- bit coefficients or 20-bit data and 10-bit coefficients are made possible by configuring the mux/adder to scale fir b's output by 2 -10 prior to summing with fir a. when the dual fir is configured as two independent filters, the mux1-0 inputs would be used to multiplex the filter outputs of each cell. for applications in which fir a and b are configured as a single filter, the mux/adder is configured to sum the output of each fir cell. note: while a 20-bit coef?ient ?ter is a single ?ter, the mode select is set to 1 and mux1-0 is set to 00. input/output formats the dual fir supports mixed mode arithmetic with both unsigned and two's complement data and coefficients. the input and output formats for both data types are shown below. if the dual fir is configured as an even symmetric filter with unsigned data and coefficients, the output will be unsigned. otherwise, the output will be two's complement. the mux/adder can be configured to implement programmable rounding at bit locations 2 -10 through 2 1 . the round is implemented by adding a 1 to the specified location (see table 2). figure 4 illustrates the rounding operation. for example, to configure the part such that the output is rounded to the 10 msbs, out18 - 27, the round position would be chosen to be 2 -1 . the negative sign on the msb indicates 2s complement format. table 4. fir coefficient write addresses fir coeff. csel (4-0) coeff. set cell a/b multip lier destination a8 a7-3 a2 a1-0 fir bank 1 xxxx x 0 00 a 0 1 xxxx x 0 01 a 1 1 xxxx x 0 10 a 2 1 xxxx x 0 11 a 3 1 xxxx x 1 00 b 0 1 xxxx x 1 01 b 1 1 xxxx x 1 10 b 2 1 xxxx x 1 11 b 3 table 5. mux1-0 bit definitions mux1-0 decoding mux1-0 out0-27 00 fira + firb (fir b scaled by 2 -10 ) 01 fira + firb 10 fira 11 firb input data format ina0-9, inb0-9 fractional two? complement 9876543210 -2 0 .2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 output data format out9-27 fractional two's complement 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 -2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 .2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 output data format out0-8 fractional two's complement 876543210 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 2 -16 2 -17 2 -18 input data format ina0-9, inb0-9 fractional unsigned 9876543210 2 0 .2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 output data format out9-27 fractional unsigned 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 .2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 output data format out0-8 fractional unsigned 876543210 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 2 -16 2 -17 2 -18 figure 3. input/output format definitions hsp43168
10 application examples in this section a number of examples are presented which detail even, odd, symmetric, asymmetric, decimating and dual fir ?ter con?urations. these examples are intended to illustrate the different operational features of the hsp43168 and should be used as a guide in developing an application speci? ?ter con?uration. use table 6 to select and ?d the example that best matches your application. examples 1-5 are explained using a single four tap fir cell, but the same concept applies to fir filters which use both fir cells (a and b) in a single filter configuration. example 6 details a dual filter mode where fir cell a and b implement different digital filters. all examples are functionally verified configurations. each example details a complete design solution, including a block diagram, a data/coefficient alignment illustration, a data flow diagram and a control signal timing diagram. two programmable configuration control registers define a unique fir filter configuration. register 000h has all filter configuration unique parameters, while register 001h, bit 4, is filter configuration unique. table 7 details the configuration control register values, the number of filter coefficient banks required and the mux1-0 control values for each filter example. example 1. even-tap even symmetric filter example the hsp43168 may be configured as two independent 8-tap symmetric filters as shown by the block diagram in figure 5. each of the fir cells takes advantage of symmetric filter coefficients by pre-adding data samples common to a given coefficient. as a result, each fir cell can implement an 8-tap symmetric filter using only four multipliers. similarly, when the hsp43168 is configured in single filter mode a 16-tap symmetric filter is possible by using the multipliers in both cells. the operation of the fir cell is better understood by comparing the data and coefficient alignment for a given filter output, figure 6, with the data flow through the fir cell, as shown in figure 7. the block diagrams in figure 7 are a simplification of the fir cell shown in figure 1. for simplicity, the alus and fir cell accumulators were replaced by adders, and the pipeline delay registers were omitted. in this example, we will only show the data flow through one of the two fir cells. in figure 7, the order of the data samples within the filter cell is shown by the numbers in the forward and backward shifting decimation paths. the output of the filter cell is table 6. filter example selection guide filter type example number even tap even symmetric 1 odd tap even symmetric 2 asymmetric 3 even tap decimating 4 odd tap decimating 5 dual decimating 6 figure 4. round position bit definition i out 9-27 i out 0-8 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 2 -10 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 ?ound position?value number of output bits location of addition of 1 output bits table 7. configuration control register values filter type reg 000 hex reg 001 hex # of filter coefficient banks mux 1-0 even tap even symmetric 1d0 010 1 10 odd tap even symmetric 110 010 1 10 asymmetric 110 010 2 10 even tap decimate by n+1 1dn 000 n+1 10 odd tap decimate by n+1 11n 000 n+1 10 dual: even and odd tap decimate by n+1 15n or 19n 000 bit 4 n+1 10 and 11 hsp43168 ina0-9 inb0-9 out9-27 fir a fir b m u x figure 5. using hsp43168 as two independent filters 8-tap even symmetric 8-tap even symmetric aa bb hsp43168
11 given by the equation at the bottom of each block diagram. figure 7a shows the data sample alignment at the pre- adders for the data/coefficient alignment shown in figure 6. the dual filter application is configured by writing 1d0h to address 000h via the microprocessor interface, cin0-9, a0-8, and wr. since this application does not use decimation, the 4th bit of the control register at address 001h must be set to disable data reversal (see table 2). failure to disable data reversal will produce erroneous results. using this architecture, only the unique coef?ients need to be stored in the coef?ient bank. for example, the above ?ter would be stored in the ?st coef?ient set for fir a by writing c0, c1, c2, and c3 to address 100h, 101h, 102h, and 103h respectively. to write the same ?ter to the ?st coef?ient set for fir b, the address sequence would change to 104h, 105h, 106h, and 107h. to operate the hsp43168 in this mode, txfr is tied low to ensure proper data flow; both fwrd and r vrs are tied low to enable data samples from the forward and reverse data paths to the alus for pre-adding; accen is tied low to prevent accumulation over multiple clks; shften is tied low to allow shifting of data through the decimation registers; mux0-1 is programmed to multiplex the output the of either fir a or fir b; csel0-4 is programmable to access the stored coefficient set, in this example csel = 00000. c0 c1 c2 c3 c3 c2 c1 c0 x9 x8 x7 x6 x5 x4 x3 x2 x1 x0 h(n) x(n) figure 6. data/coefficient alignment for 8-tap even symmetric filter 8 taps figure 7a. data flow as data sample 7 is clocked into the feed forward stage figure 7b. data flow as data sample 8 is clocked into the feed forward stage figure 7c. data flow as data sample 9 is clocked into the feed forward stage figure 7. data flow diagrams for 8-tap symmetric filter 6 5 4 7 c0 c1 c2 c3 0 1 2 3 (x7+x0)c0+(x6+x1)c1+(x5+x2)c2+(x4+x3)c3 + + + + + + + + + + 7 6 5 8 c0 c1 c2 c3 1 2 3 (x8+x1)c0+(x7+x2)c1+(x6+x3)c2+(x5+x4)c3 4 + + + + + 8 7 6 9 c0 c1 c2 c3 2 3 4 5 (x9+x2)c0+(x8+x3)c1+(x7+x4)c2+(x6+x5)c3 hsp43168
12 example 2. odd-tap even symmetric filter example the hsp43168 may be configured as two independent 7-tap symmetric filters with a functional block diagram shown in figure 8. again, this example shows data flow through one of the two fir cells. as in the 8-tap filter example, the hsp43168 implements the filtering operation by summing data samples sharing a common coefficient prior to multiplication by that coefficient. however, for odd length filters the pre-addition requires that the center coefficient be scaled by 1/2. the operation of the fir cell for odd length ?ters is better understood by comparing the data/coef?ient alignment in figure 9 with the data flow diagrams in figure 10. the block diagrams in figure 10 are a simpli?ation of the fir cell shown in figure 1. for odd length filters, proper data/coefficient alignment is ensured by routing data entering the last register in the third forward decimation stage to the backward shifting registers. in this configuration, the center coefficient must be scaled by 1/2 to compensate for the summation of the same data sample from both the forward and backward shifting registers. hsp43168 ina0-9 inb0-9 out9-27 fir a fir b m u x figure 8. using hsp43168 as two independent filters 7-tap even symmetric 7-tap even symmetric aa bb c0 c1 c2 c3 h(n) c2 c1 c0 x9 x8 x7 x6 x5 x4 x3 x2 x1 x0 x(n) figure 9. data/coefficient alignment for 7-tap symmetric filter 7-taps figure 10a. data flow as data sample 6 is clocked into the feed forward stage figure 10b. data flow as data sample 7 is clocked into the feed forward stage figure 10c. data flow as data sample 8 is clocked into the feed forward stage figure 10. data flow diagrams for 7-tap symmetric filter 5 4 3 6 c0 c1 c2 c3/2 0 1 2 3 + + + + + (x6+x0)c0+(x5+x1)c1+(x4+x2)c2+(x3+x3)c3/2 + + + + + 6 5 4 7 c0 c1 c2 c3/2 1 2 3 (x7+x1)c0+(x6+x2)c1+(x5+x3)c2+(x4+x4)c3/2 4 + + + + + 2 3 4 5 7 6 5 8 c0 c1 c2 c3/2 (x8+x2)c0+(x7+x3)c1+(x6+x4)c2+(x5+x5)c3/2 hsp43168
13 in the data flow diagrams of figure 10, the order of the data samples input in to the ?ter cell is shown by the numbers in the forward and backward shifting decimation paths. the output of the ?ter cell is given by the equation at the bottom of the block. the diagram in figure 10a shows data sample alignment at the pre-adders for the data/coef?ient alignment shown in figure 9. this dual ?ter application is con?ured by writing 110h to address 000h via the microprocessor interface, cin0-9, a0-8, and wr. also, data reversal must be disabled by setting bit 4 of the control register at address 0001h. as in the 8-tap example, only the unique coef?ients need to be stored in the coef?ient bank. these coef?ients are stored in the ?st coef?ient set for fir a by writing c0, c1, c2, and c3 to address 100h, 101h, 102h, and 103h respectively. to write the same ?ter to the ?st coef?ient set for fir b, the address sequence would change to 104h, 105h, 106h, and 107h. the control signals txfr, fwrd, rvrs, accen, shften, and csel0-4 are controlled as described in example 1. example 3. asymmetric filter example the fir cells within the hsp43168 can each calculate 4 asymmetric taps on each clock. thus, a single fir cell can implement an 8-tap asymmetric ?ter if the hsp43168 is clocked at twice the input data rate. similarly, if the dual is con?ured as a single ?ter, a 16-tap asymmetric ?ter is realizable. only one of the two fir cells are used in this example for the block diagram shown in figure 11. for this example, the fir cells are con?ured as two 8-tap asymmetric ?ters which are clocked at twice the input data rate. new data is shifted into the forward and backward decimation paths every other clk by the assertion of shften. the ?ter output is computed by passing data from each decimation path to the multipliers on alternating clocks. two sets of coef?ients are required, one for data on the forward decimation path, and one for data on the reverse path. the ?ter output is generated by accumulating the multiplier outputs for two clks. the operation of this con?uration is better understood by comparing the data/coef?ient alignment in figure 12 with the data flow diagrams in figure 13. the alus have been omitted from the fir cell diagrams because data is fed to the multipliers directly from the forward and reverse decimation paths. the data samples within the fir cell are shown by the numbers in the decimation paths. hsp43168 ina0-9 inb0-9 out9-27 fir a fir b m u x figure 11. using hsp43168 as two independent filters 8-tap asymmetric 8-tap asymmetric aa bb c7 c6 c5 c4 c3 c2 c1 c0 h(n) x(n) figure 12. data/coefficient alignment for 8-tap asymmetric filter 8-taps x9 x8 x7 x6 x5 x4 x3 x2 x1 x0 hsp43168
14 for this application, each filter cell is configured as an odd length filter by writing 110h to the control register at address 000h. even though an even tap filter is being implemented, the filter cells must be configured as odd length to ensure proper data flow. in addition, the filters must be set to even symmetry. also, the 4th bit at control address 001h must be set to disable data reversal, and txfr must be tied low. since an 8-tap asymmetric filter is being implemented, two sets of coefficients must be stored. these eight coefficients could be loaded into the first two coefficient sets for fir a by writing c0, c1, c2, c3, c7, c6, c5, and c4 to address 100h, 101h, 102h, 103h, 108h, 109h, 10ah, and 10bh respectively. the sum of products required for this 8-tap filter require dynamic control over fwrd, r vrs, accen, and csel0-4. the relative timing of these signals is shown in figure 14. figure 13a. data shifting disabled, backward shifting decimation registers feeding multipliers figure 13b. shifting of data sample 7 into fir cell enabled, forward shifting registers feeding multipliers figure 13c. data shifting disabled, backward shifting decimation registers feeding multipliers figure 13d. shifting of data sample 8 into fir cell enabled, forward shifting registers feeding multipliers figure 13. data flow diagrams for 8-tap asymmetric filter 6 5 4 0 1 2 3 c0 c1 c2 c3 (x0)c0+(x1)c1+(x2)c2+(x3)c3 accumulator 6 5 4 0 1 2 3 c7 c6 c5 c4 accumulator 7 (x0)c0+(x1)c1+(x2)c2+(x3)c3 +(x7)c7+(x6)c6+(x5)c5+(x4)c4 7 6 5 1 2 3 4 c0 c1 c2 c3 (x1)c0+(x2)c1+(x3)c2+(x4)c3 accumulator accumulator 76 5 1234 c7 c6 c5 c4 8 (x1)c0+(x2)c1+(x3)c2+(x4)c3 +(x8)c7+(x7)c6+(x6)c5+(x5)c4 hsp43168
15 example 4. even-tap decimating filter example the hsp43168 supports ?tering applications requiring decimation to 16. in these applications the output data rate is reduced by a factor of n. as a result, n clock cycles can be used for the computation of the ?ter output. for example, each fir cell can calculate 8 symmetric or 4 asymmetric taps in one clock. if the application requires decimation by two, the ?ter output can be calculated over two clocks thus, boosting the number of taps per fir cell to 16 symmetric or 8 asymmetric. for this example, each fir cell is con?ured as an independent 24-tap decimate x3 ?ter. again, the data ?w diagrams show only one of the fir cells shown in figure 15. the alignment of data relative to the 24 ?ter coef?ients for a particular output is depicted graphically in figure 16. as in previous examples, the hsp43168 implements the ?tering operation by summing data samples prior to multiplication by the common coef?ient. in this example an output is required every third clk which allows 3 clks for computation. on each clk, one of three sets of coef?ients are used to calculate 8 of the ?ter taps. the block diagrams in figure 17 show the data ?w and accumulator output for the data/coef?ient alignment in figure 16. proper data and coef?ient alignment is achieved by asserting txfr once every three clks to switch the lifos which are being read and written. this has the effect of feeding blocks of three samples into the backward shifting decimation path which are reversed in sample order. in addition, accen is deasserted once every three clocks to allow accumulation over three clks. the three sets of coef?ients required in the calculation of a 24-tap symmetric ?ter are cycled through using csel0-4. the timing relationship between the csel0-4, accen, and txfr are shown in figure 18. to operate in this mode the dual is con?ured by writing 1d2 to address 000h via the microprocessor interface, cin0-9, a0-8, and wr. data reversal must be enabled see (table 2). the 12 unique coef?ients for this example are stored as three sets of coef?ients for either fir cell. for fir a, the coef?ients are loaded into the coef?ient bank by writing c2, c5, c8, c11, c1, c4, c7, c10, c0, c3, c6, and c9 to address [100h, 101h, 102h, 103h], csel = 0; [108h, 109h, 10ah, 10bh], csel = 1; [110h, 111h, 112h, and 113h], csel = 2, respectively. 0 1 2 3 13 14 15 16 x0 x1 101 0 01 10 x6 x7 x8 clk ? ina0-9 csel0-4 accen shften r vrs fwrd 0 ? note that clk is 2x data rate. figure 14. control timing for 8-tap asymmetric filter txfr (tied low) figure 15. even-tap decimating filter, 24-tap dec = 3 figure 16. data/coefficient alignment for 24-tap decimate by 3 fir filter hsp43168 ina0-9 inb0-9 out9-27 fir a fir b m u x even-tap decimating even-tap decimating aa bb 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 h(n) c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 24-taps x(n) hsp43168
16 example 5. odd-tap decimating symmetric filter this example highlights the use of the hsp43168 as two independent, 23-tap, symmetric, decimate by 3 ?ters. in this example, the operational differences in the control signals and data reversal structure may be compared to the previously discussed even-tap decimating ?ter. figure 19 shows two fir cells. the data ?w in this example uses only one of the fir cells. figure 17a. computational flow as data sample 21 is clocked into the feed forward stage figure 17b. computational flow as data sample 22 is clocked into the feed forward stage figure 17c. computational flow as data sample 23 is clocked into the feed forward stage figure 17d. computational flow as data sample 24 is clocked into the feed forward stage figure 17. data flow diagrams for 24-tap decimated by 3 fir filter + + + + accumulator c2 c5 c8 c11 6 7 8 9 10 11 21 (x2+x21)c2+(x5+x18)c5+(x8+x15)c8+(x11+x12)c11 csel = 0 12 13 14 3 4 5 15 16 17 0 1 2 18 19 20 + + + + accumulator c1 c4 c7 c10 5 0 18 3 4 11 6 7 19 20 21 16 17 18 13 14 15 9 10 22 12 (x1+x22)c1+(x4x19)c4+(x7+x16)c7+(x10+x13)c10 +(x2+x21)c2+(x5+x18)c5+(x8+x15)c8+(x11+x12)c11 csel = 1 + + + + accumulator c0 c3 c6 c9 4 5 0 7 8 3 20 21 22 17 18 19 14 15 16 23 10 11 6 12 13 9 (x0+x23)c0+(x3+x20)c3+(x6+x17)c6+(x9+x14)c9 +(x1+x22)c1+(x4+x19)c4+(x7+x16)c7+(x10+x13)c10 +(x2+x21)c2+(x5+x18)c5+(x8+x15)c8+(x11+x12)c11 csel = 2 accen asserted and active txfr asserted and active + + + + accumulator c2 c5 c8 c11 3 4 56 7 8 21 22 23 18 19 20 15 16 17 24 9 10 11 13 12 (x5+x24)c0+(x8+x21)c5+(x11+x18)c8+(x14+x15)c11 14 csel = 0 0123 5 21 22 23 0 012 0 clk ina0-9 csel0-4 accen txfr 123 4 5 4 22 23 21 1 2 012 ? tied low. figure 18. control signal timing for 24-tap decimate x3 filter fwrd ? r vrs ? shiften ? hsp43168 ina0-9 inb0-9 out9-27 fir a fir b m u x figure 19. using hsp43168 as two independent filters odd-tap decimating odd-tap decimating aa bb hsp43168
17 as in the 24-tap example, an output is required every third clk which allows 3 clks for computation. on each clk, one of three sets of coef?ients are used to calculate the ?ter taps. since this is an odd length ?ter, the center coef?ient must be scaled by 1/2 to compensate for the summation of the same data sample from the forward and backward shifting decimation paths. the block diagrams in figure 20 show the data ?w, and the accumulator output for the data coef?ient alignment is shown in figure 21. proper data and coefficient alignment is achieved by asserting txfr once every three clks to switch the lifos which are being read and written. in the odd-tap mode, txfr is internally delayed by one clock cycle with respect to accen so that the convolutional sum will be computed correctly. for odd length filters, data prior to the last register in the forward decimation path is routed to the feedback circuitry. as a result, txfr should be asserted one cycle prior to the input data samples which align with the center tap. the timing relationship between the csel0-5, accen, and txfr are shown in figure 22. figure 20a. computational flow as data sample 21 is clocked into the feed forward stage txfr takes affect on this clock cycle figure 20b. computational flow as data sample 22 is clocked into the feed forward stage figure 20c. computational flow as data sample 23 is clocked into the feed forward stage figure 20d. computational flow as data sample 24 is clocked into the feed forward stage txfr takes affect on this clock cycle figure 20. data flow diagrams for 23-tap decimate by 3 symmetric filter + + + + accumulator c2 c5 c8 c11/2 1 2 34 5 6 18 19 20 15 16 17 12 13 14 21 (x3+x21)c2+(x6+x18)c5+(x9+x15)c8+(x12+x12)c11/2 7 8 91110 12 csel = 0 + + + + accumulator c1 c4 c7 c10 6 1 29 4 5 12 7 8 19 20 21 16 17 18 13 14 15 10 11 22 13 (x2+x22)c1+(x5+x19)c4+(x8+x16)c7+(x11+x13)c10 +(x3+x21)c2+(x6+x18)c5+(x9+x15)c8+(x12+x12)c11/2 csel = 1 + + + + accumulator c0 c3 c6 c9 5 6 18 9 4 20 21 22 17 18 19 14 15 16 23 11 12 7 13 14 10 (x1+x23)c0+(x4+x20)c3+(x7+x17)c6+(x14+x10)c9 +(x2+x22)c1+(x5+x19)c4+(x8+x16)c7+(x11+x13)c10 +(x3+x21)c2+(x6+x18)c5+(x9+x15)c8+(x12+x12)c11/2 accen asserted and active txfr asserted csel = 2 + + + + accumulator c2 c5 c8 c11/2 4 5 67 8 9 21 22 23 18 19 20 15 16 17 24 10 11 12 14 13 (x6+x24)c2+(x9+x21)c5+(x12+x18)c8+(x15+x15)c11/2 15 csel = 0 hsp43168
18 to operate in this mode, the dual is con?ured by writing 112h to address 000h via the microprocessor interface, cin0-9, a0-8, and wr. data reversal must be enabled (see table 2). the 12 unique coef?ients for this example are stored as three sets of coef?ients for either fir cell. for fir a, the coef?ients are loaded into the coef?ient bank by writing [c2, c5, c8, (c11)/ 2], csel = 0; [c1, c4, c7, c10], csel = 1; [c0, c3, c6, and c9], csel = 2; to address 100h, 101h, 102h, 103h, 108h, 109h, 10ah, 10bh, 110h, 111h, 112h, and 113h, respectively. example 6. dual decimation example the purpose of this example is to give an overview of one of the more complex applications of the hsp43168. the input is two data streams (a) and (b) samples. figure 23 shows the upper level block diagram of the system being implemented. the decimation rate was set to n. n-1 is loaded into the decimation factor in control word 000h. to demonstrate the muxed decimation, lets suppose that the application requires ?ter a to be con?ured as an even-decimate-by-3 ?ter and ?ter b to be con?ured as a odd-decimate-by-3 ?ter. the output data is made of the two decimated data streams multiplexed together and has a data rate equal to 2 times the input sampling rate divided by the decimation factor. figure 24 shows the data/coef?ient alignment for fir a and fir b. to operate in this mode, control word 000h must be written with a 0x152. data reversal must be enabled by setting bit 4 of control word 001h = 0. the ?ter set selected by csel0-4 = 0 should be loaded by writing c2, c5, c8, c11, d2, d5, d8, and (d11)/ 2 into 100h, 101h, 102h, 103h, 104h, 105h, 106h, and 107h. the ?ter set selected by csel0-4 = 1 should be loaded by writing c1, c4, c7, c10, d1, d4, d7, and d10 into 108h, 109h, 10ah, 10bh, 10ch, 10dh, 10eh, and 10fh. the ?ter set selected by csel0-4 = 2 should be loaded by writing c0, c3, c6, c9, d0, d3, d6, and d9 into 110h, 111h, 112h, 113h, 114h, 115h, 116h, and 117h. c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 c11 figure 21. data/coefficient alignment for 23-tap decimate by 3 symmetric filter h(n) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x(n) 23-taps 0123 5 20 21 22 0 012 0 clk ina0-9 csel0-4 accen txfr 123 4 5 4 22 23 21 1 2 012 ? tied low. figure 22. control signal timing for 23-tap symmetric filter fwrd ? r vrs ? shiften ? a3, a2, a1, a0 b3, b2, b1, b0 hsp43168 inb0-9 ina0-9 f s decimate by n 2f s /(n+1) out9-27 aout1 bout0 aout0 bout1 figure 23. multiplexed decimation block diagram hsp43168
19 figure 25 shows the timing diagram required to obtained the multiplexed/decimated output. the output of the two filters are provided at by selecting the odd-decimation filter first, then the even-decimation second using mux0-1. figure 26 shows the data flow diagram for the multiplexed decimation example. h2(n) firb fira figure 24. data/coefficient alignment for multiplexed decimation example d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d11 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 10 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 h1(n) c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 23-taps b(n) 24-taps a(n) 0123 5 20 21 22 0 012 0 clk ina0-9 csel0-4 txfr 123 4 5 4 21 22 20 1 2 201 11 10 11 11 11 10 mux0-1 accen figure 25. timing diagram for multiplexed decimation example figure 26a. computational flow as data sample 21 is clocked into the feed forward stage figure 26b. computational flow as data sample 22 is clocked into the feed forward stage + + + + accumulator d2 d5 d8 d11/2 1 2 34 5 6 18 19 20 15 16 17 12 13 14 21 7 8 91110 12 csel = 0 (x3+x21)d2+(x6+x18)d5+(x9+x15)d8+(x12+x12)d11/2 b data fir b + + + + accumulator c2 c5 c8 c11 6 7 8 9 10 11 21 csel = 0 12 13 14 3 4 5 15 16 17 0 1 2 18 19 20 (x2+x21)c2+(x5+x18)c5+(x8+x15)c8+(x11+x12)c11 fir a stream a data stream + + + + accumulator d1 d4 d7 d10 6 1 29 4 5 12 7 8 19 20 21 16 17 18 13 14 15 10 11 22 13 csel = 1 (x2+x22)d1+(x5+x19)d4+(x8+x16)d7+(x11+x13)d10 +(x3+x21)d2+(x6+x18)d5+(x9+x15)d8+(x12+x12)d11/2 fir b + + + + accumulator c1 c4 c7 c10 5 0 18 3 4 11 6 7 19 20 21 16 17 18 13 14 15 9 10 22 12 csel = 1 (x1+x22)c1+(x4x19)c4+(x7+x16)c7+(x10+x13)c10 +(x2+x21)c2+(x5+x18)c5+(x8+x15)c8+(x11+x12)c11 fir a hsp43168
20 figure 26c. computational flow as data sample 23 is clocked into the feed forward stage figure 26d. computational flow as data sample 24 is clocked into the feed forward stage figure 26. data flow diagram for multiplexed decimation example + + + + accumulator d0 d3 d6 d9 5 6 18 9 4 20 21 22 17 18 19 14 15 16 23 11 12 7 13 14 10 output of b is sent to out9-27 csel = 2 fir b (x1+x23)d0+(x4+x20)d3+(x7+x17)d6+(x14+x10)d9 +(x2+x22)d1+(x5+x19)d4+(x8+x16)d7+(x11+x13)d10 +(x3+x21)d2+(x6+x18)d5+(x9+x15)d8+(x12+x12)d11/2 + + + + accumulator c0 c3 c6 c9 4 5 07 8 3 20 21 22 17 18 19 14 15 16 23 10 11 6 12 13 9 csel = 2 (x0+x23)c0+(x3+x20)c3+(x6+x17)c6+(x9+x14)c9 +(x1+x22)c1+(x4+x19)c4+(x7+x16)c7+(x10+x13)c10 +(x2+x21)c2+(x5+x18)c5+(x8+x15)c8+(x11+x12)c11 fir a + + + + accumulator d2 d5 d8 d11/2 4 5 67 8 9 21 22 23 18 19 20 15 16 17 24 10 11 12 14 13 (x6+x24)d2+(x9+x21)d5+(x12+x18)d8+(x15+x15)d11/2 15 csel = 0 fir b + + + + accumulator c2 c5 c8 c11 3 4 56 7 8 21 22 23 18 19 20 15 16 17 24 9 10 11 13 12 14 csel = 0 (x5+x24)c0+(x8+x21)c5+(x11+x18)c8+(x14+x15)c11 output of a is sent to out9-27 fir a hsp43168
21 absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0v input, output or i/o voltage . . . . . . . . . . . . gnd -0.5v to v cc +0.5v esd classi?ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 operating conditions voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v 5% temperature range, commercial . . . . . . . . . . . . . . . . . 0 o c to 70 o c temperature range, industrial. . . . . . . . . . . . . . . . . . . .-40 o c to 85 o die characteristics back side potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v number of transistors or gates . . . . . . . . . . . . . . . . . . . . . . . . 32529 thermal resistance (typical, note 1) ja ( o c/w) jc ( o c/w) cpga package . . . . . . . . . . . . . . . . . . 35 6 mqfp package . . . . . . . . . . . . . . . . . . 33.0 n/a plcc package. . . . . . . . . . . . . . . . . . . 23.0 n/a maximum junction temperature cpga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 o c mqfp and plcc packages. . . . . . . . . . . . . . . . . . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (mqfp and plcc - leads tips only) caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. ja is measured with the component mounted on an evaluation pc board in free air. dc electrical speci?ations parameter symbol test conditions min max units power supply current i ccop v cc = max clk frequency 33mhz notes 3, 4, 5 - 363 ma standby power supply current i ccsb v cc = max, outputs not loaded - 500 a input leakage current i i v cc = max, input = 0v or v cc -10 10 a output leakage current i o v cc = max, input = 0v or v cc -10 10 a logical one input voltage v ih v cc = max 2.0 - v logical zero input voltage v il v cc = min - 0.8 v logical one output voltage v oh i oh = -400 a, v cc = min 2.6 - v logical zero output voltage v ol i ol = 2ma, v cc = min - 0.4 v clock input high v ihc v cc = max 3.0 - v clock input low v ilc v cc = min - 0.8 v input capacitance c in clk frequency 1mhz all measurements referenced to gnd. t a = 25 o c, note 2 -12pf output capacitance c out -12pf notes: 2. controlled via design or process parameters and not directly tested. characterized upon initial design and after major process and/or changes. 3. power supply current is proportional to operating frequency. typical rating for i ccop is 11ma/mhz. 4. output load per test load circuit and c l = 40pf. 5. maximum junction temperature must be considered when operating part at high clock frequencies. hsp43168
22 ac test load circuit note: test head capacitance. ac electrical speci?ations v cc = +4.75v to +5.25v, t a = 0 o c to 70 o c commercial, t a = -40 o c to 85 o c industrial (note 6) parameter symbol notes -33 (33mhz) -40 (40.8mhz) -45 (45mhz) units min max min max min max clk period t cp 30 - 24.5 - 22 - ns clk high t ch 12 - 10 - 8 - ns clk low t cl 12 - 10 - 8 - ns wr period t wp 30 - 24.5 - 22 - ns wr high t wh 12 - 10 - 10 - ns wr low t wl 12 - 10 - 10 - ns setup time a0-8 to wr going low t aws 10 - 8 - 8 - ns hold time a0-8 from wr going high t awh 0-0-0- ns setup time cin0-9 to wr going high t cws 12 - 11 - 10 - ns hold time cin0-9 from wr going high t cwh 1-1-1- ns setup time wr low to clk low t wlcl note 7 5 - 4 - 3 - ns setup time cin0-9 to clk low t cvcl note 7 7 - 7 - 7 - ns setup time csel0-5, shften, fwrd, r vrs, txfr, ina0-9, inb0-9, accen, mux0-1 to clk going high t ecs 15 - 13 - 12 - ns hold time csel0-5, shften, fwrd, r vrs, txfr, ina0-9, inb0-9, accen, mux0-1 to clk going high t ech 0-0-0- ns clk to output delay out0-27 t do -14-13-12ns output enable time t oe -12-12-12ns output disable time t od note 8 - 12 - 12 - 12 ns output rise, fall time t rf note 8 - 6 - 6 - 6 ns notes: 6. ac tests performed with c l = 40pf, i ol = 2ma, and i oh = -400 a. input reference level clk = 2.0v. input reference level for all other inputs is 1.5v. test v ih = 3.0v, v ihc = 4.0v, v il = 0v, v ilc = 0v. 7. setup time requirement for loading of data on cin0-9 to guarantee recognition on the following clock. 8. controlled via design or process parameters and not directly tested. characterized upon initial design and after major proces s and/or changes. equivalent circuit c l (note) i oh 1.5v i ol dut switch s1 open for i ccsb and i ccop s 1 hsp43168
23 waveforms figure 27. output enable, disable timing figure 28. output rise and fall times t ecs t ech t do clk out0 - 27 t wh t wl t wp wr t wlcl t aws t awh a0 - 8 t cwh t cws cin0 - 9 t cvcl t cp t cl t ch csel0 - 4, mux0 - 1 ina0 - 9, inb0 - 9, accen shften, fwrd r vrs, txfr 1.5v 1.7v 1.3v 1.5v high impedance high impedance out0 - 27 oel, oeh t oe t od t rf 2.0v 0.8v 2.0v 0.8v t rf hsp43168
24 hsp43168 metric plastic quad flatpack packages (mqfp) d d1 e e1 -a- pin 1 a2 a1 a 12 o -16 o 12 o -16 o 0 o -7 o 0.40 0.016 min l 0 o min plane b 0.005/0.009 0.13/0.23 with plating base metal seating 0.005/0.007 0.13/0.17 b1 -b- e 0.008 0.20 a-b s d s c m 0.076 0.003 -c- -d- -h- q100.14x20 (jedec ms-022gc-1 issue b) 100 lead metric plastic quad flatpack package symbol inches millimeters notes min max min max a - 0.134 - 3.40 - a1 0.010 - 0.25 - - a2 0.101 0.113 2.57 2.87 - b 0.009 0.015 0.22 0.38 6 b1 0.009 0.013 0.22 0.33 - d 0.908 0.918 23.08 23.32 3 d1 0.782 0.792 19.88 20.12 4, 5 e 0.673 0.681 17.10 17.30 3 e1 0.547 0.555 13.90 14.10 4, 5 l 0.029 0.040 0.73 1.03 - n 100 100 7 e 0.026 bsc 0.65 bsc - nd 30 30 - ne 20 20 - rev. 1 4/99 notes: 1. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. 2. all dimensions and tolerances per ansi y14.5m-1982. 3. dimensions d and e to be determined at seating plane . 4. dimensions d1 and e1 to be determined at datum plane . 5. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25mm (0.010 inch) per side. 6. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. ??is the number of terminal positions. -c- -h-
25 ceramic pin grid array packages (cpga) index corner e1 e ? ? s d1 see note 9 c s s1 b b1 ? a e 0.008 c b b a see note 7 a l a1 q c 0.010 c a 0.030 b b l a1 q k seating plane at standoff d m m m m section b-b b2 section a-a g84.a mil-std-1835 cmga3-p84c (p-ac) 84 lead ceramic pin grid array package symbol inches millimeters notes min max min max a 0.215 0.345 5.46 8.76 - a1 0.070 0.145 1.78 3.68 3 b 0.016 0.0215 0.41 0.55 8 b1 0.016 0.020 0.41 0.51 - b2 0.042 0.058 1.07 1.47 4 c - 0.080 - 2.03 - d 1.140 1.180 28.96 29.97 - d1 1.000 bsc 25.4 bsc - e 1.140 1.180 28.96 29.97 - e1 1.000 bsc 25.4 bsc - e 0.100 bsc 2.54 bsc 6 k 0.008 ref 0.20 ref - l 0.120 0.140 3.05 3.56 - q 0.040 0.060 1.02 1.52 5 s 0.000 bsc 0.00 bsc 10 s1 0.003 - 0.08 - - m11 111 n - 121 - 121 2 rev. 1 6/28/95 notes: 1. ??represents the maximum pin matrix size. 2. ? represents the maximum allowable number of pins. number of pins and location of pins within the matrix is shown on the pinout listing in this data sheet. 3. dimension ?1 includes the package body and lid for both cav- ity-up and cavity-down configurations. this package is cavity up. dimension ?1 does not include heatsinks or other attached features. 4. standoffs are intrinsic and shall be located on the pin matrix di- agonals. the seating plane is defined by the standoffs at dimen- sions q. 5. dimension ??applies to cavity-up configurations only. 6. all pins shall be on the 0.100 inch grid. 7. datum c is the plane of pin to package interface for both cavity up and down configurations. 8. pin diameter includes solder dip or custom finishes. pin tips shall have a radius or chamfer. 9. corner shape (chamfer, notch, radius, etc.) may vary from that shown on the drawing. the index corner shall be clearly unique. 10. dimension ??is measured with respect to datums a and b. 11. dimensioning and tolerancing per ansi y14.5m - 1982. 12. controlling dimension: inch. hsp43168
26 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (407) 724-7000 fax: (407) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 hsp43168 plastic leaded chip carrier packages (plcc) notes: 1. controlling dimension: inch. converted millimeter dimensions are not necessarily exact. 2. dimensions and tolerancing per ansi y14.5m-1982. 3. dimensions d1 and e1 do not include mold protrusions. allowable mold protrusion is 0.010 inch (0.25mm) per side. dimensions d1 and e1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. to be measured at seating plane contact point. 5. centerline to be determined where center leads exit plastic body. 6. ??is the number of terminal positions. -c- a1 a seating plane 0.020 (0.51) min view ? d2/e2 0.025 (0.64) 0.045 (1.14) r 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) tp e e1 0.042 (1.07) 0.048 (1.22) pin (1) identifier c l d1 d 0.020 (0.51) max 3 plcs 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) min 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) min view ??typ. 0.004 (0.10) c -c- d2/e2 c l n84.1.15 (jedec ms-018af issue a) 84 lead plastic leaded chip carrier package symbol inches millimeters notes min max min max a 0.165 0.180 4.20 4.57 - a1 0.090 0.120 2.29 3.04 - d 1.185 1.195 30.10 30.35 - d1 1.150 1.158 29.21 29.41 3 d2 0.541 0.569 13.75 14.45 4, 5 e 1.185 1.195 30.10 30.35 - e1 1.150 1.158 29.21 29.41 3 e2 0.541 0.569 13.75 14.45 4, 5 n84 846 rev. 2 11/97

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