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ds004-1.0 oct01 cygnal integrated products, inc. ? 2001 page 1 preliminary ultra small isp flash mcu family c8051f300/1/2/3 analog peripherals - 8-bit adc ? up to 500 ksps ? up to 8 external inputs ? programmable amplifier gains of 4, 2, 1, & 0.5 ? vref fromexternal pin or vdd ? built-in temperature sensor ( 3c) ? external conversion start input - comparator ? programmable hysteresis and response time ? configurable as interrupt or reset source ? low current ( < 0.5a) on-chip debug - on-chip debug circuitry facilitates full speed, non-intrusive in-systemdebug (no emulator required!) - provides breakpoints, single stepping, inspect/modify memory and registers - superior performance to emulation systems using ice-chips, target pods, and sockets - complete development kit: $99 supply voltage 2.7v to 3.6v - typical operating current: 5ma @ 25 mhz; 11 a @ 32 khz - typical stop mode current: 0.1 a - temperature range: -40c to +85c high speed8051 c core - pipe-lined instruction architecture; executes 70% of instructions in 1 or 2 systemclocks - up to 25 mips throughput with 25 mhz clock - expanded interrupt handler memory - 256 bytes internal data ram - 8k bytes flash; in-system programmable in 512 byte sectors digital peripherals - 8 port i/o; all 5 v tolerant with high sink current - hardware enhanced uart and smbus? serial ports - three general purpose 16-bit counter/timers - 16-bit programmable counter array (pca) with three capture/compare modules - real time clock mode using pca or timer and external clock source clock sources - internal oscillator: 24.5 mhz with 2% accuracy sup- ports uart operation - external oscillator: crystal, rc, c, or clock (1 or 2 pin modes) - canswitchbetweenclocksourceson-the-fly;usefulin power saving modes 11-pin micro leadpackage - 3x3mm pwb footprint; actual mlp size: analog peripherals 8-bit 500ksps adc pga 8kb isp flash 256 b sram por debug circuitry 12 interrupts 8051 cpu (25mips) temp sensor digital i/o programmable precision internal oscillator high-speed controller core a m u x i/o port crossbar uart smbus pca timer 0 timer 1 timer 2 voltage comparator + - wdt
page 2 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 notes
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 3 preliminary c8051f300/1/2/3 table of contents 1. system overview .........................................................................................................11 1.1. cip-51? microcontroller core ......................................................................................13 1.1.1. fully 8051 compatible ..........................................................................................13 1.1.2. improved throughput ............................................................................................13 1.1.3. additional features................................................................................................14 1.2. on-chip memory ............................................................................................................15 1.3. on-chip debug circuitry ................................................................................................16 1.4. programmable digital i/o and crossbar .........................................................................17 1.5. serial ports................................................................................................................ .......17 1.6. programmable counter array .........................................................................................18 1.7. 8-bit analog to digital converter (c8051f300/2 only) ................................................19 1.8. comparator ................................................................................................................. .....20 2. absolute maximum ratings ..................................................................................21 3. global dc electrical characteristics ......................................................21 4. pinout andpackage definitions........................................................................22 5. adc0 (8-bit adc, c8051f300/2 only) ..........................................................................25 5.1. analog multiplexer and pga..........................................................................................26 5.2. modes of operation.........................................................................................................27 5.2.1. starting a conversion.............................................................................................27 5.2.2. tracking modes .....................................................................................................28 5.2.3. settling time requirements ..................................................................................29 5.3. programmable window detector ....................................................................................33 5.3.1. window detector in single-ended mode .............................................................33 5.3.2. window detector in differential mode.................................................................34 6. voltage reference (c8051f300/2)..........................................................................37 7. comparator0 .................................................................................................................. 39 8. cip-51 microcontroller..........................................................................................45 8.1. instruction set ......................................................................................................47 8.1.1. instruction and cpu timing..................................................................................47 8.1.2. movx instruction and programmemory.............................................................47 8.2. memory organization........................................................................................51 8.2.1. programmemory ...................................................................................................51 8.2.2. data memory .........................................................................................................51 8.2.3. general purpose registers .....................................................................................52 8.2.4. bit addressable locations .....................................................................................52 8.2.5. stack ...................................................................................................................5 2 8.2.6. special function registers.....................................................................................52 8.2.7. register descriptions .............................................................................................55 8.3. interrupt handler ........................................................................................................... ..58 8.3.1. mcu interrupt sources and vectors .....................................................................58 8.3.2. external interrupts .................................................................................................59 8.3.3. interrupt priorities..................................................................................................59 8.3.4. interrupt latency....................................................................................................59
page 4 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 8.3.5. interrupt register descriptions ..............................................................................61 8.4. power management modes .............................................................................................66 8.4.1. idle mode ...............................................................................................................66 8.4.2. stop mode..............................................................................................................66 9. reset sources ................................................................................................................6 9 9.1. power-on reset.............................................................................................................. .70 9.2. power-fail reset / vdd monitor....................................................................................70 9.3. external reset.............................................................................................................. ....71 9.4. missing clock detector reset .........................................................................................71 9.5. comparator0 reset ..........................................................................................................7 1 9.6. pca watchdog timer reset ...........................................................................................71 9.7. flash error reset .........................................................................................................71 9.8. software reset.............................................................................................................. ...71 10. flash memory ................................................................................................................7 5 10.1. programming the flash memory ...............................................................................75 10.1.1. flash lock and key functions ..........................................................................75 10.1.2. flash erase procedure........................................................................................75 10.1.3. flash write procedure .......................................................................................76 10.2.non-volatile data storage ...............................................................................................77 10.3. security options ........................................................................................................... ...77 11. oscillators................................................................................................................. ....79 11.1. programmable internal oscillator ...................................................................................79 11.1.1. programming the internal oscillator on c8051f300/1 devices ...........................80 11.1.2. programming the internal oscillator on C8051F302/3 devices ...........................80 11.2. external oscillator drive circuit.....................................................................................82 11.3. systemclock selection...................................................................................................82 11.4. external crystal example................................................................................................84 11.5. external rc example ......................................................................................................84 11.6. external capacitor example............................................................................................84 12. port input/output .......................................................................................................85 12.1. priority crossbar decoder ...............................................................................................86 12.2.port i/o initialization..................................................................................................... ..88 12.3. general purpose port i/o.................................................................................................91 13. smbus....................................................................................................................... .............93 13.1. supporting documents ....................................................................................................94 13.2. smbus configuration......................................................................................................94 13.3. smbus operation ............................................................................................................ 95 13.3.1. arbitration............................................................................................................. .95 13.3.2. clock low extension.............................................................................................96 13.3.3. scl low timeout .................................................................................................96 13.3.4. scl high (smbus free) timeout.........................................................................96 13.4. using the smbus............................................................................................................. 97 13.4.1. smbus configuration register..............................................................................98 13.4.2. smb0cn control register ..................................................................................101 13.4.3. data register........................................................................................................104
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 5 preliminary c8051f300/1/2/3 13.5. smbus transfer modes.................................................................................................105 13.5.1. master transmitter mode ....................................................................................105 13.5.2. master receiver mode.........................................................................................106 13.5.3. slave receiver mode ...........................................................................................107 13.5.4. slave transmitter mode.......................................................................................108 13.6. smbus status decoding................................................................................................109 14. uart0 ....................................................................................................................... ...........111 14.1. enhanced baud rate generation...................................................................................112 14.2. operational modes ........................................................................................................11 3 14.2.1. 8-bit uart .........................................................................................................113 14.2.2. 9-bit uart .........................................................................................................114 14.3. multiprocessor communications...................................................................................115 15. timers...................................................................................................................... ..........121 15.1. timer 0 and timer 1......................................................................................................121 15.1.1. mode 0: 13-bit counter/timer.............................................................................121 15.1.2. mode 1: 16-bit counter/timer.............................................................................122 15.1.3. mode 2: 8-bit counter/timer with auto-reload .................................................123 15.1.4. mode 3: two 8-bit counter/timers (timer 0 only) ...........................................124 15.2. timer 2 .................................................................................................................... ...129 15.2.1. 16-bit timer with auto-reload ...........................................................................129 15.2.2. 8-bit timers with auto-reload............................................................................130 16. programmable counter array .......................................................................133 16.1. pca counter/timer.......................................................................................................134 16.2. capture/compare modules............................................................................................135 16.2.1. edge-triggered capture mode .............................................................................136 16.2.2. software timer (compare) mode........................................................................137 16.2.3. high speed output mode ....................................................................................138 16.2.4. frequency output mode ......................................................................................139 16.2.5. 8-bit pulse width modulator mode ....................................................................140 16.2.6. 16-bit pulse width modulator mode ..................................................................141 16.3. watchdog timer mode..................................................................................................142 16.3.1. watchdog timer operation .................................................................................142 16.3.2. watchdog timer usage .......................................................................................143 16.4. register descriptions for pca ......................................................................................144 17. c2 interface ................................................................................................................. .149 17.1. c2 interface registers ...................................................................................................149 17.2. c2 pin sharing.............................................................................................................. .151
page 6 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 notes
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 7 preliminary c8051f300/1/2/3 list of figures andtables 1. system overview table 1.1. product selection guide ......................................................................................11 figure 1.1. c8051f300/2 block diagram..............................................................................12 figure 1.2. c8051f301/3 block diagram..............................................................................12 figure 1.3. comparison of peak mcu execution speeds.....................................................13 figure 1.4. on-chip clock and reset....................................................................................14 figure 1.5. on-board memory map ......................................................................................15 figure 1.6. development/in-system debug diagram ...........................................................16 figure 1.7. digital crossbar diagram....................................................................................17 figure 1.8. pca block diagram............................................................................................18 figure 1.9. pca block diagram............................................................................................18 figure 1.10. 8-bit adc block diagram..................................................................................19 figure 1.11. comparator block diagram ................................................................................20 2. absolute maximum ratings table 2.1. absolute maximum ratings*..............................................................................21 3. global dc electrical characteristics table 3.1. global dc electrical characteristics...................................................................21 4. pinout andpackage definitions table 4.1. pin definitions for the c8051f300/1/2/3 ............................................................22 figure 4.1. mlp-11 pinout diagram(top view) .................................................................23 figure 4.2. mlp-11 package drawing ..................................................................................24 5. adc0 (8-bit adc, c8051f300/2 only) figure 5.1. adc0 functional block diagram.......................................................................25 figure 5.2. temperature sensor transfer function ...............................................................27 figure 5.3. 8-bit adc track and conversion example timing...........................................28 figure 5.4. adc0 equivalent input circuits .........................................................................29 figure 5.5. amx0sl: amux0 channel select register (c8051f300/2)............................30 figure 5.6. adc0cf: adc0 configuration register (c8051f300/2)..................................31 figure 5.7. adc0: adc0 data word register (c8051f300/2) ...........................................31 figure 5.8. adc0cn: adc0 control register (c8051f300/2) ...........................................32 figure 5.9. adc window compare examples, single-ended mode ...................................33 figure 5.10. adc window compare examples, differential mode ......................................34 figure 5.11. adc0gt: adc0 greater-than data byte register (c8051f300/2) .................35 figure 5.12. adc0lt: adc0 less-than data byte register (c8051f300/2) ......................35 table 5.1. adc0 electrical characteristics..........................................................................36 6. voltage reference (c8051f300/2) figure 6.1. voltage reference functional block diagram....................................................37 figure 6.2. ref0cn: reference control register ................................................................38 table 6.1. external voltage reference circuit electrical characteristics ...........................38 7. comparator0 figure 7.1. comparator0 functional block diagram ............................................................39 figure 7.2. comparator hysteresis plot.................................................................................40 figure 7.3. cpt0cn: comparator0 control register ...........................................................41
page 8 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 figure 7.4. cpt0mx: comparator0 mux selection register..............................................42 figure 7.5. cpt0md: comparator0 mode selection register..............................................43 table 7.1. comparator0 electrical characteristics...............................................................44 8. cip-51 microcontroller figure 8.1. cip-51 block diagram........................................................................................45 table 8.1. cip-51 instruction set summary.........................................................................47 figure 8.2. memory map .......................................................................................................51 table 8.2. special function register (sfr) memory map..................................................53 table 8.3. special function registers ..................................................................................53 figure 8.3. dpl: data pointer low byte ..............................................................................55 figure 8.4. dph: data pointer high byte .............................................................................55 figure 8.5. sp: stack pointer .................................................................................................56 figure 8.6. psw: programstatus word ................................................................................56 figure 8.7. acc: accumulator..............................................................................................57 figure 8.8. b: b register .......................................................................................................57 table 8.4. interrupt summary...............................................................................................60 figure 8.9. ie: interrupt enable .............................................................................................61 figure 8.10. ip: interrupt priority ............................................................................................62 figure 8.11. eie1: extended interrupt enable 1 .....................................................................63 figure 8.12. eip1: extended interrupt priority 1.....................................................................64 figure 8.13. int01cf: int0/int1 configuration register ...................................................65 figure 8.14. pcon: power control register ..........................................................................67 9. reset sources figure 9.1. reset sources.......................................................................................................69 figure 9.2. power-on and vdd monitor reset timing .......................................................70 figure 9.3. rstsrc: reset source register.........................................................................72 table 9.1. reset electrical characteristics ...........................................................................73 10. flash memory table 10.1. flash electrical characteristics .......................................................................76 figure 10.1. psctl: programstore r/w control ..................................................................77 figure 10.2. flkey: flash lock and key register ...........................................................78 figure 10.3. flscl: flash scale register ..........................................................................78 11. oscillators figure 11.1. oscillator diagram..............................................................................................79 figure 11.2. oscicl: internal oscillator calibration register ..............................................81 figure 11.3. oscicn: internal oscillator control register ...................................................81 table 11.1. internal oscillator electrical characteristics.......................................................82 figure 11.4. oscxcn: external oscillator control register.................................................83 12. port input/output figure 12.1. port i/o functional block diagram....................................................................85 figure 12.2. port i/o cell block diagram...............................................................................85 figure 12.3. crossbar priority decoder with xbar0 = 0x00.................................................86 figure 12.4. crossbar priority decoder with xbr0 = 0x44 ...................................................87 figure 12.5. xbr0: port i/o crossbar register 0 ...................................................................89 figure 12.6. xbr1: port i/o crossbar register 1 ...................................................................89
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 9 preliminary c8051f300/1/2/3 figure 12.7. xbr2: port i/o crossbar register 2 ...................................................................90 figure 12.8. p0: port0 register................................................................................................91 figure 12.9. p0mdin: port0 input mode register .................................................................91 figure 12.10. p0mdout: port0 output mode register.........................................................92 table 12.1. port i/o dc electrical characteristics ................................................................92 13. smbus figure 13.1. smbus block diagram.......................................................................................93 figure 13.2. typical smbus configuration ............................................................................94 figure 13.3. smbus transaction .............................................................................................95 table 13.1. smbus clock source selection...........................................................................98 figure 13.4. typical smbus scl generation.........................................................................98 table 13.2. minimum sda setup and hold times ...............................................................99 figure 13.5. smb0cf: smbus clock/configuration register .............................................100 figure 13.6. smb0cn: smbus control register .................................................................102 table 13.3. sources for hardware changes to smb0cn ....................................................103 figure 13.7. smb0dat: smbus data register ...................................................................104 figure 13.8. typical master transmitter sequence...............................................................105 figure 13.9. typical master receiver sequence ...................................................................106 figure 13.10. typical slave receiver sequence ...................................................................107 figure 13.11. typical slave transmitter sequence ...............................................................108 table 13.4. smbus status decoding....................................................................................109 14. uart0 figure 14.1. uart0 block diagram.....................................................................................111 figure 14.2. uart0 baud rate logic ..................................................................................112 figure 14.3. uart interconnect diagram............................................................................113 figure 14.4. 8-bit uart timing diagram ...........................................................................113 figure 14.5. 9-bit uart timing diagram ...........................................................................114 figure 14.6. uart multi-processor mode interconnect diagram.......................................115 figure 14.7. scon0: serial port 0 control register.............................................................116 figure 14.8. sbuf0: serial (uart0) port data buffer register .........................................117 table 14.1. timer settings for standard baud rates using the internal oscillator ...........118 table 14.2. timer settings for standard baud rates using an external oscillator.............118 table 14.3. timer settings for standard baud rates using an external oscillator.............119 table 14.4. timer settings for standard baud rates using an external oscillator.............119 table 14.5. timer settings for standard baud rates using an external oscillator.............120 table 14.6. timer settings for standard baud rates using an external oscillator.............120 15. timers figure 15.1. t0 mode 0 block diagram................................................................................122 figure 15.2. t0 mode 2 block diagram................................................................................123 figure 15.3. t0 mode 3 block diagram................................................................................124 figure 15.4. tcon: timer control register.........................................................................125 figure 15.5. tmod: timer mode register...........................................................................126 figure 15.6. ckcon: clock control register......................................................................127 figure 15.7. tl0: timer 0 low byte ....................................................................................128 figure 15.8. tl1: timer 1 low byte ....................................................................................128
page 10 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 figure 15.9. th0: timer 0 high byte ...................................................................................128 figure 15.10. th1: timer 1 high byte .................................................................................128 figure 15.11. timer 2 16-bit mode block diagram .............................................................129 figure 15.12. timer 2 8-bit mode block diagram ...............................................................130 figure 15.13. tmr2cn: timer 2 control register ..............................................................131 figure 15.14. tmr2rll: timer 2 reload register low byte ............................................132 figure 15.15. tmr2rlh: timer 2 reload register high byte ...........................................132 figure 15.16. tmr2l: timer 2 low byte ............................................................................132 figure 15.17. tmr2h timer 2 high byte ............................................................................132 16. programmable counter array figure 16.1. pca block diagram..........................................................................................133 figure 16.2. pca counter/timer block diagram .................................................................134 table 16.1. pca timebase input options............................................................................134 figure 16.3. pca interrupt block diagram...........................................................................135 table 16.2. pca0cpm register settings for pca capture/compare modules..................135 figure 16.4. pca capture mode diagram............................................................................136 figure 16.5. pca software timer mode diagram................................................................137 figure 16.6. pca high speed output mode diagram..........................................................138 figure 16.7. pca frequency output mode ...........................................................................139 figure 16.8. pca 8-bit pwm mode diagram......................................................................140 figure 16.9. pca 16-bit pwm mode ...................................................................................141 figure 16.10. pca module 2 with watchdog timer enabled ..............................................142 table 16.3. watchdog timer timeout intervals ..................................................................143 figure 16.11. pca0cn: pca control register ....................................................................144 figure 16.12. pca0md: pca mode register ......................................................................145 figure 16.13. pca0cpmn: pca capture/compare mode registers ...................................146 figure 16.14. pca0l: pca counter/timer low byte .........................................................147 figure 16.15. pca0h: pca counter/timer high byte ........................................................147 figure 16.16. pca0cpln: pca capture module low byte ................................................148 figure 16.17. pca0cphn: pca capture module high byte ...............................................148 17. c2 interface figure 17.1. c2add: c2 address register ..........................................................................149 figure 17.2. deviceid: c2 device id register .................................................................149 figure 17.3. revid: c2 revision id register .....................................................................150 figure 17.4. fpctl: c2 flash programming control register ........................................150 figure 17.5. fpdat: c2 flash programming data register ............................................150 figure 17.6. typical c2 pin sharing .....................................................................................151
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 11 preliminary c8051f300/1/2/3 1. system overview c8051f300/1/2/3 devices are fully integrated mixed-signal system-on-a-chip mcus. highlighted features are listed below. refer to table 1.1 for specific product feature selection. ? high-speed pipelined 8051-compatible microcontroller core (up to 25 mips) ? in-system, full-speed, non-intrusive debug interface (on-chip) ? true 8-bit 500 ksps 11-channel adc with programmable gain pre-amplifier and analog multiplexer ? precision programmable 25 mhz internal oscillator ? 8k bytes of on-chip flash memory ? 256 bytes of on-chip ram ?smbus/i 2 c and enhanced uart serial interfaces implemented in hardware ? three general-purpose 16-bit timers ? programmable counter/timer array (pca) with three capture/compare modules and watchdog timer function ? on-chip power-on reset, vdd monitor, and temperature sensor ? on-chip voltage comparator ? byte-wide i/o port (5v tolerant) with on-chip power-on reset, vdd monitor, watchdog timer, and clock oscillator, the c8051f300/1/2/3 devices are truly stand-alone system-on-a-chip solutions. the flash memory can be reprogrammed even in-circuit, pro- viding non-volatile data storage, and also allowing field upgrades of the 8051 firmware. user software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings. the on-chip cygnal 2-wire (c2) development interface allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production mcu installed in the final application. this debug logic supports inspec- tion and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. all ana- log and digital peripherals are fully functional while debugging using c2. the two c2 interface pins can be shared with user functions, allowing in-systemdebugging without occupying package pins. each device is specified for 2.7 v-to-3.6 v operation over the industrial temperature range (-45c to +85c). the port i/o and /rst pins are tolerant of input signals up to 5 v. the c8051f300/1/2/3 are available in the 11-pin mlp package shown in figure 4.2. table 1.1. product selection guide mips (peak) flash memory ram calibrated internal oscillator smbus/i 2 c uart timers (16-bit) programmable counter array digital port i/os 8-bit 500ksps adc temperature sensor analog comparators package c8051f300 25 8k 256 ! ! ! 3 ! 8 ! ! 1 mlp-11 c8051f301 25 8k 256 ! ! ! 3 ! 8 - - 1 mlp-11 C8051F302 25 8k 256 - ! ! 3 ! 8 ! ! 1 mlp-11 c8051f303 25 8k 256 - ! ! 3 ! 8 - - 1 mlp-11
page 12 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 figure 1.1. c8051f300/2 block diagram port 0 latch uart 8kbyte flash 256 byte sram por sfr bus 8 0 5 1 c o r e timer 0, 1 pca/ wdt 8-bit 500ksps adc a m u x ain0-ain7 p 0 d r v vref x b a r port i/o mode & config. xbar control reset xtal1 xtal2 external oscillator circuit system clock precision internal oscillator clock & reset configuration analog/digital power debug hw vdd adc config. & control smbus x2 x4 x2 c2d c2d cp0 pga + - temp cp0 p0.0/vref p0.1 p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6/cnvstr p0.7/c2d vdd gnd /rst/c2ck brown- out vdd cnvstr figure 1.2. c8051f301/3 block diagram port 0 latch uart 8kbyte flash 256 byte sram por sfr bus 8 0 5 1 c o r e timer 0, 1 pca/ wdt p 0 d r v x b a r port i/o mode & config. xbar control reset xtal1 xtal2 external oscillator circuit system clock precision internal oscillator clock & reset configuration analog/digital power debug hw smbus x2 x4 x2 c2d c2d cp0 + - cp0 p0.0/vref p0.1 p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6 p0.7/c2d vdd gnd /rst/c2ck brown- out
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 13 preliminary c8051f300/1/2/3 1.1. cip-51? microcontroller core 1.1.1. fully 8051 compatible the c8051f300/1/2/3 family utilizes cygnal's proprietary cip-51 microcontroller core. the cip-51 is fully compati- ble with the mcs-51? instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. the cip-51 core offers all the peripherals included with a standard 8052, including two standard 16-bit counter/timers, one enhanced 16-bit counter/timer with external oscillator input, a full-duplex uart with extended baud rate configuration, 256 bytes of internal ram, 128 byte special function register (sfr) address space, and a byte-wide i/o port. 1.1.2. improved throughput the cip-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. in a standard 8051, all instructions except for mul and div take 12 or 24 systemclock cycles to exe- cute with a maximum system clock of 12-to-24 mhz. by contrast, the cip-51 core executes 70% of its instructions in one or two systemclock cycles, with only four instructions taking more than four systemclock cycles. the cip-51 has a total of 109 instructions. the table below shows the total number of instrutions that require each execution time. with the cip-51's maximum system clock at 25 mhz, it has a peak throughput of 25 mips. figure 1.3 shows a com- parison of peak throughputs for various 8-bit microcontroller cores with their maximum system clocks. clocks to execute 1 2 2/3 3 3/4 4 4/5 5 8 number of instructions 26 50 5 14 7 3 1 2 1 5 10 15 20 aduc812 8051 (16mhz clk) philips 80c51 (33mhz clk) microchip pic17c75x (33mhz clk) cygnal cip-51 (25mhz clk) mips 25 figure 1.3. comparison of peak mcu execution speeds
page 14 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 1.1.3. additional features the c8051f300/1/2/3 soc family includes several key enhancements to the cip-51 core and peripherals to improve performance and ease of use in end applications. the extended interrupt handler provides 12 interrupt sources into the cip-51 (as opposed to 7 for the standard 8051), allowing numerous analog and digital peripherals to interrupt the controller. an interrupt driven system requires less intervention by the mcu, giving it more effective throughput. the extra interrupt sources are very useful when build- ing multi-tasking, real-time systems. eight reset sources are available: power-on reset circuitry (por), an on-chip vdd monitor (forces reset when power supply voltage drops below 2.7 v), a watchdog timer, a missing clock detector, a voltage level detection from comparator0, a forced software reset, an external reset pin, and an errant flash read/write protection circuit. each reset source except for the por, reset input pin, or flash protection may be disabled by the user in software. the wdt may be permanently enabled in software after a power-on reset during mcu initialization. the internal oscillator is available as a factory calibrated 24.5 mhz 2% (c8051f300/1) or an uncalibrated 20 mhz 20% (C8051F302/3). on all c8051f300/1/2/3 devices, the internal oscillator period may be user pro- grammed in 0.5% increments. an external oscillator drive circuit is also included, allowing an external crystal, ceramic resonator, capacitor, rc, or cmos clock source to generate the systemclock. if desired, the systemclock source may be switched on-the-fly to the external oscillator circuit. an external oscillator can be extremely useful in low power applications, allowing the mcu to run froma slow (power saving) external crystal source, while periodi- cally switching to the fast (up to 25 mhz) internal oscillator as needed. pca wdt missing clock detector (one- shot) (software reset) system reset reset funnel p0.x p0.y en swrsf internal oscillator system clock cip-51 microcontroller core extended interrupt handler clock select en wdt enable mcd enable xtal1 xtal2 external oscillator drive errant flash operation + - comparator 0 c0rsef /rst (wired-or) power on reset + - vdd supply monitor enable '0' figure 1.4. on-chip clock and reset
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 15 preliminary c8051f300/1/2/3 1.2. on-chip memory the cip-51 has a standard 8051 programand data address configuration. it includes 256 bytes of data ram, with the upper 128 bytes dual-mapped. indirect addressing accesses the upper 128 bytes of general purpose ram, and direct addressing accesses the 128 byte sfr address space. the lower 128 bytes of ram are accessible via direct and indi- rect addressing. the first 32 bytes are addressable as four banks of general purpose registers, and the next 16 bytes can be byte addressable or bit addressable. program memory consists of 8k bytes of flash. this memory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip programming voltage. the 512 bytes from addresses 0x1e00 to 0x1fff are reserved for factory use. see figure 1.5 for the mcu system memory map. program memory (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function register's (direct addressing only) data memory general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 internal data address space flash (in-system programmable in 512 byte sectors) 0x0000 0x1fff reserved 0x1e00 0x1dff figure 1.5. on-board memory map
page 16 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 1.3. on-chip debug circuitry the c8051f300/1/2/3 devices include on-chip cygnal 2-wire (c2) debug circuitry that provides non-intrusive, full speed, in-circuit debugging of the production part installed in the end application. cygnal's debugging system supports inspection and modification of memory and registers, breakpoints, and single stepping. no additional target ram, program memory, timers, or communications channels are required. all the dig- ital and analog peripherals are functional and work correctly while debugging. all the peripherals (except for the adc and smbus) are stalled when the mcu is halted, during single stepping, or at a breakpoint in order to keep themsynchronized. the c8051f300dk development kit provides all the hardware and software necessary to develop application code and performin-circuit debugging with the c8051f300/1/2/3 mcus. the kit includes software with a developer's stu- dio and debugger, an integrated 8051 assembler, and an rs-232 to c2 serial adapter. it also has a target application board with the associated mcu installed and large prototyping area, plus the rs-232 and c2 cables, and wall-mount power supply. the development kit requires a windows 95/98/nt/me/2000 computer with one available rs-232 serial port. as shown in figure 1.6, the pc is connected via rs-232 to the serial adapter. a six-inch ribbon cable connects the serial adapter to the user's application board, picking up the two c2 pins and vdd and gnd. the serial adapter takes its power fromthe application board; it requires roughly 20 ma at 2.7-3.6v. for applications where there is not sufficient power available fromthe target board, the provided power supply can be connected directly to the serial adapter. the cygnal ide interface is a vastly superior developing and debugging configuration, compared to standard mcu emulators that use on-board "ice chips" and require the mcu in the application board to be socketed. cygnal's debug paradigmincreases ease of use and preserves the performance of the precision analog peripherals. target pcb rs-232 serial adapter vdd gnd c2 (x2), vdd, gnd windows 95/98/nt/me/2000 cygnal integrated development environment c8051f300 figure 1.6. development/in-system debug diagram
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 17 preliminary c8051f300/1/2/3 1.4. programmable digital i/o and crossbar c8051f300/1/2/3 devices include a byte-wide i/o port that behaves like a typical 8051 port with a few enhance- ments. each port pin may be configured as an analog input or a digital i/o pin. pins selected as digital i/os may addi- tionally be configured for push-pull or open-drain output. the weak pull-ups that are fixed on typical 8051 devices may be globally disabled, providing power savings capabilities. perhaps the most unique port i/o enhancement is the digital crossbar. this is essentially a digital switching network that allows mapping of internal digital system resources to port i/o pins (see figure 1.7). on-chip counter/timers, serial buses, hw interrupts, comparator output, and other digital signals in the controller can be configured to appear on the port i/o pins specified in the crossbar control registers. this allows the user to select the exact mix of general purpose port i/o and digital resources needed for the particular application. 1.5. serial ports the c8051f300/1/2/3 family includes an smbus/i 2 c interface and a full-duplex uart with enhanced baud rate configuration. each of the serial buses is fully implemented in hardware and makes extensive use of the cip-51's interrupts, thus requiring very little cpu intervention. figure 1.7. digital crossbar diagram xbr0, xbr1, xbr2 registers digital crossbar priority decoder sysclk 2 2 (internal digital signals) highest priority lowest priority p0 i/o cells p0.0 p0.7 8 p0mdout, p0mdin registers smbus uart t0, t1 2 4 pca cp0 outputs 2 p0 port latch (p0.0-p0.7) 8
page 18 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 1.6. programmable counter array an on-chip programmable counter/timer array (pca) is included in addition to the three 16-bit general purpose counter/timers. the pca consists of a dedicated 16-bit counter/timer time base with three programmable cap- ture/compare modules. the pca clock is derived from one of six sources: the system clock divided by 12, the system clock divided by 4, timer 0 overflows, an external clock input (eci), the system clock, or the external oscillator clock source divided by 8. the external clock source selection is useful for real-time clock functionality, where the pca is clocked by an external source while the internal oscillator drives the systemclock. each capture/compare module can be configured to operate in one of six modes: edge-triggered capture, software timer, high speed output, 8- or 16-bit pulse width modulator, or frequency output. additionally, capture/compare module 2 offers watchdog timer (wdt) capabilities. following a system reset, module 2 is configured and enabled in wdt mode. the pca capture/compare module i/o and external clock input may be routed to port i/o via the digital crossbar. 16-bit counter/timer cex1 eci digital crossbar cex2 cex0 port i/o capture/compare module 1 capture/compare module 0 capture/compare module 2 pca clock mux sysclk/12 sysclk/4 timer 0 overflow eci sysclk external clock/8 figure 1.8. pca block diagram
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 19 preliminary c8051f300/1/2/3 1.7. 8-bit analog to digital converter (c8051f300/2 only) the c8051f300/2 includes an on-chip 8-bit sar adc with a 10-channel differential input multiplexer and program- mable gain amplifier. with a maximum throughput of 500 ksps, the adc offers true 8-bit accuracy with an inl of 1lsb. the adc systemincludes a configurable analog multiplexer that selects both positive and negative adc inputs. each port pin is available as an adc input; additionally, the on-chip temperature sensor output and the power supply voltage (vdd) are available as adc inputs. user firmware may shut down the adc to save power. the integrated programmable gain amplifier (pga) amplifies the the adc input by 0.5, 1, 2, or 4 as defined by user software. the gain stage is especially useful when different adc input channels have widely varied input voltage signals, or when it is necessary to "zoomin" on a signal with a large dc offset. conversions can be started in five ways: a software command, an overflow of timer 0, 1, or 2, or an external convert start signal. this flexibility allows the start of conversion to be triggered by software events, a periodic signal (timer overflows), or external hw signals. conversion completions are indicated by a status bit and an interrupt (if enabled). the resulting 8-bit data word is latched into an sfr upon completion of a conversion. window compare registers for the adc data can be configured to interrupt the controller when adc data is either within or outside of a specified range. the adc can monitor a key voltage continuously in background mode, but not interrupt the controller unless the converted data is within/outside the specified range. figure 1.9. 8-bit adc block diagram x vdd 8 9-to-1 amux temp sensor 10-to-1 amux vdd p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 dgnd programmablegain amplifier start conversion window compare logic window compare interrupt + - configuration, control, and data registers analog multiplexer t0 overflow tmr2 overflow t1overflow software write external convert start 8-bit sar adc end of conversion interrupt adc data register
page 20 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 1.8. comparator c8051f300/1/2/3 devices include an on-chip voltage comparator that is enabled/disabled and configured via user software. all port i/o pins may be configurated as comparator inputs. two comparator outputs may be routed to a port pin if desired: a latched output and/or an unlatched (asynchronous) output. comparator response time is pro- grammable, allowing the user to select between high-speed and low-power modes. positive and negative hysteresis is also configurable. comparator interrupts may be generated on rising, falling, or both edges. when in idle mode, these interrupts may be used as a wake-up source. the comparator may also be configured as a reset source. reset decision tree + - crossbar interrupt handler q q set clr d q q set clr d (synchronizer) gnd cp0 + p0.0 p0.2 p0.4 p0.6 cp0 - p0.1 p0.3 p0.5 p0.7 vdd figure 1.10. comparator block diagram
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 21 preliminary c8051f300/1/2/3 2. absolute maximum ratings 3. global dc electrical characteristics table 1.1. absolute maximum ratings * parameter conditions min typ max units ambient temperature under bias -55 125 c storage temperature -65 150 c voltage on any port i/o pin or /rst with respect to gnd 0.3 5.8 v voltage on vdd with respect to gnd 0.3 4.2 v maximum total current through vdd and gnd 500 ma maximum output current sunk by /rst or any port pin 100 ma * note: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the devices at those or any other conditions above those indi- cated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 1.2. global dc electrical characteristics -40c to +85c, 25 mhz systemclock unless otherwise specified. parameter conditions min typ max units digital supply voltage 2.7 3.0 3.6 v digital supply current with cpu active vdd=2.7v, clock=25mhz vdd=2.7v, clock=1mhz vdd=2.7v, clock=32khz 5.8 0.34 11.6 ma ma a digital supply current with cpu inactive (not accessing flash) vdd=2.7v, clock=25mhz vdd=2.7v, clock=1mhz vdd=2.7v, clock=32khz 2.1 83 2.8 ma a a digital supply current (shut- down) oscillator not running < 0.1 a digital supply ram data retention voltage 1.5 v specified operating tempera- ture range -40 +85 c
page 22 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 4. pinout andpackage definitions table 4.1. pin definitions for the c8051f300/1/2/3 pin number name type description 1 vref / p0.0 ain di/oor ain external voltage reference input. port 0.0. see section 12 for complete description. 2 p0.1 di/oor ain port 0.1. see section 12 for complete description. 3 vdd power supply voltage. 4 xtal1 / p0.2 ain di/oor ain crystal input. this pin is the external oscillator circuit return for a crystal or ceramic resonator. see section 11.2 . port 0.2. see section 12 for complete description. 5 xtal2 / p0.3 aout di/o crystal input/output. for an external crystal or resonator, this pin is the excitation driver. this pin is the external clock input for cmos, capacitor, or rc network configurations. see section 11.2 . port 0.3. see section 12 for complete description. 6 p0.4 di/oor ain port 0.4. see section 12 for complete description. 7 p0.5 di/oor ain port 0.5. see section 12 for complete description. 8 c2ck / /rst di/o di/o clock input for the c2 development interface. device reset. open-drain output of internal por or vdd moni- tor. an external source can initiate a systemreset by driving this pinlowforatleast10s. 9 p0.6 / cnvstr di/oor ain di/o port 0.6. see section 12 for complete description. adc external convert start input strobe. 10 c2d / p0.7 di/o di/oor ain data signal for the c2 development interface. port 0.7. see section 12 for complete description. 11 gnd ground.
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 23 preliminary c8051f300/1/2/3 figure 4.1. mlp-11 pinout diagram (top view) vref / p0.0 p0.1 vdd xtal1/ p0.2 xtal2 / p0.3 p0.4 p0.5 c2ck / /rst p0.6 / cnvstr c2d / p0.7 gnd
page 24 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 a 1 e a3 a2 a side d view side e view l b e e d e e2 d2 lt lb k b d4 bottom view r e a1 a a3 a2 b a3 a2 a1 a k l lb lt r d d2 d3 e e2 d4 e 0.18 0.23 0.30 0.25 0 0.65 1.00 0 0.02 0.05 0.80 0.90 1.00 min typ max 0.27 0.45 0.55 0.65 0.36 0.37 0.09 3.00 2.20 2.25 2.27 3.00 1.36 0.386 0.5 mm d3 figure 4.2. mlp-11 package drawing
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 25 preliminary c8051f300/2 5. adc0 (8-bit adc, c8051f300/2 only) the adc0 subsystemfor the c8051f300/2 consists of two analog multiplexers (referred to collectively as amux0) with 11 total input selections, a differential programmable gain amplifier (pga), and a 500 ksps, 8-bit successive- approximation-register adc with integrated track-and-hold and programmable window detector (see block diagram in figure 5.1). the amux0, pga, data conversion modes, and window detector are all configurable under software control via the special function registers shown in figure 5.1. adc0 operates in both single-ended and differential modes, and may be configured to measure any port pin, the temperature sensor output, or vdd with respect to any port pin or gnd. the adc0 subsystemis enabled only when the ad0en bit in the adc0 control register (adc0cn) is set to logic 1. the adc0 subsystemis in low power shutdown when this bit is logic 0. figure 5.1. adc0 functional block diagram amux0 + - x vdd adc0cf amp0gn0 amp0gn1 ad0sc0 ad0sc1 ad0sc2 ad0sc3 ad0sc4 8-bit sar adc ref 8 sysclk adc0 16 adc0cn ad0cm0 ad0cm1 ad0cm2 ad0wint ad0busy ad0int ad0tm ad0en timer 0 overflow timer 2 overflow timer 1overflow start conversion 000 ad0busy (w) vdd adc0gt adc0lt 9-to-1 amux ad0wint temp sensor 10-to-1 amux vdd p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 gnd 001 010 011 1xx cnvstr input comb. logic amx0sl amx0p0 amx0p1 amx0p2 amx0n3 amx0n2 amx0n1 amx0n0 amx0p3
page 26 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/2 5.1. analog multiplexer and pga the analog multiplexers (amux0) select the positive and negative inputs to the pga, allowing any port pin to be measured relative to any other port pin or gnd. additionally, the on-chip temperature sensor or the positive power supply (vdd) may be selected as the positive pga input. when gndis selected as the negative input, adc0 operates in single-ended mode; all other times, adc0 operates in differential mode. the adc0 input channels are selected in the amx0sl register as described in figure 5.5. the conversion code format differs in single-ended versus differential modes, as shown below. when in single- ended mode (negative input is selected gnd), conversion codes are represented as 8-bit unsigned integers. inputs are measured from 0 to vref * 255/256. example codes are shown below. when in differential mode (negative input is not selected as gnd), conversion codes are represented as 8-bit signed 2s complement numbers. inputs are measured from -vref to vref * 127/128. example codes are shown below. important note about adc0 input configuration: port pins selected as adc0 inputs should be configured as analog inputs, and should be skipped by the digital crossbar. to configure a port pin for analog input, set to 1 the corresponding bit in register p0mdin. to force the crossbar to skip a port pin, set to 1 the corresponding bit in reg- ister xbr0. see section 12. port input/output on page 85 for more port i/o configuration details. the pga amplifies the amux0 output signal as defined by the amp0gn1-0 bits in the adc0 configuration regis- ter (figure 5.6). the pga is software-programmable for gains of 0.5, 1, 2, or 4. the gain defaults to 0.5 on reset. the temperature sensor transfer function is shown in figure 5.2 on page 27. the output voltage (v temp ) is the pos- itive pga input when the temperature sensor is selected by bits amx0p2-0 in register amx0sl; this voltage will be amplified by the pga according to the user-programmed pga settings. input voltage adc0 output (conversion code) vref * 255/256 0xff vref * 128/256 0x80 vref * 64/256 0x40 0 0x00 input voltage adc0 output (conversion code) vref * 127/128 0x7f vref * 64/128 0x40 0 0x00 -vref * 64/128 0xc0 -vref 0x80
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 27 preliminary c8051f300/2 5.2. modes of operation adc0 has a maximum conversion speed of 500 ksps. the adc0 conversion clock is a divided version of the system clock, determined by the ad0sc bits in the adc0cf register (system clock divided by (ad0sc + 1) for 0 ad0sc 31). the adc0 conversion clock should be no more than 8.3 mhz. 5.2.1. starting a conversion a conversion can be initiated in one of five ways, depending on the programmed states of the adc0 start of conver- sion mode bits (ad0cm2-0) in register adc0cn. conversions may be initiated by one of the following: 1. writing a 1 to the ad0busy bit of register adc0cn 2. a timer 0 overflow (i.e. timed continuous conversions) 3. a timer 2 overflow 4. a timer 1 overflow 5. a rising edge on the cnvstr input signal (pin p0.6) writing a 1 to ad0busy provides software control of adc0 whereby conversions are performed "on-demand". during conversion, the ad0busy bit is set to logic 1 and reset to logic 0 when the conversion is complete. the fall- ing edge of ad0busy triggers an interrupt (when enabled) and sets the adc0 interrupt flag (ad0int). note: when polling for adc conversion completions, the adc0 interrupt flag (ad0int) should be used. converted data is avail- able in the adc0 data register, adc0 when bit ad0int is logic 1. note that when timer 2 overflows are used as the conversion source, timer 2 low byte overflows are used if timer 2 is in 8-bit mode; timer 2 high byte overflows are used if timer 2 is in 16-bit mode. see section 15. timers on page 121 for timer configuration. important note about using cnvstr: the cnvstr input pin also functions as port pin p0.6. when the cnvstr input is used as the adc0 conversion source, port pin p0.6 should be skipped by the digital crossbar. to configure the crossbar to skip p0.6, set to 1 bit6 in register xbr0. see section 12. port input/output on page 85 for details on port i/o configuration. figure 5.2. temperature sensor transfer function 0 -50 50 100 (celsius) 0.700 0.800 0.900 1.000 1.100 (volts) v temp = 0.0033*(temp c )+0.89 for pga gain = 1 1.200
page 28 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/2 5.2.2. tracking modes the ad0tm bit in register adc0cn controls the adc0 track-and-hold mode. in its default state, the adc0 input is continuously tracked, except when a conversion is in progress. when the ad0tm bit is logic 1, adc0 operates in low-power track-and-hold mode. in this mode, each conversion is preceded by a tracking period of 3 sar clocks (after the start-of-conversion signal). when the cnvstr signal is used to initiate conversions in low-power tracking mode, adc0 tracks only when cnvstr is low; conversion begins on the rising edge of cnvstr (see figure 5.3). tracking can also be disabled (shutdown) when the device is in low power standby or sleep modes. low-power track- and-hold mode is also useful when amux or pga settings are frequently changed, due to the settling time require- ments described in section 5.2.3. settling time requirements on page 29 . figure 5.3. 8-bit adc track and conversion example timing write '1' to ad0busy, timer 0, timer 2, timer 1overflow (ad0cm[2:0]=000, 001, 010, 011) ad0tm=1 track convert low power mode ad0tm=0 track or convert convert track low power or convert sar clocks 1 234567891011 12 123456789 sar clocks b. adc timing for internal trigger source 123456789 cnvstr (ad0cm[2:0]=1xx) ad0tm=1 a. adc timing for external trigger source sar clocks trackorconvert convert track ad0tm=0 track convert low power mode low power or convert
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 29 preliminary c8051f300/2 5.2.3. settling time requirements when the adc0 input configuration is changed (i.e., a different amux0 or pga selection is made), a minimum tracking time is required before an accurate conversion can be performed. this tracking time is determined by the amux0 resistance, the adc0 sampling capacitance, any external source resistance, and the accuracy required for the conversion. note that in low-power tracking mode, three sar clocks are used for tracking at the start of every conversion. for most applications, these three sar clocks will meet the minimum tracking time requirements. figure 5.4 shows the equivalent adc0 input circuits for both differential and single-ended modes. notice that the equivalent time constant for both input circuits is the same. the required adc0 settling time for a given settling accuracy (sa) may be approximated by equation 5.1. when measuring the temperature sensor output or vdd with respect to gnd, r total reduces to r mux . see table 5.1 for adc0 minimum settling time requirements. where: sa is the settling accuracy, given as a fraction of an lsb (for example, 0.25 to settle within 1/4 lsb) t is the required settling time in seconds r total is the sumof the amux0 resistance and any external source resistance. n is the adc resolution in bits (8). equation 5.1. adc0 settling time requirements t 2 n sa ------ - ?? ?? r total c sample ln = r mux =5k rc input =r mux *c sample r mux =5k c sample = 5pf c sample = 5pf mux select mux select differential mode p0.x p0.y r mux =5k c sample = 5pf rc input =r mux *c sample mux select single-ended mode p0.x note: when the pga gain is set to 0.5, c sample = 3pf figure 5.4. adc0 equivalent input circuits
page 30 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/2 figure 5.5. amx0sl: amux0 channel select register (c8051f300/2) bits7-4: amx0n3-0: amux0 negative input selection note that when gnd is selected as the negative input, adc0 operates in single-ended mode. for all other negative input selections, adc0 operates in differential mode. 0000-1000b: adc0 negative input selected per the chart below. bits3-0: amx0p3-0: amux0 positive input selection 0000-1001b: adc0 positive input selected per the chart below. 1010-1111b: reserved. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue amx0n3 amx0n2 amx0n1 amx0n0 amx0p3 amx0p2 amx0p1 amx0p0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbb amx0n3-0 adc0 negative input 0000 p0.0 0001 p0.1 0010 p0.2 0011 p0.3 0100 p0.4 0101 p0.5 0110 p0.6 0111 p0.7 1xxx gnd (adc in single-ended mode) amx0p2-0 adc0 positive input 0000 p0.0 0001 p0.1 0010 p0.2 0011 p0.3 0100 p0.4 0101 p0.5 0110 p0.6 0111 p0.7 1000 temperature sensor 1001 vdd
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 31 preliminary c8051f300/2 figure 5.6. adc0cf: adc0 configuration register (c8051f300/2) bits7-3: ad0sc4-0: adc0 sar conversion clock period bits sar conversion clock is derived fromsystemclock by the following equation, where ad0sc refers to the 5-bit value held in bits ad0sc4-0. sar conversion clock requirements are given in table 5.1. bit2: unused. read = 0b; write = dont care bits1-0: amp0gn1-0: adc0 internal amplifier gain (pga) 00: gain = 0.5 01: gain = 1 10: gain = 2 11: gain = 4 r/wr/wr/wr/wr/wr/wr/wr/wresetvalue ad0sc4 ad0sc3 ad0sc2 ad0sc1 ad0sc0 - amp0gn1 amp0gn0 11111000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbc a d 0 sc sysclk clk sar --------------------- -1 C = figure 5.7. adc0: adc0 data word register (c8051f300/2) bits7-0: adc0 data word. adc0 holds the output data byte fromthe last adc0 conversion. when in single-ended mode, adc0 holds an 8-bit unsigned integer. when in differential mode, adc0 holds a 2s complement signed 8-bit integer. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbe
page 32 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/2 figure 5.8. adc0cn: adc0 control register (c8051f300/2) bit7: ad0en: adc0 enable bit. 0: adc0 disabled. adc0 is in low-power shutdown. 1: adc0 enabled. adc0 is active and ready for data conversions. bit6: ad0tm: adc0 track mode bit. 0: normal track mode: when adc0 is enabled, tracking is continuous unless a conversion is in progress. 1: low-power track mode: tracking defined by ad0cm2-0 bits (see below). bit5: ad0int: adc0 conversion complete interrupt flag. 0: adc0 has not completed a data conversion since the last time ad0int was cleared. 1: adc0 has completed a data conversion. bit4: ad0busy: adc0 busy bit. read: 0: adc0 conversion is complete or a conversion is not currently in progress. ad0int is set to logic 1 on the falling edge of ad0busy. 1: adc0 conversion is in progress. write: 0: no effect. 1: initiates adc0 conversion if ad0cm2-0 = 000b bit3: ad0wint: adc0 window compare interrupt flag. 0: adc0 window comparison data match has not occurred since this flag was last cleared. 1: adc0 window comparison data match has occurred. bits2-0: ad0cm2-0: adc0 start of conversion mode select. when ad0tm = 0: 000: adc0 conversion initiated on every write of 1 to ad0busy. 001: adc0 conversion initiated on overflow of timer 0. 010: adc0 conversion initiated on overflow of timer 2. 011: adc0 conversion initiated on overflow of timer 1. 1xx: adc0 conversion initiated on rising edge of external cnvstr. when ad0tm = 1: 000: tracking initiated on write of 1 to ad0busy and lasts 3 sar clocks, followed by conversion. 001: tracking initiated on overflow of timer 0 and lasts 3 sar clocks, followed by conversion. 010: tracking initiated on overflow of timer 2 and lasts 3 sar clocks, followed by conversion. 011: tracking initiated on overflow of timer 1 and lasts 3 sar clocks, followed by conversion. 1xx: adc0 tracks only when cnvstr input is logic low; conversion starts on rising cnvstr edge. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue ad0en ad0tm ad0int ad0busy ad0wint ad0cm2 ad0cm1 ad0cm0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xe8
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 33 preliminary c8051f300/2 5.3. programmable window detector the adc programmable window detector continuously compares the adc0 output to user-programmed limits, and notifies the systemwhen a desired condition is detected. this is especially effective in an interrupt-driven system, saving code space and cpu bandwidth while delivering faster systemresponse times. the window detector interrupt flag (ad0wint in register adc0cn) can also be used in polled mode. the adc0 greater-than (adc0gt) and less-than (adc0lt) registers hold the comparison values. example comparisons for differential and single-ended modes are shown in figure 5.10 and figure 5.9, respectively. notice that the window detector flag can be pro- grammed to indicate when measured data is inside or outside of the user-programmed limits, depending on the con- tents of the adc0lt and adc0gt registers. 5.3.1. window detector in single-ended mode figure 5.9 shows two example window comparisons for single-ended mode, with adc0lt = 0x20 and adc0gt = 0x10. notice that in single-ended mode, the codes vary from 0 to vref*(255/256) and are represented as 8-bit unsigned integers. in the left example, an ad0wint interrupt will be generated if the adc0 conversion word (adc0) is within the range defined by adc0gt and adc0lt (if 0x10 < adc0 < 0x20). in the right example, and ad0wint interrupt will be generated if adc0 is outside of the range defined by adc0gt and adc0lt (if adc0 < 0x10 or adc0 > 0x20). figure 5.9. adc window compare examples, single-ended mode 0xff 0x21 0x20 0x1f 0x11 0x10 0x0f 0x00 0 input voltage (p0.x - gnd) ref x (255/256) ref x (32/256) ref x (16/256) ad0wint=1 ad0wint not affected ad0wint not affected adc0lt adc0gt 0xff 0x21 0x20 0x1f 0x11 0x10 0x0f 0x00 0 input voltage (p0.x - gnd) ref x (255/256) ref x (32/256) ref x (16/256) ad0wint not affected adc0gt adc0lt ad0wint=1 ad0wint=1 adc0 adc0
page 34 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/2 5.3.2. window detector in differential mode figure 5.10 shows two example window comparisons for differential mode, with adc0lt = 0x10 (+16d) and adc0gt = 0xff (-1d). notice that in differential mode, the codes vary from -vref to vref*(127/128) and are represented as 8-bit 2s complement signed integers. in the left example, an ad0wint interrupt will be generated if the adc0 conversion word (adc0l) is within the range defined by adc0gt and adc0lt (if 0xff (-1d) < adc0 < 0x0f (16d)). in the right example, an ad0wint interrupt will be generated if adc0 is outside of the range defined by adc0gt and adc0lt (if adc0 < 0xff (-1d) or adc0 > 0x10 (+16d)). figure 5.10. adc window compare examples, differential mode 0x7f (127d) 0x11 (17d) 0x10 (16d) 0x0f (15d) 0x00 (0d) 0xff (-1d) 0xfe (-2d) 0x80 (-128d) -ref input voltage (p0.x - p0.y) ref x (127/128) ref x (16/128) ref x (-1/256) 0x7f (127d) 0x11 (17d) 0x10 (16d) 0x0f (15d) 0x00 (0d) 0xff (-1d) 0xfe (-2d) 0x80 (-128d) -ref input voltage (p0.x - p0.y) ref x (127/128) ref x (16/128) ref x (-1/256) ad0wint=1 ad0wint not affected ad0wint not affected adc0lt adc0gt ad0wint not affected adc0gt adc0lt ad0wint=1 ad0wint=1 adc0 adc0
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 35 preliminary c8051f300/2 figure 5.11. adc0gt: adc0 greater-than data byte register (c8051f300/2) bits7-0: adc0 greater-than data word r/wr/wr/wr/wr/wr/wr/wr/wresetvalue 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc4 figure 5.12. adc0lt: adc0 less-than data byte register (c8051f300/2) bits7-0: adc0 less-than data word r/wr/wr/wr/wr/wr/wr/wr/wresetvalue 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc6
page 36 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/2 table 5.1. adc0 electrical characteristics vdd = 3.0 v, vref = 2.40 v (refsl=0), pga gain = 1, -40c to +85c unless otherwise specified parameter conditions min typ max units dc accuracy resolution 8 bits integral nonlinearity 0.5 1 lsb differential nonlinearity guaranteed monotonic 0.5 1 lsb offset error 0.50.6 lsb full scale error differential mode -10.5 lsb offset temperature coefficient tbd ppm/c dynamic performance (10 khz sine-wave differential input, 0 to 1 db below full scale, 500 ksps) signal-to-noise plus distortion tbd 48 db total harmonic distortion up to the 5 th harmonic -56 db spurious-free dynamic range 58 db conversion rate sar conversion clock 5 mhz conversion time in system clocks adc0cf = 00000xxxb 8 clocks track/hold acquisition time 800 ns throughput rate 500 ksps analog inputs input voltage range 0 vref v input capacitance 10 pf power specifications power supply current (vdd sup- plied to adc0) operating mode, 500 ksps 400 tbd a power supply rejection 0.3 mv/v
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 37 preliminary c8051f300/2 6. voltage reference (c8051f300/2) the voltage reference mux on c8051f300/2 devices is configurable to use an externally connected voltage refer- ence or the power supply voltage, vdd (see figure 6.1). the refsl bit in the reference control register (ref0cn) selects the reference source. for an external source, refsl should be set to 0; for vdd as the reference source, refsl should be set to 1. the biase bit enables the internal voltage bias generator, which is used by the adc, temperature sensor, and inter- nal oscillator. this bit is forced to logic 1 when any of the aforementioned peripherals is enabled. the bias generator may be enabled manually by writing a 1 to the biase bit in register ref0cn; see figure 6.2 for ref0cn register details. the electrical specifications for the voltage reference circuit are given in table 6.1. important note about the vref input: port pin p0.0 is used as the external vref input. when using an external voltage reference, p0.0 should be configured as analog input and skipped by the digital crossbar. to configure p0.0 as analog input, set to 1 bit0 in register p0mdin. to configure the crossbar to skip p0.0, set to 1 bit0 in register xbr0. refer to section 12. port input/output on page 85 for complete port i/o configuration details. the exter- nal reference voltage must be within the range 0 vref vdd. on c8051f300/2 devices, the temperature sensor connects to the highest order input of the adc0 positive input mul- tiplexer (see section 5.1. analog multiplexer and pga on page 26 for details). the tempe bit in register ref0cn enables/disables the temperature sensor. while disabled, the temperature sensor defaults to a high imped- ance state and any adc0 measurements performed on the sensor result in meaningless data. figure 6.1. voltage reference functional block diagram internal vref (to adc) to analog mux vdd vref r1 vdd external voltage reference circuit gnd ref0cn refsl tempe biase temp sensor en bias generator to adc, internal oscillator en ioscen 0 1
page 38 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/2 table 6.1. external voltage reference circuit electrical characteristics vdd = 3.0 v; -40c to +85c unless otherwise specified parameter conditions min typ max units input voltage range 0 vdd v input current sample rate = 500 ksps; vref = 3.0 v 12 a figure 6.2. ref0cn: reference control register bits7-3: unused. read = 00000b; write = dont care. bit3: refsl: voltage reference select this bit selects the source for the internal voltage reference. 0: vref input pin used as voltage reference. 1: vdd used as voltage reference. bit2: tempe: temperature sensor enable bit. 0: internal temperature sensor off. 1: internal temperature sensor on. bit1: biase: internal analog bias generator enable bit. (must be 1 if using adc). 0: internal bias generator off. 1: internal bias generator on. bit0: unused. read = 0b. write = dont care. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue - - - - refsl tempe biase - 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd1
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 39 preliminary c8051f300/1/2/3 7. comparator0 c8051f300/1/2/3 devices include an on-chip programmable voltage comparator, shown in figure 7.1. comparator0 offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the port pins: a synchronous latched output (cp0), or an asynchronous raw output (cp0a). the asyn- chronous cp0a signal is available even when in when the systemclock is not active. this allows comparator0 to operate and generate an output with the device in stop mode. when assigned to a port pin, the comparator0 output may be configured as open drain or push-pull (see section 12.2. port i/o initialization on page 88 ). comparator0 may also be used as a reset source (see section 9.5. comparator0 reset on page 71 ). the inputs for comparator0 are selected in the cpt0mx register (figure 7.4). the cmx0p1-cmx0p0 bits select the comparator0 positive input; the cmx0n1-cmx0n0 bits select the comparator0 negative input. important note about comparator inputs: the port pins selected as comparator inputs should be configured as analog inputs in their associated port configuration register, and configured to be skipped by the crossbar (for details on port configuration, see section 12.3. general purpose port i/o on page 91 ). vdd cpt0cn reset decision tree + - crossbar interrupt logic q q set clr d q q set clr d (synchronizer) gnd cp0 + p0.0 p0.2 p0.4 p0.6 cp0 - p0.1 p0.3 p0.5 p0.7 cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0 cpt0mx cmx0n1 cmx0n0 cmx0p1 cmx0p0 cpt0md cp0md1 cp0md0 cp0 rising-edge interrupt flag cp0 falling-edge interrupt flag cp0 cp0a figure 7.1. comparator0 functional block diagram
page 40 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 the output of comparator0 can be polled in software, used as an interrupt source, and/or routed to a port pin. when routed to a port pin, the comparator0 output is available asynchronous or synchronous to the system clock; the asyn- chronous output is available even in stop mode (with no system clock active). when disabled, the comparator0 out- put (if assigned to a port i/o pin via the crossbar) defaults to the logic low state, and its supply current falls to less than 100 na. see section 12.1. priority crossbar decoder on page 86 for details on configuring the comparator0 output via the digital crossbar. comparator0 inputs can be externally driven from -0.25 v to (vdd) + 0.25 v without damage or upset. the complete electrical specifications for comparator0 are given in table 7.1. the comparator0 response time may be configured in software via the cp0md1-0 bits in register cpt0md (see figure 7.5). selecting a longer response time reduces the amount of current consumed by comparator0. see table 7.1 for complete timing and current consumption specifications. the hysteresis of comparator0 is software-programmable via its comparator0 control register (cpt0cn). the user can programboth the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going symmetry of this hysteresis around the threshold voltage. the comparator0 hysteresis is programmed using bits3-0 in the comparator0 control register cpt0cn (shown in figure 7.3). the amount of negative hysteresis voltage is determined by the settings of the cp0hyn bits. as shown in figure 7.2, settings of 20, 10 or 5 mv of negative hysteresis can be programmed, or negative hysteresis can be dis- abled. in a similar way, the amount of positive hysteresis is determined by the setting the cp0hyp bits. positive hysteresis voltage (programmed with cp0hyp bits) negative hysteresis voltage (programmed by cp0hyn bits) vin- vin+ inputs circuit configuration + _ cp0+ cp0- cp0 vin+ vin- out v oh positive hysteresis disabled maximum positive hysteresis negative hysteresis disabled maximum negative hysteresis output v ol figure 7.2. comparator hysteresis plot
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 41 preliminary c8051f300/1/2/3 comparator0 interrupts can be generated on both rising-edge and falling-edge output transitions. (for interrupt enable and priority control, see section 8.3. interrupt handler on page 58 ). the cp0fif flag is set to logic 1 upon a comparator0 falling-edge interrupt, and the cp0rif flag is set to logic 1 upon the comparator0 rising-edge interrupt. once set, these bits remain set until cleared by software. the output state of comparator0 can be obtained at any time by reading the cp0out bit. comparator0 is enabled by setting the cp0en bit to logic 1, and is disabled by clearing this bit to logic 0. figure 7.3. cpt0cn: comparator0 control register bit7: cp0en: comparator0 enable bit. 0: comparator0 disabled. 1: comparator0 enabled. bit6: cp0out: comparator0 output state flag. 0: voltage on cp0+ < cp0-. 1: voltage on cp0+ > cp0-. bit5: cp0rif: comparator0 rising-edge interrupt flag. 0: no comparator0 rising edge interrupt has occurred since this flag was last cleared. 1: comparator0 rising edge interrupt has occurred. bit4: cp0fif: comparator0 falling-edge interrupt flag. 0: no comparator0 falling-edge interrupt has occurred since this flag was last cleared. 1: comparator0 falling-edge interrupt has occurred. bits3-2: cp0hyp1-0: comparator0 positive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 5 mv. 10: positive hysteresis = 10 mv. 11: positive hysteresis = 20 mv. bits1-0: cp0hyn1-0: comparator0 negative hysteresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 5 mv. 10: negative hysteresis = 10 mv. 11: negative hysteresis = 20 mv. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf8
page 42 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 figure 7.4. cpt0mx: comparator0 mux selection register bits7-6: unused. read = 00b, write = dont care. bits6-4: cmx0n1-cmx0n0: comparator0 negative input mux select these bits select which port pin is used as the comparator0 negative input. bits3-2: unused. read = 00b, write = dont care. bits1-0: cmx0p1-cmx0p0: comparator0 positive input mux select these bits select which port pin is used as the comparator0 positive input. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue - - cmx0n1 cmx0n0 - - cmx0p1 cmx0p0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9f cmx0n1 cmx0n0 negative input 00 p0.1 01 p0.3 10 p0.5 11 p0.7 cmx0p1 cmx0p0 positive input 00 p0.0 01 p0.2 10 p0.4 11 p0.6
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 43 preliminary c8051f300/1/2/3 figure 7.5. cpt0md: comparator0 mode selection register bits7-2: unused. read = 000000b, write = dont care. bits1-0: cp0md1-cp0md0: comparator0 mode select these bits select the response time for comparator0. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue - - - - - - cp0md1 cp0md0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9d mode cp0md1 cp0md0 cp0 response time (typ) 000 100ns 101 175ns 210 320ns 311 1050ns
page 44 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 table 7.1. comparator0 electrical characteristics vdd = 3.0 v, -40c to +85c unless otherwise specified. parameter conditions min typ max units response time: mode 0, vcm ? =1.5v cp0+ - cp0- = 100 mv 100 ns cp0+-cp0-=-100mv 250 ns response time: mode 1, vcm ? =1.5v cp0+ - cp0- = 100 mv 175 ns cp0+-cp0-=-100mv 500 ns response time: mode 2, vcm ? =1.5v cp0+ - cp0- = 100 mv 320 ns cp0+-cp0-=-100mv 1100 ns response time: mode 3, vcm ? =1.5v cp0+ - cp0- = 100 mv 1050 ns cp0+-cp0-=-100mv 5200 ns common-mode rejection ratio 1.5 4 mv/v positive hysteresis 1 cp0hyp1-0 = 00 0 1 mv positive hysteresis 2 cp0hyp1-0 = 01 3 5 7 mv positive hysteresis 3 cp0hyp1-0 = 10 7 10 15 mv positive hysteresis 4 cp0hyp1-0 = 11 15 20 25 mv negative hysteresis 1 cp0hyn1-0 = 00 0 1 mv negative hysteresis 2 cp0hyn1-0 = 01 3 5 7 mv negative hysteresis 3 cp0hyn1-0 = 10 7 10 15 mv negative hysteresis 4 cp0hyn1-0 = 11 15 20 25 mv inverting or non-inverting input voltage range -0.25 vdd + 0.25 v input capacitance 7 pf input bias current -5 0.001 +5 na inputoffsetvoltage -5 +5 mv power supply power supply rejection 0.1 1 mv/v power-up time 10 s supply current at dc mode 0 7.6 a mode 1 3.2 a mode 2 1.3 a mode 3 0.4 a ? vcm is the common-mode voltage on cp0+ and cp0-.
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 45 preliminary c8051f300/1/2/3 8. cip-51 microcontroller the mcu system controller core is the cip-51 microcontroller. the cip-51 is fully compatible with the mcs-51? instruction set; standard 803x/805x assemblers and compilers can be used to develop software. the mcu family has a superset of all the peripherals included with a standard 8051. included are three 16-bit counter/timers (see descrip- tion in section 15 ), an enhanced full-duplex uart (see description in section 14 ), 256 bytes of internal ram, 128 byte special function register (sfr) address space ( section 8.2.6 ), and one byte-wide i/o port (see description in section 12 ). the cip-51 also includes on-chip debug hardware (see description in section 17 ), and interfaces directly with the analog and digital subsystems providing a complete data acquisition or control-system solution in a single integrated circuit. the cip-51 microcontroller core implements the standard 8051 organization and peripherals as well as additional customperipherals and functions to extend its capability (see figure 8.1 for a block diagram). the cip-51 includes the following features: data bus tmp1 tmp2 prgm. address reg. pc incrementer alu psw data bus data bus memory interface mem_address d8 pipeline buffer data pointer interrupt interface system_irqs emulation_irq mem_control control logic a16 program counter (pc) stop clock reset idle power control register data bus sfr bus interface sfr_address sfr_control sfr_write_data sfr_read_data d8 d8 bregister d8 d8 accumulator d8 d8 d8 d8 d8 d8 d8 d8 mem_write_data mem_read_data d8 sram address register sram (256 x 8) d8 stack pointer d8 figure 8.1. cip-51 block diagram - fully compatible with mcs-51 instruction set - 25 mips peak throughput with 25 mhz clock - 0 to 25 mhz clock frequency - 256 bytes of internal ram - byte-wide i/o port - extended interrupt handler - reset input - power management modes - on-chip debug logic - programand data memory security
page 46 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 performance the cip-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. in a standard 8051, all instructions except for mul and div take 12 or 24 systemclock cycles to exe- cute, and usually have a maximum system clock of 12 mhz. by contrast, the cip-51 core executes 70% of its instruc- tions in one or two systemclock cycles, with no instructions taking more than eight systemclock cycles. with the cip-51's maximum system clock at 25 mhz, it has a peak throughput of 25 mips. the cip-51 has a total of 109 instructions. the table below shows the total number of instrutions that require each execution time. programming and debugging support in-system programming of the flash program memory and communication with on-chip debug support logic is accomplished via the cygnal 2-wire development interface (c2). note that the re-programmable flash can also be read and changed a single byte at a time by the application software using the movc and movx instructions. this feature allows programmemory to be used for non-volatile data storage as well as updating programcode under soft- ware control. the on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware break- points, starting, stopping and single stepping through programexecution (including interrupt service routines), exam- ination of the program's call stack, and reading/writing the contents of registers and memory. this method of on-chip debugging is completely non-intrusive, requiring no ram, stack, timers, or other on-chip resources. c2 details can be found in section 17. c2 interface on page 149 . the cip-51 is supported by development tools from cygnal integrated products and third party vendors. cygnal pro- vides an integrated development environment (ide) including editor, macro assembler, debugger and programmer. the ide's debugger and programmer interface to the cip-51 via the c2 interface to provide fast and efficient in-sys- tem device programming and debugging. third party macro assemblers and c compilers are also available. clocks to execute 1 2 2/3 3 3/4 4 4/5 5 8 number of instructions 26 50 5 14 7 3 1 2 1
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 47 preliminary c8051f300/1/2/3 8.1. instruction set the instruction set of the cip-51 systemcontroller is fully compatible with the standard mcs-51? instruction set. standard 8051 development tools can be used to develop software for the cip-51. all cip-51 instructions are the binary and functional equivalent of their mcs-51? counterparts, including opcodes, addressing modes and effect on psw flags. however, instruction timing is different than that of the standard 8051. 8.1.1. instruction and cpu timing in many 8051 implementations, a distinction is made between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. however, the cip-51 implementation is based solely on clock cycle tim- ing. all instruction timings are specified in terms of clock cycles. due to the pipelined architecture of the cip-51, most instructions execute in the same number of clock cycles as there are programbytes in the instruction. conditional branch instructions take one less clock cycle to complete when the branch is not taken as opposed to when the branch is taken. table 8.1 is the cip-51 instruction set summary , which includes the mnemonic, number of bytes, and number of clock cycles for each instruction. 8.1.2. movx instruction and program memory the movx instruction is typically used to access external data memory (note: the c8051f300/1/2/3 does not sup- port external data or program memory). in the cip-51, the movx instruction accesses the on-chip program memory space implemented as re-programmable flash memory. this feature provides a mechanism for the cip-51 to update programcode and use the programmemory space for non-volatile data storage. refer to section 10. flash memory on page 75 for further details. table 8.1. cip-51 instruction set summary mnemonic description bytes clock cycles arithmetic operations add a, rn addregistertoa 1 1 add a, direct add direct byte to a 2 2 add a, @ri add indirect ram to a 1 2 add a, #data add immediate to a 2 2 addc a, rn add register to a with carry 1 1 addc a, direct add direct byte to a with carry 2 2 addc a, @ri add indirect ram to a with carry 1 2 addc a, #data add immediate to a with carry 2 2 subb a, rn subtract register froma with borrow 1 1 subb a, direct subtract direct byte froma with borrow 2 2 subb a, @ri subtract indirect ram froma with borrow 1 2 subb a, #data subtract immediate from a with borrow 2 2 inc a increment a 1 1 inc rn increment register 1 1 inc direct increment direct byte 2 2 inc @ri increment indirect ram 1 2 dec a decrement a 1 1 dec rn decrement register 1 1 dec direct decrement direct byte 2 2 dec @ri decrement indirect ram 1 2 inc dptr increment data pointer 1 1
page 48 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 mul ab multiply a and b 1 4 div ab divide a by b 1 8 da a decimal adjust a 1 1 logical operations anl a, rn and register to a 1 1 anl a, direct and direct byte to a 2 2 anl a, @ri and indirect ram to a 1 2 anl a, #data and immediate to a 2 2 anl direct, a andatodirectbyte 2 2 anl direct, #data and immediate to direct byte 3 3 orl a, rn or register to a 1 1 orl a, direct or direct byte to a 2 2 orl a, @ri or indirect ram to a 1 2 orl a, #data or immediate to a 2 2 orl direct, a or a to direct byte 2 2 orl direct, #data or immediate to direct byte 3 3 xrl a, rn exclusive-or register to a 1 1 xrl a, direct exclusive-or direct byte to a 2 2 xrl a, @ri exclusive-or indirect ram to a 1 2 xrl a, #data exclusive-or immediate to a 2 2 xrl direct, a exclusive-or a to direct byte 2 2 xrl direct, #data exclusive-or immediate to direct byte 3 3 clr a clear a 1 1 cpl a complement a 1 1 rl a rotate a left 1 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rotate a right through carry 1 1 swap a swap nibbles of a 1 1 data transfer mov a, rn move register to a 1 1 mov a, direct move direct byte to a 2 2 mov a, @ri move indirect ram to a 1 2 mov a, #data move immediate to a 2 2 mov rn, a move a to register 1 1 mov rn, direct move direct byte to register 2 2 mov rn, #data move immediate to register 2 2 mov direct, a move a to direct byte 2 2 mov direct, rn move register to direct byte 2 2 mov direct, direct move direct byte to direct byte 3 3 mov direct, @ri move indirect ram to direct byte 2 2 mov direct, #data move immediate to direct byte 3 3 mov @ri, a move a to indirect ram 1 2 mov @ri, direct move direct byte to indirect ram 2 2 mov @ri, #data move immediate to indirect ram 2 2 table 8.1. cip-51 instruction set summary mnemonic description bytes clock cycles
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 49 preliminary c8051f300/1/2/3 mov dptr, #data16 load dptr with 16-bit constant 3 3 movc a, @a+dptr move code byte relative dptr to a 1 3 movc a, @a+pc move code byte relative pc to a 1 3 movx a, @ri move external data (8-bit address) to a 1 3 movx @ri, a move a to external data (8-bit address) 1 3 movx a, @dptr move external data (16-bit address) to a 1 3 movx @dptr, a move a to external data (16-bit address) 1 3 push direct push direct byte onto stack 2 2 pop direct pop direct byte fromstack 2 2 xch a, rn exchange register with a 1 1 xch a, direct exchange direct byte with a 2 2 xch a, @ri exchange indirect ram with a 1 2 xchd a, @ri exchange low nibble of indirect ram with a 1 2 boolean manipulation clr c clear carry 1 1 clr bit clear direct bit 2 2 setb c set carry 1 1 setb bit set direct bit 2 2 cpl c complement carry 1 1 cpl bit complement direct bit 2 2 anl c, bit and direct bit to carry 2 2 anl c, /bit and complement of direct bit to carry 2 2 orl c, bit or direct bit to carry 2 2 orl c, /bit or complement of direct bit to carry 2 2 mov c, bit move direct bit to carry 2 2 mov bit, c move carry to direct bit 2 2 jc rel jump if carry is set 2 2/3 jnc rel jump if carry is not set 2 2/3 jb bit, rel jump if direct bit is set 3 3/4 jnb bit, rel jump if direct bit is not set 3 3/4 jbc bit, rel jump if direct bit is set and clear bit 3 3/4 program branching acall addr11 absolute subroutine call 2 3 lcall addr16 long subroutine call 3 4 ret return fromsubroutine 1 5 reti return frominterrupt 1 5 ajmp addr11 absolute jump 2 3 ljmp addr16 long jump 3 4 sjmp rel short jump (relative address) 2 3 jmp @a+dptr jump indirect relative to dptr 1 3 jz rel jump if a equals zero 2 2/3 jnz rel jump if a does not equal zero 2 2/3 cjne a, direct, rel compare direct byte to a and jump if not equal 3 3/4 cjne a, #data, rel compare immediate to a and jump if not equal 3 3/4 cjne rn, #data, rel compare immediate to register and jump if not equal 3 3/4 table 8.1. cip-51 instruction set summary mnemonic description bytes clock cycles
page 50 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 cjne @ri, #data, rel compare immediate to indirect and jump if not equal 3 4/5 djnz rn, rel decrement register and jump if not zero 2 2/3 djnz direct, rel decrement direct byte and jump if not zero 3 3/4 nop no operation 1 1 table 8.1. cip-51 instruction set summary mnemonic description bytes clock cycles notes on registers, operands and addressing modes: rn - register r0-r7 of the currently selected register bank. @ri - data ram location addressed indirectly through r0 or r1. rel - 8-bit, signed (twos complement) offset relative to the first byte of the following instruction. used by sjmp and all conditional jumps. direct - 8-bit internal data locations address. this could be a direct-access data ram location (0x00-0x7f) or an sfr (0x80-0xff). #data - 8-bit constant #data16 - 16-bit constant bit - direct-accessed bit in data ram or sfr addr11 - 11-bit destination address used by acall and ajmp. the destination must be within the same 2k-byte page of program memory as the first byte of the following instruction. addr16 - 16-bit destination address used by lcall and ljmp. the destination may be anywhere within the 8k- byte program memory space. there is one unused opcode (0xa5) that performs the same function as nop. all mnemonics copyrighted ? intel corporation 1980.
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 51 preliminary c8051f300/1/2/3 8.2. memory organization the memory organization of the cip-51 system controller is similar to that of a standard 8051. there are two sepa- rate memory spaces: program memory and data memory. program and data memory share the same address space but are accessed via different instruction types. the cip-51 memory organization is shown in figure 8.2. 8.2.1. program memory the cip-51 core has a 64k-byte program memory space. the c8051f300/1/2/3 implements 8192 bytes of this pro- gram memory space as in-system, re-programmable flash memory, organized in a contiguous block from addresses 0x0000 to 0x1fff. note: 512 bytes (0x1e00 - 0x1fff) of this memory are reserved for factory use and are not available for user programstorage. program memory is normally assumed to be read-only. however, the cip-51 can write to program memory by setting the programstore write enable bit (psctl.0) and using the movx instruction. this feature provides a mechanism for the cip-51 to update programcode and use the programmemory space for non-volatile data storage. refer to sec- tion 10. flash memory on page 75 for further details. 8.2.2. data memory the cip-51 includes 256 bytes of internal ram mapped into the data memory space from 0x00 through 0xff. the lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. either direct or indi- rect addressing may be used to access the lower 128 bytes of data memory. locations 0x00 through 0x1f are addres- sable as four banks of general purpose registers, each bank consisting of eight byte-wide registers. the next 16 bytes, locations 0x20 through 0x2f, may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. the upper 128 bytes of data memory are accessible only by indirect addressing. this region occupies the same address space as the special function registers (sfr) but is physically separate fromthe sfr space. the addressing mode used by an instruction when accessing locations above 0x7f determines whether the cpu accesses the upper 128 bytes of data memory space or the sfrs. instructions that use direct addressing will access the sfr space. instructions using indirect addressing above 0x7f access the upper 128 bytes of data memory. figure 8.2 illustrates the data memory organization of the cip-51. figure 8.2. memory map flash (in-system programmable in 512 byte sectors) program memory 0x0000 0x1fff (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function register's (direct addressing only) reserved 0x1e00 0x1dff data memory general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 internal data address space
page 52 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 8.2.3. general purpose registers the lower 32 bytes of data memory, locations 0x00 through 0x1f, may be addressed as four banks of general-purpose registers. each bank consists of eight byte-wide registers designated r0 through r7. only one of these banks may be enabled at a time. two bits in the program status word, rs0 (psw.3) and rs1 (psw.4), select the active register bank (see description of the psw in figure 8.6). this allows fast context switching when entering subroutines and inter- rupt service routines. indirect addressing modes use registers r0 and r1 as index registers. 8.2.4. bit addressable locations in addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2f are also accessible as 128 individually addressable bits. each bit has a bit address from0x00 to 0x7f. bit 0 of the byte at 0x20 has bit address 0x00 while bit 7 of the byte at 0x20 has bit address 0x07. bit 7 of the byte at 0x2f has bit address 0x7f. a bit access is distinguished froma full byte access by the type of instruction used (bit source or destination operands as opposed to a byte source or destination). the mcs-51? assembly language allows an alternate notation for bit addressing of the form xx.b where xx is the byte address and b is the bit position within the byte. for example, the instruction: mov c, 22.3h moves the boolean value at 0x13 (bit 3 of the byte at location 0x22) into the carry flag. 8.2.5. stack a programmer's stack can be located anywhere in the 256-byte data memory. the stack area is designated using the stack pointer (sp, 0x81) sfr. the sp will point to the last location used. the next value pushed on the stack is placed at sp+1 and then sp is incremented. a reset initializes the stack pointer to location 0x07. therefore, the first value pushed on the stack is placed at location 0x08, which is also the first register (r0) of register bank 1. thus, if more than one register bank is to be used, the sp should be initialized to a location in the data memory not being used for data storage. the stack depth can extend up to 256 bytes. 8.2.6. special function registers the direct-access data memory locations from 0x80 to 0xff constitute the special function registers (sfrs). the sfrs provide control and data exchange with the cip-51's resources and peripherals. the cip-51 duplicates the sfrs found in a typical 8051 implementation as well as implementing additional sfrs used to configure and access the sub-systems unique to the mcu. this allows the addition of new functionality while retaining compatibility with the mcs-51? instruction set. table 8.2 lists the sfrs implemented in the cip-51 system controller. the sfr registers are accessed anytime the direct addressing mode is used to access memory locations from 0x80 to 0xff. sfrs with addresses ending in 0x0 or 0x8 (e.g. p0, tcon, scon0, ie, etc.) are bit-addressable as well as byte-addressable. all other sfrs are byte-addressable only. unoccupied addresses in the sfr space are reserved for future use. accessing these areas will have an indeterminate effect and should be avoided. refer to the corresponding pages of the datasheet, as indicated in table 8.3, for a detailed description of each register.
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 53 preliminary c8051f300/1/2/3 table 8.3. special function registers sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address description page no. acc 0xe0 accumulator 57 adc0cf 0xbc adc0 configuration 31 adc0cn 0xe8 adc0 control 32 adc0gt 0xc4 adc0 greater-than compare word 35 adc0lt 0xc6 adc0 less-than compare word 35 adc0 0xbe adc0 data word 31 amx0sl 0xbb adc0 multiplexer channel select 30 b0xf0 bregister 57 ckcon 0x8e clock control 127 cpt0cn 0xf8 comparator0 control 41 cpt0md 0x9d comparator0 mode selection 43 cpt0mx 0x9f comparator0 mux selection 42 dph 0x83 data pointer high 55 dpl 0x82 data pointer low 55 eie1 0xe6 extended interrupt enable 1 63 eip1 0xf6 external interrupt priority 1 64 table 8.2. special function register (sfr) memory map f8 cpt0cn pca0l pca0h pca0cpl0 pca0cph0 f0 bp0mdin eip1 e8 adc0cn pca0cpl1 pca0cph1 pca0cpl2 pca0cph2 rstsrc e0 acc xbr0 xbr1 xbr2 it01cf eie1 d8 pca0cn pca0md pca0cpm0 pca0cpm1 pca0cpm2 d0 psw ref0cn c8 tmr2cn tmr2rll tmr2rlh tmr2l tmr2h c0 smb0cn smb0cf smb0dat adc0gt adc0lt b8 ip amx0sl adc0cf adc0 b0 oscxcn oscicn oscicl flscl flkey a8 ie a0 p0mdout 98 scon0 sbuf0 cpt0md cpt0mx 90 88 tcon tmod tl0 tl1 th0 th1 ckcon psctl 80 p0 sp dpl dph pcon 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) (bit addressable)
page 54 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 register address description page flkey 0xb7 flash lock and key 78 flscl 0xb6 flash scale 78 ie 0xa8 interrupt enable 61 ip 0xb8 interrupt priority 62 oscicl 0xb3 internal oscillator calibration 81 oscicn 0xb2 internal oscillator control 81 oscxcn 0xb1 external oscillator control 83 p0 0x80 port 0 latch 91 p0mdin 0xf1 port 0 input mode configuration 91 p0mdout 0xa4 port 0 output mode configuration 92 pca0cn 0xd8 pca control 144 pca0md 0xd9 pca mode 145 pca0cph0 0xfc pca capture 0 high 148 pca0cph1 0xea pca capture 1 high 148 pca0cph2 0xec pca capture 2 high 148 pca0cpl0 0xfb pca capture 0 low 148 pca0cpl1 0xe9 pca capture 1 low 148 pca0cpl2 0xeb pca capture 2 low 148 pca0cpm0 0xda pca module 0 mode register 146 pca0cpm1 0xdb pca module 1 mode register 146 pca0cpm2 0xdc pca module 2 mode register 146 pca0h 0xfa pca counter high 147 pca0l 0xf9 pca counter low 147 pcon 0x87 power control 67 psctl 0x8f programstore r/w control 77 psw 0xd0 programstatus word 56 ref0cn 0xd1 voltage reference control 37 rstsrc 0xef reset source configuration/status 72 sbuf0 0x99 uart 0 data buffer 117 scon0 0x98 uart 0 control 116 smb0cf 0xc1 smbus configuration 100 smb0cn 0xc0 smbus control 102 smb0dat 0xc2 smbus data 104 sp 0x81 stack pointer 56 tmr2cn 0xc8 timer/counter 2 control 131 tcon 0x88 timer/counter control 125 th0 0x8c timer/counter 0 high 128 th1 0x8d timer/counter 1 high 128 tl0 0x8a timer/counter 0 low 128 tl1 0x8b timer/counter 1 low 128 tmod 0x89 timer/counter mode 126 tmr2rlh 0xcb timer/counter 2 reload high 132 tmr2rll 0xca timer/counter 2 reload low 132 tmr2h 0xcd timer/counter 2 high 132 tmr2l 0xcc timer/counter 2 low 132 xbr0 0xe1 port i/o crossbar control 0 89 table 8.3. special function registers
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 55 preliminary c8051f300/1/2/3 8.2.7. register descriptions following are descriptions of sfrs related to the operation of the cip-51 systemcontroller. reserved bits should not be set to logic l. future product versions may use these bits to implement new features in which case the reset value of the bit will be logic 0, selecting the feature's default state. detailed descriptions of the remaining sfrs are included in the sections of the datasheet associated with their corresponding systemfunction. register address description page xbr1 0xe2 port i/o crossbar control 1 89 xbr2 0xe3 port i/o crossbar control 2 90 0x97, 0xae, 0xaf, 0xb4, 0xb6, 0xbf, 0xce, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xdd, 0xde, 0xdf, 0xf5 reserved table 8.3. special function registers figure 8.3. dpl: data pointer low byte bits7-0: dpl: data pointer low. the dpl register is the low byte of the 16-bit dptr. dptr is used to access indirectly addressed flash memory. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x82 figure 8.4. dph: data pointer high byte bits7-0: dph: data pointer high. the dph register is the high byte of the 16-bit dptr. dptr is used to access indirectly addressed flash memory. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x83
page 56 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 figure 8.5. sp: stack pointer bits7-0: sp: stack pointer. the stack pointer holds the location of the top of the stack. the stack pointer is incremented before every push operation. the sp register defaults to 0x07 after reset. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue 00000111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x81 figure 8.6. psw: program status word bit7: cy: carry flag. this bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtrac- tion). it is cleared to logic 0 by all other arithmetic operations. bit6: ac: auxiliary carry flag this bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. it is cleared to logic 0 by all other arithmetic operations. bit5: f0: user flag 0. this is a bit-addressable, general purpose flag for use under software control. bits4-3: rs1-rs0: register bank select. these bits select which register bank is used during register accesses. bit2: ov: overflow flag. this bit is set to logic 1 if the last arithmetic operation resulted in a carry (addition), borrow (subtrac- tion), or overflow (multiply or divide). it is cleared to logic 0 by all other arithmetic operations. bit1: f1: user flag 1. this is a bit-addressable, general purpose flag for use under software control. bit0: parity: parity flag. this bit is set to logic 1 if the sumof the eight bits in the accumulator is odd and cleared if the sumis even. r/wr/wr/wr/wr/wr/wr/w rresetvalue cy ac f0 rs1 rs0 ov f1 parity 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xd0 rs1 rs0 register bank address 0 0 0 0x00 - 0x07 0 1 1 0x08 - 0x0f 1 0 2 0x10 - 0x17 1 1 3 0x18 - 0x1f
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 57 preliminary c8051f300/1/2/3 figure 8.7. acc: accumulator bits7-0: acc: accumulator. this register is the accumulator for arithmetic operations. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue acc.7 acc.6 acc.5 acc.4 acc.3 acc.2 acc.1 acc.0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xe0 figure 8.8. b: b register bits7-0: b: b register. this register serves as a second accumulator for certain arithmetic operations. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xf0
page 58 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 8.3. interrupt handler the cip-51 includes an extended interrupt systemsupporting a total of 12 interrupt sources with two priority levels. the allocation of interrupt sources between on-chip peripherals and external inputs pins varies according to the spe- cific version of the device. each interrupt source has one or more associated interrupt-pending flag(s) located in an sfr. when a peripheral or external source meets a valid interrupt condition, the associated interrupt-pending flag is set to logic 1. if interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is set. as soon as execution of the current instruction is complete, the cpu generates an lcall to a predetermined address to begin execution of an interrupt service routine (isr). each isr must end with an reti instruction, which returns pro- gramexecution to the next instruction that would have been executed if the interrupt request had not occurred. if interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and programexecution continues as normal. (the interrupt-pending flag is set to logic 1 regardless of the interrupt's enable/disable state.) each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in an sfr (ie-eie1). however, interrupts must first be globally enabled by setting the ea bit (ie.7) to logic 1 before the individual interrupt enables are recognized. setting the ea bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable settings. some interrupt-pending flags are automatically cleared by the hardware when the cpu vectors to the isr. however, most are not cleared by the hardware and must be cleared by software before returning from the isr. if an interrupt- pending flag remains set after the cpu completes the return-from-interrupt (reti) instruction, a new interrupt request will be generated immediately and the cpu will re-enter the isr after the completion of the next instruction. 8.3.1. mcu interrupt sources and vectors the mcus support 12 interrupt sources. software can simulate an interrupt by setting any interrupt-pending flag to logic 1. if interrupts are enabled for the flag, an interrupt request will be generated and the cpu will vector to the isr address associated with the interrupt-pending flag. mcu interrupt sources, associated vector addresses, priority order and control bits are summarized in table 8.4 on page 60. refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its inter- rupt-pending flag(s).
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 59 preliminary c8051f300/1/2/3 8.3.2. external interrupts the /int0 and /int1 external interrupt sources are configurable as active high or low, edge or level sensitive. the in0pl (/int0 polarity) and in1pl (/int1 polarity) bits in the it01cf register select active high or active low; the it0andit1bitsintcon( section 15.1. timer 0 and timer 1 on page 121 ) select level or edge sensitive. the table below lists the possible configurations. /int0 and /int1 are assigned to port pins as defined in the it01cf register (see figure 8.13). note that /int0 and /int0 port pin assignments are independent of any crossbar assignments. /int0 and /int1 will monitor their assigned port pins without disturbing the peripheral that was assigned the port pin via the crossbar. to assign a port pin only to /int0 and/or /int1, configure the crossbar to skip the selected pin(s). this is accomplished by setting the associated bit in register xbr0 (see section 12.1. priority crossbar decoder on page 86 for complete details on configuring the crossbar). ie0 (tcon.1) and ie1 (tcon.3) serve as the interrupt-pending flags for the /int0 and /int1 external interrupts, respectively. if an /int0 or /int1 external interrupt is configured as edge-sensitive, the corresponding interrupt- pending flag is automatically cleared by the hardware when the cpu vectors to the isr. when configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined by the corresponding polarity bit (in0pl or in1pl); the flag remains logic 0 while the input is inactive. the external interrupt source must hold the input active until the interrupt request is recognized. it must then deactivate the interrupt request before execution of the isr completes or another interrupt request will be generated. 8.3.3. interrupt priorities each interrupt source can be individually programmed to one of two priority levels: low or high. a low priority inter- rupt service routine can be preempted by a high priority interrupt. a high priority interrupt cannot be preempted. each interrupt has an associated interrupt priority bit in an sfr (ip or eip1) used to configure its priority level. low prior- ity is the default. if two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. if both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in table 8.4. 8.3.4. interrupt latency interrupt response time depends on the state of the cpu when the interrupt occurs. pending interrupts are sampled and priority decoded each systemclock cycle. therefore, the fastest possible response time is 5 systemclock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the lcall to the isr. if an interrupt is pending when a reti is executed, a single instruction is executed before an lcall is made to service the pending interrupt. therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the cpu is performing an reti instruction followed by a div as the next instruction. in this case, the response time is 18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the reti, 8 clock cycles to complete the div instruction and 4 clock cycles to execute the lcall to the isr. if the cpu is executing an isr for an interrupt with equal or higher priority, the new interrupt will not be serviced until the current isr completes, including the reti and following instruction. it0 in0pl /int0 interrupt it1 in1pl /int1 interrupt 0 0 active low, edge sensitive 0 0 active low, edge sensitive 0 1 active high, edge sensitive 0 1 active high, edge sensitive 1 0 active low, level sensitive 1 0 active low, level sensitive 1 1 active high, level sensitive 1 1 active high, level sensitive
page 60 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 table 8.4. interrupt summary interrupt source interrupt vector priority order pending flag bit addressable? cleared by hw? enable flag priority control reset 0x0000 top none n/a n/a always enabled always highest external interrupt 0 (/int0) 0x0003 0 ie0 (tcon.1) y y ex0 (ie.0) px0 (ip.0) timer 0 overflow 0x000b 1 tf0 (tcon.5) y y et0 (ie.1) pt0 (ip.1) external interrupt 1 (/int1) 0x0013 2 ie1 (tcon.3) y y ex1 (ie.2) px1 (ip.2) timer 1 overflow 0x001b 3 tf1 (tcon.7) y y et1 (ie.3) pt1 (ip.3) uart0 0x0023 4 ri0 (scon0.0) ti0 (scon0.1) y n es0 (ie.4) ps0 (ip.4) timer 2 overflow 0x002b 5 tf2h (tmr2cn.7) tf2l (tmr2cn.6) y n et2 (ie.5) pt2 (ip.5) smbus interface 0x0033 6 si (smb0cn.0) y n esmb0 (eie1.0) psmb0 (eip1.0) adc0 window compare 0x003b 7 ad0wint (adc0cn.3) y n ewadc0 (eie1.1) pwadc0 (eip1.1) adc0 conversion complete 0x0043 8 ad0int (adc0cn.5) y n eadc0c (eie1.2) padc0c (eip1.2) programmable counter array 0x004b 9 cf (pca0cn.7) ccfn (pca0cn.n) y n epca0 (eie1.3) ppca0 (eip1.3) comparator0 falling edge 0x0053 10 cp0fif (cpt0cn.4) n n ecp0f (eie1.4) pcp0f (eip1.4) comparator0 rising edge 0x005b 11 cp0rif (cpt0cn.5) n n ecp0r (eie1.5) pcp0r (eip1.5)
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 61 preliminary c8051f300/1/2/3 8.3.5. interrupt register descriptions the sfrs used to enable the interrupt sources and set their priority level are described below. refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). figure 8.9. ie: interrupt enable bit7: ea: enable all interrupts. this bit globally enables/disables all interrupts. it overrides the individual interrupt mask settings. 0: disable all interrupt sources. 1: enable each interrupt according to its individual mask setting. bit6: iegf0: general purpose flag 0. this is a general purpose flag for use under software control. bit5: et2: enable timer 2 interrupt. this bit sets the masking of the timer 2 interrupt. 0: disable timer 2 interrupt. 1: enable interrupt requests generated by the tf2l or tf2h flags (tmr2cn.7). bit4: es0: enable uart0 interrupt. this bit sets the masking of the uart0 interrupt. 0: disable uart0 interrupt. 1: enable uart0 interrupt. bit3: et1: enable timer 1 interrupt. this bit sets the masking of the timer 1 interrupt. 0: disable all timer 1 interrupt. 1: enable interrupt requests generated by the tf1 flag (tcon.7). bit2: ex1: enable external interrupt 1. this bit sets the masking of external interrupt 1. 0: disable external interrupt 1. 1: enable interrupt requests generated by the /int1 input. bit1: et0: enable timer 0 interrupt. this bit sets the masking of the timer 0 interrupt. 0: disable all timer 0 interrupt. 1: enable interrupt requests generated by the tf0 flag (tcon.5). bit0: ex0: enable external interrupt 0. this bit sets the masking of external interrupt 0. 0: disable external interrupt 0. 1: enable interrupt requests generated by the /int0 input. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue ea iegf0 et2 es0 et1 ex1 et0 ex0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xa8
page 62 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 figure 8.10. ip: interrupt priority bits7-6: unused. read = 11b, write = don't care. bit5: pt2: timer 2 interrupt priority control. this bit sets the priority of the timer 2 interrupt. 0: timer 2 interrupt priority determined by default priority order. 1: timer 2 interrupts set to high priority level. bit4: ps0: uart0 interrupt priority control. this bit sets the priority of the uart0 interrupt. 0: uart0 interrupt priority determined by default priority order. 1: uart0 interrupts set to high priority level. bit3: pt1: timer 1 interrupt priority control. this bit sets the priority of the timer 1 interrupt. 0: timer 1 interrupt priority determined by default priority order. 1: timer 1 interrupts set to high priority level. bit2: px1: external interrupt 1 priority control. this bit sets the priority of the external interrupt 1 interrupt. 0: external interrupt 1 priority determined by default priority order. 1: external interrupt 1 set to high priority level. bit1: pt0: timer 0 interrupt priority control. this bit sets the priority of the timer 0 interrupt. 0: timer 0 interrupt priority determined by default priority order. 1: timer 0 interrupt set to high priority level. bit0: px0: external interrupt 0 priority control. this bit sets the priority of the external interrupt 0 interrupt. 0: external interrupt 0 priority determined by default priority order. 1: external interrupt 0 set to high priority level. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue - - pt2 ps0 pt1 px1 pt0 px0 11000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xb8
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 63 preliminary c8051f300/1/2/3 figure 8.11. eie1: extended interrupt enable 1 bits7-6: unused. read = 00b. write = dont care. bit5: ecp0r: enable comparator0 (cp0) rising edge interrupt. this bit sets the masking of the cp0 rising edge interrupt. 0: disable cp0 rising edge interrupt. 1: enable interrupt requests generated by the cp0rif flag (cpt0cn.5). bit4: ecp0f: enable comparator0 (cp0) falling edge interrupt. this bit sets the masking of the cp0 falling edge interrupt. 0: disable cp0 falling edge interrupt. 1: enable interrupt requests generated by the cp0fif flag (cpt0cn.4). bit3: epca0: enable programmable counter array (pca0) interrupt. this bit sets the masking of the pca0 interrupts. 0: disable all pca0 interrupts. 1: enable interrupt requests generated by pca0. bit2: eadc0c: enable adc0 conversion complete interrupt. this bit sets the masking of the adc0 conversion complete interrupt. 0: disable adc0 conversion complete interrupt. 1: enable interrupt requests generated by the ad0int flag (adc0cn.5). bit1: ewadc0: enable window comparison adc0 interrupt. this bit sets the masking of adc0 window comparison interrupt. 0: disable adc0 window comparison interrupt. 1: enable interrupt requests generated by adc0 window compare flag (adc0cn.3). bit0: esmb0: enable smbus interrupt. this bit sets the masking of the smbus interrupt. 0: disable all smbus interrupts. 1: enable interrupt requests generated by the si flag (smb0cn.0). r/wr/wr/wr/wr/wr/wr/wr/wresetvalue - - ecp0r ecp0f epca0 eadc0c ewadc0 esmb0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe6
page 64 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 figure 8.12. eip1: extended interrupt priority 1 bits7-6: unused. read = 11b. write = dont care. bit5: pcp0r: comparator0 (cp0) rising interrupt priority control. this bit sets the priority of the cp0 rising-edge interrupt. 0: cp0 rising interrupt set to low priority level. 1: cp0 rising interrupt set to high priority level. bit4: pcp0f: comparator0 (cp0) falling interrupt priority control. this bit sets the priority of the cp0 falling-edge interrupt. 0: cp0 falling interrupt set to low priority level. 1: cp0 falling interrupt set to high priority level. bit3: ppca0: programmable counter array (pca0) interrupt priority control. this bit sets the priority of the pca0 interrupt. 0: pca0 interrupt set to low priority level. 1: pca0 interrupt set to high priority level. bit2: padc0c adc0 conversion complete interrupt priority control this bit sets the priority of the adc0 conversion complete interrupt. 0: adc0 conversion complete interrupt set to low priority level. 1: adc0 conversion complete interrupt set to high priority level. bit1: pwadc0: adc0 window comparator interrupt priority control. this bit sets the priority of the adc0 window interrupt. 0: adc0 window interrupt set to low priority level. 1: adc0 window interrupt set to high priority level. bit0: psmb0: smbus interrupt priority control. this bit sets the priority of the smbus interrupt. 0: smbus interrupt set to low priority level. 1: smbus interrupt set to high priority level. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue - - pcp0r pcp0f ppca0 padc0c pwadc0 psmb0 11000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf6
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 65 preliminary c8051f300/1/2/3 bit7: in1pl: /int1 polarity 0: /int1 input is active low. 1: /int1 input is active high. bits6-4: in1sl2-0: /int1 port pin selection bits these bits select which port pin is assigned to /int1. note that this pin assignment is independent of the crossbar; /int1 will monitor the assigned port pin without disturbing the peripheral that has been assigned the port pin via the crossbar. the crossbar will not assign the port pin to a peripheral if it is configured to skip the selected pin (accomplished by setting to 1 the corresponding bit in register xbr0). bit3: in0pl: /int0 polarity 0: /int0 interrupt is active low. 1: /int0 interrupt is active high. bits2-0: int0sl2-0: /int0 port pin selection bits these bits select which port pin is assigned to /int0. note that this pin assignment is independent of the crossbar. /int0 will monitor the assigned port pin without disturbing the peripheral that has been assigned the port pin via the crossbar. the crossbar will not assign the port pin to a peripheral if it is configured to skip the selected pin (accomplished by setting to 1 the corresponding bit in register xbr0). r/wr/wr/wr/wr/wr/wr/wr/wresetvalue in1pl in1sl2 in1sl1 in1sl0 in0pl in0sl2 in0sl1 in0sl0 00000001 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe4 in1sl2-0 /int1 port pin 000 p0.0 001 p0.1 010 p0.2 011 p0.3 100 p0.4 101 p0.5 110 p0.6 111 p0.7 in0sl2-0 /int0 port pin 000 p0.0 001 p0.1 010 p0.2 011 p0.3 100 p0.4 101 p0.5 110 p0.6 111 p0.7 figure 8.13. int01cf: int0/int1 configuration register
page 66 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 8.4. power management modes the cip-51 core has two software programmable power management modes: idle and stop. idle mode halts the cpu while leaving the peripherals and clocks active. in stop mode, the cpu is halted, all interrupts and timers (except the missing clock detector) are inactive, and the systemclock is stopped (analog peripherals remain in their selected states). since clocks are running in idle mode, power consumption is dependent upon the system clock frequency and the number of peripherals left in active mode before entering idle. stop mode consumes the least power. figure 1.15 describes the power control register (pcon) used to control the cip-51's power management modes. although the cip-51 has idle and stop modes built in (as with any standard 8051 architecture), power management of the entire mcu is better accomplished by enabling/disabling individual peripherals as needed. each analog periph- eral can be disabled when not in use and placed in low power mode. digital peripherals, such as timers or serial buses, draw little power when they are not in use. turning off the oscillators lowers power consuption considerably; however a reset is required to restart the mcu. 8.4.1. idle mode setting the idle mode select bit (pcon.0) causes the cip-51 to halt the cpu and enter idle mode as soon as the instruction that sets the bit completes execution. all internal registers and memory maintain their original data. all analog and digital peripherals can remain active during idle mode. idle mode is terminated when an enabled interrupt is asserted or a reset occurs. the assertion of an enabled interrupt will cause the idle mode selection bit (pcon.0) to be cleared and the cpu to resume operation. the pending inter- rupt will be serviced and the next instruction to be executed after the return frominterrupt (reti) will be the instruc- tion immediately following the one that set the idle mode select bit. if idle mode is terminated by an internal or external reset, the cip-51 performs a normal reset sequence and begins program execution at address 0x0000. if enabled, the watchdog timer (wdt) will eventually cause an internal watchdog reset and thereby terminate the idle mode. this feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the pcon register. if this behavior is not desired, the wdt may be disabled by software prior to entering the idle mode if the wdt was initially configured to allow this operation. this provides the opportunity for additional power savings, allowing the system to remain in the idle mode indefinitely, waiting for an external stimulus to wake up the system. refer to section 16.3. watchdog timer mode on page 142 for more information on the use and configuration of the wdt. 8.4.2. stop mode setting the stop mode select bit (pcon.1) causes the cip-51 to enter stop mode as soon as the instruction that sets the bit completes execution. in stop mode the internal oscillator, cpu, and all digital peripherals are stopped; the state of the external oscillator circuit is not affected. each analog peripheral (including the external oscillator circuit) may be shut down individually prior to entering stop mode. stop mode can only be terminated by an internal or external reset. on reset, the cip-51 performs the normal reset sequence and begins program execution at address 0x0000. if enabled, the missing clock detector will cause an internal reset and thereby terminate the stop mode. the missing clock detector should be disabled if the cpu is to be put to in stop mode for longer than the mcd timeout of 100 sec.
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 67 preliminary c8051f300/1/2/3 bits7-2: gf5-gf0: general purpose flags 5-0. these are general purpose flags for use under software control. bit1: stop: stop mode select. setting this bit will place the cip-51 in stop mode. this bit will always be read as 0. 1: goes into power down mode. (turns off oscillators). bit0: idle: idle mode select. setting this bit will place the cip-51 in idle mode. this bit will always be read as 0. 1: goes into idle mode. (shuts off clock to cpu, but clock to timers, interrupts, serial ports, and analog peripherals are still active.) r/wr/wr/wr/wr/wr/wr/wr/wresetvalue gf5 gf4 gf3 gf2 gf1 gf0 stop idle 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x87 figure 8.14. pcon: power control register
page 68 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 notes
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 69 preliminary c8051f300/1/2/3 9. reset sources reset circuitry allows the controller to be easily placed in a predefined default condition. on entry to this reset state, the following occur: ? cip-51 halts programexecution ? special function registers (sfrs) are initialized to their defined reset values ? external port pins are forced to a known state ? interrupts and timers are disabled. all sfrs are reset to the predefined values noted in the sfr detailed descriptions. the contents of internal data mem- ory are unaffected during a reset; any previously stored data is preserved. however, since the stack pointer sfr is reset, the stack is effectively lost even though the data on the stack is not altered. the port i/o latches are reset to 0xff (all logic ones) in open-drain mode. weak pull-ups are enabled during and after the reset. for vdd monitor and power-on resets, the /rst pin is driven low until the device exits the reset state. on exit fromthe reset state, the programcounter (pc) is reset, and the systemclock defaults to the internal oscillator. refer to section 11. oscillators on page 79 for information on selecting and configuring the system clock source. the watchdog timer is enabled with the system clock divided by 12 as its clock source ( section 16.3. watchdog timer mode on page 142 details the use of the watchdog timer). once the system clock source is stable, program execution begins at location 0x0000. pca wdt missing clock detector (one- shot) (software reset) system reset reset funnel p0.x p0.y en swrsf internal oscillator system clock cip-51 microcontroller core extended interrupt handler clock select en wdt enable mcd enable xtal1 xtal2 external oscillator drive errant flash operation + - comparator 0 c0rsef /rst (wired-or) power on reset + - vdd supply monitor enable '0' figure 9.1. reset sources
page 70 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 9.1. power-on reset during power-up, the device is held in a reset state and the /rst pin is driven low until vdd settles above 2.7 v (v rst ). a delay occurs before the device is released from reset; the delay decreases as the vdd ramp time increases (vdd ramp time is defined as how fast vdd ramps from 0 v to 2.7 v). figure 9.2. plots the power-on and vdd monitor reset timing. the maximum vdd ramp time is 1 ms; slower ramp times may cause the device to be released fromreset before vdd reaches the v rst level. for ramp times less than 1 ms, the power-on reset delay (t pordelay ) is typically less than 0.3 ms. on exit froma power-on reset, the porsf flag (rstsrc.1) is set by hardware to logic 1. when porsf is set, all of the other reset flags in the rstsrc register are indeterminate (porsf is cleared by all other resets). since all resets cause programexecution to begin at the same location (0x0000) software can read the porsf flag to determine if a power-up was the cause of reset. the content of internal data memory should be assumed to be undefined after a power-on reset. the vdd monitor is disabled following a power-on reset. 9.2. power-fail reset / vdd monitor when a power-down transition or power irregularity causes vdd to drop below v rst , the power supply monitor will drive the /rst pin low and hold the cip-51 in a reset state (see figure 9.2). when vdd returns to a level above v rst , the cip-51 will be released from the reset state. note that even though internal data memory contents are not altered by the power-fail reset, it is impossible to determine if vdd dropped below the level required for data reten- tion. if the porsf flag reads 1, the data may no longer be valid. the vdd monitor is disabled after power-on resets; however its defined state (enabled/disabled) is not altered by any other reset source. for example, if the vdd monitor is enabled and a software reset is performed, the vdd monitor will still be enabled after the reset. the vdd monitor is enabled by writing a 1 to the porsf bit in register rstsrc. see figure 9.2 for vdd monitor timing; note that the reset delay is not incurred after a vdd monitor reset. see table 9.1 for electrical characteristics of the vdd monitor. important note: enabling the vdd monitor will immediately generate a system reset. the device will then return fromthe reset state with the vdd monitor enabled. power-on reset vdd monitor reset /rst t volts 1.0 2.0 logic high logic low t pordelay v d d 2.70 2.55 v rst vdd figure 9.2. power-on and vdd monitor reset timing
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 71 preliminary c8051f300/1/2/3 9.3. external reset the external /rst pin provides a means for external circuitry to force the device into a reset state. asserting an active-low signal on the /rst pin generates a reset; an external pull-up and/or decoupling of the /rst pin may be necessary to avoid erroneous noise-induced resets. see table 9.1 for complete /rst pin specifications. the pinrsf flag (rstsrc.0) is set on exit froman external reset. 9.4. missing clock detector reset the missing clock detector (mcd) is a one-shot circuit that is triggered by the systemclock. if the systemclock remains high or low for more than 100 s, the one-shot will time out and generate a reset. after a mcd reset, the mcdrsf flag (rstsrc.2) will read 1, signifying the mcd as the reset source; otherwise, this bit reads 0. writ- ing a 1 to the mcdrsf bit enables the missing clock detector; writing a 0 disables it. the state of the /rst pin is unaffected by this reset. 9.5. comparator0 reset comparator0 can be configured as a reset source by writing a 1 to the c0rsef flag (rstsrc.5). comparator0 should be enabled and allowed to settle prior to writing to c0rsef to prevent any turn-on chatter on the output from generating an unwanted reset. the comparator0 reset is active-low: if the non-inverting input voltage (on cp0+) is less than the inverting input voltage (on cp0-), the device is put into the reset state. after a comparator0 reset, the c0rsef flag (rstsrc.5) will read 1 signifying comparator0 as the reset source; otherwise, this bit reads 0. the state of the /rst pin is unaffected by this reset. 9.6. pca watchdog timer reset the programmable watchdog timer (wdt) function of the programmable counter array (pca) can be used to pre- vent software fromrunning out of control during a systemmalfunction. the pca wdt function can be enabled or disabled by software as described in section 16.3. watchdog timer mode on page 142 ; the wdt is enabled and clocked by sysclk / 12 following any reset. if a systemmalfunction prevents user software fromupdating the wdt, a reset is generated and the wdtrsf bit (rstsrc.5) is set to 1. the state of the /rst pin is unaffected by this reset. 9.7. flash error reset if a flash read/write/erase attempt is unsuccessful, a system reset is generated. this may occur due to any of the following: ? a flash write or erase is attempted above user code space. this occurs when pswe is set to 1 and a movx operation is attempted above address 0x1dff. ? a flash read is attempted above user code space. this occurs when a movc operation is attempted above address 0x1dff. ? a programread is attempted above the reserved address space. this occurs when user code attempts to branch to an address above 0x1fff. the ferror bit (rstsrc.6) is set following a flash error reset. the state of the /rst pin is unaffected by this reset. 9.8. software reset software may force a reset by writing a 1 to the swrsf bit (rstsrc.4). the swrsf bit will read 1 following a software forced reset. the state of the /rst pin is unaffected by this reset.
page 72 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 figure 9.3. rstsrc: reset source register (note: do not use read-modify-write operations (orl, anl) on this register) bit7: unused. read = 0. write = dont care. bit6: ferror: flash error indicator 0: source of last reset was not a flash read/write/erase error. 1: source of last reset was a flash read/write/erase error. bit5: c0rsef: comparator0 reset enable and flag write 0: comparator0 is not a reset source. 1: comparator0 is a reset source (active-low). read 0: source of last reset was not comparator0. 1: source of last reset was comparator0. bit4: swrsf: software reset force and flag. write 0: no effect. 1: forces a systemreset. read 0: source of last reset was not a write to the swrsf bit. 1: source of last was a write to the swrsf bit. bit3: wdtrsf: watchdog timer reset flag 0: source of last reset was not a wdt timeout. 1: source of last reset was a wdt timeout. bit2: mcdrsf: missing clock detector flag write: 0: missing clock detector disabled 1: missing clock detector enabled; triggers a reset if a missing clock condition is detected. read: 0: source of last reset was not a missing clock detector timeout. 1: source of last reset was a missing clock detector timeout. bit1: porsf: power-on reset force and flag this bit is set anytime a power-on reset occurs. this may be due to a true power-on reset or a vdd monitor reset. in either case, data memory should be considered indeterminate following the reset. writing this bit enables/disables the vdd monitor. write: 0: vdd monitor disabled. 1: vdd monitor enabled. read: 0: last reset was not a power-on or vdd monitor reset. 1: last reset was a power-on or vdd monitor reset; all other reset flags indeterminate. bit0: pinrsf: hw pin reset flag 0: source of last reset was not /rst pin. 1: source of last reset was /rst pin. r r r/w r/w r r/w r/w r reset value - ferror c0rsef swrsf wdtrsf mcdrsf porsf pinrsf 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xef
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 73 preliminary c8051f300/1/2/3 table 9.1. reset electrical characteristics -40c to +85c unless otherwise specified. parameter conditions min typ max units /rst output low voltage i ol = 8.5 ma, vdd = 2.7 v to 3.6 v 0.6 v /rst input high voltage 0.7 x vdd v /rst input low voltage 0.3 x vdd /rst input leakage current /rst = 0.0 v 25 40 a vdd por threshold (v rst ) 2.40 2.55 2.70 v missing clock detector timeout time from last system clock rising edge to reset initiation 100 220 500 s reset time delay delay between release of any reset source and code execution at location 0x0000 5.0 s minimum /rst low time to generateasystemreset 15 s
page 74 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 notes
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 75 preliminary c8051f300/1/2/3 10. flash memory 8k bytes of on-chip, re-programmable flash memory is included for program code and non-volatile data storage (note: 512 bytes at location 0x1e00 to 0x1fff are reserved for factory use). the flash memory can be pro- grammed in-system, a single byte at a time, through the c2 interface or by software using the movx instruction. once cleared to logic 0, a flash bit must be erased to set it back to logic 1. flash bytes would typically be erased (set to 0xff) before being reprogrammed. the write and erase operations are automatically timed by hardware for proper execution; data polling to determine the end of the write/erase operation is not required. code execution is stalled during a flash write/erase operation. the flash memory is designed to withstand at least 20,000 write/ erase cycles; refer to table 10.1 for complete flash memory electrical characteristics. 10.1. programming the flash memory the simplest means of programming the flash memory is through the c2 interface using programming tools pro- vided by cygnal or a third party vendor. this is the only means for programming a non-initialized device. for details on the c2 commands to program flash memory, see section 17. c2 interface on page 149 . 10.1.1. flash lock and key functions flash writes and erases by user software are protected with a lock and key function; flash reads by user software are unrestricted. the flash lock and key register (flkey) must be written with the correct key codes, in sequence, before flash operations may be performed. the key codes are: 0xa5, 0xf1. the timing does not matter, but the codes must be written in order. if the key codes are written out of order, or the wrong codes are written, flash writes and erases will be disabled until the next systemreset. flash writes and erases will also be disabled if a flash write or erase is attempted before the key codes have been written properly. the flash lock resets after each write or erase; the key codes must be written again before a following flash operation can be performed. the flkey register is detailed in figure 10.2. 10.1.2. flash erase procedure the flash memory can be programmed by software using the movx instruction with the address and data byte to be programmed provided as normal operands. before writing to flash memory using movx, flash write opera- tions must be enabled by: (1) setting the pswe program store write enable bit (psctl.0) to logic 1 (this directs the movx writes to target flash memory); and (2) writing the flash key codes in sequence to the flash lock register (flkey). the pswe bit remains set until cleared by software. a write to flash memory can clear bits but cannot set them; only an erase operation can set bits in flash. there- fore, the byte location to be programmed should be erased before a new value is written. the 8k byte flash mem- ory is organized in 512-byte pages. the erase operation applies to an entire page (setting all bytes in the page to 0xff). to erase an entire 512-byte page, performthe following steps: step 1. disable interrupts (recommended). step 2. set the programstore erase enable bit (psee in the psctl register). step 3. set the programstore write enable bit (pswe in the psctl register). step 4. write the first key code to flkey: 0xa5. step 5. write the second key code to flkey: 0xf1. step 6. using the movx instruction, write a data byte to any location within the 512-byte page to be erased.
page 76 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 10.1.3. flash write procedure flash bytes are programmed by software with the following sequence: step 1. disable interrupts (recommended). step 2. erase the 512-byte flash page containing the target location, as described in section 10.1.2 . step 3. set the pswe bit in psctl. step 4. clear the psee bit in psctl. step 5. write the first key code to flkey: 0xa5. step 6. write the second key code to flkey: 0xf1. step 7. using the movx instruction, write a single data byte to the desired location within the 512-byte sector. steps 5-7 must be repeated for each byte to be written. after flash writes are complete, pswe should be cleared so that movx instructions do not target programmemory. table 10.1. flash electrical characteristics parameter conditions min typ max units endurance 20k 100k erase/write erase cycle time 25 mhz systemclock 10 15 20 ms write cycle time 25 mhz systemclock 40 55 70 s
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 77 preliminary c8051f300/1/2/3 10.2. non-volatile data storage the flash memory can be used for non-volatile data storage as well as program code. this allows data such as cal- ibration coefficients to be calculated and stored at run time. data is written using the movx instruction and read using the movc instruction. 10.3. security options the cip-51 provides security options to protect the flash memory from inadvertent modification by software as well as to prevent the viewing of proprietary programcode and constants. the programstore write enable (bit pswe in register psctl) and the programstore erase enable (bit psee in register psctl) bits protect the flash memory from accidental modification by software. pswe must be explicitly set to 1 before software can modify the flash memory; both pswe and psee must be set to 1 before software can erase flash memory. additional security features prevent proprietary programcode and data constants frombeing read or altered across the c2 inter- face. a security lock byte stored at flash location 0x1dff protects the flash programmemory frombeing read or altered across the c2 interface. bits7-4 of the lock byte protect against flash writes; clearing any of these bits to logic 0 prevents all flash memory from being written across the c2 interface. bits 3-0 of the lock byte protect against flash reads; clearing any of these bits to logic 0 prevents all flash memory from being read across the c2 interface. the lock bits can always be read and cleared to logic 0 regardless of the security settings. however, the only means of removing a lock once set is to erase the entire program memory space by performing a c2 device erase operation. bits7-2: unused: read = 000000b, write = dont care. bit1: psee: programstore erase enable setting this bit (in combination with pswe) allows an entire page of flash program memory to be erased. if this bit is logic 1 and flash writes are enabled (pswe is logic 1), a write to flash memory using the movx instruction will erase the entire page that contains the location addressed by the movx instruction. the value of the data byte written does not matter. 0: flash program memory erasure disabled. 1: flash program memory erasure enabled. bit0: pswe: programstore write enable setting this bit allows writing a byte of data to the flash program memory using the movx instruction. the flash location should be erased before writing data. 0: writes to flash program memory disabled. 1: writes to flash program memory enabled; the movx instruction targets flash memory. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue - - - - - - psee pswe 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8f figure 10.1. psctl: program store r/w control
page 78 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 figure 10.2. flkey: flash lock and key register bits7-0: flkey: flash lock and key register write: this register must be written to before flash writes or erases can be performed. flash remains locked until this register is written to with the following key codes: 0xa5, 0xf1. the timing of the writes does not matter, as long as the codes are written in order. the key codes must be written for each flash write or erase operation. flash will be locked until the next systemreset if the wrong codes are written or if a flash operation is attempted before the codes have been written correctly. read: when read, bits 1-0 indicate the current flash lock state. 00: flash is write/erase locked. 01: the first key code has been written (0xa5). 10: flash is unlocked (writes/erases allowed). 11: flash writes/erases disabled until the next reset. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb7 figure 10.3. flscl: flash scale register bits7: fose: flash one-shot enable this bit enables the 50 ns flash read one-shot. when the flash one-shot disabled, the flash sense amps are enabled for a full clock cycle during flash reads. 0: flash one-shot disabled. 1: flash one-shot enabled. bits6-0: reserved. read = 0. must write 0. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue fose reserved reserved reserved reserved reserved reserved reserved 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb7
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 79 preliminary c8051f300/1/2/3 11. oscillators c8051f300/1/2/3 devices include a programmable internal oscillator and an external oscillator drive circuit. the internal oscillator can be enabled/disabled and calibrated using the oscicn and oscicl registers, as shown in figure 11.1. the systemclock can be sourced by the external oscillator circuit, the internal oscillator, or a scaled ver- sion of the internal oscillator. the internal oscillator's electrical specifications are given in table 11.1 on page 82. 11.1. programmable internal oscillator all c8051f300/1/2/3 devices include a programmable internal oscillator that defaults as the system clock after a sys- tem reset. the internal oscillator period can be programmed via the oscicl register as defined by equation 11.1, where f base is the frequency of the internal oscillator following a reset, ? t is the change in internal oscillator period, and ? oscicl is a change to the value held in register oscicl. on c8051f300/1 devices, oscicl is factory calibrated to obtain a 24.5 mhz base frequency ( f base ). section 11.1.1 details oscillator programming for c8051f300/1 devices. on C8051F302/3 devices oscicl always resets to 0x20. the resulting base frequency is a nominal 20 mhz and may vary 20% from device-to-device. section 11.1.2 details oscillator programming for C8051F302/3 devices. electrical specifications for the precision internal oscillator are given in table 11.1 on page 82. the programmed internal oscillator frequency must not exceed 25 mhz. note that the system clock may be derived from the pro- grammed internal oscillator divided by 1, 2, 4, or 8, as defined by the ifcn bits in register oscicn. the divide value defaults to 8 following a reset. figure 11.1. oscillator diagram osc programmable internal clock generator input circuit en sysclk n oscicl oscicn ifrdy clksl ioscen ifcn1 ifcn0 xtal1 xtal2 option 2 vdd xtal2 option 1 10m ? option 3 xtal2 option 4 xtal2 oscxcn xtlvld xoscmd2 xoscmd1 xoscmd0 xfcn2 xfcn1 xfcn0 equation 11.1. change in internal oscillator period with oscicl ? t 0.005 1 f base ------------ - ? oscicl =
page 80 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 11.1.1. programming the internal oscillator on c8051f300/1 devices on c8051f300/1 devices, the oscicl reset value is factory calibrated to result in a 24.5 mhz internal oscillator with a 2% accuracy. note that the calibrated reset value of oscicl may vary from device-to-device. software should read and adjust the value of oscicl according to equation 11.1 to obtain the desired frequency. the example below shows how to obtain a 16 mhz internal oscillator frequency. 11.1.2. programming the internal oscillator on C8051F302/3 devices on C8051F302/3 devices, oscicl resets to 0x20 and results in a nominal 20 mhz internal oscillator with a 20% variation fromdevice-to-device. to programa desired frequency on these devices, the internal oscillator frequency must be measured with oscicl at a known value. the measured frequency and known oscicl value can then be used to approximate the desired frequency according to equation 11.1 and the above procedure. it may be necessary to measure the programmed oscillator frequency and fine-tune oscicl appropriately. this procedure must be fol- lowed for each individual device. the internal oscillator frequency may be measured by routing sysclk to a port pin as described in section 12.1. priority crossbar decoder on page 86 . f base is the internal oscillator reset frequency; t base is the oscillator reset period. f des is the desired internal oscillator frequency; t des is the desired oscillator period. the required change in period ( ? t des ) is the difference between the base period and the desired period. using equation 11.1 and the above calculations, find ? oscicl : ? oscicl is rounded to the nearest integer (-106) and added to the reset value of register oscicl. the resultin g internal oscillator frequency is: f base 24500000 hz = t base 1 24500000 ----------------------- - s = f des 16000000 hz = t des 1 16000000 ----------------------- - s = ? t des 1 24500000 ----------------------- - 1 16000000 ----------------------- - C 0.2 -7 10 s C == 0.2 -7 10 C 0.005 1 f base ------------ - ? oscicl = ? oscicl 106.25 C = f osc 16013100 hz =
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 81 preliminary c8051f300/1/2/3 figure 11.2. oscicl: internal oscillator calibration register bit7: unused. read = 0. write = dont care. bits 6-0: oscicl: internal oscillator calibration register this register determines the internal oscillator period as per equation 11.1. the reset value for oscicl defines the internal oscillator base frequency. on c8051f300/1 devices, the reset value is factory calibrated to generate an internal oscillator frequency of 24.5 mhz. on C8051F302/3 devices, the reset value is always 0x20; this value results in a nominal frequency of 20 mhz with a 20% vari- ation fromdevice-to-device. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue va ri a b l e bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb3 figure 11.3. oscicn: internal oscillator control register bits7-5: unused. read = 000b, write = don't care bit4: ifrdy: internal oscillator frequency ready flag 0: internal oscillator not running at programmed frequency. 1: internal oscillator running at programmed frequency. bit3: clksl: systemclock source select bit 0: sysclk derived fromthe internal oscillator, and scaled as per the ifcn bits. 1: sysclk derived fromthe external oscillator circuit. bit2: ioscen: internal oscillator enable bit 0: internal oscillator disabled 1: internal oscillator enabled bits1-0: ifcn1-0: internal oscillator frequency control bits 00: sysclk derived frominternal oscillator divided by 8. 01: sysclk derived frominternal oscillator divided by 4. 10: sysclk derived frominternal oscillator divided by 2. 11: sysclk derived frominternal oscillator divided by 1. r/wr/wr/w r r/wr/wr/wr/wresetvalue - - - ifrdy clksl ioscen ifcn1 ifcn0 00010100 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb2
page 82 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 11.2. external oscillator drive circuit the external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or rc network. a cmos clock may also provide a clock input. for a crystal or ceramic resonator configuration, the crystal/resonator must be wired across the xtal1 and xtal2 pins as shown in option 1 of figure 11.1. a 10 m ? resistor also must be wired across the xtal2 and xtal1 pins for the crystal/resonator configuration. in rc, capacitor, or cmos clock config- uration, the clock source should be wired to the xtal2 pin as shown in option 2, 3, or 4 of figure 11.1. the type of external oscillator must be selected in the oscxcn register, and the frequency control bits (xfcn) must be selected appropriately (see figure 11.4). important note on external oscillator usage: port pins must be configured when using the external oscillator cir- cuit. when the external oscillator drive circuit is enabled in crystal/resonator mode, port pins p0.2 and p0.3 are occu- pied as xtal1 and xtal2 respectively. when the external oscillator drive circuit is enabled in capacitor, rc, or cmos clock mode, port pin p0.3 is occupied as xtal2. in either case, the occupied port pins should be configured as analog inputs, and the crossbar should be configured to skip the occupied port pins. see section 12.2. port i/o initialization on page 88 for details on port input mode selection; see section 12.1. priority crossbar decoder on page 86 for crossbar configuration. 11.3. system clock selection the clksl bit in register oscicn selects which oscillator generates the systemclock. clksl must be set to 1 for the systemclock to run fromthe external oscillator; however the external oscillator may still clock peripherals (tim- ers, pca) when the internal oscillator is selected as the systemclock. the systemclock may be switched on-the-fly between the internal and external oscillator, so long as the selected oscillator is enabled and settled. the internal oscillator requires little start-up time, and may be enabled and selected as the system clock in the same write to oscicn. external crystals and ceramic resonators typically require a start-up time before they are settled and ready for use as the systemclock. the crystal valid flag (xtlvld in register oscxcn) is set to 1 by hardware when the external oscillator is settled. to avoid reading a false xtlvld, in crystal mode software should delay at least 1 ms between enabling the external oscillator and checking xtlvld. rc and c modes typically require no startup time. table 11.1. internal oscillator electrical characteristics -40c to +85c unless otherwise specified parameter conditions min typ max units calibrated internal oscillator frequency c8051f300/1 devices 24 24.5 25 mhz uncalibrated internal oscillator frequency C8051F302/3 devices 15 20 25 mhz internal oscillator supply current (fromvdd) oscicn.2 = 1 tbd a
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 83 preliminary c8051f300/1/2/3 figure 11.4. oscxcn: external oscillator control register bit7: xtlvld: crystal oscillator valid flag (read only when xoscmd = 11x.) 0: crystal oscillator is unused or not yet stable. 1: crystal oscillator is running and stable. bits6-4: xoscmd2-0: external oscillator mode bits 00x: external oscillator circuit off. 010: external cmos clock mode. 011: external cmos clock mode with divide by 2 stage. 100: rc oscillator mode with divide by 2 stage. 101: capacitor oscillator mode with divide by 2 stage. 110: crystal oscillator mode. 111: crystal oscillator mode with divide by 2 stage. bit3: reserved. read = 0, write = don't care bits2-0: xfcn2-0: external oscillator frequency control bits 000-111: see table below: crystal mode (circuit fromfigure 11.1, option 1; xoscmd = 11x) choose xfcn value to match crystal frequency. rc mode (circuit fromfigure 11.1, option 2; xoscmd = 10x) choose xfcn value to match frequency range: f=1.23(10 3 )/(r*c) ,where f = frequency of oscillation in mhz c = capacitor value in pf r = pull-up resistor value in k ? cmode (circuit fromfigure 11.1, option 3; xoscmd = 10x) choose k factor (kf) for the oscillation frequency desired: f = kf / (c * vdd) ,where f = frequency of oscillation in mhz c = capacitor value the xtal2 pin in pf vdd = power supply on mcu in volts r r/w r/w r/w r r/w r/w r/w reset value xtlvld xoscmd2 xoscmd1 xoscmd0 - xfcn2 xfcn1 xfcn0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb1 xfcn crystal (xoscmd = 11x) rc (xoscmd = 10x) c (xoscmd = 10x) 000 f 32khz f 25khz k factor = 0.87 001 32khz < f 84khz 25khz < f 50khz k factor = 2.6 010 84khz < f 225khz 50khz < f 100khz k factor = 7.7 011 225khz < f 590khz 100khz < f 200khz k factor = 22 100 590khz < f 1.5mhz 200khz < f 400khz k factor = 65 101 1.5mhz < f 4mhz 400khz < f 800khz k factor = 180 110 4mhz < f 10mhz 800khz < f 1.6mhz k factor = 664 111 10mhz < f 30mhz 1.6mhz < f 3.2mhz k factor = 1590
page 84 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 11.4. external crystal example if a crystal or ceramic resonator is used as an external oscillator source for the mcu, the circuit should be configured as shown in figure 11.1, option 1. the external oscillator frequency control value (xfcn) should be chosen from the crystal columof the table in figure 11.4 (oscxcn register). for example, an 11.0592 mhz crystal requires an xfcn setting of 111b. when the crystal oscillator is enabled, a transient pulse may appear on the crystal driver output (xtal2) that is suffi- cient to cause the xtlvld bit in oscxcn to temporarily set to logic 1 before the crystal oscillator has actually started. introducing a blanking interval of 1 ms between enabling the oscillator and checking the xtlvld bit will prevent a premature switch to the external oscillator as the system clock. switching to the external oscillator before the crystal oscillator has stabilized can result in unpredictable behavior. the recommended procedure is: step 1. enable the external oscillator. step 2. wait 1 ms. step 3. poll for xtlvld => 1. step 4. switch the systemclock to the external oscillator. important note on external crystals: crystal oscillator circuits are quite sensitive to pcb layout. the crystal should be placed as close as possible to the xtal pins on the device. the traces should be as short as possible and shielded with ground plane fromany other traces which could introduce noise or interference. 11.5. external rc example if an rc network is used as an external oscillator source for the mcu, the circuit should be configured as shown in figure 11.1, option 2. the capacitor should be no greater than 100 pf; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the pcb layout. to determine the required external oscil- lator frequency control value (xfcn) in the oscxcn register, first select the rc network value to produce the desired frequency of oscillation. if the frequency desired is 100 khz, let r = 246 k ? andc=50pf: f=1.23(10 3 )/rc=1.23(10 3 ) / [ 246 * 50 ] = 0.1 mhz = 100 khz referring to the table in figure 11.4, the required xfcn setting is 010b. 11.6. external capacitor example if a capacitor is used as an external oscillator for the mcu, the circuit should be configured as shown in figure 11.1, option 3. the capacitor should be no greater than 100 pf; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the pcb layout. to determine the required external oscillator fre- quency control value (xfcn) in the oscxcn register, select the capacitor to be used and find the frequency of oscillation fromthe equations below. assume vdd = 3.0 v and c = 50 pf: f = kf / ( c * vdd ) = kf / ( 50 * 3 ) mhz f = kf / 150 mhz if a frequency of roughly 150 khz is desired, select the k factor fromthe table in figure 11.4 as kf = 22: f = 22 / 150 = 0.146 mhz, or 146 khz therefore, the xfcn value to use in this example is 011b.
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 85 preliminary c8051f300/1/2/3 12. port input/output digital and analog resources are available through a byte-wide digital i/o port, port0. each of the port pins can be defined as general-purpose i/o (gpio), analog input, or assigned to one of the internal digital resources as shown in figure 12.3. the designer has complete control over which functions are assigned, limited only by the number of physical i/o pins. this resource assignment flexibility is achieved through the use of a priority crossbar decoder. note that the state of a port i/o pin can always be read in the corresponding port latch, regardless of the crossbar set- tings. the crossbar assigns the selected internal digital resources to the i/o pins based on the priority decoder (figure 12.3 and figure 12.4). the registers xbr0, xbr1, and xbr2, defined in figure 12.5, figure 12.6, and figure 12.7 are used to select internal digital functions. all port i/os are 5 v tolerant (refer to figure 12.2 for the port cell circuit). the port i/o cells are configured as either push-pull or open-drain in the port0 output mode register (p0mdout). complete electrical specifications for port i/o are given in table 12.1 on page 92. figure 12.1. port i/o functional block diagram xbr0, xbr1, xbr2 registers digital crossbar priority decoder sysclk 2 2 (internal digital signals) highest priority lowest priority p0 i/o cells p0.0 p0.7 8 p0mdout, p0mdin registers smbus uart t0, t1 2 4 pca cp0 outputs 2 p0 port latch (p0.0-p0.7) 8 figure 12.2. port i/o cell block diagram gnd /port-outenable port-output push-pull vdd vdd /weak-pullup (weak) port pad analog input analog select port-input
page 86 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 12.1. priority crossbar decoder the priority crossbar decoder (figure 12.3) assigns a priority to each i/o function, starting at the top with uart0. when a digital resource is selected, the least-significant unassigned port pin is assigned to that resource (excluding uart0, which is always at pins 4 and 5). if a port pin is assigned, the crossbar skips that pin when assigning the next selected resource. additionally, the crossbar will skip port pins whose associated bits in the xbr0 register are set. the xbr0 register allows software to skip port pins that are to be used for analog input or gpio. important note on crossbar configuration: if a port pin is claimed by a peripheral without use of the crossbar, its corresponding xbr0 bit should be set. this applies to p0.0 if vref is enabled, p0.3 and/or p0.2 if the external oscil- lator circuit is enabled, p0.6 if the adc is configured to use the external conversion start signal (cnvstr), and any selected adc or comparator inputs. the crossbar skips selected pins as if they were already assigned, and moves to the next unassigned pin. figure 12.3 shows the crossbar decoder priority with no port pins skipped (xbr0 = 0x00); figure 12.4 shows the crossbar decoder priority with pins 6 and 2 skipped (xbr0 = 0x44). figure 12.3. crossbar priority decoder with xbar0 = 0x00 v ref x1 x2 cnvstr 01234567 00000000 special function signals are not assigned by the crossbar. when these signals are enabled, the crossbar must be manually configured to skip their corresponding port pins. port pin potentially available to peripheral sf signals eci t0 t1 xbr0[0:7] signals unavailable sf signal s pin i/o tx0 rx0 sda scl p0 sysclk cex2 cp0 cp0a cex0 cex1
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 87 preliminary c8051f300/1/2/3 registers xbr1 and xbr2 are used to assign the digital i/o resources to the physical i/o port pins. note that when the smbus is selected, the crossbar assigns both pins associated with the smbus (sda and scl). either or both of the uart signals may be selected by the crossbar. uart0 pin assignments are fixed for bootloading purposes: when uart tx0 is selected, it is always assigned to p0.4; when uart rx0 is selected, it is always assigned to p0.5. standard port i/os appear contiguously after the prioritized functions have been assigned. for example, if assigned functions that take the first 3 port i/o (p0.[2:0]), 5 port i/o are left for analog or gpio use. figure 12.4. crossbar priority decoder with xbr0 = 0x44 v ref x1 x2 cnvstr 01234567 00100010 port pin potentially available to peripheral port pin skipped by crossbar special function signals are not assigned by the crossbar. when these signals are enabled, the crossbar must be manually configured to skip their corresponding port pins. sf signals rx0 sda scl sysclk cex2 eci p0 xbr0[0:7] t0 t1 sf signals pin i/o tx0 signals unavailable cex0 cex1 cp0 cp0a
page 88 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 12.2. port i/o initialization port i/o initialization consists of the following steps: step 1. select the input mode (analog or digital) for all port pins, using the port0 input mode register (p0mdin). step 2. select the output mode (open-drain or push-pull) for all port pins, using the port0 output mode register (p0mdout). step 3. set xbr0 to skip any pins selected as analog inputs or special functions. step 4. assign port pins to desired peripherals. all port pins must be configured as either analog or digital inputs. any pins to be used as comparator or adc inputs should be configured as an analog inputs. when a pin is configured as an analog input, its weak pull-up, digital driver, and digital receiver is disabled. this process saves power and reduces noise on the analog input. pins configured as digital inputs may still be used by analog peripherals; however this practice is not recommended. additionally, all analog input pins should be configured to be skipped by the crossbar (accomplished by setting the associated bits in xbr0). port input mode is set in the p0mdin register, where a 1 indicates a digital input, and a 0 indicates an analog input. all pins default to digital inputs on reset. see figure 12.9 for the p0mdin register details. the output driver characteristics of the i/o pins are defined using the port0 output mode register p0mdout (see figure 12.10). each port output driver can be configured as either open drain or push-pull. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. the only exception to this is the smbus (sda, scl) pins, which are configured as open-drain regardless of the p0mdout settings. when the weakpud bit in xbr2 is 0, a weak pull-up is enabled for all port i/o configured as open-drain. weakpud does not affect the push-pull port i/o. furthermore, the weak pull-up is turned off on an open-drain output that is driving a 0 to avoid unnecessary power dissipation. registers xbr0, xbr1 and xbr2 must be loaded with the appropriate values to select the digital i/o functions required by the design. setting the xbare bit in xbr2 to 1 enables the crossbar. until the crossbar is enabled, the external pins remain as standard port i/o regardless of the xbrn register settings. for given xbrn register settings, one can determine the i/o pin-out using the priority decode table; as an alternative, the configuration wizard utility of the cygnal ide software will determine the port i/o pin-assignments based on the xbrn register settings.
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 89 preliminary c8051f300/1/2/3 figure 12.5. xbr0: port i/o crossbar register 0 bit7: unused. read = 0b; write = dont care. bits6-0: xskp[6:0]: crossbar skip enable bits these bits select port pins to be skipped by the crossbar decoder. port pins used as analog inputs (for adc or comparator) or used as special functions (vref input, external oscillator circuit, cnvstr input) should be skipped by the crossbar. 0: corresponding p0.n pin is not skipped by the crossbar. 1: corresponding p0.n pin is skipped by the crossbar. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue - xskp6 xskp5 xskp4 xskp3 xskp2 xskp1 xskp0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe1 figure 12.6. xbr1: port i/o crossbar register 1 bits7-6: pca0me: pca module i/0 enable bits 00: all pca i/o unavailable at port pins. 01: cex0 routed to port pin. 10: cex0, cex1 routed to port pins. 11: cex0, cex1, cex2 routed to port pins. bit5: cp0aoen: comparator0 asynchronous output enable 0: asynchronous cp0 unavailable at port pin. 1: asynchronous cp0 routed to port pin. bit4: cp0oen: comparator0 output enable 0: cp0 unavailable at port pin. 1: cp0 routed to port pin. bit3: syscke: /sysclk output enable 0: /sysclk unavailable at port pin. 1: /sysclk output routed to port pin. bit2: smb0oen: smbus i/o enable 0: smbus i/o unavailable at port pins. 1: sda, scl routed to port pins. bit1: urx0en: uart rx enable 0: uart rx0 unavailable at port pin. 1: uart rx0 routed to port pin p0.5. bit0: utx0en: uart tx output enable 0: uart tx0 unavailable at port pin. 1:uarttx0routedtoportpinp0.4. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue pca0me cp0aoen cp0oen syscke smb0oen urx0en utx0en 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe2
page 90 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 figure 12.7. xbr2: port i/o crossbar register 2 bit7: weakpud: port i/o weak pull-up disable 0: weak pull-ups enabled (except for ports whose i/o are configured as push-pull). 1: weak pull-ups disabled. bit6: xbare: crossbar enable 0: crossbar disabled. 1: crossbar enabled. bits5-3: unused: read=000b. write = dont care. bit2: t1e: t1 enable 0: t1 unavailable at port pin. 1: t1 routed to port pin. bit1: t0e: t0 enable 0: t0 unavailable at port pin. 1: t0 routed to port pin. bit0: ecie: pca0 counter input enable 0: eci unavailable at port pin. 1: eci routed to port pin. r/w r/w r/w r/w r/w r/w r/w r/w reset value weakpud xbare - - - t1e t0e ecie 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe3
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 91 preliminary c8051f300/1/2/3 12.3. general purpose port i/o port pins that remain unassigned by the crossbar and are not used by analog peripherals can be used for general pur- pose i/o. port0 is accessed through a corresponding special function register (sfr) that is both byte addressable and bit addressable. when writing to a port, the value written to the sfr is latched to maintain the output data value at each pin. when reading, the logic levels of the port's input pins are returned regardless of the xbrn settings (i.e., even when the pin is assigned to another signal by the crossbar, the port register can always read its corresponding port i/o pin). the exception to this is the execution of the read-modify-write instructions. the read-modify-write instructionswhenoperatingonaportsfrarethefollowing:anl,orl,xrl,jbc,cpl,inc,dec,djnzand mov, clr or set, when the destination is an individual bit in a port sfr. for these instructions, the value of the register (not the pin) is read, modified, and written back to the sfr. figure 12.8. p0: port0 register bits7-0: p0.[7:0] write - output appears on i/o pins per xbr0, xbr1, and xbr2 registers 0: logic low output. 1: logic high output (open-drain if corresponding p0mdout.n bit = 0) read - always reads 1 if selected as analog input in register p0mdin. directly reads port latch when configured as digital input. 0: p0.n pin is logic low. 1: p0.n pin is logic high. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0x80 figure 12.9. p0mdin: port0 input mode register bits7-0: input configuration bits for p0.7-p0.0 (respectively) port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver dis- abled. 0: corresponding p0.n pin is configured as an analog input. 1: corresponding p0.n pin is configured as a digital input. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf1
page 92 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 table 12.1. port i/o dc electrical characteristics vdd = 2.7 to 3.6v, -40c to +85c unless otherwise specified parameters conditions min typ max units output high voltage i oh = -3ma, port i/o push-pull i oh = -10a, port i/o push-pull i oh = -10ma, port i/o push-pull vdd-0.7 vdd-0.1 vdd-0.8 v output low voltage i ol =8.5ma i ol = 10a i ol =25ma 1.0 0.6 0.1 v input high voltage 2.0 v input low voltage 0.8 v input leakage current weak pull-up off weak pull-up on, v in =0v 25 1 40 a figure 12.10. p0mdout: port0 output mode register bits7-0: output configuration bits for p0.7-p0.0 (respectively): ignored if corresponding bit in register p0mdin is logic 0. 0: corresponding p0.n output is open-drain. 1: corresponding p0.n output is push-pull. (note: when sda and scl appear on any of the port i/o, each are open-drain regardless of the value of p0mdout). r/wr/wr/wr/wr/wr/wr/wr/wresetvalue 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa4
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 93 preliminary c8051f300/1/2/3 13. smbus the smbus i/o interface is a two-wire, bi-directional serial bus. the smbus is compliant with the system manage- ment bus specification, version 1.1, and compatible with the i 2 c serial bus. reads and writes to the interface by the systemcontroller are byte oriented with the smbus interface autonomously controlling the serial transfer of the data. data can be transferred at up to 1/8th of the systemclock if desired (this can be faster than allowed by the smbus specification, depending on the systemclock used). a method of extending the clock-low duration is available to accommodate devices with different speed capabilities on the same bus. the smbus interface may operate as a master and/or slave, and may function on a bus with multiple masters. the smbus provides control of sda (serial data), scl (serial clock) generation and synchronization, arbitration logic, and start/stop control and generation. three sfrs are associated with the smbus: smb0cf configures the smbus; smb0cn controls the status of the smbus; and smb0dat is the data register, used for both transmitting and receiving smbus data and slave addresses. figure 13.1. smbus block diagram data path control smbus control logic c r o s s b a r scl filter n sda control scl control arbitration scl synchronization irq generation scl generation (master mode) sda control interrupt request port i/o smb0cn s t a a c k r q a r b l o s t a c k s i t x m o d e m a s t e r s t o 01 00 10 11 t0 overflow t1overflow tmr2h overflow tmr2l overflow smb0cf e n s m b i n h b u s y e x t h o l d s m b t o e s m b f t e s m b c s 1 s m b c s 0 0 1 2 3 4 5 6 7 smb0dat sda filter n
page 94 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 13.1. supporting documents it is assumed the reader is familiar with or has access to the following supporting documents: 1. the i 2 c-bus and how to use it (including specifications), philips semiconductor. 2. the i 2 c-bus specification -- version 2.0, philips semiconductor. 3. system management bus specification -- version 1.1, sbs implementers forum. 13.2. smbus configuration figure 13.2 shows a typical smbus configuration. the smbus specification allows any recessive voltage between 3.0 v and 5.0 v; different devices on the bus may operate at different voltage levels. the bi-directional scl (serial clock) and sda (serial data) lines must be connected to a positive power supply voltage through a pull-up resistor or similar circuit. every device connected to the bus must have an open-drain or open-collector output for both the scl and sda lines, so that both are pulled high (recessive state) when the bus is free. the maximum number of devices on the bus is limited only by the requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively. figure 13.2. typical smbus configuration vdd = 5v master device slave device 1 slave device 2 vdd = 3v vdd = 5v vdd = 3v sda scl
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 95 preliminary c8051f300/1/2/3 13.3. smbus operation two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (write), and data transfers from an addressed slave transmitter to a master receiver (read). the master device ini- tiates both types of data transfers and provides the serial clock pulses on scl. the smbus interface may operate as a master or a slave, and multiple master devices on the same bus are supported. if two or more masters attempt to ini- tiate a data transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbi- tration. note that it is not necessary to specify one device as the master in a system; any device who transmits a start and a slave address becomes the master for the duration of that transfer. a typical smbus transaction consists of a start condition followed by an address byte (bits7-1: 7-bit slave address; bit0: r/w direction bit), one or more bytes of data, and a stop condition. each byte that is received (by a master or slave) must be acknowledged (ack) with a low sda during a high scl (see figure 13.3). if the receiving device does not ack, the transmitting device will read a nack (not acknowledge), which is a high sda during a high scl. the direction bit (r/w) occupies the least-significant bit position of the address byte. the direction bit is set to logic 1 to indicate a "read" operation and cleared to logic 0 to indicate a "write" operation. all transactions are initiated by a master, with one or more addressed slave devices as the target. the master gener- ates the start condition and then transmits the slave address and direction bit. if the transaction is a write opera- tion from the master to the slave, the master transmits the data a byte at a time waiting for an ack from the slave at the end of each byte. for read operations, the slave transmits the data waiting for an ack from the master at the end of each byte. at the end of the data transfer, the master generates a stop condition to terminate the transaction and free the bus. figure 13.3 illustrates a typical smbus transaction. 13.3.1. arbitration a master may start a transfer only if the bus is free. the bus is free after a stop condition or after the scl and sda lines remain high for a specified time (see section 13.3.4. scl high (smbus free) timeout on page 96 ). in the event that two or more devices attempt to begin a transfer at the same time, an arbitration scheme is employed to force one master to give up the bus. the master devices continue transmitting until one attempts a high while the other transmits a low. since the bus is open-drain, the bus will be pulled low. the master attempting the high will detect a low sda and lose the arbitration. the winning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. this arbitration scheme is non- destructive: one device always wins, and no data is lost. figure 13.3. smbus transaction sla6 sda sla5-0 r/w d7 d6-0 scl slave address + r/w data byte start ack nack stop
page 96 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 13.3.2. clock low extension smbus provides a clock synchronization mechanism, similar to i 2 c, which allows devices with different speed capa- bilities to coexist on the bus. a clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. the slave may temporarily hold the scl line low to extend the clock low period, effectively decreasing the serial clock frequency. 13.3.3. scl low timeout if the scl line is held low by a slave device on the bus, no further communication is possible. furthermore, the mas- ter cannot force the scl line high to correct the error condition. to solve this problem, the smbus protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than 25 ms as a timeout condi- tion. devices that have detected the timeout condition must reset the communication no later than 10 ms after detect- ing the timeout condition. when the smbtoe bit in smb0cf is set, timer 2 is used to detect scl low timeouts. timer 2 is forced to reload when scl is high, and allowed to count when scl is low. with timer 2 enabled and configured to overflow after 25 ms (and smbtoe set), the timer 2 interrupt service routine can be used to reset (disable and re-enable) the smbus in the event of an scl low timeout. timer 2 configuration details can be found in section 15.2. timer 2 on page 129 . 13.3.4. scl high (smbus free) timeout the smbus specification stipulates that if the scl and sda lines remain high for more that 50 s, the bus is desig- nated as free. when the smbfte bit in smb0cf is set, the bus will be considered free if scl and sda remain high for more than 10 smbus clock source periods. if the smbus is waiting to generate a master start, the start will be generated following this timeout. note that a clock source is required for free timeout detection, even in a slave- only implementation.
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 97 preliminary c8051f300/1/2/3 13.4. using the smbus the smbus can operate in both master and slave modes. the interface provides timing and shifting control for serial transfers; higher level protocol is determined by user software. the smbus interface provides the following applica- tion-independent features: ? byte-wise serial data transfers ? clock signal generation on scl (master mode only) and sda data synchronization ? timeout/bus error recognition, as defined by the smb0cf configuration register ? start/stop timing, detection, and generation ? bus arbitration ? interrupt generation ? status information smbus interrupts are generated for each data byte or slave address that is transferred. when transmitting, this inter- rupt is generated after the ack cycle so that software may read the received ack value; when receiving data, this interrupt is generated before the ack cycle so that software may define the outgoing ack value. see section 13.5. smbus transfer modes on page 105 for more details on transmission sequences. interrupts are also generated to indicate the beginning of a transfer when a master (start generated), or the end of a transfer when a slave (stop detected). software should read the smb0cn (smbus control register) to find the cause of the smbus interrupt. the smb0cn register is described in section 13.4.2. smb0cn control register on page 101 ; table 13.4 provides a quick smb0cn decoding reference. smbus configuration options include: ? timeout detection (scl low timeout and/or bus free timeout) ? sda setup and hold time extensions ? slave event enable/disable ? clock source selection these options are selected in the smb0cf register, as described in section 13.4.1. smbus configuration regis- ter on page 98 .
page 98 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 13.4.1. smbus configuration register the smbus configuration register (smb0cf) is used to enable the smbus master and/or slave modes, select the smbus clock source, and select the smbus timing and timeout options. when the ensmb bit is set, the smbus is enabled for all master and slave events. slave events may be disabled by setting the inh bit. with slave events inhib- ited, the smbus interface will still monitor the scl and sda pins; however, the interface will nack all received addresses and will not generate any slave interrupts. when the inh bit is set, all slave events will be inhibited follow- ing the next start (interrupts will continue for the duration of the current transfer). the smbcs1-0 bits select the smbus clock source, which is used only when operating as a master or when the free timeout detection is enabled. when operating as a master, overflows from the selected source determine the absolute minimum scl low and high times as defined in equation 13.1. note that the selected clock source may be shared by other peripherals so long as the timer is left running at all times. for example, timer 1 overflows may generate the smbus and uart baud rates simultaneously. timer configuration is covered in section 15. timers on page 121 . the selected clock source should be configured to establish the minimum scl high and low times as per equation 13.1. when the interface is operating as a master (and scl is not driven or extended by any other devices on the bus), the typical smbus bit rate is approximated by equation 13.2. figure 13.4 shows the typical scl generation described by equation 13.2. notice that t high is typically twice as large as t low . the actual scl output may vary due to other devices on the bus (scl may be extended low by slower slave devices, or driven low by contending master devices). the bit rate when operating as a master will never exceed the limits defined by equation equation 13.1. table 13.1. smbus clock source selection smbcs1 smbcs0 smbus clock source 0 0 timer 0 overflow 0 1 timer 1 overflow 1 0 timer 2 high byte overflow 1 1 timer 2 low byte overflow equation 13.1. minimum scl high and low times t highmin t lowmin 1 f clocksourceoverflow --------------------------------------------- - == equation 13.2. typical smbus bit rate bitrate f clocksourceoverflow 3 --------------------------------------------- - = scl timer source overflows sclhightimeout t low t high figure 13.4. typical smbus scl generation
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 99 preliminary c8051f300/1/2/3 setting the exthold bit extends the minimum setup and hold times for the sda line. the minimum sda setup time defines the absolute minimum time that sda is stable before scl transitions from low-to-high. the minimum sda hold time defines the absolute minimum time that the current sda value remains stable after scl transitions fromhigh-to-low. exthold should be set so that the minimumsetup and hold times meet the smbus specification requirements of 250 ns and 300 ns, respectively. table 13.2 shows the minimum setup and hold times for the two exthold settings. setup and hold time extensions are typically necessary when sysclk is above 10 mhz. with the smbtoe bit set, timer 2 should be configured to overflow after 25 ms in order to detect scl low timeouts (see section 13.3.3. scl low timeout on page 96 ). the smbus interface will force timer 2 to reload while scl is high, and allow timer 2 to count when scl is low. the timer 2 interrupt service routine should be used to reset smbus communication by disabling and re-enabling the smbus. timer 2 configuration is described in section 15.2. timer 2 on page 129 . smbus free timeout detection can be enabled by setting the smbfte bit. when this bit is set, the bus will be con- sidered free if sda and scl remain high for more than 10 smbus clock source periods (see figure 13.4). when a free timeout is detected, the interface will respond as if a stop was detected (an interrupt will be generated, and sto will be set). table 13.2. minimum sda setup and hold times exthold minimum sda setup time minimum sda hold time 0 t low - 4 systemclocks or 1 systemclock + s/w delay ? 3 systemclocks 1 11 systemclocks 12 systemclocks ? setup time for ack bit transmissions and the msb of all data transfers. the s/w delay occurs between the time smb0dat or ack is written and when si is cleared. note that if si is cleared in the same write that defines the outgoing ack value, s/w delay is zero.
page 100 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 figure 13.5. smb0cf: smbus clock/configuration register bit7: ensmb: smbus enable this bit enables/disables the smbus interface. when enabled, the interface constantly monitors the sda and scl pins. 0: smbus interface disabled. 1: smbus interface enabled. bit6: inh: smbus slave inhibit when this bit is set to logic 1, the smbus does not generate an interrupt when slave events occur. this effectively removes the smbus slave from the bus. master mode interrupts are not affected. 0: smbus slave mode enabled. 1: smbus slave mode inhibited. bit5: busy: smbus busy indicator this bit is set to logic 1 by hardware when a transfer is in progress. it is cleared to logic 0 when a stop or free-timeout is sensed. bit4: exthold: smbus setup and hold time extension enable this bit controls the sda setup and hold times according to table 13.2. 0: sda extended setup and hold times disabled. 1: sda extended setup and hold times enabled. bit3: smbtoe: smbus scl timeout detection enable this bit enables scl low timeout detection. if set to logic 1, the smbus forces timer 2 to reload while scl is high and allows timer 2 to count when scl goes low. timer 2 should be programmed to generate interrupts at 25 ms, and the timer 2 interrupt service routine should reset smbus commu- nication. bit2: smbfte: smbus free timeout detection enable when this bit is set to logic 1, the bus will be considered free if scl and sda remain high for more than 10 smbus clock source periods. bits1-0: smbcs1-smbcs0: smbus clock source selection these two bits select the smbus clock source, which is used to generate the smbus bit rate. the selected device should be configured according to equation 13.1. r/wr/w r r/wr/wr/wr/wr/wresetvalue ensmb inh busy exthold smbtoe smbfte smbcs1 smbcs0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc1 smbcs1 smbcs0 smbus clock source 00 timer0overflow 01 timer1overflow 1 0 timer 2 high byte overflow 1 1 timer 2 low byte overflow
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 101 preliminary c8051f300/1/2/3 13.4.2. smb0cn control register smb0cn is used to control the interface and to provide status information (see figure 13.6). the higher four bits of smb0cn (master, txmode, sta, and sto) forma status vector that can be used to jump to service routines. master and txmode indicate the master/slave state and transmit/receive modes, respectively. sta and sto indicate that a start and/or stop has been detected or generated since the last smbus interrupt. sta and sto are also used to generate start and stop conditions when operating as a master. writing a 1 to sta will cause the smbus interface to enter master mode and generate a start when the bus becomes free (sta is not cleared by hardware after the start is generated). writing a 1 to sto while in master mode will cause the interface to generate a stop and end the current transfer after the next ack cycle. if sto and sta are both set (while in master mode), a stop followed by a start will be generated. as a receiver, writing the ack bit defines the outgoing ack value; as a transmitter, reading the ack bit indicates the value received on the last ack cycle. ackrq is set each time a byte is received, indicating that an outgoing ack value is needed. when ackrq is set, software should write the desired outgoing value to the ack bit before clearing si. a nack will be generated if software does not write the ack bit before clearing si. sda will reflect the defined ack value immediately following a write to the ack bit; however scl will remain low until si is cleared. if a received slave address is not acknowledged, further slave events will be ignored until the next start is detected. the arblost bit indicates that the interface has lost an arbitration. this may occur anytime the interface is trans- mitting (master or slave). a lost arbitration while operating as a slave indicates a bus error condition. arblost is cleared by hardware each time si is cleared. the si bit (smbus interrupt flag) is set at the beginning and end of each transfer, after each byte frame, or when an arbitration is lost; see table 13.3 for more details. important note about the si bit: the smbus interface is stalled while si is set; thus scl is held low, and the bus is stalled until software clears si. table 13.3 lists all sources for hardware changes to the smb0cn bits. refer to table 13.4 for smbus status decoding using the smb0cn register.
page 102 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 figure 13.6. smb0cn: smbus control register bit7: master: smbus master/slave indicator this read-only bit indicates when the smbus is operating as a master. 0: smbus operating in slave mode. 1: smbus operating in master mode. bit6: txmode: smbus transmit mode indicator. this read-only bit indicates when the smbus is operating as a transmitter. 0: smbus in receiver mode. 1: smbus in transmitter mode. bit5: sta:smbusstartflag. write: 0: no start generated. 1: when operating as a master, a start condition is transmitted if the bus is free (if the bus is not free, the start is transmitted after a stop is received or a timeout is detected). if sta is set by soft- ware as an active master, a repeated start will be generated after the next ack cycle. read: 0: no start or repeated start detected. 1: start or repeated start detected. bit4: sto: smbus stop flag. write: 0: no stop condition is transmitted. 1: setting sto to logic 1 causes a stop condition to be transmitted after the next ack cycle. when the stop condition is generated, hardware clears sto to logic 0. if both sta and sto are set, a stop condition is transmitted followed by a start condition. read: 0: no stop condition detected. 1: stop condition detected (if in slave mode) or pending (if in master mode). bit3: ackrq: smbus acknowledge request this read-only bit is set to logic 1 when the smbus has received a byte and needs the ack bit to be written with the correct ack response value. bit2: arblost: smbus arbitration lost indicator this read-only bit is set to logic 1 when the smbus loses arbitration while operating as a transmitter. a lost arbitration while a slave indicates a bus error condition. bit1: ack: smbus acknowledge flag. this bit defines the out-going ack level and records incoming ack levels. it should be written each time a byte is received (when ackrq=1), or read after each byte is transmitted. 0: a "not acknowledge" has been received (if in transmitter mode) or will be transmitted (if in receiver mode). 1: an "acknowledge" has been received (if in transmitter mode) or will be transmitted (if in receiver mode). bit0: si: smbus interrupt flag this bit is set by hardware under the conditions listed in table 13.3. si must be cleared by software. while si is set, scl is held low and the smbus is stalled. r r r/wr/w r r r/wr/wresetvalue master txmode sta sto ackrq arblost ack si 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xc0
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 103 preliminary c8051f300/1/2/3 table 13.3. sources for hardware changes to smb0cn bit set by hardware when: cleared by hardware when: master ? a start is generated. ? a stop is generated. ? arbitration is lost. txmode ? start is generated. ? smb0dat is written before the start of an smbus frame. ? a start is detected. ? arbitration is lost. ? smb0dat is not written before the start of an smbus frame. sta ? a start followed by an address byte is received. ? must be cleared by software. sto ? a stop is detected while addressed as a slave. ? arbitration is lost due to a detected stop. ? a pending stop is generated. ackrq ? a byte has been received and an ack response value is needed. ? after each ack cycle. arblost ? a repeated start is detected as a master when sta is low (unwanted repeated start). ? scl is sensed low while attempting to generate a stop or repeated start condition. ? sda is sensed low while transmitting a 1 (excluding ack bits). ? each time si is cleared. ack ? the incoming ack value is low (acknowl- edge). ? the incoming ack value is high (not acknowledge). si ? a start has been generated. ? lost arbitration. ? a byte has been transmitted and an ack/nack received. ? a byte has been received. ? a start or repeated start followed by a slave address + r/w has been received. ? a stop has been received. ? must be cleared by software.
page 104 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 13.4.3. data register the smbus data register smb0dat holds a byte of serial data to be transmitted or one that has just been received. software may safely read or write to the data register when the si flag is set. software should not attempt to access the smb0dat register when the smbus is enabled and the si flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register. data in smb0dat is always shifted out msb first. after a byte has been received, the first bit of received data is located at the msb of smb0dat. while data is being shifted out, data on the bus is simultaneously being shifted in. smb0dat always contains the last data byte present on the bus. in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data or address in smb0dat. figure 13.7. smb0dat: smbus data register bits7-0: smb0dat: smbus data. the smb0dat register contains a byte of data to be transmitted on the smbus serial interface or a byte that has just been received on the smbus serial interface. the cpu can read fromor write to this register whenever the si serial interrupt flag (smb0cn.0) is set to logic one. the serial data in the register remains stable as long as the si flag is set. when the si flag is not set, the system may be in the process of shifting data in/out and the cpu should not attempt to access this register. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc2
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 105 preliminary c8051f300/1/2/3 13.5. smbus transfer modes the smbus interface may be configured to operate as master and/or slave. at any particular time, it will be operating in one of the following four modes: master transmitter, master receiver, slave transmitter, or slave receiver. the smbus interface enters master mode any time a start is generated, and remains in master mode until it loses an arbitration or generates a stop. an smbus interrupt is generated at the end of all smbus byte frames; however, note that the interrupt is generated before the ack cycle when operating as a receiver, and after the ack cycle when operating as a transmitter. 13.5.1. master transmitter mode serial data is transmitted on sda while the serial clock is output on scl. the smbus interface generates the start condition and transmits the first byte containing the address of the target slave and the data direction bit. in this case the data direction bit (r/w) will be logic 0 (write). the master then transmits one or more bytes of serial data. after each byte is transmitted, an acknowledge bit is generated by the slave. the transfer is ended when the sto bit is set and a stop is generated. note that the interface will switch to master receiver mode if smb0dat is not writ- ten following a master transmitter interrupt. figure 13.8 shows a typical master transmitter sequence. two transmit data bytes are shown, though any number of bytes may be transmitted. notice that the data byte transferred inter- rupts occur after the ack cycle in this mode. a a a s w p data byte data byte sla s = start p=stop a=ack w=write sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt figure 13.8. typical master transmitter sequence
page 106 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 13.5.2. master receiver mode serial data is received on sda while the serial clock is output on scl. the smbus interface generates the start condition and transmits the first byte containing the address of the target slave and the data direction bit. in this case the data direction bit (r/w) will be logic 1 (read). serial data is then received fromthe slave on sda while the smbus outputs the serial clock. the slave transmits one or more bytes of serial data. after each byte is received, ackrq is set to 1 and an interrupt is generated. software must write the ack bit (smb0cn.1) to define the out- going acknowledge value (note: writing a 1 to the ack bit generates an ack; writing a 0 generates a nack). software should write a 0 to the ack bit after the last byte is received, to transmit a nack. the interface exits master receiver mode after the sto bit is set and a stop is generated. note that the interface will switch to master transmitter mode if smb0dat is written while an active master receiver. figure 13.9 shows a typical master receiver sequence. two received data bytes are shown, though any number of bytes may be received. notice that the data byte transferred interrupts occur before the ack cycle in this mode. figure 13.9. typical master receiver sequence data byte data byte a n a s r p sla s = start p=stop a=ack n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 107 preliminary c8051f300/1/2/3 13.5.3. slave receiver mode serial data is received on sda and the clock is received on scl. when slave events are enabled (inh = 0), the inter- face enters slave receiver mode when a start followed by a slave address and direction bit (write in this case) is received. upon entering slave receiver mode, an interrupt is generated and the ackrq bit is set. software responds to the received slave address with an ack, or ignores the received slave address with a nack. if the received slave address is ignored, slave interrupts will be inhibited until the next start is detected. if the received slave address is acknowledged, zero or more data bytes are received. software must write the ack bit after each received byte to ack or nack the received byte. the interface exits slave receiver mode after receiving a stop. note that the interface will switch to slave transmitter mode if smb0dat is written while an active slave receiver. figure 13.10 shows a typical slave receiver sequence. two received data bytes are shown, though any number of bytes may be received. notice that the data byte transferred interrupts occur before the ack cycle in this mode. p r sla s data byte data byte a a a s=start p=stop a=ack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt figure 13.10. typical slave receiver sequence
page 108 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 13.5.4. slave transmitter mode serial data is transmitted on sda and the clock is received on scl. when slave events are enabled (inh = 0), the interface enters slave receiver mode (to receive the slave address) when a start followed by a slave address and direction bit (read in this case) is received. upon entering slave transmitter mode, an interrupt is generated and the ackrq bit is set. software responds to the received slave address with an ack, or ignores the received slave address with a nack. if the received slave address is ignored, slave interrupts will be inhibited until a start is detected. if the received slave address is acknowledged, data should be written to smb0dat to be transmitted. the interface enters slave transmitter mode, and transmits one or more bytes of data. after each byte is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ack, smb0dat should be written with the next data byte. if the acknowledge bit is a nack, smb0dat should not be written to before si is cleared (note: an error con- dition may be generated if smb0dat is written following a received nack while in slave transmitter mode). the interface exits slave transmitter mode after receiving a stop. note that the interface will switch to slave receiver mode if smb0dat is not written following a slave transmitter interrupt. figure 13.11 shows a typical slave trans- mitter sequence. two transmitted data bytes are shown, though any number of bytes may be transmitted. notice that the data byte transferred interrupts occur after the ack cycle in this mode. p w sla s data byte data byte a n a s = start p=stop n = nack w=write sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt figure 13.11. typical slave transmitter sequence
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 109 preliminary c8051f300/1/2/3 13.6. smbus status decoding the current smbus status can be easily decoded using the smb0cn register. in the table below, status vector refers to the four upper bits of smb0cn: master, txmode, sta, and sto. note that the shown response options are only the typical responses; application-specific procedures are allowed as long as they conformwith the smbus specification. highlighted responses are allowed but do not conformto the smbus specification. table 13.4. smbus status decoding mode values read current smbus state typical response options va lue s written status vector ackrq arblost ack sta sto ack master transmitter 1110 0 0 x a master start was generated. load slave address + r/w into smb0dat. 0 0 x 1100 0 0 0 a master data or address byte was transmitted; nack received. setstatorestarttransfer. 1 0 x abort transfer. 0 1 x 0 0 1 a master data or address byte was transmitted; ack received. load next data byte into smb0dat 0 0 x end transfer with stop 0 1 x end transfer with stop and start another transfer. 1 1 x send repeated start 1 0 x switch to master receiver mode (clear si without writ- ing new data to smb0dat). 0 0 x master receiver 1000 1 0 x a master data byte was received; ack requested. acknowledge received byte; read smb0dat. 0 0 1 send nack to indicate last byte, and send stop. 0 1 0 send nack to indicate last byte, and send stop followed by start. 1 1 0 send ack followed by repeated start. 1 0 1 send nack to indicate last byte, and send repeated start. 1 0 0 send ack and switch to mas- ter transmitter mode (write to smb0dat before clearing si). 0 0 1 send nack and switch to master transmitter mode (write to smb0dat before clearing si). 0 0 0
page 110 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 slave transmitter 0100 0 0 0 a slave byte was transmitted; nack received. no action required (expecting stop condition). 0 0 x 0 0 1 a slave byte was transmitted; ack received. load smb0dat with next data byte to transmit. 0 0 x 0 1 x a slave byte was transmitted; error detected. no action required (expecting master to end transfer). 0 0 x 0101 0 x x a stop was detected while an addressed slave transmitter. no action required (transfer complete). 0 0 x slave receiver 0010 1 0 x a slave address was received; ack requested. acknowledge received address. 0 0 1 do not acknowledge received address. 0 0 0 1 1 x lost arbitration as master; slave address received; ack requested. acknowledge received address. 0 0 1 do not acknowledge received address. 0 0 0 reschedule failed transfer; do not acknowledge received address 1 0 0 0010 0 1 x lost arbitration while attempting a repeated start. abort failed transfer. 0 0 x reschedule failed transfer. 1 0 x 0001 1 1 x lost arbitration while attempting a stop. no action required (transfer complete/aborted). 0 0 0 0 0 x a stop was detected while an addressed slave receiver. no action required (transfer complete). 0 0 x 0 1 x lost arbitration due to a detected stop. abort transfer. 0 0 x reschedule failed transfer. 1 0 x 0000 1 0 x a slave byte was received; ack requested. acknowledge received byte; read smb0dat. 0 0 1 do not acknowledge received byte. 0 0 0 1 1 x lost arbitration while transmitting a data byte as master. abort failed transfer. 0 0 0 reschedule failed transfer. 1 0 0 table 13.4. smbus status decoding mode values read current smbus state typical response options va lue s written status ve cto r ackrq arblost ack sta sto ack
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 111 preliminary c8051f300/1/2/3 14. uart0 uart0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 uart. enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in section 14.1. enhanced baud rate generation on page 112 ). received data buffering allows uart0 to start reception of a second incoming data byte before software has finished reading the previous data byte. uart0 has two associated sfrs: serial control register 0 (scon0) and serial data buffer 0 (sbuf0). the single sbuf0 location provides access to both transmit and receive registers. reading sbuf0 accesses the buffered receive register; writing sbuf0 accesses the transmit register. with uart0 interrupts enabled, an interrupt is generated each time a transmit is completed (ti0 is set in scon0), or a data byte has been received (ri0 is set in scon0). the uart0 interrupt flags are not cleared by hardware when the cpu vectors to the interrupt service routine. they must be cleared manually by software, allowing software to determine the cause of the uart0 interrupt (transmit complete or receive complete). figure 14.1. uart0 block diagram uart baud rate generator ri scon0 ri0 ti0 rb80 tb80 ren0 mce0 s0mode tx control tx clock send sbuf (tx shift) start data write to sbuf crossbar tx shift zero detector tx irq set q d clr stop bit tb8 sfr bus serial port interrupt ti port i/o rx control start rx clock load sbuf shift 0x1ff rb8 rx irq input shift register (9 bits) load sbuf0 read sbuf sfr bus crossbar rx sbuf (rx latch)
page 112 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 14.1. enhanced baud rate generation the uart0 baud rate is generated by timer 1 in 8-bit auto-reload mode. the tx clock is generated by tl1; the rx clock is generated by a copy of tl1 (shown as rx timer in figure 14.2), which is not user-accessible. both tx and rx timer overflows are divided by two to generate the tx and rx baud rates. the rx timer runs when timer 1 is enabled, and uses the same reload value (th1). however, an rx timer reload is forced when a start condition is detected on the rx pin. this allows a receive to begin any time a start is detected, independent of the tx timer state. timer 1 should be configured for mode 2, 8-bit auto-reload (see section 15.1.3. mode 2: 8-bit counter/timer with auto-reload on page 123 ). the timer 1 reload value should be set so that overflows will occur at two times the desired uart baud rate frequency. note that timer 1 may be clocked by one of five sources: sysclk, sysclk / 4, sysclk / 12, sysclk / 48, or the external oscillator clock / 8. for any given timer 1 clock source, the uart0 baud rate is determined by equation 14.1. where t1 clk is the frequency of the clock supplied to timer 1, and t1h is the high byte of timer 1 (reload value). timer 1 clock frequency is selected as described in section 15.2. timer 2 on page 129 . a quick reference for typ- ical baud rates and systemclock frequencies is given in tables 14.1 through 14.6. note that the internal oscillator may still generate the system clock when the external oscillator is driving timer 1 (see section 15.1. timer 0 and timer 1 on page 121 for more detials). figure 14.2. uart0 baud rate logic rx timer start detected overflow overflow th1 tl1 tx clock 2 rx clock 2 timer 1uart0 equation 14.1. uart0 baud rate uartbaudrate t 1 clk 256 t 1 h C () ------------------------------ - 1 2 -- - =
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 113 preliminary c8051f300/1/2/3 14.2. operational modes uart0 provides standard asynchronous, full duplex communication. the uart mode (8-bit or 9-bit) is selected by the s0mode bit (scon0.7). typical uart connection options are shown below. 14.2.1. 8-bit uart 8-bit uart mode uses a total of 10 bits per data byte: one start bit, eight data bits (lsb first), and one stop bit. data are transmitted lsb first from the tx pin and received at the rx pin. on receive, the eight data bits are stored in sbuf0 and the stop bit goes into rb80 (scon0.2). data transmission begins when software writes a data byte to the sbuf0 register. the ti0 transmit interrupt flag (scon0.1) is set at the end of the transmission (the beginning of the stop-bit time). data reception can begin any time after the ren0 receive enable bit (scon0.4) is set to logic 1. after the stop bit is received, the data byte will be loaded into the sbuf0 receive register if the following conditions are met: ri0 must be logic 0, and if mce0 is logic 1, the stop bit must be logic 1. in the event of a receive data overrun, the first received 8 bits are latched into the sbuf0 receive register and the following overrun data bits are lost. if these conditions are met, the eight bits of data is stored in sbuf0, the stop bit is stored in rb80 and the ri0 flag is set. if these conditions are not met, sbuf0 and rb80 will not be loaded and the ri0 flag will not be set. an interrupt will occur if enabled when either ti0 or ri0 is set. figure 14.3. uart interconnect diagram or rs-232 c8051fxxx rs-232 level xltr tx rx c8051fxxx rx tx mcu rx tx figure 14.4. 8-bit uart timing diagram d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space
page 114 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 14.2.2. 9-bit uart 9-bit uart mode uses a total of eleven bits per data byte: a start bit, 8 data bits (lsb first), a programmable ninth data bit, and a stop bit. the state of the ninth transmit data bit is determined by the value in tb80 (scon0.3), which is assigned by user software. it can be assigned the value of the parity flag (bit p in register psw) for error detection, or used in multiprocessor communications. on receive, the ninth data bit goes into rb80 (scon0.2) and the stop bit is ignored. data transmission begins when an instruction writes a data byte to the sbuf0 register. the ti0 transmit interrupt flag (scon0.1) is set at the end of the transmission (the beginning of the stop-bit time). data reception can begin any time after the ren0 receive enable bit (scon0.4) is set to 1. after the stop bit is received, the data byte will be loaded into the sbuf0 receive register if the following conditions are met: (1) ri0 must be logic 0, and (2) if mce0 is logic 1, the 9th bit must be logic 1 (when mce0 is logic 0, the state of the ninth data bit is unimportant). if these conditions are met, the eight bits of data are stored in sbuf0, the ninth bit is stored in rb80, and the ri0 flag is set to 1. if the above conditions are not met, sbuf0 and rb80 will not be loaded and the ri0 flag will not be set to 1. a uart0 interrupt will occur if enabled when either ti0 or ri0 is set to 1. figure 14.5. 9-bit uart timing diagram d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space d8
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 115 preliminary c8051f300/1/2/3 14.3. multiprocessor communications 9-bit uart mode supports multiprocessor communication between a master processor and one or more slave pro- cessors by special use of the ninth data bit. when a master processor wants to transmit to one or more slaves, it first sends an address byte to select the target(s). an address byte differs froma data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. setting the mce0 bit (scon.5) of a slave processor configures its uart such that when a stop bit is received, the uart will generate an interrupt only if the ninth bit is logic one (rb80 = 1) signifying an address byte has been received. in the uart interrupt handler, software will compare the received address with the slave's own assigned 8- bit address. if the addresses match, the slave will clear its mce0 bit to enable interrupts on the reception of the fol- lowing data byte(s). slaves that weren't addressed leave their mce0 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the data. once the entire message is received, the addressed slave resets its mce0 bit to ignore all transmissions until it receives the next address byte. multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. the master processor can be con- figured to receive all transmissions or a protocol can be implemented such that the master/slave role is temporarily reversed to enable half-duplex transmission between the original master and slave(s). figure 14.6. uart multi-processor mode interconnect diagram master device slave device tx rx rx tx slave device rx tx slave device rx tx +5v
page 116 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 figure 14.7. scon0: serial port 0 control register bit7: s0mode: serial port 0 operation mode. this bit selects the uart0 operation mode. 0: mode 0: 8-bit uart with variable baud rate 1: mode 1: 9-bit uart with variable baud rate bit6: unused. read = 1b. write = dont care. bit5: mce0: multiprocessor communication enable. the function of this bit is dependent on the serial port 0 operation mode. mode 0: checks for valid stop bit. 0: logic level of stop bit is ignored. 1: ri0 will only be activated if stop bit is logic level 1. mode 1: multiprocessor communications enable. 0: logic level of ninth bit is ignored. 1:ri0issetandaninterruptisgeneratedonlywhentheninthbitislogic1. bit4: ren0: receive enable. this bit enables/disables the uart receiver. 0: uart0 reception disabled. 1: uart0 reception enabled. bit3: tb80: ninth transmission bit. the logic level of this bit will be assigned to the ninth transmission bit in 9-bit uart mode. it is not used in 8-bit uart mode. set or cleared by software as required. bit2: rb80: ninth receive bit. rb80 is assigned the value of the stop bit in mode 0; it is assigned the value of the 9th data bit in mode 1. bit1: ti0: transmit interrupt flag. set by hardware when a byte of data has been transmitted by uart0 (after the 8th bit in 8-bit uart mode, or at the beginning of the stop bit in 9-bit uart mode). when the uart0 interrupt is enabled, setting this bit causes the cpu to vector to the uart0 interrupt service routine. this bit must be cleared manually by software bit0: ri0: receive interrupt flag. set to 1 by hardware when a byte of data has been received by uart0 (set at the stop bit sam- pling time). when the uart0 interrupt is enabled, setting this bit to 1 causes the cpu to vector to the uart0 interrupt service routine. this bit must be cleared manually by software. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue s0mode - mce0 ren0 tb80 rb80 ti0 ri0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0x98
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 117 preliminary c8051f300/1/2/3 figure 14.8. sbuf0: serial (uart0) port data buffer register bits7-0: sbuf0[7:0]: serial data buffer bits 7-0 (msb-lsb) this sfr accesses two registers; a transmit shift register and a receive latch register. when data is written to sbuf0, it goes to the transmit shift register and is held for serial transmission. writing a byte to sbuf0 is what initiates the transmission. a read of sbuf0 returns the contents of the receive latch. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x99
page 118 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 table 14.1. timer settings for standard baud rates using the internal oscillator frequency: 24.5 mhz target baud rate (bps) baud rate %error oscillator divide factor timer clock source sca1-sca0 (pre-scale select) ? t1m ? timer 1 reload va lu e (h ex) sysclk from internal osc. 230400 -0.32% 106 sysclk xx 1 0xcb 115200 -0.32% 212 sysclk xx 1 0x96 57600 0.15% 426 sysclk xx 1 0x2b 28800 -0.32% 848 sysclk / 4 01 0 0x96 14400 0.15% 1704 sysclk / 12 00 0 0xb9 9600 -0.32% 2544 sysclk / 12 00 0 0x96 2400 -0.32% 10176 sysclk / 48 10 0 0x96 1200 0.15% 20448 sysclk / 48 10 0 0x2b x=dontcare ? sca1-sca0 and t1m bit definitions can be found in section 15.1 . table 14.2. timer settings for standard baud rates using an external oscillator frequency: 25.0 mhz target baud rate (bps) baud rate %error oscillator divide factor timer clock source sca1-sca0 (pre-scale select) ? t1m ? timer 1 reload va lu e (h ex) sysclk from external osc. 230400 -0.47% 108 sysclk xx 1 0xca 115200 0.45% 218 sysclk xx 1 0x93 57600 -0.01% 434 sysclk xx 1 0x27 28800 0.45% 872 sysclk / 4 01 0 0x93 14400 -0.01% 1736 sysclk / 4 01 0 0x27 9600 0.15% 2608 extclk / 8 11 0 0x5d 2400 0.45% 10464 sysclk / 48 10 0 0x93 1200 -0.01% 20832 sysclk / 48 10 0 0x27 sysclk from internal osc. 57600 -0.47% 432 extclk / 8 11 0 0xe5 28800 -0.47% 864 extclk / 8 11 0 0xca 14400 0.45% 1744 extclk / 8 11 0 0x93 9600 0.15% 2608 extclk / 8 11 0 0x5d x=dontcare ? sca1-sca0 and t1m bit definitions can be found in section 15.1 .
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 119 preliminary c8051f300/1/2/3 table 14.3. timer settings for standard baud rates using an external oscillator frequency: 22.1184 mhz target baud rate (bps) baud rate %error oscillator divide factor timer clock source sca1-sca0 (pre-scale select) ? t1m ? timer 1 reload va lu e (h ex) sysclk from external osc. 230400 0.00% 96 sysclk xx 1 0xd0 115200 0.00% 192 sysclk xx 1 0xa0 57600 0.00% 384 sysclk xx 1 0x40 28800 0.00% 768 sysclk / 12 00 0 0xe0 14400 0.00% 1536 sysclk / 12 00 0 0xc0 9600 0.00% 2304 sysclk / 12 00 0 0xa0 2400 0.00% 9216 sysclk / 48 10 0 0xa0 1200 0.00% 18432 sysclk / 48 10 0 0x40 sysclk from internal osc. 230400 0.00% 96 extclk / 8 11 0 0xfa 115200 0.00% 192 extclk / 8 11 0 0xf4 57600 0.00% 384 extclk / 8 11 0 0xe8 28800 0.00% 768 extclk / 8 11 0 0xd0 14400 0.00% 1536 extclk / 8 11 0 0xa0 9600 0.00% 2304 extclk / 8 11 0 0x70 x=dontcare ? sca1-sca0 and t1m bit definitions can be found in section 15.1 . table 14.4. timer settings for standard baud rates using an external oscillator frequency: 18.432 mhz target baud rate (bps) baud rate %error oscillator divide factor timer clock source sca1-sca0 (pre-scale select) ? t1m ? timer 1 reload va lu e (h ex) sysclk from external osc. 230400 0.00% 80 sysclk xx 1 0xd8 115200 0.00% 160 sysclk xx 1 0xb0 57600 0.00% 320 sysclk xx 1 0x60 28800 0.00% 640 sysclk / 4 01 0 0xb0 14400 0.00% 1280 sysclk / 4 01 0 0x60 9600 0.00% 1920 sysclk / 12 00 0 0xb0 2400 0.00% 7680 sysclk / 48 10 0 0xb0 1200 0.00% 15360 sysclk / 48 10 0 0x60 sysclk from internal osc. 230400 0.00% 80 extclk / 8 11 0 0xfb 115200 0.00% 160 extclk / 8 11 0 0xf6 57600 0.00% 320 extclk / 8 11 0 0xec 28800 0.00% 640 extclk / 8 11 0 0xd8 14400 0.00% 1280 extclk / 8 11 0 0xb0 9600 0.00% 1920 extclk / 8 11 0 0x88 x=dontcare ? sca1-sca0 and t1m bit definitions can be found in section 15.1 .
page 120 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 table 14.5. timer settings for standard baud rates using an external oscillator frequency: 11.0592 mhz target baud rate (bps) baud rate %error oscillator divide factor timer clock source sca1-sca0 (pre-scale select) ? t1m ? timer 1 reload va lu e (h ex) sysclk from external osc. 230400 0.00% 48 sysclk xx 1 0xe8 115200 0.00% 96 sysclk xx 1 0xd0 57600 0.00% 192 sysclk xx 1 0xa0 28800 0.00% 384 sysclk xx 1 0x40 14400 0.00% 768 sysclk / 12 00 0 0xe0 9600 0.00% 1152 sysclk / 12 00 0 0xd0 2400 0.00% 4608 sysclk / 12 00 0 0x40 1200 0.00% 9216 sysclk / 48 10 0 0xa0 sysclk from internal osc. 230400 0.00% 48 extclk / 8 11 0 0xfd 115200 0.00% 96 extclk / 8 11 0 0xfa 57600 0.00% 192 extclk / 8 11 0 0xf4 28800 0.00% 384 extclk / 8 11 0 0xe8 14400 0.00% 768 extclk / 8 11 0 0xd0 9600 0.00% 1152 extclk / 8 11 0 0xb8 x=dontcare ? sca1-sca0 and t1m bit definitions can be found in section 15.1 . table 14.6. timer settings for standard baud rates using an external oscillator frequency: 3.6864 mhz target baud rate (bps) baud rate %error oscillator divide factor timer clock source sca1-sca0 (pre-scale select) ? t1m ? timer 1 reload va lu e (h ex) sysclk from external osc. 230400 0.00% 16 sysclk xx 1 0xf8 115200 0.00% 32 sysclk xx 1 0xf0 57600 0.00% 64 sysclk xx 1 0xe0 28800 0.00% 128 sysclk xx 1 0xc0 14400 0.00% 256 sysclk xx 1 0x80 9600 0.00% 384 sysclk xx 1 0x40 2400 0.00% 1536 sysclk / 12 00 0 0xc0 1200 0.00% 3072 sysclk / 12 00 0 0x80 sysclk from internal osc. 230400 0.00% 16 extclk / 8 11 0 0xff 115200 0.00% 32 extclk / 8 11 0 0xfe 57600 0.00% 64 extclk / 8 11 0 0xfc 28800 0.00% 128 extclk / 8 11 0 0xf8 14400 0.00% 256 extclk / 8 11 0 0xf0 9600 0.00% 384 extclk / 8 11 0 0xe8 x=dontcare ? sca1-sca0 and t1m bit definitions can be found in section 15.1 .
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 121 preliminary c8051f300/1/2/3 15. timers each mcu includes 3 counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and one is a 16-bit auto-reload timer for use with the adc, smbus, or for general purpose use. these timers can be used to measure time intervals, count external events and generate periodic interrupt requests. timer 0 and timer 1 are nearly identical and have four primary modes of operation. timer 2 offers 16-bit and split 8-bit timer functionality with auto-reload. timers 0 and 1 may be clocked by one of five sources, determined by the timer mode select bits (t1m-t0m) and the clock scale bits (sca1-sca0). the clock scale bits define a pre-scaled clock fromwhich timer 0 and/or timer 1 may be clocked (see figure 15.6 for pre-scaled clock selection). timer 0/1 may then be configured to use this pre-scaled clock signal or the system clock. timer 2 may be clocked by the systemclock, the systemclock divided by 12, or the external oscillator clock source divided by 8. timer 0 and timer 1 may also be operated as counters. when functioning as a counter, a counter/timer register is incremented on each high-to-low transition at the selected input pin. events with a frequency of up to one-fourth the systemclock's frequency can be counted. the input signal need not be periodic, but it should be held at a given level for at least two full systemclock cycles to ensure the level is properly sampled. 15.1. timer 0 and timer 1 each timer is implemented as 16-bit register accessed as two separate bytes: a low byte (tl0 or tl1) and a high byte (th0 or th1). the counter/timer control register (tcon) is used to enable timer 0 and timer 1 as well as indicate their status. timer 0 interrupts can be enabled by setting the et0 bit in the ie regitser ( section 8.3.5. interrupt register descriptions on page 61 ); timer 1 interrupts can be enabled by setting the et1 bit in the ie register ( sec- tion 8.3.5 ). both counter/timers operate in one of four primary modes selected by setting the mode select bits t1m1- t0m0 in the counter/timer mode register (tmod). each timer can be configured independently. each operating mode is described below. 15.1.1. mode 0: 13-bit counter/timer timer 0 and timer 1 operate as 13-bit counter/timers in mode 0. the following describes the configuration and oper- ation of timer 0. however, both timers operate identically, and timer 1 is configured in the same manner as described for timer 0. the th0 register holds the eight msbs of the 13-bit counter/timer. tl0 holds the five lsbs in bit positions tl0.4- tl0.0. the three upper bits of tl0 (tl0.7-tl0.5) are indeterminate and should be masked out or ignored when read- ing. as the 13-bit timer register increments and overflows from 0x1fff (all ones) to 0x0000, the timer overflow flag tf0 (tcon.5) is set and an interrupt will occur if timer 0 interrupts are enabled. the c/t0 bit (tmod.2) selects the counter/timer's clock source. when c/t0 is set to logic 1, high-to-low transitions at the selected timer 0 input pin (t0) increment the timer register (refer to section 12.1. priority crossbar decoder on page 86 for information on selecting and configuring external i/o pins). clearing c/t selects the clock defined by the t0m bit (ckcon.3). when t0m is set, timer 0 is clocked by the system clock. when t0m is cleared, timer 0 is clocked by the source selected by the clock scale bits in ckcon (see figure 15.6). timer 0 and timer 1 modes: timer 2 modes: 13-bit counter/timer 16-bit timer with auto-reload 16-bit counter/timer 8-bit counter/timer with auto-reload two 8-bit timers with auto-reload two 8-bit counter/timers (timer 0 only)
page 122 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 setting the tr0 bit (tcon.4) enables the timer when either gate0 (tmod.3) is logic 0 or the input signal /int0 is active as defined by bit in0pl in register int01cf (see figure 8.13). setting gate0 to 1 allows the timer to be controlled by the external input signal /int0 (see section 8.3.5. interrupt register descriptions on page 61 ), facilitating pulse width measurements. setting tr0 does not force the timer to reset. the timer registers should be loaded with the desired initial value before the timer is enabled. tl1 and th1 form the 13-bit register for timer 1 in the same manner as described above for tl0 and th0. timer 1 is configured and controlled using the relevant tcon and tmod bits just as with timer 0. the input signal /int1 is used with timer 1; the /int1 polarity is defined by bit in1pl in register int01cf (see figure 8.13). 15.1.2. mode 1: 16-bit counter/timer mode 1 operation is the same as mode 0, except that the counter/timer registers use all 16 bits. the counter/timers are enabled and configured in mode 1 in the same manner as for mode 0. tr0 gate0 /int0 counter/timer 0 x x disabled 1 0 x enabled 1 1 0 disabled 1 1 1 enabled x = don't care figure 15.1. t0 mode 0 block diagram tclk tl0 (5 bits) th0 (8 bits) tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tr0 0 1 0 1 sysclk pre-scaled clock ckcon t 2 m h s c a 0 s c a 1 t 2 m l t 1 m t 0 m tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 gate0 /int0 t0 crossbar int01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 in0pl xor
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 123 preliminary c8051f300/1/2/3 15.1.3. mode 2: 8-bit counter/timer with auto-reload mode 2 configures timer 0 and timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. tl0 holds the count and th0 holds the reload value. when the counter in tl0 overflows fromall ones to 0x00, the timer overflow flag tf0 (tcon.5) is set and the counter in tl0 is reloaded from th0. if timer 0 interrupts are enabled, an interrupt will occur when the tf0 flag is set. the reload value in th0 is not changed. tl0 must be initial- ized to the desired value before enabling the timer for the first count to be correct. when in mode 2, timer 1 operates identically to timer 0. both counter/timers are enabled and configured in mode 2 in the same manner as mode 0. setting the tr0 bit (tcon.4) enables the timer when either gate0 (tmod.3) is logic 0 or when the input signal /int0 is active as defined by bit in0pl in register int01cf (see section 8.3.2. external interrupts on page 59 for details on the external input signals /int0 and /int1) . figure 15.2. t0 mode 2 block diagram tclk tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tl0 (8 bits) reload th0 (8 bits) 0 1 0 1 sysclk pre-scaled clock ckcon t 2 m h s c a 0 s c a 1 t 2 m l t 1 m t 0 m int01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 tr0 gate0 in0pl xor /int0 t0 crossbar
page 124 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 15.1.4. mode 3: two 8-bit counter/timers (timer 0 only) in mode 3, timer 0 is configured as two separate 8-bit counter/timers held in tl0 and th0. the counter/timer in tl0 is controlled using the timer 0 control/status bits in tcon and tmod: tr0, c/t0, gate0 and tf0. tl0 can use either the system clock or an external input signal as its timebase. the th0 register is restricted to a timer function sourced by the systemclock or prescaled clock. th0 is enabled using the timer 1 run control bit tr1. th0 sets the timer 1 overflow flag tf1 on overflow and thus controls the timer 1 interrupt. timer 1 is inactive in mode 3. when timer 0 is operating in mode 3, timer 1 can be operated in modes 0, 1 or 2, but cannot be clocked by external signals nor set the tf1 flag and generate an interrupt. however, the timer 1 overflow can be used to generate baud rates for the smbus and/or uart, and/or initiate adc conversions. while timer 0 is operating in mode 3, timer 1 run control is handled through its mode settings. to run timer 1 while timer 0 is in mode 3, set the timer 1 mode as 0, 1, or 2. to disable timer 1, configure it for mode 3. figure 15.3. t0 mode 3 block diagram tl0 (8 bits) tmod 0 1 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt interrupt 0 1 sysclk pre-scaled clock tr1 th0 (8 bits) ckcon t 2 m h s c a 0 s c a 1 t 2 m l t 1 m t 0 m t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tr0 gate0 in0pl xor /int0 t0 crossbar
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 125 preliminary c8051f300/1/2/3 figure 15.4. tcon: timer control register bit7: tf1: timer 1 overflow flag. set by hardware when timer 1 overflows. this flag can be cleared by software but is automatically cleared when the cpu vectors to the timer 1 interrupt service routine. 0: no timer 1 overflow detected. 1: timer 1 has overflowed. bit6: tr1: timer 1 run control. 0: timer 1 disabled. 1: timer 1 enabled. bit5: tf0: timer 0 overflow flag. set by hardware when timer 0 overflows. this flag can be cleared by software but is automatically cleared when the cpu vectors to the timer 0 interrupt service routine. 0: no timer 0 overflow detected. 1: timer 0 has overflowed. bit4: tr0: timer 0 run control. 0: timer 0 disabled. 1: timer 0 enabled. bit3: ie1: external interrupt 1. this flag is set by hardware when an edge/level of type defined by it1 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external interrupt 1 service routine if it1 = 1. when it1 = 0, this flag is set to 1 when /int1 is active as defined by bit in1pl in register int01cf (see figure 8.13). bit2: it1: interrupt 1 type select. this bit selects whether the configured /int1 interrupt will be edge or level sensitive. /int1 is con- figured active low or high by the in1pl bit in the it01cf register (see figure 8.13). 0: /int1 is level triggered. 1: /int1 is edge triggered. bit1: ie0: external interrupt 0. this flag is set by hardware when an edge/level of type defined by it0 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external interrupt 0 service routine if it0 = 1. when it0 = 0, this flag is set to 1 when /int0 is active as defined by bit in0pl in register int01cf (see figure 8.13). bit0: it0: interrupt 0 type select. this bit selects whether the configured /int0 interrupt will be edge or level sensitive. /int0 is con- figured active low or high by the in0pl bit in register it01cf (see figure 8.13). 0: /int0 is level triggered. 1: /int0 is edge triggered. r/w r/w r/w r/w r/w r/w r/w r/w reset value tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0x88
page 126 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 figure 15.5. tmod: timer mode register bit7: gate1: timer 1 gate control. 0: timer 1 enabled when tr1 = 1 irrespective of /int1 logic level. 1: timer 1 enabled only when tr1 = 1 and /int1 is active as defined by bit in1pl in register int01cf (see figure 8.13). bit6: c/t1: counter/timer 1 select. 0: timer function: timer 1 incremented by clock defined by t1m bit (ckcon.4). 1: counter function: timer 1 incremented by high-to-low transitions on external input pin (t1). bits5-4: t1m1-t1m0: timer 1 mode select. these bits select the timer 1 operation mode. bit3: gate0: timer 0 gate control. 0: timer 0 enabled when tr0 = 1 irrespective of /int0 logic level. 1: timer 0 enabled only when tr0 = 1 and /int0 is active as defined by bit in0pl in register int01cf (see figure 8.13). bit2: c/t0: counter/timer select. 0: timer function: timer 0 incremented by clock defined by t0m bit (ckcon.3). 1: counter function: timer 0 incremented by high-to-low transitions on external input pin (t0). bits1-0: t0m1-t0m0: timer 0 mode select. these bits select the timer 0 operation mode. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue gate1 c/t1 t1m1 t1m0 gate0 c/t0 t0m1 t0m0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x89 t1m1 t1m0 mode 0 0 mode 0: 13-bit counter/timer 0 1 mode 1: 16-bit counter/timer 1 0 mode 2: 8-bit counter/timer with auto-reload 1 1 mode 3: timer 1 inactive t0m1 t0m0 mode 0 0 mode 0: 13-bit counter/timer 0 1 mode 1: 16-bit counter/timer 1 0 mode 2: 8-bit counter/timer with auto-reload 1 1 mode 3: two 8-bit counter/timers
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 127 preliminary c8051f300/1/2/3 figure 15.6. ckcon: clock control register bit7: unused. read = 0b, write = dont care. bit6: t2mh: timer 2 high byte clock select this bit selects the clock supplied to the timer 2 high byte if timer 2 is configured in split 8-bit timer mode. t2mh is ignored if timer 2 is in any other mode. 0: timer 2 high byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 high byte uses the system clock. bit5: t2ml: timer 2 low byte clock select this bit selects the clock supplied to timer 2. if timer 2 is configured in split 8-bit timer mode, this bit selects the clock supplied to the lower 8-bit timer. 0: timer 2 low byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 low byte uses the system clock. bit4: t1m: timer 1 clock select. this select the clock source supplied to timer 1. t1m is ignored when c/t1 is set to logic 1. 0: timer 1 uses the clock defined by the prescale bits, sca1-sca0. 1: timer 1 uses the system clock. bit3: t0m: timer 0 clock select. this bit selects the clock source supplied to timer 0. t0m is ignored when c/t0 is set to logic 1. 0: counter/timer 0 uses the clock defined by the prescale bits, sca1-sca0. 1: counter/timer 0 uses the system clock. bit2: unused. read = 0b, write = dont care. bits1-0: sca1-sca0: timer 0/1 prescale bits these bits control the division of the clock supplied to timer 0 and/or timer 1 if configured to use prescaled clock inputs. r/w r/w r/w r/w r/w r/w r/w r/w reset value - t2mh t2ml t1m t0m - sca1 sca0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8e sca1 sca0 prescaled clock 0 0 systemclock divided by 12 0 1 systemclock divided by 4 1 0 systemclock divided by 48 1 1 external clock divided by 8
page 128 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 figure 15.7. tl0: timer 0 low byte bits 7-0: tl0: timer 0 low byte. the tl0 register is the low byte of the 16-bit timer 0 r/wr/wr/wr/wr/wr/wr/wr/wresetvalue 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8a figure 15.8. tl1: timer 1 low byte bits 7-0: tl1: timer 1 low byte. the tl1 register is the low byte of the 16-bit timer 1. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8b figure 15.9. th0: timer 0 high byte bits 7-0: th0: timer 0 high byte. the th0 register is the high byte of the 16-bit timer 0. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8c figure 15.10. th1: timer 1 high byte bits 7-0: th1: timer 1 high byte. the th1 register is the high byte of the 16-bit timer 1. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8d
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 129 preliminary c8051f300/1/2/3 15.2. timer 2 timer 2 is a 16-bit timer formed by two 8-bit sfrs: tl2 (low byte) and th2 (high byte). timer 2 may operate in 16- bit auto-reload mode or (split) 8-bit auto-reload mode. the t2split bit (tmr2cn.3) defines the timer 2 operation mode. timer 2 may be clocked by the system clock, the system clock divided by 12, or the external oscillator source divided by 8. the external clock mode is ideal for real-time clock (rtc) functionality, where the internal oscillator drives the systemclock while timer 2 (and/or the pca) is clocked by an external precison oscillator. 15.2.1. 16-bit timer with auto-reload when t2split (tmr2cn.3) is zero, timer 2 operates as a 16-bit timer with auto-reload. timer 2 can be clocked by sysclk, sysclk divided by 12, or the external oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16-bit value in the timer 2 reload registers (tmr2rlh and tmr2rll) is loaded into the timer 2 register as shown in figure 15.11, and the timer 2 high byte overflow flag (tmr2cn.7) is set. if timer 2 interrupts are enabled (if ie.5 is set), an interrupt will be generated on each timer 2 overflow. additionally, if timer 2 interrupts are enabled and the tf2len bit is set (tmr2cn.5), an interrupt will be generated each time the lower 8 bits (tl2) overflow from 0xff to 0x00. figure 15.11. timer 2 16-bit mode block diagram external clock / 8 sysclk / 12 sysclk tl2 th2 tmr2rll tmr2rlh reload tclk 0 1 tr2 tmr2cn t2split tf2l tf2h t2xclk tr2 0 1 t2xclk ckcon t 2 m h s c a 0 s c a 1 t 2 m l t 1 m t 0 m interrupt tf2len to adc, smbus to smbus tl2 overflow
page 130 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 15.2.2. 8-bit timers with auto-reload when t2split is set, timer 2 operates as two 8-bit timers (th2 and tl2). both 8-bit timers operate in auto-reload mode as shown in figure 15.12. tmr2rll holds the reload value for tl2; tmr2rlh holds the reload value for th2. the tr2 bit in tmr2cn handles the run control th2. tl2 is always running when configured for 8-bit mode. each 8-bit timer may be configured to use sysclk, sysclk divided by 12, or the external oscillator clock source divided by 8. the timer 2 clock select bits (t2mh and t2ml in ckcon) select either sysclk or the clock defined by the timer 2 external clock select bit (t2xclk in tmr2cn), as follows: the tf2h bit is set when th2 overflows from0xff to 0x00; the tf2l bit is set when tl2 overflows from0xff to 0x00. when timer 2 interrupts are enabled (ie.5), an interrupt is generated each time th2 overflows. if timer 2 interrupts are enabled and tf2len (tmr2cn.5) is set, an interrupt is generated each time either tl2 or th2 over- flows. when tf2len is enabled, software must check the tf2h and tf2l flags to determine the source of the timer 2 interrupt. the tf2h and tf2l interrupt flags are not cleared by hardware and must be manually cleared by software . t2mh t2xclk th2 clock source t2ml t2xclk tl2 clock source 0 0 sysclk / 12 0 0 sysclk / 12 0 1 external clock / 8 0 1 external clock / 8 1 x sysclk 1 x sysclk figure 15.12. timer 2 8-bit mode block diagram sysclk tclk 0 1 tr2 external clock / 8 sysclk / 12 0 1 t2xclk 1 0 th2 tmr2rlh reload ckcon t 2 m h s c a 0 s c a 1 t 2 m l t 1 m t 0 m reload tclk tl2 tmr2rll interrupt tmr2cn t2split tf2len tf2l tf2h t2xclk tr2 to adc, smbus to smbus
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 131 preliminary c8051f300/1/2/3 bit7: tf2h: timer 2 high byte overflow flag set by hardware when the timer 2 high byte overflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 2 overflows from 0xffff to 0x0000. when the timer 2 interrupt is enabled, set- ting this bit causes the cpu to vector to the timer 2 interrupt service routine. tf2h is not automati- cally cleared by hardware and must be cleared by software. bit6: tf2l: timer 2 low byte overflow flag set by hardware when the timer 2 low byte overflows from 0xff to 0x00. when this bit is set, an interrupt will be generated if tf2len is set and timer 2 interrupts are enabled. tf2l will set when the low byte overflows regardless of the timer 2 mode. this bit is not automatically cleared by hard- ware. bit5: tf2len: timer 2 low byte interrupt enable. this bit enables/disables timer 2 low byte interrupts. if tf2len is set and timer 2 interrupts are enabled, an interrupt will be generated when the low byte of timer 2 overflows. this bit should be cleared when operating timer 2 in 16-bit mode. 0: timer 2 low byte interrupts disabled. 1: timer 2 low byte interrupts enabled. bit4: unused. read = 0b. write = dont care. bit3: t2split: timer 2 split mode enable when this bit is set, timer 2 operates as two 8-bit timers with auto-reload. 0: timer 2 operates in 16-bit auto-reload mode. 1: timer 2 operates as two 8-bit auto-reload timers. bit2: tr2: timer 2 run control. this bit enables/disables timer 2. in 8-bit mode, this bit enables/disables th2 only; tl2 is always enabled in this mode. 0: timer 2 disabled. 1: timer 2 enabled. bit1: unused. read = 0b. write = dont care. bit0: t2xclk: timer 2 external clock select this bit selects the external clock source for timer 2. if timer 2 is in 8-bit mode, this bit selects the external oscillator clock source for both timer bytes. however, the timer 2 clock select bits (t2mh and t2ml in register ckcon) may still be used to select between the external clock and the system clock for either timer. 0: timer 2 external clock selection is the system clock divided by 12. 1: timer 2 external clock selection is the external clock divided by 8. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue tf2h tf2l tf2len - t2split tr2 - t2xclk 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xc8 figure 15.13. tmr2cn: timer 2 control register
page 132 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 bits 7-0: tmr2rll: timer 2 reload register low byte. tmr2rll holds the low byte of the reload value for timer 2. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xca figure 15.14. tmr2rll: timer 2 reload register low byte figure 15.15. tmr2rlh: timer 2 reload register high byte bits 7-0: tmr2rlh: timer 2 reload register high byte. the tmr2rlh holds the high byte of the reload value for timer 2. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xcb figure 15.16. tmr2l: timer 2 low byte bits 7-0: tmr2l: timer 2 low byte. in 16-bit mode, the tmr2l register contains the low byte of the 16-bit timer 2. in 8-bit mode, tmr2l contains the 8-bit low byte timer value. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xcc figure 15.17. tmr2h timer 2 high byte bits 7-0: tmr2h: timer 2 high byte. in 16-bit mode, the tmr2h register contains the high byte of the 16-bit timer 2. in 8-bit mode, tmr2h contains the 8-bit high byte timer value. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xcd
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 133 preliminary c8051f300/1/2/3 16. programmable counter array the programmable counter array (pca0) provides enhanced timer functionality while requiring less cpu interven- tion than the standard 8051 counter/timers. the pca consists of a dedicated 16-bit counter/timer and three 16-bit capture/compare modules. each capture/compare module has its own associated i/o line (cexn) which is routed through the crossbar to port i/o when enabled (see section 12.1. priority crossbar decoder on page 86 for details on configuring the crossbar). the counter/timer is driven by a programmable timebase that can select between six sources: systemclock, systemclock divided by four, systemclock divided by twelve, the external oscillator clock source divided by 8, timer 0 overflow, or an external clock signal on the eci input pin. each capture/compare mod- ule may be configured to operate independently in one of six modes: edge-triggered capture, software timer, high- speed output, frequency output, 8-bit pwm, or 16-bit pwm (each mode is described in section 16.2. capture/ compare modules on page 135 ). the external oscillator clock option is ideal for real-time clock (rtc) functional- ity, allowing the pca to be clocked by a precision external oscillator while the internal oscillator drives the system clock. the pca is configured and controlled through the systemcontroller's special function registers. the basic pca block diagramis shown in figure 16.1 . 16-bit counter/timer cex1 eci digital crossbar cex2 cex0 port i/o capture/compare module 1 capture/compare module 0 capture/compare module 2 pca clock mux sysclk/12 sysclk/4 timer 0 overflow eci sysclk external clock/8 figure 16.1. pca block diagram
page 134 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 16.1. pca counter/timer the 16-bit pca counter/timer consists of two 8-bit sfrs: pca0l and pca0h. pca0h is the high byte (msb) of the 16-bit counter/timer and pca0l is the low byte (lsb). reading pca0l automatically latches the value of pca0h into a snapshot register; the following pca0h read accesses this snapshot register. reading the pca0l register first guarantees an accurate reading of the entire 16-bit pca0 counter. reading pca0h or pca0l does not disturb the counter operation. the cps2-cps0 bits in the pca0md register select the timebase for the counter/timer as shown in table 16.1. when the counter/timer overflows from 0xffff to 0x0000, the counter overflow flag (cf) in pca0md is set to logic 1 and an interrupt request is generated if cf interrupts are enabled. setting the ecf bit in pca0md to logic 1 enables the cf flag to generate an interrupt request. the cf bit is not automatically cleared by hardware when the cpu vectors to the interrupt service routine, and must be cleared by software (note: pca0 interrupts must be glo- bally enabled before cf interrupts are recognized. pca0 interrupts are globally enabled by setting the ea bit (ie.7) and the epca0 bit in eie1 to logic 1). clearing the cidl bit in the pca0md register allows the pca to continue normal operation while the cpu is in idle mode. table 16.1. pca timebase input options cps2 cps1 cps0 timebase 0 0 0 systemclock divided by 12 0 0 1 systemclock divided by 4 0 1 0 timer 0 overflow 0 1 1 high-to-low transitions on eci (max rate = system clock divided by 4) 1 0 0 systemclock 1 0 1 external oscillator source divided by 8 figure 16.2. pca counter/timer block diagram pca0cn c f c r c c f 0 c c f 2 c c f 1 sysclk/12 sysclk/4 timer 0 overflow eci 000 001 010 011 pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 idle 0 1 100 101 sysclk external clock/8 pca0h pca0l snapshot register to sfr bus overflow to pca interrupt system cf pca0l read to pca modules
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 135 preliminary c8051f300/1/2/3 16.2. capture/compare modules each module can be configured to operate independently in one of six operation modes: edge-triggered capture, software timer, high speed output, frequency output, 8-bit pulse width modulator, or 16-bit pulse width modu- lator. each module has special function registers (sfrs) associated with it in the cip-51 system controller. these registers are used to exchange data with a module and configure the module's mode of operation. table 16.2 summarizes the bit settings in the pca0cpmn registers used to select the pca capture/compare modules operating modes. setting the eccfn bit in a pca0cpmn register enables the module's ccfn interrupt. note: pca0 interrupts must be globally enabled before individual ccfn interrupts are recognized. pca0 interrupts are globally enabled by setting the ea bit (ie.7) and the epca0 bit (eie1.3) to logic 1. see figure 16.3 for details on the pca interrupt configuration. table 16.2. pca0cpm register settings for pca capture/compare modules pwm16 ecom capp capn mat tog pwm eccf operation mode x x 1 0 0 0 0 x capture triggered by positive edge on cexn x x 0 1 0 0 0 x capture triggered by negative edge on cexn x x 1 1 0 0 0 x capture triggered by transition on cexn x 1 0 0 1 0 0 x software timer x 1 0 0 1 1 0 x high speed output x 1 0 0 x 1 1 x frequency output 0 1 0 0 x 0 1 x 8-bit pulse width modulator 1 1 0 0 x 0 1 x 16-bit pulse width modulator x = dont care figure 16.3. pca interrupt block diagram pca0cn c f c r c c f 0 c c f 2 c c f 1 pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 0 1 pca module 0 pca module 1 eccf1 0 1 eccf0 0 1 pca module 2 eccf2 pca counter/ timer overflow 0 1 pca0cpmn (forn=0to2) p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n interrupt priority decoder epca0 (eie.3) 0 1 ea (ie.7) 0 1
page 136 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 16.2.1. edge-triggered capture mode in this mode, a valid transition on the cexn pin causes the pca to capture the value of the pca counter/timer and load it into the corresponding module's 16-bit capture/compare register (pca0cpln and pca0cphn). the cappn and capnn bits in the pca0cpmn register are used to select the type of transition that triggers the capture: low-to- high transition (positive edge), high-to-low transition (negative edge), or either transition (positive or negative edge). when a capture occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1 and an interrupt request is generated if ccf interrupts are enabled. the ccfn bit is not automatically cleared by hardware when the cpu vec- tors to the interrupt service routine, and must be cleared by software. if both cappn and capnn bits are set to logic 1, then the state of the port pin associated with cexn can be read directly to determine whether a rising-edge or fall- ing-edge caused the capture. figure 16.4. pca capture mode diagram pca0l pca0cpln pca timebase cexn crossbar port i/o pca0h capture pca0cphn 0 1 0 1 (to ccfn) pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n pca0cn c f c r c c f 0 c c f 2 c c f 1 pca interrupt 0 000x x
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 137 preliminary c8051f300/1/2/3 16.2.2. software timer (compare) mode in software timer mode, the pca counter/timer value is compared to the module's 16-bit capture/compare register (pca0cphn and pca0cpln). when a match occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1 and an interrupt request is generated if ccf interrupts are enabled. the ccfn bit is not automatically cleared by hardware when the cpu vectors to the interrupt service routine, and must be cleared by software. setting the ecomn and matn bits in the pca0cpmn register enables software timer mode. important note about capture/compare registers : when writing a 16-bit value to the pca0 capture/compare registers, the low byte should always be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. figure 16.5. pca software timer mode diagram match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 00 00 0 1 x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x pca0cn c f c r c c f 0 c c f 2 c c f 1 pca interrupt
page 138 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 16.2.3. high speed output mode in high speed output mode, a modules associated cexn pin is toggled each time a match occurs between the pca counter and the module's 16-bit capture/compare register (pca0cphn and pca0cpln) setting the togn, matn, and ecomn bits in the pca0cpmn register enables the high-speed output mode. important note about capture/compare registers : when writing a 16-bit value to the pca0 capture/compare registers, the low byte should always be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. figure 16.6. pca high speed output mode diagram match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 0 1 00 0x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x cexn crossbar port i/o toggle 0 1 togn pca0cn c f c r c c f 0 c c f 2 c c f 1 pca interrupt
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 139 preliminary c8051f300/1/2/3 16.2.4. frequency output mode frequency output mode produces a programmable-frequency square wave on the modules associated cexn pin. the capture/compare module high byte holds the number of pca clocks to count before the output is toggled. the frequency of the square wave is then defined by equation 16.1. where f pca is the frequency of the clock selected by the cps2-0 bits in the pca mode register, pca0md. the lower byte of the capture/compare module is compared to the pca counter low byte; on a match, cexn is toggled and the offset held in the high byte is added to the matched value in pca0cpln. note that enabling module match (ccfn) interrupts in this mode will generate interrupts at rate of 2* f cexn . frequency output mode is enabled by set- ting the ecomn, togn, and pwmn bits in the pca0cpmn register. equation 16.1. square wave frequency output f cexn f pca 2 pca 0 cphn ---------------------------------------- - = 8-bit comparator pca0l enable pca timebase match pca0cphn 8-bit adder pca0cpln adder enable cexn crossbar port i/o toggle 0 1 togn 000 x pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x enb enb 0 1 write to pca0cpln write to pca0cphn reset figure 16.7. pca frequency output mode
page 140 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 16.2.5. 8-bit pulse width modulator mode each module can be used independently to generate a pulse width modulated (pwm) output on its associated cexn pin. the frequency of the output is dependent on the timebase for the pca counter/timer. the duty cycle of the pwm output signal is varied using the module's pca0cpln capture/compare register. when the value in the low byte of the pca counter/timer (pca0l) is equal to the value in pca0cpln, the output on the cexn pin will be set. when the count value in pca0l overflows, the cexn output will be reset (see figure 16.8). also, when the counter/timer low byte (pca0l) overflows from 0xff to 0x00, pca0cpln is reloaded automatically with the value stored in the mod- ules capture/compare high byte (pca0cphn) without software intervention. setting the ecomn and pwmn bits in the pca0cpmn register enables 8-bit pulse width modulator mode. the duty cycle for 8-bit pwm mode is given by equation 16.2. important note about capture/compare registers : when writing a 16-bit value to the pca0 capture/compare registers, the low byte should always be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. using equation 16.2, the largest duty cycle is 100% (pca0cphn = 0), and the smallest duty cycle is 0.39% (pca0cphn = 0xff). a 0% duty cycle may be generated by clearing the ecomn bit to 0. dutycycle 256 pca 0 cphn C () 256 --------------------------------------------------- = equation 16.2. 8-bit pwm duty cycle 8-bit comparator pca0l pca0cpln pca0cphn cexn crossbar port i/o enable overflow pca timebase 00x0 x q q set clr s r match pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 enb enb 0 1 write to pca0cpln write to pca0cphn reset figure 16.8. pca 8-bit pwm mode diagram
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 141 preliminary c8051f300/1/2/3 16.2.6. 16-bit pulse width modulator mode a pca module may also be operated in 16-bit pwm mode. in this mode, the 16-bit capture/compare module defines the number of pca clocks for the low time of the pwm signal. when the pca counter matches the module contents, the output on cexn is asserted high; when the counter overflows, cexn is asserted low. to output a varying duty cycle, new value writes should be synchronized with pca ccfn match interrupts. 16-bit pwm mode is enabled by setting the ecomn, pwmn, and pwm16n bits in the pca0cpmn register. for a varying duty cycle, match interrupts should be enabled (eccfn = 1 and matn = 1) to help synchronize the capture/compare register writes. the duty cycle for 16-bit pwm mode is given by equation 16.3. important note about capture/compare registers : when writing a 16-bit value to the pca0 capture/compare registers, the low byte should always be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. using equation 16.3, the largest duty cycle is 100% (pca0cpn = 0), and the smallest duty cycle is 0.0015% (pca0cpn = 0xffff). a 0% duty cycle may be generated by clearing the ecomn bit to 0. equation 16.3. 16-bit pwm duty cycle dutycycle 65536 pca 0 cpn C () 65536 ---------------------------------------------------- - = figure 16.9. pca 16-bit pwm mode pca0cpln pca0cphn enable pca timebase 00x0 x pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 1 16-bit comparator cexn crossbar port i/o overflow q q set clr s r match pca0h pca0l enb enb 0 1 write to pca0cpln write to pca0cphn reset
page 142 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 16.3. watchdog timer mode a programmable watchdog timer (wdt) function is available through the pca module 2. the wdt is used to gen- erate a reset if the time between writes to the wdt update register (pca0cph2) exceed a specified limit. the wdt can be configured and enabled/disabled as needed by software. with the wdte bit set in the pca0md register, module 2 operates as a watchdog timer (wdt). the module 2 high byte is compared to the pca counter high byte; the module 2 low byte holds the offset to be used when wdt updates are performed. the watchdog timer is enabled on reset. 16.3.1. watchdog timer operation while the wdt is enabled: ? pca counter is forced on. ? writes to pca0l and pca0h are not allowed. ? pca clock source bits (cps2-cps0) are frozen. ? pca idle control bit (cidl) is frozen. ? module 2 is forced into software timer mode. ? writes to the module 2 mode register (pca0cpm2) are disabled. while the wdt is enabled, writes to the cr bit will not change the pca counter state; the counter will run until the wdt is disabled. the pca counter run control (cr) will read zero if the wdt is enabled but user software has not enabled the pca counter. if a match occurs between pca0cph2 and pca0h while the wdt is enabled, a reset will be generated. to prevent a wdt reset, the wdt may be updated with a write of any value to pca0cph2. upon a pca0cph2 write, pca0h plus the offset held in pca0cpl2 is loaded into pca0cph2 (see figure 16.10). figure 16.10. pca module 2 with watchdog timer enabled pca0h enable pca0l overflow reset pca0cpl2 8-bit adder pca0cph2 adder enable pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 match write to pca0cph2 8-bit comparator
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 143 preliminary c8051f300/1/2/3 note that the 8-bit offset held in pca0cph2 is compared to the upper byte of the 16-bit pca counter. this offset value is the number of pca0l overflows before a reset. up to 256 pca clocks may pass before the first pca0l overflow occurs, depending on the value of the pca0l when the update is performed. the total offset is then given (in pca clocks) by equation 16.4, where pca0l is the value of the pca0l register at the time of the update. the wdt reset is generated when pca0l overflows while there is a match between pca0cph2 and pca0h. soft- ware may force a wdt reset by writing a 1 to the ccf2 flag (pca0cn.2) while the wdt is enabled. 16.3.2. watchdog timer usage to configure the wdt, performthe following tasks: ? disable the wdt by writing a 0 to the wdte bit. ? select the desired pca clock source (with the cps2-cps0 bits). ? load pca0cpl2 with the desired wdt update offset value. ? configure the pca idle mode (set cidl if the wdt should be suspended while the cpu is in idle mode). ? enable the wdt by setting the wdte bit to 1. the pca clock source and idle mode select cannot be changed while the wdt is enabled. the watchdog timer is enabled by setting the wdte or wdlck bits in the pca0md register. when wdlck is set, the wdt cannot be disabled until the next systemreset. if wdlck is not set, the wdt is disabled by clearing the wdte bit. the wdt is enabled following any reset. the pca0 counter clock defaults to the systemclock divided by 12, pca0l defaults to 0x00, and pca0cpl2 defaults to 0x00. using equation 16.4, this results in a wdt timeout inter- val of 256 system clock cycles. table 16.3 lists some example timeout intervals for typical system clocks. table 16.3. watchdog timer timeout intervals system clock (hz) pca0cpl2 timeout interval (ms) 24,500,000 255 2.6645 24,500,000 128 1.3375 24,500,000 32 0.3344 18,432,000 255 3.5417 18,432,000 128 1.7778 18,432,000 32 0.4444 11,059,200 255 5.9028 11,059,200 128 2.9630 11,059,200 32 0.7407 3,686,400 255 17.7083 3,686,400 128 8.8889 3,686,400 32 2.2222 32,000 255 2040.0 32,000 128 1024.0 32,000 32 256.0 equation 16.4. watchdog timer offset in pca clocks offset 256 pca 0 cpl 2 () 256 pca 0 l C () + =
page 144 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 16.4. register descriptions for pca following are detailed descriptions of the special function registers related to the operation of the pca. bit7: cf: pca counter/timer overflow flag. set by hardware when the pca counter/timer overflows from 0xffff to 0x0000. when the counter/timer overflow (cf) interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. bit6: cr: pca counter/timer run control. this bit enables/disables the pca counter/timer. 0: pca counter/timer disabled. 1: pca counter/timer enabled. bits5-3: unused. read = 000b, write = don't care. bit2: ccf2: pca module 2 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf2 interrupt is enabled, set- ting this bit causes the cpu to vector to the pca interrupt service routine. this bit is not automati- cally cleared by hardware and must be cleared by software. bit1: ccf1: pca module 1 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf1 interrupt is enabled, set- ting this bit causes the cpu to vector to the pca interrupt service routine. this bit is not automati- cally cleared by hardware and must be cleared by software. bit0: ccf0: pca module 0 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf0 interrupt is enabled, set- ting this bit causes the cpu to vector to the pca interrupt service routine. this bit is not automati- cally cleared by hardware and must be cleared by software. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue cf cr - - - ccf2 ccf1 ccf0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xd8 figure 16.11. pca0cn: pca control register
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 145 preliminary c8051f300/1/2/3 figure 16.12. pca0md: pca mode register bit7: cidl: pca counter/timer idle control. specifies pca behavior when cpu is in idle mode. 0: pca continues to function normally while the system controller is in idle mode. 1: pca operation is suspended while the systemcontroller is in idle mode. bit6: wdte: watchdog timer enable if this bit is set, pca module 2 is used as the watchdog timer. 0: watchdog timer disabled. 1: pca module 2 enabled as watchdog timer. bit5: wdlck: watchdog timer lock this bit locks/unlocks the watchdog timer enable. when wdlck is set, the watchdog timer may not be disabled until the next systemreset. 0: watchdog timer enable unlocked. 1: watchdog timer enable locked. bit4: unused. read = 0b, write = don't care. bits3-1: cps2-cps0: pca counter/timer pulse select. these bits select the timebase source for the pca counter bit0: ecf: pca counter/timer overflow interrupt enable. this bit sets the masking of the pca counter/timer overflow (cf) interrupt. 0: disable the cf interrupt. 1: enable a pca counter/timer overflow interrupt request when cf (pca0cn.7) is set. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue cidl wdte wdlck - cps2 cps1 cps0 ecf 01000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd9 cps2 cps1 cps0 timebase 0 0 0 systemclock divided by 12 0 0 1 systemclock divided by 4 0 1 0 timer 0 overflow 011 high-to-low transitions on eci (max rate = system clock divided by 4) 100systemclock 1 0 1 external clock divided by 8 1 1 0 reserved 1 1 1 reserved
page 146 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 pca0cpmn address: pca0cpm0 = 0xda (n = 0) pca0cpm1 = 0xdb (n = 1) pca0cpm2 = 0xdc (n = 2) bit7: pwm16n: 16-bit pulse width modulation enable this bit selects 16-bit mode when pulse width modulation mode is enabled (pwmn = 1). 0: 8-bit pwm selected. 1: 16-bit pwm selected. bit6: ecomn: comparator function enable. this bit enables/disables the comparator function for pca module n. 0: disabled. 1: enabled. bit5: cappn: capture positive function enable. this bit enables/disables the positive edge capture for pca module n. 0: disabled. 1: enabled. bit4: capnn: capture negative function enable. this bit enables/disables the negative edge capture for pca module n. 0: disabled. 1: enabled. bit3: matn: match function enable. this bit enables/disables the match function for pca module n. when enabled, matches of the pca counter with a module's capture/compare register cause the ccfn bit in pca0md register to be set to logic 1. 0: disabled. 1: enabled. bit2: togn: toggle function enable. this bit enables/disables the toggle function for pca module n. when enabled, matches of the pca counter with a module's capture/compare register cause the logic level on the cexn pin to toggle. if the pwmn bit is also set to logic 1, the module operates in frequency output mode. 0: disabled. 1: enabled. bit1: pwmn: pulse width modulation mode enable. this bit enables/disables the pwm function for pca module n. when enabled, a pulse width modu- lated signal is output on the cexn pin. 8-bit pwm is used if pwm16n is cleared; 16-bit mode is used if pwm16n is set to logic 1. if the togn bit is also set, the module operates in frequency output mode. 0: disabled. 1: enabled. bit0: eccfn: capture/compare flag interrupt enable. this bit sets the masking of the capture/compare flag (ccfn) interrupt. 0: disable ccfn interrupts. 1: enable a capture/compare flag interrupt request when ccfn is set. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue pwm16n ecomn cappn capnn matn togn pwmn eecfn 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xda, 0xdb, 0xdc f i gure 16 . 13 .p c a 0c pmn: p c a c apture /c ompare mode reg i sters
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 147 preliminary c8051f300/1/2/3 bits 7-0: pca0l: pca counter/timer low byte. the pca0l register holds the low byte (lsb) of the 16-bit pca counter/timer. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf9 f i gure 16 . 14 .p c a 0 l: p c a c ounter / t i mer low byte bits 7-0: pca0h: pca counter/timer high byte. the pca0h register holds the high byte (msb) of the 16-bit pca counter/timer. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xfa figure 16.15. pca0h: pca counter/timer high byte
page 148 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 figure 16.16. pca0cpln: pca capture module low byte pca0cpln address: pca0cpl0 = 0xfb (n = 0) pca0cpl1 = 0xe9 (n = 1) pca0cpl2 = 0xeb (n = 2) bits7-0: pca0cpln: pca capture module low byte. the pca0cpln register holds the low byte (lsb) of the 16-bit capture module n. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xfb, 0xe9, 0xeb pca0cphn address: pca0cph0 = 0xfc (n = 0) pca0cph1 = 0xea (n = 1) pca0cph2 = 0xec(n = 2) bits7-0: pca0cphn: pca capture module high byte. the pca0cphn register holds the high byte (msb) of the 16-bit capture module n. r/wr/wr/wr/wr/wr/wr/wr/wresetvalue 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xfc, 0xea, 0xec figure 16.17. pca0cphn: pca capture module high byte
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 149 preliminary c8051f300/1/2/3 17. c2 interface c8051f300/1/2/3 devices include an on-chip cygnal 2-wire (c2) debug interface to allow flash programming, boundary scan functions, and in-systemdebugging with the production part installed in the end application. the c2 interface operates similar to jtag, where the three jtag data signals (tdi, tdo, tms) are mapped into one bi- directional c2 data signal (c2d). see the c2 interface specification for details on the c2 protocol. 17.1. c2 interface registers the following describes the c2 registers necessary to perform flash programming and boundary scan functions through the c2 interface. all c2 registers are accessed through the c2 interface as described in the c2 interface spec- ification. figure 17.1. c2add: c2 address register bits7-0: the c2add register is accessed via the c2 interface to select the target data register for c2 data read and data write commands. reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address description 0x00 selects the device id register for data read instructions 0x01 selects the revision id register for data read instructions 0x02 selects the c2 flash programming control register for data read/write instructions 0xb4 selects the c2 flash programming data register for data read/write instructions 0x80 selects the port0 register for data read/write instructions 0xf1 selects the port0 input mode register for data read/write instructions 0xa4 selects the port0 output mode register for data read/write instructions figure 17.2. deviceid: c2 device id register this read-only register returns the 8-bit device id: 0x04 (c8051f300/1/2/3). reset value 00000100 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
page 150 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 figure 17.3. revid: c2 revision id register this read-only register returns the 8-bit revision id: 0x00 (revision a) reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 figure 17.4. fpctl: c2 flash programming control register bits7-0 fpctl: flash programming control register this register is used to enable flash programming via the c2 interface. to enable c2 flash programming, the following codes must be written in order: 0x02, 0x01. note that once c2 flash programming is enabled, a system reset must be issued to resume normal operation. reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 figure 17.5. fpdat: c2 flash programming data register bits7-0: fpdat: c2 flash programming data register this register is used to pass flash commands, addresses, and data during c2 flash accesses. valid commands are listed below. reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 code command 0x06 flash block read 0x07 flash block write 0x08 flash page erase 0x03 device erase
? 2001 cygnal integrated products, inc. ds004-1.0 oct01 page 151 preliminary c8051f300/1/2/3 17.2. c2 pin sharing the c2 protocol allows the c2 pins to be shared with user functions so that in-systemdebugging, flash program- ming, and boundary scan functions may be performed. this is possible because c2 communication is typically per- formed when the device is in the halt state, where all on-chip peripherals and user software are stalled. in this halted state, the c2 interface can safely borrow the c2ck (normally /rst) and c2d (normally p0.7) pins. in most appli- cations, external resistors are required to isolate c2 interface traffic fromthe user application. a typical isolation con- figuration is shown in figure 17.6. the configuration in figure 17.6 assumes the following: 1. the user input (b) cannot change state while the target device is halted. 2. the /rst pin on the target device is used as an input only. additional resistors may be necessary depending on the specific application. c2d (p0.7) c2ck (/rst) /reset (a) input (b) output (c) c8051f300 figure 17.6. typical c2 pin sharing
page 152 ds004-1.0 oct01 ? 2001 cygnal integrated products, inc. preliminary c8051f300/1/2/3 disclaimers life support : these products are not designed for use in life support appliances or systems where malfunction of these products can reasonably be expected to result in personal injury. cygnal integrated products customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify cygnal inte- grated products for any damages resulting from such applications. right to make changes : cygnal integrated products reserves the right to make changes, without notice, in the prod- ucts, including circuits and/or software, described or contained herein in order to improve design and/or performance. cygnal integrated products assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free frompatent, copyright, or mask work infringement, unless otherwise specified. cip-51 is a trademark of cygnal integrated products, inc. mcs-51 and smbus are trademarks of intel corporation. i 2 c is a trademark of philips semiconductor. cygnal integratedproducts 4301 westbank drive suite b-100 austin, tx 78746 www.cygnal.com

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