 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation (http://www.renesas.com) send any inquiries to http://www.renesas.com/inquiry.
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas el ectronics products li sted herein, please confirm the latest product information with a renesas electronics sales office. also , please pay regular and careful attention to additional and different information to be disclosed by rene sas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringeme nt of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electroni cs products or techni cal information descri bed in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyri ghts or other intell ectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any re nesas electronics product, wh ether in whole or in part . 4. descriptions of circuits, software and other related informat ion in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully re sponsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this doc ument, you should comply with the applicable export control laws and regulations and follow the proc edures required by such laws and re gulations. you should not use renesas electronics products or the technology described in this docum ent for any purpose relating to mil itary applicati ons or use by the military, including but not l imited to the development of weapons of mass de struction. renesas electronics products and technology may not be used for or incor porated into any products or systems whose manufacture, us e, or sale is prohibited under any applicable dom estic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing th e information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products ar e classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product de pends on the product?s quality grade, as indicated below. you must check the qua lity grade of each renesas electronics pr oduct before using it in a particular application. you may not use any renesas electronics produc t for any application categorized as ?speci fic? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. re nesas electronics shall not be in any way liable for any damages or losses incurred by you or third partie s arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intende d where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electr onics data sheets or data books, etc. ?standard?: computers; office equipmen t; communications e quipment; test and measurement equipment; audio and visual equipment; home electronic a ppliances; machine tools; personal electronic equipmen t; and industrial robots. ?high quality?: transportation equi pment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specif ically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support device s or systems), surgical im plantations, or healthcare intervention (e.g. excision, etc.), and any other applicati ons or purposes that pose a di rect threat to human life. 8. you should use the renesas electronics pr oducts described in this document within the range specified by renesas electronics , especially with respect to the maximum ra ting, operating supply voltage range, movement power volta ge range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its produc ts, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate a nd malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physic al injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safe ty design for hardware and software in cluding but not limited to redundancy, fire control and malfunction prevention, appropri ate treatment for aging degradation or an y other appropriate measures. because the evaluation of microcomputer software alone is very difficult , please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesa s electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regul ate the inclusion or use of c ontrolled substances, including wi thout limitation, the eu rohs directive. renesas electronics assumes no liability for damage s or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in w hole or in part, without prio r written consent of renes as electronics. 12. please contact a renesa s electronics sales office if you have any questi ons regarding the informat ion contained in this document or renesas electroni cs products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics. document no. u17553ej4v0ud00 (4th edition) date published march 2007 ns cp(k) printed in japan 2005 pd78f0891(a) pd78f0891(a2) pd78f0892(a) pd78f0892(a2) pd78f0893(a) pd78f0893(a2) 78k0/ff2 8-bit single-chip microcontrollers user?s manual the 78k0/ff2 has an on-chip debug function. do not use this product for mass production after the on-ch ip debug function has been used because its reliability cannot be guaranteed, due to issues with respect to the number of times the flash memory can be rewritten. nec electronics does not accept complaints concerning when use this produc t for mass production after the on-chip debug function has been used. user?s manual u17553ej4v0ud 2 [memo] user?s manual u17553ej4v0ud 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6 user?s manual u17553ej4v0ud 4 eeprom is trademark of nec electronics corporation. windows, windows nt and windows xp are either regi stered trademarks or tr ademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of internati onal business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademar ks of sun microsystems, inc. superflash is a registered trademark of silicon storage t echnology, inc. in several countries including the united states and japan. caution: this product uses superflash ? technology licensed from silicon storage technology, inc. the information in this document is current as of march, 2007. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec ele ctronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific": user?s manual u17553ej4v0ud 5 [memo] user?s manual u17553ej4v0ud 6 introduction readers this manual is intended for user engineer s who wish to understand the functions of the 78k0/ff2 and design and develop application systems and programs for these devices. the target products are as follows. 78k0/ff2: pd78f0891 (a), 78f0892 (a), 78f0893 (a), 78f0891 (a2), 78f0892 (a2), 78f0893 (a2), purpose this manual is intended to give users an understanding of the functions described in the organization below. organization the 78k0/ff2 manual are separated into two parts: this manual and the instructions edition (common to the 78k/0 series). 78k0/ff2 user?s manual (this manual) 78k/0 series user?s manual instructions ? pin functions ? internal block functions ? interrupts ? other on-chip peripheral functions ? electrical specifications ? cpu functions ? instruction set ? explanation of each instruction how to read this manual it is assumed that the readers of this ma nual have general knowledge of electrical engineering, logic circuits, and microcontrollers. ? when using this manual as the manual for (a) and (a2) grade products: only the quality grade differs betwe en (a) grade products and (a2) grade products. read the part number as follows. ? pd78f0891 pd78f0891 (a), 78f0891 (a2) ? pd78f0892 pd78f0892 (a), 78f0892 (a2) ? pd78f0893 pd78f0893 (a), 78f0893 (a2) ? to gain a general understanding of functions: read this manual in the order of the contents . the mark user?s manual u17553ej4v0ud 7 related documents the related documents indicated in this pu blication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. 78k0/ff2 user?s manual this manual 78k/0 series instructions user?s manual u12326e documents related to development tools (software) (user?s manuals) document name document no. operation u17199e language u17198e ra78k0 ver.3.80 assembler package structured assembly language u17197e operation u17201e cc78k0 ver.3.70 c compiler language u17200e id78k0-qb ver. 2.90 integrat ed debugger operation u17437e pm plus ver. 5.20 u16934e documents related to development tools (hardware) (user?s manuals) document name document no. qb-78k0fx2 in-circuit emulator u17534e qb-78k0mini on-chip debug emulator u17029e qb-mini2 on-chip debug emulator with programming function u18371e documents related to fl ash memory programming document name document no. pg-fp4 flash memory programmer user?s manual u15260e pg-fpl3 flash memory programmer user?s manual u17454e other documents document name document no. semiconductor selection guide ? products and packages ? x13769x semiconductor device mount manual note quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devi ces by electrostatic discharge (esd) c11892e note see the ?semiconductor device mo unt manual? website (http://www.necel .com/pkg/en/mount/index.html). caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document when designing. user?s manual u17553ej4v0ud 8 contents chapter 1 outline ........................................................................................................... ................. 17 1.1 features.................................................................................................................. ....................... 17 1.2 applications .............................................................................................................. .................... 18 1.3 ordering information ...................................................................................................... ............. 18 1.4 pin configuration (top view) .............................................................................................. ........ 19 1.5 fx2 series lineup......................................................................................................... ................ 21 1.5.1 78k0/fx2 product lineup ................................................................................................. .................. 21 1.6 block diagram ............................................................................................................. ................. 23 1.7 outline of functions ...................................................................................................... .............. 24 chapter 2 pin functions .................................................................................................... ........... 26 2.1 pin function list ......................................................................................................... ................. 26 2.2 description of pin functions .............................................................................................. ........ 30 2.2.1 p00, p01, p05, p06 (port 0) ............................................................................................. ................. 30 2.2.2 p10 to p17 (por t 1) ..................................................................................................... ....................... 31 2.2.3 p30 to p33 (por t 3) ..................................................................................................... ....................... 32 2.2.4 p40 to p47 (por t 4) ..................................................................................................... ....................... 32 2.2.5 p50 to p57 (por t 5) ..................................................................................................... ....................... 33 2.2.6 p60 to p67 (por t 6) ..................................................................................................... ....................... 33 2.2.7 p70 to p76 (por t 7) ..................................................................................................... ....................... 33 2.2.8 p80 to p87 (por t 8) ..................................................................................................... ....................... 34 2.2.9 p90 to p97 (por t 9) ..................................................................................................... ....................... 34 2.2.10 p120 to p124 ( port 12) ................................................................................................. ................... 34 2.2.11 p130 to p132 ( port 13) ................................................................................................. ................... 35 2.2.12 av ref ............................................................................................................................... ................ 36 2.2.13 av ss ............................................................................................................................... ................. 36 2.2.14 reset .................................................................................................................. .......................... 36 2.2.15 regc................................................................................................................... ........................... 36 2.2.16 v dd and ev dd ............................................................................................................................... ... 36 2.2.17 v ss and ev ss ............................................................................................................................... .... 36 2.2.18 flmd0 .................................................................................................................. .......................... 36 2.3 pin i/o circuits and recomme nded connection of unused pins .... ....................................... 37 chapter 3 cpu architecture ................................................................................................. ..... 41 3.1 memory space .............................................................................................................. ................ 41 3.1.1 internal progr am memory space........................................................................................... ............. 47 3.1.2 bank area ( pd78f0892 and 78f0 893 onl y).................................................................................... 48 3.1.3 internal dat a memory space .............................................................................................. ................ 50 3.1.4 special function register (sfr) area .................................................................................... ............. 50 3.1.5 data me mory addr essing .................................................................................................. ................ 50 3.2 processor registers ....................................................................................................... ............. 54 3.2.1 contro l regist ers ....................................................................................................... ......................... 54 3.2.2 general-pur pose registers............................................................................................... .................. 58 3.2.3 special functi on register s (sfrs) ....................................................................................... ............ 59 3.3 instruction address addressi ng............................................................................................ ..... 66 user?s manual u17553ej4v0ud 9 3.3.1 relati ve addre ssing..................................................................................................... .......................66 3.3.2 immedi ate addres sing.................................................................................................... ....................67 3.3.3 table indi rect addr essing ............................................................................................... ....................68 3.3.4 regist er addre ssing ..................................................................................................... ......................68 3.4 operand address addressing .................................... ............................................................ .... 69 3.4.1 impli ed addre ssing ...................................................................................................... .......................69 3.4.2 regist er addre ssing ..................................................................................................... ......................70 3.4.3 direct addre ssing ....................................................................................................... ........................71 3.4.4 short di rect addr essing ................................................................................................. .....................72 3.4.5 special function register (sfr ) addres sing.............................................................................. ..........73 3.4.6 register i ndirect addr essi ng............................................................................................ ...................74 3.4.7 based addre ssing ........................................................................................................ ......................75 3.4.8 based in dexed addr essing................................................................................................ .................76 3.4.9 stack addre ssing........................................................................................................ ........................77 chapter 4 memory bank select function ( pd78f0892, 78f0893 only) .................. 78 4.1 memory bank............................................................................................................... ................. 78 4.2 difference in repr esentation of memory space ....................................................................... 79 4.3 memory bank select register (bank)....................................................................................... 8 0 4.4 selecting memory bank..................................................................................................... .......... 81 4.4.1 referencing val ues between me mory banks ................................................................................. ....81 4.4.2 branching instruct ion between me mory banks.............................................................................. .....83 4.4.3 subroutine call bet ween memory banks .................................................................................... ........85 4.4.4 instruction branch to bank area by inte rrupt............................................................................ ...........87 chapter 5 port functions ................................................................................................... ........ 89 5.1 port functions ............................................................................................................ .................. 89 5.2 port configuration ........................................................................................................ ............... 90 5.2.1 po rt 0 .................................................................................................................. ...............................91 5.2.2 po rt 1 .................................................................................................................. ...............................93 5.2.3 po rt 3 .................................................................................................................. ...............................96 5.2.4 po rt 4 .................................................................................................................. ...............................98 5.2.5 po rt 5 .................................................................................................................. ...............................99 5.2.6 po rt 6 .................................................................................................................. .............................100 5.2.7 po rt 7 .................................................................................................................. .............................102 5.2.8 po rt 8 .................................................................................................................. .............................107 5.2.9 po rt 9 .................................................................................................................. .............................108 5.2.10 po rt 12 ................................................................................................................ ...........................109 5.2.11 po rt 13 ................................................................................................................ ...........................112 5.3 registers controlling port functi on ....................................................................................... . 115 5.4 port function operations.................................................................................................. ........ 122 5.4.1 writi ng to i/o port ..................................................................................................... ........................122 5.4.2 reading from i/o port................................................................................................... ....................122 5.4.3 operatio ns on i/o port.................................................................................................. ....................122 5.5 cautions on 1-bit manipulation in struction for port register n (pn) .................................... 123 chapter 6 clock generator .................................................................................................. .. 124 6.1 functions of clock generator.................................... .......................................................... ..... 124 user?s manual u17553ej4v0ud 10 6.2 configuration of clock gene rator .......................................................................................... .. 125 6.3 registers controlling clock generator.......................... .......................................................... 1 27 6.4 system clock oscillator ................................................................................................... ......... 136 6.4.1 x1 oscill ator........................................................................................................... ...........................136 6.4.2 xt1 oscilla tor.......................................................................................................... ..........................136 6.4.3 when subsystem clock is not us ed ........................................................................................ ..........139 6.4.4 internal hi gh-speed os cillator.......................................................................................... ..................139 6.4.5 internal lo w-speed os cillator ........................................................................................... ..................139 6.4.6 pr escaler ............................................................................................................... ...........................139 6.5 clock generator operation ................................................................................................. ...... 140 6.6 controlling clock......................................................................................................... ............... 144 6.6.1 controlling hi gh-speed system clock ..................................................................................... ...........144 6.6.2 example of controlling intern al high-speed osc illation clock ............................................................ .147 6.6.3 example of cont rolling subsyst em clock.................................................................................. .........149 6.6.4 controlling internal low-speed oscillati on cloc k ........................................................................ ........151 6.6.5 clocks supplied to cp u and periphera l hardw are .......................................................................... ..151 6.6.6 cpu clock stat us transiti on diagr am..................................................................................... ............152 6.6.7 condition before changing cpu clock and processi ng after changing cpu cl ock ...........................157 6.6.8 time required for switchover of cpu clock and main system cl ock .................................................158 6.6.9 conditions before clock osc illation is stopp ed .......................................................................... ........159 chapter 7 16-bit timer/event counters 00 to 03 ........................................................... 160 7.1 functions of 16-bit timer/event counters 00 to 03................................................................ 160 7.2 configuration of 16-bit timer/ event counters 00 to 03 .............. ........................................... 161 7.3 registers controlling 16-bit ti mer/event counters 00 to 03........ ......................................... 170 7.4 operation of 16-bit timer/event counters 00 to 03 ................................................................ 191 7.4.1 interval timer oper ation................................................................................................ .....................191 7.4.2 ppg out put operat ions ................................................................................................... ..................194 7.4.3 pulse width m easurement operati ons ...................................................................................... ........197 7.4.4 external event counter operatio n........................................................................................ ..............205 7.4.5 square-wave output op eration ............................................................................................ .............208 7.4.6 one-shot pul se output operatio n ......................................................................................... .............210 7.5 special use of tm0n ....................................................................................................... ........... 215 7.5.1 rewriting cr01n during tm0n operatio n ................................................................................... ......215 7.5.2 setting l vs0n and lvr0n ................................................................................................. ..............215 7.6 cautions for 16-bit timer/event counters 00 to 03 ................................................................ 217 chapter 8 8-bit timer/event counters 50 and 51........................................................... 221 8.1 functions of 8-bit timer/event counters 50 and 51............................................................... 221 8.2 configuration of 8-bit timer/ event counters 50 and 51 ........................................................ 223 8.3 registers controlling 8-bit time r/event counters 50 and 51................................................ 225 8.4 operations of 8-bit timer/e vent counters 50 and 51 .................. ........................................... 230 8.4.1 operation as interval timer ............................................................................................. ..................230 8.4.2 operation as ex ternal event count er ..................................................................................... ...........232 8.4.3 square-wave output op eration ............................................................................................ .............233 8.4.4 pwm out put operat ion.................................................................................................... ..................234 8.5 cautions for 8-bit timer/even t counters 50 and 51 .................... ........................................... 238 user?s manual u17553ej4v0ud 11 chapter 9 8-bit timers h0 and h1 ........................................................................................ .. 239 9.1 functions of 8-bit timers h0 and h1 ........................ ............................................................... 239 9.2 configuration of 8-bit timers h0 and h1.................. ............................................................... 23 9 9.3 registers controlling 8-bit timers h0 and h1 ......... ............................................................... 243 9.4 operation of 8-bit timers h0 and h1 ........................ ............................................................... 248 9.4.1 operation as interv al timer/squar e-wave output .......................................................................... .....248 9.4.2 operation as pwm output mode ............................................................................................ ..........251 9.4.3 carrier generator mode oper ation (8-bit ti mer h1 only).................................................................. ..257 chapter 10 watch timer ..................................................................................................... ........ 264 10.1 functions of watch timer ................................................................................................. ...... 264 10.2 configuration of watch time r............................................................................................. .... 265 10.3 register controlling watch timer......................................................................................... . 266 10.4 watch timer operations................................................................................................... ....... 268 10.4.1 watch ti mer operat ion .................................................................................................. ..................268 10.4.2 interval timer oper ation ............................................................................................... ...................269 10.5 cautions for watch timer ................................................................................................. ...... 270 chapter 11 watchdog timer .................................................................................................. ... 271 11.1 functions of watchdog timer .................................. ............................................................ .. 271 11.2 configuration of watchdog time r.......................................................................................... 272 11.3 register controlling watchdog time r ................................................................................... 273 11.4 operation of watchdog timer................................... ........................................................... ... 274 11.4.1 controlling oper ation of wa tchdog ti mer................................................................................ .........274 11.4.2 setting overflow time of wa tchdog ti mer................................................................................ .........276 11.4.3 setting window open pe riod of watc hdog ti mer ........................................................................... ...277 chapter 12 clock output/buzzer output controller............................................... 279 12.1 functions of clock output/buzze r output controller....................... ................................... 279 12.2 configuration of clock output /buzzer output controller ................................................... 280 12.3 register controlling clock output/buzzer output controller............................................. 280 12.4 clock output/buzzer output cont roller operations............................................................. 283 12.4.1 clock out put operat ion ................................................................................................. ..................283 12.4.2 operation as buzzer output ............................................................................................. ...............283 chapter 13 a/d converter ................................................................................................... ...... 284 13.1 function of a/d converter .................................... ............................................................ ...... 284 13.2 configuration of a/d converter ........................................................................................... ... 285 13.3 registers used in a/d converter .......................................................................................... . 287 13.4 a/d converter operations ................................................................................................. ...... 295 13.4.1 basic operations of a/d c onverter...................................................................................... ............295 13.4.2 input voltage and conversion results................................................................................... ...........297 13.4.3 a/d converte r operati on mode ........................................................................................... ............298 13.5 how to read a/d converter characteristics table .............................................................. 300 13.6 cautions for a/d converter............................................................................................... ...... 302 chapter 14 serial interfaces uart60 and uart61.......................................................... 306 14.1 functions of serial interfaces uart60 and uart61 ........................ ................................... 306 user?s manual u17553ej4v0ud 12 14.2 configurations of serial interface uart60 and uart61..................................................... 311 14.3 registers controlling serial interfaces uart 60 and uart61 ............................................ 315 14.4 operations of serial interface uart60 and uart 61............................................................ 334 14.4.1 operat ion stop mode.................................................................................................... ..................334 14.4.2 asynchronous serial interface (u art) mode .............................................................................. ...335 14.4.3 dedicated ba ud rate g enerat or.......................................................................................... .............350 chapter 15 serial interfaces csi10 and csi11 ................................................................ 356 15.1 functions of serial interfaces csi10 and csi11 ................................................................... 356 15.2 configuration of serial interf aces csi10 and csi11 ............................................................. 357 15.3 registers controlling serial interfaces csi10 a nd csi11 .................................................... 359 15.4 operation of serial interfaces csi10 and csi11... ................................................................. 364 15.4.1 operat ion stop mode.................................................................................................... ..................364 15.4.2 3-wire se rial i/o mode ................................................................................................. ...................365 chapter 16 can controller .................................................................................................. ... 377 16.1 outline description ...................................................................................................... ............ 377 16.1.1 f eatures ............................................................................................................... ..........................377 16.1.2 overview of f uncti ons .................................................................................................. ...................378 16.1.3 conf iguration .......................................................................................................... ........................379 16.2 can protocol ............................................................................................................. ............... 380 16.2.1 fram e forma t........................................................................................................... .......................380 16.2.2 fr ame ty pes ............................................................................................................ .......................381 16.2.3 data frame and remote frame ............................................................................................ ............381 16.2.4 erro r frame ............................................................................................................ .........................389 16.2.5 over load fr ame......................................................................................................... ......................390 16.3 functions ................................................................................................................ .................. 391 16.3.1 determinin g bus pr iority ............................................................................................... ..................391 16.3.2 bit stuffi ng ........................................................................................................... ...........................391 16.3.3 mult i masters .......................................................................................................... ........................391 16.3.4 mu lti cast ............................................................................................................. ...........................391 16.3.5 can sleep mode/ca n stop mode function .................................................................................. ..391 16.3.6 error c ontrol f unction ................................................................................................. .....................392 16.3.7 baud rate control fu nction ............................................................................................. .................398 16.4 connection with target system................................ ............................................................ .. 402 16.5 internal registers of can controller..................... ................................................................ . 403 16.5.1 can controlle r configuration........................................................................................... ................403 16.5.2 register access type ................................................................................................... ...................404 16.5.3 register bi t configuration............................................................................................. ...................413 16.6 bit set/clear function................................................................................................... ........... 417 16.7 control registers ........................................................................................................ ............. 419 16.8 can controller initializat ion............................................................................................ ........ 454 16.8.1 initializati on of can module ........................................................................................... ................454 16.8.2 initializati on of messa ge buffe r ....................................................................................... ................454 16.8.3 redefinition of message buffer......................................................................................... ..............454 16.8.4 transition from initia lization mode to operation mode .................................................................. ..455 16.8.5 resetting error count er c0erc of can m odule ............................................................................ 456 16.9 message reception ........................................................................................................ .......... 457 user?s manual u17553ej4v0ud 13 16.9.1 message recept ion...................................................................................................... ...................457 16.9.2 receiv e data read ...................................................................................................... ..................458 16.9.3 receive hist ory list fu nction.......................................................................................... ..................459 16.9.4 mask function .......................................................................................................... .......................461 16.9.5 multi buffer re ceive block functi on .................................................................................... ..............463 16.9.6 remote fr ame rec eption................................................................................................. ................464 16.10 message transmission.................................................................................................... ...... 465 16.10.1 message transmi ssion .................................................................................................. ...............465 16.10.2 transmit hist ory list f unction........................................................................................ .................467 16.10.3 automatic blo ck transmissi on (abt) .................................................................................... ........469 16.10.4 transmission abort process ............................................................................................ .............470 16.10.5 remote fr ame trans mission ............................................................................................. ............471 16.11 power save modes........................................................................................................ ......... 472 16.11.1 can sleep m ode ........................................................................................................ ..................472 16.11.2 can stop m ode......................................................................................................... ...................474 16.11.3 example of usi ng power savi ng modes................................................................................... .....475 16.12 interrupt function ...................................................................................................... ............ 476 16.13 diagnosis functions and special operational mode s ....................................................... 477 16.13.1 receiv e-only mode ..................................................................................................... .................477 16.13.2 single- shot mode ...................................................................................................... ...................478 16.13.3 self -test mode ........................................................................................................ ......................479 16.13.4 receive/transmit o peration in each operation mode ................................................................480 16.14 time stamp function..................................................................................................... ........ 481 16.14.1 time st amp func tion................................................................................................... ..................481 16.15 baud rate settings ...................................................................................................... .......... 483 16.15.1 baud ra te se ttings .................................................................................................... ....................483 16.15.2 representat ive examples of baud rate setti ngs ......................................................................... ..487 16.16 operation of can controller.................................. ........................................................... .... 491 chapter 17 interrupt functions ............................................................................................ 5 17 17.1 interrupt function types........................................... ...................................................... ........ 517 17.2 interrupt sources and configuration ..................................................................................... 5 17 17.3 registers controlling interrupt functions ............. ............................................................... 521 17.4 interrupt servicing operati ons ........................................................................................... .... 529 17.4.1 maskable interr upt acknow ledgement..................................................................................... .......529 17.4.2 software interrupt request acknow ledgement ............................................................................. ...531 17.4.3 multiple in terrupt se rvicing ........................................................................................... ..................532 17.4.4 interrupt request hold ................................................................................................. ....................535 chapter 18 standby function ................................................................................................ .. 536 18.1 standby function and conf iguration..................................................................................... 53 6 18.1.1 standby func tion ....................................................................................................... .....................536 18.1.2 registers contro lling standby function................................................................................. ...........536 18.2 standby function operation..................................... .......................................................... .... 539 18.2.1 ha lt m ode .............................................................................................................. ......................539 18.2.2 st op m ode .............................................................................................................. .....................545 user?s manual u17553ej4v0ud 14 chapter 19 reset function.................................................................................................. ...... 552 19.1 register for confirming reset source ......................... .......................................................... 56 0 chapter 20 multiplier/divider ............................................................................................... .... 561 20.1 functions of multiplier/d ivider.......................................................................................... ...... 561 20.2 configuration of multiplier/ divider ...................................................................................... ... 561 20.3 register controlling multiplier/divider .................... .............................................................. 565 20.4 operations of multiplier/di vider......................................................................................... ..... 566 20.4.1 multiplica tion oper ation............................................................................................... ....................566 20.4.2 divisio n operat ion..................................................................................................... ......................568 chapter 21 power-on-clear circuit...................................................................................... 570 21.1 functions of power-on-clear circuit........................ .............................................................. 570 21.2 configuration of power-on-clea r circuit ............................................................................... 571 21.3 operation of power-on-clear circuit ........................ .............................................................. 571 21.4 cautions for power-on-clear circuit ........................ .............................................................. 574 chapter 22 low-voltage detector ....................................................................................... 576 22.1 functions of low-voltage detector.......................... .............................................................. 576 22.2 configuration of low-voltage detector ................................................................................. 577 22.3 registers controlling low-voltage detector............... .......................................................... 577 22.4 operation of low-voltage detector .......................... .............................................................. 580 22.4.1 when us ed as re set ..................................................................................................... ..................581 22.4.2 when used as interrupt ................................................................................................. .................586 22.5 cautions for low-voltage detector .......................... .............................................................. 591 chapter 23 option byte..................................................................................................... .......... 594 23.1 functions of option by tes ................................................................................................ ...... 594 23.2 format of option byte .................................................................................................... ......... 596 chapter 24 flash memory .................................................................................................... ...... 599 24.1 internal memory size switching register................ .............................................................. 599 24.2 internal expansion ram size switching register ................................................................ 600 24.3 writing with flash memory programmer ............................................................................... 601 24.4 programming environment .................................................................................................. ... 604 24.5 communication mode....................................................................................................... ....... 604 24.6 connection of pins on board.............................................................................................. .... 606 24.6.1 fl md0 pin.............................................................................................................. ........................606 24.6.2 serial interfac e pins.................................................................................................. ......................606 24.6.3 r eset pin.............................................................................................................. ........................608 24.6.4 po rt pins .............................................................................................................. ...........................608 24.6.5 re gc pin ............................................................................................................... ........................608 24.6.6 other signal pins ...................................................................................................... ......................608 24.6.7 powe r suppl y........................................................................................................... .......................609 24.7 programming method ....................................................................................................... ....... 610 24.7.1 controlli ng flash memory............................................................................................... .................610 24.7.2 flash memory programmi ng mode.......................................................................................... .......610 user?s manual u17553ej4v0ud 15 24.7.3 selecting communicati on mode ........................................................................................... ..........611 24.7.4 communi cation co mmands................................................................................................. ...........612 24.8 security settings........................................................................................................ .............. 613 24.9 processing time for each command when pg-f p4 is used (reference) ........................ 615 24.10 flash memory programming by self-programming.. ......................................................... 616 24.10.1 registers used for se lf-programming func tion.......................................................................... ....623 24.11 boot swap function ...................................................................................................... ........ 627 chapter 25 on-chip debug function ..................................................................................... 629 25.1 outline of functions ..................................................................................................... ........... 629 25.2 connection with minicube ................................................................................................. ... 630 25.3 connection circuit examples ................................... ........................................................... ... 631 25.4 on-chip debug security id ................................................................................................ ..... 633 25.5 restrictions and cautions on on-chip debug function .................. ................................... 633 chapter 26 instruction set ................................................................................................. ..... 634 26.1 conventions used in operation list........................ .............................................................. 6 34 26.1.1 operand identifiers and specificat ion me thods .......................................................................... ....634 26.1.2 description of operation column........................................................................................ .............635 26.1.3 description of flag operati on colu mn ................................................................................... ...........635 26.2 operation list ........................................................................................................... ................ 636 26.3 instructions listed by addressing type ................ ............................................................... 644 chapter 27 electrical specifications ((a) grade products).................................. 647 27.1 absolute maximum ratings ................................................................................................. ... 647 27.2 oscillator characteristics...................................... ......................................................... ......... 649 27.3 dc characteristics ....................................................................................................... ............ 651 27.4 ac characteristics ....................................................................................................... ............ 658 27.5 data retention characteristics................................ ........................................................... .... 668 27.6 flash eeprom programming characteristics.......... ............................................................ 669 chapter 28 electrical specifications ((a2) grade products)................................ 670 28.1 absolute maximum ratings ................................................................................................. ... 670 28.2 oscillator characteristics...................................... ......................................................... ......... 672 28.3 dc characteristics ....................................................................................................... ............ 674 28.4 ac characteristics ....................................................................................................... ............ 680 28.5 data retention characteristics................................ ........................................................... .... 690 28.6 flash eeprom programming characteristics.......... ............................................................ 691 chapter 29 package drawings................................................................................................ 692 chapter 30 recommended soldering conditions........................................................... 694 chapter 31 cautions for wait .............................................................................................. .. 695 31.1 cautions for wait ........................................................................................................ ............. 695 31.2 peripheral hardware that generate s wait ............................................................................ 696 31.3 example of wait occurrence ............................................................................................... ... 698 user?s manual u17553ej4v0ud 16 appendix a development tools............................................................................................... 699 a.1 software package .......................................................................................................... ............ 703 a.2 language processing software ....................................... ....................................................... . 703 a.3 control software .......................................................................................................... .............. 704 a.4 flash memory programming tools.......................................................................................... 70 5 a.4.1 when using flash memory programmer fg-fp4, fl-pr4, pg-f pl3, and fp -lite3 ......................705 a.4.2 when using on-chip debug emulator with programm ing function qb-mini2....................................705 a.5 debugging tools (hardware)............................................ .................................................... .... 706 a.5.1 when using in-circu it emulator qb-78k0fx2............................................................................... ....706 a.5.2 when using on-chip de bug emulator qb -78k0min i ........................................................................706 a.5.3 when using on-chip debug emulator with programm ing function qb-mini2....................................707 a.6 debugging tools (software)................................................ ................................................ ..... 707 appendix b notes on target system design ................................................................... 708 appendix c register index .................................................................................................. ....... 710 c.1 register index (in alphabetical order with respect to register names) ............................ 710 c.2 register index (in alphabetical order with respect to register symbol)........................... 715 appendix d revision history ................................................................................................ ..... 720 d.1 main revisions in this edition................................. ........................................................... ...... 720 d.2 revision history of preceding editions .................... .............................................................. 72 1 user?s manual u17553ej4v0ud 17 chapter 1 outline 1.1 features { minimum instruction execution time can be changed from high speed (0.1 s: @ 20 mhz operation with high- speed system clock) to ultra low-speed (122 s: @ 32.768 khz operation with subsystem clock) { general-purpose register: 8 bits 32 registers (8 bits 8 registers 4 banks) { rom, ram capacities data memory item part number program memory (rom) internal high-speed ram note internal expansion ram note pd78f0891 flash memory note 60 kb 1024 bytes 2048 bytes pd78f0892 96 kb 4096 bytes pd78f0893 128 kb 6144 bytes note the internal flash memory, internal high-speed ra m capacities, and internal expansion ram capacities can be changed using the internal memory size swit ching register (ims) and the internal expansion ram size switching register (ixs). { on-chip single-power-supply flash memory { self-programming (with boot swap function) { on-chip debug function { on-chip power-on-clear (poc) circuit and low-voltage detector (lvi) { short startup is possible via the cpu default star t using the on-chip internal high-speed oscillator { on-chip watchdog timer (operable with on-chip internal low-speed oscillator clock) { on-chip multiplier/divider { on-chip clock output/buzzer output controller { i/o ports: 71 (n-ch open drain: 4) { timer: 10 channels { serial interface: 4 channels (uart (lin (local interconnect network)-bus supported): 1 channel, csi/uart note : 1 channel, csi: 1 channel, can: 1 channel) { 10-bit resolution a/d converter: 16 channels { supply voltage: v dd = 4.0 to 5.5 v when 20 mhz, v dd = 2.7 to 5.5 v when 10 mhz, v dd = 1.8 to 5.5 v when 5 mhz (with internal high-speed oscillator clock or subsystem clock: v dd = 1.8 to 5.5 v) { operating ambient temperature: t a = ? 40 to +85 c, ? 40 to +125 c note select either of the functions of these alternate-function pins. chapter 1 outline user?s manual u17553ej4v0ud 18 1.2 applications { automotive electrical appliances (body c ontrol, door control, front light control) { industrial equipment (industria l robot, building control) 1.3 ordering information ? flash memory version part number package quality grade pd78f0891gc(a)-gad-ax 80-pin pl astic lqfp (14x14) special pd78f0891gc(a2)-gad-ax 80-pin pl astic lqfp (14x14) special pd78f0891gk(a)-gak-ax 80-pin plastic lq fp (fine pitch) (12x12) special pd78f0891gk(a2)-gak-ax 80-pin plastic lq fp (fine pitch) (12x12) special pd78f0892gc(a)-gad-ax 80-pin pl astic lqfp (14x14) special pd78f0892gc(a2)-gad-ax 80-pin pl astic lqfp (14x14) special pd78f0892gk(a)-gak-ax 80-pin plastic lq fp (fine pitch) (12x12) special pd78f0892gk(a2)-gak-ax 80-pin plastic lq fp (fine pitch) (12x12) special pd78f0893gc(a)-gad-ax 80-pin pl astic lqfp (14x14) special pd78f0893gc(a2)-gad-ax 80-pin pl astic lqfp (14x14) special pd78f0893gk(a)-gak-ax 80-pin plastic lq fp (fine pitch) (12x12) special pd78f0893gk(a2)-gak-ax 80-pin plastic lq fp (fine pitch) (12x12) special remark all these products are lead free products. chapter 1 outline user?s manual u17553ej4v0ud 19 1.4 pin configuration (top view) ? 80-pin plastic lqfp (14x14) ? 80-pin plastic lqfp (fine pitch)(12x12) p120/intp0/exlvi p47 p46 p45 p44 p43 p42 p41 p40 reset p124/xt2/exclks p123/xt1 flmd0 p122/x2/exclk p121/x1 regc v ss ev ss v dd ev dd av ss av ref p57 p56 p55 p54 p10/sck10/t x d61 p11/si10/r x d61 p12/so10 p13/t x d60 p14/r x d60 p15/toh0 p16/toh1/intp5 p17/ti50/to50 p30/intp1 p53 p52 p51 p50 p31/ti002/intp2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p60 p61 p62 p63 p33/ti51/to51/intp4 p64 p65 p66 p67 p130 p76/sck11 p75/si11 p74/so11 p73/buz/intp7 p72/pcl/intp6 p71/crxd p70/ctxd p06/ti011/to01 p05/ssi11/ti001 p32/ti012/to02/intp3 p131/ti003 p132/ti013/to03 p00/ti000 p01/ti010/to00 p80/ani0 p81/ani1 p82/ani2 p83/ani3 p84/ani4 p85/ani5 p86/ani6 p87/ani7 p90/ani8 p91/ani9 p92/ani10 p93/ani11 p94/ani12 p95/ani13 p96/ani14 p97/ani15 cautions 1. make av ss and ev ss the same potential as v ss . 2. make ev dd the same potential as v dd . 3. connect the regc pin to v ss via a capacitor (0.47 to 1 f: recommended). 4. ani0/p80 to ani15/p97 are set in the analog input mode after release of reset. chapter 1 outline user?s manual u17553ej4v0ud 20 pin identification ani0 to ani15: analog input av ref : analog reference voltage av ss : analog ground buz: buzzer output crxd: receive data for can ctxd: transmit data for can ev dd : power supply for port ev ss : ground for port exclk: external clock input (main system clock) exclks: external clock input (subsystem clock) exlvi: external potential input for low-voltage detector flmd0: flash programming mode intp0 to intp7: external interrupt input p00, p01, p05, p06 : port 0 p10 to p17: port 1 p30 to p33: port 3 p40 to p47: port 4 p50 to p57: port 5 p60 to p67: port 6 p70 to p76: port 7 p80 to p87: port 8 p90 to p97: port 9 p120 to p124: port 12 p130 to p132: port 13 pcl: programmable clock output regc: regulator capacitance reset: reset rxd60, rxd61: receive data sck10, sck11: serial clock input/output si10, si11: serial data input so10, so11: serial data output ssi11: serial interface chip select input ti000, ti010, ti001, ti011, ti002, ti012, ti003, ti013, ti50, ti51: timer input to00, to01, to02, to03 to50, to51, toh0, toh1: timer output txd60, txd61: transmit data v dd : power supply v ss : ground x1, x2: crystal oscillator (high-speed system clock) xt1, xt2: crystal oscillator (subsystem clock) chapter 1 outline user?s manual u17553ej4v0ud 21 1.5 fx2 series lineup 1.5.1 78k0/fx2 product lineup ? 80-pin lqfp (12 12 mm 0.5 mm pitch, 14 14 mm 0.65 mm pitch) single-power-supply flash memory: 60 kb, ram: 3 kb 78k0/ff2 pd78f0891 ? 44-pin lqfp (10 10 mm 0.8 mm pitch) pd78f0881 single-power-supply flash memory: 32 kb, ram: 2 kb single-power-supply flash memory: 48 kb, ram: 3 kb pd78f0882 single-power-supply flash memory: 60kb, ram: 3 kb 78k0/fc2 pd78f0883 pd78f0887 ? 64-pin lqfp (10 10 mm 0.5 mm pitch, 12 12 mm 0.65 mm pitch) 78k0/fe2 pd78f0888 single-power-supply flash memory: 60 kb, ram: 3 kb single-power-supply flash memory: 48 kb, ram: 3 kb ? 48-pin lqfp (7 7 mm 0.5 mm pitch) pd78f0884 single-power-supply flash memory: 32 kb, ram: 2 kb single-power-supply flash memory: 48 kb, ram: 3 kb pd78f0885 single-power-supply flash memory: 60kb, ram: 3 kb 78k0/fc2 pd78f0886 single-power-supply flash memory: 96 kb, ram: 5 kb pd78f0892 single-power-supply flash memory: 128 kb, ram: 7 kb pd78f0893 single-power-supply flash memory: 96 kb, ram: 5 kb pd78f0889 single-power-supply flash memory: 128 kb, ram: 7 kb pd78f0890 remark all product with on-chip debug function. chapter 1 outline user?s manual u17553ej4v0ud 22 the list of functions in the 78k0/fx2 is shown below. part number item 78k0/fc2 78k0/fe2 78k0/ff2 number of pins 44 pins 48 pins 64 pins 80 pins flash memory 32 k/48 k/60 k 48 k/60 k/96 k/128 k 60 k/96 k/128 k internal memory (bytes) ram 2 k/3 k/3 k 3 k/3 k/5 k/7 k 3 k/5 k/7 k power supply voltage v dd = 4.0 to 5.5 v when 20 mhz, v dd = 2.7 to 5.5 v when 10 mhz, v dd = 1.8 to 5.5 v when 5 mhz minimum instruction execution time 0.1 s (when 20 mhz, v dd = 4.0 to 5.5 v) crystal/ceramic 4 to 20 mhz subclock 32.768 khz internal low-speed oscillator 240 khz (typ.) clock internal high-speed oscillator 8 mhz (typ., v dd = 2.7 to 5.5 v) cmos i/o 33 36 50 66 cmos output 1 ports n-ch open-drain i/o 3 4 16 bits (tm0) 2 ch note 4 ch 8 bits (tm5) 2 ch 8 bits (tmh) 2 ch for watch 1 ch timer wdt 1 ch can 1 ch 3-wire csi ? 1 ch lin-uart 1 ch serial interface lin-uart/csi 1 ch 10-bit a/d converter 8 ch 9 ch 12 ch 16 ch external 8 interrupts internal 24 29 reset pin provided poc 1.59 v 0.15 v (detection voltage is fixed) lvi 4.24/4.09/3.93/3.78/3.62/3.47/3.32/3.16/3.01/2.85/2.70/2.55/2.39/2.24/2.08/1.93 v (selectable by software) reset wdt provided multiplier/divider provided clock output/buzzer output provided self-programming function provided on-chip debug function provided standby function halt/stop mode operating ambient temperature t a = ? 40 to +85 c, ? 40 to +125 c note since tm01 does not have the following terminal at 78k0/fc2, the function is restricted in part. pd78f0881, 78f0882, and 78f 0883: ti001, ti011, to01 pd78f0884, 78f0885, and 78f0886: ti001 chapter 1 outline user?s manual u17553ej4v0ud 23 1.6 block diagram port 0 p00.p01,p05, p06 4 port 3 p30 to p33 4 internal high-speed ram v ss , ev ss flmd0 v dd , ev dd port 1 p10 to p17 8 multiplier/divider reset control port 4 p40 to p47 8 port 6 p60 to p67 8 port 7 p70 to p76 7 port 8 p80 to p87 8 port 9 p90 to p97 8 port 12 p120 to p124 5 port 5 p50 to p57 8 port 13 p131, p132 2 buzzer output buz/p73 system control reset x1/p121 x2/exclk/p122 xt1/p123 xt2/exclks/p124 exlvi/p120 clock output control pcl/p72 power on clear/ low voltage indicator poc/lvi control internal expansion ram 16-bit timer/ event counter 00 to00/ti010/p01 ti000/p00 (linsel) serial interface csi10 si10/p11 so10/p12 sck10/p10 ani0/p80 to ani7/p87 ani8/p90 to ani15/p97 interrupt control 8-bit timer h0 toh0/p15 8-bit timer h1 toh1/p16 ti50/to50/p17 8-bit timer/ event counter 50 16 a/d converter rxd60/p14 rxd60/p14 (linsel) txd60/p13 serial interface uart60 watchdog timer rxd61/p11 txd61/p10 serial interface uart61 av ref av ss intp1/p30 to intp4/p33 4 intp0/p120 (linsel) 16-bit timer/ event counter 01 to01/ti011/p06 ti001/p05 ti51/to51/p33 8-bit timer/ event counter 51 internal low-speed oscillator watch timer serial interface csi11 ssi11/p05 so11/p73 si11/p74 sck11/p75 intp5/p16 intp6/p72 intp7/p73 2 78k/0 cpu core flash memory on-chip debugger crxd/p71 ctxd/p70 can p130 rxd60/p14 (linsel) 16-bit timer/ event counter 02 to02/ti012/p32 ti002/p31 16-bit timer/ event counter 03 to03/ti013/p132 ti003/p131 linsel internal high-speed oscillator bank chapter 1 outline user?s manual u17553ej4v0ud 24 1.7 outline of functions (1/2) item pd78f0891 pd78f0892 pd78f0893 flash memory (self-programming supported) note 60 k 96 k 128 k bank ? 4 6 high-speed ram note 1 k internal memory (bytes) expansion ram note 2 k 4 k 6 k memory space 64 kb high-speed system clock (oscillation frequency) crystal/ceramic oscillation (x 1 ), external main syst em clock input (exclk) 4 to 20 mhz: v dd = 4.0 to 5.5 v, 4 to 10 mhz: v dd = 2.7 to 5.5 v, 4 to 5 mhz: v dd = 1.8 to 5.5 v internal high-speed oscillation clock (oscillation frequency) on-chip intaernal oscillation (8 mhz (typ.): v dd = 2.7 to 5.5 v) internal low-speed oscillation clock (oscillation frequency) on-chip internal osc illation (240 khz (typ.)) subsystem clock (oscillation frequency) crystal oscillation (xt1), external subsystem clock input (exclks) (32.768 khz: v dd = 1.8 to 5.5 v) general-purpose registers 8 bits 32 registers (8 bits 8 registers 4 banks) 0.1 s/0.2 s/0.4 s/0.8 s/1.6 s (high-speed syst em clock: @ f xp = 20 mhz operation) 0.25 s/0.5 s/1.0 s/2.0 s/4.0 s (typ.) (internal oscillator clock: @ f rh = 8 mhz (typ.) operation) minimum instruction execution time 122 s (subsystem clock: when operating at f xt = 32.768 khz) instruction set ? 16-bit operation ? multiply/divide (8 bits 8 bits, 16 bits 8 bits) ? bit manipulate (set, reset, test, and boolean operation) ? bcd adjust, etc. i/o ports total: 71 cmos i/o 66 cmos output 1 n-ch open-drain i/o 4 timers ? 16-bit timer/event counter: 4 channels ? 8-bit timer/event counter: 2 channels ? 8-bit timer: 2 channels ? watch timer 1 channel ? watchdog timer: 1 channel timer outputs 8 (pwm output: 4) clock output ? 78.125 khz, 156.25 khz, 312.5 khz, 625 khz, 1.25 mhz, 2.5 mhz, 5 mhz, 10 mhz (high-speed system clock: 10 mhz) ? 32.768 khz (subsystem clock: 32.768 khz) buzzer output 1.22 khz, 2.44 khz, 4.88 khz, 9.77 khz (high-speed system clock: 10 mhz) a/d converter 10-bit resolution 16 channels note the internal flash memory capacity, internal high-sp eed ram capacity, and internal expansion ram capacity can be changed using the internal memory size switch ing register (ims) and the internal expansion ram size switching register (ixs). chapter 1 outline user?s manual u17553ej4v0ud 25 (2/2) item pd78f0891 pd78f0892 pd78f0893 can 1 ch 3-wire csi 1 ch lin-uart 1 ch serial interface lin-uart/ csi note1 1 ch multiplier/divider ? 16 bit x 16 bit = 32 bit (multiplication) ? 32 bit 32 bit = 32 bit remainder of 16 bits (division) internal 29 vectored interrupt sources external 8 reset ? reset using reset pin ? internal reset by watchdog timer ? internal reset by power-on-clear ? internal reset by low-voltage detector on-chip debug function provided supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = ? 40 to +85 c, ? 40 to +125 c package ? 80-pin plastic lq fp (fine pitch) (12x12) ? 80-pin plastic lqfp(14x14) note select either of the functions of these alternate-function pins. an outline of the timer is shown below. 16-bit timer/ event counters 00 to 03 8-bit timer/ event counters 50 and 51 8-bit timers h0 and h1 tm00 tm01 tm02 tm03 tm50 tm51 tmh0 tmh1 watch timer watchdog timer interval timer 1 ch 1 ch 1 ch 1 ch 1 ch 1 ch 1 ch 1 ch note 1 channel 1 channel operation mode external event counter 1 ch 1 ch 1 ch 1 ch 1 ch 1 ch ? ? ? ? timer output 1 1 1 1 1 1 1 1 ? ? ppg output 1 1 1 1 ? ? ? ? ? ? pwm output ? ? ? ? 1 1 1 1 ? ? pulse width measurement 2 2 2 2 ? ? ? ? ? ? square-wave output 1 1 1 1 1 1 1 1 ? ? function interrupt source 2 2 2 2 1 1 1 1 1 ? note in the watch timer, the watch timer function and in terval timer function can be used simultaneously. remark tm51 and tmh1 can be used in combination as a carrier generator mode. user?s manual u17553ej4v0ud 26 chapter 2 pin functions 2.1 pin function list there are three types of pi n i/o buffer power supplies: av ref , ev dd , and v dd . the relationship between these power supplies and the pins is shown below. table 2-1. pin i/o buffer power supplies power supply corresponding pins av ref p80 to p87, p90 to p97 ev dd port pins other than p80 to p87, p90 to p97 and p121 to p124 v dd ? p121 to p124 ? non-port pins this section explains the names and f unctions of the pins of the 78k0/ff2. (1) port pins table 2-2. port pins (1/2) pin name i/o function after reset alternate function p00 ti000 p01 ti010/to00 p05 ssi11/ti001 p06 i/o port 0. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ti011/to01 p10 sck10/txd61 p11 si10/rxd61 p12 so10 p13 txd60 p14 rxd60 p15 toh0 p16 toh1/intp5 p17 i/o port 1. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ti50/to50 p30 intp1 p31 intp2/ti002 p32 intp3/ti012/to02 p33 i/o port 3. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input intp4/ti51/to51 p40 to p47 i/o port 4. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ? chapter 2 pin functions user?s manual u17553ej4v0ud 27 table 2-2. port pins (2/2) pin name i/o function after reset alternate function p50 to p57 i/o port 5. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ? p60 to p63 n-ch open drain i/o port. p64 to p67 i/o port 6. 8-bit i/o port input/output can be specified in 1-bit units. use of an on-chip pull-up resister can be specified by a software setting input ? p70 ctxd p71 crxd p72 pcl/intp6 p73 buz/intp7 p74 so11 p75 si11 p76 i/o port 7. 7-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input sck11 p80 to p87 i/o port 8. 8-bit i/o port. input/output can be specified in 1-bit units. input ani0 to ani7 p90 to p97 i/o port 9. 8-bit i/o port. input/output can be specified in 1-bit units. input ani8 to ani15 p120 intp0/exlvi p121 x1 p122 x2/exclk p123 xt1 p124 i/o port 12. 5-bit i/o port. only for p120, use of an on-chip pull-up resistor can be specified by a software setting. input xt2/exclks p130 output output p131 p132 i/o port 13. p130 is 1-bit output-only port. p131 and p132 are 2-bit i/o port. p131 and p132 use of an on-chip pull-up resistor can be specified by a software setting. input ? chapter 2 pin functions user?s manual u17553ej4v0ud 28 (2) non-port pins table 2-3. non-port pins (1/2) pin name i/o function after reset alternate function intp0 p120/exlvi intp1 p30 intp2 p31/ti002 intp3 p32/ti012/to02 intp4 p33/ti51/to51 intp5 p16/toh1 intp6 p72/pcl intp7 input external interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input p73/buz si10 p11/rxd61 si11 input serial data input to serial interface input p75 so10 p12 so11 output serial data output from serial interface input p74 sck10 p10/txd61 sck11 i/o clock input/output for serial interface input p76 ssi11 input serial interface chip select input input p05/ti001 rxd60 p14 rxd61 input serial data input to asynch ronous serial interface input p11/si10 txd60 p13 txd61 output serial data output from asyn chronous serial interface input p10/sck10 ti000 external count clock input to 16-bit timer/event counter 00 capture trigger input to captur e registers (cr000, cr010) of 16-bit timer/event counter 00 p00 ti001 external count clock input to 16-bit timer/event counter 01 capture trigger input to captur e registers (cr001, cr011) of 16-bit timer/event counter 01 p05/ssi11 ti002 external count clock input to 16-bit timer/event counter 02 capture trigger input to captur e registers (cr002, cr012) of 16-bit timer/event counter 02 p31/intp2 ti003 external count clock input to 16-bit timer/event counter 03 capture trigger input to captur e registers (cr003, cr013) of 16-bit timer/event counter 03 p131 ti010 capture trigger input to capture register (cr000) of 16-bit timer/event counter 00 p01/to00 ti011 capture trigger input to capture register (cr001) of 16-bit timer/event counter 01 p06/to01 ti012 capture trigger input to capture register (cr002) of 16-bit timer/event counter 02 p32/to02/intp3 ti013 input capture trigger input to capture register (cr003) of 16-bit timer/event counter 03 input p132/to03 to00 16-bit timer/event counter 00 output p01/ti010 to01 16-bit timer/event counter 01 output p06/ti011 to02 output 16-bit timer/event counter 02 output input p32/ti012/intp3 chapter 2 pin functions user?s manual u17553ej4v0ud 29 table 2-3. non-port pins (2/2) pin name i/o function after reset alternate function to03 output 16-bit timer/event counter 03 output input p132/ti013 ti50 external count clock input to 8-bit timer/event counter 50 p17/to50 ti51 input external count clock input to 8-bit timer/event counter 51 input p33/to51/intp4 to50 8-bit timer/event counter 50 output p17/ti50 to51 8-bit timer/event counter 51 output p33/ti51/intp4 toh0 8-bit timer h0 output p15 toh1 output 8-bit timer h1 output input p16/intp5 pcl output clock output (for trimming of high-speed system clock, subsystem clock) input p72/intp6 buz output buzzer output input p73/intp7 ani0 to ani15 input a/d converter analog input input p80 to p87 p90 to p97 ctxd input can transmit data output input p70 crxd output can receive data input input p71 av ref input a/d converter reference voltage input and positive power supply for port 2 ? ? av ss ? a/d converter ground potential. make the same potential as ev ss or v ss . ? ? reset input system reset input ? ? x1 input input p121 x2 ? connecting resonator for hi gh-speed system clock input p122/exclk xt1 input input p123 xt2 ? connecting resonator fo r subsystem clock input p124/exclks exclk input external clock input fo r main system clock input p122/x2 exclks input external clock input for subsystem clock input p124/xt2 exlvi input potential input for external low-voltage detection input p120/intp0 v dd ? positive power suppl y (except for ports) ? ? ev dd ? positive power supply for ports ? ? v ss ? ground potential (except for ports) ? ? ev ss ? ground potential for ports ? ? flmd0 ? flash memory programming mode setting. ? ? regc ? this is the pin for connecting regulator output (2.5 v) stabilization capacitance for internal operation. connect this pin to v ss via a capacitor (0.47 to 1 f: recommended). ? ? chapter 2 pin functions user?s manual u17553ej4v0ud 30 2.2 description of pin functions 2.2.1 p00, p01, p05, p06 (port 0) p00, p01, p05 and p06 function as a 4-bit i/o port. these pi ns also function as timer i/o and serial interface chip select input. the following operation modes can be specified in 1-bit units. (1) port mode p00, p01, p05 and p06 function as 4-bit i/o port. p00, p01, p05 and p06 can be set to input or output in 1-bit units using port mode register 0 (pm0). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (pu0). (2) control mode p00, p01, p05 and p06 function as timer i/o, and serial interface chip select input. (a) ti000, ti001 these are the pins for inputting an external count clo ck to 16-bit timer/event counters 00 and 01 and are also for inputting a capture trigger signal to the captur e registers (cr000, cr010 or cr001, cr011) of 16-bit timer/event counters 00 and 01. (b) ti010, ti011 these are the pins for inputting a capt ure trigger signal to the capture re gister (cr000 or cr001) of 16-bit timer/event counters 00 and 01. (c) to00, to01 these are timer output pins. (d) ssi11 this is the serial interface chip select input pin. chapter 2 pin functions user?s manual u17553ej4v0ud 31 2.2.2 p10 to p17 (port 1) p10 to p17 function as an 8-bit i/o port. t hese pins also function as pins for ex ternal interrupt re quest input, serial interface data i/o, cl ock i/o, and timer i/o. the following operation modes can be specified in 1-bit units. (1) port mode p10 to p17 function as an 8-bit i/o port. p10 to p17 can be set to input or output in 1-bit units using port mode register 1 (pm1). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (pu1). (2) control mode p10 to p17 function as external interrupt request in put, serial interface data i/o, clock i/o, and timer i/o. (a) si10 this is a serial interface serial data input pin. (b) so10 this is a serial interface serial data output pin. (c) sck10 this is a serial interface serial clock i/o pin. (d) rxd60, rxd61 these are the serial data input pins of the asynchronous serial interface. (e) txd60, txd61 these are the serial data output pins of the asynchronous serial interface. (f) ti50 this is the pin for inputting an external c ount clock to 8-bit timer/event counter 50. (g) to50, toh0, and toh1 these are timer output pins. (h) intp5 this is an external interrupt request input pin for whic h the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. chapter 2 pin functions user?s manual u17553ej4v0ud 32 2.2.3 p30 to p33 (port 3) p30 to p33 function as a 4-bit i/o port. these pins also function as pins for external interrupt request input and timer i/o. the following operation modes can be specified in 1-bit units. (1) port mode p30 to p33 function as a 4-bit i/o port. p30 to p33 c an be set to input or output in 1-bit units using port mode register 3 (pm3). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (pu3). (2) control mode p30 to p33 function as external interru pt request input pins and timer i/o pins. (a) intp1 to intp4 these are the external interrupt request input pins fo r which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) ti002 this is the pin for inputting an external count clock to 16-bit timer/event counter 02 and is also for inputting a capture trigger signal to the ca pture registers (cr002, cr012) of 16-bit timer/event counter 02. (c) ti012 this is the pin for inputting a capture trigger signal to the capture register (cr002) of 16-bit timer/event counter 02. (d) to02 this is a timer output pin. (e) ti51 this is an external count clock input pin to 8-bit timer/event counter 51. (f) to51 this is a timer output pin. cautions 1. be sure to pull the p31/ti002/intp2 pin down before a re set release, to prevent malfunction. 2. connect p31/ti002/intp2 as follows when writ ing the flash memory wit h a flash programmer. - p31/ti002/intp2: connect to ev ss via a resistor (10 k : recommended). the above connection is no t necessary when writing the fl ash memory by means of self programming. remark p31/ti002/intp2 and p32/ti012/to02/in tp3 can be used as on-chip debug mode setting pins when the on-chip debug function is used. for details, refer to chapter 25 on-chip debug function . 2.2.4 p40 to p47 (port 4) p40 to p47 function as a 8-bit i/o port. p40 to p47 can be set to input or output in 1-bit units using port mode register 4 (pm4). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (pu4). chapter 2 pin functions user?s manual u17553ej4v0ud 33 2.2.5 p50 to p57 (port 5) p50 to p57 function as a 8-bit i/o port. p50 to p57 can be set to input or output in 1-bit units using port mode register 5 (pm5). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 5 (pu5). 2.2.6 p60 to p67 (port 6) p60 to p67 function as a 8-bit i/o port. p60 to p67 can be set to input port or output por t in 1-bit units using port mode register 6 (pm6). p64 to p67 use of an on-chip pu ll-up resistor can be specifie d by pull-up resistor option register 6 (pu6). p60 to p63 are n-ch open-drain pins. 2.2.7 p70 to p76 (port 7) p70 to p76 function as a 7-bit i/o port. these pins also function as external interrupt request input, clock output pins, buzzer output pins, can i/f i/o, serial interface data i/o and clock i/o. the following operation modes can be specified in 1-bit units. (1) port mode p70 to p76 function as a 7-bit i/o port. p70 to p76 c an be set to input or output in 1-bit units using port mode register 7 (pm7). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (pu7). (2) control mode p70 to p76 function as external in terrupt request input, out put pins, buzzer output pins, can i/f i/o, serial interface data i/o and clock i/o. (a) intp6, intp7 these are the external interrupt request input pins fo r which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) crxd this is the can serial receive data input pin. (c) ctxd this is the can serial transmit data output pin. (d) pcl this is a clock output pin. (e) buz this is a buzzer output pin. (f) si11 this is a serial interface serial data input pin. (g) so11 this is a serial interface serial data output pin. (h) sck11 this is the serial interf ace serial clock i/o pin. chapter 2 pin functions user?s manual u17553ej4v0ud 34 2.2.8 p80 to p87 (port 8) p80 to p87 function as an 8-bit i/o port. these pins also function as pins for a/d converter analog input. the following operation modes can be specified in 1-bit units. (1) port mode p80 to p87 function as an 8-bit i/o port. p80 to p87 can be set to input or output in 1-bit units using port mode register 8 (pm8). (2) control mode p80 to p87 function as a/d converter analog input pins (ani0 to ani7). when using these pins as analog input pins, see (5) p80/ani0 to p87/ani7, p90/ani8 to p97/ani15 in 13.6 cautions for a/d converter . caution p80/ani0 to p87/ani7 is set in the analog input mode after release of reset. 2.2.9 p90 to p97 (port 9) p90 to p97 function as an 8-bit i/o port. these pins also function as pins for a/d converter analog input. the following operation modes can be specified in 1-bit units. (1) port mode p90 to p97 function as an 8-bit i/o port. p90 to p97 can be set to input or output in 1-bit units using port mode register 9 (pm9). (2) control mode p90 to p97 function as a/d converter analog input pins (ani8 to ani15). when using these pins as analog input pins, see (5) p80/ani0 to p87/ani7, p90/ani8 to p97/ani15 in 13.6 cautions for a/d converter . caution p90/ani8 to p97/ani15 is set in the an alog input mode after release of reset. 2.2.10 p120 to p124 (port 12) p120 to p124 function as a 5-bit i/o port. these pins also function as pins for extern al interrupt request input, external clock input for main system cl ock, external clock input for subsyste m clock and potential input for external low-voltage detection. the following operatio n modes can be specified in 1-bit units. (1) port mode p120 to p124 function as a 5-bit i/o port. p120 to p124 ca n be set to input or output using port mode register 12 (pm12). only for p120, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (pu12). (2) control mode p120 to p124 function as pins for external interrupt request input, potential input for external low-voltage detection, resonator connection for main system clock, re sonator connection for subsystem clock, external clock input for main system clock and external clock input for subsystem clock. (a) intp0 this functions as an external interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. chapter 2 pin functions user?s manual u17553ej4v0ud 35 (b) exlvi this is a potential input pin for external low-voltage detection. (c) x1, x2 these are the pins for connecting a re sonator for high-speed system clock. when supplying an external clock, input a signal to t he x1 pin and input the inverse signal to the x2 pin. caution connect p121/x1 as follows when writin g the flash memory with a flash programmer. - p121/x1: when using this pin as a port, connect it to v ss via a resistor (10 k : recommended) (in the input mode) or leave it open (in the output mode). the above connection is not necessary when writing the flash memory by means of self programming. remark the x1 and x2 pins can be used as on-chip debug mode setting pins when the on-chip debug function is used. for details, refer to chapter 25 on-chip debug function . (d) exclk this is an external clock inpu t pin for main system clock. (e) xt1, xt2 these are the pins for connecting a resonator for subsystem clock. when supplying an external clock, input a signal to t he xt1 pin and input the inve rse signal to the xt2 pin. (f) exclks this is an external clock in put pin for subsystem clock. 2.2.11 p130 to p132 (port 13) p130 functions as a 1-bit output-only port. p131 and p132 function as a 2-bit i/o port. these pins also function as pins for timer i/o. the following operatio n modes can be specified in 1-bit units. (1) port mode p131 and p132 can be set to input or output in 1 bit uni ts using port mode register 13 (pm13). p131 and p132 use of an on-chip pull-up resistor can be specified by pull-up resistor option register 13 (pu13). (2) control mode p130, p131 and p132 function as timer i/o and serial interface chip select input. (a) ti003 this is the pin for inputting an external count clock to 16-bit timer/event counter 03 and is also for inputting a capture trigger signal to the ca pture registers (cr003, cr013) of 16-bit timer/event counter 03. (b) ti013 this is the pin for inputting a capture trigger signal to the capture register (cr003) of 16-bit timer/event counter 03. (c) to03 this is a timer output pin. chapter 2 pin functions user?s manual u17553ej4v0ud 36 2.2.12 av ref this is the a/d converter reference voltage input pin. when the a/d converter is not used, connect this pin directly to ev dd or v dd note . note connect port 8 and port 9 directly to ev dd when it is used as a digital port. 2.2.13 av ss this is the a/d converter ground potenti al pin. even when the a/d converter is not used, always use this pin with the same potential as the ev ss pin or v ss pin. 2.2.14 reset this is the active-low system reset input pin. 2.2.15 regc this is the pin for connecting regulator output (2.5 v) st abilization capacitance for internal operation. connect this pin to v ss via a capacitor (0.47 to 1 f: recommended). regc v ss caution keep the wiring length as short as possible for the broken- line part in the above figure. 2.2.16 v dd and ev dd v dd is the positive power supply pin for other than ports. ev dd is the positive power supply pin for ports. 2.2.17 v ss and ev ss v ss is the ground potential pin for other than ports. ev ss is the ground potential pin for ports. 2.2.18 flmd0 this is a pin for setting flash memory programming mode. connect to ev ss or v ss in the normal operation mode. in flash memory programming mode, be sure to connect this pin to the flash programmer. chapter 2 pin functions user?s manual u17553ej4v0ud 37 2.3 pin i/o circuits and recommended connection of unused pins table 2-4 shows the types of pin i/o circuits and the recommended connections of unused pins. refer to figure 2-1 for the configurat ion of the i/o circuit of each type. table 2-4. pin i/o circuit types (1/2) pin name i/o circuit type i/o recommended connection of unused pins p00/ti000 input: independently connect to ev dd or ev ss via a resistor. output: leave open. p01/ti010/to00 p05/ssi11/ti001 p06/ti011/to01 p10/sck10/txd61 p11/si10/rxd61 5-ah p12/so10 p13/txd60 5-h p14/rxd60 5-ah p15/toh0 5-h p16/toh1/intp5 p17/ti50/to50 p30/intp1 p31/ti002/intp2 note p32/ti012/to02/intp3 p33/ti51/to51/intp4 5-ah p40 to p47 p50 to p57 5-h p60 to p63 13-p input: connect to ev ss . output: leave this pin open at low-level output after clearing the output latch of the port to 0. p64 to p67 p70/ctxd 5-h p71/crxd p72/pcl/intp6 p73/buz/intp7 5-ah p74/so11 5-h p75/si11 p76/sck11 5-ah i/o input: independently connect to ev dd or ev ss via a resistor. output: leave open. note connect p31/ti002/intp2 as follows when writing the flash memory with a flash programmer. - p31/ti002/intp2: connect to ev ss via a resistor (10 k : recommended). the above connection is not necessary when writing the flash memory by means of self programming. chapter 2 pin functions user?s manual u17553ej4v0ud 38 table 2-4. pin i/o circuit types (2/2) pin name i/o circuit type i/o recommended connection of unused pins p80/ani0 to p87/ani7 note 1 p90/ani8 to p97/ani15 note 1 11-g i/o chapter 2 pin functions user?s manual u17553ej4v0ud 39 figure 2-1. pin i/o circuit list (1/2) type 3-c type 2 type 5-h type 11-g schmitt-triggered input with hysteresis characteristics in ev dd p-ch n-ch data out vss0 pullup enable output data output disable input enable ev dd p-ch ev dd p-ch in/out n-ch evss data output disable av ref p-ch in/out n-ch p-ch n-ch av ref (threshold voltage) comparator input enable + _ av ss av ss pull-up enable data output disable input enable ev dd p-ch ev dd p-ch in/out n -ch ev ss type 5-ah data output disable in/out n-ch input enable evss type 13-p chapter 2 pin functions user?s manual u17553ej4v0ud 40 figure 2-1. pin i/o circuit list (2/2) data output disable input enable ev dd p-ch x1, xt1 n -ch ev ss reset data output disable input enable ev dd p-ch n -ch ev ss reset p-ch n-ch x2, xt2 type 37 user?s manual u17553ej4v0ud 41 chapter 3 cpu architecture 3.1 memory space products in the 78k0/ff2 can each access a 64 kb memory s pace. figures 3-1 to 3-3 show the memory map. caution regardless of the internal memory capacity, the initial valu es of the internal memory size switching register (ims) and internal expansi on ram size switching register (ixs) of the 78k0/ff2 is fixed (ims = cfh, ixs = 0ch). therefore, set the value corresponding to each product as indicated below. table 3-1. set values of internal memo ry size switching register (ims) and internal expansion ram si ze switching register (ixs) flash memory version ims ixs pd78f0891 cfh 08h pd78f0892 cch note 04h pd78f0893 cch note 00h note the pd78f0892 and pd78f0893 have internal roms of 96 kb and 128 kb, respectively. however, the set val ue of ims of these dev ices is the same as those of the 48 kb produ ct because banks are used. for how to set the banks, see 4.3 memory bank select register (bank) . chapter 3 cpu architecture user?s manual u17553ej4v0ud 42 figure 3-1. memory map ( pd78f0891) ffffh ff00h feffh fee0h fedfh f800h f7ffh f000h efffh 0000h internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits flash memory 61440 8 bits program memory space data memory space internal expansion ram 2048 8 bits ram space in which instruction can be fetched fa00h f9ffh fe20h fe1fh reserved fb00h faffh afcan area (256 8 bits) special function registers (sfr) 256 8 bits ff20h ff1fh short direct addressing note 1 fe10h fe0fh note 2 0190h 018fh 0083h 0082h 0800h 07ffh 1000h 0fffh 0040h 003fh 0000h 0085h 0084h program area efffh program area 0080h 007fh 1085h 1084h 1080h 107fh vector table area 64 8 bits callt table area 64 8 bits program area 1915 8 bits option byte area note 3 5 8 bits callf entry area 2048 8 bits option byte area note 3 5 8 bits 1fffh boot cluster 0 note 4 boot cluster 1 notes 1. during on-chip debugging, use of this area is disabl ed since it is used as the user data backup area for communication. 2. during on-chip debugging, use of this area is dis abled since it is used as the communication command area (269 bytes). 3. when boot swap is not used: set the option bytes to 0080h to 0084h. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h. 4. writing boot cluster 0 can be prohibited depending on the setting of security (see 24.8 security setting ). remark the flash memory is divided into blocks (one block = 1 kb). for the address values and block numbers, see table 3-2 correspondence between address va lues and block numbers in flash memory . block 00h block 01h block 3bh 1 kb efffh 07ffh 0000h 0400h 03ffh ec00h ebffh chapter 3 cpu architecture user?s manual u17553ej4v0ud 43 figure 3-2. memory map ( pd78f0892) 16384 8 bits (bank 1) 16384 8 bits (bank 3) 16384 8 bits (bank 2) internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved reserved flash memory 32768 8 bits (common) flash memory 16384 8 bits (bank 0) program memory space data memory space internal expansion ram 4096 8 bits note 2 ram space in which instruction can be fetched note 1 special function registers (sfr) 256 8 bits short direct addressing afcan area 256 8 bits ffffh ff00h fee0h fedfh f800h f7ffh e800h e7ffh 8000h 7fffh 0000h 0083h 0082h 0190h 018fh c000h bfffh fe10h fe0fh fe20h fe1fh ff20h ff1fh fb00h faffh fa00h f9ffh feffh 0800h 07ffh 1000h 0fffh 0040h 003fh 0000h 0085h 0084h program area 7fffh program area 0080h 007fh 1085h 1084h 1080h 107fh vector table area 64 8 bits callt table area 64 8 bits program area 1915 8 bits option byte area note 3 5 8 bits callf entry area 2048 8 bits option byte area note 3 5 8 bits 1fffh boot cluster 0 note 4 boot cluster 1 notes 1. during on-chip debugging, use of this area is disabl ed since it is used as the user data backup area for communication. 2. during on-chip debugging, use of this area is dis abled since it is used as the communication command area (269 bytes). 3. when boot swap is not used: set the option bytes to 0080h to 0084h. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h. 4. writing boot cluster 0 can be prohibited depending on the setting of security (see 24.8 security setting ). remark the flash memory is divided into blocks (one block = 1 kb). for the address values and block numbers, see table 3-2 correspondence between address va lues and block numbers in flash memory . block 00h block 01h block 1fh block 20h block 2fh 1 kb common area bank area (memory bank 0) block 30h block 3fh (memory bank 1) block 40h block 4fh (memory bank 2) block 50h block 5fh (memory bank 3) bfffh 8000h 7fffh 84ffh 83ffh bc00h bbffh 07ffh 0000h 0400h 03ffh 7c00h 7bffh chapter 3 cpu architecture user?s manual u17553ej4v0ud 44 figure 3-3. memory map ( pd78f0893) 16384 8 bits (bank 1) 16384 8 bits (bank 4) 16384 8 bits (bank 3) 16384 8 bits (bank 5) 16384 8 bits (bank 2) internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved reserved flash memory 32768 8 bits (common) flash memory 16384 8 bits (bank 0) program memory space internal expansion ram 6144 8 bits note 2 note 1 special function registers (sfr) 256 8 bits short direct addressing afcan area 256 8 bits ffffh ff00h feffh fee0h fedfh fb00h faffh f800h f7ffh e000h dfffh 8000h 7fffh 0000h 0083h 0082h 0190h 018fh c000h bfffh fa00h fe10h fe0fh fe20h fe1fh ff20h ff1fh data memory space f9ffh ram space in which instruction can be fetched 0800h 07ffh 1000h 0fffh 0040h 003fh 0000h 0085h 0084h program area 7fffh program area 0080h 007fh 1085h 1084h 1080h 107fh vector table area 64 8 bits callt table area 64 8 bits program area 1915 8 bits option byte area note 3 5 8 bits callf entry area 2048 8 bits option byte area note 3 5 8 bits 1fffh boot cluster 0 note 4 boot cluster 1 notes 1. during on-chip debugging, use of this area is disabl ed since it is used as the user data backup area for communication. 2. during on-chip debugging, use of this area is dis abled since it is used as the communication command area (269 bytes). 3. when boot swap is not used: set the option bytes to 0080h to 0084h. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h. 4. writing boot cluster 0 can be prohibited depending on the setting of security (see 24.8 security setting ). remark the flash memory is divided into blocks (one block = 1 kb). for the address values and block numbers, see table 3-2 correspondence between address va lues and block numbers in flash memory . block 00h block 01h block 1fh block 20h block 2fh 1 kb common area bank area (memory bank 0) block 30h block 3fh (memory bank 1) block 40h block 4fh (memory bank 2) block 70h block 7fh (memory bank 5) . . . bfffh 8000h 7fffh 84ffh 83ffh bc00h bbffh 07ffh 0000h 0400h 03ffh 7c00h 7bffh chapter 3 cpu architecture user?s manual u17553ej4v0ud 45 correspondence between the address values and block numbers in the flash memory are shown below. table 3-2. correspondence betw een address values and block nu mbers in flash memory (1/2) (1) pd78f0891 address value block number address value block number address value block number address value block number 0000h to 03ffh 00h 4000h to 43ffh 10h 8000h to 83ffh 20h c000h to c3ffh 30h 0400h to 07ffh 01h 4400h to 47ffh 11h 8400h to 87ffh 21h c400h to c7ffh 31h 0800h to 0bffh 02h 4800h to 4bffh 12h 8800h to 8bffh 22h c800h to cbffh 32h 0c00h to 0fffh 03h 4c00h to 4fffh 13h 8c00h to 8fffh 23h cc00h to cfffh 33h 1000h to 13ffh 04h 5000h to 53ffh 14h 9000h to 93ffh 24h d000h to d3ffh 34h 1400h to 17ffh 05h 5400h to 57ffh 15h 9400h to 97ffh 25h d400h to d7ffh 35h 1800h to 1bffh 06h 5800h to 5bffh 16h 9800h to 9bffh 26h d800h to dbffh 36h 1c00h to 1fffh 07h 5c00h to 5fffh 17h 9c00h to 9fffh 27h dc00h to dfffh 37h 2000h to 23ffh 08h 6000h to 63ffh 18h a000h to a3ffh 28h e000h to e3ffh 38h 2400h to 27ffh 09h 6400h to 67ffh 19h a400h to a7ffh 29h e400h to e7ffh 39h 2800h to 2bffh 0ah 6800h to 6bffh 1ah a800h to abffh 2ah e800h to ebffh 3ah 2c00h to 2fffh 0bh 6c00h to 6fffh 1bh ac00h to afffh 2bh ec00h to efffh 3bh 3000h to 33ffh 0ch 7000h to 73ffh 1ch b000h to b3ffh 2ch 3400h to 37ffh 0dh 7400h to 77ffh 1dh b400h to b7ffh 2dh 3800h to 3bffh 0eh 7800h to 7bffh 1eh b800h to bbffh 2eh 3c00h to 3fffh 0fh 7c00h to 7fffh 1fh bc00h to bfffh 2fh chapter 3 cpu architecture user?s manual u17553ej4v0ud 46 table 3-2. correspondence betw een address values and block nu mbers in flash memory (2/2) (2) pd78f0892, 78f0893 address value block number address value memory bank block number address value memory bank block number address value memory bank block number 0000h to 03ffh 00h 8000h to 83ffh 20h 8000h to 83ffh 40h 8000h to 83ffh 60h 0400h to 07ffh 01h 8400h to 87ffh 21h 8400h to 87ffh 41h 8400h to 87ffh 61h 0800h to 0bffh 02h 8800h to 8bffh 22h 8800h to 8bffh 42h 8800h to 8bffh 62h 0c00h to 0fffh 03h 8c00h to 8fffh 23h 8c00h to 8fffh 43h 8c00h to 8fffh 63h 1000h to 13ffh 04h 9000h to 93ffh 24h 9000h to 93ffh 44h 9000h to 93ffh 64h 1400h to 17ffh 05h 9400h to 97ffh 25h 9400h to 97ffh 45h 9400h to 97ffh 65h 1800h to 1bffh 06h 9800h to 9bffh 26h 9800h to 9bffh 46h 9800h to 9bffh 66h 1c00h to 1fffh 07h 9c00h to 9fffh 27h 9c00h to 9fffh 47h 9c00h to 9fffh 67h 2000h to 23ffh 08h a000h to a3ffh 28h a000h to a3ffh 48h a000h to a3ffh 68h 2400h to 27ffh 09h a400h to a7ffh 29h a400h to a7ffh 49h a400h to a7ffh 69h 2800h to 2bffh 0ah a800h to abffh 2ah a800h to abffh 4ah a800h to abffh 6ah 2c00h to 2fffh 0bh ac00h to afffh 2bh ac00h to afffh 4bh ac00h to afffh 6bh 3000h to 33ffh 0ch b000h to b3ffh 2ch b000h to b3ffh 4ch b000h to b3ffh 6ch 3400h to 37ffh 0dh b400h to b7ffh 2dh b400h to b7ffh 4dh b400h to b7ffh 6dh 3800h to 3bffh 0eh b800h to bbffh 2eh b800h to bbffh 4eh b800h to bbffh 6eh 3c00h to 3fffh 0fh bc00h to bfffh 0 2fh bc00h to bfffh 2 4fh bc00h to bfffh 4 6fh 4000h to 43ffh 10h 8000h to 83ffh 30h 8000h to 83ffh 50h 8000h to 83ffh 70h 4400h to 47ffh 11h 8400h to 87ffh 31h 8400h to 87ffh 51h 8400h to 87ffh 71h 4800h to 4bffh 12h 8800h to 8bffh 32h 8800h to 8bffh 52h 8800h to 8bffh 72h 4c00h to 4fffh 13h 8c00h to 8fffh 33h 8c00h to 8fffh 53h 8c00h to 8fffh 73h 5000h to 53ffh 14h 9000h to 93ffh 34h 9000h to 93ffh 54h 9000h to 93ffh 74h 5400h to 57ffh 15h 9400h to 97ffh 35h 9400h to 97ffh 55h 9400h to 97ffh 75h 5800h to 5bffh 16h 9800h to 9bffh 36h 9800h to 9bffh 56h 9800h to 9bffh 76h 5c00h to 5fffh 17h 9c00h to 9fffh 37h 9c00h to 9fffh 57h 9c00h to 9fffh 77h 6000h to 63ffh 18h a000h to a3ffh 38h a000h to a3ffh 58h a000h to a3ffh 78h 6400h to 67ffh 19h a400h to a7ffh 39h a400h to a7ffh 59h a400h to a7ffh 79h 6800h to 6bffh 1ah a800h to abffh 3ah a800h to abffh 5ah a800h to abffh 7ah 6c00h to 6fffh 1bh ac00h to afffh 3bh ac00h to afffh 5bh ac00h to afffh 7bh 7000h to 73ffh 1ch b000h to b3ffh 3ch b000h to b3ffh 5ch b000h to b3ffh 7ch 7400h to 77ffh 1dh b400h to b7ffh 3dh b400h to b7ffh 5dh b400h to b7ffh 7dh 7800h to 7bffh 1eh b800h to bbffh 3eh b800h to bbffh 5eh b800h to bbffh 7eh 7c00h to 7fffh 1fh bc00h to bfffh 1 3fh bc00h to bfffh 3 5fh bc00h to bfffh 5 7fh remark pd78f0892: block numbers 00h to 5fh pd78f0893: block numbers 00h to 7fh chapter 3 cpu architecture user?s manual u17553ej4v0ud 47 3.1.1 internal program memory space the internal program memory space stores the program and table data. normally, it is addressed with the program counter (pc). 78k0/ff2 products incorporate internal rom (flash memory), as shown below. table 3-2. intern al rom capacity internal rom part number structure capacity pd78f0891 61440 8 bits (0000h to efffh) pd78f0892 98304 8 bits (0000h to 7fffh (common area: 32 kb) + 8000h to bfffh (bank area: 16 kb) 4) pd78f0893 flash memory 131072 8 bits (0000h to 7fffh (common area: 32 kb) + 8000h to bfffh (bank area: 16 kb) 6) the internal program memory space is divided into the following areas. (1) vector code area the 64-byte area 0000h to 003fh is reserved as a vect or code area. the program start addresses for branch upon reset signal input or generation of each interru pt request are stored in the vector code area. of the 16-bit address, the lower 8 bits are stored at even addresses and t he higher 8 bits are stored at odd addresses. table 3-3. vector code vector code address interrupt source vector code address interrupt source 0020h intcsi10/intsre61 0000h reset input, poc, lvi, wdt 0022h intp6/intsr61 0004h intlvi 0024h intp7/intst61 0006h intp0 0026h inttmh1 0008h intp1 0028h inttmh0 000ah intp2/inttm002 002ah inttm50 000ch intp3/inttm012 002ch inttm000 000eh intp4/inttm003 002eh inttm010 0010h intp5/inttm013 0030h intad 0012h intc0err 0032h intwti/intdmu 0014h intc0wup 0034h inttm51 0016h intc0rec 0036h intwt 0018h intc0trx 0038h intcsi11 001ah intsre60 003ah inttm001 001ch intsr60 003ch inttm011 001eh intst60 003eh brk chapter 3 cpu architecture user?s manual u17553ej4v0ud 48 (2) callt instruction table area the 64-byte area 0040h to 007fh can st ore the subroutine entry address of a 1-byte call instruction (callt). (3) option byte area the option byte area is assigned to t he 1-byte area of 0080h. refer to chapter 23 option byte for details. (4) callf instruction entry area the area 0800h to 0fffh can perform a direct subrout ine call with a 2-byte ca ll instruction (callf). (5) on-chip debug security id setting area a 10-byte area of 0085h to 008eh and 1085h to 108eh can be used as an on-chip debug security id setting area. set the on-chip debug security id of 10 bytes at 0085h to 008eh when the b oot swap is not used and at 0085h to 008eh and 1085h to 108eh when the boot swap is used. for details, see chapter 25 on-chip debug function . 3.1.2 bank area ( pd78f0892 and 78f0893 only) the pd78f0892 has bank areas 0 to 3 and the pd78f0893 has bank areas 0 to 5 as illustrated below. the banks are selected by a bank select register (bank) (see 4.3 memory bank select register (bank) ). cautions 1. instructions cannot be fetched between different banks. 2. branch and access cannot be directly executed between differe nt memory banks. execute branch or access between different memory banks via the common area. 3. allocate interrupt ser vicing in the common area. 4. an instruction that extends from 7fffh to 8000h can only be executed in memory bank 0. figure 3-4. internal rom (f lash memory) configuration (a) pd78f0892 8000h 7fffh bfffh common area 32768 8 bits bank area 0 16384 8 bits 0000h bank area 3 16384 8 bits bank area 1 16384 8 bits bank area 2 16384 8 bits chapter 3 cpu architecture user?s manual u17553ej4v0ud 49 (b) pd78f0893 8000h 7fffh bfffh common area 32768 8 bits bank area 0 16384 8 bits 0000h bank area 1 16384 8 bits bank area 2 16384 8 bits bank area 3 16384 8 bits bank area 4 16384 8 bits bank area 5 16384 8 bits the following table shows the relations among bank num bers, cpu addresses, and real addresses of the flash memory. table 3-4. bank numbers, cpu address es, and real addresses of flash memory (a) pd78f0892 bank no. cpu address real address of flash memory ? 0000h to 7fffh (common area) 00000h to 07fffh 0 08000h to 0bfffh 1 0c000h to 0ffffh 2 10000h to 13fffh 3 8000h to bfffh 14000h to 17fffh 4 or more setting prohibited (b) pd78f0893 bank no. cpu address real address of flash memory ? 0000h to 7fffh (common area) 00000h to 07fffh 0 08000h to 0bfffh 1 0c000h to 0ffffh 2 10000h to 13fffh 3 14000h to 17fffh 4 18000h to 1bfffh 5 8000h to bfffh 1c000h to 1ffffh 6 or more setting prohibited chapter 3 cpu architecture user?s manual u17553ej4v0ud 50 3.1.3 internal data memory space 78k0/ff2 products incorporate the following ram. (1) internal high-speed ram table 3-5. internal high-speed ram capacity part number internal high-speed ram pd78f0891 pd78f0892 pd78f0893 1024 8 bits (fb00h to feffh) the 32-byte area fee0h to feffh is assigned to four g eneral-purpose register banks consisting of eight 8-bit registers per one bank. this area cannot be used as a program area in which instructions are written and executed. the internal high-speed ram can also be used as a stack memory. (2) internal expansion ram table 3-6. internal expansion ram capacity part number internal expansion ram pd78f0891 2048 8 bits (f000h to f7ffh) pd78f0892 4096 8 bits (e800h to f7ffh) pd78f0893 6144 8 bits (e000h to f7ffh) the internal expansion ram can also be used as a normal data area similar to the inte rnal high-speed ram, as well as a program area in which inst ructions can be written and executed. the internal expansion ram cannot be used as a stack memory. 3.1.4 special function register (sfr) area on-chip peripheral hardware special function registers (sfr s) are allocated in the area ff00h to ffffh (refer to table 3-7 special function register list in 3.2.3 special function registers (sfrs) ). caution do not access addresses to which sfrs are not assigned. 3.1.5 data memory addressing addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. several addressing modes are provided for addressing the memo ry relevant to the executi on of instructions for the 78k0/ff2, based on operability and other cons iderations. for areas containing dat a memory in particular, special addressing methods designed for the functions of special function registers (sfr) and general-purpose registers are available for use. figure 3-5 to 3-7 show correspondenc e between data memory and addressing. for details of each addressing mode, refer to 3.4 operand address addressing . chapter 3 cpu architecture user?s manual u17553ej4v0ud 51 figure 3-5. correspondence between data memory and addressing ( pd78f0891) ffffh ff20h ff1fh 0000h ff00h feffh fee0h fedfh fe20h fe1fh f800h f7ffh f000h efffh fe10h fe0fh special function registers (sfr) 256 8 bits short direct addressing sfr addressing internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits flash memory 61440 8 bits direct addressing register indirect addressing based addressing based indexed addressing internal expansion ram 2048 8 bits fa00h f9ffh note 1 0083h 0082h note 2 reserved afcan area (256 8 bits) fb00h faffh register addressing 0190h 018fh notes 1. during on-chip debugging, use of this area is disabl ed since it is used as the user data backup area for communication. 2. during on-chip debugging, use of this area is di sabled since it is used as the communication command area (269 bytes). chapter 3 cpu architecture user?s manual u17553ej4v0ud 52 figure 3-6. correspondence between data memory and addressing ( pd78f0892) 16384 8 bits (bank 1) 16384 8 bits (bank 3) 16384 8 bits (bank 2) special function registers (sfr) 256 8 bits short direct addressing sfr addressing internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved flash memory 16384 8 bits (bank 0) register addressing direct addressing register indirect addressing based addressing based indexed addressing internal expansion ram 4096 8 bits note 1 note 2 afcan area (256 8 bits) ffffh ff00h feffh fee0h fedfh fb00h faffh f800h f7ffh e800h e7ffh 0000h 0083h 0082h 0190h 018fh fa00h f9ffh fe10h fe0fh fe20h fe1fh ff20h ff1fh reserved 8000h 7fffh c000h bfffh flash memory 32768 8 bits (common) notes 1. during on-chip debugging, use of this area is disabl ed since it is used as the user data backup area for communication. 2. during on-chip debugging, use of this area is di sabled since it is used as the communication command area (269 bytes). chapter 3 cpu architecture user?s manual u17553ej4v0ud 53 figure 3-7. correspondence between data memory and addressing ( pd78f0893) 16384 8 bits (bank 1) 16384 8 bits (bank 3) 16384 8 bits (bank 2) special function registers (sfr) 256 8 bits short direct addressing sfr addressing internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved flash memory 16384 8 bits (bank 0) register addressing direct addressing register indirect addressing based addressing based indexed addressing internal expansion ram 6144 8 bits note 1 note 2 afcan area (256 8 bits) ffffh ff00h feffh fee0h fedfh fb00h faffh f800h f7ffh e000h dfffh 0000h 0083h 0082h 0190h 018fh fa00h f9ffh fe10h fe0fh fe20h fe1fh ff20h ff1fh reserved 8000h 7fffh c000h bfffh flash memory 32768 8 bits (common) 16384 8 bits (bank 4) 16384 8 bits (bank 5) notes 1. during on-chip debugging, use of this area is disabl ed since it is used as the user data backup area for communication. 2. during on-chip debugging, use of this area is di sabled since it is used as the communication command area (269 bytes). chapter 3 cpu architecture user?s manual u17553ej4v0ud 54 3.2 processor registers 78k0/ff2 products incorporate t he following processor registers. 3.2.1 control registers the control registers control the program sequence, statuses and stack memory. the control registers consist of a program counter (pc), a program status word (psw) and a stack pointer (sp). (1) program counter (pc) the program counter is a 16-bit regist er that holds the address information of the next program to be executed. in normal operation, the pc is automat ically incremented according to the numbe r of bytes of the instruction to be fetched. when a branch instruction is execut ed, immediate data and regi ster contents are set. reset signal generation sets the reset vector code values at addresses 0000h and 0001h to the program counter. figure 3-8. format of program counter 15 0 pc pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (2) program status word (psw) the program status word is an 8-bit r egister consisting of various flags set/reset by instruction execution. program status word contents ar e automatically stacked upon interrupt request generation or push psw instruction execution and are re stored upon execution of the retb , reti and pop psw instructions. reset signal sets the psw to 02h. figure 3-9. format of program status word 7 0 psw ie z rbs1 ac rbs0 0 isp cy (a) interrupt enable flag (ie) this flag controls the interrupt reques t acknowledge operations of the cpu. when 0, the ie flag is set to the interrupt disabled (di) state, and all maskable interrupt requests are disabled. other interrupt requests are all disabled. when 1, the ie flag is set to the interrupt enabled (ei) state and interrupt request acknowledgement is controlled with an in-service priority flag (isp), an in terrupt mask flag for various interrupt sources, and a priority specification flag. the ie flag is reset (0) upon di instruction execution or interrupt acknowledgement and is set (1) upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is se t (1). it is reset (0 ) in all other cases. chapter 3 cpu architecture user?s manual u17553ej4v0ud 55 (c) register bank select flags (rbs0 and rbs1) these are 2-bit flags to select one of the four register banks. in these flags, the 2-bit information that indicates t he register bank selected by sel rbn instruction execution is stored. (d) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bi t 3, this flag is set (1). it is reset (0) in all other cases. (e) in-service priority flag (isp) this flag manages the priority of acknowledgeable mask able vectored interrupts. when this flag is 0, low- level vectored interrupt requests specified by a priority specification flag register (pr0l, pr0h, pr1l, pr1h) (refer to 17.3 (3) priority specifi cation flag registers (p r0l, pr0h, pr1l, pr1h) ) can not be acknowledged. actual request acknowledgement is controlled by the interrupt enable flag (ie). (f) carry flag (cy) this flag stores overflow and underflow upon add/subtract instruct ion execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) stack pointer (sp) this is a 16-bit register to hold the start address of the memory stack area. only the internal high-speed ram area can be set as the stack area. figure 3-10 format of stack pointer 15 0 sp sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 the sp is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the stack memory. each stack operation saves/restores dat a as shown in figures 3-11 and 3-12. caution since rest signal generation makes the sp c ontents undefined, be sure to initialize the sp before using the stack. chapter 3 cpu architecture user?s manual u17553ej4v0ud 56 figure 3-11. data to be saved to stack memory (a) push rp instruction (when sp = fee0h) register pair lower fee0h sp sp fee0h fedfh fedeh register pair higher fedeh (b) call, callf, callt instructions (when sp = fee0h) pc15 to pc8 fee0h sp sp fee0h fedfh fedeh pc7 to pc0 fedeh (c) interrupt, brk instruct ions (when sp = fee0h) pc15 to pc8 psw fedfh fee0h sp sp fee0h fedeh feddh pc7 to pc0 feddh chapter 3 cpu architecture user?s manual u17553ej4v0ud 57 figure 3-12. data to be restored from stack memory (a) pop rp instruction (when sp = fedeh) register pair lower fee0h sp sp fee0h fedfh fedeh register pair higher fedeh (b) ret instruction (when sp = fedeh) pc15 to pc8 fee0h sp sp fee0h fedfh fedeh pc7 to pc0 fedeh (c) reti, retb instructions (when sp = feddh) pc15 to pc8 psw fedfh fee0h sp sp fee0h fedeh feddh pc7 to pc0 feddh chapter 3 cpu architecture user?s manual u17553ej4v0ud 58 3.2.2 general-purpose registers general-purpose registers are mapp ed at particular addresses (fee0h to feffh) of the data memory. the general-purpose registers consists of 4 bank s, each bank consisting of eight 8-bit r egisters (x, a, c, b, e, d, l, and h). each register can be used as an 8-bit register, and two 8-bit r egisters can also be used in a pair as a 16-bit register (ax, bc, de, and hl). these registers can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). register banks to be used for instructi on execution are set by the cpu control instruction (sel rbn). because of the 4-register bank configur ation, an efficient program can be created by switching between a register for normal processing and a register for interrupts for each bank. figure 3-13. configuration of general-purpose registers (a) absolute name bank0 bank1 bank2 bank3 feffh fef8h fee0h rp3 rp2 rp1 rp0 r7 15 0 7 0 r6 r5 r4 r3 r2 r1 r0 16-bit processing 8-bit processing fef0h fee8h (b) function name bank0 bank1 bank2 bank3 feffh fef8h fee0h hl de bc ax h 15 0 7 0 l d e b c a x 16-bit processing 8-bit processing fef0h fee8h chapter 3 cpu architecture user?s manual u17553ej4v0ud 59 3.2.3 special function registers (sfrs) unlike a general-purpose register, each special f unction register has a special function. sfrs are allocated to the ff00h to ffffh area. special function registers can be manipulated like general -purpose registers, using operation, transfer and bit manipulation instructions. the manipulatable bit units, 1, 8, and 16, depend on the spec ial function register type. each manipulation bit unit can be specified as follows. ? 1-bit manipulation describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified with an address. ? 8-bit manipulation describe the symbol reserved by the assembler fo r the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified with an address. ? 16-bit manipulation describe the symbol reserved by the assembler fo r the 16-bit manipulation instruction operand (sfrp). when specifying an address, describe an even address. table 3-7 gives a list of the special f unction registers. the meanings of items in the table are as follows. ? symbol symbol indicating the address of a special function register. it is a re served word in the ra78k0, and is defined by the header file ?sfrbit.h? in the cc78k0. when us ing the ra78k0, id78k0-ns, id78k0, or sm78k0, symbols can be written as an instruction operand. ? r/w indicates whether the corresponding special f unction register can be read or written. r/w: read/write enable r: read only w: write only ? manipulatable bit units indicates the manipulatable bit unit (1, 8, or 16). ? ? ? indicates a bit unit for which manipulation is not possible. ? after reset indicates each register status upon reset signal generation. chapter 3 cpu architecture user?s manual u17553ej4v0ud 60 table 3-7. special function register list (1/6) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff00h port register 0 p0 r/w ? 00h ff01h port register 1 p1 r/w ? 00h ff02h 8-bit timer h compare register 00 cmp00 r/w ? ? 00h ff03h port register 3 p3 r/w ? 00h ff04h port register 4 p4 r/w ? 00h ff05h port register 5 p5 r/w ? 00h ff06h port register 6 p6 r/w ? 00h ff07h port register 7 p7 r/w ? 00h ff08h port register 8 p8 r/w ? 00h ff09h port register 9 p9 r/w ? 00h ff0ah receive buffer register 60 rxb60 r ? ? ffh ff0bh transmit buffer register 60 txb60 r/w ? ? ffh ff0ch port register 12 p12 r/w ? 00h ff0dh port register 13 p13 r/w ? 00h ff0eh 8-bit timer h compare register 10 cmp10 r/w ? ? 00h ff0fh serial i/o shift register 10 sio10 r ? ? 00h ff10h ff11h 16-bit timer counter 00 tm00 r ? ? 0000h ff12h ff13h 16-bit timer capture/compare register 000 cr000 r/w ? ? 0000h ff14h ff15h 16-bit timer capture/compare register 010 cr010 r/w ? ? 0000h ff16h 8-bit timer counter 50 tm50 r ? ? 00h ff17h 8-bit timer compare register 50 cr50 r/w ? 00h ff18h 10- bit a/d conversion result register adcr r ? ? 0000h ff19h 8-bit a/d conversion result register adcrh r ? ? 00h ff1ah 8-bit timer h compare register 01 cmp01 r/w ? ? 00h ff1bh 8-bit timer h compare register 11 cmp11 r/w ? ? 00h ff1fh 8-bit timer counter 51 tm51 r ? ? 00h ff20h port mode register 0 pm0 r/w ? ffh ff21h port mode register 1 pm1 r/w ? ffh ff22h a/d port configuration register adpc r/w ? 00h ff23h port mode register 3 pm3 r/w ? ffh ff24h port mode register 4 pm4 r/w ? ffh ff25h port mode register 5 pm5 r/w ? ffh ff26h port mode register 6 pm6 r/w ? ffh ff27h port mode register 7 pm7 r/w ? ffh ff28h port mode register 8 pm8 r/w ? ffh ff29h port mode register 9 pm9 r/w ? ffh chapter 3 cpu architecture user?s manual u17553ej4v0ud 61 table 3-7. special function register list (2/6) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff2ah a/d converter mode register adm r/w ? 00h ff2bh analog input channel specification register ads r/w ? 00h ff2ch port mode register 12 pm12 r/w ? ffh ff2dh port mode register 13 pm13 r/w ? feh ff2eh asynchronous serial interface selection register 61 asim61 r/w ? 01h ff2fh asynchronous serial inte rface reception error status register 61 asis61 r ? ? 00h ff30h pull-up resistor option register 0 pu0 r/w ? 00h ff31h pull-up resistor option register 1 pu1 r/w ? 00h ff33h pull-up resistor option register 3 pu3 r/w ? 00h ff34h pull-up resistor option register 4 pu4 r/w ? 00h ff35h pull-up resistor option register 5 pu5 r/w ? 00h ff36h pull-up resistor option register 6 pu6 r/w ? 00h ff37h pull-up resistor option register 7 pu7 r/w ? 00h ff38h asynchronous serial in terface transmission status register 61 asif61 r ? ? 00h ff39h clock selection register 61 cksr61 r/w ? ? 00h ff3ah asynchronous serial interface receive buffer register 61 rxb61 r/w ? ? ffh ff3bh asynchronous serial interface transmit buffer register 61 txb61 r/w ? ? ffh ff3ch pull-up resistor option register 12 pu12 r/w ? 00h ff3dh pull-up resistor option register 13 pu13 r/w ? 00h ff3eh baud rate generator control register 61 brgc61 r/w ? ? ffh ff3fh asynchronous serial interface control register 61 asicl61 r/w ? 16h ff40h clock output selection register cks r/w ? 00h ff41h 8-bit timer compare register 51 cr51 r/w ? 00h ff42h multiplier/divider control register 0 dmuc0 r/w ? 00h ff43h 8-bit timer mode control register 51 tmc51 r/w ? 00h ff44h sdr0l ff45h remainder data register 0 sdr0 sdr0h r/w ? 0000h ff47h serial i/o shift register 11 sio11 r ? ? 00h ff48h external interrupt risi ng edge enable register egp r/w ? 00h ff49h external interrupt fa lling edge enable register egn r/w ? 00h ff4ah multiplication/division data register a0l mda0l r/w ? 0000h ff4bh ff4ch multiplication/division data register a0h mda0h r/w ? 0000h ff4dh ff4eh transmit buffer register 11 sotb11 r/w ? ? 00h chapter 3 cpu architecture user?s manual u17553ej4v0ud 62 table 3-7. special function register list (3/6) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff4fh input switch control register isc r/w ? 00h ff50h asynchronous serial interface operation mode register 60 asim60 r/w ? 01h ff51h prescaler mode register 03 prm03 r/w ? 00h ff52h capture/compare control register 03 crc03 r/w ? 00h ff53h asynchronous serial inte rface reception error status register 60 asis60 r ? ? 00h ff54h 16-bit timer mode control register 02 tmc02 r/w ? 00h ff55h asynchronous serial in terface transmission status register 60 asif60 r ? ? 00h ff56h clock selection register 60 cksr60 r/w ? ? 00h ff57h baud rate generator control register 60 brgc60 r/w ? ? ffh ff58h asynchronous serial interface control register 60 asicl60 r/w ? 16h ff59h prescaler mode register 02 prm02 r/w ? 00h ff5ah ff5bh 16-bit timer counter 02 tm02 r ? ? 0000h ff5ch capture/compare control register 02 crc02 r/w ? 00h ff60h ff61h module receive history list get pointer register c0rgpt r/w ? ? xx02h ff62h ff63h module transmission hist ory list get pointer register c0tgpt r/w ? ? xx02h ff64h ff65h can global macro clock selection c0gmctrl r/w ? ? 0000h ff66h ff67h can global macro automatic block transmission delay register c0gmabt r/w ? ? 0000h ff68h module last out pointer register c0lopt r ? ? undefined ff69h 8-bit timer h mode register 0 tmhmd0 r/w ? 00h ff6ah timer clock selection register 50 tcl50 r/w ? 00h ff6bh 8-bit timer mode control register 50 tmc50 r/w ? 00h ff6ch 16-bit capture/compare register 002 cr002 r/w ? ? 0000h ff6dh ff6eh can global macro clock se lection register c0gmcs r/w ? ? 0fh ff6fh can global macro automatic block transmission register c0gmabtd r/w ? ? 00h ff70h ff71h can module mask 1 register l c0mask1l r/w ? ? undefined ff72h ff73h can module mask 1 register h c0mask1h r/w ? ? undefined ff74h ff75h can module mask 2 register l c0mask2l r/w ? ? undefined chapter 3 cpu architecture user?s manual u17553ej4v0ud 63 table 3-7. special function register list (4/6) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff76h ff77h can module mask 2 register h c0mask2h r/w ? ? undefined ff78h ff79h can module mask 3 register l c0mask3l r/w ? ? undefined ff7ah ff7bh can module mask 3 register h c0mask3h r/w ? ? undefined ff7ch ff7dh can module mask 4 register l c0mask4l r/w ? ? undefined ff7eh ff7fh can module mask 4 register h c0mask4h r/w ? ? undefined ff80h serial operation mode register 10 csim10 r/w ? 00h ff81h serial clock selection register 10 csic10 r/w ? 00h ff84h transmit buffer register 10 sotb10 r/w ? ? 00h ff88h serial operation mode register 11 csim11 r/w ? 00h ff89h serial clock selection register 11 csic11 r/w ? 00h ff8ah can module time stamp register c0ts r/w ? ? 0000h ff8bh ff8ch timer clock selection register 51 tcl51 r/w ? 00h ff8fh watch timer operation mode register wtm r/w ? 00h ff90h ff91h can module control register c0ctrl r/w ? ? 0000h ff92h can module last error code register c0lec r/w ? ? 00h ff93h can module information register c0info r ? ? 00h ff94h ff95h can module error counters c0erc r ? ? 0000h ff96h ff97h can module interrupt enable register c0ie r/w ? ? 0000h ff98h can module interrupt pending register c0ints r/w ? ? 0000h ff99h ff9bh watchdog timer enable register wdte r/w ? ? 1ah/9ah note1 ff9ch ff9dh can module bit rate register c0btr r/w ? ? 370fh ff9eh can module bit rate prescaler register c0brp r/w ? ? ffh ff9fh can module last in pointer register c0lipt r ? ? undefined ffa0h internal oscillator mode register rcm r/w ? 00h note2 ffa1h main clock mode register mcm r/w ? 00h ffa2h main osc control register moc r/w ? 80h notes 1. the reset value of wdte is determined by setting of option byte. 2. the value of this register is 00h immediately after a reset release but automatically changes to 80h after internal high-speed oscillator has been stabilized. chapter 3 cpu architecture user?s manual u17553ej4v0ud 64 tables 3-7. special function register list (5/6) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ffa3h oscillation stabilization time counter status register ostc r ? 00h ffa4h oscillation stabilization time select register osts r/w ? 05h ffa5h 16-bit timer output control register 02 toc02 r/w ? 00h ffa6h ffa7h 16-bit timer counter 03 tm03 r ? ? 0000h ffa8h ffa9h 16-bit timer capture/compare register 003 cr003 r/w ? ? 0000h ffaah ffabh 16-bit timer capture/compare register 013 cr013 r/w ? ? 0000h ffach reset control flag register resf r ? ? 00h note 1 ffadh 16-bit timer mode control register 03 tmc03 r/w ? 00h ffaeh mdb0l ffafh multiplier/divider data register b0 mdb0 mdb0h r/w ? 0000h ffb0h ffb1h 16-bit timer counter 01 tm01 r ? ? 0000h ffb2h 16-bit timer capture/compare register 001 cr001 r/w ? ? 0000h ffb3h ffb4h ffb5h 16-bit timer capture/compare register 011 cr011 r/w ? ? 0000h ffb6h 16-bit timer mode control register 01 tmc01 r/w ? 00h ffb7h prescaler mode register 01 prm01 r/w ? 00h ffb8h capture/compare control register 01 crc01 r/w ? 00h ffb9h 16-bit timer output control register 01 toc01 r/w ? 00h ffbah 16-bit timer mode control register 00 tmc00 r/w ? 00h ffbbh prescaler mode register 00 prm00 r/w ? 00h ffbch capture/compare control register 00 crc00 r/w ? 00h ffbdh 16-bit timer output control register 00 toc00 r/w ? 00h ffbeh low-voltage detection register lvim r/w ? 00h ffbfh low-voltage detection level selection register lvis r/w ? 00h ffc2h flash status register pfs r/w ? 00h ffc4h flash programming mode control register flpmc r/w ? 08h/0ch note 2 ffe0h interrupt request flag register 0l if0l r/w 00h ffe1h interrupt request flag register 0h if0 if0h r/w 00h ffe2h interrupt request flag register 1l if1l r/w 00h ffe3h interrupt request flag register 1h if1 if1h r/w 00h notes 1. this value varies depending on the reset source. 2. varies depending on the operation mode. ? user mode: 08h ? on-board mode: 0ch chapter 3 cpu architecture user?s manual u17553ej4v0ud 65 tables 3-7. special function register list (6/6) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ffe4h interrupt mask flag register 0l mk0l r/w ffh ffe5h interrupt mask flag register 0h mk0 mk0h r/w ffh ffe6h interrupt mask flag register 1l mk1l r/w ffh ffe7h interrupt mask flag register 1h mk1 mk1h r/w dfh ffe8h priority specificati on flag register 0l pr0l r/w ffh ffe9h priority specific ation flag register 0h pr0 pr0h r/w ffh ffeah priority specificati on flag register 1l pr1l r/w ffh ffebh priority specific ation flag register 1h pr1 pr1h r/w ffh ffech 16-bit timer capture/compare register 012 cr012 r/w ? ? 0000h ffedh ffeeh 8-bit timer h carrier control register 1 tmcyc1 r/w ? 00h ffefh clock operation mode select register oscctl r/w ? 00h fff0h internal memory size switching register note ims r/w ? ? cfh fff4h internal expansion ram size switching register note ixs r/w ? ? 0ch fff9h 16-bit timer output control register 03 toc03 r/w ? 00h fffah 8-bit timer h mode register 1 tmhmd1 r/w ? 00h fffbh processor clock control register pcc r/w ? 01h note regardless of the internal memory capac ity, the initial values of the inter nal memory size switching register (ims) and internal expansion ram size switching register (ixs) of the 78k0/ff2 is fixed (ims = cfh, ixs = 0ch). therefore, set the value corresponding to each as indicated below. flash memory version ims ixs pd78f0891 cfh 08h pd78f0892 cch 04h pd78f0893 cch 00h chapter 3 cpu architecture user?s manual u17553ej4v0ud 66 3.3 instruction address addressing an instruction address is determined by program counter (pc) contents and is normally incremented (+1 for each byte) automatically according to the num ber of bytes of an instruction to be fetched each time another instruction is executed. when a branch instruction is executed, the branch destination information is set to the pc and branched by the following addressing (for deta ils of instructions, refer to 78k/0 series instructions user?s manual (u12326e) . 3.3.1 relative addressing [function] the value obtained by adding 8-bit immediate data (displ acement value: jdisp8) of an instruction code to the start address of the following instruction is transfe rred to the program counter (pc) and branched. the displacement value is treated as signed two?s complement data ( ? 128 to +127) and bit 7 becomes a sign bit. in other words, relative addressing consists of relati ve branching from the start address of the following instruction to the ? 128 to +127 range. this function is carried out when the br $addr16 instruct ion or a conditional branch instruction is executed. [illustration] 15 0 pc + 15 0 876 s 15 0 pc jdisp8 when s = 0, all bits of are 0. when s = 1, all bits of are 1. pc indicates the start address of the instruction after the br instruction. ... chapter 3 cpu architecture user?s manual u17553ej4v0ud 67 3.3.2 immediate addressing [function] immediate data in the instruction word is tran sferred to the program counter (pc) and branched. this function is carried out when the call !addr16 or br !addr16 or callf !addr11 instruction is executed. call !addr16 and br !addr16 instructions can be branc hed to the entire memory s pace. the callf !addr11 instruction is branc hed to the 0800h to 0fffh area. [illustration] in the case of call !addr16 and br !addr16 instructions 15 0 pc 87 70 call or br low addr. high addr. in the case of callf !addr11 instruction 15 0 pc 87 70 fa 10?8 11 10 00001 643 callf fa 7?0 chapter 3 cpu architecture user?s manual u17553ej4v0ud 68 3.3.3 table indirect addressing [function] table contents (branch desti nation address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation co de are transferred to the progr am counter (pc) and branched. this function is carried out when the ca llt [addr5] instruction is executed. this instruction references the address stored in the me mory table from 40h to 7fh, and allows branching to the entire memory space. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address+1 effective address 01 00000000 87 87 65 0 0 1 11 765 10 ta 4?0 operation code 3.3.4 register addressing [function] register pair (ax) contents to be s pecified with an instruction word are tr ansferred to the program counter (pc) and branched. this function is carried out when t he br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87 chapter 3 cpu architecture user?s manual u17553ej4v0ud 69 3.4 operand address addressing the following methods are available to specify the r egister and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 implied addressing [function] the register that functions as an accumulator (a and ax) among the general-purpose registers is automatically (implicitly) addressed. of the 78k0/ff2 instruction words, the followi ng instructions employ implied addressing. instruction register to be s pecified by implied addressing mulu a register for multiplicand and ax register for product storage divuw ax register for dividend and quotient storage adjba/adjbs a register for storage of numeric va lues that become decimal correction targets ror4/rol4 a register for storage of di git data that undergoes digit rotation [operand format] because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [description example] in the case of mulu x with an 8-bit 8-bit multiply instruction, the pr oduct of a register and x register is stored in ax. in this example, the a and ax registers are specified by implied addressing. chapter 3 cpu architecture user?s manual u17553ej4v0ud 70 3.4.2 register addressing [function] the general-purpose register to be specified is accesse d as an operand with the regi ster bank select flags (rbs0 to rbs1) and the register specify co des (rn and rpn) of an operation code. register addressing is carried out when an instruction with the following operand format is executed. when an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl ?r? and ?rp? can be described by absolute names (r0 to r7 and rp0 to rp3) as well as function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl). [description example] mov a, c; when selecting c register as r operation code 0 1100010 register specify code incw de; when selecting de register pair as rp operation code 1 0000100 register specify code chapter 3 cpu architecture user?s manual u17553ej4v0ud 71 3.4.3 direct addressing [function] the memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !0fe00h; when setting !addr16 to fe00h operation code 10001110 op c ode 00000000 00h 11111110 feh [illustration] memory 0 7 addr16 (lower) addr16 (upper) op code chapter 3 cpu architecture user?s manual u17553ej4v0ud 72 3.4.4 short direct addressing [function] the memory to be manipulated in the fixed space is di rectly addressed with 8-bit data in an instruction word. this addressing is applied to the 256-byte space fe20h to ff1fh. internal ram and special function registers (sfrs) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. the sfr area (ff00h to ff1fh) where short direct addressing is applied is a part of the overall sfr area. ports that are frequently accessed in a program and compare and capture r egisters of the timer/event counter are mapped in this area, allowing sfrs to be mani pulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effe ctive address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. refer to the [illustration] shown below. [operand format] identifier description saddr immediate data that indicate label or fe20h to ff1fh saddrp immediate data that indicate label or fe20h to ff1fh (even address only) [description example] mov 0fe30h, a; when transferring valu e of a register to saddr (fe30h) operation code 1 1110010 op c ode 0 0110000 30h (s addr-offset) [illustration] 15 0 short direct memory effective address 1 111111 87 0 7 op code saddr-offset when 8-bit immediate data is 20h to ffh, = 0 when 8-bit immediate data is 00h to 1fh, = 1 chapter 3 cpu architecture user?s manual u17553ej4v0ud 73 3.4.5 special function register (sfr) addressing [function] a memory-mapped special function register (sfr) is addre ssed with 8-bit immediate data in an instruction word. this addressing is applied to the 240-byte spaces ff00h to ffcfh and ffe0h to ffffh. however, the sfrs mapped at ff00h to ff1fh can be ac cessed with short direct addressing. [operand format] identifier description sfr special function register name sfrp 16-bit manipulatable special function register name (even address only) [description example] mov pm0, a; when selecting pm0 (ff20h) as sfr operation code 11110110 op c ode 00100000 20h (sfr-offset) [illustration] 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1 chapter 3 cpu architecture user?s manual u17553ej4v0ud 74 3.4.6 register indirect addressing [function] register pair contents specified by a register pair spec ify code in an instruction word and by a register bank select flag (rbs0 and rbs1) serve as an operand address for addressing the memory. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [de], [hl] [description example] mov a, [de]; when selecting [de] as register pair operation code 10000101 [illustration] 16 0 8 d 7 e 0 7 7 0 a de the contents of the memory addressed are transferred. memory the memory address specified with the register pair de chapter 3 cpu architecture user?s manual u17553ej4v0ud 75 3.4.7 based addressing [function] 8-bit immediate data is added as offset data to the conten ts of the base register, that is, the hl register pair in the register bank specifie d by the register bank select flag (rbs0 and rbs1), and the sum is used to address the memory. addition is performed by expanding the offs et data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [hl + byte] [description example] mov a, [hl + 10h]; when setting byte to 10h operation code 10101110 00010000 [illustration] 16 0 8 h 7 l 0 7 7 0 a hl the contents of the memory addressed are transferred. memory + 10 chapter 3 cpu architecture user?s manual u17553ej4v0ud 76 3.4.8 based indexed addressing [function] the b or c register contents specified in an instruction word are added to the contents of the base register, that is, the hl register pair in the regist er bank specified by the register ba nk select flag (rbs0 and rbs1), and the sum is used to address the memory. addition is perform ed by expanding the b or c register contents as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [hl + b], [hl + c] [description example] in the case of mov a, [hl + b]; (selecting b register) operation code 10101011 [illustration] 16 0 h 7 8 l 0 7 b + 0 7 7 0 a hl the contents of the memory addressed are transferred. memory chapter 3 cpu architecture user?s manual u17553ej4v0ud 77 3.4.9 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subroutine call and return instructions are executed or the register is sa ved/reset upon generation of an interrupt request. with stack addressing, only the internal high-speed ram area can be accessed. [description example] in the case of push de; (saving de register) operation code 10110101 [illustration] e fee0h sp sp fee0h fedfh fedeh d memory 0 7 fedeh user?s manual u17553ej4v0ud 78 chapter 4 memory bank select function ( pd78f0892, 78f0893 only) 4.1 memory bank the pd78f0892, 78f0893 implement a rom capacity of 96 kb or 128 kb by selecting a memory bank from a memory space of 8000h to bfffh. the pd78f0892 has memory banks 0 to 3, and the pd78f0893 have memory banks 0 to 5, as shown below. the memory banks are selected by using a memory bank select register (bank). figure 4-1. internal rom (f lash memory) configuration (a) pd78f0892 8000h 7fffh 0000h flash memory 32768 8 bits bfffh flash memory 16384 8 bits (memory bank 0) (memory bank 1) (memory bank 2) common area bank area (memory bank 3) (b) pd78f0893 8000h 7fffh 0000h flash memory 32768 8 bits bfffh flash memory 16384 8 bits (memory bank 0) (memory bank 1) common area bank area (memory bank 3) (memory bank 4) (memory bank 5) (memory bank 2) chapter 4 memory bank select function ( pd78f0892, 78f0893 only) user?s manual u17553ej4v0ud 79 4.2 difference in representation of memory space with the 78k0/ff2 products which support the memory bank, addresses can be viewed in the following two different ways. ? memory bank number + cpu address ? flash memory real address (hex format [bank]) figure 4-2. address view (a) memory bank number + cpu address (b) flash memory real address (hex format [bank]) 0000h common (32 kb) memory bank 0 (16 kb) memory bank 1 memory bank 2 common area bank area memory bank 3 memory bank 4 memory bank 5 bfffh 8000h 7fffh memory bank 5 (16 kb) memory bank 4 (16 kb) memory bank 3 (16 kb) memory bank 2 (16 kb) memory bank 1 (16 kb) memory bank 0 (16 kb) common (32 kb) 1ffffh 1c000h 1bfffh 18000h 17fffh 14000h 13fffh 10000h 0ffffh 0c000h 0bfffh 08000h 07fffh 00000h ?memory bank number + cpu address? is represented with a vacancy in the address space, while the flash memory real address is shown with no vacancy in the address space. ?memory bank number + cpu address? is used for addressing in the user program. for on-board programming and self programming not using the self programming sample library note 1 , the flash memory real address is used. note that the hex file that is output by the assembler (ra78k0) by defau lt uses the flash memory real address. for address representation of the other tools such as the simulator and the debugger note 2 , see table 4-1 . notes 1. ?memory bank number + cpu address? can be used when performing self programming, using the self programming sample library, because the addresses are automatically translated. 2. sm+ for 78k0/fx2, id78k0-qb chapter 4 memory bank select function ( pd78f0892, 78f0893 only) user?s manual u17553ej4v0ud 80 table 4-1. memory bank address representation memory bank number cpu address flash memo ry real address address representation in simulator and debugger note 1 memory bank 0 08000h-0bfffh 08000h-0bfffh memory bank 1 0c000h-0ffffh 18000h-1bfffh memory bank 2 10000h-13fffh 28000h-2bfffh memory bank 3 14000h-17fffh 38000h-3bfffh memory bank 4 18000h-1bfffh 48000h-4bfffh memory bank 5 08000h-0bfffh note 2 1c000h-1ffffh 58000h-5bfffh notes 1. sm+ for 78k0/fx2, id78k0-qb 2. set the memory bank to be used by the memory bank select register (bank) (see figure 4-3 ). for details, see the ra78k0 ver. 3.80 assembler package operation user?s manual (u17199e) . 4.3 memory bank select register (bank) the memory bank select register (bank) is used to select a memory bank to be used. bank can be set by an 8-bit memory manipulation instruction. reset signal generation clears bank to 00h. figure 4-3. format of memory bank select register (bank) address: fff3h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 bank 0 0 0 0 0 bank2 bank1 bank0 bank setting bank2 bank1 bank0 pd78f0892 pd78f0893 0 0 0 common area (32 k) + memory bank 0 (16 k) 0 0 1 common area (32 k) + memory bank 1 (16 k) 0 1 0 common area (32 k) + memory bank 2 (16 k) 0 1 1 common area (32 k) + memory bank 3 (16 k) 1 0 0 common area (32 k) + memory bank 4 (16 k) 1 0 1 setting prohibited common area (32 k) + memory bank 5 (16 k) other than above setting prohibited caution be sure to change the value of the bank register in the common area (0000h to 7fffh). if the value of the bank register is changed in the bank area (8000h to bfffh), an inadvertent program loop occurs in the cpu. therefore, never change the value of the bank register in the bank area. chapter 4 memory bank select function ( pd78f0892, 78f0893 only) user?s manual u17553ej4v0ud 81 4.4 selecting memory bank the memory bank selected by the memory bank select re gister (bank) is reflected on the bank area and can be addressed. therefore, to access a memory bank different fr om the one currently selected , that memory bank must be selected by using the bank register. the value of the bank register must not be changed in the bank area (8000h to bfffh). therefore, to change the memory bank, branch an instruction to the common area (0000h to 7fffh) and c hange the value of the bank register in that area. cautions 1. instructions cannot be fe tched between different memory banks. 2. branching and accessing cannot be directly executed between differ ent memory banks. execute branching or accessing between diff erent memory banks via the common area. 3. allocate interrupt ser vicing in the common area. 4. an instruction that extends from 7fffh to 8000h can only be executed in memory bank 0. 4.4.1 referencing valu es between memory banks values cannot be directly referenced from one memory bank to another. to access another memory bank from one memory bank, branch once to the common area (0000h to 7fffh), change the setting of the bank register there, and then reference a value. memory bank m common area bank area memory bank n referencing value common area bank area referencing value memory bank m memory bank n chapter 4 memory bank select function ( pd78f0892, 78f0893 only) user?s manual u17553ej4v0ud 82 ? software example (to store a value to be referenced in register a) ramd dseg saddr r_bnka: ds 2 ; secures ram for specifyi ng an address at the reference destination. r_bnkn: ds 1 ; secures ram for specifying a me mory bank number at the reference destination. r_bnkrn: ds 1 ; secures ram for saving a me mory bank number at the reference source. etrc cseg unit entry: mov r_bnkn,#banknum data1 ; stores the memo ry bank number at the reference destination. movw r_bnka,#data1 ; stores the address at the reference destination. call !bnkrd ; calls a subroutine for referencing between memory banks. : : bnkc cseg at 7000h bnkrd: ; subroutine for referencing between memory banks. push hl ; saves the contents of the hl register. mov a,r_bnkn ; acquires the memory bank number at the reference destination. xch a,bank ; swaps the memory bank number at the reference source for that at the reference ; destination mov r_bnkrn,a ; saves the memory bank number at the reference source. xchw ax,hl ; saves the contents of the x register. movw ax,r_bnka ; acquires the address at the reference destination. xchw ax,hl ; specifies the address at the reference destination. mov a,[hl] ; reads the target value. xch a,r_bnkrn ; acquires the memory bank number at the reference source. mov bank,a ; specifies the memory bank number at the reference source. mov a,r_bnkrn ; write the target value to the a register. pop hl ; restores the contents of the hl register. ret ; return data cseg bank3 data1: db 0aah end chapter 4 memory bank select function ( pd78f0892, 78f0893 only) user?s manual u17553ej4v0ud 83 4.4.2 branching instruct ion between memory banks instructions cannot branch directly from one memory bank to another. to branch an instruction from one memory bank to another , branch once to the comm on area (0000h to 7fffh), change the setting of the bank r egister there, and then execute the branch instruction again. memory bank m common area bank area memory bank n instruction branch common area bank area instruction branch memory bank m memory bank n chapter 4 memory bank select function ( pd78f0892, 78f0893 only) user?s manual u17553ej4v0ud 84 ? software example 1 (to branch from all areas) ? software example 2 (to branch from common area to any bank area) ramd dseg saddr r_bnka: ds 2 ; secures ram for specifyi ng a memory bank at the branch destination. r_bnkn: ds 1 ; secures ram for specifying a memory bank number at the branch destination. rsaveax: ds 2 ; secures ram for saving the ax register. etrc cseg unit entry: mov r_bnkn,#banknum test ; stores the memory bank number at the branch destination in ram. movw r_bnka,#test ; stores the addr ess at the branch destination in ram. br !bnkbr ; branches to inte r-memory bank branch processing. : : bnkc cseg at 7000h ; bnkbr: movw rsaveax,ax ; saves the ax register. mov a,r_bnkn ; acquires the memory bank number at the branch destination. mov bank,a ; specifies the memory bank number at the branch destination. movw ax,r_bnka ; specifies the address at the branch destination. push ax ; sets the address at the branch destination to stack. movw ax,rsaveax ; restores the ax register. ret ; branch bn3 cseg bank3 test: mov ??? : : end etrc cseg at 2000h entry: mov r_bnkn,#banknum test ; stores the memory bank number at the branch destination in ram. br !test ; stores the address at the branch destination in ram. bn3 cseg bank3 test: mov ??? : : end chapter 4 memory bank select function ( pd78f0892, 78f0893 only) user?s manual u17553ej4v0ud 85 4.4.3 subroutine call between memory banks subroutines cannot be directly called between memory banks. to call a subroutine between memory banks, branch once to the common ar ea (0000h to 7fffh), specify the memory bank at the calling destination by using the bank register there, execut e the call instruction, and branch to the call destination by that instruction. at this time, save the current value of the bank register to ram. restore the value of the bank register before executing the re t instruction. memory bank m common area bank area memory bank n br instruction common area bank area call instruction memory bank m memory bank n call inst- ruction call instruction change bank and save memory bank number at calling source. ret instruction ret instruction chapter 4 memory bank select function ( pd78f0892, 78f0893 only) user?s manual u17553ej4v0ud 86 ? software example remark in the software example above, multiplexed processing is not supported. ramd dseg saddr r_bnka: ds 2 ; secures ram for specif ying an address at the calling destination. r_bnkn: ds 1 ; secures ram for specifying a memory bank number at the calling destination. r_bnkrn: ds 1 ; secures ram for saving a memory bank number at the calling source. rsaveax: ds 2 ; secures ram for saving the ax register. etrc cseg unit entry: mov r_bnkn,#banknum test ; store the memory bank number at the calling destination in ram. movw r_bnka,#test ; stores the addr ess at the calling destination in ram. call !bnkcal ; branches to an inter-memory bank calling processing routine. : : bnkc cseg at 7000h bnkcal: ; inter-memory bank calling processing routine movw rsaveax,ax ; saves the ax register. mov a,r_bnkn ; acquires the memory bank number at the calling destination. xch a,bank ; changes the bank and acquires the memory bank number at the calling source. mov r_bnkrn,a ; saves the memory bank number at the calling source to ram. call !bnkcals ; calls a subroutine to branch to the calling destination. movw rsaveax,ax ; saves the ax register. xch a,r_bnkrn ; acquires the memory bank number at the calling source. mov bank,a ; specifies the memory bank number at the calling source. movw rsaveax,ax ; restores the ax register. ret ; returns to the calling source. bnkcals: movw ax,r_bnka ; specifies the address at the calling destination. push ax ; sets the address at the calling destination to stack. movw ax,rsaveax ; restores source ax register. ret ax ; branches to the calling destination. bn3 cseg bank3 test: ; mov ??? : : ret end chapter 4 memory bank select function ( pd78f0892, 78f0893 only) user?s manual u17553ej4v0ud 87 4.4.4 instruction branch to bank area by interrupt when an interrupt occurs, instructions can branch to the me mory bank specified by the bank register by using the vector table, but it is difficult to identif y the bank register when the interrupt occurs. therefore, specify the branch destinatio n address specified by the vector table in the common area (0000h to 7fffh), specify the memory bank at the branch destinati on by using the bank register in the common area, and execute the call instruction. at this time, save the ba nk register value before the change to ram, and restore the value of the bank register before executing the reti instruction. remark allocate interrupt servicing that requires a quick response in the common area. memory bank m common area bank area memory bank n instruction branch save the original memory bank number. specify the address and memory bank at the destination, and execute the call instruction. vector table ? software example (when using interrupt request of 16-bit timer/event counter 00) vctbl cseg at 0020h dw bnkitm000 ; specifies an address at the timer interrupt destination. ramd dseg saddr r_bnkrn: ds 1 ; secures ram for saving the memory bank number before the interrupt occurs. bnkc cseg at 7000h bnkitm000: ; inter-memory ban k interrupt servicing routine push ax ; saves the contents of the ax register. mov a,bank mov r_bnkrn,a ; saves the memory bank number before the interrupt to ram. mov bank,#banknum test ; specifies the memory bank number of the interrupt routine. call !test ; calls the interrupt routine. mov a,r_bnkrn ; restores the memory bank number before the interrupt. mov bank,a pop ax ; restores the contents of the ax register. reti bn3 cseg bank3 test: ; interrupt servicing routine mov ??? : : ret end chapter 4 memory bank select function ( pd78f0892, 78f0893 only) user?s manual u17553ej4v0ud 88 remark note the following points to use the memory bank select function efficiently. ? allocate a routine that is used often in the common area. ? if a value that is planned to be referenced is placed in ram, it can be referenced from all of the areas. ? if the reference destination and the branch destinati on of the routine placed in a memory bank are placed in the same memory bank, then the code size and processing are more efficient. ? allocate interrupt servicing that requires a quick response in the common area. user?s manual u17553ej4v0ud 89 chapter 5 port functions 5.1 port functions there are three types of pin i/o buffer power supplies: av ref , ev dd and v dd . the relationship between these power supplies and the pins is shown below. table 5-1. pin i/o buffer power supplies power supply corresponding pins av ref p80 to p87, p90 to p97 ev dd port pins other than p80 to p87, p90 to p97 and p121 to p124 v dd ? p121 to p124 ? non-port pins 78k0/ff2 products are provided with the ports shown in figu re 5-1, which enable variety of control operations. in addition to the func tion as digital i/o ports, these ports have several alternate f unctions. for details of the alternate functions, refer to chapter 2 pin functions . the 78k0/ff2 has a total of 71 i/o ports, ports 0, 1, 3 to 9, 12 and 13. the port conf iguration is shown below. chapter 5 port functions user?s manual u17553ej4v0ud 90 figure 5-1. port types p90 p97 p30 p33 p50 p57 p10 p17 p40 p47 p60 p67 p70 p120 p132 p130 port 0 port 1 port 9 port 3 p00 p06 p05 p01 port 12 port 13 port 7 p80 p87 port 4 port 5 port 6 p76 p124 port 8 5.2 port configuration ports include the following hardware. table 5-2. port configuration item configuration control registers port mode register (pm0, pm1, pm3 to pm9, pm12, pm13) port register (p0, p1, p3 to p9, p12, p13) pull-up resistor option register (pu0, pu1, pu3 to pu7, pu12, pu13) port total: 71 (cmos i/o: 66, cmos output: 1, n-ch open drain i/o: 4) pull-up resistor total: 46 chapter 5 port functions user?s manual u17553ej4v0ud 91 5.2.1 port 0 port 0 is a 4-bit i/o port with an output latch. port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (pm0). w hen the p00, p01, p05 and p 06 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (pu0). this port can also be used for timer i/o, serial interface chip select input. reset signal generation sets port 0 to input mode. figures 5-2 and 5-3 show block diagrams of port 0. caution to use p05/ssi11/ti001 as general-purpose por ts, set serial operation mode register 11 (csim11) to the default status (00h). figure 5-2. block diagram of p00 and p05 p00/ti000, p05/ssi11/ti001 wr pu rd wr port wr pm pu00, pu05 alternate function output latch (p00, p05) pm00, pm05 ev dd p-ch selector internal bus pu0 pm0 p0 p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wr : write signal chapter 5 port functions user?s manual u17553ej4v0ud 92 figure 5-3. block diagram of p01 and p06 p01/ti010/to00, p06/ti011/to01 wr pu rd wr port wr pm pu01, pu06 alternate function output latch (p01, p06) pm01, pm06 alternate function ev dd p-ch selector internal bus pu0 pm0 p0 p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 rd: read signal wr : write signal chapter 5 port functions user?s manual u17553ej4v0ud 93 5.2.2 port 1 port 1 is an 8-bit i/o port with an output latch. port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (pm1). when the p10 to p17 pi ns are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (pu1). this port can also be used for external interrupt requ est input, serial interfac e data i/o, clock i/o, and timer i/o. reset signal generation sets port 1 to input mode. figures 5-4 to 5-6 show block diagrams of port 1. caution to use p10/sck10/txd61 and p12/so10 as ge neral-purpose ports, set serial operation mode register 10 (csim10) and serial clock selection regi ster 10 (csic10) to the default status (00h). figure 5-4. block diagram of p10, p16 and p17 p10/sck10/txd61, p16/toh1/intp5, p17/ti50/to50 wr pu rd wr port wr pm pu10, pu16, pu17 alternate function output latch (p10, p16, p17) pm10, pm16, pm17 alternate function ev dd p-ch selector internal bus pu1 pm1 p1 p1: port register 1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal chapter 5 port functions user?s manual u17553ej4v0ud 94 figure 5-5. block diagram of p11 and p14 p11/si10/rxd61, p14/rxd60 wr pu rd wr port wr pm pu11, pu14 alternate function output latch (p11, p14) pm11, pm14 ev dd p-ch selector internal bus pu1 pm1 p1 p1: port register 1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal chapter 5 port functions user?s manual u17553ej4v0ud 95 figure 5-6. block diagram of p12, p13 and p15 p12/so10, p13/txd60, p15/toh0 wr pu rd wr port wr pm pu12, pu13, pu15 output latch (p12, p13, p15) pm12, pm13, pm15 alternate function ev dd p-ch selector internal bus pu1 pm1 p1 p1: port register 1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal chapter 5 port functions user?s manual u17553ej4v0ud 96 5.2.3 port 3 port 3 is a 4-bit i/o port with an output latch. port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (pm3). when used as an input por t, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resist or option register 3 (pu3). this port can also be used for external interrupt request input and timer i/o. reset signal generation sets port 3 to input mode. figures 5-7 and 5-8 show block diagrams of port 3. cautions 1. be sure to pull th e p31 pin down before a reset release, to prevent malfunction. 2. connect p31/ti002/intp2 as follows when writ ing the flash memory wit h a flash programmer. - p31/ti002/intp2: connect to ev ss via a resistor (10 k : recommended). the above connection is no t necessary when writing the fl ash memory by means of self programming. remark p31/intp2/ti002 and p32/intp3/ti012/to02 can be used for on-chip debug mode setting when the on-chip debug function is used. for details, refer to chapter 25 on-chip debug function. figure 5-7. block diagram of p30 and p31 p30/intp1, p31/intp2/ti002 wr pu rd wr port wr pm pu30, pu31 alternate function output latch (p30, p31) pm30, pm31 ev dd p-ch selector internal bus pu3 pm3 p3 p3: port register 3 pu3: pull-up resistor option register 3 pm3: port mode register 3 rd: read signal wr : write signal chapter 5 port functions user?s manual u17553ej4v0ud 97 figure 5-8. block diagram of p32 and p33 p32/intp3/ti012/to02, p33/intp4/ti51/to51 wr pu rd wr port wr pm pu32, pu33 alternate function output latch (p32, p33) pm32, pm33 alternate function ev dd p-ch selector internal bus pu3 pm3 p3 p3: port register 3 pu3: pull-up resistor option register 3 pm3: port mode register 3 rd: read signal wr : write signal chapter 5 port functions user?s manual u17553ej4v0ud 98 5.2.4 port 4 port 4 is a 8-bit i/o port with an output latch. port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (pm4). use of an on-chip pull-up resistor can be specified in 1-bit units with pull-up resistor option register 4 (pu4). reset signal generation sets port 4 to input mode. figure 5-9 shows a block diagram of port 4. figure 5-9. block diagram of p40 to p47 rd p-ch wr pu wr port wr pm ev dd p40 to p47 pu40 to pu47 output latch (p40 to p47) pm40 to pm47 selector internal bus pu4 pm4 p4 p4: port register 4 pu4: pull-up resistor option register 4 pm4: port mode register 4 rd: read signal wr : write signal chapter 5 port functions user?s manual u17553ej4v0ud 99 5.2.5 port 5 port 5 is 8-bit i/o port with an output la tch. port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (pm5). use of an on-chip pull-up resist or can be specified in 1-bit units using pull-up resistor option register 5 (pu5). reset signal generation sets port 5 to input mode. figure 5-10 shows a block diagram of port 5. figure 5-10. block diag ram of p50 to p57 rd p-ch wr pu wr port wr pm ev dd p50 to p57 pu50 to pu57 output latch (p50 to p57) pm50 to pm57 selector internal bus pu5 pm5 p5 p5: port register 5 pu5: pull-up resistor option register 5 pm5: port mode register 5 rd: read signal wr : write signal chapter 5 port functions user?s manual u17553ej4v0ud 100 5.2.6 port 6 port 6 is a 8-bit i/o port with an output latch. port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (pm6). p64 top67 use of an on-c hip pull-up resistor can be specified in 1-bit units using pull-up resistor option register 6 (pu6). p60 to p 63 are not including pull-up resistor option register. the p60 to p63 pins are n-ch open-drain pins (6 v tolerance). reset signal generation sets port 6 to input mode. figures 5-11 and 5-12 show block diagrams of port 6. figure 5-11. block diag ram of p60 to p63 rd p60 to p63 wr port wr pm output latch (p60 to p63) pm60 to pm63 selector internal bus pm6 p6 p6: port register 6 pm6: port mode register 6 rd: read signal wr : write signal chapter 5 port functions user?s manual u17553ej4v0ud 101 figure 5-12. block diag ram of p64 to p67 rd p-ch wr pu wr port wr pm ev dd p64 to p67 pu64 to pu67 output latch (p64 to p67) pm64 to pm67 selector internal bus pu6 pm6 p6 p6: port register 6 pu6: pull-up resistor option register 6 pm6: port mode register 6 rd: read signal wr : write signal chapter 5 port functions user?s manual u17553ej4v0ud 102 5.2.7 port 7 port 7 is an 7-bit i/o port with an output latch. port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (pm7). when the p70 to p76 pi ns are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 7 (pu7). this port can also be used for external interrupt reques t input, and clock output pins, buzzer output pins, can i/f i/o, serial interface data i/o, clock i/o. reset signal generation sets port 7 to input mode. figures 5-13 to 5-17 show block diagrams of port 7. caution to use p74/so11 and p76/sck11 as general- purpose ports, set serial operation mode register 10 (csim 10) and serial clock selection resister 10 (csic10) to the default status (00h). figure 5-13. blo ck diagram of p70 p70/ctxd wr pu rd wr port wr pm pu70 output latch (p70) pm70 alternate function ev dd p-ch selector internal bus pu7 pm7 p7 p7: port register 7 pu7: pull-up resistor option register 7 pm7: port mode register 7 rd: read signal wr : write signal chapter 5 port functions user?s manual u17553ej4v0ud 103 figure 5-14. block diagram of p71 and p75 p71/crxd p75/si11 wr pu rd wr port wr pm pu71 and pu75 alternate function output latch (p71 and p75) pm71 and pm75 ev dd p-ch selector internal bus pu7 pm7 p7 p7: port register 7 pu7: pull-up resistor option register 7 pm7: port mode register 7 rd: read signal wr : write signal chapter 5 port functions user?s manual u17553ej4v0ud 104 figure 5-15. block diagram of p72 and p73 p72/pcl/intp6 p73/buz/intp7 wr pu rd wr port wr pm pu72 and pu73 alternate function output latch (p72 and p73) pm72 and pm73 alternate function ev dd p-ch selector internal bus pu7 pm7 p7 p7: port register 7 pu7: pull-up resistor option register 7 pm7: port mode register 7 rd: read signal wr : write signal chapter 5 port functions user?s manual u17553ej4v0ud 105 figure 5-16. blo ck diagram of p74 p74/so11 wr pu rd wr port wr pm pu74 output latch (p74) pm74 alternate function ev dd p-ch selector internal bus pu7 pm7 p7 p7: port register 7 pu7: pull-up resistor option register 7 pm7: port mode register 7 rd: read signal wr : write signal chapter 5 port functions user?s manual u17553ej4v0ud 106 figure 5-17. blo ck diagram of p76 p76/sck11 wr pu rd wr port wr pm pu76 output latch (p76) pm76 alternate function ev dd p-ch selector internal bus pu7 pm7 p7 alternate function p7: port register 7 pu7: pull-up resistor option register 7 pm7: port mode register 7 rd: read signal wr : write signal chapter 5 port functions user?s manual u17553ej4v0ud 107 5.2.8 port 8 port 8 is an 8-bit i/o port with an output latch. port 8 can be set to the input mode or output mode in 1-bit units using port mode register 8 (pm8). this port can also be used for a/d converter analog input. to use p80/ani0 to p87/ani7 as di gital input pins, set them in the di gital i/o mode by using the a/d port configuration register (adpc) and in the input mode by using pm8. use t hese pins starting from the lower bit. to use p80/ani0 to p87/ani7 as digi tal output pins, set them in the di gital i/o mode by using adpc and in the output mode by using pm8 (for details, see 13.3 (5) a/d port configuration register (adpc) ). table 5-3. setting functions of p80/ani0 to p87/ani7 pins adpc pm8 ads p80/ani0 to p87/ani7 pin input mode ? digital input digital i/o selection output mode ? digital output selects ani. analog input (to be converted) input mode does not select ani. analog input (not to be converted) selects ani. analog input selection output mode does not select ani. setting prohibited all p80/ani0 to p87/ani7 are set in the anal og input mode when the reset signal is generated. figure 5-18 shows a block diagram of port 8. caution make the av ref pin the same potential as the v dd pin when port 8 is used as a digital port. figure 5-18. block di agram of p80 to p87 internal bus p80/ani0 to p87/ani7 rd wr port wr pm output latch (p80 to p87) pm80 to pm87 selector pm8 a/d converter p8 p8: port register 8 pm8: port mode register 8 rd: read signal wr : write signal chapter 5 port functions user?s manual u17553ej4v0ud 108 5.2.9 port 9 port 9 is an 8-bit i/o port with an output latch. port 9 can be set to the input mode or output mode in 1-bit units using port mode register 9 (pm9). this port can also be used for a/d converter analog input. to use p90/ani8 to p97/ani15 as digital input pins, set them in the digital i/o mode by using the a/d port configuration register (adpc) and in the input mode by using pm9. use t hese pins starting from the lower bit. to use p90/ani8 to p97/ani15 as digital output pins, set them in the digital i/o mode by using adpc and in the output mode by using pm9 (for details, see 13.3 (5) a/d port configuration register (adpc) ). table 5-4. setting functions of p90/ani8 to p97/ani15 pins adpc pm9 ads p90/ani8 to p97/ani15 pin input mode ? digital input digital i/o selection output mode ? digital output selects ani. analog input (to be converted) input mode does not select ani. analog input (not to be converted) selects ani. analog input selection output mode does not select ani. setting prohibited all p90/ani8 to p97/ani15 are set in the analog input mode when the reset signal is generated. figure 5-19 shows a block diagram of port 9. caution make the av ref pin the same potential as the v dd pin when port 9 is used as a digital port. figure 5-19. block di agram of p90 to p97 internal bus p90/ani8 to p97/ani15 rd wr port wr pm output latch (p90 to p97) pm90 to pm97 selector pm9 a/d converter p9 p9: port register 9 pm9: port mode register 9 rd: read signal wr : write signal chapter 5 port functions user?s manual u17553ej4v0ud 109 5.2.10 port 12 port 12 is a 5-bit i/o port with an output latch. port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (pm12). when used as an input por t only for p120, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (pu12). this port can also be used for external interrupt input, potential input for external low-voltage detector, connecting resonator for main system clock, connecti ng resonator for subsystem clock, exter nal clock input for main system clock, external clock input for subsystem clock. reset signal generation sets port 12 to input mode. figures 5-20 and 5-21 show block diagrams of port 12. cautions 1. when using the p121 to p124 pins to co nnect a resonator for the ma in system clock (x1, x2) or subsystem clock (xt1, xt2), or to input an external clock for the main system clock (exclk) or subsystem clock (exclks), the x1 oscillation mode, xt 1 oscillation mode, or external clock input mode must be set by us ing the clock operation mode select register (oscctl) (for detail, see 6.3 (5) clock operation mode select register (oscctl)). the reset value of oscctl is 00h (all of the p121 to p124 pi ns are i/o port pins). at this time, setting of the pm121 to pm124 and p121 to p124 pins is not necessary. 2. connect p121/x1 as follows when writin g the flash memory with a flash programmer. - p121/x1: when using this pin as a port, connect it to v ss via a resistor (10 k : recommended) (in the input mode) or leave it open (in the output mode). the above connection is not necessary when writing the flash memory by means of self programming. chapter 5 port functions user?s manual u17553ej4v0ud 110 figure 5-20. blo ck diagram of p120 p120/intp0/exlvi wr pu rd wr port wr pm pu120 alternate function output latch (p120) pm120 ev dd p-ch selector internal bus pu12 pm12 p12 p12: port register 12 pu12: pull-up resistor option register 12 pm12: port mode register 12 rd: read signal wr : write signal chapter 5 port functions user?s manual u17553ej4v0ud 111 figure 5-21. block di agram of p121 to p124 p122/x2/exclk, p124/xt2/exclks rd wr port wr pm output latch (p122/p124) pm122/pm124 pm12 p12 rd wr port wr pm output latch (p121/p123) pm121/pm123 pm12 p12 exclk, oscsel/ exclks, oscsels oscctl oscsel/ oscsels oscctl p121/x1, p123/xt1 oscsel/ oscsels oscctl oscsel/oscsels oscctl internal bus selector selector exclk/exclks oscctl p12: port register 12 pu12: pull-up resistor option register 12 pm12: port mode register 12 rd: read signal wr : write signal chapter 5 port functions user?s manual u17553ej4v0ud 112 5.2.11 port 13 port 130 is a 1-bit output-only port. port 131 and 132 are 2-bit i/o port. p131 and p132 can be set to the input mode or output mode in 1-bit units using port mode register 13 (pm13). when used as an inpu t port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 13 (pu13). figures 5-22 to 5-24 show block diagrams of port 13. figure 5-22. blo ck diagram of p130 rd output latch (p130) wr port p130 internal bus p13 p13: port register 13 rd: read signal wr : write signal remark when reset is effected, p130 outputs a low level. if p130 is set to output a high level before reset is effected, the output signal of p130 ca n be dummy-output as the cpu reset signal. p130 set by software reset signal chapter 5 port functions user?s manual u17553ej4v0ud 113 figure 5-23. blo ck diagram of p131 p131/ti003 wr pu rd wr port wr pm alternate function output latch (p131) ev dd p-ch selector internal bus pu13 pm13 pu131 pm131 p13 p13: port register 13 pu13: pull-up resistor option register 13 pm13: port mode register 13 rd: read signal wr : write signal chapter 5 port functions user?s manual u17553ej4v0ud 114 figure 5-24. blo ck diagram of p132 p132/ti013/to03 wr pu rd wr port wr pm pu132 alternate function output latch (p132) pm132 alternate function ev dd p-ch selector internal bus pu13 pm13 p13 p13: port register 13 pu13: pull-up resistor option register 13 pm13: port mode register 13 rd: read signal wr : write signal chapter 5 port functions user?s manual u17553ej4v0ud 115 5.3 registers controlling port function port functions are controlled by the following three types of registers. ? port mode registers (pm0, pm1, pm3 to pm9, pm12, pm13) ? port registers (p0, p1, p3 to p9, p12, p13) ? pull-up resistor option registers (pu0, pu1, pu3 to pu7, pu12, pu13) ? a/d port configuration register (adpc) chapter 5 port functions user?s manual u17553ej4v0ud 116 (1) port mode registers (pm0, pm1, pm3 to pm9, pm12, pm13) these registers specify input or output mode for the port in 1-bit units. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets these registers to ffh except for pm13. pm13 is set to feh. when port pins are used as alternate-function pins, set t he port mode register and output latch as shown in table 5-5. figure 5-25. format of port mode register 7 1 symbol pm0 6 pm06 5 pm05 4 1 3 1 2 1 1 pm01 0 pm00 address ff20h after reset ffh r/w r/w 7 pm17 pm1 6 pm16 5 pm15 4 pm14 3 pm13 2 pm12 1 pm11 0 pm10 ff21h ffh r/w 7 1 pm3 6 1 5 1 4 1 3 pm33 2 pm32 1 pm31 0 pm30 ff23h ffh r/w 7 pm47 pm4 6 pm46 5 pm45 4 pm44 3 pm43 2 pm42 1 pm41 0 pm40 ff24h ffh r/w 7 pm57 pm5 6 pm56 5 pm55 4 pm54 3 pm53 2 pm52 1 pm51 0 pm50 ff25h ffh r/w 7 pm67 pm6 6 pm66 5 pm65 4 pm64 3 pm63 2 pm62 1 pm61 0 pm60 ff26h ffh r/w 7 1 pm7 6 pm76 5 pm75 4 pm74 3 pm73 2 pm72 1 pm71 0 pm70 ff27h ffh r/w 7 pm87 pm8 6 pm86 5 pm85 4 pm84 3 pm83 2 pm82 1 pm81 0 pm80 ff28h ffh r/w 7 pm97 pm9 6 pm96 5 pm95 4 pm94 3 pm93 2 pm92 1 pm91 0 pm90 ff29h ffh r/w 7 1 pm12 6 1 5 1 4 pm124 3 pm123 2 pm122 1 pm121 0 pm120 ff2ch ffh r/w 7 1 pm13 6 1 5 1 4 1 3 1 2 pm132 1 pm131 0 0 ff2dh feh r/w pmmn pmn pin i/o mode selection (m = 0, 1, 3 to 9, 12, 13; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 5 port functions user?s manual u17553ej4v0ud 117 table 5-5. settings of port mode register a nd output latch when using alternate function (1/2) alternate function pin name function name i/o pm p p00 ti000 input 1 ti010 input 1 p01 to00 output 0 0 ssi11 input 1 p05 ti001 input 1 ti011 input 1 p06 to01 output 0 0 input 1 sck10 output 0 1 p10 txd61 output 0 1 si10 input 1 p11 rxd61 input 1 p12 so10 output 0 0 p13 txd60 output 0 1 p14 rxd60 input 1 p15 toh0 output 0 0 toh1 output 0 0 p16 intp5 input 1 ti50 input 1 p17 to50 output 0 0 p30 intp1 input 1 intp2 input 1 p31 ti002 input 1 intp3 input 1 ti012 input 1 p32 to02 output 0 0 intp4 input 1 ti51 input 1 p33 to51 output 0 0 p70 ctxd output 0 1 p71 crxd input 1 pcl output 0 0 p72 intp6 input 1 buz output 0 0 p73 intp7 input 1 p74 so11 output 0 0 p75 si11 input 1 remark : don?t care pm : port mode register p : port output latch chapter 5 port functions user?s manual u17553ej4v0ud 118 table 5-5. settings of port mode register a nd output latch when using alternate function (2/2) alternate function pin name function name i/o pm p input 1 p76 sck11 output 0 1 p80-p87 ani0-ani7 input 1 p90-p97 ani8-ani15 input 1 intp0 input 1 p120 exlvi input 1 p121 x1 input 1 x2 input 1 p122 exclk input 1 p123 xt1 input 1 xt2 input 1 p124 exclks input 1 p131 ti003 input 1 ti013 input 1 p132 to03 output 0 0 remark : don?t care pm : port mode register p : port output latch caution when using p80/ani0 to p87/ani 7, p90/ani8 to p97/ani15 in th e input mode, not only pm8 and pm9 (input/output) but also the a/d port configuration re gister (adpc) (analog input/digital input) must be set (for details, see 13.3 (4) anal og input channel specification regi ster (ads) to (7) port mode register 9 (pm9)). the reset value of adpc is 00h (p80/ani0 to p87/ani7, p90/ani8 to p97/ani15 are all analog input pins). chapter 5 port functions user?s manual u17553ej4v0ud 119 (2) port registers (p0, p1, p3 to p9, p12, p13) these registers write the data t hat is output from the chip when data is output from a port. if the data is read in the input mode, the pin level is read. if it is read in the output mode, the value of the output latch is read. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. figure 5-26. format of port register 7 0 symbol p0 6 p06 5 p05 4 0 3 0 2 0 1 p01 0 p00 address ff00h after reset 00h (output latch) r/w r/w 7 p17 p1 6 p16 5 p15 4 p14 3 p13 2 p12 1 p11 0 p10 ff01h 00h (output latch) r/w 7 p97 p9 6 p96 5 p95 4 p94 3 p93 2 p92 1 p91 0 p90 ff09h 7 0 p3 6 0 5 0 4 0 3 p33 2 p32 1 p31 0 p30 ff03h 00h (output latch) r/w 7 p47 p4 6 p46 5 p45 4 p44 3 p43 2 p42 1 p41 0 p40 ff04h 00h (output latch) r/w 7 p57 p5 6 p56 5 p55 4 p54 3 p53 2 p52 1 p51 0 p50 ff05h 00h (output latch) r/w 7 p67 p6 6 p66 5 p65 4 p64 3 p63 2 p62 1 p61 0 p60 ff06h 00h (output latch) r/w 7 0 p7 6 p76 5 p75 4 p74 3 p73 2 p72 1 p71 0 p70 ff07h 00h (output latch) r/w 7 0 p12 6 0 5 0 4 p124 3 p123 2 p122 1 p121 0 p120 ff0ch 00h (output latch) r/w 7 0 p13 6 0 5 0 4 0 3 0 2 p132 1 p131 0 p130 ff0dh 00h (output latch) r/w 7 p87 p8 6 p86 5 p85 4 p84 3 p83 2 p82 1 p81 0 p80 ff08h 00h (output latch) 00h (output latch) r/w r/w m = 0, 1, 3 to 9, 12, 13; n = 0 to 7 pmn output data control (in output mode) input data read (in input mode) 0 output 0 input low level 1 output 1 input high level chapter 5 port functions user?s manual u17553ej4v0ud 120 (3) pull-up resistor option registers (pu0, pu1, pu3 to pu7, pu12, pu13) these registers specify whether the on-chip pull-up resistors of p00, p01, p05, p06, p10 to p 17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p76, p120, p131 and p132 are to be used or not. on-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified in pu0, pu1, pu3 to pu7, pu12, and pu13. on-chip pull-up resistors cannot be connected to bits set to output mode and bits used as alte rnate-function output pins, regardless of the settings of pu0, pu1, pu3 to pu7, pu12, and pu13. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. figure 5-27. format of pull-up resistor option register 7 0 symbol pu0 6 pu06 5 pu05 4 0 3 0 2 0 1 pu01 0 pu00 address ff30h after reset 00h r/w r/w 7 pu17 pu1 6 pu16 5 pu15 4 pu14 3 pu13 2 pu12 1 pu11 0 pu10 ff31h 00h r/w 7 0 pu3 6 0 5 0 4 0 3 pu33 2 pu32 1 pu31 0 pu30 ff33h 00h r/w 7 pu47 pu4 6 pu46 5 pu45 4 pu44 3 pu43 2 pu42 1 pu41 0 pu40 ff34h 00h r/w 7 pu57 pu5 6 pu56 5 pu55 4 pu54 3 pu53 2 pu52 1 pu51 0 pu50 ff35h 00h r/w 7 0 pu7 6 pu76 5 pu75 4 pu74 3 pu73 2 pu72 1 pu71 0 pu70 ff37h 00h r/w 7 0 pu12 6 0 5 0 4 0 3 0 2 0 1 0 0 pu120 ff3ch 00h r/w 7 0 pu13 6 0 5 0 4 0 3 0 2 pu132 1 pu131 0 0 ff3dh 00h r/w 7 pu67 pu6 6 pu66 5 pu65 4 pu64 3 0 2 0 1 0 0 0 ff36h 00h r/w pumn pumn pin on-chip pull-up resistor selection (m = 0, 1, 3 to 7, 12, 13, n = 0 to 7) 0 on-chip pull-up resistor not connected 1 on-chip pull-up resistor connected chapter 5 port functions user?s manual u17553ej4v0ud 121 (4) a/d port configuration register (adpc) this register switches the p80/ani0 to p87/ani7 and p90/ani8 to p97/ ani15 pins to digital i/o of port or analog input of a/d converter. adpc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. table 5-6. format of a/d port configuration register (adpc) analog input (a)/ digita l input (d) switching adpc4 adpc3 adpc2 adpc1 adpc0 p97/ ani15 p96/ ani14 p95/ ani13 p94/ ani12 p93/ ani11 p92/ ani10 p91/ ani9 p90/ ani8 p87/ ani7 p86/ ani6 p85/ ani5 p84/ ani4 p83/ ani3 p82/ ani2 p81/ ani1 p80/ ani0 0 0 0 0 0 a a a a a a a a a a a a a a a a 0 0 0 0 1 a a a a a a a a a a a a a a a d 0 0 0 1 0 a a a a a a a a a a a a a a d d 0 0 0 1 1 a a a a a a a a a a a a a d d d 0 0 1 0 0 a a a a a a a a a a a a d d d d 0 0 1 0 1 a a a a a a a a a a a d d d d d 0 0 1 1 0 a a a a a a a a a a d d d d d d 0 0 1 1 1 a a a a a a a a a d d d d d d d 0 1 0 0 0 a a a a a a a a d d d d d d d d 0 1 0 0 1 a a a a a a a d d d d d d d d d 0 1 0 1 0 a a a a a a d d d d d d d d d d 0 1 0 1 1 a a a a a d d d d d d d d d d d 0 1 1 0 0 a a a a d d d d d d d d d d d d 0 1 1 0 1 a a a d d d d d d d d d d d d d 0 1 1 1 0 a a d d d d d d d d d d d d d d 0 1 1 1 1 a d d d d d d d d d d d d d d d 1 0 0 0 0 d d d d d d d d d d d d d d d d other than above setting prohibited cautions 1. set the channel used for a/d conversion to the input m ode by using port mode register 8 (pm8) and port mode register 9 (pm9). 2. if data is written to adpc, a wait cycle is generated. do not write data to adpc when the cpu is operating on the subsystem clock and th e peripheral hardware clock is stopped. for details, see chapter 31 cautions for wait. chapter 5 port functions user?s manual u17553ej4v0ud 122 5.4 port function operations port operations differ depending on whether the inpu t or output mode is set, as shown below. 5.4.1 writing to i/o port (1) output mode a value is written to the output latch by a transfer instruct ion, and the output latch content s are output from the pin. once data is written to the output latch, it is reta ined until data is written to the output latch again. the data of the output latch is cleared by reset. (2) input mode a value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. once data is written to the output latch, it is reta ined until data is written to the output latch again. 5.4.2 reading from i/o port (1) output mode the output latch contents ar e read by a transfer instruction. t he output latch content s do not change. (2) input mode the pin status is read by a transfer instruct ion. the output latch c ontents do not change. 5.4.3 operations on i/o port (1) output mode an operation is performed on the output latch contents, and the result is wr itten to the output latch. the output latch contents are output from the pins. once data is written to the output latch, it is reta ined until data is written to the output latch again. the data of the output latch is cleared by reset. (2) input mode the pin level is read and an operation is performed on its cont ents. the result of the op eration is written to the output latch, but since the output buffer is off, the pin status does not change. chapter 5 port functions user?s manual u17553ej4v0ud 123 5.5 cautions on 1-bit manipulation in struction for port register n (pn) when a 1-bit manipulation instruction is executed on a por t that provides both input and output functions, the output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit. therefore, it is recommended to rewr ite the output latch when switching a port from input mode to output mode. user?s manual u17553ej4v0ud 124 chapter 6 clock generator 6.1 functions of clock generator the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following system clocks and clock oscillators are selectable. (1) main system clock <1> x1 oscillator this circuit oscillates a clock of f x = 4 to 20 mhz. oscillation can be stopped by executing the stop instruction or using the main osc control register (moc). <2> internal high-speed oscillator this circuit oscillates a clock of f rh = 8 mhz (typ.). after a reset release, the cpu always starts operating with this internal high-speed oscillation clock. oscillation can be stopped by executing the stop instruction or using the intern al oscillator mode register (rcm). an external main system clock (f exclk = 4 to 20 mhz) can also be supplied from the exclk pin. as the main system clock, a high-speed syst em clock (x1 clock or external main system clock) or internal high-speed oscillation clock can be selected by using the main clock mode register (mcm). (2) subsystem clock ? subsystem clock oscillator this circuit oscillates at a frequency of f xt = 32.768 khz. oscillation can be stopped by using the processor clock control register (pcc) and clock operation mode se lect register (oscctl). an external subsystem clock (f exclks = 32.768 khz) can also be supplied from the exclks pin. (3) internal low-speed oscillation clock (clock for watchdog timer) ? internal low-speed oscillator this circuit oscillates a clock of f rl = 240 khz (typ.). after a reset release, the internal low-speed oscillation clock always starts operat ing. oscillation can be stopped by using the internal oscillator mode register (rcm). the internal low-speed oscillation clock cannot be us ed as the cpu clock. the following hardware operates with the internal low-speed oscillation clock. ? watchdog timer ? tmh1 (f rl , f rl /2 7 , f rl /2 9 ) remarks 1. f x : x1 clock oscillation frequency 2. f rh : internal high-speed oscillation clock frequency 3. f exclk : external main system clock frequency 4. f xt : xt1 clock oscillation frequency 5. f exclks : external subsystem clock frequency 6. f rl : internal low-speed oscillation clock frequency chapter 6 clock generator user?s manual u17553ej4v0ud 125 6.2 configuration of clock generator the clock generator includes the following hardware. table 6-1. configuration of clock generator item configuration control registers processor clock control register (pcc) internal oscillator mode register (rcm) main clock mode register (mcm) main osc control register (moc) clock operation mode select register (oscctl) oscillation stabilization time counter status register (ostc) oscillation stabilization time select register (osts) oscillators x1 oscillator xt1 oscillator internal high-speed oscillator internal low-speed oscillator chapter 6 clock generator user?s manual u17553ej4v0ud 126 figure 6-1. block diag ram of clock generator option byte 1: cannot be stopped 0: can be stopped internal oscillato r mode register (rcm) lsrstop rsts rstop internal high-speed oscillator (8 mhz (typ.)) internal low-speed oscillator (240 khz (typ.)) f rl clock operation mode select register (oscctl) oscsels exclks xt1/p123 xt2/exclks/ p124 f sub peripheral hardware clock (f prs ) watchdog timer, 8-bit timer h1 watch timer 1/2 cpu clock (f cpu ) processor clock control register (pcc) css pcc2 cls pcc1 pcc0 prescaler main system clock switch f xp peripheral hardware clock switch x1 oscillation stabilization time counter osts1 osts0 osts2 oscillation stabilization time select register (osts) 3 most 16 most 15 most 14 most 13 most 11 oscillation stabilization time counter status register (ostc) controller mcm0 xsel mcs mstop stop exclk oscsel amph clock operation mode select register (oscctl) 4 f xp 2 f xp 2 2 f xp 2 3 f xp 2 4 main clock mode register (mcm) main clock mode register (mcm) main osc control register (moc) f rh internal bus internal bus high-speed system clock oscillator crystal/ceramic oscillation external input clock x1/p121 x2/exclk/ p122 f xh f sub 2 crystal oscillation external input clock subsystem clock oscillator f x f exclk f xt f exclks selector chapter 6 clock generator user?s manual u17553ej4v0ud 127 remarks 1. f x : x1 clock oscillation frequency 2. f rh : internal high-speed oscillation clock frequency 3. f exclk : external main system clock frequency 4. f xh : high-speed system clock oscillation frequency 5. f xp : main system clock oscillation frequency 6. f prs : peripheral hardware clock frequency 7. f cpu : cpu clock oscillation frequency 8. f xt : xt1 clock oscillation frequency 9. f exclks : external subsystem clock frequency 10. f sub : subsystem clock frequency 11. f rl : internal low-speed oscillation clock frequency 6.3 registers controlling clock generator the following seven registers are used to control the clock generator. ? processor clock control register (pcc) ? internal oscillator mode register (rcm) ? main clock mode register (mcm) ? main osc control register (moc) ? clock operation mode sele ct register (oscctl) ? oscillation stabilization time c ounter status register (ostc) ? oscillation stabilization time select register (osts) (1) processor clock control register (pcc) this register is used to select the cpu clock and the division ratio. pcc is set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pcc to 01h. chapter 6 clock generator user?s manual u17553ej4v0ud 128 figure 6-2. format of processor clock control register (pcc) address: fffbh after reset: 01h r/w note 1 symbol 7 6 <5> <4> 3 2 1 0 pcc 0 0 cls css 0 pcc2 pcc1 pcc0 cls cpu clock status 0 main system clock 1 subsystem clock notes 1. bit 5 is read-only. 2. be sure to switch css from 1 to 0 when bits 1 (mcs) and 0 (mcm0) of the main clock mode register (mcm) are 1. caution be sure to clear bits 3 and 6 to 0. remarks 1. f xp : main system clock oscillation frequency 2. f sub : subsystem clock frequency the fastest instruction can be executed in 2 clocks of the cpu clock in the 78k0/ff2. therefore, the relationship between the cpu clock (f cpu ) and the minimum instruction execution time is as shown in table 6-2. table 6-2. relationship between cpu clo ck and minimum instruction execution time minimum instruction execution time: 2/f cpu high-speed system clock note internal high-speed oscillation clock note subsystem clock cpu clock (f cpu ) at 10 mhz operation at 20 mhz operation at 8 mhz (typ.) operation at 32.768 khz operation f xp 0.2 s 0.1 s 0.25 s (typ.) ? f xp /2 0.4 s 0.2 s 0.5 s (typ.) ? f xp /2 2 0.8 s 0.4 s 1.0 s (typ.) ? f xp /2 3 1.6 s 0.8 s 2.0 s (typ.) ? f xp /2 4 3.2 s 1.6 s 4.0 s (typ.) ? f sub /2 ? ? 122.1 s note the main clock mode register (mcm) is used to se t the cpu clock (high-speed system clock/internal high-speed oscillation clock) (see figure 6-4 ). css note 2 pcc2 pcc1 pcc0 cpu clock (f cpu ) selection 0 0 0 f xp 0 0 1 f xp /2 (default) 0 1 0 f xp /2 2 0 1 1 f xp /2 3 0 1 0 0 f xp /2 4 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 0 f sub /2 other than above setting prohibited chapter 6 clock generator user?s manual u17553ej4v0ud 129 (2) internal oscillator mode register (rcm) this register sets the operation mode of internal oscillator. rcm can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 80h note 1 . figure 6-3. format of internal oscillator mode register (rcm) address: ffa0h after reset: 80h note 1 r/w note 2 symbol <7> 6 5 4 3 2 <1> <0> rcm rsts 0 0 0 0 0 lsrstop rstop rsts status of internal high-speed oscillator oscillation 0 waiting for stabilization of internal high-spee d oscillator oscillation in high-accuracy mode (internal high-speed oscillator oper ation in low-accuracy mode) 1 internal high-speed oscillato r operation in high-accuracy mode lsrstop internal low-speed oscillator oscillating/stopped 0 internal low-speed oscillator 1 internal low-s peed oscillator stopped rstop internal high-speed oscillator oscillating/stopped 0 internal high-spe ed oscillator oscillating 1 internal high-speed oscillator stopped notes 1. the value of this register is 00h immedi ately after a reset release but automatically changes to 80h after internal high-speed oscillator oscillation has been stabilized. 2. bit 7 is read-only. caution when setting rstop to 1, be sure to confirm that the cpu operates with a clock other than the internal high -speed oscillation clock. specifically, set rstop to 1 under either of the following conditions. ? when mcs = 1 (when cpu operates with the high-speed system clock) ? when cls = 1 (when cpu opera tes with the subsystem clock) chapter 6 clock generator user?s manual u17553ej4v0ud 130 (3) main clock mode register (mcm) this register selects the main system clock supplied to cpu clock and clock supplied to peripheral hardware clock. mcm can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 6-4. format of main clock mode register (mcm) address: ffa1h after reset: 00h r/w note symbol 7 6 5 4 3 <2> <1> <0> mcm 0 0 0 0 0 xsel mcs mcm0 selection of clock supplied to main system clock and peripheral hardware xsel mcm0 main system clock (f xp ) peripheral hardware clock (f prs ) 0 0 0 1 internal high-speed oscillation clock (f rh ) 1 0 internal high-speed oscillation clock (f rh ) 1 1 high-speed system clock (f xh ) high-speed system clock (f xh ) mcs main system clock status 0 operates with internal high-speed oscillation clock 1 operates with hi gh-speed system clock note bit 1 is read-only. cautions 1. xsel can be change d only once after a reset release. 2. the peripheral hardware cannot operate when the pe ripheral hardware clock is stopped. to resume the operation of the peripheral ha rdware after the peripheral hardware clock has been stoppe d, initialize the peripheral hardware. 3. a clock other than f prs is supplied to the following peripheral functions regardless of the se tting of xsel and mcm0. ? watchdog timer ? when ?f rl /2 7 ? is selected as the count clock for 8-bit timer h1 ? peripheral hardware selects the ext ernal clock as the clock source (except when the external count clock of tm 0n (n = 0, 1) is selected (ti00n pin valid edge)) 4. it takes one clock to change the cpu clock. chapter 6 clock generator user?s manual u17553ej4v0ud 131 (4) main osc control register (moc) this register selects the operati on mode of the high-speed system clock. this register is used to stop the x1 oscillator or to disable an external clock input from the exclk pin when the cpu operates with a clock other than the high-speed system clock. moc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 80h. figure 6-5. format of main osc control register (moc) address: ffa2h after reset: 80h r/w symbol <7> 6 5 4 3 2 1 0 moc mstop 0 0 0 0 0 0 0 control of high-speed system clock operation mstop x1 oscillation mode external clock input mode 0 x1 oscillator operating external clock from exclk pin is enabled 1 x1 oscillator stopped external clock from exclk pin is disabled cautions 1. when setting ms top to 1, be sure to confirm that the cpu operates with a clock other than the high-speed system clock. specifical ly, set mstop to 1 under either of the following conditions. ? when mcs = 0 (when cpu operates with the internal high-speed oscillation clock) ? when cls = 1 (when cpu operat es with the subsystem clock) in addition, stop peripheral hardware th at is operating on the high-speed system clock before setting mstop to 1. 2. do not clear mstop to 0 while bit 6 (oscsel) of the clock operation mode select register (oscctl) is 0. 3. the peripheral hardware cannot operate when the pe ripheral hardware clock is stopped. to resume the operation of the peripheral hardware after the peripheral hardware clock has been stopped, in itialize the peri pheral hardware. chapter 6 clock generator user?s manual u17553ej4v0ud 132 (5) clock operation mode select register (oscctl) this register selects the operation modes of the high-speed system and subsystem clocks. oscctl can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 6-6. format of clock operati on mode select register (oscctl) address: ffefh after reset: 00h r/w symbol <7> <6> <5> <4> 3 2 1 <0> oscctl exclk oscsel exclks oscsels 0 0 0 amph exclk oscsel high-speed system clock operation mode p121/x1 pin p122/x2/exclk pin 0 0 i/o port mode i/o port 0 1 x1 oscillation mode crystal/ceramic resonator connection 1 0 i/o port mode i/o port 1 1 external clock input mode i/o port external clock input exclks oscsels subsystem clock operation mode p123/xt1 pin p124/xt2/exclks pin 0 0 i/o port mode i/o port 0 1 xt1 oscillation mode crystal resonator connection 1 0 i/o port mode i/o port 1 1 external clock input mode i/o port external clock input amph operating frequency control 0 4 mhz f xh 10 mhz 1 10 mhz < f xh 20 mhz cautions 1. be sure to set amph to 1 if the high-speed system cl ock oscillation frequency exceeds 10 mhz. 2. set amph before setting the peripheral functions after a reset release. the value of amph can be changed only once after a reset release. wh en the high-speed system clock (x1 oscillation) is selected as the cpu clock, supply of the cpu clock is stopped for 4.06 to 16.12 s after amph is set to 1. when the high- speed system clock (externa l clock input) is selected as the cpu clock, supply of the cpu clock is stopped for the duratio n of 160 external clocks after amph is set to 1. 3. if the stop instruction is executed wh en amph = 1, supply of the cpu clock is stopped for 4.06 to 16.12 s after the stop mode is re leased when the internal high-speed oscillation clock is selected as the cp u clock, or for the duration of 160 external clocks when th e high-speed system clock (external clock input) is selected as the cpu clo ck. when the high -speed system clock (x1 oscillation) is selected as the cpu cl ock, the oscillation stabilizatio n time is counted after the stop mode is released. 4. amph can be changed only once after a reset release. chapter 6 clock generator user?s manual u17553ej4v0ud 133 cautions 5. to change the value of exclk a nd oscsel, be sure to confirm that bit 7 (mstop) of the main osc control register (moc) is 1 (the x1 oscillator stops or the external clock from the exclk pin is disabled). 6. to change the value of exclks and os csels, confirm that bit 5 (cls) of the processor clock control register (pcc) is 0 (the cpu is operating with the high- speed system clock). remark f xh : high-speed system clock oscillation frequency chapter 6 clock generator user?s manual u17553ej4v0ud 134 (6) oscillation stabilization time c ounter status register (ostc) this is the status register of t he x1 clock oscillation stabilization time counter. if the internal high-speed oscillation clock or subsystem clock is used as the cpu clock, the x1 clo ck oscillation stabilization time can be checked. ostc can be read by a 1-bit or 8-bit memory manipulation instruction. when reset is released (reset by reset input, poc, lv i, and wdt), the stop instruction and mstop (bit 7 of moc register) = 1 clear ostc to 00h. figure 6-7. format of oscillation stabilizati on time counter status register (ostc) address: ffa3h after reset: 00h r symbol 7 6 5 4 3 2 1 0 ostc 0 0 0 most11 most 13 most14 most15 most16 most11 most13 most14 most15 most16 oscillation stabilization time status f x = 10 mhz f x = 20 mhz 1 0 0 0 0 2 11 /f x min. 204.8 s min. 102.4 s min. 1 1 0 0 0 2 13 /f x min. 819.2 s min. 409.6 s min. 1 1 1 0 0 2 14 /f x min. 1.64 ms min. 819.2 s min. 1 1 1 1 0 2 15 /f x min. 3.27 ms min. 1.64 ms min. 1 1 1 1 1 2 16 /f x min. 6.55 ms min. 3.27 ms min. cautions 1. after the above time has elapsed, th e bits are set to 1 in order from most11 and remain 1. 2. if the stop mode is entered and th en released while the internal high-speed oscillation clock or subsystem clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc after stop mode is released. 3. the x1 clock oscillation stabilization wa it time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency chapter 6 clock generator user?s manual u17553ej4v0ud 135 (7) oscillation stabilization time select register (osts) this register is used to select the x1 clock oscillati on stabilization wait time when the stop mode is released. the wait time set by osts is valid only after the st op mode is released with the x1 clock selected as the cpu clock. after the stop mode is released with the inte rnal high-speed oscillation clock or subsystem clock selected as the cpu clock, the oscillation st abilization time must be confirmed by ostc. osts can be set by an 8-bit memory manipulation instruction. reset signal generation sets osts to 05h. figure 6-8. format of oscillation stabiliz ation time select register (osts) address: ffa4h after reset: 05h r/w symbol 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 osts2 osts1 osts0 osts2 osts1 osts0 oscillation stabilization time selection f x = 10 mhz f x = 20 mhz 0 0 1 2 11 /f x 204.8 s 102.4 s 0 1 0 2 13 /f x 819.2 s 409.6 s 0 1 1 2 14 /f x 1.64 ms 819.2 s 1 0 0 2 15 /f x 3.27 ms 1.64 ms 1 0 1 2 16 /f x 6.55 ms 3.27 ms other than above setting prohibited cautions 1. to set the stop mode when the x1 clock is used as the cpu clock, set osts before executing the stop instruction. 2. do not change the value of the osts register during the x1 clock oscillation stabilization time. 3. if the stop mode is entered and th en released while the internal high-speed oscillation clock or subsystem clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc after stop mode is released. 4. the x1 clock oscillation stabilization wa it time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency chapter 6 clock generator user?s manual u17553ej4v0ud 136 6.4 system clock oscillator 6.4.1 x1 oscillator the x1 oscillator oscillates with a cryst al resonator or ceramic resonator (4 to 20 mhz) connected to the x1 and x2 pins. an external clock can also be input. in this case, input the clock signal to the exclk pin. figure 6-9 shows an example of the exte rnal circuit of the x1 oscillator. figure 6-9. example of extern al circuit of x1 oscillator (a) crystal or ceramic osc illation (b) external clock v ss x1 x2 crystal resonator or ceramic resonator exclk external clock cautions are listed on the next page. 6.4.2 xt1 oscillator the xt1 oscillator oscillates with a crystal resonator (standard: 32.768 khz) connected to the xt1 and xt2 pins. an external clock can also be input. in this case, input the clock signal to the exclks pin. figure 6-10 shows an example of the exte rnal circuit of the xt1 oscillator. figure 6-10. example of extern al circuit of xt1 oscillator (a) crystal oscillation (b) external clock xt2 v ss xt1 32.768 khz exclks external clock cautions are listed on the next page. chapter 6 clock generator user?s manual u17553ej4v0ud 137 caution when using the x1 oscillator and xt1 osc illator, wire as follows in the area enclosed by the broken lines in the figures 6-9 and 6-10 to avoid an adverse e ffect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lin es. do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the os cillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. note that the xt1 oscillator is designed as a low-amplit ude circuit for reducing power consumption. figure 6-11 shows examples of incorrect resonator connection. figure 6-11. examples of incorr ect resonator connection (1/2) (a) too long wiring (b) crossed signal line x2 v ss x1 x1 v ss x2 port remark when using the subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. also, insert resistors in series on the xt2 side. chapter 6 clock generator user?s manual u17553ej4v0ud 138 figure 6-11. examples of incorr ect resonator connection (2/2) (c) wiring near high alternating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) v ss x1 x2 v ss x1 x2 ab c pmn v dd high current high current (e) signals are fetched v ss x1 x2 remark when using the subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. also, insert resistors in series on the xt2 side. caution when x2 and xt1 are wired in parallel, the cr osstalk noise of x2 may in crease with xt1, resulting in malfunctioning. chapter 6 clock generator user?s manual u17553ej4v0ud 139 6.4.3 when subsystem clock is not used if it is not necessary to use the subsystem clock for low power consumption operat ions, or if not using the subsystem clock as an i/o port, set the xt1 and xt2 pins to i/o mode (oscsels = 0) and connect them as follows. input (pm123/pm124 = 1): i ndependently connect to v dd or v ss via a resistor. output (pm123/pm124 = 0): leave open. remark oscsels: bit 4 of clock operati on mode select register (oscctl) pm123, pm124: bits 3 and 4 of port mode register 12 (pm12) 6.4.4 internal hi gh-speed oscillator the internal high-speed oscillator is incorporated in the 78 k0/ff2. oscillation can be controlled by the internal oscillator mode register (rcm). after a reset release, the inter nal high-speed oscillation clock st arts oscillation (8 mhz (typ.)). 6.4.5 internal low-speed oscillator the internal low-speed oscillator is incorporated in the 78k0/ff2. the internal low-speed oscillation clock is only used as the watchdog timer and the clock of 8-bit timer h1. the internal low-speed oscillation clock cannot be used as the cpu clock. ?can be stopped by software? or ?cannot be stopped? ca n be selected by the option byte. when ?can be stopped by software? is set, oscillation can be controlled by the internal oscillator mode register (rcm). after a reset release, the internal low-speed oscillat ion clock starts oscillation and the watchdog timer is operated (240 khz (typ.)). 6.4.6 prescaler the prescaler generates various clocks by dividing the main system clock when the ma in system clock is selected as the clock to be supplied to the cpu. chapter 6 clock generator user?s manual u17553ej4v0ud 140 6.5 clock generator operation the clock generator generates the following clocks and contro ls the operation modes of the cpu, such as standby mode. ? main system clock f xp ? high-speed system clock f xh x1 clock f x external main system clock f exclk ? internal high-speed oscillation clock f rh ? subsystem clock f sub ? xt1 clock f xt ? external subsystem clock f exclks ? internal low-speed oscillation clock f rl ? cpu clock f cpu ? peripheral hardware clock f prs the cpu starts operation when the on-chip internal high-s peed oscillator starts outputting after a reset release in the 78k0/ff2, thus enabling the following. (1) enhancement of security function when the x1 clock is set as the cpu clock by the defaul t setting, the device cannot operate if the x1 clock is damaged or badly connected and therefore does not operate after reset is released. however, the start clock of the cpu is the on-chip internal high-speed oscillation cl ock, so the device can be st arted by the internal high- speed oscillation clock after a reset release. consequently, the system c an be safely shut down by performing a minimum operation, such as acknowledging a reset source by software or performing safety processing when there is a malfunction. (2) improvement of performance because the cpu can be started with out waiting for the x1 clock oscillation stabilization time, the total performance can be improved. a timing diagram of the cpu default start using the inter nal high-speed oscillation clock is shown in figure 6-12 and 6-13. chapter 6 clock generator user?s manual u17553ej4v0ud 141 figure 6-12 operation of the clock generating circuit when power supply voltage injection (when 1.59 v poc mode setup (option byte: lvistart = 0)) internal high-speed oscillation clock (f rh ) cpu clock high-speed system clock (f xh ) (when x1 oscillation selected) internal high-speed oscillation clock high-speed system clock switched by software subsystem clock (f sub ) (when xt1 oscillation selected) subsystem clock x1 clock oscillation stabilization time: 2 11 /f x to 2 16 /f x note 2 starting x1 oscillation is set by software. starting xt1 oscillation is set by software. reset processing (11 to 45 s) <3> waiting for voltage stabilization internal reset signal 0 v 1.59 v (typ.) 1.8 v 0.5 v/ms (min.) power supply voltage (v dd ) <1> <2> <4> <5> <5> <4> note 1 (1.93 to 5.39 ms) <1> the internal reset signal by the power-on clear (poc) circuit is generated after a power supply injection. <2> if power supply voltage exceeds 1.59 v (typ.), reset will be released and the oscillation start of the high- speed oscillator will be carried out automatically. <3> if power supply voltage is rose by inc lination of 0.5 v/ms (max. ), after the voltage stable waiting time of a power supply/regulator passed after reset release and reset processing will be performed, cpu carries out a start of operation with high- speed oscillation clock . <4> one clock or xt1 clock should set up an oscillation start by software (see (1) in 6.6.1 controlling high- speed system clock and (1) in 6.6.3 example of controlling subsystem clock ). <5> when you change cpu to x1 clock or xt1 clock, set up a change by software after the oscillation stability waiting of a clock (see (3) in 6.6.1 controlling hi gh-speed system clock and (3) in 6.6.3 example of controlling subsystem clock ). notes 1. the internal voltage stabilization time includes the o scillation accuracy stabilization time of the internal high-speed oscillation clock. 2. when releasing a reset (above figure) or releas ing stop mode while the cpu is operating on the internal high-speed oscillation clock, confirm the osci llation stabilization time for the x1 clock using the oscillation stabilization time count er status register (ostc). if the cpu operates on the high-speed system clock (x1 oscillation), set the oscillation st abilization time when releasing stop mode using the oscillation stabilization time select register (osts). chapter 6 clock generator user?s manual u17553ej4v0ud 142 cautions 1. when the standup of voltage until it reach es 1.8 v from the time of a power supply injection is looser than 0.5 v/ms (max.), input a low level into reset pi n, or set up 2.7 v/1.59 v poc mode (lvistart = 1) from an option byte until it reaches 1.8 v from the time of a power supply injection (refer to figure 6-13). when a low level is inputted into reset pin until it reaches 1.8 v, after the reset release by reset pin operates to the same timing as <2> of figure 6-12 or subsequent ones. 2. when using the external clock input from exclk pin and exclks pi n, oscillation stable waiting time is unnecessary. remark the clock which is not used as a cpu clo ck can be suspended by setup of software during microcomputer operation. moreover, high-speed osci llation clock and a high-speed system clock can suspend a clock by execution of a stop command (see (4) in 6.6.1 controlling high-speed system clock , (3) in 6.6.2 example of controlling inte rnal high-speed oscillation clock , and (4) in 6.6.3 example of controlling subsystem clock ). chapter 6 clock generator user?s manual u17553ej4v0ud 143 figure 6-13 operation of the clock generating circuit when power supply voltage injection (when 2.7 v/1.59v poc mode setup (option byte: lvistart = 1)) internal high-speed oscillation clock (f rh ) cpu clock high-speed system clock (f xh ) (when x1 oscillation selected) internal high-speed oscillation clock high-speed system clock switched by software subsystem clock (f sub ) (when xt1 oscillation selected) subsystem clock x1 clock oscillation stabilization time: 2 11 /f x to 2 16 /f x note starting x1 oscillation is set by software. starting xt1 oscillation is set by software. waiting for oscillation accuracy stabilization (86 to 361 s) internal reset signal 0 v 2.7 v (typ.) power supply voltage (v dd ) <1> <3> <2> <4> <5> reset processing (11 to 45 s) <4> <5> <1> the internal reset signal by the power-on clear (poc) circuit is generated after a power supply injection. <2> if power supply voltage exceeds 1.59 v (typ.), rese t will be canceled and the oscillation start of the high- speed oscillator will be carried out automatically. <3> after reset release, after reset processing is perfo rmed, cpu carries out a start of operation with high-speed oscillation clock. <4> x1 clock or xt1 clock should set up an oscillation start by software (see (1) in 6.6.1 controlling high- speed system clock and (1) in 6.6.3 example of cont rolling subsystem clock ). <5> when you change cpu to x1 clock or xt1 clock, se t up a change by software after the oscillation stability waiting of a clock (see (3) in 6.6.1 controlling high-speed system clock and (3) in 6.6.3 example of controlling subsystem clock ). note check the oscillation stable time of x1 clock with an oscillation stable time counter status register (ostc) when stop mode release in case the time of rese t release (figure 6-13) and a cpu clock are high-speed oscillation clocks . moreover, when a cpu clock is a high-speed system cl ock (x1 oscillation), set up the oscillation stable time at the time of stop mode release by the oscillati on stable time selection register (osts). cautions 1. a voltage oscillation stabilization time of 1.93 to 5.39 ms is require d after the supply voltage reaches 1.59 v (typ.). if the s upply voltage rises from 1.59 v (t yp.) to 2.7 v (typ.) within 1.93 ms, the power supply oscillation stabilization ti me of 0 to 5.39 ms is automatically generated before reset processing. 2. it is not necessary to wait for the oscillation stabilization ti me when an external clock input from the exclk and exc lks pins is used. chapter 6 clock generator user?s manual u17553ej4v0ud 144 remark the clock which is not used as a cpu clock can be suspended by setup of software during microcomputer operation. moreover, high-speed osc illation clock and a high-speed system clock can suspend a clock by execution of a stop command (see (4) in 6.6.1 controlling high-speed system clock, (3) in 6.6.2 example of controlling internal high-speed oscillation clock, and (4) in 6.6.3 example of controlling subsystem clock ). 6.6 controlling clock 6.6.1 controlling hi gh-speed system clock the following two types of high-s peed system clocks are available. ? x1 clock: crystal/ceramic resonator is connected across the x1 and x2 pins. ? external main system clock: exter nal clock is input to the exclk pin. when the high-speed system clock is not used, the x1/p 121 and x2/exclk/p122 pins can be used as i/o port pins. caution the x1/p121 and x2/exclk/p122 pins are in the i/o port mode after a reset release. the following describes examples of setti ng procedures for the following cases. (1) when oscillating x1 clock (2) when using external main system clock (3) when using high-speed system clock as cpu clock and peripheral hardware clock (4) when stopping high-speed system clock (1) example of setting procedure when oscillating the x1 clock <1> setting frequency (oscctl register) using amph, set the gain of the on-chip osci llator according to the frequency to be used. amph note operating frequency control 0 4 mhz f xh 10 mhz 1 10 mhz < f xh 20 mhz note set amph before setting the peripheral functions a fter a reset release. the value of amph can be changed only once after a reset release. when amph is set to 1, the clock supply to the cpu is stopped for 4.06 to 16.12 s. remark f xh : high-speed system clock oscillation frequency <2> setting p121/x1 and p122/x2/exclk pins and selecti ng x1 clock or external clock (oscctl register) when exclk is cleared to 0 and oscsel is set to 1, the mode is switched from port mode to x1 oscillation mode. exclk oscsel operation mode of high- speed system clock pin p121/x1 pin p122/x2/exclk pin 0 1 x1 oscillation mode crystal/ceramic resonator connection <3> controlling oscillation of x1 clock (moc register) if mstop is cleared to 0, the x1 oscillator starts oscillating. chapter 6 clock generator user?s manual u17553ej4v0ud 145 <4> waiting for the stabilization of the oscillation of x1 clock check the ostc register and wait for the necessary time. during the wait time, other software processing c an be executed with the internal high-speed oscillation clock. cautions 1. do not change the value of exclk and oscsel while the x1 clock is operating. 2. set the x1 clock after th e supply voltage has r eached the operable volt age of the clock to be used (see chapter 27 electrical spec ifications ((a) grade products) or chapter 28 electrical specificat ions ((a2) grade products)). (2) example of setting procedure when using the external main system clock <1> setting frequency (oscctl register) using amph, set the frequency to be used. amph note operating frequency control 0 4 mhz f xh 10 mhz 1 10 mhz < f xh 20 mhz note set amph before setting the peripheral functions a fter a reset release. the value of amph can be changed only once after a reset release. the clock supply to the cpu is stopped for the duration of 160 external clocks after amph is set to 1. remark f xh : high-speed system clock oscillation frequency <2> setting p121/x1 and p122/x2/exclk pins and selecting operation mode (oscctl register) when exclk and oscsel are set to 1, the mode is switched from port mode to external clock input mode. exclk oscsel operation mode of high- speed system clock pin p121/x1 pin p122/x2/exclk pin 1 1 external clock input mode i/o port external clock input <3> controlling external main system clock input (moc register) when mstop is cleared to 0, the input of the external main system clock is enabled. cautions 1. do not change the value of exclk a nd oscsel while the external main system clock is operating. 2. set the external main system clock afte r the supply voltage h as reached the operable voltage of the clock to be used (see chapter 27 electrical specifications ((a) grade products) or chapter 28 el ectrical specifications ((a2) grade products)). (3) example of setting procedure when using high-speed system clo ck as cpu clock and peripheral hardware clock <1> setting high-speed system clock oscillation note (see 6.6.1 (1) example of setting proce dure when oscillating the x1 clock and (2) example of setting procedure when using th e external main system clock. ) note the setting of <1> is not necessary when hi gh-speed system clock is already operating. chapter 6 clock generator user?s manual u17553ej4v0ud 146 <2> setting the high-speed system clock as the main system clock (mcm register) when xsel and mcm0 are set to 1, the high-speed syst em clock is supplied as the main system clock and peripheral hardware clock. selection of main system clock and clock supplied to peripheral hardware xsel mcm0 main system clock (f xp ) peripheral hardware clock (f prs ) 1 1 high-speed system clock (f xh ) high-speed system clock (f xh ) caution if the high-speed system clock is selected as the main syst em clock, a clock other than the high-speed system clock cannot be set as the peripheral hardware clock. <3> setting the main system clock as the cpu clo ck and selecting the division ratio (pcc register) when css is cleared to 0, the main system clock is supplied to the cpu. to select the cpu clock division ratio, use pcc0, pcc1, and pcc2. css pcc2 pcc1 pcc0 cpu clock (f cpu ) selection 0 0 0 f xp 0 0 1 f xp /2 (default) 0 1 0 f xp /2 2 0 1 1 f xp /2 3 1 0 0 f xp /2 4 0 other than above setting prohibited (4) example of setting procedure when stopping the high-speed system clock the high-speed system clock can be st opped in the foll owing two ways. ? executing the stop instruction and stopping the x1 oscillation (disabling clock input if the external clock is used) ? setting mstop to 1 and stopping the x1 oscillation (dis abling clock input if the external clock is used) (a) to execute a stop instruction <1> setting to stop peripheral hardware stop peripheral hardware that c annot be used in the stop mode (f or peripheral hardware that cannot be used in stop mode, see chapter 18 standby function ). <2> setting the x1 clock oscillation st abilization time after standby release when the cpu is operating on the x1 clock, set t he value of the osts r egister before the stop instruction is executed. <3> executing the stop instruction when the stop instruction is ex ecuted, the system is placed in the stop mode and x1 oscillation is stopped (the input of the ex ternal clock is disabled). chapter 6 clock generator user?s manual u17553ej4v0ud 147 (b) to stop x1 oscillation (disabling exter nal clock input) by setting mstop to 1 <1> confirming the cpu clock st atus (pcc and mcm registers) confirm with cls and mcs that the cpu is oper ating on a clock other than the high-speed system clock. when cls = 0 and mcs = 1, the high-speed system cl ock is supplied to the cpu, so change the cpu clock to the subsystem clock or internal high-speed oscillation clock. cls mcs cpu clock status 0 0 internal high-speed oscillation clock 0 1 high-speed system clock 1 subsystem clock <2> stopping the high-speed system clock (moc register) when mstop is set to 1, x1 oscillation is stopp ed (the input of the external clock is disabled). caution be sure to confirm that mcs = 0 or cls = 1 when setting mstop to 1. in addition, stop peripheral hardware that is operating on the high-speed system clock. 6.6.2 example of controlling inte rnal high-speed oscillation clock the following describes examples of clock setting procedures for the following cases. (1) when restarting oscillation of the internal high-speed oscillation clock (2) when using internal high-speed oscillation clock as cpu clock, and internal high-speed oscillation clock or high-speed system clock as peripheral hardware clock (3) when stopping the internal high-speed oscillation clock (1) example of setting procedure wh en restarting oscillation of the in ternal high-speed oscillation clock note 1 <1> setting restart of oscillation of the intern al high-speed oscillation clock (rcm register) when rstop is cleared to 0, the internal high-speed oscillation clock starts operating. <2> waiting for the oscillation accuracy stabilization time of internal high-speed oscillation clock (rcm register) wait until rsts is set to 1 note 2 . notes 1. after a reset release, the internal high-speed oscillator automatically starts oscillating and the internal high-speed oscillation clock is selected as the cpu clock. 2. this wait time is not necessary if high accura cy is not necessary for the cpu clock and peripheral hardware clock. (2) example of setting procedure when using intern al high-speed oscillation clock as cpu clock, and internal high-speed oscillation clock or high-speed system clo ck as peripheral hardware clock <1> ? restarting oscillation of the internal high-speed oscillation clock note (see 6.6.2 (1) example of setting procedure when restarting internal high-speed oscillation clock ). ? oscillating the high-speed system clock note (this setting is required when using the high-speed system clock as the peripheral hardware clock. see 6.6.1 (1) example of setting proced ure when oscillating the x1 clock and (2) example of setting procedure when using th e external main system clock. ) chapter 6 clock generator user?s manual u17553ej4v0ud 148 note the setting of <1> is not necessary when the internal high-speed oscillation clock or high- speed system clock is already operating. <2> selecting the clock s upplied as the main system clock and peri pheral hardware clock (mcm register) set the main system clock and peripheral hardware clock using xsel and mcm0. selection of main system clock and clock supplied to peripheral hardware xsel mcm0 main system clock (f xp ) peripheral hardware clock (f prs ) 0 0 0 1 internal high-speed oscillation clock (f rh ) 1 0 internal high-speed oscillation clock (f rh ) high-speed system clock (f xh ) <3> selecting the cpu clock division ratio (pcc register) when css is cleared to 0, the main system clock is supplied to the cpu. to select the cpu clock division ratio, use pcc0, pcc1, and pcc2. css pcc2 pcc1 pcc0 cpu clock (f cpu ) selection 0 0 0 f xp 0 0 1 f xp /2 (default) 0 1 0 f xp /2 2 0 1 1 f xp /2 3 1 0 0 f xp /2 4 0 other than above setting prohibited (3) example of setting procedure when stoppi ng the internal high-speed oscillation clock the internal high-speed oscillation clock can be stopped in the following two ways. ? executing the stop instruction to set the stop mode ? setting rstop to 1 and stopping the internal high-speed oscillation clock (a) to execute a stop instruction <1> setting of peripheral hardware stop peripheral hardware that c annot be used in the stop mode (f or peripheral hardware that cannot be used in stop mode, see chapter 18 standby function ). <2> setting the x1 clock oscillation st abilization time after standby release when the cpu is operating on the x1 clock, set t he value of the osts r egister before the stop instruction is executed. <3> executing the stop instruction when the stop instruction is ex ecuted, the system is placed in the stop mode and internal high- speed oscillation clock is stopped. chapter 6 clock generator user?s manual u17553ej4v0ud 149 (b) to stop internal high-speed o scillation clock by setting rstop to 1 <1> confirming the cpu clock st atus (pcc and mcm registers) confirm with cls and mcs that the cpu is operat ing on a clock other than the internal high-speed oscillation clock. when cls = 0 and mcs = 0, the internal high-speed oscillation clock is supplied to the cpu, so change the cpu clock to the high-spe ed system clock or subsystem clock. cls mcs cpu clock status 0 0 internal high-speed oscillation clock 0 1 high-speed system clock 1 subsystem clock <2> stopping the internal high-speed oscillation clock (rcm register) when rstop is set to 1, internal high-speed oscillation clock is stopped. caution be sure to confirm that mcs = 1 or cls = 1 when setting rstop to 1. in addition, stop peripheral hardware that is operating on the internal high-speed oscillation clock. 6.6.3 example of cont rolling subsystem clock the following two types of sub system clocks are available. ? xt1 clock: crystal/ceramic resonator is connected across the xt1 and xt2 pins. ? external subsystem clock: external clock is input to the exclks pin. when the subsystem clock is not us ed, the xt1/p123 and xt2/ exclks/p124 pins can be used as i/o port pins. caution the xt1/p123 and xt2/exclks/p124 pins are in the i/o port mode after a reset release. the following describes examples of setti ng procedures for the following cases. (1) when oscillating xt1 clock (2) when using external subsystem clock (3) when using subsystem clock as cpu clock (4) when stopping subsystem clock (1) example of setting procedur e when oscillating the xt1 clock <1> setting xt1 and xt2 pins and selectin g operation mode (pcc and oscctl registers) when xtstart, exclks, and oscsels are set as any of the following, the mode is switched from port mode to xt1 oscillation mode. xtstart exclks oscsels operation mode of subsystem clock pin p123/xt1 pin p124/xt2/ exclks pin 0 0 1 1 xt1 oscillation mode crystal/ceramic resonator connection remark : don?t care <2> waiting for the stabilization of the subsystem clock oscillation wait for the oscillation stabilization time of the subsystem clock by software, using a timer function. caution do not change the value of xtstart, exclks, and oscsel s while the subsystem clock is operating. chapter 6 clock generator user?s manual u17553ej4v0ud 150 (2) example of setting procedure when using the external subsystem clock <1> setting xt1 and xt2 pins, selecting xt1 clock/ external clock and controlling oscillation (pcc and oscctl registers) when xtstart is cleared to 0 and exclks and oscsel s are set to 1, the mode is switched from port mode to external clock input mode. in this ca se, input the external clock to the exclks/xt2/p124 pins. xtstart exclks oscsels operation mode of subsystem clock pin p123/xt1 pin p124/xt2/ exclks pin 0 1 1 external clock input mode i/o port external clock input caution do not change the value of xtstart, exclks, and oscsel s while the subsystem clock is operating. (3) example of setting procedure when us ing the subsystem cl ock as the cpu clock <1> setting subsystem clock oscillation note (see 6.6.3 (1) example of setting proce dure when oscillating the xt1 clock and (2) example of setting procedure when using the external subsystem clock .) note the setting of <1> is not necessary when while the subsystem clock is operating. <2> switching the cpu clock (pcc register) when css is set to 1, the subsystem clock is supplied to the cpu. css pcc2 pcc1 pcc0 cpu clock (f cpu ) selection 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 f sub /2 1 other than above setting prohibited (4) example of setting procedure wh en stopping the subsystem clock <1> confirming the cpu clock st atus (pcc and mcm registers) confirm with cls and mcs that the cpu is operat ing on a clock other than the subsystem clock. when cls = 1, the subsystem clock is supplied to t he cpu, so change the cpu clock to the internal high-speed oscillation clock or high-speed system clock. cls mcs cpu clock status 0 0 internal high-speed oscillation clock 0 1 high-speed system clock 1 subsystem clock <2> stopping the subsystem clock (oscctl register) when oscsels is cleared to 0, xt1 oscillation is stop ped (the input of the external clock is disabled). cautions 1. be sure to confirm th at cls = 0 when clearing oscsels to 0. in addition, stop the watch timer if it is operating on the subsystem clock. 2. the subsystem clock oscillation cannot be stopped using the stop instruction. chapter 6 clock generator user?s manual u17553ej4v0ud 151 6.6.4 controlling internal low-speed oscillation clock the internal low-speed oscillation clock is a clock for the watchdog timer. it cannot be used as the cpu clock. with this clock, only the following peripheral hardware can operate. ? watchdog timer ? 8-bit timer h1 (if f rl is selected as the count clock) in addition, the following operation modes can be selected by the option byte. ? internal low-speed oscillation clock oscillation cannot be stopped ? internal low-speed oscillation clock oscillation can be stopped by software after a reset release, the internal low-spe ed oscillation clock automatically oscillates. (1) to stop the internal low-speed oscilla tion clock (example of setting method) <1> setting lsrstop to 1 (rcm register) if lsrstop is set to 1, the internal low-speed oscillator oscillation is stopped. (2) to oscillate the internal low-speed o scillation clock (example of setting method) <1> clearing lsrstop to 0 (rcm register) if lsrstop is cleared to 0, the internal low-speed oscillation clock is oscillated. caution if ?internal low-speed osci llation clock oscillation cannot be stopped? is selected by the option byte, oscillation of the internal low-speed oscillation clock cannot be controlled. 6.6.5 clocks supplied to cp u and peripheral hardware the following table shows the relation among the clocks supplied to the cpu and peripheral hardware, and setting of registers. table 6-3. clocks supplied to cpu and peripheral hardware, and register setting supplied clock xsel css mcm0 exclk clock supplied to cpu clock supplied to peripheral hardware 0 0 internal high-speed oscillation clock 0 1 subsystem clock internal high-speed oscillation clock 1 0 0 0 x1 clock 1 0 0 1 internal high-speed oscillation clock external main system clock 1 0 1 0 x1 clock 1 0 1 1 external main system clock 1 1 0 0 x1 clock 1 1 0 1 external main system clock 1 1 1 0 x1 clock 1 1 1 1 subsystem clock external main system clock remarks 1. xsel: bit 2 of the main clock mode register (mcm) 2. css: bit 4 of the processor clock control register (pcc) 3. mcm0: bit 0 of mcm 4. exclk: bit 7 of the clock operat ion mode select register (oscctl) chapter 6 clock generator user?s manual u17553ej4v0ud 152 6.6.6 cpu clock stat us transition diagram figure 6-14 shows the cpu clock status transition diagram of this product. figure 6-14. cpu clock st atus transition diagram power on reset release v dd 1.59 v (typ.) v dd 1.8 v (min.) v dd < 1.59 v (typ.) internal low-speed oscillation: woken up internal high-speed oscillation: woken up x1 oscillation/exclk input: stops (i/o port mode) xt1 oscillation/exclks input: stops (i/o port mode) internal low-speed oscillation: operating internal high-speed oscillation: operating x1 oscillation/exclk input: stops (i/o port mode) xt1 oscillation/exclks input: stops (i/o port mode) cpu: operating with internal high- speed oscillation internal low-speed oscillation: operable internal high-speed oscillation: operating x1 oscillation/exclk input: selectable by cpu xt1 oscillation/exclks input: selectable by cpu cpu: internal high- speed oscillation stop internal low-speed oscillation: operable internal high-speed oscillation: stops x1 oscillation/exclk input: stops xt1 oscillation/exclks input: operable cpu: internal high- speed oscillation halt internal low-speed oscillation: operable internal high-speed oscillation: operating x1 oscillation/exclk input: operable xt1 oscillation/exclks input: operable cpu: operating with x1 oscillation or exclk input cpu: x1 oscillation/exclk input stop cpu: x1 oscillation/exclk input halt internal low-speed oscillation: operable internal high-speed oscillation: selectable by cpu x1 oscillation/exclk input: operating xt1 oscillation/exclks input: selectable by cpu internal low-speed oscillation: operable internal high-speed oscillation: stops x1 oscillation/exclk input: stops xt1 oscillation: operable internal low-speed oscillation: operable internal high-speed oscillation: operable x1 oscillation/exclk input: operating xt1 oscillation/exclks input: operable cpu: operating with xt1 oscillation or exclks input cpu: xt1 oscillation/exclks input halt internal low-speed oscillation: operable internal high-speed oscillation: selectable by cpu x1 oscillation/exclk input: selectable by cpu xt1 oscillation/exclks input: operating internal low-speed oscillation: operable internal high-speed oscillation: operable x1 oscillation/exclk input: operable xt1 oscillation/exclks input: operating (b) (a) (c) (d) (e) (f) (g) (h) (i) remark in the 2.7 v/1.59 v poc mode (opt ion byte: lvistart = 1), the cpu clock status changes to (a) in the above figure when the supply voltage exceeds 2.7 v (typ.), and to (b) after reset processing (11 to 45 s). chapter 6 clock generator user?s manual u17553ej4v0ud 153 table 6-4 shows transition of the cpu clock and examples of setting the sfr registers. table 6-4. cpu clock transition a nd sfr register setting examples (1/4) (1) cpu operating with high-speed system clock (c) after reset release (a) (the cpu operates with the internal high-speed oscill ation clock immediately after a reset release (b).) (setting sequence of sfr registers) setting flag of sfr register status transition amph exclk oscsel mstop ostc register xsel mcm0 (a) (b) (c) (x1 clock: less than 10 mhz) 0 0 1 0 must be checked 1 1 (a) (b) (c) (external main clock: less than 10 mhz) 0 1 1 0 must not be checked 1 1 (a) (b) (c) (x1 clock: 10 mhz or more) 1 0 1 0 must be checked 1 1 (a) (b) (c) (external main clock: 10 mhz or more) 1 1 1 0 must not be checked 1 1 (2) cpu operating with internal high-speed oscillation clock (b) a fter reset release (a) status transition sfr register setting (a) (b) sfr registers do not have to be se t (default status after reset release). (3) cpu operating with subsystem cl ock (d) after reset release (a) (the cpu operates with the internal high-speed oscill ation clock immediately after a reset release (b).) (setting sequence of sfr registers) setting flag of sfr register status transition exclks oscsels waiting for oscillation stabilization css (a) (b) (d) (xt1 clock) 0 1 necessary 1 (a) (b) (d) (external subsystem clock) 1 1 unnecessary 1 remarks 1. (a) to (i) in table 6-4 correspond to (a) to (i) in figure 6-14. 2. exclk, oscsel, exclks, oscsels, amph: bits 7 to 4 and 0 of the clock oper ation mode select register (oscctl) mstop: bit 7 of the main osc control register (moc) xsel, mcm0: bits 2 and 0 of the main clock mode register (mcm) css: bit 4 of the processor clock control register (pcc) chapter 6 clock generator user?s manual u17553ej4v0ud 154 table 6-4. cpu clock transition a nd sfr register setting examples (2/4) (4) cpu clock changing from inte rnal high-speed oscillation clock (b) to high-speed system clock (c) (setting sequence of sfr registers) setting flag of sfr register status transition amph exclk oscsel mstop ostc register xsel mcm0 (b) (c) (x1 clock: less than 10 mhz) 0 0 1 0 must be checked 1 1 (b) (c) (external main clock: less than 10 mhz) 0 1 1 0 must not be checked 1 1 (b) (c) (x1 clock: 10 mhz or more) 1 0 1 0 must be checked 1 1 (b) (c) (external main clock: 10 mhz or more) 1 1 1 0 must not be checked 1 1 unnecessary if these registers are already set unnecessary if the cpu is operating with the high-speed system clock unnecessary if this register is already set (5) cpu clock changing from in ternal high-speed oscillation cl ock (b) to subsystem clock (d) (setting sequence of sfr registers) setting flag of sfr register status transition exclks oscsels waiting for oscillation stabilization css (b) (d) (xt1 clock) 0 1 necessary 1 (b) (d) (external subsystem clock) 1 1 unnecessary 1 unnecessary if the cpu is operating with the subsystem clock remarks 1. (a) to (i) in table 6-4 correspond to (a) to (i) in figure 6-14. 2. exclk, oscsel, exclks, oscsels, amph: bits 7 to 4 and 0 of the clock oper ation mode select register (oscctl) mstop: bit 7 of the main osc control register (moc) xsel, mcm0: bits 2 and 0 of the main clock mode register (mcm) css: bit 4 of the processor clock control register (pcc) chapter 6 clock generator user?s manual u17553ej4v0ud 155 table 6-4. cpu clock transition a nd sfr register setting examples (3/4) (6) cpu clock changing from high- speed system clock (c) to internal high-speed oscillation clock (b) (setting sequence of sfr registers) setting flag of sfr register status transition rstop rsts mcm0 (c) (b) 0 confirm this flag is 1. 0 unnecessary if the cpu is operating with the internal high-speed oscillation clock (7) cpu clock changing from high-speed system clock (c) to subsystem clock (d) (setting sequence of sfr registers) setting flag of sfr register status transition exclks oscsels waiting for oscillation stabilization css (c) (d) (xt1 clock) 0 1 necessary 1 (c) (d) (external subsystem clock) 1 1 unnecessary 1 unnecessary if the cpu is operating with the subsystem clock (8) cpu clock changing from subsystem clock (d) to high-sp eed system clock (c) (setting sequence of sfr registers) setting flag of sfr register status transition amph exclk oscsel mstop ostc register xsel mcm0 css (d) (c) (x1 clock: less than 10 mhz) 0 0 1 0 must be checked 1 1 0 (d) (c) (external main clock: less than 10 mhz) 0 1 1 0 must not be checked 1 1 0 (d) (c) (x1 clock: 10 mhz or more) 1 0 1 0 must be checked 1 1 0 (d) (c) (external main clock: 10 mhz or more) 1 1 1 0 must not be checked 1 1 0 unnecessary if these registers are already set unnecessary if the cpu is operating with the high-speed system clock unnecessary if this register is already set remarks 1. (a) to (i) in table 6-4 correspond to (a) to (i) in figure 6-14. 2. exclk, oscsel, exclks, oscsels, amph: bits 7 to 4 and 0 of the clock oper ation mode select register (oscctl) mstop: bit 7 of the main osc control register (moc) xsel, mcm0: bits 2 and 0 of the main clock mode register (mcm) css: bit 4 of the processor clock control register (pcc) rsts, rstop: bits 7 and 0 of the internal oscillator mode register (rcm) chapter 6 clock generator user?s manual u17553ej4v0ud 156 table 6-4. cpu clock transition a nd sfr register setting examples (4/4) (9) cpu clock changing from subsystem clock (d ) to internal high-speed oscillation clock (b) (setting sequence of sfr registers) setting flag of sfr register status transition rstop rsts mcm0 css (d) (b) 0 confirm this flag is 1. 0 0 unnecessary if the cpu is operating with the internal high-speed oscillation clock unnecessary if xsel is 0 (10) ? halt mode (e) set while cpu is operating wit h internal high-speed oscillation clock (b) ? halt mode (f) set while cpu is ope rating with high-speed system clock (c) ? halt mode (g) set while cpu is operating with subsystem clock (d) status transition setting (b) (e) (c) (f) (d) (g) executing halt instruction (11) ? stop mode (h) set while cp u is operating with internal hi gh-speed oscillation clock (b) ? stop mode (i) set while cpu is ope rating with high-speed system clock (c) (setting sequence) status transition setting (b) (h) (c) (i) stopping peripheral functions that cannot operate in stop mode executing stop instruction remarks 1. (a) to (i) in table 6-4 correspond to (a) to (i) in figure 6-14. 2. mcm0: bit 0 of the main clock mode register (mcm) css: bit 4 of the processor clock control register (pcc) rsts, rstop: bits 7 and 0 of the internal oscillator mode register (rcm) chapter 6 clock generator user?s manual u17553ej4v0ud 157 6.6.7 condition before changing cpu clo ck and processing after changing cpu clock condition before changing the cpu clock and processing after changing the cpu clock are shown below. table 6-5. changing cpu clock cpu clock before change after change condition before change processing after change x1 clock stabilization of x1 oscillation ? mstop = 0, oscsel = 1, exclk = 0 ? after elapse of oscillation stabilization time ? internal high-speed oscillator can be stopped (rstop = 1). ? clock supply to cpu is stopped for 4.06 to 16.12 s after amph has been set to 1. internal high- speed oscillation clock external main system clock enabling input of exter nal clock from exclk pin ? mstop = 0, oscsel = 1, exclk = 1 ? internal high-speed oscillator can be stopped (rstop = 1). ? clock supply to cpu is stopped for the duration of 160 external clocks from the exclk pin after amph has been set to 1. x1 clock x1 oscillation can be stopped (mstop = 1). external main system clock internal high- speed oscillation clock oscillation of internal high-speed oscillator ? rstop = 0 external main system clock input can be disabled (mstop = 1). internal high- speed oscillation clock operating current can be reduced by stopping internal high-speed oscillator (rstop = 1). x1 clock x1 oscillation can be stopped (mstop = 1). external main system clock xt1 clock stabilization of xt1 oscillation ? xtstart = 0, exclks = 0, oscsels = 1, or xtstart = 1 ? after elapse of oscillation stabilization time external main system clock input can be disabled (mstop = 1). internal high- speed oscillation clock operating current can be reduced by stopping internal high-speed oscillator (rstop = 1). x1 clock x1 oscillation can be stopped (mstop = 1). external main system clock external subsystem clock enabling input of ex ternal clock from exclks pin ? xtstart = 0, exclks = 1, oscsels = 1 external main system clock input can be disabled (mstop = 1). internal high- speed oscillation clock oscillation of internal high-speed oscillator and selection of internal high-speed oscillation clock as main system clock ? rstop = 0, mcs = 0 xt1 oscillation can be stopped or external subsystem clock input can be disabled (oscsels = 0). x1 clock stabilization of x1 oscillation and selection of high-speed system cl ock as main system clock ? mstop = 0, oscsel = 1, exclk = 0 ? after elapse of oscillation stabilization time ? mcs = 1 ? xt1 oscillation can be stopped or external subsystem clock input can be disabled (oscsels = 0). ? clock supply to cpu is stopped for 4.06 to 16.12 s after amph has been set to 1. xt1 clock, external subsystem clock external main system clock enabling input of exter nal clock from exclk pin and selection of high-speed system clock as main system clock ? mstop = 0, oscsel = 1, exclk = 1 ? mcs = 1 ? xt1 oscillation can be stopped or external subsystem clock input can be disabled (oscsels = 0). ? clock supply to cpu is stopped for the duration of 160 external clocks from the exclk pin after amph has been set to 1. chapter 6 clock generator user?s manual u17553ej4v0ud 158 6.6.8 time required for switchover of cpu clock and main system clock by setting bits 0 to 2 (pcc0 to pcc2) and bit 4 (css) of the processor clock control register (pcc), the cpu clock can be switched (between the main system clock and the s ubsystem clock) and the division ratio of the main system clock can be changed. the actual switchover operat ion is not performed immediately after rewr iting to pcc; operat ion continues on the pre-switchover clock for several clocks (see table 6-6 ). whether the cpu is oper ating on the main system clock or the sub system clock can be ascertained using bit 5 (cls) of the pcc register. table 6-6. time required for switchover of cpu clock and main system cl ock cycle division factor set value before switchover set value after switchover css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css p cc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 0 0 0 16 clocks 16 clocks 16 clocks 16 clocks 2f xp /f sub clocks 0 0 1 8 clocks 8 clocks 8 clocks 8 clocks f xp /f sub clocks 0 1 0 4 clocks 4 clocks 4 clocks 4 clocks f xp /2f sub clocks 0 1 1 2 clocks 2 clocks 2 clocks 2 clocks f xp /4f sub clocks 0 1 0 0 1 clock 1 clock 1 clock 1 clock f xp /8f sub clocks 1 2 clocks 2 clocks 2 clo cks 2 clocks 2 clocks caution selection of the main system clock cycle division factor (pcc0 to pcc2) and switchover from the main system clock to the subsystem clock (changing css from 0 to 1) should not be set simultaneously. simultaneous setting is possible, however, for selection of the ma in system clock cycle division factor (pcc0 to pcc2 ) and switchover from the subsystem clock to the main system clock (changing css from 1 to 0). remarks 1. the number of clocks listed in table 6-6 is the number of cpu clocks before switchover. 2. when switching the cpu clock from the main system clock to the subsystem clock, calculate the number of clocks by rounding up to the next clock and discarding the decimal portion, as shown below. example when switching cpu clock from f xp /2 to f sub /2 (@ oscillation with f xp = 10 mhz, f sub = 32.768 khz) f xp /f sub = 10000/32.768 ? 305.1 306 clocks by setting bit 0 (mcm0) of the main clock mode register (mcm), the main system clo ck can be switch ed (between the internal high-speed oscillation clock and the high-speed system clock). the actual switchover oper ation is not performed immediately after re writing to mcm0; operation continues on the pre-switchover clock for several clocks (see table 6-7 ). whether the cpu is operating on the internal high-speed oscillation cloc k or the high-speed system clock can be ascertained using bit 1 (mcs) of mcm. chapter 6 clock generator user?s manual u17553ej4v0ud 159 table 6-7. maximum time required for main system clock switchover set value before switchover set value after switchover mcm0 mcm0 0 1 0 1 + 2f rh /f xh clock 1 1 + 2f xh /f rh clock caution when switching the intern al high-speed oscillation clock to the high-speed system clock, bit 2 (xsel) of mcm must be set to 1 in advance. the value of xsel can be changed only once after a reset release. remarks 1. the number of clocks listed in table 6-7 is t he number of main system clocks before switchover. 2. calculate the number of clocks in t able 6-7 by removing the decimal portion. example when switching the main system clock from the internal high-speed oscillation clock to the high-speed system clock (@ oscillation with f rh = 8 mhz, f xh = 10 mhz) 1 + 2f rh /f xh = 1 + 2 8/10 = 1 + 2 0.8 = 1 + 1.6 = 2.6 2 clocks 6.6.9 conditions before cl ock oscillation is stopped the following lists the register flag settings for stopping th e clock oscillation (disabling external clock input) and conditions before the clock oscillation is stopped. table 6-8. conditions before the clo ck oscillation is stopped and flag settings clock conditions before clock oscillation is stopped (external clock input disabled) flag settings of sfr register internal high-speed oscillation clock mcs = 1 or cls = 1 (the cpu is operating on a clock ot her than the internal high-speed oscillation clock) rstop = 1 x1 clock external main system clock mcs = 0 or cls = 1 (the cpu is operating on a clock other than the high-speed system clock) mstop = 1 xt1 clock external subsystem clock cls = 0 (the cpu is operating on a clock other than the subsystem clock) oscsels = 0 user?s manual u17553ej4v0ud 160 chapter 7 16-bit timer/event counters 00 to 03 the 78k0/ff2 incorporates 16-bit timer/event counters 00 to 03. 7.1 functions of 16-bit timer/event counters 00 to 03 16-bit timer/event counters 00 to 03 have the following functions. ? interval timer ? ppg output ? pulse width measurement ? external event counter ? square-wave output ? one-shot pulse output (1) interval timer 16-bit timer/event counters 00 to 03 generate an in terrupt request at the preset time interval. (2) ppg output 16-bit timer/event counters 00 to 03 can output a re ctangular wave whose frequency and output pulse width can be set freely. (3) pulse width measurement 16-bit timer/event counters 00 to 03 can measure the pulse width of an externally input signal. (4) external event counter 16-bit timer/event counters 00 to 03 can measure the number of pulses of an externally input signal. (5) square-wave output 16-bit timer/event counters 00 to 03 can output a square wave with any selected frequency. (6) one-shot pulse output 16-bit timer event counters 00 to 03 can output a one-s hot pulse whose output pulse width can be set freely. chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 161 7.2 configuration of 16-bit timer/event counters 00 to 03 16-bit timer/event counters 00 to 03 include the following hardware. table 7-1. configuration of 16- bit timer/event counters 00 to 03 item configuration timer counter 16 bits (tm0n) register 16-bit timer capture/compar e register: 16 bits (cr00n, cr01n) timer input ti00n, ti01n timer output to0n, output controller control registers 16-bit timer mode control register 0n (tmc0n) 16-bit timer capture/compare control register 0n (crc0n) 16-bit timer output control register 0n (toc0n) prescaler mode register 0n (prm0n) port mode register 0, 3, 13 (pm0, pm3, pm13) port register 0, 3, 13 (p0, p3, p13) remark n = 0 to 3 figures 7-1 to 7-4 show the block diagrams. figure 7-1. block diagram of 16-bit timer/event counter 00 internal bus capture/compare control register 00 (crc00) ti010/to00/p01 f prs f prs /2 2 f prs /2 8 f prs ti000/p00 prescaler mode register 00 (prm00) 2 prm001 prm000 crc002 16-bit timer capture/compare register 010 (cr010) match match 16-bit timer counter 00 (tm00) clear noise elimi- nator crc002 crc001 crc000 inttm000 to00/ti010/ p01 inttm010 16-bit timer output control register 00 (toc00) 16-bit timer mode control register 00 (tmc00) internal bus tmc003 tmc002 tmc001 ovf00 toc004 lvs00 lvr00 toc001 toe00 selector 16-bit timer capture/compare register 000 (cr000) selector selector selector noise elimi- nator noise elimi- nator output controller ospe00 ospt00 output latch (p01) pm01 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 162 figure 7-2. block diagram of 16-bit timer/event counter 01 internal bus capture/compare control register 01 (crc01) ti011/to01/p06 f prs f prs /2 4 f prs /2 6 f prs ti001/p05 prescaler mode register 01 (prm01) 2 prm011 prm010 crc012 16-bit timer capture/compare register 011 (cr011) match match 16-bit timer counter 01 (tm01) clear noise elimi- nator crc012 crc011 crc010 inttm001 to01/ti011/ p06 inttm011 16-bit timer output control register 01 (toc01) 16-bit timer mode control register 01 (tmc01) internal bus tmc013 tmc012 tmc011 ovf01 toc014 lvs01 lvr01 toc011 toe01 selector 16-bit timer capture/compare register 001 (cr001) selector selector selector noise elimi- nator noise elimi- nator output controller ospe01 ospt01 output latch (p06) pm06 figure 7-3. block diagram of 16-bit timer/event counter 02 internal bus capture/compare control register 02 (crc02) ti012/to02/ intp3/p32 f prs f prs /2 2 f prs /2 8 f prs ti002/intp2 /p31 prescaler mode register 02 (prm02) 2 prm021 prm020 crc022 16-bit timer capture/compare register 012 (cr012) match match 16-bit timer counter 02 (tm02) clear noise elimi- nator crc022 crc021 crc020 inttm002 to02/ti012/ intp3/p32 inttm012 16-bit timer output control register 02 (toc02) 16-bit timer mode control register 02 (tmc02) internal bus tmc023 tmc022 tmc021 ovf02 toc024 lvs02 lvr02 toc021 toe02 selector 16-bit timer capture/compare register 002 (cr002) selector selector selector noise elimi- nator noise elimi- nator output controller ospe02 ospt02 output latch (p32) pm32 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 163 figure 7-4. block diagram of 16-bit timer/event counter 03 internal bus capture/compare control register 03 (crc03) ti013/to03/p132 f prs f prs /2 4 f prs /2 6 f prs ti003/p131 prescaler mode register 03 (prm03) 2 prm031 prm030 crc032 16-bit timer capture/compare register 013 (cr013) match match 16-bit timer counter 03 (tm03) clear noise elimi- nator crc032 crc031 crc030 inttm003 to03/ti013/ p132 inttm013 16-bit timer output control register 03 (toc03) 16-bit timer mode control register 03 (tmc03) internal bus tmc033 tmc032 tmc031 ovf03 toc034 lvs03 lvr03 toc031 toe03 selector 16-bit timer capture/compare register 003 (cr003) selector selector selector noise elimi- nator noise elimi- nator output controller ospe03 ospt03 output latch (p132) pm132 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 164 (1) 16-bit timer counter 0n (tm0n) tm0n is a 16-bit read-only regist er that counts count pulses. the counter is incremented in synchronization with the rising edge of the count clock. if the count value is read during operat ion, then input of the count clock is temporarily stopped, and the count value at that point is read. figure 7-5. format of 16-bit timer counter 0n (tm0n) tm0n (n = 0 to 3) symbol ff11h (tm00) ffb1h (tm01) ff5bh (tm02) ffa7h (tm03) ff10h (tm00) ffb0h (tm01) ff5ah (tm02) ffa6h (tm03) address: ff10h, ff11h (tm00), ffb0h, ffb1h (tm01) after reset: 0000h r ff5ah, ff5bh (tm02), ffa6h, ffa7h (tm03) the count value is reset to 0000h in the following cases. <1> at reset signal generation <2> if tmc0n3 and tmc0n2 are cleared <3> if the valid edge of the ti00n pin is input in the mode in which clear & start occurs when inputting the valid edge of the ti00n pin <4> if tm0n and cr00n match in the mode in which cl ear & start occurs on a match of tm0n and cr00n <5> ospt0n is set to 1 in one-shot pulse output m ode or the valid edge is input to the ti00n pin cautions 1. even if tm0n is read , the value is not captured by cr01n. 2. when tm0n is read, input of the count clo ck is temporarily stopped a nd it is resumed after the timer has been read. ther efore, no clock miss occurs. chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 165 (2) 16-bit timer capture/comp are register 00n (cr00n) cr00n is a 16-bit register that has t he functions of both a captur e register and a compare r egister. whether it is used as a capture register or as a comp are register is set by bit 0 (crc0n0) of capture/compar e control register 0n (crc0n). cr00n can be set by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0000h. figure 7-6. format of 16-bit timer ca pture/compare register 00n (cr00n) cr00n (n = 0 to 3) symbol ff13h (cr000) ffb3h (cr001) ff6dh (cr002) ffa9h (cr003) ff12h (cr000) ffb2h (cr001) ff6ch (cr002) ffa8h (cr003) address: ff12h, ff13h (cr000), ffb2h, ffb3h (cr001) after reset: 0000h r/w ff6ch, ff6dh (cr002), ffa8h, ffa9h (cr003) ? when cr00n is used as a compare register the value set in cr00n is constant ly compared with 16-bit timer count er 0n (tm0n) count value, and an interrupt request (inttm00n) is gener ated if they match. the set valu e is held until cr00n is rewritten. caution cr00n does not perform th e capture operation when it is set in the comparison mode, even if a capture trigger is input to it. ? when cr00n is used as a capture register it is possible to select the valid edge of the ti00n pi n or the ti01n pin as the c apture trigger. the ti00n or ti01n pin valid edge is set using prescaler mode register 0n (prm0n) (see table 7-2 ). chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 166 table 7-2. cr00n capture trigger and valid edges of ti00n and ti01n pins (1) ti00n pin valid edge selected as captu re trigger (crc0n1 = 1, crc0n0 = 1) ti00n pin valid edge cr00n capture trigger es0n1 es0n0 falling edge rising edge 0 1 rising edge falling edge 0 0 no capture operation both rising and falling edges 1 1 (2) ti01n pin valid edge selected as captu re trigger (crc0n1 = 0, crc0n0 = 1) ti01n pin valid edge cr00n capture trigger es1n1 es1n0 falling edge falling edge 0 0 rising edge rising edge 0 1 both rising and falling edges both rising and falling edges 1 1 cautions 1. set a value other than 0000h in cr00n in the mode in which clear & start occurs on a match of tm0n and cr00n. 2. if cr00n is cleared to 0000h in the free-running mode and in the clear m ode using the valid edge of the ti00n pin, an interrupt request (inttm00n ) is generated when the value of cr00n changes from 0000h to 0001h following tm0n overflow (ffffh). in additi on, inttm00n is generated after a match between tm0n and cr00n, after detecting th e valid edge of the ti01n pin, and the timer is cleared by a one-shot trigger. 3. when p01 or p06 is used as the valid edge i nput of the ti01n pin, it cannot be used as the timer output (to0n). moreover, when p01 or p06 is u sed as to0n, it cannot be used as the valid edge input of the ti01n pin. 4. when cr00n is used as a capture register, read data is unde fined if the register read time and capture trigger input conflict (the captu re data itself is the correct value). if count stop input and capture trigger in put conflict, the capture d data is undefined. 5. do not rewrite cr00n during tm0n operation. remarks 1. setting es0n1, es0n0 = 1, 0 and es1n1, es1n0 = 1, 0 is prohibited. 2. es0n1, es0n0: bits 5 and 4 of prescaler mode register 0n (prm0n) es1n1, es1n0: bits 7 and 6 of prescaler mode register 0n (prm0n) crc0n1, crc0n0: bits 1 and 0 of capture/ compare control register 0n (crc0n) 3. n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 167 (3) 16-bit timer capture/comp are register 01n (cr01n) cr01n is a 16-bit register that has t he functions of both a captur e register and a compare r egister. whether it is used as a capture register or a compar e register is set by bit 2 (crc0n2) of capture/compare c ontrol register 0n (crc0n). cr01n can be set by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0000h. figure 7-7. format of 16-bit timer ca pture/compare register 01n (cr01n) cr01n (n = 0 to 3) symbol ff15h (cr010) ffb5h (cr011) ffedh (cr012) ffabh (cr013) ff14h (cr010) ffb4h (cr011) ffech (cr012) ffaah (cr013) address: ff14h, ff15h (cr010), ffb4h, ffb5h (cr011) after reset: 0000h r/w ffech, ffedh (cr012), ffaah, ffabh (cr013) ? when cr01n is used as a compare register the value set in the cr01n is cons tantly compared with 16-bit timer c ounter 0n (tm0n) count value, and an interrupt request (inttm01n) is gener ated if they match. the set valu e is held until cr01n is rewritten. ? when cr01n is used as a capture register it is possible to select the valid edge of the ti00n pin as the capture trigger. the ti00n pin valid edge is set by prescaler mode register 0n (prm0n) (see table 7-3 ). table 7-3. cr01n capture trigger and valid edge of ti00n pin (crc0n2 = 1) ti00n pin valid edge cr01n capture trigger es0n1 es0n0 falling edge falling edge 0 0 rising edge rising edge 0 1 both rising and falling edges both rising and falling edges 1 1 cautions 1. if the cr01n register is cleared to 0000h, an interrupt requ est (inttm01n) is generated when the value of cr01n changes from 0000h to 0001h following tm0n over flow (ffffh). in addition, inttm01n is generated after a ma tch between tm0n and cr01n, afte r detecting the valid edge of the ti00n pin, and the timer is cleared by a one-shot trigger. 2. when cr01n is used as a capture register, read data is unde fined if the register read time and capture trigger input conflict (the captu re data itself is the correct value). if count stop input and capture trigger in put conflict, the capture d data is undefined. 3. cr01n can be rewritten during tm0n operation. for details, see caution 2 in figure 7-33 ppg output operation timing. remarks 1. setting es0n1, es0n0 = 1, 0 is prohibited. 2. es0n1, es0n0: bits 5 and 4 of prescaler mode register 0n (prm0n) crc0n2: bit 2 of capture/compar e control register 0n (crc0n) 3. n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 168 (4) setting range when cr00n or cr01n is used as a compare register when cr00n or cr01n is used as a compare register, set it as shown below. operation cr00n register setting range cr01n register setting range operation as interval timer operation as square-wave output operation as external event counter 0000h < n ffffh 0000h note m ffffh normally, this setting is not used. mask the match interrupt signal (inttm01n). operation in the clear & start mode entered by ti00n pin valid edge input operation as free-running timer 0000h note n ffffh 0000h note m ffffh operation as ppg output m < n ffffh 0000h note m < n operation as one-shot pulse output 0000h note n ffffh (n m) 0000h note m ffffh (m n) note when 0000h is set, a match interrupt immediately after the timer operation does not occur and timer output is not changed, and the first match timing is as follows . a match interrupt occurs at the timing when the timer counter (tm0n register) is changed from 0000h to 0001h. ? when the timer counter is cleared due to overflow ? when the timer counter is cleared due to ti00n pin valid edge (when clear & start mode is entered by ti00n pin valid edge input) ? when the timer counter is cleared due to compare ma tch (when clear & start mode is entered by match between tm0n and cr00n (cr00n = other than 0000h, cr01n = 0000h)) operation enabled (other than 00) tm0n register timer counter clear interrupt signal is not generated interrupt signal is generated timer operation enable bit (tmc0n3, tmc0n2) interrupt request signal compare register set value (0000h) operation disabled (00) remarks 1. n: cr00n register set value, m: cr01n register set value 2. for details of tmc0n3 and tmc0n2, see 7.3 (1) 16-bit timer mode c ontrol register 0n (tmc0n) . 3. n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 169 table 7-4. capture oper ation of cr00n and cr01n external input signal capture operation ti00n pin input ti01n pin input set values of es0n1 and es0n0 position of edge to be captured set values of es1n1 and es1n0 position of edge to be captured 01: rising 01: rising 00: falling 00: falling crc0n1 = 1 ti00n pin input (reverse phase) 11: both edges (cannot be captured) crc0n1 bit = 0 ti01n pin input 11: both edges capture operation of cr00n interrupt signal inttm00n signal is not generated even if value is captured. interrupt signal inttm00n signal is generated each time value is captured. set values of es0n1 and es0n0 position of edge to be captured 01: rising 00: falling ti00n pin input note 11: both edges capture operation of cr01n interrupt signal inttm01n signal is generated each time value is captured. note the capture operation of cr01n is not affected by the setting of the crc0n1 bit. caution to capture the count value of the tm0n regi ster to the cr00n regist er by using the phase reverse to that input to the ti 00n pin, the interrupt request si gnal (inttm00n) is not generated after the value has been captured . if the valid edge is detect ed on the ti01n pin during this operation, the capture operation is not performe d but the inttm00n signal is generated as an external interrupt signal. to not use the external interrupt, mask the inttm00n signal. remarks 1. crc0n1: see 7.3 (2) capture/compare control register 0n (crc0n) . es1n1, es1n0, es0n1, es0n0: see 7.3 (4) prescaler mode register 0n (prm0n) . 2. n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 170 7.3 registers controlling 16-bi t timer/event counters 00 to 03 the following six registers are used to cont rol 16-bit timer/event counters 00 to 03. ? 16-bit timer mode control register 0n (tmc0n) ? capture/compare contro l register 0n (crc0n) ? 16-bit timer output control register 0n (toc0n) ? prescaler mode register 0n (prm0n) ? port mode register 0, 3, 13 (pm0, pm3, pm13) ? port register 0, 3, 13 (p0, p3, p13) (1) 16-bit timer mode cont rol register 0n (tmc0n) this register sets the 16-bit timer operating mode, t he 16-bit timer counter 0n (tm0n) clear mode, and output timing, and detects an overflow. rewriting tmc0n is prohibited during operation (when tm c0n3 and tmc0n2 = other than 00). however, it can be changed when tmc0n3 and tmc0n2 are cleared to 00 (s topping operation) and when ovf0n is cleared to 0. tmc0n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears tmc0n to 00h. caution 16-bit timer counter 0n (tm0n) starts opera tion at the moment tmc0n2 and tmc0n3 are set to values other than 0, 0 (operation stop mode), resp ectively. set tmc0n2 and tmc0n3 to 0, 0 to stop the operation. remark n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 171 figure 7-8. format of 16-bit timer mode control register 00 (tmc00) address: ffbah after reset: 00h r/w symbol 7 6 5 4 3 2 1 <0> tmc00 0 0 0 0 tmc003 tmc002 tmc001 ovf00 tmc003 tmc002 operation enable of 16-bit timer/event counter 00 0 0 disables 16-bit timer/event counter 00 ope ration. stops supplyi ng operating clock. clears 16-bit timer counter 00 (tm00). 0 1 free-running timer mode 1 0 clear & start mode entered by ti000 pin valid edge input note 1 1 clear & start mode entered upon a match between tm00 and cr000 tmc001 condition to reverse timer output (to00) 0 ? match between tm00 and cr000 or match between tm00 and cr010 1 ? match between tm00 and cr000 or match between tm00 and cr010 ? trigger input of ti000 pin valid edge ovf00 tm00 overflow flag clear (0) clears ovf00 to 0 or tmc003 and tmc002 = 00 set (1) overflow occurs. ovf00 is set to 1 when the value of tm00 changes from ffffh to 0000h in all the operation modes (free-running timer mode, clear & start mode entered by ti000 pin valid edge input, and clear & start mode entered upon a match between tm00 and cr000). it can also be set to 1 by writing 1 to ovf00. note the ti000 pin valid edge is set by bits 5 and 4 ( es001, es000) of prescaler mode register 00 (prm00). remark to00: 16-bit timer/event counter 00 output pin ti000: 16-bit timer/event counter 00 input pin tm00: 16-bit timer counter 00 cr000: 16-bit timer capture/compare register 000 cr010: 16-bit timer capture/compare register 010 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 172 figure 7-9. format of 16-bit timer mode control register 01 (tmc01) address: ffb6h after reset: 00h r/w symbol 7 6 5 4 3 2 1 <0> tmc01 0 0 0 0 tmc013 tmc012 tmc011 ovf01 tmc013 tmc012 operation enable of 16-bit timer/event counter 01 0 0 disables 16-bit timer/event counter 01 ope ration. stops supplyi ng operating clock. clears 16-bit timer counter 01 (tm01). 0 1 free-running timer mode 1 0 clear & start mode entered by ti001 pin valid edge input note 1 1 clear & start mode entered upon a match between tm01 and cr001 tmc011 condition to reverse timer output (to01) 0 ? match between tm01 and cr001 or match between tm01 and cr011 1 ? match between tm01 and cr001 or match between tm01 and cr011 ? trigger input of ti001 pin valid edge ovf01 tm01 overflow flag clear (0) clears ovf01 to 0 or tmc013 and tmc012 = 00 set (1) overflow occurs. ovf01 is set to 1 when the value of tm01 changes from ffffh to 0000h in all the operation modes (free-running timer mode, clear & start mode entered by ti001 pin valid edge input, and clear & start mode entered upon a match between tm01 and cr001). it can also be set to 1 by writing 1 to ovf01. note the ti001 pin valid edge is set by bits 5 and 4 ( es011, es010) of prescaler mode register 01 (prm01). remark to01: 16-bit timer/event counter 01 output pin ti001: 16-bit timer/event counter 01 input pin tm01: 16-bit timer counter 01 cr001: 16-bit timer capture/compare register 001 cr011: 16-bit timer capture/compare register 011 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 173 figure 7-10. format of 16-bit timer mode control register 02 (tmc02) address: ff54h after reset: 00h r/w symbol 7 6 5 4 3 2 1 <0> tmc02 0 0 0 0 tmc023 tmc022 tmc021 ovf02 tmc023 tmc022 operation enable of 16-bit timer/event counter 01 0 0 disables 16-bit timer/event counter 02 ope ration. stops supplyi ng operating clock. clears 16-bit timer counter 02 (tm02). 0 1 free-running timer mode 1 0 clear & start mode entered by ti002 pin valid edge input note 1 1 clear & start mode entered upon a match between tm02 and cr002 tmc021 condition to reverse timer output (to02) 0 ? match between tm02 and cr002 or match between tm02 and cr012 1 ? match between tm02 and cr002 or match between tm02 and cr012 ? trigger input of ti002 pin valid edge ovf02 tm02 overflow flag clear (0) clears ovf02 to 0 or tmc023 and tmc022 = 00 set (1) overflow occurs. ovf02 is set to 1 when the value of tm02 changes from ffffh to 0000h in all the operation modes (free-running timer mode, clear & start mode entered by ti002 pin valid edge input, and clear & start mode entered upon a match between tm02 and cr002). it can also be set to 1 by writing 1 to ovf02. note the ti002 pin valid edge is set by bits 5 and 4 ( es021, es020) of prescaler mode register 02 (prm02). remark to02: 16-bit timer/event counter 02 output pin ti002: 16-bit timer/event counter 02 input pin tm02: 16-bit timer counter 02 cr002: 16-bit timer capture/compare register 002 cr012: 16-bit timer capture/compare register 012 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 174 figure 7-11. format of 16-bit timer mode control register 03 (tmc03) address: ffadh after reset: 00h r/w symbol 7 6 5 4 3 2 1 <0> tmc03 0 0 0 0 tmc033 tmc032 tmc031 ovf03 tmc033 tmc032 operation enable of 16-bit timer/event counter 03 0 0 disables 16-bit timer/event counter 03 ope ration. stops supplyi ng operating clock. clears 16-bit timer counter 03 (tm03). 0 1 free-running timer mode 1 0 clear & start mode entered by ti003 pin valid edge input note 1 1 clear & start mode entered upon a match between tm03 and cr003 tmc031 condition to reverse timer output (to03) 0 ? match between tm03 and cr003 or match between tm03 and cr013 1 ? match between tm03 and cr003 or match between tm03 and cr013 ? trigger input of ti003 pin valid edge ovf03 tm03 overflow flag clear (0) clears ovf03 to 0 or tmc033 and tmc032 = 00 set (1) overflow occurs. ovf03 is set to 1 when the value of tm03 changes from ffffh to 0000h in all the operation modes (free-running timer mode, clear & start mode entered by ti003 pin valid edge input, and clear & start mode entered upon a match between tm03 and cr003). it can also be set to 1 by writing 1 to ovf03. note the ti003 pin valid edge is set by bits 5 and 4 ( es031, es030) of prescaler mode register 03 (prm03). remark to03: 16-bit timer/event counter 03 output pin ti003: 16-bit timer/event counter 03 input pin tm03: 16-bit timer counter 03 cr003: 16-bit timer capture/compare register 003 cr013: 16-bit timer capture/compare register 013 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 175 (2) capture/compare control register 0n (crc0n) crc0n is the register that controls the operation of cr00n and cr01n. changing the value of crc0n is prohibited during oper ation (when tmc0n3 and tmc0n2 = other than 00). crc0n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears crc0n to 00h. figure 7-12. format of capture/co mpare control register 00 (crc00) address: ffbch after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 crc00 0 0 0 0 0 crc002 crc001 crc000 crc002 cr010 operating mode selection 0 operates as compare register 1 operates as capture register crc001 cr000 capture trigger selection 0 captures on valid edge of ti010 pin 1 captures on valid edge of ti000 pin by reverse phase note the valid edge of the ti010 and ti000 pin is set by prm00. if es001 and es000 are set to 11 (both edges) when crc001 is 1, the valid edge of the ti000 pin cannot be detected. crc000 cr000 operating mode selection 0 operates as compare register 1 operates as capture register if tmc003 and tmc002 are set to 11 (clear & start mode entered upon a match between tm00 and cr000), be sure to set crc000 to 0. note when the valid edge is detected from the ti010 pin, the capture opera tion is not performed but the inttm000 signal is generated as an external interrupt signal. caution to ensure that the capture operation is perf ormed properly, the capture trigger requires a pulse two cycles longer than the count clock selected by prescaler mode register 00 (prm00). remark n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 176 figure 7-13. example of cr01n capture op eration (when rising edge is specified) count clock tm0n ti00n rising edge detection cr01n inttm01n n ? 3n ? 2n ? 1 n n + 1 n valid edge remark n = 0 to 3 figure 7-14. format of capture/co mpare control register 01 (crc01) address: ffb8h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 crc01 0 0 0 0 0 crc012 crc011 crc010 crc012 cr011 operating mode selection 0 operates as compare register 1 operates as capture register crc011 cr001 capture trigger selection 0 captures on valid edge of ti011 pin 1 captures on valid edge of ti001 pin by reverse phase note the valid edge of the ti011 and ti001 pin is set by prm01. if es011 and es010 are set to 11 (both edges) when crc011 is 1, the valid edge of the ti001 pin cannot be detected. crc010 cr001 operating mode selection 0 operates as compare register 1 operates as capture register if tmc013 and tmc012 are set to 11 (clear & start mode entered upon a match between tm01 and cr001), be sure to set crc010 to 0. note when the valid edge is detected from the ti011 pin, the capture opera tion is not performed but the inttm001 signal is generated as an external interrupt signal. caution to ensure that the capture operation is perf ormed properly, the capture trigger requires a pulse two cycles longer than the count clock selected by pr escaler mode register 01 (prm01) (see figure 7-13 example of cr01n capture oper ation (when rising edge is specified)). chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 177 figure 7-15. format of capture/co mpare control register 02 (crc02) address: ff5ch after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 crc02 0 0 0 0 0 crc022 crc021 crc020 crc022 cr012 operating mode selection 0 operates as compare register 1 operates as capture register crc021 cr002 capture trigger selection 0 captures on valid edge of ti012 pin 1 captures on valid edge of ti002 pin by reverse phase note the valid edge of the ti012 and ti002 pin is set by prm02. if es021 and es020 are set to 11 (both edges) when crc021 is 1, the valid edge of the ti002 pin cannot be detected. crc020 cr002 operating mode selection 0 operates as compare register 1 operates as capture register if tmc023 and tmc022 are set to 11 (clear & start mode entered upon a match between tm02 and cr002), be sure to set crc020 to 0. note when the valid edge is detected from the ti012 pin, the capture opera tion is not performed but the inttm002 signal is generated as an external interrupt signal. caution to ensure that the capture operation is perf ormed properly, the capture trigger requires a pulse two cycles longer than the count clock selected by pr escaler mode register 02 (prm02) (see figure 7-13 example of cr01n capture oper ation (when rising edge is specified)). chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 178 figure 7-16. format of capture/co mpare control register 03 (crc03) address: ff52h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 crc03 0 0 0 0 0 crc032 crc031 crc030 crc032 cr013 operating mode selection 0 operates as compare register 1 operates as capture register crc031 cr003 capture trigger selection 0 captures on valid edge of ti013 pin 1 captures on valid edge of ti003 pin by reverse phase note the valid edge of the ti013 and ti003 pin is set by prm03. if es031 and es030 are set to 11 (both edges) when crc031 is 1, the valid edge of the ti003 pin cannot be detected. crc030 cr003 operating mode selection 0 operates as compare register 1 operates as capture register if tmc033 and tmc032 are set to 11 (clear & start mode entered upon a match between tm03 and cr003), be sure to set crc030 to 0. note when the valid edge is detected from the ti013 pin, the capture opera tion is not performed but the inttm003 signal is generated as an external interrupt signal. caution to ensure that the capture operation is perf ormed properly, the capture trigger requires a pulse two cycles longer than the count clock selected by pr escaler mode register 03 (prm03) (see figure 7-13 example of cr01n capture oper ation (when rising edge is specified). chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 179 (3) 16-bit timer output control register 0n (toc0n) toc0n is an 8-bit register that controls the to0n pin output. toc0n can be rewritten while only ospt0n is oper ating (when tmc0n3 and tmc0n2 = other than 00). rewriting the other bits is prohibited during operation. however, toc0n4 can be rewritten during timer operation as a means to rewrite cr01n (see 7.5.1 rewriting cr01n during tm0n operation ). toc0n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears toc0n to 00h. caution be sure to set toc0n using the following procedure. <1> set toc0n4 and toc0n1 to 1. <2> set only toe0n to 1. <3> set either of lvs0n or lvr0n to 1. remark n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 180 figure 7-17. format of 16-bit timer ou tput control register 00 (toc00) address: ffbdh after reset: 00h r/w symbol 7 <6> <5> 4 <3> <2> 1 <0> toc00 0 ospt00 ospe00 toc004 lvs00 lvr00 toc001 toe00 ospt00 one-shot pulse out put trigger via software 0 ? 1 one-shot pulse output the value of this bit is always ?0? when it is read. do not set this bit to 1 in a mode other than the one- shot pulse output mode. if it is set to 1, tm00 is cleared and started. ospe00 one-shot pulse output operation control 0 successive pulse output 1 one-shot pulse output one-shot pulse output operates correctly in the fr ee-running timer mode or clear & start mode entered by ti000 pin valid edge input. the one-shot pulse cannot be output in the clear & start mode entered upon a match between tm00 and cr000. toc004 to00 pin output control on match between cr010 and tm00 0 disables inversion operation 1 enables inversion operation the interrupt signal (inttm010) is generated even when toc004 = 0. lvs00 lvr00 setting of to00 pin output status 0 0 no change 0 1 initial value of to00 pin output is low level (to00 pin output is cleared to 0). 1 0 initial value of to00 pin output is high level (to00 pin output is set to 1). 1 1 setting prohibited ? lvs00 and lvr00 can be used to set the initial value of the output level of the to00 pin. if the initial value does not have to be set, leave lvs00 and lvr00 as 00. ? be sure to set lvs00 and lvr00 when toe00 = 1. lvs00, lvr00, and toe00 being simultaneously set to 1 is prohibited. ? lvs00 and lvr00 are trigger bits. by setting these bits to 1, the initial value of the output level of the to00 pin can be set. even if these bits are clear ed to 0, output of the to00 pin is not affected. ? the values of lvs00 and lvr00 are always 0 when they are read. ? for how to set lvs00 and lvr00, see 7.5.2 setting lvs0n and lvr0n . toc001 to00 pin output control on match between cr000 and tm00 0 disables inversion operation 1 enables inversion operation the interrupt signal (inttm000) is generated even when toc001 = 0. toe00 to00 pin output control 0 disables output (to00 pin output fixed to low level) 1 enables output chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 181 figure 7-18. format of 16-bit timer ou tput control register 01 (toc01) address: ffb9h after reset: 00h r/w symbol 7 <6> <5> 4 <3> <2> 1 <0> toc01 0 ospt01 ospe01 toc014 lvs01 lvr01 toc011 toe01 ospt01 one-shot pulse out put trigger via software 0 ? 1 one-shot pulse output the value of this bit is always 0 w hen it is read. do not set this bit to 1 in a mode other than the one-shot pulse output mode. if it is set to 1, tm01 is cleared and started. ospe01 one-shot pulse output operation control 0 successive pulse output 1 one-shot pulse output one-shot pulse output operates correctly in the fr ee-running timer mode or clear & start mode entered by ti001 pin valid edge input. the one-shot pulse cannot be output in the clear & start mode entered upon a match between tm01 and cr001. toc014 to01 pin output control on match between cr011 and tm01 0 disables inversion operation 1 enables inversion operation the interrupt signal (inttm011) is generated even when toc014 = 0. lvs01 lvr01 setting of to01 pin output status 0 0 no change 0 1 initial value of to01 pin output is low level (to01 pin output is cleared to 0). 1 0 initial value of to01 pin output is high level (to01 pin output is set to 1). 1 1 setting prohibited ? lvs01 and lvr01 can be used to set the initial value of the output level of the to01 pin. if the initial value does not have to be set, leave lvs01 and lvr01 as 00. ? be sure to set lvs01 and lvr01 when toe01 = 1. lvs01, lvr01, and toe01 being simultaneously set to 1 is prohibited. ? lvs01 and lvr01 are trigger bits. by setting these bits to 1, the initial value of the output level of the to01 pin can be set. even if these bits are clear ed to 0, output of the to01 pin is not affected. ? the values of lvs01 and lvr01 are always 0 when they are read. ? for how to set lvs01 and lvr01, see 7.5.2 setting lvs0n and lvr0n . toc011 to01 pin output control on match between cr001 and tm01 0 disables inversion operation 1 enables inversion operation the interrupt signal (inttm001) is generated even when toc011 = 0. toe01 to01 pin output control 0 disables output (to01 pin output is fixed to low level) 1 enables output chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 182 figure 7-19. format of 16-bit timer ou tput control register 02 (toc02) address: ffa5h after reset: 00h r/w symbol 7 <6> <5> 4 <3> <2> 1 <0> toc02 0 ospt02 ospe02 toc024 lvs02 lvr02 toc021 toe02 ospt02 one-shot pulse out put trigger via software 0 ? 1 one-shot pulse output the value of this bit is always 0 w hen it is read. do not set this bit to 1 in a mode other than the one-shot pulse output mode. if it is set to 1, tm02 is cleared and started. ospe02 one-shot pulse output operation control 0 successive pulse output 1 one-shot pulse output one-shot pulse output operates correctly in the fr ee-running timer mode or clear & start mode entered by ti002 pin valid edge input. the one-shot pulse cannot be output in the clear & start mode entered upon a match between tm02 and cr002. toc024 to02 pin output control on match between cr012 and tm02 0 disables inversion operation 1 enables inversion operation the interrupt signal (inttm012) is generated even when toc024 = 0. lvs02 lvr02 setting of to02 pin output status 0 0 no change 0 1 initial value of to02 pin output is low level (to02 pin output is cleared to 0). 1 0 initial value of to02 pin output is high level (to02 pin output is set to 1). 1 1 setting prohibited ? lvs02 and lvr02 can be used to set the initial value of the output level of the to02 pin. if the initial value does not have to be set, leave lvs02 and lvr02 as 00. ? be sure to set lvs02 and lvr02 when toe02 = 1. lvs02, lvr02, and toe02 being simultaneously set to 1 is prohibited. ? lvs02 and lvr02 are trigger bits. by setting these bits to 1, the initial value of the output level of the to02 pin can be set. even if these bits are clear ed to 0, output of the to02 pin is not affected. ? the values of lvs02 and lvr02 are always 0 when they are read. ? for how to set lvs02 and lvr02, see 7.5.2 setting lvs0n and lvr0n . toc021 to02 pin output control on match between cr002 and tm02 0 disables inversion operation 1 enables inversion operation the interrupt signal (inttm002) is generated even when toc012 = 0. toe02 to02 pin output control 0 disables output (to02 pin output is fixed to low level) 1 enables output chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 183 figure 7-20. format of 16-bit timer ou tput control register 03 (toc03) address: fff9h after reset: 00h r/w symbol 7 <6> <5> 4 <3> <2> 1 <0> toc03 0 ospt03 ospe03 toc034 lvs03 lvr03 toc031 toe03 ospt03 one-shot pulse out put trigger via software 0 ? 1 one-shot pulse output the value of this bit is always 0 w hen it is read. do not set this bit to 1 in a mode other than the one-shot pulse output mode. if it is set to 1, tm03 is cleared and started. ospe03 one-shot pulse output operation control 0 successive pulse output 1 one-shot pulse output one-shot pulse output operates correctly in the fr ee-running timer mode or clear & start mode entered by ti003 pin valid edge input. the one-shot pulse cannot be output in the clear & start mode entered upon a match between tm03 and cr003. toc034 to03 pin output control on match between cr013 and tm03 0 disables inversion operation 1 enables inversion operation the interrupt signal (inttm013) is generated even when toc034 = 0. lvs03 lvr03 setting of to03 pin output status 0 0 no change 0 1 initial value of to03 pin output is low level (to03 pin output is cleared to 0). 1 0 initial value of to03 pin output is high level (to03 pin output is set to 1). 1 1 setting prohibited ? lvs03 and lvr03 can be used to set the initial value of the output level of the to03 pin. if the initial value does not have to be set, leave lvs03 and lvr03 as 00. ? be sure to set lvs03 and lvr03 when toe03 = 1. lvs03, lvr03, and toe03 being simultaneously set to 1 is prohibited. ? lvs03 and lvr03 are trigger bits. by setting these bits to 1, the initial value of the output level of the to03 pin can be set. even if these bits are clear ed to 0, output of the to03 pin is not affected. ? the values of lvs03 and lvr03 are always 0 when they are read. ? for how to set lvs03 and lvr03, see 7.5.2 setting lvs0n and lvr0n . toc013 to03 pin output control on match between cr003 and tm03 0 disables inversion operation 1 enables inversion operation the interrupt signal (inttm003) is generated even when toc013 = 0. toe03 to03 pin output control 0 disables output (to03 pin output is fixed to low level) 1 enables output chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 184 (4) prescaler mode register 0n (prm0n) prm0n is the register that se ts the tm0n count clock and ti00n and ti01n pin input valid edges. rewriting prm0n is prohibited during operati on (when tmc0n3 and tmc0n2 = other than 00). prm0n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears prm0n to 00h. cautions 1. do not apply the following setting wh en setting the prm0n1 and prm0n0 bits to 11 (to specify the valid edge of th e ti00n pin as a count clock). ? clear & start mode entered by the ti00n pin valid edge ? setting the ti00n pin as a capture trigger 2. if the operation of the 16- bit timer/event counter 0n is enab led when the ti00n or ti01n pin is at high level and when the valid edge of th e ti00n or ti01n pin is specified to be the rising edge or both edges, the high level of th e ti00n or ti01n pin is detected as a rising edge. note this when the ti00n or ti01n pin is pulled up. ho wever, the rising edge is not detected when the timer oper ation has been once stopped a nd then is enabled again. 3. the valid edge of ti010 and timer output (to 00) cannot be used for the p01 pin at the same time, and the valid edge of ti011 and timer output (to01) cannot be used for the p06 pin at the same time. select ei ther of the functions. remark n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 185 figure 7-21. format of prescaler mode register 00 (prm00) address: ffbbh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 prm00 es101 es100 es001 es000 0 0 prm001 prm000 es101 es100 ti010 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es001 es000 ti000 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges count clock selection prm001 prm000 f prs = 4 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz 0 0 f prs 4 mhz 5 mhz 10 mhz 20 mhz 0 1 f prs /2 2 1 mhz 1.25 mhz 2.5 mhz 5 mhz 1 0 f prs /2 8 15.62 khz 19.53 khz 39.06 khz 78.12 khz 1 1 ti000 valid edge note note the external clock requires a pulse two cycles longer than internal clock (f prs ). cautions 1. always set data to prm 00 after stopping the timer operation. 2. if the valid edge of the ti000 pin is to be set for the count clock, do not set the clear & start mode using the valid edge of the ti000 pin and the capture trigger. 3. if the ti000 or ti010 pin is high level immedi ately after system reset, the rising edge is immediately detected after the ri sing edge or both the rising and falling edges are set as the valid edge(s) of the ti000 pin or ti010 pin to enable the operation of 16-bit timer counter 00 (tm00). care is therefore required when pulling up the ti000 or ti010 pi n. however, when re- enabling operation for ti 000 pin or ti010 pin are high level after the operation has been stopped, the rising edge is not detected. 4. when ti010 pin is used valid edge, it cannot be used as the ti mer output (to00) to p01, and when to00 is used, it cannot be used to the ti010 pin valid edge. remark f prs : peripheral hardware clock frequency chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 186 figure 7-22. format of prescaler mode register 01 (prm01) address: ffb7h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 prm01 es111 es110 es011 es010 0 0 prm011 prm010 es111 es110 ti011 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es011 es010 ti001 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges count clock selection prm011 prm010 f prs = 4 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz 0 0 f prs 4 mhz 5 mhz 10 mhz 20 mhz 0 1 f prs /2 4 250 khz 312.5 khz 625 khz 1.25 mhz 1 0 f prs /2 6 62.5 khz 78.125 khz 156.25 khz 312.5 khz 1 1 ti001 valid edge note note the external clock requires a pulse two cycles longer than internal clock (f prs ). cautions 1. always set data to prm 01 after stopping the timer operation. 2. if the valid edge of the ti001 pin is to be set for the count clock, do not set the clear & start mode using the valid edge of the ti001 pin and the capture trigger. 3. if the ti001 or ti011 pin is high level immedi ately after system reset, the rising edge is immediately detected after the ri sing edge or both the rising and falling edges are set as the valid edge(s) of the ti001 pin or ti011 pin to enable the operation of 16-bit timer counter 01 (tm01). care is therefore required when pulling up the ti001 or ti011 pi n. however, when re- enabling operation for ti 001 pin or ti011 pin are high level after the operation has been stopped, the rising edge is not detected. 4. when ti011 pin is used valid edge, it cannot be used as the ti mer output (to01) to p06, and when to01 is used, it cannot be used to the ti011 pin valid edge. remark f prs : peripheral hardware clock frequency chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 187 figure 7-23. format of prescaler mode register 02 (prm02) address: ff59h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 prm02 es121 es120 es021 es020 0 0 prm021 prm020 es121 es120 ti012 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es021 es020 ti002 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges count clock selection prm021 prm020 f prs = 4 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz 0 0 f prs 4 mhz 5 mhz 10 mhz 20 mhz 0 1 f prs /2 2 1 mhz 1.25 mhz 2.5 mhz 5 mhz 1 0 f prs /2 8 15.62 khz 19.53 khz 39.06 khz 78.12 khz 1 1 ti002 valid edge note note the external clock requires a pulse two cycles longer than internal clock (f prs ). cautions 1. always set data to prm 02 after stopping the timer operation. 2. if the valid edge of the ti002 pin is to be set for the count clock, do not set the clear & start mode using the valid edge of the ti002 pin and the capture trigger. 3. if the ti002 or ti012 pin is high level immedi ately after system reset, the rising edge is immediately detected after the ri sing edge or both the rising and falling edges are set as the valid edge(s) of the ti002 pin or ti012 pin to enable the operation of 16-bit timer counter 02 (tm02). care is therefore required when pulling up the ti002 or ti012 pi n. however, when re- enabling operation for ti 002 pin or ti012 pin are high level after the operation has been stopped, the rising edge is not detected. 4. when ti012 pin is used valid edge, it cannot be used as the ti mer output (to02) to p32, and when to02 is used, it cannot be used to the ti012 pin valid edge. remark f prs : peripheral hardware clock frequency chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 188 figure 7-24. format of prescaler mode register 03 (prm03) address: ff51h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 prm03 es131 es130 es031 es030 0 0 prm031 prm030 es131 es130 ti013 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es031 es030 ti003 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges count clock selection prm031 prm030 f prs = 4 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz 0 0 f prs 4 mhz 5 mhz 10 mhz 20 mhz 0 1 f prs /2 4 250 khz 312.5 khz 625 khz 1.25 mhz 1 0 f prs /2 6 62.5 khz 78.125 khz 156.25 khz 312.5 khz 1 1 ti003 valid edge note note the external clock requires a pulse two cycles longer than internal clock (f prs ). cautions 1. always set data to prm 03 after stopping the timer operation. 2. if the valid edge of the ti003 pin is to be set for the count clock, do not set the clear & start mode using the valid edge of the ti003 pin and the capture trigger. 3. if the ti003 or ti013 pin is high level immedi ately after system reset, the rising edge is immediately detected after the ri sing edge or both the rising and falling edges are set as the valid edge(s) of the ti003 pin or ti013 pin to enable the operation of 16-bit timer counter 03 (tm03). care is therefore required when pulling up the ti003 or ti013 pi n. however, when re- enabling operation for ti 003 pin or ti013 pin are high level after the operation has been stopped, the rising edge is not detected. 4. when ti013 pin is used valid edge, it cannot be used as the timer output (to03) to p132, and when to03 is used, it cannot be used to the ti013 pin valid edge. remark f prs : peripheral hardware clock frequency chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 189 (5) port mode register 0 (pm0) this register sets port 0 input/output in 1-bit units. when using the p01/to00/ti010 and p 06/to01/ti011 pins for timer outpu t, set pm01 and pm06 and the output latch of p01 and p06 to 0. when using the p01/to00/ti010 and p06/to 01/ti011 pins for timer input, set pm01 and pm06 to 1. at this time, the output latch of p01 and p06 may be 0 or 1. pm0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pm0 to ffh. figure 7-25. format of port mode register 0 (pm0) address: ff20h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm0 1 pm06 pm05 1 1 1 pm01 pm00 pm0n p0n pin i/o mode selection (n = 0, 1, 5, 6) 0 output mode (output buffer on) 1 input mode (output buffer off) (6) port mode register 3 (pm3) this register sets port 3 input/output in 1-bit units. when using the p32/to02/ti012/intp3 pin for timer out put, set pm32 and the output latch of p32 to 0. when using the p31/ti002/intp2 and p32/ ti012/to02/intp3 pins for timer inpu t, set pm31 and pm32 to 1. at this time, the output latch of p31 and p32 may be 0 or 1. pm3 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pm3 to ffh. figure 7-26. format of port mode register 3 (pm3) address: ff23h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm3 1 1 1 1 pm33 pm32 pm31 pm30 pm3n p3n pin i/o mode selection (n = 0 to 3) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 190 (7) port mode register 13 (pm13) this register sets port 13 input/output in 1-bit units. when using the p132/to03/ti013 pin for timer output, set pm132 and the output latch of p132 to 0. when using the p131/ti003 and p132/ti013 /to03 pins for timer input, set pm131 and pm132 to 1. at this time, the output latch of p131 and p132 may be 0 or 1. pm13 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pm13 to ffh. figure 7-27. format of port mode register 13 (pm13) address: ff2dh after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm13 1 1 1 1 1 pm132 pm131 0 pm13n p13n pin i/o mode selection (n = 1, 2) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 191 7.4 operation of 16-bit timer/event counters 00 to 03 7.4.1 interval timer operation setting 16-bit timer mode control register 0n (tmc0n) and capture/compare control register 0n (crc0n) as shown in figure 7-28 allows operation as an interval timer. setting the basic operation setting procedure is as follows. <1> set the crc0n register (see figure 7-28 for the set value). <2> set any value to the cr00n register. <3> set the count clock by using the prm0n register. <4> set the tmc0n register to start the operation (see figure 7-28 for the set value). caution cr00n cannot be rewr itten during tm0n operation. remark for how to enable the inttm00n interrupt, see chapter 17 interrupt functions . interrupt requests are generated repeatedly using the count value preset in 16-bit timer capture/compare register 00n (cr00n) as the interval. when the count value of 16-bit timer counter 0n (tm0n) matches the value set in cr00n, counting continues with the tm0n value cleared to 0 and the interrupt request signal (inttm00n) is generated. the count clock of 16-bit timer/event counter 0n can be selected with bits 0 and 1 (prm0n0, prm0n1) of prescaler mode register 0n (prm0n). remark n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 192 figure 7-28. control register setti ngs for interval timer operation (a) 16-bit timer mode cont rol register 0n (tmc0n) 7 0 6 0 5 0 4 0 tmc0n3 1 tmc0n2 1 tmc0n1 0/1 ovf0n 0 tmc0n clears and starts on match between tm0n and cr00n. (b) capture/compare cont rol register 0n (crc0n) 7 0 6 0 5 0 4 0 3 0 crc0n2 0/1 crc0n1 0/1 crc0n0 0 crc0n cr00n used as compare register (c) prescaler mode register 0n (prm0n) es1n1 0/1 es1n0 0/1 es0n1 0/1 es0n0 0/1 3 0 2 0 prm0n1 0/1 prm0n0 0/1 prm0n selects count clock. setting invalid (setting ?10? is prohibited.) setting invalid (setting ?10? is prohibited.) remarks 1. 0/1: setting 0 or 1 allows another function to be used simultaneously with the interval timer. see the description of the respective control registers for details. 2. n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 193 figure 7-29. interval ti mer configuration diagram 16-bit timer capture/compare register 00n (cr00n) 16-bit timer counter 0n (tm0n) ovf0n clear circuit inttm00n f prs (f prs ) note 1 f prs /2 2 (f prs /2 4 ) note 1 f prs /2 8 (f prs /2 6 ) note 1 ti000/p00 (ti001/p05) ti002/p31 (ti003/p131) note 1 selector noise eliminator f prs note 2 notes 1. frequencies and pin names without parentheses ar e for 16-bit timer/event counter 00 and 02, and those in parentheses are for 16-bi t timer/event counter 01 and 03. 2. ovf0n is set to 1 only when 16-bit timer capt ure/compare register 00n is set to ffffh. figure 7-30. timing of interval timer operation count clock t tm0n count value cr00n inttm00n 0000h 0001h n 0000h 0001h n 0000h 0001h n n n n n timer operation enabled clear clear interrupt acknowledged interrupt acknowledged remark interval time = (n + 1) t n = 0001h to ffffh n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 194 7.4.2 ppg output operations setting 16-bit timer mode control register 0n (tmc0n) and capture/compare control register 0n (crc0n) as shown in figure 7-31 allows operation as ppg (programmable pulse generator) output. setting the basic operation setting procedure is as follows. <1> set the crc0n register (see figure 7-31 for the set value). <2> set any value to the cr00n register as the cycle. <3> set any value to the cr01n register as the duty factor. <4> set the toc0n register (see figure 7-31 for the set value). <5> set the count clock by using the prm0n register. <6> set the tmc0n register to start the operation (see figure 7-31 for the set value). caution to change the value of the duty factor (the value of the cr01n register) during operation, see caution 2 in figure 7-33 ppg output operation timing. remarks 1. for the setting of the to0n pin, see 7.3 (5) port mode register 0 (pm0) to (7) port mode register 13 (pm13) . 2. for how to enable the inttm00n interrupt, see chapter 17 interrupt functions . in the ppg output oper ation, rectangular wa ves are output from the to0n pin with the pulse wi dth and the cycle that correspond to the count values preset in 16-bit time r capture/compare register 01n (cr01n) and in 16-bit timer capture/compare register 00n (cr00n), respectively. remark n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 195 figure 7-31. control register settings for ppg output operation (a) 16-bit timer mode cont rol register 0n (tmc0n) 7 0 6 0 5 0 4 0 tmc0n3 1 tmc0n2 1 tmc0n1 0 ovf0n 0 tmc0n clears and starts on match between tm0n and cr00n. (b) capture/compare cont rol register 0n (crc0n) 7 0 6 0 5 0 4 0 3 0 crc0n2 0 crc0n1 crc0n0 0 crc0n cr00n used as compare register cr01n used as compare register (c) 16-bit timer output control register 0n (toc0n) 7 0 ospt0n 0 ospe0n 0 toc0n4 1 lvs0n 0/1 lvr0n 0/1 toc0n1 1 toe0n 1 toc0n enables to0n output. inverts output on match between tm0n and cr00n. specifies initial value of to0n output f/f (setting ?11? is prohibited). inverts output on match between tm0n and cr01n. disables one-shot pulse output. (d) prescaler mode register 0n (prm0n) es1n1 0/1 es1n0 0/1 es0n1 0/1 es0n0 0/1 3 0 2 0 prm0n1 0/1 prm0n0 0/1 prm0n selects count clock. setting invalid (setting ?10? is prohibited.) setting invalid (setting ?10? is prohibited.) cautions 1. values in the following ra nge should be set in cr00n and cr01n: 0000h cr01n < cr00n ffffh 2. the cycle of the pulse generated through ppg output (cr00n setting value + 1) has a duty of (cr01n setting value + 1)/(cr00n setting value + 1). remark : don?t care n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 196 figure 7-32. configuration diagram of ppg output 16-bit timer capture/compare register 00n (cr00n) 16-bit timer counter 0n (tm0n) clear circuit noise eliminator f prs f prs (f prs ) note f prs /2 2 (f prs /2 4 ) note f prs /2 8 (f prs /2 6 ) note ti000/p00 (ti001/p05) ti002/p31 (ti003/p131) note 16-bit timer capture/compare register 01n (cr01n) to00/ti010/p01 (to01/ti011/p06) to02/ti012/p32 (to03/ti013/p132) note selector output controller note frequencies and pin names without parentheses are for 16-bit timer/event counter 00 and 02, and those in parentheses are for 16-bit timer/event counter 01 and 03. figure 7-33. ppg output operation timing t 0000h 0000h 0001h 0001h m ? 1 count clock tm0n count value to0n pulse width: (m + 1) t 1 cycle: (n + 1) t n cr00n capture value cr01n capture value m m n ? 1 n n clear clear cautions 1. cr00n cannot be re written during tm0n operation. 2. in the ppg output operatio n, change the pulse width (rew rite cr01n) during tm0n operation using the following procedure. <1> disable the timer output inversion operati on by match of tm0n and cr01n (toc0n4 = 0) <2> disable the inttm01n interrupt (tmmk01n = 1) <3> rewrite cr01n <4> wait for 1 cycle of the tm0n count clock <5> enable the timer output inversion operati on by match of tm0n and cr01n (toc0n4 = 1) <6> clear the interrupt request flag of inttm01n (tmif01n = 0) <7> enable the inttm01n interrupt (tmmk01n = 0) remarks 1. 0000h m < n ffffh 2. n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 197 7.4.3 pulse width measurement operations it is possible to measure the pulse width of the signal s input to the ti00n pin and ti01n pin using 16-bit timer counter 0n (tm0n). there are two measurement methods : measuring with tm0n used in free -running mode, and measuring by restarting the timer in synchronization with th e edge of the signal in put to the ti00n pin. when an interrupt occurs, read the valid value of the capt ure register, check the overflow flag, and then calculate the necessary pulse width. clear the overflow flag after checking it. the capture operation is not performed unt il the signal pulse width is sampl ed in the count clock cycle selected by prescaler mode register 0n (prm0n) and the valid level of the ti00n or ti01n pin is dete cted twice, thus eliminating noise with a short pulse width. figure 7-34. cr01n capture operat ion with rising edge specified count clock tm0n ti00n rising edge detection cr01n inttm01n n ? 3n ? 2n ? 1 n n + 1 n setting the basic operation setting procedure is as follows. <1> set the crc0n register (see figures 7-35 , 7-38 , 7-40 , and 7-42 for the set value). <2> set the count clock by using the prm0n register. <3> set the tmc0n register to start the operation (see figures 7-35 , 7-38 , 7-40 , and 7-42 for the set value). caution to use two capture register s, set the ti00n and ti01n pins. remarks 1. for the setting of the ti 00n (or ti01n) pin, see 7.3 (5) port mode register 0 (pm0) to (7) port mode register 13 (pm13) . 2. for how to enable the inttm00n (or inttm01n) interrupt, see chapter 17 interrupt functions . 3. n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 198 (1) pulse width measurement with free-runni ng counter and one capture register when 16-bit timer counter 0n (tm0n) is operated in free-ru nning mode, and the edge specified by prescaler mode register 0n (prm0n) is input to the ti00n pin, the value of tm0n is taken into 16-bit timer capture/compare register 01n (cr01n) and an external interrupt request signal (inttm01n) is set. specify both the rising and falling edges of the ti00n pin by using bits 4 and 5 (es0n0 and es0n1) of prm0n. sampling is performed using the count clock selected by prm0n, and a capture operation is only performed when a valid level of the ti00n pin is detected twic e, thus eliminating noise with a short pulse width. figure 7-35. control register settings for pul se width measurement with free-running counter and one capture register (whe n ti00n and cr01n are used) (a) 16-bit timer mode cont rol register 0n (tmc0n) 7 0 6 0 5 0 4 0 tmc0n3 0 tmc0n2 1 tmc0n1 0/1 ovf0n 0 tmc0n free-running mode (b) capture/compare cont rol register 0n (crc0n) 7 0 6 0 5 0 4 0 3 0 crc0n2 1 crc0n1 0/1 crc0n0 0 crc0n cr00n used as compare register cr01n used as capture register (c) prescaler mode register 0n (prm0n) es1n1 0/1 es1n0 0/1 es0n1 1 es0n0 1 3 0 2 0 prm0n1 0/1 prm0n0 0/1 prm0n selects count clock (setting ?11? is prohibited). specifies both edges for pulse width detection. setting invalid (setting ?10? is prohibited.) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respecti ve control registers for details. n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 199 figure 7-36. configuration di agram for pulse width measureme nt with free-running counter f prs (f prs ) note f prs /2 2 (f prs /2 4 ) note f prs /2 8 (f prs /2 6 ) note ti00n 16-bit timer counter 0n (tm0n) ovf0n 16-bit timer capture/compare register 01n (cr01n) internal bus inttm01n selector note frequencies without parentheses are for 16-bit timer/ev ent counter 00 and 02, and those in parentheses are for 16-bit timer/event counter 01 and 03. figure 7-37. timing of pulse width measureme nt operation with free-running counter and one capture register ( with both edges specified) t 0000h 0000h ffffh 0001h d0 d0 count clock tm0n count value ti00n pin input cr01n capture value inttm01n ovf0n (d1 ? d0) t (d3 ? d2) t (10000h ? d1 + d2) t d1 d2 d3 d2 d3 d0 + 1 d1 d1 + 1 note note clear ovf0n by software. remark n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 200 (2) measurement of two pulse widths with free-running counter when 16-bit timer counter 0n (tm0n) is operated in free- running mode, it is possible to simultaneously measure the pulse widths of the two signals input to the ti00n pin and the ti01n pin. when the edge specified by bits 4 and 5 (es0n0 and es0n1) of prescaler mode register 0n (prm0n) is input to the ti00n pin, the value of tm0n is taken into 16-bit time r capture/compare register 01n (cr01n) and an interrupt request signal (inttm01n) is set. also, when the edge specified by bits 6 and 7 (es1n0 and es1n1) of prm0n is input to the ti01n pin, the value of tm0n is taken into 16-bit timer capture/compare register 00n (cr00n) and an interrupt request signal (inttm00n) is set. specify both the rising and falling edges as the edges of the ti00n and ti01n pins, by using bits 4 and 5 (es0n0 and es0n1) and bits 6 and 7 (es1n0 and es1n1) of prm0n. sampling is performed using the co unt clock cycle selected by prescale r mode register 0n (prm0n), and a capture operation is only performed when a valid level of the ti00n or ti01n pin is detected twice, thus eliminating noise with a short pulse width. figure 7-38. control register settings for measure ment of two pulse widths with free-running counter (a) 16-bit timer mode cont rol register 0n (tmc0n) 7 0 6 0 5 0 4 0 tmc0n3 0 tmc0n2 1 tmc0n1 0/1 ovf0n 0 tmc0n free-running mode (b) capture/compare cont rol register 0n (crc0n) 7 0 6 0 5 0 4 0 3 0 crc0n2 1 crc0n1 0 crc0n0 1 crc0n cr00n used as capture register captures valid edge of ti01n pin to cr00n. cr01n used as capture register (c) prescaler mode register 0n (prm0n) es1n1 1 es1n0 1 es0n1 1 es0n0 1 3 0 2 0 prm0n1 0/1 prm0n0 0/1 prm0n selects count clock (setting ?11? is prohibited). specifies both edges for pulse width detection. specifies both edges for pulse width detection. remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respecti ve control registers for details. n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 201 figure 7-39. timing of pulse width measure ment operation with free-running counter (with both edges specified) t 0000h 0000h ffffh 0001h d0 d0 ti01n pin input cr00n capture value inttm01n inttm00n ovf0n (d1 ? d0) t (d3 ? d2) t (10000h ? d1 + d2) t (10000h ? d1 + (d2 + 1)) t d1 d2 + 1 d1 d2 d2 d3 d0 + 1 d1 d1 + 1 d2 + 1 d2 + 2 count clock tm0n count value ti00n pin input cr01n capture value note note clear ovf0n by software. remark n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 202 (3) pulse width measurement with free-runni ng counter and two capture registers when 16-bit timer counter 0n (tm0n) is operated in free-running mode, it is possible to measure the pulse width of the signal input to the ti00n pin. when the rising or falling edge specified by bits 4 and 5 (es0n0 and es0n1) of prescaler mode register 0n (prm0n) is input to the ti00n pin, the value of tm0n is taken into 16-bi t timer capture/compare register 01n (cr01n) and an interrupt request signal (inttm01n) is set. also, when the inverse edge to that of the capture operation is input into cr 01n, the value of tm0n is taken into 16-bit timer capture/compare register 00n (cr00n). sampling is performed using the co unt clock cycle selected by prescale r mode register 0n (prm0n), and a capture operation is only performed when a valid level of the ti00n pin is detec ted twice, thus eliminating noise with a short pulse width. figure 7-40. control register settings for pulse width measurement with fr ee-running counter and two capture registers (with rising edge specified) (a) 16-bit timer mode cont rol register 0n (tmc0n) 7 0 6 0 5 0 4 0 tmc0n3 0 tmc0n2 1 tmc0n1 0/1 ovf0n 0 tmc0n free-running mode (b) capture/compare cont rol register 0n (crc0n) 7 0 6 0 5 0 4 0 3 0 crc0n2 1 crc0n1 1 crc0n0 1 crc0n cr00n used as capture register captures to cr00n at inverse edge to valid edge of ti00n. cr01n used as capture register (c) prescaler mode register 0n (prm0n) es1n1 0/1 es1n0 0/1 es0n1 0 es0n0 1 3 0 2 0 prm0n1 0/1 prm0n0 0/1 prm0n selects count clock (setting ?11? is prohibited). specifies rising edge for pulse width detection. setting invalid (setting ?10? is prohibited.) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respecti ve control registers for details. n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 203 figure 7-41. timing of pulse width measureme nt operation with free-running counter and two capture registers (with rising edge specified) t 0000h 0000h ffffh 0001h d0 d0 inttm01n ovf0n d2 d1 d3 d2 d3 d0 + 1 d2 + 1 d1 d1 + 1 cr00n capture value count clock tm0n count value ti00n pin input cr01n capture value (d1 ? d0) t (d3 ? d2) t (10000h ? d1 + d2) t note note clear ovf0n by software. (4) pulse width measurement by means of restart when input of a valid edge to the ti00n pi n is detected, the count value of 16- bit timer counter 0n (tm0n) is taken into 16-bit timer capture/compare register 01n (cr01n), and then the pulse width of t he signal input to the ti00n pin is measured by clearing tm0n and restarting the count operation. either of two edges ? rising or falling ? can be selected using bits 4 and 5 ( es0n0 and es0n1) of prescaler mode register 0n (prm0n). sampling is performed using the count clock cycle sele cted by prescaler mode register 0n (prm0n) and a capture operation is only performed when a valid level of the ti00n pin is detec ted twice, thus eliminating noise with a short pulse width. remark n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 204 figure 7-42. control register settings for pu lse width measurement by means of restart (with rising edge specified) (a) 16-bit timer mode cont rol register 0n (tmc0n) 7 0 6 0 5 0 4 0 tmc0n3 1 tmc0n2 0 tmc0n1 0/1 ovf0n 0 tmc0n clears and starts at valid edge of ti00n pin. (b) capture/compare cont rol register 0n (crc0n) 7 0 6 0 5 0 4 0 3 0 crc0n2 1 crc0n1 1 crc00n 1 crc0n cr00n used as capture register captures to cr00n at inverse edge to valid edge of ti00n. cr01n used as capture register (c) prescaler mode register 0n (prm0n) es1n1 0/1 es1n0 0/1 es0n1 0 es0n0 1 3 0 2 0 prm0n1 0/1 prm0n0 0/1 prm0n selects count clock (setting ?11? is prohibited). specifies rising edge for pulse width detection. setting invalid (setting ?10? is prohibited.) figure 7-43. timing of pulse width measurement operation by means of restart (with risi ng edge specified) t 0000h 0001h 0000h 0001h 0000h 0001h d0 d0 inttm01n d1 t d2 t d2 d1 d2 d1 cr00n capture value count clock tm0n count value ti00n pin input cr01n capture value remark n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 205 7.4.4 external event counter operation setting the basic operation setting procedure is as follows. <1> set the crc0n register (see figure 7-44 for the set value). <2> set the count clock by using the prm0n register. <3> set any value to the cr00n register (0000h cannot be set). <4> set the tmc0n register to start the operation (see figure 7-44 for the set value). remarks 1. for the setting of the ti00n pin, see 7.3 (5) port mode register 0 (pm0) to (7) port mode register 13 (pm13) . 2. for how to enable the inttm00n interrupt, see chapter 17 interrupt functions . the external event counter counts the num ber of external clock pulses input to the ti00n pin using 16-bit timer counter 0n (tm0n). tm0n is incremented each time the valid edge specified by prescaler mode register 0n (prm0n) is input. when the tm0n count value matches the 16-bit timer capt ure/compare register 00n (cr00n) value, tm0n is cleared to 0 and the interrupt requ est signal (inttm00n) is generated. input a value other than 0000h to cr00n (a count operation with 1-bit pulse cannot be carried out). any of three edges ? rising, falling, or both edges ? can be selected using bits 4 and 5 (es0n0 and es0n1) of prescaler mode register 0n (prm0n). sampling is performed using the internal clock (f prs ) and an operation is only performed when a valid level of the ti00n pin is detected twice, thus eliminating noise with a short pulse width. chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 206 figure 7-44. control register setti ngs in external event counter mode (with rising edge specified) (a) 16-bit timer mode cont rol register 0n (tmc0n) 7 0 6 0 5 0 4 0 tmc0n3 1 tmc0n2 1 tmc0n1 0/1 ovf0n 0 tmc0n clears and starts on match between tm0n and cr00n. (b) capture/compare cont rol register 0n (crc0n) 7 0 6 0 5 0 4 0 3 0 crc0n2 0/1 crc0n1 0/1 crc0n0 0 crc0n cr00n used as compare register (c) prescaler mode register 0n (prm0n) es1n1 0/1 es1n0 0/1 es0n1 0 es0n0 1 3 0 2 0 prm0n1 1 prm0n0 1 prm0n selects external clock. specifies rising edge for pulse width detection. setting invalid (setting ?10? is prohibited.) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with the external event counter. see the description of the respecti ve control registers for details. n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 207 figure 7-45. configuration diagra m of external event counter f prs internal bus 16-bit timer capture/compare register 00n (cr00n) match clear ovf0n note noise eliminator 16-bit timer counter 0n (tm0n) valid edge of ti00n pin inttm00n note ovf0n is set to 1 only when cr00n is set to ffffh. figure 7-46. external event counter oper ation timing (with rising edge specified) ti00n pin input tm0n count value cr00n inttm00n 0000h 0001h 0002h 0003h 0004h 0005h n ? 1 n 0000h 0001h 0002h 0003h n caution when reading the ext ernal event counter count val ue, tm0n should be read. remark n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 208 7.4.5 square-wave output operation setting the basic operation setting procedure is as follows. <1> set the count clock by using the prm0n register. <2> set the crc0n register (see figure 7-47 for the set value). <3> set the toc0n register (see figure 7-47 for the set value). <4> set any value to the cr00n register (0000h cannot be set). <5> set the tmc0n register to start the operation (see figure 7-47 for the set value). caution cr00n cannot be rewr itten during tm0n operation. remarks 1. for the setting of the to0n pin, see 7.3 (5) port mode register 0 (pm0) to (7) port mode register 13 (pm13) . 2. for how to enable the inttm00n interrupt, see chapter 17 interrupt functions . a square wave with any selected frequency can be output at intervals determined by the count value preset to 16- bit timer capture/compare register 00n (cr00n). the to0n pin output status is reversed at intervals determined by the count value preset to cr00n + 1 by setting bit 0 (toe0n) and bit 1 (toc0n1) of 16-bit timer output control register 0n (toc0n) to 1. this enables a square wave with any selected frequency to be output. figure 7-47. control register settings in square-wave output mode (1/2) (a) 16-bit timer mode cont rol register 0n (tmc0n) 7 0 6 0 5 0 4 0 tmc0n3 1 tmc0n2 1 tmc0n1 0 ovf0n 0 tmc0n clears and starts on match between tm0n and cr00n. (b) capture/compare cont rol register 0n (crc0n) 7 0 6 0 5 0 4 0 3 0 crc0n2 0/1 crc0n1 0/1 crc0n0 0 crc0n cr00n used as compare register chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 209 figure 7-47. control register settings in square-wave output mode (2/2) (c) 16-bit timer output control register 0n (toc0n) 7 0 ospt0n 0 ospe0n 0 toc0n4 0 lvs0n 0/1 lvr0n 0/1 toc0n1 1 toe0n 1 toc0n enables to0n output. inverts output on match between tm0n and cr00n. specifies initial value of to0n output f/f (setting ?11? is prohibited). does not invert output on match between tm0n and cr01n. disables one-shot pulse output. (d) prescaler mode register 0n (prm0n) es1n1 0/1 es1n0 0/1 es0n1 0/1 es0n0 0/1 3 0 2 0 prm0n1 0/1 prm0n0 0/1 prm0n selects count clock. setting invalid (setting ?10? is prohibited.) setting invalid (setting ?10? is prohibited.) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with square-wave output. see the description of the respective control registers for details. n = 0 to 3 figure 7-48. square-wave output operation timing count clock tm0n count value cr00n inttm00n to0n pin output 0000h 0001h 0002h n ? 1 n 0000h 0001h 0002h n ? 1 n 0000h n remark n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 210 7.4.6 one-shot pulse output operation 16-bit timer/event counter 0n can output a one-shot pulse in synchronization with a software trigger or an external trigger (ti00n pin input). setting the basic operation setting procedure is as follows. <1> set the count clock by using the prm0n register. <2> set the crc0n register (see figures 7-49 and 7-51 for the set value). <3> set the toc0n register (see figures 7-49 and 7-51 for the set value). <4> set any value to the cr00n and cr01n registers (0000h cannot be set). <5> set the tmc0n register to start the operation (see figures 7-49 and 7-51 for the set value). remarks 1. for the setting of the to0n pin, see 7.3 (5) port mode register 0 (pm0) to (7) port mode register 13 (pm13) . 2. for how to enable the inttm00n (if necessary, inttm01n) interrupt, see chapter 17 interrupt functions . (1) one-shot pulse output with software trigger a one-shot pulse can be output from t he to0n pin by setting 16-bit timer mode control register 0n (tmc0n), capture/compare control register 0n (crc0n), and 16-bit timer output control register 0n (toc0n) as shown in figure 7-49, and by setting bit 6 (ospt0n) of the toc0n register to 1 by software. by setting the ospt0n bit to 1, 16-bit timer/event co unter 0n is cleared and starte d, and its output becomes active at the count value (n) set in advance to 16-bit time r capture/compare register 01n (cr01n). after that, the output becomes inactive at the count value (m) set in advance to 16-bit timer capture/compare register 00n (cr00n) note . even after the one-shot pulse has been output, the tm0n regi ster continues its operat ion. to stop the tm0n register, the tmc0n3 and tmc0n2 bits of t he tmc0n register must be set to 00. note the case where n < m is described here. when n > m, the output becomes active with the cr00n register and inactive with the cr01n register. do not set n to m. cautions 1. do not set the ospt0n bit while the one-shot pulse is being output. to output the one- shot pulse again, wait until the current one-shot pulse output is completed. 2. when using the one-shot pulse output of 16-bit timer/event counter 0n with a software trigger, do not change the level of the ti 00n pin or its alternate-function port pin. because the external trigger is valid even in this case, the timer is cleared and started even at the level of the ti00n pin or its alternate-function po rt pin, resulting in the output of a pulse at an undesired timing. remark n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 211 figure 7-49. control register settings for on e-shot pulse output with software trigger (a) 16-bit timer mode cont rol register 0n (tmc0n) 0000 7654 0 tmc0n3 tmc0n tmc0n2 tmc0n1 ovf0n free-running mode 100 (b) capture/compare cont rol register 0n (crc0n) 00000 76543 crc0n crc0n2 crc0n1 crc0n0 cr00n as compare register cr01n as compare register 0 0/1 0 (c) 16-bit timer output control register 0n (toc0n) 0 7 0 1 1 0/1 toc0n lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n enables to0n output. inverts output upon match between tm0n and cr00n. specifies initial value of to0n output f/f (setting ?11? is prohibited.) inverts output upon match between tm0n and cr01n. sets one-shot pulse output mode. set to 1 for output. 0/1 1 1 (d) prescaler mode register 0n (prm0n) 0/1 0/1 0/1 0/1 0 prm0n prm0n1 prm0n0 selects count clock. setting invalid (setting ?10? is prohibited.) 0 0/1 0/1 es1n1 es1n0 es0n1 es0n0 setting invalid (setting ?10? is prohibited.) 32 caution do not set 0000h to the cr00n and cr01n registers. remark n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 212 figure 7-50. timing of one-shot pulse output operation with software trigger 0000h n nn n n mm m m nm n + 1 n ? 1 m ? 1 0001h m + 1 m + 2 0000h count clock tm0n count cr01n set value cr00n set value ospt0n inttm01n inttm00n to0n pin output set tmc0n to 04h (tm0n count starts) caution 16-bit timer counter 0n st arts operating as soon as a value othe r than 00 (operation stop mode) is set to the tmc0n3 and tmc0n2 bits. remark n < m (2) one-shot pulse output with external trigger a one-shot pulse can be output from t he to0n pin by setting 16-bit timer mode control register 0n (tmc0n), capture/compare control register 0n (crc0n), and 16-bit timer output control register 0n (toc0n) as shown in figure 7-51, and by using the valid edge of the ti00n pin as an external trigger. the valid edge of the ti00n pin is specified by bits 4 and 5 (es0n0, es 0n1) of prescaler mode register 0n (prm0n). the rising, falling, or both the rising and falling edges can be specified. when the valid edge of the ti00n pin is detected, the 16-bit time r/event counter is clear ed and started, and the output becomes active at the count value set in advance to 16-bit timer capture/compare register 01n (cr01n). after that, the output becomes inactive at the count value set in advance to 16-bit timer capture/compare register 00n (cr00n) note . note the case where n < m is described here. when n > m, the output becomes active with the cr00n register and inactive with the cr01n register. do not set n to m. caution even if the external trigger is generated again while the one-shot pulse is output, it is ignored. remark n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 213 figure 7-51. control register settings for on e-shot pulse output with external trigger (with rising edge specified) (a) 16-bit timer mode cont rol register 0n (tmc0n) 0000 7654 1 tmc0n3 tmc0n tmc0n2 tmc0n1 ovf0n clears and starts at valid edge of ti00n pin. 000 (b) capture/compare cont rol register 0n (crc0n) 00000 76543 crc0n crc0n2 crc0n1 crc0n0 cr00n used as compare register cr01n used as compare register 0 0/1 0 (c) 16-bit timer output control register 0n (toc0n) 0 7 01 1 0/1 toc0n lvr0n toc0n1 toe0n ospe0n ospt0n toc0n4 lvs0n enables to0n output. inverts output upon match between tm0n and cr00n. specifies initial value of to0n output f/f (setting ?11? is prohibited.) inverts output upon match between tm0n and cr01n. sets one-shot pulse output mode. 0/1 1 1 (d) prescaler mode register 0n (prm0n) 0/1 0/1 0 1 prm0n prm0n1 prm0n0 selects count clock (setting ?11? is prohibited). specifies the rising edge for pulse width detection. 0/1 0/1 es1n1 es1n0 es0n1 es0n0 setting invalid (setting ?10? is prohibited.) 00 32 caution do not set the cr00n a nd cr01n registers to 0000h. remark n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 214 figure 7-52. timing of one-shot pulse output operation with external trigger (wit h rising edge specified) 0000h n nn n n mm m m m n + 1 n + 2 m + 1 m + 2 m ? 2 m ? 1 0001h 0000h count clock tm0n count value cr01n set value cr00n set value ti00n pin input inttm01n inttm00n to0n pin output when tmc0n is set to 08h (tm0n count starts) t caution 16-bit timer counter 0n st arts operating as soon as a value othe r than 00 (operation stop mode) is set to the tmc0n2 and tmc0n3 bits. remark n < m n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 215 7.5 special use of tm0n 7.5.1 rewriting cr01n during tm0n operation in principle, rewriting cr00n and cr01n of the 78k0/ff2 when they are used as compare registers is prohibited while tm0n is operating (tmc0n3 and tmc0n2 = other than 00). however, the value of cr01n can be changed, even while tm0n is operating, using the following procedure if cr01n is used for ppg output and the duty factor is chang ed (change the value of cr01n immediately after its value matches the value of tm0n. if t he value of cr01n is changed immediatel y before its value matches tm0n, an unexpected operation may be performed). procedure for changing value of cr01n <1> disable interrupt inttm01n (tmmk01n = 1). <2> disable reversal of the timer output when th e value of tm0n matches that of cr01n (toc0n4 = 0). <3> change the value of cr01n. <4> wait for one cycle of the count clock of tm0n. <5> enable reversal of the timer output when the value of tm0n matches that of cr01n (toc0n4 = 1). <6> clear the interrupt flag of inttm01n (tmif01n = 0) to 0. <7> enable interrupt inttm01n (tmmk01n = 0). remark for tmif01n and tmmk01n, see chapter 17 interrupt functions . 7.5.2 setting lvs0n and lvr0n (1) usage of lvs0n and lvr0n lvs0n and lvr0n are used to set the default value of the to0n pin output and to inve rt the timer output without enabling the timer operation (tmc0n3 and tmc0n2 = 00). clear lvs0n and lvr0n to 00 (default value: low- level output) when software control is unnecessary. lvs0n lvr0n timer output status 0 0 not changed (low-level output) 0 1 cleared (low-level output) 1 0 set (high-level output) 1 1 setting prohibited remark n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 216 (2) setting lvs0n and lvr0n set lvs0n and lvr0n using the following procedure. figure 7-53. example of flow for setting lvs0n and lvr0n bits setting toc0n.ospe0n, toc0n4, toc0n1 bits setting toc0n.toe0n bit setting toc0n.lvs0n, lvr0n bits setting tmc0n.tmc0n3, tmc0n2 bits <3> enabling timer operation <2> setting of timer output f/f <1> setting of timer output operation caution be sure to set lvs0n and lvr0n fo llowing steps <1>, <2>, and <3> above. step <2> can be performed after <1> and before <3>. figure 7-54. timing example of lvr0n and lvs0n toc0n.lvs0n bit toc0n.lvr0n bit operable bits (tmc0n3, tmc0n2) to0n pin output inttm00n signal <1> 00 <2> <1> <3> <4> <4> <4> 01, 10, or 11 <1> the to0n pin output goes high when lvs0n and lvr0n = 10. <2> the to0n pin output goes low when lvs0n and lv r0n = 01 (the pin output remains unchanged from the high level even if lvs0n and lvr0n are cleared to 00). <3> the timer starts operating when tmc0n3 and tmc0n2 are set to 01, 10, or 11. because lvs0n and lvr0n were set to 10 before the operat ion was started, the to 0n pin output starts from the high level. after the timer starts operating, setting lvs0n and lvr0n is prohibited until tmc0n3 and tmc0n2 = 00 (disabling the timer operation). <4> the output level of the to0n pi n is inverted each time an interrupt signal (inttm00n) is generated. remark n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 217 7.6 cautions for 16-bit timer/event counters 00 to 03 (1) restrictions for each channel of 16-bit timer/event counter 0n table 7-5 shows the restrictions for each channel. table 7-5. restrictions for each ch annel of 16-bit timer/event counter 0n operation restriction as interval timer as square-wave output as external event counter ? as clear & start mode entered by ti00n pin valid edge input using timer output (to0n) is prohibited when det ection of the valid edge of the ti01n pin is used. (toc0n = 00h) as free-running timer ? as ppg output 0000h cp01n < cr00n ffffh as one-shot pulse output setting the same value to cr00n and cp01n is prohibited. as pulse width measurement using timer output (to0n) is prohibited (toc0n = 00h) (2) timer start errors an error of up to one clock may occur in the time requir ed for a match signal to be generated after timer start. this is because counting tm0n is start ed asynchronously to the count pulse. figure 7-55. start timing of tm0n count 0000h timer start 0001h 0002h 0003h 0004h count pulse tm0n count value (3) setting of cr00n and cr01n (c lear & start mode entered upon a match between tm0n and cr00n) set a value other than 0000h to cr00n and cr01n (tm0n c annot count one pulse when it is used as an external event counter). remark n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 218 (4) timing of holding data by capture register (a) when the valid edge is input to t he ti00n/ti01n pin and the reverse phase of the ti00n pin is detected while cr00n/cr01n is read, cr01n performs a capture operation but the read value of cr00n/cr01n is not guaranteed. at this time, an interrupt signal (inttm 00n/inttm01n) is generated wh en the valid edge of the ti00n/ti01n pin is detected (t he interrupt signal is not generated when the reverse-phase edge of the ti00n pin is detected). when the count value is captured because the valid edge of the ti00n/ti01n pi n was detected, read the value of cr00n/cr01n after inttm00n/inttm01n is generated. figure 7-56. timing of holding data by capture register n n + 1 n + 2 x n + 1 m m + 1 m + 2 count pulse tm0n count value edge input inttm01n value captured to cr01n capture read signal capture operation is performed but read value is not guaranteed. capture operation (b) the values of cr00n and cr01n are not guarant eed after 16-bit timer/event counter 0n stops. (5) setting valid edge set the valid edge of the ti00n pin while the timer operation is stopped (tmc0n3 and tmc0n2 = 00). set the valid edge by using es0n0 and es0n1. (6) re-triggering one-shot pulse make sure that the trigger is not generated while an active level is being output in t he one-shot pulse output mode. be sure to input the next trigger afte r the current active level is output. remark n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 219 (7) operation of ovf0n flag (a) setting ovf0n flag (1) the ovf0n flag is set to 1 in the following case, as well as when tm0n overflows. select the clear & start mode entered upon a match between tm0n and cr00n. set cr00n to ffffh. when tm0n matches cr00n and tm0n is cleared from ffffh to 0000h figure 7-57. operation timing of ovf0n flag fffeh ffffh ffffh 0000h 0001h count pulse tm0n inttm00n ovf0n cr00n (b) clearing ovf0n flag even if the ovf0n flag is cleared to 0 after tm0n overflows and before the next count clock is counted (before the value of tm0n becomes 0001h), it is set to 1 again and clearing is invalid. (8) one-shot pulse output one-shot pulse output operates correct ly in the free-running timer mode or the clear & start mode entered by the ti00n pin valid edge. the one-shot pulse cannot be output in the clea r & start mode entered upon a match between tm0n and cr00n. remark n = 0 to 3 chapter 7 16-bit timer/event counters 00 to 03 user?s manual u17553ej4v0ud 220 (9) capture operation (a) when valid edge of ti00n is specified as count clock when the valid edge of ti00n is specified as the count cl ock, the capture register for which ti00n is specified as a trigger does not operate correctly. (b) pulse width to accurately capture value by signals input to ti01n and ti00n pins to accurately capture the count value, the pulse input to the ti00n and ti01n pins as a capture trigger must be wider than two count clocks selected by prm0n (see figure 7-13 ). (c) generation of interrupt signal the capture operation is per formed at the falling edge of the count clock but the in terrupt signals (inttm00n and inttm01n) are generated at the risi ng edge of the next count clock (see figure 7-13 ). (d) note when crc0n1 (bit 1 of capture/compare control register 0n (crc0n)) is set to 1 when the count value of the tm0n regist er is captured to the cr00n regi ster in the phase reverse to the signal input to the ti00n pin, the interrupt signal (i nttm00n) is not generated after the count value is captured. if the valid edge is det ected on the ti01n pin during this oper ation, the captur e operation is not performed but the inttm00n signal is generated as an ex ternal interrupt signal. mask the inttm00n signal when the external interrupt is not used. (10) edge detection (a) specifying valid edge after reset if the operation of the 16-bit timer/ev ent counter 0n is enabled after reset and while the ti00n or ti01n pin is at high level and when the rising edge or both the edges are specified as the valid edge of the ti00n or ti01n pin, then the high level of the ti00n or ti01n pin is detected as the rising edge. note this when the ti00n or ti01n pin is pulled up. however, t he rising edge is not detected when the operation is once stopped and then enabled again. (b) sampling clock for eliminating noise the sampling clock for eliminating noise differs depend ing on whether the valid edge of ti00n is used as the count clock or capture trigger. in the fo rmer case, the sampling clock is fixed to f prs . in the latter, the count clock selected by prm0n is used for sampling. when the signal input to the ti00n pin is sampled and the valid level is detected two times in a row, the valid edge is detected. therefore, noise having a short pulse width can be eliminated (see figure 7-13 ). (11) timer operation the signal input to the ti00n/ti01n pin is not acknow ledged while the timer is stopped, regardless of the operation mode of the cpu. remarks 1. f prs : peripheral hardware clock frequency 2. n = 0 to 3 user?s manual u17553ej4v0ud 221 chapter 8 8-bit timer/even t counters 50 and 51 8.1 functions of 8-bit ti mer/event counters 50 and 51 8-bit timer/event counters 50 and 51 have the following functions. ? interval timer ? external event counter ? square-wave output ? pwm output figures 8-1 and 8-2 show the block diagrams of 8-bit timer/event counters 50 and 51. figure 8-1. block diagram of 8-bit timer/event counter 50 internal bus 8-bit timer compare register 50 (cr50) ti50/to50/ p17 f prs /2 2 f prs /2 6 f prs /2 8 f prs /2 13 f prs f prs /2 match mask circuit ovf clear 3 selector tcl502 tcl501 tcl500 timer clock selection register 50 (tcl50) internal bus tce50 tmc506 lvs50 lvr50 tmc501 toe50 invert level 8-bit timer mode control register 50 (tmc50) s r s q r inv selector to tmh0 to uart0 to uart6 inttm50 to50/ti50/ p17 note 1 note 2 selector 8-bit timer counter 50 (tm50) selector output latch (p17) pm17 notes 1. timer output f/f 2. pwm output f/f chapter 8 8-bit timer/event counters 50 and 51 user?s manual u17553ej4v0ud 222 figure 8-2. block diagram of 8-bit timer/event counter 51 internal bus 8-bit timer compare register 51 (cr51) ti51/to51/p33/intp4 f prs /2 8 f prs /2 12 f prs f prs /2 match mask circuit ovf clear 3 selector tcl512 tcl511 tcl510 timer clock selection register 51 (tcl51) internal bus tce51 tmc516 lvs51 lvr51 tmc511 toe51 invert level 8-bit timer mode control register 51 (tmc51) s r s q r inv selector inttm51 to51/ti51/ p33/intp4 note 1 note 2 selector 8-bit timer counter 51 (tm51) selector output latch (p33) pm33 f prs /2 6 f prs /2 4 notes 1. timer output f/f 2. pwm output f/f chapter 8 8-bit timer/event counters 50 and 51 user?s manual u17553ej4v0ud 223 8.2 configuration of 8-bit timer/event counters 50 and 51 8-bit timer/event counters 50 and 51 include the following hardware. table 8-1. configuration of 8-bit timer/event counters 50 and 51 item configuration timer register 8-bit timer counter 5n (tm5n) register 8-bit timer compare register 5n (cr5n) timer input ti5n timer output to5n control registers timer clock selection register 5n (tcl5n) 8-bit timer mode control register 5n (tmc5n) port mode register 1 (pm1) or port mode register 3 (pm3) port register 1 (p1) or port register 3 (p3) (1) 8-bit timer counter 5n (tm5n) tm5n is an 8-bit register that count s the count pulses and is read-only. the counter is incremented in synchronization with the rising edge of the count clock. figure 8-3. format of 8-bit timer counter 5n (tm5n) symbol tm5n (n = 0, 1) address: ff16h (tm50), ff1fh (tm51) after reset: 00h r in the following situations, the count value is cleared to 00h. <1> reset signal generation <2> when tce5n is cleared <3> when tm5n and cr5n match in the mode in which cl ear & start occurs upon a match of the tm5n and cr5n. remark n = 0, 1 chapter 8 8-bit timer/event counters 50 and 51 user?s manual u17553ej4v0ud 224 (2) 8-bit timer compare register 5n (cr5n) cr5n can be read and written by an 8-bi t memory manipulation instruction. except in pwm mode, the value set in cr5n is constantly compared with the 8-bit timer counter 5n (tm5n) count value, and an interrupt request (in ttm5n) is generated if they match. in pwm mode, when the to5n pin becomes active due to a tm5n overflow and the values of tm5n and cr5n match, the to5n pin becomes inactive. the value of cr5n can be set within 00h to ffh. reset signal generation clears cr5n to 00h. figure 8-4. format of 8-bit time r compare register 5n (cr5n) symbol cr5n (n = 0, 1) address: ff17h (cr50), ff41h (cr51) after reset: 00h r/w cautions 1. in the mode in whic h clear & start occurs on a match of tm5n and cr5n (tmc5n6 = 0), do not write other values to cr5n during operation. 2. in pwm mode, make the cr5n rewrite pe riod 3 count clocks of the count clock (clock selected by tcl5n) or more. remark n = 0, 1 chapter 8 8-bit timer/event counters 50 and 51 user?s manual u17553ej4v0ud 225 8.3 registers controlling 8-bit timer/event counters 50 and 51 the following four registers are used to co ntrol 8-bit timer/event counters 50 and 51. ? timer clock selection register 5n (tcl5n) ? 8-bit timer mode control register 5n (tmc5n) ? port mode register 1 (pm1) or port mode register 3 (pm3) ? port register 1 (p1) or port register 3 (p3) (1) timer clock selecti on register 5n (tcl5n) this register sets the count clock of 8-bit timer/ev ent counter 5n and the valid edge of the ti5n pin input. tcl5n can be set by an 8-bit memory manipulation instruction. reset signal generation clears tcl5n to 00h. remark n = 0, 1 figure 8-5. format of timer clo ck selection register 50 (tcl50) address: ff6ah after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 tcl50 0 0 0 0 0 tcl502 tcl501 tcl500 count clock selection tcl502 tcl501 tcl500 f prs = 4 mhz f prs = 8 mhz f prs = 10 mhz f prs = 20 mhz 0 0 0 ti50 pin falling edge note 1 0 0 1 ti50 pin rising edge note 2 0 1 0 f prs 4 mhz 8 mhz 10 mhz 20 mhz 0 1 1 f prs /2 2 mhz 4 mhz 5 mhz 10 mhz 1 0 0 f prs /2 2 1 mhz 2 mhz 2.5 mhz 5 mhz 1 0 1 f prs /2 6 62.5 khz 125 khz 156.25 khz 312.5 khz 1 1 0 f prs /2 8 15.62 khz 31.25 khz 39.06 khz 78.13 khz 1 1 1 f prs /2 13 0.48 khz 0.97 khz 1.22 khz 2.44 khz notes 1. in the on-board mode, the flmd0 pin falling edge is selected. 2. in the on-board mode, the flmd0 pin rising edge is selected. cautions 1. when rewriting tcl50 to othe r data, stop the timer operation beforehand. 2. be sure to set bits 3 to 7 to 0. remark f prs : peripheral hardware clock frequency chapter 8 8-bit timer/event counters 50 and 51 user?s manual u17553ej4v0ud 226 figure 8-6. format of timer clo ck selection register 51 (tcl51) address: ff8ch after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 tcl51 0 0 0 0 0 tcl512 tcl511 tcl510 count clock selection tcl512 tcl511 tcl510 f prs = 4 mhz f prs = 8 mhz f prs = 10 mhz f prs = 20 mhz 0 0 0 ti51 pin falling edge 0 0 1 ti51 pin rising edge 0 1 0 f prs 4 mhz 8 mhz 10 mhz 20 mhz 0 1 1 f prs /2 2 mhz 4 mhz 5 mhz 10 mhz 1 0 0 f prs /2 4 500 khz 1 mhz 625 khz 1.25 mhz 1 0 1 f prs /2 6 62.5 khz 125 khz 156.25 khz 312.5 khz 1 1 0 f prs /2 8 15.62 khz 31.25 khz 39.06 khz 78.13 khz 1 1 1 f prs /2 12 0.97 khz 1.95 khz 2.44 khz 4.88 khz cautions 1. when rewriting tcl51 to othe r data, stop the timer operation beforehand. 2. be sure to set bits 3 to 7 to 0. remark f prs : peripheral hardware clock frequency chapter 8 8-bit timer/event counters 50 and 51 user?s manual u17553ej4v0ud 227 (2) 8-bit timer mode control register 5n (tmc5n) tmc5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (tm5n) count operation control <2> 8-bit timer counter 5n (tm5n) operating mode selection <3> timer output f/f (flip flop) status setting <4> active level selection in timer f/f control or pwm (free-running) mode. <5> timer output control tmc5n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. remark n = 0, 1 figure 8-7. format of 8-bit timer mode control register 50 (tmc50) address: ff6bh after reset: 00h r/w note symbol <7> 6 5 4 <3> <2> 1 <0> tmc50 tce50 tmc506 0 0 lvs50 lvr50 tmc501 toe50 tce50 tm50 count operation control 0 after clearing to 0, count operation disabled (counter stopped) 1 count operation start tmc506 tm50 operating mode selection 0 mode in which clear & start occurs on a match between tm50 and cr50 1 pwm (free-running) mode lvs50 lvr50 timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited in other modes (tmc506 = 0) in pwm mode (tmc506 = 1) tmc501 timer f/f control active level selection 0 inversion operation disabled active-high 1 inversion operation enabled active-low toe50 timer output control 0 output disabled (tm50 output is low level) 1 output enabled note bits 2 and 3 are write-only. (refer to cautions and remarks on the next page.) chapter 8 8-bit timer/event counters 50 and 51 user?s manual u17553ej4v0ud 228 figure 8-8. format of 8-bit timer mode control register 51 (tmc51) address: ff43h after reset: 00h r/w note symbol <7> 6 5 4 <3> <2> 1 <0> tmc51 tce51 tmc516 0 0 lvs51 lvr51 tmc511 toe51 tce51 tm51 count operation control 0 after clearing to 0, count operation disabled (counter stopped) 1 count operation start tmc516 tm51 operating mode selection 0 mode in which clear & start occurs on a match between tm51 and cr51 1 pwm (free-running) mode lvs51 lvr51 timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited in other modes (tmc516 = 0) in pwm mode (tmc516 = 1) tmc511 timer f/f control active level selection 0 inversion operation disabled active-high 1 inversion operation enabled active-low toe51 timer output control 0 output disabled (tm51 output is low level) 1 output enabled note bits 2 and 3 are write-only. cautions 1. the settings of lvs5n and lv r5n are valid in other than pwm mode. 2. perform <1> to <4> below in the following order, not at the same time. <1> set tmc5n1, tmc5n6 : operation mode setting <2> set toe5n to enable output: timer output enable <3> set lvs5n, lvr5n (see caution 1): timer f/f setting <4> set tce5n 3. stop operation befo re rewriting tmc5n6. remarks 1. in pwm mode, pwm output is made inactive by clearing tce5n to 0. 2. if lvs5n and lvr5n are read, the value is 0. 3. the values of the tmc5n6, lvs5n, lvr5n, tmc 5n1, and toe5n bits are re flected at the to5n pin regardless of the value of tce5n. 4. n = 0, 1 chapter 8 8-bit timer/event counters 50 and 51 user?s manual u17553ej4v0ud 229 (3) port mode registers 1 and 3 (pm1, pm3) these registers set port 1 and 3 input/output in 1-bit units. when using the p17/to50/ti50 and p 33/to51/ti51/intp4 pins for timer output, clear pm17 and pm33 and the output latches of p17 and p33 to 0. when using the p17/to50/ti50 and p33/ to51/ti51/intp4 pins for timer input, set pm17 and pm33 to 1. the output latches of p17 and p33 at this time may be 0 or 1. pm1 and pm3 can be set by a 1-bit or 8- bit memory manipulation instruction. reset signal generation sets these registers to ffh. figure 8-9. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) figure 8-10. format of port mode register 3 (pm3) address: ff23h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm3 1 1 1 1 pm33 pm32 pm31 pm30 pm3n p3n pin i/o mode selection (n = 0 to 3) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 8 8-bit timer/event counters 50 and 51 user?s manual u17553ej4v0ud 230 8.4 operations of 8-bit timer/event counters 50 and 51 8.4.1 operation as interval timer 8-bit timer/event counter 5n operates as an interval timer that generates interrupt req uests repeatedly at intervals of the count value preset to 8-bi t timer compare register 5n (cr5n). when the count value of 8-bit timer counter 5n (tm5n) ma tches the value set to cr5n, counting continues with the tm5n value cleared to 0 and an interrupt request signal (inttm5n) is generated. the count clock of tm5n can be selected with bits 0 to 2 (tcl5n0 to tcl5n2) of timer clock selection register 5n (tcl5n). setting <1> set the registers. ? tcl5n: select the count clock. ? cr5n: compare value ? tmc5n: stop the count operation, se lect the mode in which clear & start occurs on a match of tm5n and cr5n. (tmc5n = 0000 0b = don?t care) <2> after tce5n = 1 is set, the count operation starts. <3> if the values of tm5n and cr5n match, intt m5n is generated (tm5n is cleared to 00h). <4> inttm5n is generated repeatedly at the same interval. set tce5n to 0 to stop the count operation. caution do not write other values to cr5n during operation. figure 8-11. interval ti mer operation timing (1/2) (a) basic operation t count clock tm5n count value cr5n tce5n inttm5n count start clear clear 00h 01h n 00h 01h n 00h 01h n n n n n interrupt acknowledged interrupt acknowledged interval time interval time remark interval time = (n + 1) t n = 00h to ffh n = 0, 1 chapter 8 8-bit timer/event counters 50 and 51 user?s manual u17553ej4v0ud 231 figure 8-11. interval ti mer operation timing (2/2) (b) when cr5n = 00h t interval time count clock tm5n cr5n tce5n inttm5n 00h 00h 00h 00h 00h (c) when cr5n = ffh t count clock tm5n cr5n tce5n inttm5n 01 fe ff 00 fe ff 00 ff ff ff interval time interrupt acknowledged interrupt acknowledged remark n = 0, 1 chapter 8 8-bit timer/event counters 50 and 51 user?s manual u17553ej4v0ud 232 8.4.2 operation as external event counter the external event counter c ounts the number of external clock pulses to be input to the ti5n pin by 8-bit timer counter 5n (tm5n). tm5n is incremented each time the vali d edge specified by timer clock selection register 5n (tcl5n) is input. either the rising or falling edge can be selected. when the tm5n count value matches the value of 8-bit ti mer compare register 5n (cr5n), tm5n is cleared to 0 and an interrupt request signal (inttm5n) is generated. whenever the tm5n value matches the va lue of cr5n, inttm5n is generated. setting <1> set each register. ? set the port mode register (pm17 or pm33) note to 1. ? tcl5n: select ti5n pin input edge. ti5n pin falling edge tcl5n = 00h ti5n pin rising edge tcl5n = 01h ? cr5n: compare value ? tmc5n: stop the count operation, se lect the mode in which clear & start occurs on match of tm5n and cr5n, disable the timer f/f inversion operation, disable timer output. (tmc5n = 0000 00b = don?t care) <2> when tce5n = 1 is set, the number of pu lses input from the ti5n pin is counted. <3> when the values of tm5n and cr5n match, inttm5n is generated (tm5n is cleared to 00h). <4> after these settings, inttm5n is generated each time the values of tm5n and cr5n match. note 8-bit timer/event counter 50: pm17 8-bit timer/event counter 51: pm33 figure 8-12. external event counter oper ation timing (with rising edge specified) ti5n tm5n count value cr5n inttm5n 00 01 02 03 04 05 n ? 1 n 00 01 02 03 n count start remark n = 00h to ffh n = 0, 1 chapter 8 8-bit timer/event counters 50 and 51 user?s manual u17553ej4v0ud 233 8.4.3 square-wave output operation a square wave with any selected frequency is output at inte rvals determined by the value preset to 8-bit timer compare register 5n (cr5n). the to5n pin output status is inverted at intervals determined by the count value preset to cr5n by setting bit 0 (toe5n) of 8-bit timer mode control r egister 5n (tmc5n) to 1. this enabl es a square wave with any selected frequency to be output (duty = 50%). setting <1> set each register. ? clear the port output latch (p17 or p33) note and port mode register (pm17 or pm33) note to 0. ? tcl5n: select the count clock. ? cr5n: compare value ? tmc5n: stop the count operat ion, select the mode in which clear & start occurs on a match of tm5n and cr5n. lvs5n lvr5n timer output f/f status setting 1 0 high-level output 0 1 low-level output timer output f/f inversion enabled timer output enabled (tmc5n = 00001011b or 00000111b) <2> after tce5n = 1 is set, the count operation starts. <3> the timer output f/f is inverted by a match of tm5n and cr5n. after inttm5n is generated, tm5n is cleared to 00h. <4> after these settings, the timer output f/f is inverted at the same interval and a square wave is output from to5n. the frequency is as follows. frequency = 1/2t (n + 1) (n: 00h to ffh) note 8-bit timer/event counter 50: p17, pm17 8-bit timer/event counter 51: p33, pm33 caution do not write other values to cr5n during operation. remark n = 0, 1 chapter 8 8-bit timer/event counters 50 and 51 user?s manual u17553ej4v0ud 234 figure 8-13. square-wave output operation timing count clock tm5n count value 00h 01h 02h n ? 1n n 00h n ? 1 n 00h 01h 02h cr5n to5n note t count start note the initial value of to5n output can be set by bits 2 and 3 (lvr5n, lvs5n) of 8-bit timer mode control register 5n (tmc5n). 8.4.4 pwm output operation 8-bit timer/event counter 5n operates as a pwm output when bit 6 (tmc5n6) of 8-bit timer mode control register 5n (tmc5n) is set to 1. the duty pulse determined by the value set to 8-bit time r compare register 5n (cr5n) is output from to5n. set the active level width of the pwm pulse to cr5n; the active level can be selected with bit 1 (tmc5n1) of tmc5n. the count clock can be selected with bits 0 to 2 (tcl5n0 to tcl5n2) of timer clock selection register 5n (tcl5n). pwm output can be enabled/disabled with bit 0 (toe5n) of tmc5n. caution in pwm mode, make the cr5n rewrite period 3 count clocks of the count clock (clock selected by tcl5n) or more. remark n = 0, 1 chapter 8 8-bit timer/event counters 50 and 51 user?s manual u17553ej4v0ud 235 (1) pwm output basic operation setting <1> set each register. ? clear the port output latch (p17 or p33) note and port mode register (pm17 or pm33) note to 0. ? tcl5n: select the count clock. ? cr5n: compare value ? tmc5n: stop the count operation, select pwm mode. the timer output f/f is not changed. tmc5n1 active level selection 0 active-high 1 active-low timer output enabled (tmc5n = 01000001b or 01000011b) <2> the count operation starts when tce5n = 1. clear tce5n to 0 to stop the count operation. note 8-bit timer/event counter 50: p17, pm17 8-bit timer/event counter 51: p33, pm33 pwm output operation <1> pwm output (output from to5n) outputs an inactive level until an overflow occurs. <2> when an overflow occurs, the active level is outpu t. the active level is output until cr5n matches the count value of 8-bit timer counter 5n (tm5n). <3> after the cr5n matches the count value, the inacti ve level is output until an overflow occurs again. <4> operations <2> and <3> are repe ated until the count operation stops. <5> when the count operation is stopped with tce5n = 0, pwm output becomes inactive. for details of timing, see figures 8-14 and 8-15 . the cycle, active-level width, and duty are as follows. ? cycle = 2 8 t ? active-level width = nt ? duty = n/2 8 (n = 00h to ffh) remark n = 0, 1 chapter 8 8-bit timer/event counters 50 and 51 user?s manual u17553ej4v0ud 236 figure 8-14. pwm output operation timing (a) basic operation (active level = h) count clock tm5n cr5n tce5n inttm5n to5n 00h 01h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h n <2> active level <1> <3> inactive level active level <5> t (b) cr5n = 00h count clock tm5n cr5n tce5n inttm5n to5n inactive level inactive level 01h 00h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h 00h n + 2 l t (c) cr5n = ffh tm5n cr5n tce5n inttm5n to5n 01h 00h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h ffh n + 2 inactive level active level inactive level active level inactive level t remarks 1. <1> to <3> and <5> in figure 8-14 (a) correspond to <1> to <3> and <5> in pwm output operation in 8. 4. 4 (1) pwm output basic operation . 2. n = 0, 1 chapter 8 8-bit timer/event counters 50 and 51 user?s manual u17553ej4v0ud 237 (2) operation with cr5n changed figure 8-15. timing of operation with cr5n changed (a) cr5n value is changed from n to m before clock rising edge of ffh value is transferred to cr5n at overflow immediately after change. count clock tm5n cr5n tce5n inttm5n to5n <1> cr5n change (n m) n n + 1 n + 2 ffh 00h 01h m m + 1 m + 2 ffh 00h 01h 02h m m + 1 m + 2 n 02h m h <2> t (b) cr5n value is changed from n to m after clock rising edge of ffh value is transferred to cr5n at second overflow. count clock tm5n cr5n tce5n inttm5n to5n n n + 1 n + 2 ffh 00h 01h n n + 1 n + 2 ffh 00h 01h 02h n 02h n h m m m + 1 m + 2 <1> cr5n change (n m) <2> t caution when reading from cr5n betw een <1> and <2> in figure 8-15, the value read differs from the actual value (read value: m, actual value of cr5n: n). chapter 8 8-bit timer/event counters 50 and 51 user?s manual u17553ej4v0ud 238 8.5 cautions for 8-bit ti mer/event counters 50 and 51 (1) timer start error an error of up to one clock may occur in the time requir ed for a match signal to be generated after timer start. this is because 8-bit timer counters 50 and 51 (tm50, tm 51) are started asynchronous ly to the count clock. figure 8-16. 8-bit timer counter 5n start timing count clock tm5n count value 00h 01h 02h 03h 04h timer start remark n = 0, 1 user?s manual u17553ej4v0ud 239 chapter 9 8-bit timers h0 and h1 9.1 functions of 8-bit timers h0 and h1 8-bit timers h0 and h1 have the following functions. ? interval timer ? pwm output mode ? square-wave output ? carrier generator mode (8-bit timer h1 only) 9.2 configuration of 8-bit timers h0 and h1 8-bit timers h0 and h1 include the following hardware. table 9-1. configuration of 8-bit timers h0 and h1 item configuration timer register 8-bit timer counter hn registers 8-bit timer h compare register 0n (cmp0n) 8-bit timer h compare register 1n (cmp1n) timer output tohn control registers 8-bit timer h mode register n (tmhmdn) 8-bit timer h carrier control register 1 (tmcyc1) note port mode register 1 (pm1) port register 1 (p1) note 8-bit timer h1 only remark n = 0, 1 figures 9-1 and 9-2 show the block diagrams. chapter 9 8-bit timers h0 and h1 user?s manual u17553ej4v0ud 240 figure 9-1. block diag ram of 8-bit timer h0 tmhe0 cks02 cks01 cks00 tmmd01 tmmd00 tolev0 toen0 toh0/p15 inttmh0 f prs f prs /2 f prs /2 2 f prs /2 6 f prs /2 10 1 0 f/f r 3 2 pm15 match internal bus 8-bit timer h mode register 0 (tmhmd0) 8-bit timer h compare register 10 (cmp10) decoder selector interrupt generator output controller level inversion pwm mode signal timer h enable signal clear 8-bit timer h compare register 00 (cmp00) output latch (p15) 8-bit timer/ event counter 50 output selector 8-bit timer counter h0 chapter 9 8-bit timers h0 and h1 user?s manual u17553ej4v0ud 241 figure 9-2. block diag ram of 8-bit timer h1 match internal bus tmhe1 cks12 cks11 cks10 tmmd11 tmmd10 tolev1 toen1 8-bit timer h compare register 1 1 (cmp11) decoder toh1/ intp5/ p16 8-bit timer h carrier control register 1 (tmcyc1) inttmh1 inttm51 selector f prs f prs /2 2 f prs /2 4 f prs /2 6 f prs /2 12 f rl f rl /2 7 f rl /2 9 interrupt generator output controller level inversion pm16 output latch (p16) 1 0 f/f r pwm mode signal carrier generator mode signal timer h enable signal 3 2 8-bit timer h compare register 0 1 (cmp01) 8-bit timer counter h1 clear rmc1 nrzb1 nrz1 reload/ interrupt control 8-bit timer h mode register 1 (tmhmd1) selector chapter 9 8-bit timers h0 and h1 user?s manual u17553ej4v0ud 242 (1) 8-bit timer h compar e register 0n (cmp0n) this register can be read or written by an 8-bit memory mani pulation instruction. this r egister is used in all of the timer operation modes. this register constantly compares t he value set to cmp0n with the count val ue of the 8-bit timer counter hn and, when the two values match, generates an interrupt request signal (inttm hn) and inverts the output level of tohn. rewrite the value of cmp0n while the timer is stopped (tmhen = 0). a reset signal generation clears this register to 00h. figure 9-3. format of 8-bit time r h compare register 0n (cmp0n) symbol cmp0n (n = 0, 1) address: ff02h (cmp00), ff1ah (cmp01) after reset: 00h r/w 7 6 5 4 32 1 0 caution cmp0n cannot be rewritte n during timer count operation. cmp0n can be refreshed (the same value is written) during timer count operation. (2) 8-bit timer h compar e register 1n (cmp1n) this register can be read or written by an 8-bit memory manipulation instruction. this register is used in the pwm output mode and carrier generator mode. in the pwm output mode, this register constantly compares the value set to cmp1n with the count value of the 8- bit timer counter hn and, when the two values match, in verts the output level of tohn. no interrupt request signal is generated. in the carrier generator mode, the cm p1n register always compares the val ue set to cmp1n with the count value of the 8-bit timer counter hn and, wh en the two values match, generates an in terrupt request signal (inttmhn). at the same time, the count value is cleared. cmp1n can be refreshed (the same value is writt en) and rewritten during timer count operation. if the value of cmp1n is rewritten while the timer is oper ating, the new value is la tched and transferred to cmp1n when the count value of the timer matches the old val ue of cmp1n, and then the valu e of cmp1n is changed to the new value. if matching of the count value and the cmp1n value and wr iting a value to cmp1n conflict, the value of cmp1n is not changed. a reset signal generation clears this register to 00h. figure 9-4. format of 8-bit time r h compare register 1n (cmp1n) symbol cmp1n (n = 0, 1) address: ff0eh (cmp10), ff1bh (cmp11) after reset: 00h r/w 7 6 5 4 32 1 0 caution in the pwm output mode and carrier genera tor mode, be sure to set cmp1n when starting the timer count operation (tmhen = 1) after the timer count operation was stopped (tmhen = 0) (be sure to set again even if setting the same value to cmp1n). remark n = 0, 1 chapter 9 8-bit timers h0 and h1 user?s manual u17553ej4v0ud 243 9.3 registers controlling 8-bit timers h0 and h1 the following four registers are used to control 8-bit timers h0 and h1. ? 8-bit timer h mode register n (tmhmdn) ? 8-bit timer h carrier control register 1 (tmcyc1) note ? port mode register 1 (pm1) ? port register 1 (p1) note 8-bit timer h1 only (1) 8-bit timer h mode register n (tmhmdn) this register controls the mode of timer h. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. remark n = 0, 1 chapter 9 8-bit timers h0 and h1 user?s manual u17553ej4v0ud 244 figure 9-5. format of 8-bit time r h mode register 0 (tmhmd0) address: ff69h after reset: 00h r/w symbol <7> 6 5 4 3 2 <1> <0> tmhmd0 tmhe0 cks02 cks01 cks00 tmmd01 tmmd00 tolev0 toen0 tmhe0 timer operation enable 0 stops timer count operation (counter is cleared to 0) 1 enables timer count operation (count oper ation started by inputting clock) count clock selection cks02 cks01 cks00 f prs = 4 mhz f prs = 8 mhz f prs = 10 mhz f prs = 20 mhz 0 0 0 f prs 4 mhz 8 mhz 10 mhz 20 mhz 0 0 1 f prs /2 2 mhz 4 mhz 5 mhz 10 mhz 0 1 0 f prs /2 2 1 mhz 2 mhz 2.5 mhz 5 mhz 0 1 1 f prs /2 6 62.5 khz 125 khz 156.25 khz 312.5 khz 1 0 0 f prs /2 10 3.90 khz 7.81 khz 9.77 khz 19.54 khz 1 0 1 tm50 output note other than above setting prohibited tmmd01 tmmd00 timer operation mode 0 0 interval timer mode 1 0 pwm output mode other than above setting prohibited tolev0 timer output level control (in default mode) 0 low level 1 high level toen0 timer output control 0 disables output 1 enables output note when tm50 output as the count clock. ? set to pwm mode (tmc506 = 1) after the following order to bellow. <1>set the count clock to make the duty = 50%. <2>start the operation of 8- bit timer/event counter 50. ? set to mode in which the count clock is cleared and started upon a match of tm50 and cr50 (tmc506 = 0) after the following order to bellow. <1>enable the timer f/f inversion operation (tmc501 = 1). <2>start the operation of 8- bit timer/event counter 50. it is not necessary to enable the to50 pin as a timer output pin in any mode. chapter 9 8-bit timers h0 and h1 user?s manual u17553ej4v0ud 245 cautions 1. when tmhe0 = 1, setting the other bits of tmhmd0 is prohibited. however, tmhmd0 can be refreshed (the same value is written). 2. in the pwm output mode, be sure to set 8-bit timer h co mpare register 10 (cmp10) when starting the timer count operation (tmhe0 = 1) after the timer count operation was stopped (tmhe0 = 0) (be sure to set again even if setting the same value to cmp10). remarks 1. f prs : peripheral hardware clock frequency 2. tmc506: bit 6 of 8-bit timer mode control register 50 (tmc50) tmc501: bit 1 of tmc50 figure 9-6. format of 8-bit time r h mode register 1 (tmhmd1) address: fffah after reset: 00h r/w symbol <7> 6 5 4 3 2 <1> <0> tmhmd1 tmhe1 cks12 cks11 cks10 tmmd11 tmmd10 tolev1 toen1 tmhe1 timer operation enable 0 stops timer count operation (counter is cleared to 0) 1 enables timer count operation (count oper ation started by inputting clock) count clock selection cks12 cks11 cks10 f prs = 4 mhz f prs = 8 mhz f prs = 10 mhz f prs = 20 mhz 0 0 0 f prs 4 mhz 8 mhz 10 mhz 20 mhz 0 0 1 f prs /2 2 1 mhz 2 mhz 2.5 mhz 5 mhz 0 1 0 f prs /2 4 500 khz 1 mhz 625 khz 1.25 mhz 0 1 1 f prs /2 6 62.5 khz 125 khz 156.25 khz 312.5 khz 1 0 0 f prs /2 12 0.97 khz 1.95 khz 2.44 khz 4.88 khz 1 0 1 f rl /2 7 1.88 khz (typ.) 1 1 0 f rl /2 9 0.47 khz (typ.) 1 1 1 f rl 240 khz (typ.) tmmd11 tmmd10 timer operation mode 0 0 interval timer mode 0 1 carrier generator mode 1 0 pwm output mode 1 1 setting prohibited tolev1 timer output level control (in default mode) 0 low level 1 high level toen1 timer output control 0 disables output 1 enables output chapter 9 8-bit timers h0 and h1 user?s manual u17553ej4v0ud 246 cautions 1. when tmhe1 = 1, setting the other bits of tmhmd1 is prohibited. however, tmhmd1 can be refreshed (the same value is written). 2. in the pwm output mode and carrier genera tor mode, be sure to set 8-bit timer h compare register 11 (cmp11) when star ting the timer count operation (tmhe1 = 1) after the timer count operation was stopped (tmhe1 = 0) (be sure to set again ev en if setting the same value to cmp11). 3. when the carrier generator mode is used, set so that the count clock frequency of tmh1 becomes more than 6 times the count clock frequency of tm51. remarks 1. f prs : peripheral hardware clock frequency 2. f rl : internal low-speed oscillation clock frequency (2) 8-bit timer h carrier control register 1 (tmcyc1) this register controls the remote control output and carrier pulse output status of 8-bit timer h1. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 9-7. format of 8-bit timer h carrier control register 1 (tmcyc1) 0 tmcyc1 0 0 0 0 rmc1 nrzb1 nrz1 address: ffeeh after reset: 00h r/w note low-level output high-level output at rising edge of inttm51 signal input low-level output carrier pulse output at rising edge of inttm51 signal input rmc1 0 0 1 1 nrzb1 0 1 0 1 remote control output carrier output disabled status (low-level status) carrier output enabled status (rmc1 = 1: carrier pulse output, rmc1 = 0: high-level status) nrz1 0 1 carrier pulse output status flag <0> note bit 0 is read-only. chapter 9 8-bit timers h0 and h1 user?s manual u17553ej4v0ud 247 (3) port mode register 1 (pm1) this register sets port 1 input/output in 1-bit units. when using the p15/toh0 and p16/toh1/intp5 pins for timer output, clear pm15 and pm16 and the output latches of p15 and p16 to 0. pm1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. figure 9-8. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 9 8-bit timers h0 and h1 user?s manual u17553ej4v0ud 248 9.4 operation of 8-bit timers h0 and h1 9.4.1 operation as inter val timer/square-wave output when 8-bit timer counter hn and compare register 0n (cmp0n) match, an interrupt request signal (inttmhn) is generated and 8-bit timer counter hn is cleared to 00h. compare register 1n (cmp1n) is not used in interval time r mode. since a match of 8-bit timer counter hn and the cmp1n register is not detected even if the cmp1n register is set, timer output is not affected. by setting bit 0 (toenn) of timer h mode register n (tmh mdn) to 1, a square wave of any frequency (duty = 50%) is output from tohn. (1) usage generates the inttmhn signal repeatedly at the same interval. <1> set each register. figure 9-9. register setting during inte rval timer/square-wave output operation (i) setting timer h mode register n (tmhmdn) 0 0/1 0/1 0/1 0 0 0/1 0/1 tmmdn0 tolevn toenn cksn1 cksn2 tmhen tmhmdn cksn0 tmmdn1 timer output setting timer output level inversion setting interval timer mode setting count clock (f cnt ) selection count operation stopped (ii) cmp0n register setting ? compare value (n) <2> count operation starts when tmhen = 1. <3> when the values of 8-bit timer counter hn and the cmp0n register match, the inttmhn signal is generated and 8-bit timer counter hn is cleared to 00h. interval time = (n +1)/f cnt <4> subsequently, the inttmhn signal is generated at t he same interval. to stop the count operation, clear tmhen to 0. remark n = 0, 1 chapter 9 8-bit timers h0 and h1 user?s manual u17553ej4v0ud 249 (2) timing chart the timing of the interval timer/square- wave output operation is shown below. figure 9-10. timing of interval time r/square-wave output operation (1/2) (a) basic operation 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn 01h n clear interval time clear n 00h 01h n 00h 01h 00h <2> level inversion, match interrupt occurrence, 8-bit timer counter hn clear <2> level inversion, match interrupt occurrence, 8-bit timer counter hn clear <3> <1> <1> the count operation is enabled by setting the tmhen bi t to 1. the count clock starts counting no more than 1 clock after the operation is enabled. <2> when the values of 8-bit timer count er hn and the cmp0n register match, the value of 8-bit timer counter hn is cleared, the tohn output level is in verted, and the inttmhn signal is output. <3> the inttmhn signal and tohn output become inactive by clearing the tmhen bit to 0 during timer hn operation. if these are inactive from the first, the level is retained. remark n = 0, 1 n = 01h to feh chapter 9 8-bit timers h0 and h1 user?s manual u17553ej4v0ud 250 figure 9-10. timing of interval time r/square-wave output operation (2/2) (b) operation when cmp0n = ffh 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn 01h feh clear clear ffh 00h feh ffh 00h ffh interval time (c) operation when cmp0n = 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn 00h 00h interval time remark n = 0, 1 chapter 9 8-bit timers h0 and h1 user?s manual u17553ej4v0ud 251 9.4.2 operation as pwm output mode in pwm output mode, a pulse with an arbi trary duty and arbitrary cycle can be output. 8-bit timer compare register 0n (cmp0n) controls the cycle of timer output (tohn). re writing the cmp0n register during timer operation is prohibited. 8-bit timer compare register 1n (cmp1n) controls the dut y of timer output (tohn). re writing the cmp1n register during timer operation is possible. the operation in pwm output mode is as follows. tohn output becomes active and 8-bit timer counter hn is cleared to 0 when 8-bit timer counter hn and the cmp0n register match after the timer count is started. tohn output becomes inactive when 8-bit timer counter hn and the cmp1n register match. (1) usage in pwm output mode, a pulse for which an arbitr ary duty and arbitrary cycle can be set is output. <1> set each register. figure 9-11. register setting in pwm output mode (i) setting timer h mode register n (tmhmdn) 0 0/1 0/1 0/1 1 0 0/1 1 tmmdn0 tolevn toenn cksn1 cksn2 tmhen tmhmdn cksn0 tmmdn1 timer output enabled timer output level inversion setting pwm output mode selection count clock (f cnt ) selection count operation stopped (ii) setting cmp0n register ? compare value (n): cycle setting (iii) setting cmp1n register ? compare value (m): duty setting remarks 1. n = 0, 1 2. 00h cmp1n (m) < cmp0n (n) ffh chapter 9 8-bit timers h0 and h1 user?s manual u17553ej4v0ud 252 <2> the count operation starts when tmhen = 1. <3> the cmp0n register is the compare register that is to be compared first after counter operation is enabled. when the values of 8-bit timer counter hn and the cmp0 n register match, 8-bit timer counter hn is cleared, an interrupt request signal (inttmhn) is generated, and tohn output becomes active. at the same time, the compare register to be compared with 8-bit timer c ounter hn is changed from t he cmp0n register to the cmp1n register. <4> when 8-bit timer counter hn and the cmp1n regist er match, tohn output becomes inactive and the compare register to be compared with 8-bit timer coun ter hn is changed from the cmp1n register to the cmp0n register. at this time, 8-bit timer counter hn is not cleared and the inttmhn signal is not generated. <5> by performing procedures <3> and <4> repeatedl y, a pulse with an arbitrary duty can be obtained. <6> to stop the count operation, set tmhen = 0. if the setting value of the cmp0n register is n, the setting value of the cmp1n register is m, and the count clock frequency is f cnt , the pwm pulse output cycle and duty are as follows. pwm pulse output cycle = (n + 1)/f cnt duty = active width : total widt h of pwm = (m + 1) : (n + 1) cautions 1. in pwm output mode , three operation clocks (signal sel ected using the cksn2 to cksn0 bits of the tmhmdn register) are required to transfer the cmp1n register value after rewriting the register. 2. be sure to set the cmp1n register when starting the timer count operation (tmhen = 1) after the timer count operation was stopped (tmhen = 0) (be sure to set again even if setting the same value to the cmp1n register). remark n = 0, 1 chapter 9 8-bit timers h0 and h1 user?s manual u17553ej4v0ud 253 (2) timing chart the operation timing in pwm output mode is shown below. caution make sure that the cmp1n register setting value (m) and cmp0 n register setting value (n) are within the following range. 00h cmp1n (m) < cmp0n (n) ffh figure 9-12. operation timing in pwm output mode (1/4) (a) basic operation count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) tohn (tolevn = 1) 00h 01h a5h 00h 01h 02h a5h 00h a5h 00h 01h 02h cmp1n a5h 01h <1> <2> <3> <4> <1> the count operation is enabled by setting the tmhen bit to 1. start 8-bit timer counter hn by masking one count clock to count up. at this time, tohn output remains inactive (when tolevn = 0). <2> when the values of 8-bit timer counter hn and the cm p0n register match, the tohn output level is inverted, the value of 8-bit timer counter hn is cleared, and the inttmhn signal is output. <3> when the values of 8-bit timer counter hn and the cm p1n register match, the le vel of the tohn output is returned. at this time, the 8-bit timer counter val ue is not cleared and the inttmhn signal is not output. <4> clearing the tmhen bit to 0 during timer hn operati on makes the inttmhn signal and tohn output inactive. remark n = 0, 1 chapter 9 8-bit timers h0 and h1 user?s manual u17553ej4v0ud 254 figure 9-12. operation timing in pwm output mode (2/4) (b) operation when cmp0n = ffh, cmp1n = 00h count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 00h 01h ffh 00h 01h 02h ffh 00h ffh 00h 01h 02h cmp1n ffh 00h (c) operation when cmp0n = ffh, cmp1n = feh count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 00h 01h feh ffh 00h 01h feh ffh 00h 01h feh ffh 00h cmp1n ffh feh remark n = 0, 1 chapter 9 8-bit timers h0 and h1 user?s manual u17553ej4v0ud 255 figure 9-12. operation timing in pwm output mode (3/4) (d) operation when cmp0n = 01h, cmp1n = 00h count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 01h 00h 01h 00h 01h 00h 00h 01h 00h 01h cmp1n 00h remark n = 0, 1 chapter 9 8-bit timers h0 and h1 user?s manual u17553ej4v0ud 256 figure 9-12. operation timing in pwm output mode (4/4) (e) operation by changi ng cmp1n (cmp1n = 01h 03h, cmp0n = a5h) count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 00h 01h 02h a5h 00h 01h 02h 03h a5h 00h 01h 02h 03h a5h 00h cmp1n 01h a5h 03h 01h (03h) <1> <3> <4> <2> <2>' <5> <6> <1> the count operation is enabled by setting tmhen = 1. start 8-bit timer counter hn by masking one count clock to count up. at this time, the tohn output remains inactive (when tolevn = 0). <2> the cmp1n register value can be changed during timer counter operation. this operation is asynchronous to the count clock. <3> when the values of 8-bit timer count er hn and the cmp0n register match, the value of 8-bit timer counter hn is cleared, the tohn output becomes active, and the inttmhn signal is output. <4> if the cmp1n register value is changed, the value is latched and not transferred to the register. when the values of 8-bit timer counter hn and the cmp1n register before the change match, the value is transferred to the cmp1n register and the cmp1n re gister value is changed (<2>?). however, three count clocks or more are required fr om when the cmp1n register value is changed to when the value is transferred to the register. if a match signal is generated within thr ee count clocks, the changed value cannot be transferred to the register. <5> when the values of 8-bit timer counter hn and the cm p1n register after the change match, the tohn output becomes inactive. 8-bit timer counter hn is no t cleared and the inttmhn signal is not generated. <6> clearing the tmhen bit to 0 during timer hn operati on makes the inttmhn signal and tohn output inactive. remark n = 0, 1 chapter 9 8-bit timers h0 and h1 user?s manual u17553ej4v0ud 257 9.4.3 carrier generator mode operation (8-bit timer h1 only) the carrier clock generated by 8-bit timer h1 is output in the cycle set by 8-bit timer/event counter 51. in carrier generator mode, the output of the 8-bit timer h1 carrier pulse is controlled by 8-bit timer/event counter 51, and the carrier pulse is out put from the toh1 output. (1) carrier generation in carrier generator mode, 8-bit timer h compare regist er 01 (cmp01) generates a low-level width carrier pulse waveform and 8-bit timer h compare register 11 (cmp11) generates a high-level width carrier pulse waveform. rewriting the cmp11 register during 8-bit timer h1 operat ion is possible but rewriti ng the cmp01 register is prohibited. (2) carrier output control carrier output is controlled by the interrupt request sig nal (inttm51) of 8-bit timer/event counter 51 and the nrzb1 and rmc1 bits of the 8-bit timer h carrier co ntrol register (tmcyc1). the relationship between the outputs is shown below. rmc1 bit nrzb1 bit output 0 0 low-level output 0 1 high-level output 1 0 low-level output 1 1 carrier pulse output chapter 9 8-bit timers h0 and h1 user?s manual u17553ej4v0ud 258 to control the carrier pulse output during a count operation, the nrz1 and nrzb1 bits of the tmcyc1 register have a master and slave bit configuratio n. the nrz1 bit is read-only but t he nrzb1 bit can be read and written. the inttm51 signal is synchronized with the 8-bit timer h1 count clock and output as the inttm5h1 signal. the inttm5h1 signal becomes the data transfer signal of the nrz1 bit, and the nrzb1 bit value is transferred to the nrz1 bit. the timing for transfer from the nrzb1 bit to the nrz1 bit is as shown below. figure 9-13. transfer timing 8-bit timer h1 count clock tmhe1 inttm51 inttm5h1 nrz1 nrzb1 rmc1 1 1 1 0 00 <1> <2> <1> the inttm51 signal is synchronized with the count cl ock of 8-bit timer h1 and is output as the inttm5h1 signal. <2> the value of the nrzb1 bit is tr ansferred to the nrz1 bit at the second clock from the rising edge of the inttm5h1 signal. cautions 1. do not rewrite the nrzb1 bit again until at least th e second clock after it has been rewritten, or else the transfer from the nrzb1 bit to the nrz1 bit is not guaranteed. 2. when 8-bit timer/event c ounter 51 is used in the carrier generator mode, an interrupt is generated at the timing of <1>. when 8-bit timer/event counter 51 is used in a mode other than the carrier generator mode, the timi ng of the interrupt generation differs. chapter 9 8-bit timers h0 and h1 user?s manual u17553ej4v0ud 259 (3) usage outputs an arbitrary carrier clock from the toh1 pin. <1> set each register. figure 9-14. register setting in carrier generator mode (i) setting 8-bit timer h m ode register 1 (tmhmd1) 0 0/1 0/1 0/1 0 timer output enabled timer output level inversion setting carrier generator mode selection count clock (f cnt ) selection count operation stopped 1 0/1 1 tmmd10 tolev1 toen1 cks11 cks12 tmhe1 tmhmd1 cks10 tmmd11 (ii) cmp01 register setting ? compare value (iii) cmp11 register setting ? compare value (iv) tmcyc1 register setting ? rmc1 = 1 ... remote control output enable bit ? nrzb1 = 0/1 ... carrier output enable bit (v) tcl51 and tmc51 register setting ? see 8.3 registers controlling 8-bit timer/event counters 50 and 51 . <2> when tmhe1 = 1, 8-bit timer h1 starts counting. <3> when tce51 of 8-bit timer mode control register 51 (tmc 51) is set to 1, 8-bit timer/event counter 51 starts counting. <4> after the count operation is enabled, the first com pare register to be compared is the cmp01 register. when the count value of 8-bit time r counter h1 and the cmp 01 register value match, the inttmh1 signal is generated, 8-bit timer counter h1 is cleared, and at the same time, the compare register to be compared with 8-bit timer counter h1 is switched from the cmp01 register to the cmp11 register. <5> when the count value of 8-bit ti mer counter h1 and the cm p11 register value match, the inttmh1 signal is generated, 8-bit timer counter h1 is cleared, and at the same time, the compare register to be compared with 8-bit timer counter h1 is switched from the cmp11 register to the cmp01 register. <6> by performing procedures <4> and <5> r epeatedly, a carrier clock is generated. <7> the inttm51 signal is synchronized with count clock of 8-bit timer h1 and output as the inttm5h1 signal. the inttm5h1 signal becomes the data transfer signal for the nrzb1 bit, and the nrzb1 bit value is transferred to the nrz1 bit. <8> when the nrz1 bit is high level, a carri er clock is output from the toh1 pin. <9> by performing the procedures above, an arbitrary carrier clock is obtained. to stop the count operation, clear tmhe1 to 0. chapter 9 8-bit timers h0 and h1 user?s manual u17553ej4v0ud 260 if the setting value of the cmp01 register is n, the setting value of the cmp 11 register is m, and the count clock frequency is f cnt , the carrier clock output cycle and duty are as follows. carrier clock output cycle = (n + m + 2)/f cnt duty = high-level width : carrier clock ou tput width = ( m + 1) : (n + m + 2) cautions 1. be sure to set the cmp11 register when starting the timer count operation (tmhe1 = 1) after the timer count operation was stopped (tmhe1 = 0) (b e sure to set again even if setting the same value to the cmp11 register). 2. set so that the count clock frequency of tmh1 becomes more than 6 times the count clock frequency of tm51. (4) timing chart the carrier output control timing is shown below. cautions 1. set the values of the cmp01 and cmp11 registers in a range of 01h to ffh. 2. in the carrier generator mode, three ope rating clocks (signal selected by cks12 to cks10 bits of tmhmd1 register) or more are requi red from when the cmp11 register value is changed to when the value is transferred to the register. 3. be sure to set the rmc1 bit be fore the count operation is started. chapter 9 8-bit timers h0 and h1 user?s manual u17553ej4v0ud 261 figure 9-15. carrier generator mode operation timing (1/3) (a) operation when cmp01 = n, cmp11 = n 00h n 00h n 00h n 00h n 00h n 00h n n n 0 0 1 1 0 0 1 1 0 0 00h 01h l 00h 01h l 00h 01h l 00h 01h 00h 01h l l cmpn0 cmpn1 tmhen inttmhn carrier clock 8-bit timer 5n count clock tm5n count value cr5n tce5n tohn inttm5n nrzbn nrzn carrier clock inttm5hn 8-bit timer hn count clock 8-bit timer counter hn count value <1> <2> <3> <4> <5> <6> <7> <1> when tmhe1 = 0 and tce51 = 0, 8-bit timer counter h1 operation is stopped. <2> when tmhe1 = 1 is set, 8-bit timer counter h1 starts a count operation. at that ti me, the carrier clock is held at the inactive level. <3> when the count value of 8-bit timer counter h1 matc hes the cmp01 register val ue, the first inttmh1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer counter h1 is switched from the cmp01 register to the cmp11 register. 8-bit timer counter h1 is cleared to 00h. <4> when the count value of 8-bit timer counter h1 matc hes the cmp11 register value, the inttmh1 signal is generated, the carrier clock signal is inverted, and t he compare register to be compared with 8-bit timer counter h1 is switched from the cmp11 register to the cmp01 register. 8-bit timer counter h1 is cleared to 00h. by performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to 50% is generated. <5> when the inttm51 signal is generated, it is synchro nized with 8-bit timer h1 count clock and output as the inttm5h1 signal. <6> the inttm5h1 signal becomes the data transfer si gnal for the nrzb1 bit, and the nrzb1 bit value is transferred to the nrz1 bit. <7> when nrz1 = 0 is set, the toh1 output becomes low level. chapter 9 8-bit timers h0 and h1 user?s manual u17553ej4v0ud 262 figure 9-15. carrier generator mode operation timing (2/3) (b) operation when cmp01 = n, cmp11 = m n l 00h n 00h 01h m 00h n 00h 01h m 00h 00h n m 0 0 1 1 0 0 1 1 0 0 00h 01h l 00h 01h l 00h 01h l 00h 01h 00h 01h l cmpn0 cmpn1 tmhen inttmhn carrier clock 8-bit timer 5n count clock tm5n count value cr5n tce5n tohn inttm5n nrzbn nrzn carrier clock inttm5hn 8-bit timer hn count clock 8-bit timer counter hn count value <1> <2> <3> <4> <5> <6> <7> <1> when tmhe1 = 0 and tce51 = 0, 8-bit timer counter h1 operation is stopped. <2> when tmhe1 = 1 is set, 8-bit timer counter h1 starts a count operation. at that ti me, the carrier clock is held at the inactive level. <3> when the count value of 8-bit timer counter h1 matc hes the cmp01 register val ue, the first inttmh1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer counter h1 is switched from the cmp01 register to the cmp11 register. 8-bit timer counter h1 is cleared to 00h. <4> when the count value of 8-bit timer counter h1 matc hes the cmp11 register value, the inttmh1 signal is generated, the carrier clock signal is inverted, and t he compare register to be compared with 8-bit timer counter h1 is switched from the cmp11 register to the cmp01 register. 8-bit timer counter h1 is cleared to 00h. by performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to other than 50% is generated. <5> when the inttm51 signal is generated, it is synchro nized with 8-bit timer h1 count clock and output as the inttm5h1 signal. <6> a carrier signal is output at the first rising edge of the carrier clock if nrz1 is set to 1. <7> when nrz1 = 0, the toh1 output is held at the high level and is not changed to low level while the carrier clock is high level (from <6> and <7>, the high-level width of the carrier clock waveform is guaranteed). chapter 9 8-bit timers h0 and h1 user?s manual u17553ej4v0ud 263 figure 9-15. carrier generator mode operation timing (3/3) (c) operation when cmp11 is changed 8-bit timer h1 count clock cmp01 tmhe1 inttmh1 carrier clock 00h 01h n 00h 01h 01h m 00h n 00h l 00h <1> <3>? <4> <3> <2> cmp11 <5> m n l m (l) 8-bit timer counter h1 count value <1> when tmhe1 = 1 is set, 8-bit timer h1 starts a count oper ation. at that time, the carrier clock is held at the inactive level. <2> when the count value of 8-bit timer counter h1 matches the cmp01 register value, 8-bit timer counter h1 is cleared and the inttmh1 signal is output. <3> the cmp11 register can be rewritten during 8-bit timer h1 operation, however, the changed value (l) is latched. the cmp11 register is changed when the co unt value of 8-bit timer counter h1 and the cmp11 register value before t he change (m) match (<3>?). <4> when the count value of 8-bit timer counter h1 and the cmp11 register value before the change (m) match, the inttmh1 signal is output, the carrier signal is inve rted, and 8-bit timer counter h1 is cleared to 00h. <5> the timing at which the count value of 8-bit timer counter h1 and the cmp11 regi ster value match again is indicated by the value after the change (l). user?s manual u17553ej4v0ud 264 chapter 10 watch timer 10.1 functions of watch timer the watch timer has the following functions. ? watch timer ? interval timer the watch timer and the interval timer can be used simultaneously. figure 10-1 shows the watch timer block diagram. figure 10-1. block diagram of watch timer f prs /2 7 f w /2 4 f w /2 5 f w /2 6 f w /2 7 f w /2 8 f w /2 10 f w /2 11 f w /2 9 f sub intwt intwti wtm0 wtm1 wtm2 wtm3 wtm4 wtm5 wtm6 wtm7 f w clear 11-bit prescaler clear 5-bit counter watch timer operation mode register (wtm) internal bus selector selector selector selector f wx /2 4 f wx /2 5 f wx remark f prs : peripheral hardware clock frequency f sub : subsystem clock frequency f w : watch timer clock frequency (f prs /2 7 or f sub ) f wx : f w or f w /2 9 chapter 10 watch timer user?s manual u17553ej4v0ud 265 (1) watch timer when the high-speed system clock or subsystem clock is used, interrupt requests (intwt) are generated at preset intervals. table 10-1. watch timer interrupt time interrupt time when operated at f sub = 32.768 khz when operated at f prs = 4 mhz when operated at f prs = 5 mhz when operated at f prs = 10 mhz when operated at f prs = 20 mhz 2 4 /f w 488 s 0.51 ms 410 s 205 s 102 s 2 5 /f w 977 s 1.03 ms 819 s 410 s 205 s 2 13 /f w 0.25 s 0.26 s 0.210 s 0.105 s 520 s 2 14 /f w 0.5 s 0.53 s 0.419 s 0. 210 s 0.105 s remark f prs : peripheral hardware clock frequency f sub : subsystem clock frequency f w : watch timer clock frequency (f prs /2 7 or f sub ) (2) interval timer interrupt requests (intwti) are gen erated at preset time intervals. table 10-2. interval timer interval time interrupt time when operated at f sub = 32.768 khz when operated at f prs = 4 mhz when operated at f prs = 5 mhz when operated at f prs = 10 mhz when operated at f prs = 20 mhz 2 4 /f w 488 s 0.51 ms 410 s 205 s 102 s 2 5 /f w 977 s 1.03 ms 820 s 410 s 205 s 2 6 /f w 1.95 ms 2.05 ms 1.64 ms 820 s 410 s 2 7 /f w 3.91 ms 4.1 ms 3.28 ms 1.64 ms 820 s 2 8 /f w 7.81 ms 8.2 ms 6.55 ms 3.28 ms 1.64 ms 2 9 /f w 15.6 ms 16.4 ms 13.1 ms 6.55 ms 3.28 ms 2 10 /f w 31.3 ms 32.75 ms 26.2 ms 13.1 ms 6.55 ms 2 11 /f w 62.5 ms 65.55 ms 52.4 ms 26.2 ms 13.1 ms remark f prs : peripheral hardware clock frequency f sub : subsystem clock frequency f w : watch timer clock frequency (f prs /2 7 or f sub ) 10.2 configuration of watch timer the watch timer includes the following hardware. table 10-3. watch timer configuration item configuration counter 5 bits 1 prescaler 11 bits 1 control register watch timer operation mode register (wtm) chapter 10 watch timer user?s manual u17553ej4v0ud 266 10.3 register controlling watch timer the watch timer is controlled by the wa tch timer operation mode register (wtm). ? watch timer operation mode register (wtm) this register sets the watch timer count clock, enabl es/disables operation, prescaler interval time, and 5-bit counter operation control. wtm is set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears wtm to 00h. figure 10-2. format of watch timer operation mode register (wtm) address: ff8fh after reset: 00h r/w symbol 7 6 5 4 3 2 <1> <0> wtm wtm7 wtm6 wtm5 wtm4 wtm3 wtm2 wtm1 wtm0 watch timer count clock selection (f w ) wtm7 f sub = 32.768 khz f prs = 4 mhz f prs = 8 mhz f prs = 10 mhz f prs = 20 mhz 0 f prs /2 7 ? 31.25 khz 62.5 khz 78.125 khz 156.25 khz 1 f sub 32.768 khz ? wtm6 wtm5 wtm4 prescaler interval time selection 0 0 0 2 4 /f w 0 0 1 2 5 /f w 0 1 0 2 6 /f w 0 1 1 2 7 /f w 1 0 0 2 8 /f w 1 0 1 2 10 /f w 1 1 0 2 10 /f w 1 1 1 2 11 /f w wtm3 wtm2 interrupt time selection 0 0 2 14 /f w 0 1 2 13 /f w 1 0 2 5 /f w 1 1 2 4 /f w wtm1 5-bit counter operation control 0 clear after operation stop 1 start wtm0 watch timer operation enable 0 operation stop (clear bot h prescaler and 5-bit counter) 1 operation enable chapter 10 watch timer user?s manual u17553ej4v0ud 267 caution do not change the count clock and interval ti me (by setting bits 4 to 7 (wtm4 to wtm7) of wtm) during watch timer operation. remarks 1. f w : watch timer clock frequency (f prs /2 7 or f sub ) 2. f prs : peripheral hardware clock frequency 3. f sub : subsystem clock frequency chapter 10 watch timer user?s manual u17553ej4v0ud 268 10.4 watch timer operations 10.4.1 watch timer operation the watch timer generates an interrupt request (intwt) at a specific time interval by using the peripheral hardware clock or subsystem clock. when bit 0 (wtm0) and bit 1 (wtm1) of the watch timer oper ation mode register (wtm) are set to 1, the count operation starts. when these bits are cleared to 0, t he 5-bit counter is cleared an d the count operation stops. when the interval timer is simultaneously operated, zero-s econd start can be achieved only for the watch timer by clearing wtm1 to 0. in this case, however, the 11-bit prescaler is not cleared. therefore, an error up to 2 9 1/f w seconds occurs in the first overfl ow (intwt) after zero-second start. the interrupt request is generated at the following time intervals. table 10-4. watch timer interrupt time wtm3 wtm2 interrupt time selection when operated at f sub = 32.768 khz (wtm7 = 1) when operated at f prs = 4 mhz (wtm7 = 0) when operated at f prs = 5 mhz (wtm7 = 0) when operated at f prs = 10 mhz (wtm7 = 0) when operated at f prs = 20 mhz (wtm7 = 0) 0 0 2 14 /f w 0.5 s 0.53 s 0.419 s 0. 210 s 0.105 s 0 1 2 13 /f w 0.25 s 0.26 s 0.210 s 0.105 s 52.5 ms 1 0 2 5 /f w 977 s 1.03 ms 819 s 410 s 205 s 1 1 2 4 /f w 488 s 0.51 ms 410 s 205 s 102 s remarks 1. f w : watch timer clock frequency (f prs /2 7 or f sub ) 2. f prs : peripheral hardware clock frequency 3. f sub : subsystem clock frequency chapter 10 watch timer user?s manual u17553ej4v0ud 269 10.4.2 interval timer operation the watch timer operates as interval timer which generates in terrupt requests (intwti) r epeatedly at an interval of the preset count value. the interval time can be selected with bits 4 to 6 (wtm 4 to wtm6) of the watch timer operation mode register (wtm). when bit 0 (wtm0) of the wtm is set to 1, the count operation starts. when this bit is set to 0, the count operation stops. table 10-5. interval timer interval time wtm6 wtm5 wtm4 interval time when operated at f sub = 32.768 khz (wtm7 = 1) when operated at f prs = 4 mhz (wtm7 = 0) when operated at f prs = 5 mhz (wtm7 = 0) when operated at f prs = 10 mhz (wtm7 = 0) when operated at f prs = 20 mhz (wtm7 = 0) 0 0 0 2 4 /f w 488 s 0.51 ms 410 s 205 s 102 s 0 0 1 2 5 /f w 977 s 1.03 ms 820 s 410 s 205 s 0 1 0 2 6 /f w 1.95 ms 2.05 ms 1.64 ms 820 s 410 s 0 1 1 2 7 /f w 3.91 ms 4.1 ms 3.28 ms 1.64 ms 820 s 1 0 0 2 8 /f w 7.81 ms 8.2 ms 6.55 ms 3.28 ms 1.64 ms 1 0 1 2 9 /f w 15.6 ms 16.4 ms 13.1 ms 6.55 ms 3.28 ms 1 1 0 2 10 /f w 31.3 ms 32.75 ms 26.2 ms 13.1 ms 6.55 ms 1 1 1 2 11 /f w 62.5 ms 65.55 ms 52.4 ms 26.2 ms 13.1 ms remarks 1. f w : watch timer clock frequency (f prs /2 7 or f sub ) 2. f prs : peripheral hardware clock frequency 3. f sub : subsystem clock frequency figure 10-3. operation timing of watch timer/interval timer 0h start overflow overflow 5-bit counter count clock watch timer interrupt intwt interval timer interrupt intwti interrupt time of watch timer (0.5 s) interval time (t) t interrupt time of watch timer (0.5 s) remark f w : watch timer clock frequency figures in parentheses are for operation with f w = 32.768 khz (wtm7 = 1, wtm3, wtm2 = 0, 0) chapter 10 watch timer user?s manual u17553ej4v0ud 270 10.5 cautions for watch timer when operation of the watch timer and 5- bit counter is enabled by the watch timer mode control register (wtm) (by setting bits 0 (wtm0) and 1 (wtm1) of wtm to 1), the inte rval until the first interr upt request (intwt) is generated after the register is set does not exactly match the specif ication made with bits 2 and 3 (wtm2, wtm3) of wtm. subsequently, however, the intwt signal is generated at the specified intervals. figure 10-4. example of generation of watch timer interrupt request (int wt) (when interrupt period = 0.5 s) it takes 0.515625 seconds for the first intwt to be generated (2 9 1/32768 = 0.015625 s longer). intwt is then generated every 0.5 seconds. 0.5 s 0.5 s 0.515625 s wtm0, wtm1 intwt user?s manual u17553ej4v0ud 271 chapter 11 watchdog timer 11.1 functions of watchdog timer the watchdog timer operates on the internal low-speed oscillation clock. the watchdog timer is used to detect an inadvertent program loop. if a program loop is detected, an internal reset signal is generated. program loop is detected in the following cases. ? if the watchdog timer counter overflows ? if a 1-bit manipulation instruction is execut ed on the watchdog timer enable register (wdte) ? if data other than ?ach? is written to wdte ? if data is written to wdte during a window close period ? if the instruction is fetched from an area not set by the ims and ixs registers (detection of an invalid check while the cpu hangs up) ? if the cpu accesses an area that is not set by t he ims and ixs registers (excluding fb00h to ffffh) by executing a read/write instruct ion (detection of an abnormal access during a cpu program loop) when a reset occurs due to the watchdog timer, bit 4 (wdtrf) of the reset control flag register (resf) is set to 1. for details of resf, see chapter 19 reset function . chapter 11 watchdog timer user?s manual u17553ej4v0ud 272 11.2 configuration of watchdog timer the watchdog timer includes the following hardware. table 11-1. configuration of watchdog timer item configuration control register watchdog timer enable register (wdte) how the counter operation is controlled, overflow ti me, and window open period are set by the option byte. table 11-2. setting of op tion bytes and watchdog timer setting of watchdog timer option byte (0080h) window open period bits 6 and 5 (window1, window0) controlling counter operation of watchdog timer bit 4 (wdton) overflow time of watchdog timer bits 3 to 1 (wdcs2 to wdcs0) remark for the option byte, see chapter 23 option byte . figure 11-1. block diag ram of watchdog timer f rl /2 clock input controller reset output controller internal reset signal internal bus selector 17-bit counter 2 10 /f rl to 2 17 /f rl watchdog timer enable register (wdte) clear, reset control wdton of option byte (0080h) window1 and window0 of option byte (0080h) count clear signal wdcs2 to wdcs0 of option byte (0080h) overflow signal cpu access signal cpu access error detector window size determination signal chapter 11 watchdog timer user?s manual u17553ej4v0ud 273 11.3 register controlling watchdog timer the watchdog timer is controlled by the watchdog timer enable register (wdte). (1) watchdog timer enable register (wdte) writing ach to wdte clears the watchdog timer counter and starts counting again. this register can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 9ah or 1ah note . figure 11-2. format of watchdog timer enable register (wdte) 0 1 2 3 4 5 6 7 symbol wdte address: ff9bh after reset: 9ah/1ah note r/w note the wdte reset value differs depending on the wdto n setting value of the option byte (0080h). to operate watchdog timer, set wdton to 1. wdton setting value wdte reset value 0 (watchdog timer count operation disabled) 1ah 1 (watchdog timer count operation enabled) 9ah cautions 1. if a value other than a ch is written to wdte, an internal reset signal is gene rated. if the source clock to the watchdog timer is stopped, however, an internal reset signal is generated when the source clock to the watchdog timer resumes operation. 2. if a 1-bit memory manipulation instructio n is executed for wdte, an internal reset signal is generated. if the source clock to th e watchdog timer is stopped, however, an internal reset signal is gene rated when the source clock to the watchdog timer resumes operation. 3. the value read from wdte is 9ah/1ah (this differs fr om the written value (ach)). chapter 11 watchdog timer user?s manual u17553ej4v0ud 274 11.4 operation of watchdog timer 11.4.1 controlling operation of watchdog timer 1. when the watchdog timer is used, its operati on is specified by the option byte (0080h). ? enable counting operation of the watchdog timer by se tting bit 4 (wdton) of the option byte (0080h) to 1 (the counter starts operating after a reset release) (for details, see chapter 23 ). wdton operation control of watchdog ti mer counter/illegal access detection 0 counter operation disabled (counting stopped after rese t), illegal access detect ion operation disabled. 1 counter operation enabled (counting started after re set), illegal access detection operation enabled. ? set an overflow time by using bits 3 to 1 (wdcs2 to wdcs0) of the option byte (0080h) (for details, see 11.4.2 and chapter 23 ). ? set a window open period by using bits 6 and 5 (window1 and window0) of the option byte (0080h) (for details, see 11.4.3 and chapter 23 ). 2. after a reset release, the watchdog timer starts counting. 3. by writing ?ach? to wdte after the watchdog timer starts counting and before the overflow time set by the option byte, the watchdog timer is cl eared and starts counting again. 4. after that, write wdte the second time or later after a reset release during the window open period. if wdte is written during a period other than the window open period, an internal reset signal is generated. 5. if the overflow time expires without ?ach? written to wdte, an internal reset signal is generated. an internal reset signal is generated in the following cases. ? if a 1-bit manipulation instruction is execut ed on the watchdog timer enable register (wdte) ? if data other than ?ach? is written to wdte ? if the instruction is fetched from an area not set by the ims and ixs registers (det ection of an invalid check during a cpu program loop) ? if the cpu accesses an area not set by the ims and ixs registers (exc luding fb00h to ffffh) by executing a read/write instruction (det ection of an abnormal access during a cpu program loop) cautions 1. the first writing to wdte after a reset release clears the watchdog timer, if it is made before the overflow time regardless of the timing of the writing, and the watchdog timer starts counting again. 2. if the watchdog timer is cl eared by writing ?ach? to wdte, the actual overflow time may be different from the overflow time set by the option byte by up to 2/f rl seconds. 3. the watchdog timer can be cleared immediately before the count value overflows (ffffh). chapter 11 watchdog timer user?s manual u17553ej4v0ud 275 cautions 4. the operation of the watchdog timer in the halt and stop modes differs as follows depending on the set value of bit 0 (lsrosc) of the option byte. lsrosc = 0 (internal low-speed oscillator can be stopped by software) lsrosc = 1 (internal low-speed oscillator cannot be stopped) in halt mode watchdog timer operation continues. in stop mode watchdog timer operation stops. if lsrosc = 0, the watchdog timer resum es counting after the halt or stop mode is released. at this time, the counter is not clear ed to 0 but starts counting from the value at which it was stopped. if oscillation of the internal low-speed oscilla tor is stopped by setting lsrstop (bit 1 of the internal oscillation mode register (rcm) = 1) when lsrosc = 0, the watchdog timer stops operating. at this time, the counter is not cleared to 0. 5. the watchdog timer continues it s operation during self-programming and eeprom tm emulation of the flash memory. during pr ocessing, the interrupt acknowledge time is delayed. set the overflow ti me and window size taking this delay into consideration. chapter 11 watchdog timer user?s manual u17553ej4v0ud 276 11.4.2 setting overflow time of watchdog timer set the overflow time of the watchdog timer by using bits 3 to 1 (wdcs2 to wdcs0) of the option byte (0080h). if an overflow occurs, an internal reset signal is generated. if ?ach? is written to wdte during the window open period before the overflow time, the present count is cleared and the watc hdog timer starts counting again. the following overflow time is set. table 11-3. setting of over flow time of watchdog timer wdcs2 wdcs1 wdcs0 overflow time of watchdog timer 0 0 0 2 10 /f rl (3.88 ms) 0 0 1 2 11 /f rl (7.76 ms) 0 1 0 2 12 /f rl (15.52 ms) 0 1 1 2 13 /f rl (31.03 ms) 1 0 0 2 14 /f rl (62.06 ms) 1 0 1 2 15 /f rl (124.12 ms) 1 1 0 2 16 /f rl (248.24 ms) 1 1 1 2 17 /f rl (496.48 ms) cautions 1. the combination of w dcs2 = wdcs1 = wdcs0 = 0 and window1 = window0 = 0 is prohibited. 2. the watchdog timer continues its operation during self-programming and eeprom emulation of the flash memory. during processing, the interrupt acknowledge time is delayed. set the overflow time and window size taking this delay into consideration. remarks 1. f rl : internal low-speed oscillation clock frequency 2. ( ): f rl = 264 khz (max.) chapter 11 watchdog timer user?s manual u17553ej4v0ud 277 11.4.3 setting window open period of watchdog timer set the window open period of the watchdog timer by usi ng bits 6 and 5 (window1, window0) of the option byte (0080h). the outline of the window is as follows. ? if ?ach? is written to wdte during the window open per iod, the watchdog timer is cleared and starts counting again. ? even if ?ach? is written to wdte during the window cl ose period, an abnormality is detected and an internal reset signal is generated. example : if the window open period is 25% window close period (75%) window open period (25%) counting starts overflow time counting starts again when ach is written to wdte. internal reset signal is generated if ach is written to wdte. caution the first writing to wdte after a reset release clears the watchdog timer, if it is made before the overflow time regardless of the timing of th e writing, and the watc hdog timer starts counting again. the window open period to be set is as follows. table 11-4. setting window open period of watchdog timer window1 window0 window open period of watchdog timer 0 0 25% 0 1 50% 1 0 75% 1 1 100% cautions 1. the combination of w dcs2 = wdcs1 = wdcs0 = 0 and window1 = window0 = 0 is prohibited. 2. the watchdog timer continues its operation during self-programming and eeprom emulation of the flash memory. during processing, the interrupt acknowledge time is delayed. set the o verflow time and window size taking this delay into consideration. chapter 11 watchdog timer user?s manual u17553ej4v0ud 278 remark if the overflow time is set to 2 10 /f rl , the window close time and open time are as follows. setting of window open period 25% 50% 75% 100% window close time 0 to 3.56 ms 0 to 2.37 ms 0 to 0.119 ms none window open time 3.56 to 3.88 ms 2.37 to 3.88 ms 0.119 to 3.88 ms 0 to 3.88 ms user?s manual u17553ej4v0ud 279 chapter 12 clock output/buzzer output controller 12.1 functions of clock output/buzzer output controller the clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral lsis. the clock selected with the clock output selection register (cks) is output. in addition, the buzzer output is intended for square- wave output of buzzer frequency selected with cks. figure 12-1 shows the block diagram of clock output/buzzer output controller. figure 12-1. block diagram of clo ck output/buzzer output controller f prs f prs /2 10 to f prs /2 13 f prs to f prs /2 7 f sub bzoe bcs1 bcs0 cloe cloe bzoe 84 pcl/intp6/p72 buz/intp7/p73 bcs0, bcs1 clock controller prescaler internal bus ccs3 clock output selection register (cks) ccs2 ccs1 ccs0 output latch (p73) pm73 output latch (p72) pm72 selector selector chapter 12 clock output/buzzer output controller user?s manual u17553ej4v0ud 280 12.2 configuration of clock output/buzzer output controller the clock output/buzzer output controller includes the following hardware. table 12-1. clock output/buzzer output controller configuration item configuration control registers clock output selection register (cks) port mode register 7 (pm7) port register 7 (p7) 12.3 register controlling clock output/buzzer output controller the following two registers are used to control the clock output/buzzer output controller. ? clock output selection register (cks) ? port mode register 7 (pm7) (1) clock output selection register (cks) this register sets output enable/disable for clock out put (pcl) and for the buzzer frequency output (buz), and sets the output clock. cks is set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears cks to 00h. chapter 12 clock output/buzzer output controller user?s manual u17553ej4v0ud 281 figure 12-2. format of clock ou tput selection register (cks) address: ff40h after reset: 00h r/w symbol <7> 6 5 <4> 3 2 1 0 cks bzoe bcs1 bcs0 cloe ccs3 ccs2 ccs1 ccs0 bzoe buz output enable/disable specification 0 clock division circui t operation stopped. buz fixed to low level. 1 clock division ci rcuit operation enabled. buz output enabled. buz output clock selection bcs1 bcs0 f prs = 10 mhz f prs = 20 mhz 0 0 f prs /2 10 9.77 khz 19.54 khz 0 1 f prs /2 11 4.88 khz 9.77 khz 1 0 f prs /2 12 2.44 khz 4.88 khz 1 1 f prs /2 13 1.22 khz 2.44 khz cloe pcl output enable/disable specification 0 clock division circui t operation stopped. pcl fixed to low level. 1 clock division ci rcuit operation enabled. pcl output enabled. pcl output clock selection note ccs3 ccs2 ccs1 ccs0 f sub = 32.768 khz f prs = 10 mhz f prs = 20 mhz 0 0 0 0 f prs note1 10 mhz setting prohibited note2 0 0 0 1 f prs /2 5 mhz 10 mhz 0 0 1 0 f prs /2 2 2.5 mhz 5 mhz 0 0 1 1 f prs /2 3 1.25 mhz 2.5 mhz 0 1 0 0 f prs /2 4 625 khz 1.25 mhz 0 1 0 1 f prs /2 5 312.5 khz 625 khz 0 1 1 0 f prs /2 6 156.25 khz 312.5 khz 0 1 1 1 f prs /2 7 ? 78.125 khz 156.25 khz 1 0 0 0 f sub 32.768 khz ? other than above setting prohibited notes 1. if the peripheral hardware clock operates on the inte rnal high-speed oscillation clock when 1.8 v v dd < 2.7 v, setting ccs3 = ccs2 = ccs1 = ccs0 = 0 (output clock of pcl: f prs ) is prohibited. 2. the pcl output clock prohibits settings if they exceed 10 mhz. cautions 1. set bcs1 and bcs0 when the bu zzer output operation is stopped (bzoe = 0). 2. set ccs3 to ccs0 while the clock output operation is stopped (cloe = 0). remarks 1. f prs : peripheral hardware clock frequency 2. f sub : subsystem clock frequency chapter 12 clock output/buzzer output controller user?s manual u17553ej4v0ud 282 (2) port mode register 7 (pm7) this register sets port 7 input/output in 1-bit units. when using the p72/intp6/pcl pin for clock output and the p73/intp7/buz pin for buzzer output, set pm72, pm73 and the output latch of p72, p73 to 0. pm7 is set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pm7 to ffh. figure 12-3. format of port mode register 7 (pm7) address: ff27h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm7 1 pm76 pm75 pm74 pm73 pm72 pm71 pm70 pm7n p7n pin i/o mode selection (n = 0 to 6) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 12 clock output/buzzer output controller user?s manual u17553ej4v0ud 283 12.4 clock output/buzzer output controller operations 12.4.1 clock output operation the clock pulse is output as the following procedure. <1> select the clock pulse output frequency with bits 0 to 3 (ccs0 to ccs3) of the clock output selection register (cks) (clock pulse output in disabled status). <2> set bit 4 (cloe) of cks to 1 to enable clock output. remark the clock output controller is designed not to output pulses with a small width during output enable/disable switching of the clock output. as show n in figure 12-4, be sure to start output from the low period of the clock (marked with * in the figure). when stopping output, do so after the high-level period of the clock. figure 12-4. remote control output application example cloe clock output ** 12.4.2 operation as buzzer output the buzzer frequency is output as the following procedure. <1> select the buzzer output frequency with bits 5 and 6 (b cs0, bcs1) of the clock output selection register (cks) (buzzer output in disabled status). <2> set bit 7 (bzoe) of cks to 1 to enable buzzer output. user?s manual u17553ej4v0ud 284 chapter 13 a/d converter 13.1 function of a/d converter the a/d converter converts an analog input signal into a di gital value, and consists of up to sixteen channels (ani0 to ani15) with a resolution of 10 bits. the a/d converter has the following function. ? 10-bit resolution a/d conversion 10-bit resolution a/d conversion is carried out repeatedly for one channel selected from analog inputs ani0 to ani15. each time an a/d conversion operation en ds, an interrupt request (intad) is generated. figure 13-1. block diag ram of a/d converter av ref av ss intad adcs bit adcs fr2 fr1 adce fr0 sample & hold circuit av ss voltage comparator a/d converter mode register (adm) internal bus 4 ads2 ads1 ads0 analog input channel specification register (ads) controller a/d conversion result register (adcr) successive approximation register (sar) lv1 lv0 5 a/d port configuration register (adpc) adpc3 adpc2 adpc1 adpc0 5 tap selector p80/ani0 p81/ani1 p82/ani2 p83/ani3 p84/ani4 p85/ani5 p86/ani6 p87/ani7 p90/ani8 p91/ani9 p92/ani10 p93/ani11 p94/ani12 p95/ani13 p96/ani14 p97/ani15 selector ads3 adpc4 chapter 13 a/d converter user?s manual u17553ej4v0ud 285 13.2 configuration of a/d converter the a/d converter includes the following hardware. (1) ani0 to ani15 pins these are the analog input pins of the 16-channel a/d converter. they input analog signals to be converted into digital signals. pins other than the one selected as the analog input pin can be used as i/o port pins. (2) sample & hold circuit the sample & hold circuit samples the input voltage of the analog input pin selected by the selector when a/d conversion is started, and holds the samp led voltage value during a/d conversion. (3) series resistor string the series resistor stri ng is connected between av ref and av ss , and generates a voltage to be compared with the sampled voltage value. figure 13-2. circuit configuration of series resistor string adcs series resistor string av ref p-ch av ss (4) voltage comparator the voltage comparator compares the sampled voltage value and the output volt age of the series resistor string. (5) successive approximation register (sar) this register converts the result of comparison by the voltage comparator, starting from the most significant bit (msb). when the voltage value is converted into a digital valu e down to the least significant bit (lsb) (end of a/d conversion), the contents of the sar register are transfe rred to the a/d conversion result register (adcr). (6) 10-bit a/d conversion r esult register (adcr) the a/d conversion result is loaded from the successive approximation register to th is register each time a/d conversion is completed, and the adcr re gister holds the a/d conversion result in its higher 10 bits (the lower 6 bits are fixed to 0). chapter 13 a/d converter user?s manual u17553ej4v0ud 286 (7) 8-bit a/d conversion result register (adcrh) the a/d conversion result is loaded from the successive approximation register to th is register each time a/d conversion is completed, and the adcrh register stores the higher 8 bi ts of the a/d conversion result. caution when data is read from adcr and adcrh, a wait cycle is gene rated. do not read data from adcr and adcrh when the cpu is operating on the subsystem clock and the peripheral hardware clock is stopped. for de tails, see chapter 31 cautions for wait. (8) controller this circuit controls the conversion time of an input analog signal that is to be converted into a digital signal, as well as starting and stopping of t he conversion operation. when a/d c onversion has been completed, this controller generates intad. (9) av ref pin this pin inputs an analog power/reference voltage to the a/d converter. make this pin the same potential as the v dd pin when port 8 and port 9 are used as a digital port. the signal input to ani0 to ani15 is converted into a digital signal, based on the voltage applied across av ref and av ss . (10) av ss pin this is the ground potential pin of the a/d converter. al ways use this pin at the same potential as that of the v ss pin even when the a/d converter is not used. (11) a/d converter mode register (adm) this register is used to set the conversion time of the analog input signal to be conver ted, and to start or stop the conversion operation. (12) a/d port configuration register (adpc) this register switches the p80/ani0 to p87/ani7, p90/ani8 to p97/ani15 pins to analog input of a/d converter or digital i/o of port. (13) analog input channel sp ecification register (ads) this register is used to specify the port that inputs the analog voltage to be converted into a digital signal. (14) port mode register 8 (pm8) this register switches the p80/ani0 to p87/ani7 pins to input or output. (15) port mode register 9 (pm9) this register switches the p90/ani8 to p97/ani15 pins to input or output. chapter 13 a/d converter user?s manual u17553ej4v0ud 287 13.3 registers used in a/d converter the a/d converter uses the following seven registers. ? a/d converter mode register (adm) ? a/d port configuration register (adpc) ? analog input channel specification register (ads) ? port mode register 8 (pm8) ? port mode register 9 (pm9) ? 10-bit a/d conversion result register (adcr) ? 8-bit a/d conversion result register (adcrh) (1) a/d converter mode register (adm) this register sets the conversion time for analog inpu t to be a/d converted, and starts/stops conversion. adm can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 13-3. format of a/d converter mode register (adm) adce lv0 note 1 lv1 note 1 fr0 note 1 fr1 note 1 fr2 note 1 0 adcs a/d conversion operation control stops conversion operation enables conversion operation adcs 0 1 <0> 1 2 3 4 5 6 <7> adm address: ff2ah after reset: 00h r/w symbol comparator operation control note 2 stops comparator operation enables comparator operation (comparator: 1/2av ref operation) adce 0 1 notes 1. for details of fr2 to fr0, lv 1, lv0, and a/d conversion, see table 13-2 a/d conversion time selection . 2. the operation of the compar ator is controlled by adcs and adce, and it takes 1 s from operation start to operation stabilization. ther efore, when adcs is set to 1 after 1 s or more has elapsed from the time adce is set to 1, the conversion result at that time has priority over the first conversion result. otherwise, ignore data of the first conversion. chapter 13 a/d converter user?s manual u17553ej4v0ud 288 table 13-1. settings of adcs and adce adcs adce a/d co nversion operation 0 0 stop status (dc power consumption path does not exist) 0 1 conversion waiting mode (comparator: 1/2av ref operation, only comparator consumes power) 1 0 conversion mode (comparator operation stopped note ) 1 1 conversion mode (comparator: 1/2av ref operation) note ignore data of the first conversion because it is not guaranteed range. figure 13-4. timing chart wh en comparator is used adce comparator adcs conversion operation conversion operation conversion stopped conversion waiting comparator: 1/2av ref operation note note to stabilize the internal circuit, the time from the rising of the adce bit to the rising of the adcs bit must be 1 s or longer. cautions 1. a/d conversion must be stopped before re writing bits fr0 to fr2, lv1, and lv0 to values other than the identical data. 2. if data is written to adm, a wait cycle is generated. do not write data to adm when the cpu is operating on the subsystem clock and the periphera l hardware clock is stopped. for details, see chapter 31 cautions for wait. chapter 13 a/d converter user?s manual u17553ej4v0ud 289 table 13-2. a/d conversion time selection (1) 2.7 v av ref 5.5 v a/d converter mode register (adm) conversion time selection fr2 fr1 fr0 lv1 lv0 f prs = 4 mhz f prs = 10 mhz f prs = 20 mhz conversion clock (f ad ) 0 0 0 0 0 264/f prs 26.4 s 13.2 s f prs /12 0 0 1 0 0 176/f prs setting prohibited 17.6 s 8.8 s note f prs /8 0 1 0 0 0 132/f prs 33.0 s 13.2 s 6.6 s note f prs /6 0 1 1 0 0 88/f prs 22.0 s 8.8 s note f prs /4 1 0 0 0 0 66/f prs 16.5 s 6.6 s note f prs /3 1 0 1 0 0 44/f prs 11.0 s note setting prohibited setting prohibited f prs /2 other than above setting prohibited note this can be set only when 4.0 v av ref 5.5 v. (2) 2.3 v av ref < 2.7 v a/d converter mode register (adm) conversion time selection fr2 fr1 fr0 lv1 lv0 f prs = 2 mhz f prs = 5 mhz conversion clock (f ad ) 0 0 0 0 1 480/f prs setting prohibited f prs /12 0 0 1 0 1 320/f prs setting prohibited 64.0 s f prs /8 0 1 0 0 1 240/f prs 60.0 s 48.0 s f prs /6 0 1 1 0 1 160/f prs 40.0 s 32.0 s f prs /4 1 0 0 0 1 120/f prs 30.0 s setting prohibited f prs /3 other than above setting prohibited cautions 1. set the conversion ti mes with the following conditions. ? 4.0 v av ref 5.5 v: f ad = 0.6 to 3.6 mhz ? 2.7 v av ref < 4.0 v: f ad = 0.6 to 1.8 mhz ? 2.3 v av ref < 2.7 v: f ad = 0.6 to 1.48 mhz 2. when rewriting fr2 to fr0, lv1, and lv0 to other than the same data, stop a/d conversion once (adcs = 0) beforehand. 3. change lv1 and lv0 from the default value, when 2.3 v av ref < 2.7 v. 4. the above conversion time does not include clock frequency errors. select conversion time, taking clock frequency erro rs into consideration. remark f prs : peripheral hardware clock frequency chapter 13 a/d converter user?s manual u17553ej4v0ud 290 figure 13-5. a/d converter sa mpling and a/d conversion timing adcs wait period note conversion time conversion time sampling time sampling timing intad adcs 1 or ads rewrite sampling time sar clear sar clear transfer to adcr, intad generation successive conversion time note for details of wait period, see chapter 31 cautions for wait . (2) 10-bit a/d conversion r esult register (adcr) this register is a 16-bit register that stores the a/d conversion result. the lower 6 bits are fixed to 0. each time a/d conversion ends, the conversion resu lt is loaded from the successive appr oximation register, and is stored in adcr in order starting from bit 7 of ff19h. ff19h indi cates the higher 8 bits of the conversion result, and ff18h indicates the lower 2 bits of the conversion result. adcr can be read by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0000h. figure 13-6. format of 10-bit a/d conversion result register (adcr) symbol address: ff18h, ff19h after reset: 0000h r ff19h ff18h 0 0 0 0 0 0 adcr cautions 1. when writing to the a/d converter mode register (adm), analog input ch annel specification register (ads), and a/d port configuration register (adpc), the contents of adcr may become undefined. read the conversion resu lt following conversion completion before writing to adm, ads, and adpc. using timing other than the above m ay cause an incorrect conversion result to be read. 2. if data is read from adcr, a wait cycle is ge nerated. do not read data from adcr when the cpu is operating on the subsystem clock and th e peripheral hardware clock is stopped. for details, see chapter 31 cautions for wait. chapter 13 a/d converter user?s manual u17553ej4v0ud 291 (3) 8-bit a/d conversion result register (adcrh) this register is an 8-bit register that stores the a/d conversion result. the higher 8 bits of 10-bit resolution are stored. adcrh can be read by an 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 13-7. format of 8-bit a/d c onversion result register (adcrh) symbol adcrh address: ff19h after reset: 00h r 76543210 cautions 1. when writing to the a/d converter mode register (adm), analog in put channel specification register (ads), and a/d port configuration register (adpc), the contents of adcrh may become undefined. read the conversion resu lt following conversion completion before writing to adm, ads, and adpc. using timing ot her than the above m ay cause an incorrect conversion result to be read. 2. if data is read from adcrh, a wait cycle is generated. do not read data from adcrh when the cpu is operating on the subsystem clock and the peripheral hardware clock is stopped. for details, see chapter 31 cautions for wait. chapter 13 a/d converter user?s manual u17553ej4v0ud 292 (4) analog input channel specification register (ads) this register specifies the input port of the analog voltage to be a/d converted. ads can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 13-8. format of analog input channel specification register (ads) address: ff2bh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 ads 0 0 0 0 ads3 ads2 ads1 ads0 ads3 ads2 ads1 ads0 analog input channel specification 0 0 0 0 ani0 0 0 0 1 ani1 0 0 1 0 ani2 0 0 1 1 ani3 0 1 0 0 ani4 0 1 0 1 ani5 0 1 1 0 ani6 0 1 1 1 ani7 1 0 0 0 ani8 1 0 0 1 ani9 1 0 1 0 ani10 1 0 1 1 ani11 1 1 0 0 ani12 1 1 0 1 ani13 1 1 1 0 ani14 1 1 1 1 ani15 cautions 1. be sure to clear bits 4 to 7 to 0. 2 because ads and adpc do not control input and output, set the channel used for a/d conversion in the input mode by using port mode register 8, 9 (pm8, pm9). if the channel is set in the output mode, selection of adpc is disabled. 3. do not set a pin to be used as a digital input pin with adpc with ads. 4. if data is written to ads, a wait cycle is gene rated. do not write data to ads when the cpu is operating on the subsystem clock and the periphera l hardware clock is stopped. for details, see chapter 31 cautions for wait. chapter 13 a/d converter user?s manual u17553ej4v0ud 293 (5) a/d port configuration register (adpc) this register switches the p80/ani0 to p87/ani7, p90/ani8 to p97/ani15 pins to analog input of a/d converter or digital i/o of port. adpc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 13-9. format of a/d port configuration register (adpc) address: ff22h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 adpc 0 0 0 adpc4 adpc3 adpc2 adpc1 adpc0 analog input (a)/ digi tal i/o (d) switching adpc4 adpc3 adpc2 adpc1 adpc0 p97/ ani15 p96/ ani14 p95/ ani13 p94/ ani12 p93/ ani11 p92/ ani10 p91/ ani9 p90/ ani8 p87/ ani7 p86/ ani6 p85/ ani5 p84/ ani4 p83/ ani3 p82/ ani2 p81/ ani1 p80/ ani0 0 0 0 0 0 a a a a a a a a a a a a a a a a 0 0 0 0 1 a a a a a a a a a a a a a a a d 0 0 0 1 0 a a a a a a a a a a a a a a d d 0 0 0 1 1 a a a a a a a a a a a a a d d d 0 0 1 0 0 a a a a a a a a a a a a d d d d 0 0 1 0 1 a a a a a a a a a a a d d d d d 0 0 1 1 0 a a a a a a a a a a d d d d d d 0 0 1 1 1 a a a a a a a a a d d d d d d d 0 1 0 0 0 a a a a a a a a d d d d d d d d 0 1 0 0 1 a a a a a a a d d d d d d d d d 0 1 0 1 0 a a a a a a d d d d d d d d d d 0 1 0 1 1 a a a a a d d d d d d d d d d d 0 1 1 0 0 a a a a d d d d d d d d d d d d 0 1 1 0 1 a a a d d d d d d d d d d d d d 0 1 1 1 0 a a d d d d d d d d d d d d d d 0 1 1 1 1 a d d d d d d d d d d d d d d d 1 0 0 0 0 d d d d d d d d d d d d d d d d other than above setting prohibited cautions 1. set the channel to be used for a/d conversion in th e input mode by using port mode register 8, 9 (pm8, pm9). 2. if data is written to adpc, a wait cycle is generated. do not writ e data to adpc when the cpu is operating on the subsystem clock and the peripheral hardware clo ck is stopped. for details, see chapter 31 cautions for wait. chapter 13 a/d converter user?s manual u17553ej4v0ud 294 (6) port mode register 8 (pm8) when using the p80/ani0 to p87/ani7 pins for analog input port, set pm80 to pm87 to 1. the output latches of p80 to p87 at this time may be 0 or 1. if pm80 to pm87 are set to 0, they cannot be used as analog input port pins. pm8 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. figure 13-10. format of port mode register 8 (pm8) address: ff28h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm8 pm87 pm86 pm85 pm84 pm83 pm82 pm81 pm80 pm8n p8n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) (7) port mode register 9 (pm9) when using the p90/ani8 to p97/ani15 pins for analog in put port, set pm90 to pm97 to 1. the output latches of p90 to p97 at this time may be 0 or 1. if pm90 to pm97 are set to 0, they cannot be used as analog input port pins. pm9 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. figure 13-11. format of port mode register 9 (pm9) address: ff29h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm9 pm97 pm96 pm95 pm94 pm93 pm92 pm91 pm90 pm9n p9n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) p80/ani0 to p87/ani7, p90/ani8 to p97/ani15 pins ar e as shown below depending on the settings of adpc, ads, pm8 and pm9. table 13-3. setting functions of p80/ani0 to p87/ani7, p90/ani8 to p97/ani15 pins adpc pm8, pm9 ads p80/ani0 to p87/ani7, p90/ani8 to p97/ani15 pins selects ani. analog input (to be converted) input mode does not select ani. analog input (not to be converted) selects ani. analog input selection output mode does not select ani. setting prohibited input mode ? digital input digital i/o selection output mode ? digital output chapter 13 a/d converter user?s manual u17553ej4v0ud 295 13.4 a/d converter operations 13.4.1 basic operations of a/d converter <1> set bit 0 (adce) of the a/d converter mode register (adm) to 1 to start the operation of the comparator. <2> set channels for a/d conversion to analog input by us ing the a/d port configuration register (adpc) and set to input mode by using port mode register 8, 9 (pm8, pm9). <3> set a/d conversion time by using bits 5 to 1 (fr2 to fr0, lv1, and lv0) of adm. <4> select one channel for a/d conversion using the analog input channel specification register (ads). <5> start the conversion operation by setting bit 7 (adcs) of adm to 1. (<6> to <12> are operations performed by hardware.) <6> the voltage input to the selected analog input c hannel is sampled by the sample & hold circuit. <7> when sampling has been done for a certain time, the sa mple & hold circuit is placed in the hold state and the sampled voltage is held until the a/ d conversion operation has ended. <8> bit 9 of the successive approximation register (sar) is set. the series resistor string voltage tap is set to (1/2) av ref by the tap selector. <9> the voltage difference between the series resistor st ring voltage tap and sampled voltage is compared by the voltage comparator. if the analog input is greater than (1/2) av ref , the msb of sar remains set to 1. if the analog input is smaller than (1/2) av ref , the msb is reset to 0. <10> next, bit 8 of sar is automatically set to 1, and t he operation proceeds to the next comparison. the series resistor string voltage tap is selected according to the preset value of bit 9, as described below. ? bit 9 = 1: (3/4) av ref ? bit 9 = 0: (1/4) av ref the voltage tap and sampled voltage are compared and bit 8 of sar is manipulated as follows. ? analog input voltage voltage tap: bit 8 = 1 ? analog input voltage < voltage tap: bit 8 = 0 <11> comparison is continued in this way up to bit 0 of sar. <12> upon completion of the comparison of 10 bits, an effective digital result value remains in sar, and the result value is transferred to the a/d conversion resu lt register (adcr, adcrh) and then latched. at the same time, the a/d conversion end in terrupt request (intad) can also be generated. <13> repeat steps <6> to <12>, until adcs is cleared to 0. to stop the a/d converter, clear adcs to 0. to restart a/d conversion from the st atus of adce = 1, start from <5>. to start a/d conversion again when adce = 0, set adce to 1, wait for 1 s or longer, and start <5>. to change a channel of a/d conversion, start from <4>. caution make sure the period of <1> to <5> is 1 s or more. remark two types of a/d conversion re sult registers are available. ? adcr (16 bits): store 10-bit a/d conversion value ? adcrh (8 bits): store 8-bit a/d conversion value chapter 13 a/d converter user?s manual u17553ej4v0ud 296 figure 13-12. basic operation of a/d converter conversion time sampling time sampling a/d conversion undefined conversion result a/d converter operation sar adcr intad conversion result a/d conversion operations are performed continuously until bit 7 (adcs) of the a/d converter mode register (adm) is reset (0) by software. if a write operation is performed to the analog input chan nel specification register (ads) during an a/d conversion operation, the conversion operation is in itialized, and if the adcs bit is set (1), conversion starts again from the beginning. reset signal generation clears the a/d conversion re sult register (adcr, adcrh) to 0000h or 00h. chapter 13 a/d converter user?s manual u17553ej4v0ud 297 13.4.2 input voltage and conversion results the relationship between the analog input voltage input to the analog input pins (ani0 to ani15) and the theoretical a/d conversion result (stored in the 10-bit a/d conversion result regi ster (adcr)) is shown by the following expression. sar = int ( 1024 + 0.5) adcr = sar 64 or (adcr ? 0.5) v ain < (adcr + 0.5) where, int( ): function which returns integer part of value in parentheses v ain : analog input voltage av ref : av ref pin voltage adcr: a/d conversion result register (adcr) value sar: successive approximation register figure 13-13 shows the relationship between the analo g input voltage and the a/d conversion result. figure 13-13. relationship between analog i nput voltage and a/d conversion result 1023 1022 1021 3 2 1 0 ffc0h ff80h ff40h 00c0h 0080h 0040h 0000h a/d conversion result (adcr) sar adcr 1 2048 1 1024 3 2048 2 1024 5 2048 input voltage/av ref 3 1024 2043 2048 1022 1024 2045 2048 1023 1024 2047 2048 1 v ain av ref av ref 1024 av ref 1024 chapter 13 a/d converter user?s manual u17553ej4v0ud 298 13.4.3 a/d converter operation mode the operation mode of the a/d converter is the select mode. one channel of analog input is selected from ani0 to ani15 by the analog input channel specificati on register (ads) and a/d conversion is executed. (1) a/d conversion operation by setting bit 7 (adcs) of the a/d converter mode regist er (adm) to 1, the a/d conversion operation of the voltage, which is applied to the analog input pin specif ied by the analog input channel specification register (ads), is started. when a/d conversion has been completed, the result of the a/d c onversion is stored in t he a/d conversion result register (adcr), and an interrupt request signal (int ad) is generated. when one a/d conversion has been completed, the next a/d conversion operation is immedi ately started. if ads is rewritten during a/d conversion, the a/d conver sion operation under executio n is stopped and restarted from the beginning. if 0 is written to adcs during a/d conversion, a/d conv ersion is immediately stopped. at this time, the conversion result immediat ely before is retained. figure 13-14. a/d conversion operation anin rewriting adm adcs = 1 rewriting ads adcs = 0 anin anin anin anim anin anim anim stopped conversion result immediately before is retained a/d conversion adcr, adcrh intad conversion is stopped conversion result immediately before is retained remarks 1. n = 0 to 15 2. m = 0 to 15 chapter 13 a/d converter user?s manual u17553ej4v0ud 299 the setting methods are described below. <1> set bit 0 (adce) of the a/d converter mode register (adm) to 1. <2> set the channel to be used in the analog input m ode by using bits 4 to 0 (adpc4 to adpc0) of the a/d port configuration register (adpc) and bits 7 to 0 (p m87 to pm80) of port mode register 8 (pm8), bits 7 to 0 (pm97 to pm90) of port mode register 9 (pm9). <3> select conversion time by using bits 5 to 1 (fr2 to fr0, lv1, and lv0) of adm. <4> select a channel to be used by using bits 3 to 0 (ads3 to ads0) of the analog input channel specification register (ads). <5> set bit 7 (adcs) of adm to 1 to start a/d conversion. <6> when one a/d conversion has been completed, an interrupt request signal (intad) is generated. <7> transfer the a/d conversion data to the a/d conversion result register (adcr, adcrh). chapter 13 a/d converter user?s manual u17553ej4v0ud 300 13.5 how to read a/d converter characteristics table here, special terms unique to the a/d converter are explained. (1) resolution this is the minimum analog input vo ltage that can be identif ied. that is, the perce ntage of the analog input voltage per bit of digital output is called 1lsb (least si gnificant bit). the percentage of 1lsb with respect to the full scale is expressed by %fsr (full scale range). 1lsb is as follows when the resolution is 10 bits. 1lsb = 1/2 10 = 1/1024 = 0.098%fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these express the overall error. note that the quantization error is not included in the overall erro r in the characteristics table. (3) quantization error when analog values are converted to digital values, a 1/2lsb error naturally occurs. in an a/d converter, an analog input voltage in a range of 1/2lsb is converted to the same digita l code, so a quantization error cannot be avoided. note that the quantization erro r is not included in the overall error, zero -scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. figure 13-15. overall error figur e 13-16. quanti zation error ideal line 0 ?? 0 1 ?? 1 digital output overall error analog input av ref 0 0 ?? 0 1 ?? 1 digital output quantization error 1/2lsb 1/2lsb analog input 0 av ref (4) zero-scale error this shows the difference between the actual measuremen t value of the analog input vo ltage and the theoretical value (1/2lsb) when the digital output changes from 0......000 to 0......001. if the actual measurement value is greater than the theore tical value, it shows the difference between the actual measurement value of the analog in put voltage and the theoretical val ue (3/2lsb) when the digital output changes from 0??001 to 0??010. chapter 13 a/d converter user?s manual u17553ej4v0ud 301 (5) full-scale error this shows the difference between the actual measuremen t value of the analog input vo ltage and the theoretical value (full-scale ? 3/2lsb) when the digital output chan ges from 1......110 to 1......111. (6) integral linearity error this shows the degree to which the conversion charac teristics deviate from the ideal linear relationship. it expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. (7) differential linearity error while the ideal width of code output is 1lsb, this indi cates the difference between the actual measurement value and the ideal value. figure 13-17. zero-scale error figure 13-18. full-scale error 111 011 010 001 zero-scale error ideal line 000 01 2 3 av ref digital output (lower 3 bits) analog input (lsb) 111 110 101 000 0 av ref ? 3 full-scale error ideal line analog input (lsb) digital output (lower 3 bits) av ref ? 2av ref ? 1 av ref figure 13-19. integral linearity error figure 13-20. differential linearity error 0 av ref digital output analog input integral linearity error ideal line 1 ?? 1 0 ?? 0 0 av ref digital output analog input differential linearity error 1 ?? 1 0 ?? 0 ideal 1lsb width (8) conversion time this expresses the time from the start of samp ling to when the digital output is obtained. the sampling time is included in the conv ersion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on for the anal og voltage to be sampled by the sample & hold circuit. sampling time conversion time chapter 13 a/d converter user?s manual u17553ej4v0ud 302 13.6 cautions for a/d converter (1) operating current in stop mode the a/d converter stops operating in the stop mode. at this time, th e operating current can be reduced by clearing bit 7 (adcs) and bit 0 (adce) of the a/d converter mode register (adm) to 0. to restart from the standby status, clear bit 6 (adif) of interrupt request flag register 1l (if1l) to 0 and start operation. (2) input range of ani0 to ani15 observe the rated range of the ani0 to an i15 input voltage. if a voltage of av ref or higher and av ss or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. in addition, the converted values of the other channels may also be affected. (3) conflicting operations <1> conflict between a/d conversion result register (adcr, adcrh) write and adcr or adcrh read by instruction upon the end of conversion adcr or adcrh read has priority. after the read op eration, the new co nversion result is written to adcr or adcrh. <2> conflict between adcr or adcrh write and a/d conv erter mode register (adm) write, analog input channel specification register (ads), or a/d port configuration register (a dpc) write upon the end of conversion adm, ads, or adpc write has priority. adcr or adcrh write is not performed, nor is the conversion end interrupt signal (intad) generated. (4) noise countermeasures to maintain the 10-bit resolution, attent ion must be paid to noise input to the av ref pin and pins ani0 to ani15. <1> connect a capacitor with a low equivalent resistance and a good frequency response to the power supply. <2> the higher the output impedance of the analog in put source, the greater the influence. to reduce the noise, connecting external c as shown in figure 13-21 is recommended. <3> do not switch these pins wit h other pins during conversion. <4> the accuracy is improved if the halt mode is set immediately after the start of conversion. chapter 13 a/d converter user?s manual u17553ej4v0ud 303 figure 13-21. analog input pin connection reference voltage input c = 100 to 1,000 pf if there is a possibility that noise equal to or higher than av ref or equal to or lower than av ss may enter, clamp with a diode with a small v f value (0.3 v or lower). av ref av ss v ss ani0 to ani15 (5) p80/ani0 to p87/ani7, p90/ani8 to p97/ani15 <1> the analog input pins (ani0 to ani15) are also used as i/o port pins (p80 to p87, p90 to p97). when a/d conversion is performed with any of ani0 to ani15 selected, do not access p80 to p87, p90 to p97 while conversion is in progress; otherwise the conversion resolution may be degraded. it is recommended to select pins used as p80 to p87, p90 to p97 starting with the p80/an i0 that is the furthest from av ref . <2> if a digital pulse is applied to the pins adjacent to th e pins currently used for a/d conversion, the expected value of the a/d conversion may not be obtained due to coupling noise. t herefore, do not apply a pulse to the pins adjacent to the pi n undergoing a/d conversion. (6) input impedance of ani0 to ani15 pins this a/d converter charges a sampling capacitor for sampling during sampling time. therefore, only a leakage current flows when sampling is not in progress, and a current that charges the capacitor flows during sampling. consequently, the input impedance fluctuates depending on whether sampling is in progress, and on the other states. to make sure that sampling is effective, however, it is recommended to keep the ou tput impedance of the analog input source to within 10 k , and to connect a capacitor of about 100 pf to the ani0 to ani15 pins (see figure 13-21 ). (7) av ref pin input impedance a series resistor string of several tens of k is connected between the av ref and av ss pins. therefore, if the output impedance of t he reference voltage source is high, this will result in a series connection to the series resistor string between the av ref and av ss pins, resulting in a large reference voltage error. chapter 13 a/d converter user?s manual u17553ej4v0ud 304 (8) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if th e analog input channel specification register (ads) is changed. therefore, if an analog input pin is changed during a/d conversion, the a/d conversion result and adif for the pre-change analog input may be set just before the ads rewrit e. caution is therefore re quired since, at this time, when adif is read immediately after the ads rewrite, ad if is set despite the fact a/d conversion for the post- change analog input has not ended. when a/d conversion is stopped and then resumed, clear ad if before the a/d conversion operation is resumed. figure 13-22. timing of a/d conver sion end interrupt request generation ads rewrite (start of anin conversion) a/d conversion adcr adif anin anin anim anim anin anin anim anim ads rewrite (start of anim conversion) adif is set but anim conversion has not ended. remarks 1. n = 0 to 15 2. m = 0 to 15 (9) conversion results just after a/d conversion start the first a/d conversion value immediately after a/d conv ersion starts may not fall wit hin the rating range if the adcs bit is set to 1 within 1 s after the adce bit was set to 1, or if t he adcs bit is set to 1 with the adce bit = 0. take measures such as polling the a/d conversion end interrupt request (intad) and removing the first conversion result. (10) a/d conversion result regist er (adcr, adcrh) read operation when a write operation is performed to the a/d conver ter mode register (adm), analog input channel specification register (ads), and a/d port configuration register (adp c), the contents of adcr and adcrh may become undefined. read the conversion re sult following conversion completion before writing to adm, ads, and adpc. using a timing other than the above may cause an incorrect conversion result to be read. chapter 13 a/d converter user?s manual u17553ej4v0ud 305 (11) internal equivalent circuit the equivalent circuit of the analog input block is shown below. figure 13-23. internal equi valent circuit of anin pin anin c1 c2 r1 table 13-4. resistance and capacitance valu es of equivalent circui t (reference values) av ref r1 c1 c2 4.0 v av ref 5.5 v 8.1 k 8 pf 5 pf 2.7 v av ref < 4.0 v 31 k 8 pf 5 pf 2.3 v av ref < 2.7 v 381 k 8 pf 5 pf remarks 1. the resistance and capacitance values shown in table 13-4 are not guaranteed values. 2. n = 0 to 15 user?s manual u17553ej4v0ud 306 chapter 14 serial interfaces uart60 and uart61 the 78k0/ff2 incorporate serial interfaces uart60 and uart61. 14.1 functions of serial interfaces uart60 and uart61 serial interfaces uart60 and ua rt61 have the following two modes. (1) operation stop mode this mode is used when serial communication is not executed and can enable a reduction in the power consumption. for details, see 14.4.1 operation stop mode . (2) asynchronous serial interface (uart) mode this mode supports the lin (local interconnect network) -bus. the functions of this mode are outlined below. for details, see 14.4.2 asynchronous seri al interface (uart) mode and 14.4.3 dedicated baud rate generator . ? maximum transfer rate: 625 kbps ? two-pin configuration txd 6n: transmit data output pin r x d6n: receive data input pin ? data length of communication data can be selected from 7 or 8 bits. ? dedicated internal 8-bit baud rate generator allowing any baud rate to be set ? transmission and reception can be performe d independently (full-duplex operation). ? twelve operating clock inputs selectable ? msb- or lsb-first communication selectable ? inverted transmission operation ? sync break field transmission from 13 to 20 bits ? more than 11 bits can be identified for sync break field reception (sbf reception flag provided). cautions 1. the t x d6n output inversion function inverts onl y the transmission side and not the reception side. to use this function, the reception side mu st be ready for reception of inverted data. 2. if clock supply to seria l interfaces uart60 and uart61 are not stopped (e.g., in the halt mode), normal operation continues. if cl ock supply to serial interfaces uart60 and uart61 are stopped (e.g., in the stop mode), each register stops operating, and holds the value immediately before cl ock supply was stopped. the t x d6n pins also holds the value immediately before clock suppl y was stopped and out puts it. however, the operation is not guaranteed after clock supply is resumed. therefore, reset the circuit by setting power6n = 0, rxe6n = 0, and txe6n = 0. 3. set power6n = 1 and then set txe6n = 1 (tr ansmission) or rxe6n = 1 (reception) to start communication. 4. txe6n and rxe6n are synch ronized by the base clock (f xclk6 ) set by cksr6n. to enable transmission or reception again, set txe6n or rxe6n to 1 at least two clo cks of the base clock after txe6n or rxen6 has been cleared to 0. if txe6n or rxe6n is set within two clocks of the base clock, the transmission circuit or recepti on circuit may not be initialized. 5. set transmit data to txb6n at least one base clock (f xclk6 ) after setting txe6n = 1. chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 307 cautions 6. if data is continuously transmitted, the communicatio n timing from the stop bit to the next start bit is extended two operat ing clocks of the macro. how ever, this does not affect the result of communication because the reception side initializes the timing when it has detected a start bit. do no t use the continuous transmissi on function if the interface is used in lin communication operation. remarks 1 . lin stands for local interconnect network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. lin communication is single-master communication, and up to 15 slaves can be connected to one master. the lin slaves are used to control the s witches, actuators, and sensors, and these are connected to the lin mast er via the lin network. normally, the lin master is connected to a network such as can (controller area network). in addition, the lin bus uses a single-wi re method and is connected to the nodes via a transceiver that complies with iso9141. n the lin protocol, the mast er transmits a frame with baud rate information and the slave receives it and corrects the baud rate error. t herefore, communication is possible when the baud rate error in the slave is 15% or less. 2. n = 0, 1 figures 14-1 and 14-2 outline the transmi ssion and reception operations of lin. figure 14-1. lin transmission operation lin bus wakeup signal frame 8 bits note 1 55h transmission data transmission data transmission data transmission data transmission 13-bit note 2 sbf transmission note 3 sync break field sync field identifier field data field data field checksum field txd6n intst6n notes 1. the wakeup signal frame is substituted by 80h transmission in the 8-bit mode. 2. the sync break field is output by har dware. the output width is the bit le ngth set by bits 4 to 2 (sbl62n to sbl60n) of asynchronous serial interface control register 6n (asicl6n). if more precise output width adjustment is necessary, use baud rate generator control register 6n (brgc6n) (see 14.4.2 (2) (h) sbf transmission ). 3. intst6n is output on completion of each transmission. it is also output when sbf is transmitted. remark the interval between each field is controlled by software. n = 0, 1 chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 308 figure 14-2. lin reception operation lin bus 13-bit sbf reception sf reception id reception data reception data reception data reception <3> <1> <4> wakeup signal frame sync break field sync field identifer field data field data field checksum field rxd6n reception interrupt (intsr6n) edge detection (intpn) capture timer disable enable disable enable <2> <5> reception processing is as follows. <1> the wakeup signal is detected at the edge of the pin, and enables uart6n and sets the sbf reception mode. <2> reception continues until the stop bit is detected. when an sbf with low- level data of 11 bits or more has been detected, it is assum ed that sbf reception has been complet ed correctly, and an interrupt signal is output. if an sbf with low-level dat a of less than 11 bits has been detect ed, it is assumed that an sbf reception error has occurred. the interrupt signal is not output and the sbf reception mode is restored. <3> if sbf reception has been completed correctly, an interru pt signal is output. start 16-bit timer/event counter 00 by the sbf reception end interrupt servicing and meas ure the bit interval (pulse width) of the sync field (see 7.4.3 pulse width measurement operation ). detection of errors ove6n, pe6n, and fe6n is suppressed, and error detection proc essing of uart communication and dat a transfer of the shift register and rxb6n is not performed. the shift register holds the reset value ffh. <4> calculate the baud rate error from the bit length of the sync field, disable uart 6n after sf reception, and then re-set baud rate generator control register 6n (brgc6n). <5> distinguish the checksum field by software. also perform processing by software to initialize uart6n after reception of the checksum field and to set the sbf reception mode again. remark n = 0, 1 chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 309 figure 14-3 and 14-4 show the port conf iguration for lin reception operation. the wakeup signal transmitted from the lin master is received by detecting the edge of the external interrupt (intp0 and intp1). the length of the syn c field transmitted from the lin master can be measured using the external event capture operation of 16-bit ti mer/event counter 00, 01, and the ba ud rate error can be calculated. the input source of the reception port input (rxd60 and rx d61) can be input to the external interrupt (intp0 and intp1) and 16-bit timer/event counter 00, 01 by port input switch control (i sc), without connecting rxd60, rxd61, intp0, intp1, ti010 and ti001 externally. figure 14-3. port configuration for lin reception operation (uart60) rxd60 input p14/rxd60 port mode (pm14) output latch (p14) selector ti010 input p01/ti010 port input switch control (isc1) chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 310 figure 14-4. port configuration for lin reception operation (uart61) rxd61 input p11/rxd61 port mode (pm11) output latch (p11) selector ti001 input p05/ti001 port input switch control (isc2) chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 311 14.2 configurations of seri al interface uart60 and uart61 serial interfaces uart60 and uart 61 include the following hardware. table 14-1. configurations of serial interface uart60 and uart61 item configuration registers receive buffer register 6n (rxb6n) receive shift register 6n (rxs6n) transmit buffer register 6n (txb6n) transmit shift register 6n (txs6n) control registers asynchronous serial interface oper ation mode register 6n (asim6n) asynchronous serial interface recepti on error status register 6n (asis6n) asynchronous serial interface transm ission status register 6n (asif6n) clock selection register 6n (cksr6n) baud rate generator contro l register 6n (brgc6n) asynchronous serial interface control register 6n (asicl6n) input switch control register (isc) port mode register 1 (pm1) port register 1 (p1) remark n = 0, 1 chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 312 figure 14-5. block diagram of serial interface uart60 ti010, intp0 internal bus asynchronous serial interface control register 60 (asicl60) transmit buffer register 60 (txb60) transmit shift register 60 (txs60) t x d60/p13 intst60 baud rate generator asynchronous serial interface control register 60 (asicl60) reception control receive shift register 60 (rxs60) receive buffer register 60 (rxb60) r x d60/p14 intsr60 baud rate generator filter intsre60 asynchronous serial interface reception error status register 60 (asis60) asynchronous serial interface operation mode register 60 (asim60) asynchronous serial interface transmission status register 60 (asif60) transmission control registers f prs f prs /2 f prs /2 2 f prs /2 3 f prs /2 4 f prs /2 5 f prs /2 6 f prs /2 7 f prs /2 8 f prs /2 9 f prs /2 10 8-bit timer/ event counter 50 output 8 reception unit transmission unit clock selection register 60 (cksr60) baud rate generator control register 60 (brgc60) pm13 8 selector output latch p13 note selectable with input switch control register (isc) chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 313 figure 14-6. block diagram of serial interface uart61 internal bus asynchronous serial interface control register 61 (asicl61) transmit buffer register 61 (txb61) transmit shift register 61 (txs61) t x d61/p10/sck10 intst61 baud rate generator asynchronous serial interface control register 61 (asicl61) reception control receive shift register 61 (rxs61) receive buffer register 61 (rxb61) r x d61/p11/si10 intsr61 baud rate generator filter intsre61 asynchronous serial interface reception error status register 61 (asis61) asynchronous serial interface operation mode register 61 (asim61) asynchronous serial interface transmission status register 61 (asif61) transmission control registers f prs f prs /2 f prs /2 2 f prs /2 3 f prs /2 4 f prs /2 5 f prs /2 6 f prs /2 7 f prs /2 8 f prs /2 9 f prs /2 10 8-bit timer/ event counter 50 output 8 reception unit transmission unit clock selection register 61 (cksr61) baud rate generator control register 61 (brgc61) pm10 8 selector output latch p10 chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 314 (1) receive buffer register 6n (rxb6n) this 8-bit register stores parallel data conv erted by receive shift register 6n (rxs6n). each time 1 byte of data has been received, new receive da ta is transferred to this register from rxs6n. if the data length is set to 7 bits, data is transferred as follows. ? in lsb-first reception, the receive data is transferred to bits 0 to 6 of rxb6n and the msb of rxb6n is always 0. ? in msb-first reception, the receive data is transferred to bits 1 to 7 of rxb6n and the lsb of rxb6n is always 0. if an overrun error (ove6n) occurs, the rece ive data is not transferred to rxb6n. rxb6n can be read by an 8-bit memory manipulation inst ruction. no data can be written to this register. reset signal generation sets this register to ffh. (2) receive shift register 6n (rxs6n) this register converts the serial data input to the r x d6n pins into parallel data. rxs6n cannot be directly manipulated by a program. (3) transmit buffer register 6n (txb6n) this buffer register is used to set transmit data. tr ansmission is started when data is written to txb6n. this register can be read or written by an 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. cautions 1. do not write data to txb6n when bit 1 (txbf6n) of asyn chronous serial interface transmission status register 6n (asif6n) is 1. 2. do not refresh (write the same value to) txb6n by software during a communication operation (when bits 7 and 6 (power6n, txe6n) of asynchronous serial interface operation mode register 6n (asim6n) are 1 or when bits 7 and 5 (power6n, rxe6n) of asim6n are 1). 3. set transmit data to txb6n at least one base clock (f xclk6 ) after setting txe6n = 1. (4) transmit shift register 6n (txs6n) this register transmits the data transferred from txb6n fr om the txd6n pins as serial data. data is transferred from txb6n immediately after txb6n is written for the first transmission, or immediately before intst6n occurs after one frame was transmitted for continuous transmiss ion. data is transferred from txb6n and transmitted from the t x d6n pins at the falling edge of the base clock. txs6n cannot be directly manipulated by a program. remark n = 0, 1 chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 315 14.3 registers controlling serial interfaces uart60 and uart61 serial interfaces uart60 and uart61 are cont rolled by the following nine registers. ? asynchronous serial interface operat ion mode register 6n (asim6n) ? asynchronous serial interface recepti on error status register 6n (asis6n) ? asynchronous serial interface transmi ssion status register 6n (asif6n) ? clock selection register 6n (cksr6n) ? baud rate generator control register 6n (brgc6n) ? asynchronous serial interface control register 6n (asicl6n) ? input switch control register (isc) ? port mode register 1 (pm1) ? port register 1 (p1) (1) asynchronous serial interface opera tion mode register 6n (asim6n) this 8-bit register controls the serial communica tion operations of serial interface uart60 and uart61. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 01h. remarks 1. asim6n can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (power6n, txe6n) of asim6n = 1 or bits 7 and 5 (power6n, rxe6n) of asim6n = 1). 2. n = 0, 1 chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 316 figure 14-7. format of asynchronous serial interf ace operation mode register 60 (asim60) (1/2) address: ff2eh after reset: 01h r/w symbol <7> <6> <5> 4 3 2 1 0 asim60 power60 txe60 rxe60 ps610 ps600 cl60 sl60 isrm60 power60 enables/disables operati on of internal operation clock 0 note 1 disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit note 2 . 1 note 3 enables operation of the internal operation clock txe60 enables/disables transmission 0 disables transmission (synchronously resets th e transmission circuit). 1 enables transmission rxe60 enables/disables reception 0 disables reception (synchronous ly resets the reception circuit). 1 enables reception notes 1. the output of the t x d60 pins goes high level and the input from the r x d60 pins is fixed to the high level when power60 = 0 during transmission. 2. asynchronous serial interface reception error st atus register 60 (asis60), asynchronous serial interface transmission status register 60 (asif60), bit 7 (sbrf60) and bit 6 (sbrt60) of asynchronous serial interface control register 60 (asicl60), and receive buffer register 60 (rxb60) are reset. chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 317 figure 14-7. format of asynchronous serial interf ace operation mode register 60 (asim60) (2/2) ps610 ps600 transmission oper ation reception operation 0 0 does not output parity bit. reception without parity 0 1 outputs 0 parity. reception as 0 parity note 1 0 outputs odd parity. judges as odd parity. 1 1 outputs even parity. judges as even parity. cl60 specifies character length of transmit/receive data 0 character length of data = 7 bits 1 character length of data = 8 bits sl60 specifies number of stop bits of transmit data 0 number of stop bits = 1 1 number of stop bits = 2 isrm60 enables/disables occurr ence of reception completion interrupt in case of error 0 ?intsre60? occurs in case of error (at this time, intsr60 does not occur). 1 ?intsr60? occurs in case of error (at this time, intsre60 does not occur). note if ?reception as 0 parity? is selected, the parity is not judged. therefore, bit 2 (pe60) of asynchronous serial interface reception error status register 60 (asis60) is not set and the error interrupt does not occur. cautions 1. to start the transmission, set powe r60 to 1 and then set txe60 to 1. to stop the transmission, clear txe60 to 0, and then clear power60 to 0. 2. to start the reception, set power60 to 1 and then set rxe 60 to 1. to stop the reception, clear rxe60 to 0, and th en clear power60 to 0. 3. set power60 to 1 and then set rxe60 to 1 while a high level is input to the rxd60 pins. if power60 is set to 1 and rxe60 is set to 1 wh ile a low level is input, reception is started. 4. txe60 and rxe60 are synchronized by the base clock (f xclk6 ) set by cksr60. to enable transmission or reception again, set txe60 or rxe60 to 1 at least two clocks of the base clock after txe60 or rxe60 has b een cleared to 0. if txe60 or rxe60 is set within two clocks of the base clock, th e transmission circuit or reception circuit may not be initialized. 5. set transmit data to tx b60 at least one base clock (f xclk6 ) after setting txe60 = 1. 6. clear the txe60 and rxe60 bits to 0 be fore rewriting the ps610, ps600, and cl60 bits. 7. fix the ps610 and ps600 bits to 0 wh en used in lin communication operation. 8. clear txe60 to 0 before re writing the sl60 bit. recepti on is always performed with ?the number of stop bits = 1?, and therefore, is not affected by the set value of the sl60 bit. 9. make sure that rxe60 = 0 when rewriting the isrm60 bit. chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 318 figure 14-8. format of asynchronous serial interf ace operation mode register 61 (asim61) (1/2) address: ff2fh after reset: 01h r/w symbol <7> <6> <5> 4 3 2 1 0 asim61 power61 txe61 rxe61 ps611 ps601 cl61 sl61 isrm61 power61 enables/disables operati on of internal operation clock 0 note 1 disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit note 2 . 1 note 3 enables operation of the internal operation clock txe61 enables/disables transmission 0 disables transmission (synchronously resets th e transmission circuit). 1 enables transmission rxe61 enables/disables reception 0 disables reception (synchronous ly resets the reception circuit). 1 enables reception notes 1. the output of the t x d61 pins goes high level and the input from the r x d61 pins is fixed to the high level when power61 = 0 during transmission. 2. asynchronous serial interface reception error st atus register 61 (asis61), asynchronous serial interface transmission status register 61 (asif61), bit 7 (sbrf61) and bit 6 (sbrt61) of asynchronous serial interface control register 61 (asicl61), and receive buffer register 61 (rxb61) are reset. chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 319 figure 14-8. format of asynchronous serial interf ace operation mode register 61 (asim61) (2/2) ps611 ps601 transmission oper ation reception operation 0 0 does not output parity bit. reception without parity 0 1 outputs 0 parity. reception as 0 parity note 1 0 outputs odd parity. judges as odd parity. 1 1 outputs even parity. judges as even parity. cl61 specifies character length of transmit/receive data 0 character length of data = 7 bits 1 character length of data = 8 bits sl61 specifies number of stop bits of transmit data 0 number of stop bits = 1 1 number of stop bits = 2 isrm61 enables/disables occurr ence of reception completion interrupt in case of error 0 ?intsre61? occurs in case of error (at this time, intsr61 does not occur). 1 ?intsr61? occurs in case of error (at this time, intsre61 does not occur). note if ?reception as 0 parity? is selected, the parity is not judged. therefore, bit 2 (pe61) of asynchronous serial interface reception error status register 61 (asis61) is not set and the error interrupt does not occur. cautions 1. to start the transmission, set powe r61 to 1 and then set txe61 to 1. to stop the transmission, clear txe61 to 0, and then clear power61 to 0. 2. to start the reception, set power61 to 1 and then set rxe 61 to 1. to stop the reception, clear rxe61 to 0, and th en clear power61 to 0. 3. set power61 to 1 and then set rxe61 to 1 while a high level is input to the rxd61 pins. if power61 is set to 1 and rxe61 is set to 1 wh ile a low level is input, reception is started. 4. txe61 and rxe61 are synchronized by the base clock (f xclk6 ) set by cksr61. to enable transmission or reception again, set txe61 or rxe61 to 1 at least two clocks of the base clock after txe61 or rxe61 has b een cleared to 0. if txe61 or rxe61 is set within two clocks of the base clock, th e transmission circuit or reception circuit may not be initialized. 5. set transmit data to tx b61 at least one base clock (f xclk6 ) after setting txe61 = 1. 6. clear the txe61 and rxe61 bits to 0 be fore rewriting the ps611, ps601, and cl61 bits. 7. fix the ps611 and ps601 bits to 0 wh en used in lin communication operation. 8. clear txe61 to 0 before re writing the sl61 bit. recepti on is always performed with ?the number of stop bits = 1?, and therefore, is not affected by the set value of the sl61 bit. 9. make sure that rxe61 = 0 when rewriting the isrm61 bit. chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 320 (2) asynchronous serial interface reception error status register 6n (asis6n) this register indicates an error status on completion of reception by serial interfaces uart60 and uart61. it includes three error flag bits (pe6n, fe6n, ove6n). this register is read-only by an 8-bit memory manipulation instruction. reset signal generation, or clearing bit 7 (power6n) or bi t 5 (rxe6n) of asim6n to 0 clears this register to 00h. 00h is read when this register is read. if a receptio n error occurs, read asis6n and then read receive buffer register 6n (rxb6n) to clear the error flag. figure 14-9. format of asynchronous serial inte rface reception error status register 60 (asis60) address: ff53h after reset: 00h r symbol 7 6 5 4 3 2 1 0 asis60 0 0 0 0 0 pe60 fe60 ove60 pe60 status flag indicating parity error 0 if power60 = 0 and rxe60 = 0, or if asis60 register is read 1 if the parity of transmit data does not match the parity bit on completion of reception fe60 status flag indicating framing error 0 if power60 = 0 and rxe60 = 0, or if asis60 register is read 1 if the stop bit is not detected on completion of reception ove60 status flag indicating overrun error 0 if power60 = 0 and rxe60 = 0, or if asis60 register is read 1 if receive data is set to the rxb60 register and t he next reception operation is completed before the data is read. cautions 1. the operation of the pe60 bit differs depending on the set value s of the ps610 and ps600 bits of asynchronous serial interface ope ration mode register 60 (asim60). 2. the first bit of the receive da ta is checked as the stop bit, regardless of the number of stop bits. 3. if an overrun error occurs, the next receive data is not wri tten to receive buffer register 60 (rxb60) but discarded. 4. if data is read from asis60, a wait cycle is ge nerated. do not read da ta from asis60 when the cpu is operating on the subsystem clock and th e high-speed system clock is stopped. for details, see chapter 31 cautions for wait. chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 321 figure 14-10. format of asynchronous serial interf ace reception error status register 61 (asis61) address: ff2fh after reset: 00h r symbol 7 6 5 4 3 2 1 0 asis61 0 0 0 0 0 pe61 fe61 ove61 pe61 status flag indicating parity error 0 if power61 = 0 and rxe61 = 0, or if asis61 register is read 1 if the parity of transmit data does not match the parity bit on completion of reception fe61 status flag indicating framing error 0 if power61 = 0 and rxe61 = 0, or if asis61 register is read 1 if the stop bit is not detected on completion of reception ove61 status flag indicating overrun error 0 if power61 = 0 and rxe61 = 0, or if asis61 register is read 1 if receive data is set to the rxb61 register and t he next reception operation is completed before the data is read. cautions 1. the operation of the pe61 bit differs depending on the set value s of the ps611 and ps601 bits of asynchronous serial interface ope ration mode register 61 (asim61). 2. the first bit of the receive da ta is checked as the stop bit, regardless of the number of stop bits. 3. if an overrun error occurs, the next receive data is not wri tten to receive buffer register 61 (rxb61) but discarded. 4. if data is read from asis61, a wait cycle is generated. do not read data from asis6 when the cpu is operating on the subsystem clock and th e high-speed system clock is stopped. for details, see chapter 31 cautions for wait. chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 322 (3) asynchronous serial interface transm ission status register 6n (asif6n) this register indicates the status of transmission by se rial interfaces uart60 and uart61. it includes two status flag bits (txbf6n and txsf6n). transmission can be continued without disruption even during an interrupt period, by writing the next data to the txb6n register after data has been transferred from the txb6n register to the txs6n register. this register is read-only by an 8-bit memory manipulation instruction. reset signal generation, or clearing bit 7 (power6n) or bi t 6 (txe6n) of asim6n to 0 clears this register to 00h. figure 14-11. format of asynchronous serial inte rface transmission status register 60 (asif60) address: ff55h after reset: 00h r symbol 7 6 5 4 3 2 1 0 asif60 0 0 0 0 0 0 txbf60 txsf60 txbf60 transmit buffer data flag 0 if power60 = 0 or txe60 = 0, or if data is transferred to transmit shift register 60 (txs60) 1 if data is written to transmit buffer regi ster 60 (txb60) (if data exists in txb60) txsf60 transmit shift register data flag 0 if power60 = 0 or txe60 = 0, or if the next data is not transferred from transmit buffer register 60 (txb60) after completion of transfer 1 if data is transferred from transmit buffer register 60 (txb60) (if data transmission is in progress) cautions 1. to transmit data contin uously, write the first transmit data (first byte) to the txb60 register. be sure to check that the txbf60 fl ag is ?0?. if so, write the next transmit da ta (second byte) to the txb60 register. if data is written to th e txb60 register while the txbf60 flag is ?1?, the transmit data cannot be guaranteed. 2. to initialize the transmission unit upon comple tion of continuous transmission, be sure to check that the txsf60 flag is ?0? after genera tion of the transmission completion interrupt, and then execute initialization. if initializati on is executed while the t xsf60 flag is ?1?, the transmit data cannot be guaranteed. chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 323 figure 14-12. format of asynchronous serial inte rface transmission status register 61 (asif61) address: ff38h after reset: 00h r symbol 7 6 5 4 3 2 1 0 asif61 0 0 0 0 0 0 txbf61 txsf61 txbf61 transmit buffer data flag 0 if power61 = 0 or txe61 = 0, or if data is transferred to transmit shift register 61 (txs61) 1 if data is written to transmit buffer regi ster 61 (txb61) (if data exists in txb61) txsf61 transmit shift register data flag 0 if power61 = 0 or txe61 = 0, or if the next data is not transferred from transmit buffer register 61 (txb61) after completion of transfer 1 if data is transferred from transmit buffer register 61 (txb61) (if data transmission is in progress) cautions 1. to transmit data contin uously, write the first transmit data (first byte) to the txb61 register. be sure to check that the txbf61 fl ag is ?0?. if so, write the next transmit da ta (second byte) to the txb61 register. if data is written to th e txb61 register while the txbf61 flag is ?1?, the transmit data cannot be guaranteed. 2. to initialize the transmission unit upon comple tion of continuous transmission, be sure to check that the txsf61 flag is ?0? after genera tion of the transmission completion interrupt, and then execute initialization. if initializati on is executed while the t xsf61 flag is ?1?, the transmit data cannot be guaranteed. chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 324 (4) clock selection register 6n (cksr6n) this register selects the base clocks of serial interface uart60 and uart61. cksr6n can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 00h. remark cksr6n can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (power6n, txe6n) of asim6n = 1 or bits 7 and 5 (power6n, rxe6n) of asim6n = 1). figure 14-13. format of clock se lection register 60 (cksr60) address: ff56h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 cksr60 0 0 0 0 tps630 tps620 tps610 tps600 base clock (f xclk6 ) selection tps630 tps620 tps610 tps600 f prs = 4 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz 0 0 0 0 f prs 4 mhz 5 mhz 10 mhz 20 mhz 0 0 0 1 f prs /2 2 mhz 2.5 mhz 5 mhz 10 mhz 0 0 1 0 f prs /2 2 1 mhz 1.25 mhz 2.5 mhz 5 mhz 0 0 1 1 f prs /2 3 500 khz 625 khz 1.25 mhz 2.5 mhz 0 1 0 0 f prs /2 4 250 khz 312.5 khz 625 khz 1.25 mhz 0 1 0 1 f prs /2 5 125 khz 156.25 khz 312.5 khz 625 khz 0 1 1 0 f prs /2 6 62.5 khz 78.13 khz 156.25 khz 312.5 khz 0 1 1 1 f prs /2 7 31.25 khz 39.06 khz 78.13 khz 156.25 khz 1 0 0 0 f prs /2 8 15.625 khz 19.53 khz 39.06 khz 78.13 khz 1 0 0 1 f prs /2 9 7.813 khz 9.77 khz 19.53 khz 39.06 khz 1 0 1 0 f prs /2 10 3.906 khz 4.88 khz 9.77 khz 19.53 khz 1 0 1 1 tm50 output note other than above setting prohibited note note the following points when selecting the tm50 output as the base clock. ? mode in which the count clock is cleared and started upon a match of tm50 and cr50 (tmc506 = 0) start the operation of 8-bit timer/event counter 50 first and then enable the timer f/f inversion operation (tmc501 = 1). ? pwm mode (tmc506 = 1) start the operation of 8-bit timer/event counter 50 fi rst and then set the count clock to make the duty = 50%. it is not necessary to enable the to50 pin as a timer output pin in any mode. caution make sure power60 = 0 wh en rewriting tps630 to tps600. remarks 1. f prs : peripheral hardware clock frequency 2. tmc506: bit 6 of 8-bit timer mode control register 50 (tmc50) tmc501: bit 1 of tmc50 chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 325 figure 14-14. format of clock se lection register 61 (cksr61) address: ff39h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 cksr61 0 0 0 0 tps631 tps621 tps611 tps601 base clock (f xclk6 ) selection tps631 tps621 tps611 tps601 f prs = 4 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz 0 0 0 0 f prs 4 mhz 5 mhz 10 mhz 20 mhz 0 0 0 1 f prs /2 2 mhz 2.5 mhz 5 mhz 10 mhz 0 0 1 0 f prs /2 2 1 mhz 1.25 mhz 2.5 mhz 5 mhz 0 0 1 1 f prs /2 3 500 khz 625 khz 1.25 mhz 2.5 mhz 0 1 0 0 f prs /2 4 250 khz 312.5 khz 625 khz 1.25 mhz 0 1 0 1 f prs /2 5 125 khz 156.25 khz 312.5 khz 625 khz 0 1 1 0 f prs /2 6 62.5 khz 78.13 khz 156.25 khz 312.5 khz 0 1 1 1 f prs /2 7 31.25 khz 39.06 khz 78.13 khz 156.25 khz 1 0 0 0 f prs /2 8 15.625 khz 19.53 khz 39.06 khz 78.13 khz 1 0 0 1 f prs /2 9 7.813 khz 9.77 khz 19.53 khz 39.06 khz 1 0 1 0 f prs /2 10 3.906 khz 4.88 khz 9.77 khz 19.53 khz 1 0 1 1 tm50 output note other than above setting prohibited note note the following points when selecting the tm50 output as the base clock. ? mode in which the count clock is cleared and started upon a match of tm50 and cr50 (tmc506 = 0) start the operation of 8-bit timer/event counter 50 first and then enable the timer f/f inversion operation (tmc501 = 1). ? pwm mode (tmc506 = 1) start the operation of 8-bit timer/event counter 50 fi rst and then set the count clock to make the duty = 50%. it is not necessary to enable the to50 pin as a timer output pin in any mode. caution make sure power61 = 0 wh en rewriting tps631 to tps601. remarks 1. f prs : peripheral hardware clock frequency 2. tmc506: bit 6 of 8-bit timer mode control register 50 (tmc50) tmc501: bit 1 of tmc50 chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 326 (5) baud rate generator cont rol register 6n (brgc6n) this register sets the division value of the 8- bit counters of serial in terface uart60 and uart61. brgc6n can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. remark brgc6n can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (power6n, txe6n) of asim6n = 1 or bits 7 and 5 (power6n, rxe6n) of asim6n = 1). figure 14-15. format of baud rate gene rator control register 60 (brgc60) address: ff57h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 brgc60 mdl670 mdl660 mdl650 mdl640 mdl630 mdl620 mdl610 mdl600 mdl670 mdl660 mdl650 mdl640 mdl630 mdl620 mdl610 mdl600 k output clock selection of 8-bit counter 0 0 0 0 0 0 setting prohibited 0 0 0 0 0 1 0 0 4 f xclk6 /4 0 0 0 0 0 1 0 1 5 f xclk6 /5 0 0 0 0 0 1 1 0 6 f xclk6 /6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 1 1 1 0 0 252 f xclk6 /252 1 1 1 1 1 1 0 1 253 f xclk6 /253 1 1 1 1 1 1 1 0 254 f xclk6 /254 1 1 1 1 1 1 1 1 255 f xclk6 /255 cautions 1. make sure that bit 6 (t xe60) and bit 5 (rxe60) of the asim6n register = 0 when rewriting the mdl670 to mdl600 bits. 2. the baud rate is the output clo ck of the 8-bit counter divided by 2. remarks 1. f xclk6 : frequency of base clock selected by the t ps630 to tps600 bits of cksr60 register 2. k: value set by mdl670 to mdl600 bits (k = 4, 5, 6, ..., 255) 3. : don?t care chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 327 figure 14-16. format of baud rate gene rator control register 61 (brgc61) address: ff3eh after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 brgc61 mdl671 mdl661 mdl651 mdl641 mdl631 mdl621 mdl611 mdl601 mdl671 mdl661 mdl651 mdl641 mdl631 mdl621 mdl611 mdl601 k output clock selection of 8-bit counter 0 0 0 0 0 0 setting prohibited 0 0 0 0 0 1 0 0 4 f xclk6 /4 0 0 0 0 0 1 0 1 5 f xclk6 /5 0 0 0 0 0 1 1 0 6 f xclk6 /6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 1 1 1 0 0 252 f xclk6 /252 1 1 1 1 1 1 0 1 253 f xclk6 /253 1 1 1 1 1 1 1 0 254 f xclk6 /254 1 1 1 1 1 1 1 1 255 f xclk6 /255 cautions 1. make sure that bit 6 (txe61) and bit 5 (r xe61) of the asim61 register = 0 when rewriting the mdl671 to mdl601 bits. 2. the baud rate is the output clo ck of the 8-bit counter divided by 2. remarks 1. f xclk6 : frequency of base clock selected by the tps631 to tps601 bits of cksr61 register 2. k: value set by mdl671 to mdl601 bits (k = 4, 5, 6, ..., 255) 3. : don?t care chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 328 (6) asynchronous serial interface control register 6n (asicl6n) this register controls the serial communication op erations of serial interface uart60 and uart61. asicl6n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 16h. caution asicl6n can be refreshed (the same value is written) by softwar e during a communication operation (when bits 7 and 6 (power6n, txe6n) of asim6n = 1 or bits 7 and 5 (power6n, rxe6n) of asim6n = 1). however, do not set both sbrt6n and sbtt6n to 1 by a refresh operation during sbf reception (sbrt6n = 1) or sbf transmission (until intst6n occurs since sbtt6n has been set (1)), because it may re-trigger sbf re ception or sbf transmission. figure 14-17. format of asynchronous serial interface control register 60 (asicl60) (1/2) address: ff58h after reset: 16h r/w note symbol <7> <6> 5 4 3 2 1 0 asicl60 sbrf60 sbrt60 sbtt60 sbl620 sbl610 sbl600 dir60 txdlv60 sbrf60 sbf reception status flag 0 if power60 = 0 and rxe60 = 0 or if sbf reception has been completed correctly 1 sbf reception in progress sbrt60 sbf reception trigger 0 ? 1 sbf reception trigger sbtt60 sbf transmission trigger 0 ? 1 sbf transmission trigger note bit 7 is read-only. chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 329 figure 14-17. format of asynchronous serial interface control register 60 (asicl60) (2/2) sbl620 sbl610 sbl600 sbf transmission output width control 1 0 1 sbf is output with 13-bit length. 1 1 0 sbf is output with 14-bit length. 1 1 1 sbf is output with 15-bit length. 0 0 0 sbf is output with 16-bit length. 0 0 1 sbf is output with 17-bit length. 0 1 0 sbf is output with 18-bit length. 0 1 1 sbf is output with 19-bit length. 1 0 0 sbf is output with 20-bit length. dir60 first-bit specification 0 msb 1 lsb txdlv60 enables/disables inverting t x d6n output 0 normal output of t x d60 1 inverted output of t x d60 cautions 1. in the case of an sbf reception error, the mode return s to the sbf reception mode. the status of the sbrf60 flag is held (1). 2. before setting the sbrt60 bit, make sure that bit 7 (power60) and bit 5 (rxe60) of asim60 = 1. after setting the sbrt60 bit to 1, do not cl ear it to 0 before sb f reception is completed (before an interrupt requ est signal is generated). 3. the read value of the sbrt60 bit is always 0. sbrt60 is automatically cleared to 0 after sbf reception has been co rrectly completed. 4. before setting the sbtt60 bit to 1, make su re that bit 7 (power60) and bit 6 (txe60) of asim60 = 1. after setting the sbtt 60 bit to 1, do not clear it to 0 before sbf transmission is completed (before an interrupt request signal is generated). 5. the read value of the sbtt60 bit is always 0. sbtt60 is automa tically cleared to 0 at the end of sbf transmission. 6. do not set the sbrt60 bit to 1 during recep tion, and do not set the sbtt60 bit to 1 during transmission. 7. before rewriting the dir60 and txdlv60 bits, clear the txe60 and rxe60 bits to 0. chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 330 figure 14-18. format of asynchronous serial interface control register 61 (asicl61) (1/2) address: ff3fh after reset: 16h r/w note symbol <7> <6> 5 4 3 2 1 0 asicl61 sbrf61 sbrt61 sbtt61 sbl621 sbl611 sbl601 dir61 txdlv61 sbrf61 sbf reception status flag 0 if power61 = 0 and rxe61 = 0 or if sbf reception has been completed correctly 1 sbf reception in progress sbrt61 sbf reception trigger 0 ? 1 sbf reception trigger sbtt61 sbf transmission trigger 0 ? 1 sbf transmission trigger note bit 7 is read-only. chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 331 figure 14-18. format of asynchronous serial interface control register 61 (asicl61) (2/2) sbl621 sbl611 sbl601 sbf transmission output width control 1 0 1 sbf is output with 13-bit length. 1 1 0 sbf is output with 14-bit length. 1 1 1 sbf is output with 15-bit length. 0 0 0 sbf is output with 16-bit length. 0 0 1 sbf is output with 17-bit length. 0 1 0 sbf is output with 18-bit length. 0 1 1 sbf is output with 19-bit length. 1 0 0 sbf is output with 20-bit length. dir61 first-bit specification 0 msb 1 lsb txdlv61 enables/disables inverting t x d6n output 0 normal output of t x d6n 1 inverted output of t x d6n cautions 1. in the case of an sbf reception error, the mode return s to the sbf reception mode. the status of the sbrf61 flag is held (1). 2. before setting the sbrt61 bit, make sure that bit 7 (power61) and bit 5 (rxe61) of asim61 = 1. after setting the sbrt61 bit to 1, do not cl ear it to 0 before sb f reception is completed (before an interrupt requ est signal is generated). 3. the read value of the sbrt61 bit is always 0. sbrt61 is automatically cleared to 0 after sbf reception has been co rrectly completed. 4. before setting the sbtt61 bit to 1, make su re that bit 7 (power61) and bit 6 (txe61) of asim61 = 1. after setting the sbtt 61 bit to 1, do not clear it to 0 before sbf transmission is completed (before an interrupt request signal is generated). 5. the read value of the sbtt61 bit is always 0. sbtt61 is automa tically cleared to 0 at the end of sbf transmission. 6. do not set the sbrt61 bit to 1 during recep tion, and do not set the sbtt61 bit to 1 during transmission. 7. before rewriting the dir61 and txdlv61 bits, clear the txe61 and rxe61 bits to 0. chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 332 (7) input switch control register (isc) the input switch control regi ster (isc) is used to receive a status si gnal transmitted from the master during lin (local interconnect network) reception. t he input source is switched by setting isc. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 14-19. format of input s witch control register (isc) address: ff4fh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 isc isc7 0 0 isc4 isc3 isc2 isc1 isc0 isc7 interrupt source selection 0 intwti 1 intdmu isc4 intp1 input source selection 0 intp1 (p30) 1 rxd61(p11) isc3 intp0 input source selection 0 intp0 (p120) 1 rxd60 (p14) isc2 ti001 input source selection 0 ti001 (p06) 1 rxd61(p11) isc1 ti010 input source selection 0 ti010 (p01) 1 rxd60 (p14) isc0 ti000 input source selection 0 ti000 (p00) 1 tsout chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 333 (8) port mode register 1 (pm1) this register sets port 1 input/output in 1-bit units. when using the p13/txd60 and p10/sck10/txd61 pins fo r serial interface data output, clear pm13 and pm10 to 0 and set the output latch of p13 and p10 to 1. when using the p14/rxd60 and p11/si10/rxd61 in for seri al interface data input, set pm14 and pm11 to 1. the output latch of p14 and p11 at this time may be 0 or 1. pm1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. figure 14-20. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 334 14.4 operations of serial interface uart60 and uart61 serial interfaces uart60 and ua rt61 have the following two modes. ? operation stop mode ? asynchronous serial interface (uart) mode 14.4.1 operation stop mode in this mode, serial communication cannot be executed; theref ore, the power consumption can be reduced. in addition, the pins can be used as ordinary po rt pins in this mode. to set the operation stop mode, clear bits 7, 6, and 5 (power6n, txe6n, and rxe6n) of asim6n to 0. (1) register used the operation stop mode is set by asynchronous serial interface operation mode register 6n (asim6n). asim6n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 01h. address: ff50h after reset: 01h r/w symbol <7> <6> <5> 4 3 2 1 0 asim6n power6n txe6n rxe6n ps61n ps60n cl6n sl6n isrm6n power6n enables/disables operati on of internal operation clock 0 note 1 disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit note 2 . txe6n enables/disables transmission 0 disables transmission o peration (synchronously resets the transmission circuit). rxe6n enables/disables reception 0 disables reception (synchronous ly resets the reception circuit). notes 1. the output of the t x d6n pins goes high and the input from the r x d6n pins is fixed to high level when power6n = 0. 2. asynchronous serial interface reception error st atus register 6n (asis6n), asynchronous serial interface transmission status register 6n (asif6n), bit 7 (sbrf6n) and bit 6 (sbrt6n) of asynchronous serial interface control register 6n (asicl6n), and receive buffer register 6n (rxb6n) are reset. caution clear power6n to 0 after clearing t xe6n and rxe6n to 0 to stop the operation. to start the communication, set power6n to 1, and then set txe6n and rxe6n to 1. remark 1. to use the rxd60/p14, rxd 61/p11/si10, txd60/p13 and txd 61/p10/sck10 pins as general- purpose port pins, see chapter 5 port functions . 2. n = 0, 1 chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 335 14.4.2 asynchronous serial interface (uart) mode in this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. a dedicated uart baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) registers used ? asynchronous serial interface operat ion mode register 6n (asim6n) ? asynchronous serial interface recepti on error status register 6n (asis6n) ? asynchronous serial interface transmi ssion status register 6n (asif6n) ? clock selection register 6n (cksr6n) ? baud rate generator control register 6n (brgc6n) ? asynchronous serial interface control register 6n (asicl6n) ? input switch control register (isc) ? port mode register 1 (pm1) ? port register 1 (p1) the basic procedure of setting an operatio n in the uart mode is as follows. <1> set the cksr6n register (see figure 14-13, 14-14 ). <2> set the brgc6n register (see figure 14-15, 14-16 ). <3> set bits 0 to 4 (isrm6n, sl6n, cl6n, ps60n, ps61n) of the asim6n register (see figure 14-7, 14-8 ). <4> set bits 0 and 1 (txdlv6n, dir 6n) of the asicl6n register (see figure 14-17, 14-18 ). <5> set bit 7 (power6n) of the asim6n register to 1. <6> set bit 6 (txe6n) of the asim6n register to 1. transmission is enabled. set bit 5 (rxe6n) of the asim6n register to 1. reception is enabled. <7> write data to transmit buffer register 6n (txb6n). data transmission is started. caution take relationship with the other party of communication when setting the port mode register and port register. remark n = 0, 1 chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 336 the relationship between the register settings and pins is shown below. table 14-2. relationship between register settings and pins (a) uart60 pin function power6n txe6n rxe6n pm13 p13 pm14 p14 uart60 operation txd60/p13 rxd60/p14 0 0 0 note note note note stop p13 p14 0 1 note note 1 reception p13 rxd60 1 0 0 1 note note transmission txd60 p14 1 1 1 0 1 1 transmission/ reception txd60 rxd60 (b) uart61 pin function power6n txe6n rxe6n pm10 p10 pm11 p11 uart61 operation txd61/p10/sck61 rxd61/p11/si10 0 0 0 note note note note stop p10 p11 0 1 note note 1 reception p10 rxd61 1 0 0 1 note note transmission txd61 p11 1 1 1 0 1 1 transmission/ reception txd61 rxd61 note can be set as port function. remarks 1. : don?t care power6n: bit 7 of asynchronous serial interface operation mode register 6n (asim6n) txe6n: bit 6 of asim6n rxe6n: bit 5 of asim6n pm1: port mode register p1: port output latch 2. n = 0, 1 chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 337 (2) communication operation (a) format and waveform example of normal transmit/receive data figures 14-21 and 14-22 show the format and waveform example of the normal transmit/receive data. figure 14-21. format of normal uart transmit/receive data 1. lsb-first transmission/reception start bit parity bit d0 d1 d2 d3 d4 1 data frame character bits d5 d6 d7 stop bit 2. msb-first transmission/reception start bit parity bit d7 d6 d5 d4 d3 1 data frame character bits d2 d1 d0 stop bit one data frame consists of the following bits. ? start bit ... 1 bit ? character bits ... 7 or 8 bits ? parity bit ... even parity, odd parity, 0 parity, or no parity ? stop bit ... 1 or 2 bits the character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 6n (asim6n). whether data is communicated with the lsb or msb first is specified by bit 1 (dir6) of asynchronous serial interface control register 6n (asicl6n). whether the t x d6n pins outputs normal or inverted data is s pecified by bit 0 (txdlv6) of asicl6n. remark n = 0, 1 chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 338 figure 14-22. example of normal uart transmit/receive data waveform 1. data length: 8 bits, lsb first, parity: even parity, stop bit: 1 bit, communication data: 55h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 parity stop 2. data length: 8 bits, msb first, parity: even parity, stop bit: 1 bit, communication data: 55h 1 data frame start d7 d6 d5 d4 d3 d2 d1 d0 parity stop 3. data length: 8 bits, msb first, parity: even parity, stop bit: 1 bit, communication data: 55h, t x d6n pin inverted output 1 data frame start d7 d6 d5 d4 d3 d2 d1 d0 parity stop 4. data length: 7 bits, lsb first, parity: o dd parity, stop bit: 2 bits, communication data: 36h 1 data frame start d0 d1 d2 d3 d4 d5 d6 parity stop stop 5. data length: 8 bits, lsb first, parity: none, stop bit: 1 bit, communication data: 87h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 stop remark n = 0, 1 chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 339 (b) parity types and operation the parity bit is used to detect a bit error in communicati on data. usually, the same type of parity bit is used on both the transmission and reception sides. with even parity and odd parity, a 1-bit (odd number) error can be detected. with zero parity and no parity, an error cannot be detected. caution fix the ps61n and ps60n bits to 0 wh en the device is used in lin communication operation. (i) even parity ? transmission transmit data, including the parity bit, is controlled so that the number of bits that are ?1? is even. the value of the parity bit is as follows. if transmit data has an odd number of bits that are ?1?: 1 if transmit data has an even number of bits that are ?1?: 0 ? reception the number of bits that are ?1? in the receive dat a, including the parity bit, is counted. if it is odd, a parity error occurs. (ii) odd parity ? transmission unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are ?1? is odd. if transmit data has an odd number of bits that are ?1?: 0 if transmit data has an even number of bits that are ?1?: 1 ? reception the number of bits that are ?1? in the receive data, including the parit y bit, is counted. if it is even, a parity error occurs. (iii) 0 parity the parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. the parity bit is not detected when the data is received. therefore, a parity error does not occur regardless of whether the parity bit is ?0? or ?1?. (iv) no parity no parity bit is appended to the transmit data. reception is performed assuming t hat there is no parity bit when data is received. because there is no parity bit, a parity error does not occur. remark n = 0, 1 chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 340 (c) normal transmission when bit 7 (power6n) of asynchronous serial interface operation mode register 6n (asim6n) is set to 1 and bit 6 (txe6n) of asim6n is then set to 1, transmissi on is enabled. transmission can be started by writing transmit data to transmit buffer register 6n (txb6n). the start bit, parity bit, and stop bit are automatically appended to the data. when transmission is started, the data in txb6n is transferred to transmit shift register 6n (txs6n). after that, the data is sequentially output from txs6n to the t x d6n pins. when transmission is completed, the parity and stop bits set by asim6n are appended and a transmission completion interrupt request (intst6n) is generated. transmission is stopped until the data to be tr ansmitted next is written to txb6n. figure 14-23 shows the timing of the transmission comp letion interrupt request (intst6n). this interrupt occurs as soon as the last stop bit has been output. figure 14-23. normal transmission comp letion interrupt request timing 1. stop bit length: 1 intst6n d0 start d1 d2 d6 d7 stop t x d6n (output) parity 2. stop bit length: 2 t x d6n (output) intst6n d0 start d1 d2 d6 d7 parity stop remark n = 0, 1 chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 341 (d) continuous transmission the next transmit data can be written to transmit buffer r egister 6n (txb6n) as soon as transmit shift register 6 (txs6n) has started its shift operat ion. consequently, even while the intst6n interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized. in addition, t he txb6n register can be efficiently wr itten twice (2 bytes) without having to wait for the transmission time of one data frame, by reading bit 0 (txsf6n) of asynchronous serial interface transmission status register 6n (asif6n) when the transmission completion interrupt has occurred. to transmit data continuously, be sure to reference the asif6n register to check t he transmission status and whether the txb6n register can be written, and then write the data. cautions 1. the txbf6n and txsf6n flags of the as if6n register change from ?10? to ?11?, and to ?01? during continuous transmission. to check the status, therefore, do not use a combination of the txbf6n a nd txsf6n flags for judgment. read only the txbf6n flag when executing continuous transmission. 2. when the device is used in li n communication operation, the continuous transmission function cannot be used. m ake sure that asynchronous serial interface transmission status register 6n (asif6n) is 00h before writing transmit data to transmit buffer register 6n (txb6n). txbf6n writing to txb6 register 0 writing enabled 1 writing disabled caution to transmit data continuously, wr ite the first transmit data (first byte) to the txb6n register. be sure to check that the txbf6n flag is ?0?. if so, write the next transmit data (second byte) to the txb6n register. if data is written to the txb6n regi ster while the txbf6n flag is ?1?, the transmit data cannot be guaranteed. the communication status can be checked using the txsf6n flag. txsf6n transmission status 0 transmission is completed. 1 transmission is in progress. cautions 1. to initialize the transmissi on unit upon completion of continuous transmission, be sure to check that the txsf6n flag is ?0? after generation of the transmission completion interrupt, and then execute initialization. if initialization is executed while the txsf6n flag is ?1?, the tran smit data cannot be guaranteed. 2. during continuous transmission, an overrun error may occur, which means that the next tran smission was completed before execution of intst6n interrupt servicing after transmission of one data frame. an overrun e rror can be detected by developing a program that can count the num ber of transmit data and by referencing the txsf6n flag. remark n = 0, 1 chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 342 figure 14-24 shows an example of the continuous transmission processing flow. figure 14-24. example of contin uous transmission processing flow write txb6n. set registers. write txb6n. transfer executed necessary number of times? yes read asif6n txbf6n = 0? no no yes transmission completion interrupt occurs? read asif6n txsf6n = 0? no no no yes yes yes yes completion of transmission processing transfer executed necessary number of times? remark txb6n: transmit buffer register 6n asif6n: asynchronous serial interfac e transmission status register 6n txbf6n: bit 1 of asif6n (transmit buffer data flag) txsf6n: bit 0 of asif6n (trans mit shift register data flag) n = 0, 1 chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 343 figure 14-25 shows the timing of starting continuous transmission, and figure 14-25 shows the timing of ending continuous transmission. figure 14-25. timing of starting continuous transmission t x d6n start intst6n data (1) data (1) data (2) data (3) data (2) data (1) data (3) ff ff parity stop data (2) parity stop txb6n txs6n txbf6n txsf6n start start note note when asif6n is read, there is a period in which txbf6n and txsf6n = 1, 1. therefore, judge whether writing is enabled us ing only the txbf6n bit. remark t x d6n: txd6n pins (output) intst6n: interrupt request signal txb6n: transmit buffer register 6n txs6n: transmit shift register 6n asif6n: asynchronous serial interfac e transmission status register 6n txbf6n: bit 1 of asif6n txsf6n: bit 0 of asif6n n = 0, 1 chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 344 figure 14-26. timing of ending continuous transmission t x d6n start intst6n data (n ? 1) data (n ? 1) data (n) data (n) data (n ? 1) ff parity stop stop data (n) parity stop txb6n txs6n txbf6n txsf6n power6n or txe6n start remark t x d6n: t x d6n pins (output) intst6n: interrupt request signal txb6n: transmit buffer register 6n txs6n: transmit shift register 6n asif6n: asynchronous serial interfac e transmission status register 6n txbf6n: bit 1 of asif6n txsf6n: bit 0 of asif6n power6n: bit 7 of asynchronous serial interface operation mode register (asim6n) txe6n: bit 6 of asynchronous serial in terface operation mode register (asim6n) n = 0, 1 chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 345 (e) normal reception reception is enabled and the r x d6n pins input is sampled when bit 7 (power6n) of asynchronous serial interface operation mode register 6n (asim6n) is set to 1 and then bit 5 (rxe6n) of asim6n is set to 1. the 8-bit counter of the baud ra te generator starts counting when the falling edge of the r x d6n pins input is detected. when the set value of baud rate generator control register 6n (brgc6n) has been counted, the r x d6n pins input is sampled again ( in figure 14-27). if the r x d6n pins are low level at this time, it is recognized as a start bit. when the start bit is detected, receptio n is started, and serial data is sequ entially stored in the receive shift register (rxs6n) at the set baud rate. when the st op bit has been received, the reception completion interrupt (intsr6n) is generated and t he data of rxs6n is written to receive buffer register 6n (rxb6n). if an overrun error (ove6n) occurs, however, the receive data is not written to rxb6n. even if a parity error (pe6n) occurs while reception is in progress, reception c ontinues to the reception position of the stop bit, and an error interrupt (intsr6n/in tsre6n) is generated on completion of reception. figure 14-27. reception completi on interrupt request timing r x d6n (input) intsr6n start d0 d1 d2 d3 d4 d5 d6 d7 parity rxb6n stop cautions 1. if a reception erro r occurs, read asis6n and then rxb6n to clear the error flag. otherwise, an overrun erro r will occur when the next data is received, and the reception error status will persist. 2. reception is always performed with the ?number of stop bits = 1?. the second stop bit is ignored. 3. be sure to read asynchronous serial inte rface reception error status register 6n (asis6n) before reading rxb6n. remark n = 0, 1 chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 346 (f) reception error three types of errors may occur during reception: a parity error, framing error, or ov errun error. if the error flag of asynchronous serial interface reception error st atus register 6n (asis6n) is set as a result of data reception, a reception error interrupt r equest (intsr6n/intsre6n) is generated. which error has occurred during reception can be id entified by reading the contents of asis6n in the reception error interrupt servicing (intsr6n/intsre6n) (see figure 14-9, 14-10 ). the contents of asis6n are cleared to 0 when asis6n is read. table 14-3. cause of reception error reception error cause parity error the parity specifi ed for transmission does not match the parity of the receive data. framing error stop bit is not detected. overrun error reception of the next data is completed before data is read from receive buffer register 6n (rxb6n). the error interrupt can be separated into reception completion interrupt (intsr6n) and error interrupt (intsre6n) by clearing bit 0 (isrm6n) of asynchr onous serial interface operation mode register 6n (asim6n) to 0. figure 14-28. reception error interrupt 1. if isrm6n is cleared to 0 (r eception completion interrupt (intsr6n ) and error interrupt (intsre6n) are separated) (a) no error during recepti on (b) error during reception intsr6n intsre6n intsr6n intsre6n 2. if isrm6n is set to 1 (error interrupt is incl uded in intsr6n) (a) no error during recepti on (b) error during reception intsre6n intsr6n intsre6n intsr6n remark n = 0, 1 chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 347 (g) noise filter of receive data the rxd6n signal?s is sampled with the bas e clock output by the prescaler block. if two sampled values are the same, the output of t he match detector changes, and the data is sampled as input data. because the circuit is configured as shown in figure 14- 29, the internal processing of the reception operation is delayed by two clocks from the external signal status. figure 14-29. noise filter circuit internal signal b internal signal a match detector in base clock r x d60/p14 rxd61/p11si10 q in ld_en q chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 348 (h) sbf transmission when the device is used in lin communication operati on, the sbf (synchronous break field) transmission control function is used for transmission. for the transmission operation of lin, see figure 14-1 lin transmission operation . when bit 7 (power6n) of asynchronous serial interface operation mode register 6n (asim6n) is set to 1 and bit 6 (txe6n) of asim6n is then set to 1, transmission is enabled. sbf transmission can be started by setting bit 5 (sbtt6n) of asynchronous serial interface control register 6n (asicl6n) to 1. thereafter, a low level of bits 13 to 20 (set by bi ts 4 to 2 (sbl62n to sbl60n) of asicl6n) is output. following the end of sbf transmission, the transmiss ion completion interrupt request (intst6n) is generated and sbtt6n is autom atically cleared. thereafter, t he normal transmission mode is restored. transmission is suspended until the data to be transmi tted next is written to transmit buffer register 6n (txb6n), or until sbtt6n is set to 1. remark n = 0, 1 figure 14-30. sbf transmission t x d6n intst6n sbtt6n 1 2 3 4 5 6 7 8 9 10 11 12 13 stop remark t x d6n: t x d6n pins (output) intst6n: transmission completion interrupt request sbtt6n: bit 5 of asynchronous serial interface control register 6n (asicl6n) n = 0, 1 chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 349 (i) sbf reception when the device is incorporated in lin, the sbf (synch ronous break field) recept ion control function is used for reception. for the re ception operation of lin, see figure 14-2 lin reception operation . reception is enabled when bit 7 (power6n) of asynchro nous serial interface operation mode register 6n (asim6n) is set to 1 and then bit 5 (rxe6n) of asim6n is set to 1. sbf reception is enabled when bit 6 (sbrt6n) of asynchronous serial interface control regist er 6n (asicl6n) is set to 1. in the sbf reception enabled status, the r x d6n pins are sampled and the start bit is det ected in the same manner as the normal reception enable status. when the start bit has been detected, reception is started, and serial data is sequentially stored in the receive shift register 6n (rxs6n) at the set baud rate. when the stop bit is received and if the width of sbf is 11 bits or more, a reception completion interrupt requ est (intsr6n) is generated as normal processing. at this time, the sbrf6n and sbrt6n bits are automatica lly cleared, and sbf reception ends. detection of errors, such as ove6n, pe6n, and fe6n (bits 0 to 2 of asynchronous serial interface reception error status register 6n (asis6n)) is suppressed, and error detection processing of uart communication is not performed. in addition, data transfer between receive sh ift register 6n (rxs6n) and receive buffer register 6n (rxb6n) is not performed, and the reset value of ffh is retained. if the width of sbf is 10 bits or less, an interrupt does not occur as error processing after the stop bit has been received, and the sbf reception mode is restored. in this case, the sbrf6n and sbrt6n bits are not cleared. figure 14-31. sbf reception 1. normal sbf reception (stop bit is detect ed with a width of more than 10.5 bits) r x d6n sbrt6n /sbrf6n intsr6n 1234567891011 2. sbf reception error (stop bit is detect ed with a width of 10.5 bits or less) r x d6n sbrt6n /sbrf6n intsr6n 12345678910 ?0? remark r x d6n: r x d6n pins (input) sbrt6n: bit 6 of asynchronous serial interface control register 6n (asicl6n) sbrf6n: bit 7 of asicl6n intsr6n: reception completion interrupt request n = 0, 1 chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 350 14.4.3 dedicated baud rate generator the dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of uart60 and uart61. separate 8-bit counters are provided for transmission and reception. (1) configuration of ba ud rate generator ? base clock the clock selected by bits 3 to 0 (tps63n to tps60n) of clock selection register 6n (cksr6n) is supplied to each module when bit 7 (power6n) of asynchronous seri al interface operation mode register 6n (asim6n) is 1. this clock is called the base clock and its frequency is called f xclk6 . the base clock is fixed to low level when power6n = 0. ? transmission counter this counter stops operation, cleared to 0, when bi t 7 (power6n) or bit 6 (txe6n) of asynchronous serial interface operation mode regi ster 6n (asim6n) is 0. it starts counting when power6n = 1 and txe6n = 1. the counter is cleared to 0 when the first data transmi tted is written to transmit buffer register 6n (txb6n). if data are continuously transmitted, the counter is cleared to 0 agai n when one frame of data has been completely transmitted. if there is no data to be transmitted next, the count er is not cleared to 0 and continues counting until power6n or txe6n is cleared to 0. ? reception counter this counter stops operation, cleared to 0, when bit 7 (power6n) or bit 5 (rxe6n) of asynchronous serial interface operation mode regi ster 6n (asim6n) is 0. it starts counting when the start bit has been detected. the counter stops operation after one frame has been received, until the next start bit is detected. remark n = 0, 1 chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 351 figure 14-32. configuration of baud rate generator selector power6n 8-bit counter match detector baud rate baud rate generator brgc6n: mdl67n to mdl60n 1/2 power6n, txe6n (or rxe6n) cksr6n: tps63n to tps60n f prs f prs /2 f prs /2 2 f prs /2 3 f prs /2 4 f prs /2 5 f prs /2 6 f prs /2 7 f prs /2 8 f prs /2 9 f prs /2 10 8-bit timer/ event counter 50 output f xclk6 remark power6n: bit 7 of asynchronous serial in terface operation mode register 6n (asim6n) txe6n: bit 6 of asim6n rxe6n: bit 5 of asim6n cksr6n: clock selection register 6n brgc6n: baud rate generator control register 6n n = 0, 1 (2) generation of serial clock a serial clock can be generated by using clock selecti on register 6n (cksr6n) and baud rate generator control register 6n (brgc6n). select the clock to be input to the 8-bit counter by using bits 3 to 0 (tps63n to tps60n) of cksr6n. bits 7 to 0 (mdl67n to mdl60n) of brgc6n can be used to select the division value of the 8-bit counter. (a) baud rate the baud rate can be calculated by the following expression. ? baud rate = [bps] f xclk6 : frequency of base clock selected by tps 63n to tps60n bits of cksr6n register k: value set by mdl67n to mdl60n bits of brgc6n register (k = 4, 5, 6, ..., 255) (b) error of baud rate the baud rate error can be calculated by the following expression. ? error (%) = ? 1 100 [%] actual baud rate (baud rate with error) desired baud rate (correct baud rate) f xclk6 2 k chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 352 cautions 1. keep the baud rate error during tran smission to within the permi ssible error range at the reception destination. 2. make sure that the baud rate error dur ing reception satisfies the range shown in (4) permissible baud rate ra nge during reception. example : frequency of base clock = 10 mhz = 10,000,000 hz set value of mdl67n to mdl60n bits of brgc6 register = 00100001b (k = 33) target baud rate = 153600 bps baud rate = 10 m/(2 33) = 10000000/(2 33) = 151,515 [bps] error = (151515/153600 ? 1) 100 = ? 1.357 [%] (3) example of setting baud rate table 14-4. set data of baud rate generator f prs = 5.0 mhz f prs = 10.0 mhz f prs = 20.0 mhz baud rate [bps] tps63n, tps60n k calculated value err [%] tps63n, tps60n k calculated value err [%] tps63n, tps60n k calculated value err [%] 300 7h 65 301 0.16 8h 65 301 0.16 9h 65 301 0.16 600 6h 65 601 0.16 7h 65 601 0.16 8h 65 601 0.16 1200 5h 65 1202 0.16 6h 65 1202 0.16 7h 65 1202 0.16 2400 4h 65 2404 0.16 5h 65 2404 0.16 6h 65 2404 0.16 4800 3h 65 4808 0.16 4h 65 4808 0.16 5h 65 4808 0.16 9600 2h 65 9615 0.16 3h 65 9615 0.16 4h 65 9615 0.16 19200 1h 65 19231 0.16 2h 65 19231 0.16 3h 65 19231 0.16 24000 3h 13 24038 0.16 4h 13 24038 0.16 5h 13 24038 0.16 31250 4h 5 31250 0 5h 5 31250 0 6h 5 31250 0 38400 0h 65 38462 0.16 1h 65 38462 0.16 2h 65 38462 0.16 48000 2h 13 48077 0.16 3h 13 48077 0.16 4h 13 48077 0.16 76800 0h 33 75758 ? 1.36 0h 65 76923 0.16 1h 65 76923 0.16 115200 1h 11 113636 ? 1.36 0h 43 116279 0.94 0h 87 114943 ? 0.22 153600 1h 8 156250 1.73 0h 33 151515 ? 1.36 1h 33 151515 ? 1.36 312500 0h 8 312500 0 1h 8 312500 0 2h 8 312500 0 625000 0h 4 625000 0 1h 4 625000 0 2h 4 625000 0 remark tps63n to tps60n: bits 3 to 0 of clock se lection register 6n (cksr6n) (setting of base clock (f xclk6 )) k: value set by mdl67n to mdl60n bits of baud rate generator control register 6n (brgc6n) (k = 4, 5, 6, ..., 255) f prs : peripheral hardware clock frequency err: baud rate error n = 0, 1 chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 353 (4) permissible baud rate range during reception the permissible error from the baud rate at the trans mission destination during reception is shown below. caution make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. figure 14-33. permissible baud rate range during reception fl 1 data frame (11 fl) flmin flmax data frame lengtz of uart60 and uart61 start bit bit 0 bit 1 bit 7 parity bit minimum permissible data frame length maximum permissible data frame length stop bit start bit bit 0 bit 1 bit 7 parity bit latch timing stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 14-33, the latch timing of the re ceive data is determined by t he counter set by baud rate generator control register 6n (brgc6n) after the start bit has been detected. if the last data (stop bit) meets this latch timing, the data can be correctly received. assuming that 11-bit data is received, the theoretical values can be calculated as follows. fl = (brate) ? 1 brate: baud rate of uart60 and uart61 k: set value of brgc6n fl: 1-bit data length margin of latch timing: 2 clocks remark n = 0, 1 chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 354 minimum permissible data frame length: flmin = 11 fl ? fl = fl therefore, the maximum receivable baud rate at the transmission destination is as follows. brmax = (flmin/11) ? 1 = brate similarly, the maximum permissible data fr ame length can be calculated as follows. 10 k + 2 21k ? 2 11 2 k 2 k flmax = fl 11 therefore, the minimum receivable baud rate at the transmission destination is as follows. brmin = (flmax/11) ? 1 = brate the permissible baud rate error between uart60 and uart61 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. table 14-5. maximum/minimum permissible baud rate error division ratio (k) maximum perm issible baud rate error minimu m permissible baud rate error 4 +2.33% ? 2.44% 8 +3.53% ? 3.61% 20 +4.26% ? 4.31% 50 +4.56% ? 4.58% 100 +4.66% ? 4.67% 255 +4.72% ? 4.73% remarks 1. the permissible error of reception depends on t he number of bits in one frame, input clock frequency, and division ratio (k). the higher the input clock frequency and the higher the division ratio (k), the higher the permissible error. 2. k: set value of brgc6n 3. n = 0, 1 22k 21k + 2 flmax = 11 fl ? fl = fl 21k ? 2 20k 20k 21k ? 2 k ? 2 2k 21k + 2 2k chapter 14 serial interfaces uart60 and uart61 user?s manual u17553ej4v0ud 355 (5) data frame length during continuous transmission when data is continuously transmitted, th e data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. howeve r, the result of communica tion is not affected because the timing is initialized on the recepti on side when the start bit is detected. figure 14-34. data frame length during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame fl fl fl fl fl fl flstp start bit of second byte start bit bit 0 where the 1-bit data length is fl, the stop bit length is flstp, and base clock frequency is f xclk6 , the following expression is satisfied. flstp = fl + 2/f xclk6 therefore, the data frame length during continuous transmission is: data frame length = 11 fl + 2/f xclk6 user?s manual u17553ej4v0ud 356 chapter 15 serial interfaces csi10 and csi11 the 78k0/ff2 incorporate serial interfaces csi10 and csi11. 15.1 functions of serial interfaces csi10 and csi11 serial interfaces csi10 and csi11 have the following two modes. ? operation stop mode ? 3-wire serial i/o mode (1) operation stop mode this mode is used when serial communication is not performed and can enable a reduction in the power consumption. for details, see 15.4.1 operation stop mode . (2) 3-wire serial i/o mode (ms b/lsb-first selectable) this mode is used to communicate 8-bit data using three lines: a serial clock line (sck1n) and two serial data lines (si1n and so1n). the processing time of data communication can be s hortened in the 3-wire serial i/o mode because transmission and reception can be simultaneously executed. in addition, whether 8-bit data is communicated with the msb or lsb first can be specified, so this interface can be connected to any device. the 3-wire serial i/o mode is used for connecting periphe ral ics and display controllers with a clocked serial interface. for details, see 15.4.2 3-wire serial i/o mode . remark n = 0, 1 chapter 15 serial interfaces csi10 and csi11 user?s manual u17553ej4v0ud 357 15.2 configuration of serial interfaces csi10 and csi11 serial interfaces csi10 and csi11 include the following hardware. table 15-1. configuration of serial interfaces csi10 and csi11 item configuration controller transmit controller clock start/stop controller & clock phase controller registers transmit buffer register 1n (sotb1n) serial i/o shift re gister 1n (sio1n) control registers serial operation mode register 1n (csim1n) serial clock selection register 1n (csic1n) port mode register 1 (pm1) or port mode register 7 (pm7), port mode register 0 (pm0) port register 1 (p1) or port register 7 (p7), port mode register 0 (p0) remark n = 0, 1 figure 15-1. block diagram of serial interface csi10 sck10/p10/txd61 internal bus si10/p11/r x d61 intcsi10 f prs /2 f prs /2 2 f prs /2 3 f prs /2 4 f prs /2 5 f prs /2 6 f prs /2 7 transmit buffer register 10 (sotb10) transmit controller clock start/stop controller & clock phase controller serial i/o shift register 10 (sio10) output selector so10/p12 output latch 8 transmit data controller 8 output latch (p12) pm12 selector (a) baud rate generator output latch (p10) pm10 remark (a): so10 output chapter 15 serial interfaces csi10 and csi11 user?s manual u17553ej4v0ud 358 figure 15-2. block diagram of serial interface csi11 8 8 internal bus output selector output latch transmit controller clock start/stop controller & clock phase controller so11/p74 intcsi11 transmit buffer register 11 (sotb11) transmit data controller si11/p75 serial i/o shift register 11 (sio11) f prs /2 f prs /2 2 f prs /2 3 f prs /2 4 f prs /2 5 f prs /2 6 f prs /2 7 ssi11 output latch (p74) pm74 selector (a) baud rate generator output latch (p04) pm04 sck11/p76 ssi11 remark (a): so11 output (1) transmit buffer register 1n (sotb1n) this register sets the transmit data. transmission/reception is started by wr iting data to sotb1n when bit 7 (csie 1n) and bit 6 (trmd1n) of serial operation mode register 1n (csim1n) is 1. the data written to sotb1n is converted from parallel data into serial data by serial i/o shift register 1n, and output to the serial output pin (so1n). sotb1n can be written or read by an 8- bit memory manipulation instruction. reset signal generation clears this register to 00h. cautions 1. do not access sotb1n when cs ot1n = 1 (during serial communication). 2. in the slave mode, transmi ssion/reception is started when da ta is written to sotb11 with a low level input to the ssi11 pin. for deta ils of the transmissi on/reception operation, see 15.4.2 (2) communication operation. (2) serial i/o shift register 1n (sio1n) this is an 8-bit register that converts data from parallel data into serial data and vice versa. this register can be read by an 8-bit memory manipulation instruction. reception is started by reading data fr om sio1n if bit 6 (trmd1n) of serial operation mode register 1n (csim1n) is 0. during reception, the data is read from the serial input pin (si1n) to sio1n. reset signal generation clears this register to 00h. cautions 1. do not access sio1n when cs ot1n = 1 (during serial communication). 2. in the slave mode, reception is started when data is read from sio11 with a low level input to the ssi11 pin. for details of the recep tion operation, see 15.4.2 (2) communication operation. remark n = 0, 1 chapter 15 serial interfaces csi10 and csi11 user?s manual u17553ej4v0ud 359 15.3 registers controlling seri al interfaces csi10 and csi11 serial interfaces csi10 and csi11 are cont rolled by the following four registers. ? serial operation mode register 1n (csim1n) ? serial clock selection register 1n (csic1n) ? port mode register 1 (pm1) or port mode re gister 7 (pm7), port mode register 0 (pm0) ? port register 1 (p1) or port regist er 7 (p7), port mode register 0(p0) (1) serial operation mode register 1n (csim1n) csim1n is used to select the operation m ode and enable or disable operation. csim1n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. remark n = 0, 1 figure 15-3. format of serial oper ation mode register 10 (csim10) address: ff80h after reset: 00h r/w note 1 symbol <7> 6 5 4 3 2 1 0 csim10 csie10 trmd10 0 dir10 0 0 0 csot10 csie10 operation control in 3-wire serial i/o mode 0 disables operation note 2 and asynchronously resets the internal circuit note 3 . 1 enables operation trmd10 note 4 transmit/receive mode control 0 note 5 receive mode (transmission disabled). 1 transmit/receive mode dir10 note 6 first bit specification 0 msb 1 lsb csot10 communication status flag 0 communication is stopped. 1 communication is in progress. notes 1. bit 0 is a read-only bit. 2. to use p10/sck10/t x d61 and p12/so10 as general-purpose ports , set csim10 in the default status (00h). 3. bit 0 (csot10) of csim10 and serial i/o shift register 10 (sio10) are reset. 4. do not rewrite trmd10 when csot10 = 1 (during serial communication). 5. the so10 output (see (a) in figure 15-1 ) is fixed to the low level when trmd10 is 0. reception is started when data is read from sio10. 6. do not rewrite dir10 when csot10 = 1 (during serial communication). caution be sure to clear bit 5 to 0. chapter 15 serial interfaces csi10 and csi11 user?s manual u17553ej4v0ud 360 figure 15-4. format of serial oper ation mode register 11 (csim11) address: ff88h after reset: 00h r/w note 1 symbol <7> 6 5 4 3 2 1 0 csim11 csie11 trmd11 sse11 dir11 0 0 0 csot11 csie11 operation control in 3-wire serial i/o mode 0 disables operation note 2 and asynchronously resets the internal circuit note 3 . 1 enables operation trmd11 note 4 transmit/receive mode control 0 note 5 receive mode (transmission disabled). 1 transmit/receive mode sse11 notes 6, 7 ssi11 pin use selection 0 ssi11 pin is not used 1 ssi11 pin is used dir11 note 8 first bit specification 0 msb 1 lsb csot11 communication status flag 0 communication is stopped. 1 communication is in progress. notes 1. bit 0 is a read-only bit. 2. to use p74/so11, p76/sck11, and p05/ssi11/ti001 as general-pur pose ports, set csim11 in the default status (00h). 3. bit 0 (csot11) of csim11 and serial i/o shift register 11 (sio11) are reset. 4. do not rewrite trmd11 when csot11 = 1 (during serial communication). 5. the so11 output (see (a) in figure 15-2 ) is fixed to the low level when trmd11 is 0. reception is started when data is read from sio11. 6. do not rewrite sse11 when csot11 = 1 (during serial communication). 7. before setting this bit to 1, fix the ssi11 pin input level to 0 or 1. 8. do not rewrite dir11 when csot11 = 1 (during serial communication). chapter 15 serial interfaces csi10 and csi11 user?s manual u17553ej4v0ud 361 (2) serial clock selecti on register 1n (csic1n) this register specifies the timing of the data transmission/reception and sets the serial clock. csic1n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. remark n = 0, 1 figure 15-5. format of serial clo ck selection register 10 (csic10) address: ff81h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 csic10 0 0 0 ckp10 dap10 cks102 cks101 cks100 ckp10 dap10 specification of data transmission/reception timing type 0 0 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 3 1 1 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 4 csi10 serial clock selection cks102 cks101 cks100 f prs = 4 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz mode 0 0 0 f prs /2 2 mhz 2.5 mhz 5 mhz 10 mhz 0 0 1 f prs /2 2 1 mhz 1.25 mhz 2.5 mhz 5 mhz 0 1 0 f prs /2 3 500 khz 625 khz 1.25 mhz 2.5 mhz 0 1 1 f prs /2 4 250 khz 312.5 khz 625 khz 1.25 mhz 1 0 0 f prs /2 5 125 khz 156.25 khz 312.5 khz 625 khz 1 0 1 f prs /2 6 62.5 khz 78.13 khz 156.25 khz 312.5 khz 1 1 0 f prs /2 7 31.25 khz 39.06 khz 78.13 khz 156.25 khz master mode 1 1 1 external clock input to sck10 slave mode cautions 1. do not write to csic10 while csie10 = 1 (operation enabled). 2. to use p10/sck10/t x d61 and p12/so10 as general-purpose por ts, set csic10 in the default status (00h). 3. the phase type of the data clock is type 1 after reset. remark f prs : peripheral hardware clock frequency chapter 15 serial interfaces csi10 and csi11 user?s manual u17553ej4v0ud 362 figure 15-6. format of serial clo ck selection register 11 (csic11) address: ff89h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 csic11 0 0 0 ckp11 dap11 cks112 cks111 cks110 ckp11 dap11 specification of data transmission/reception timing type 0 0 d7 d6 d5 d4 d3 d2 d1 d0 sck11 so11 si11 input timing 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 sck11 so11 si11 input timing 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 sck11 so11 si11 input timing 3 1 1 d7 d6 d5 d4 d3 d2 d1 d0 sck11 so11 si11 input timing 4 csi11 serial clock selection cks112 cks111 cks110 f prs = 4 mhz f prs = 5 mhz f prs = 10 mhz f prs = 20 mhz mode 0 0 0 f prs /2 2 mhz 2.5 mhz 5 mhz 10 mhz 0 0 1 f prs /2 2 1 mhz 1.25 mhz 2.5 mhz 5 mhz 0 1 0 f prs /2 3 500 khz 625 khz 1.25 mhz 2.5 mhz 0 1 1 f prs /2 4 250 khz 312.5 khz 625 khz 1.25 mhz 1 0 0 f prs /2 5 125 khz 156.25 khz 312.5 khz 625 khz 1 0 1 f prs /2 6 62.5 khz 78.13 khz 156.25 khz 312.5 khz 1 1 0 f prs /2 7 31.25 khz 39.06 khz 78.13 khz 156.25 khz master mode 1 1 1 external clock input to sck11 slave mode cautions 1. do not write to csic11 while csie11 = 1 (operation enabled). 2. to use p74/so11 and p76/sck11 as general- purpose ports, set csic11 in the default status (00h). 3. the phase type of the data clock is type 1 after reset. remark f prs : peripheral hardware clock frequency chapter 15 serial interfaces csi10 and csi11 user?s manual u17553ej4v0ud 363 (3) port mode registers 0, 1 and 7 (pm0, pm1, pm7) these registers set port 0, 1 and 7 input/output in 1-bit units. when using p10/sck10 and p76/sck11 as the clock output pins of the serial interface, clear pm10 and pm76, and the output latches of p10 and p76 to 1. when using p12/so10 and p74/so11 as the data output pins of the serial inte rface, clear pm12, pm74, p12 and p74 to 0. when using p10/sck10/txd61 and p76/sck11 as the clock input pins of the serial interface, p11/si10/rxd61 and p75/si11 as the data input pins, an d p05/ssi11/ti001 as the chip select input pin, set pm10, pm76, pm11, pm75 and pm05 to 1. at this time, the output latches of p10, p76, p11, p75 and p05 may be 0 or 1. pm0, pm1 and pm7 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets these registers to ffh. figure 15-7. format of port mode register 0 (pm0) address: ff20h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm0 1 pm06 pm05 1 1 1 pm01 pm00 pm0n p0n pin i/o mode selection (n = 0, 1, 5, 6) 0 output mode (output buffer on) 1 input mode (output buffer off) figure 15-8. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) figure 15-9. format of port mode register 7 (pm7) address: ff2ch after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm7 1 pm76 pm75 pm74 pm73 pm72 pm71 pm70 pm7n p7n pin i/o mode selection (n = 0 to 6) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 15 serial interfaces csi10 and csi11 user?s manual u17553ej4v0ud 364 15.4 operation of serial interfaces csi10 and csi11 serial interfaces csi10 and csi11 can be used in the following two modes. ? operation stop mode ? 3-wire serial i/o mode 15.4.1 operation stop mode serial communication is not executed in this mode. therefore, the power consumption can be reduced. in addition, the p10/sck10/t x d61, p11/si10/r x d61, p12/so10, p74/so11, p75/si 11, and p76/sck11 pins can be used as ordinary i/o port pins in this mode. (1) register used the operation stop mode is set by serial operation mode register 1n (csim1n). to set the operation stop mode, clear bit 7 (csie1n) of csim1n to 0. (a) serial operation mode register 1n (csim1n) csim1n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears csim1n to 00h. remark n = 0, 1 ? serial operation mode register 10 (csim10) address: ff80h after reset: 00h r/w symbol <7> 6 5 4 3 2 1 0 csim10 csie10 trmd10 0 dir10 0 0 0 csot10 csie10 operation control in 3-wire serial i/o mode 0 disables operation note 1 and asynchronously resets the internal circuit note 2 . notes 1. to use p10/sck10/t x d61 and p12/so10 as general-purpose ports, set csim10 in the default status (00h). 2. bit 0 (csot10) of csim10 and serial i/o shift register 10 (sio10) are reset. ? serial operation mode register 11 (csim11) address: ff88h after reset: 00h r/w symbol <7> 6 5 4 3 2 1 0 csim11 csie11 trmd11 sse11 dir11 0 0 0 csot11 csie11 operation control in 3-wire serial i/o mode 0 disables operation note 1 and asynchronously resets the internal circuit note 2 . notes 1. to use p74/so11, p76/sck 11, and p05/ssi11/ti001 as general-purpose ports, set csim11 in the default status (00h). 2. bit 0 (csot11) of csim11 and serial i/o shift register 11 (sio11) are reset. chapter 15 serial interfaces csi10 and csi11 user?s manual u17553ej4v0ud 365 15.4.2 3-wire serial i/o mode the 3-wire serial i/o mode is used for connecting peripheral ics and display controll ers with a clocked serial interface. in this mode, communication is executed by using three lin es: the serial clock (sck1n), serial output (so1n), and serial input (si1n) lines. (1) registers used ? serial operation mode register 1n (csim1n) ? serial clock selection register 1n (csic1n) ? port mode register 1 (pm1) or port mode register 7 (pm7) ? port register 1 (p1) or port register 7 (p7) the basic procedure of setting an operation in the 3-wire se rial i/o mode is as follows. <1> set the csic1n register (see figures 15-5 and 15-6 ). <2> set bits 0 and 4 to 6 (csot1n, dir1n, sse11 (ser ial interface csi11 only), and trmd1n) of the csim1n register (see figures 15-3 and 15-4 ). <3> set bit 7 (csie1n) of the csim1n register to 1. transmission/reception is enabled. <4> write data to transmit buffer register 1n (sotb1n). data transmission/reception is started. read data from serial i/o shift register 1n (sio1n). data reception is started. caution take relationship with the other party of co mmunication when setting the port mode register and port register. remark n = 0, 1 chapter 15 serial interfaces csi10 and csi11 user?s manual u17553ej4v0ud 366 the relationship between the register settings and pins is shown below. table 15-2. relationship between register settings and pins (1/2) (a) serial interface csi10 pin function csie10 trmd10 pm11 p11 pm12 p12 pm10 p10 csi10 operation si10/rxd61/ p11 so10/p12 sck10/txd61/ p10 0 note 1 note 1 note 1 note 1 note 1 note 1 stop rxd61/ p11 p12 txd61/ p10 note 2 1 0 1 note 1 note 1 1 slave reception note 3 si10 p12 sck10 (input) note 3 1 1 note 1 note 1 0 0 1 slave transmission note 3 rxd61/ p11 so10 sck10 (input) note 3 1 1 1 0 0 1 slave transmission/ reception note 3 si10 so10 sck10 (input) note 3 1 0 1 note 1 note 1 0 1 master reception si10 p12 sck10 (output) 1 1 note 1 note 1 0 0 0 1 master transmission rxd61/ p11 so10 sck10 (output) 1 1 1 0 0 0 1 master transmission/ reception si10 so10 sck10 (output) notes 1. can be set as port function. 2. to use p10/sck10/txd61 as port pins, clear ckp10 to 0. 3. to use the slave mode, set cks102, cks101, and cks100 to 1, 1, 1. remark : don?t care csie10: bit 7 of serial operation mode register 10 (csim10) trmd10: bit 6 of csim10 ckp10: bit 4 of serial clock selection register 10 (csic10) cks102, cks101, cks100: bits 2 to 0 of csic10 pm1: port mode register p1: port output latch chapter 15 serial interfaces csi10 and csi11 user?s manual u17553ej4v0ud 367 table 15-2. relationship between register settings and pins (2/2) (b) serial interface csi11 pin function csie11 trmd11 sse11 pm75 p75 pm74 p74 pm76 p76 pm05 p05 csi11 operation si11/ p75 so11/ p74 sck11/ p76 ssi11/ ti001/p05 0 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 stop p75 p74 p76 note 2 ti001/ p05 0 note 1 note 1 ti001/ p05 1 0 1 1 note 1 note 1 1 1 slave reception note 3 si11 p74 sck11 (input) note 3 ssi11 0 note 1 note 1 ti001/ p05 1 1 1 note 1 note 1 0 0 1 1 slave transmission note 3 p75 so11 sck11 (input) note 3 ssi11 0 note 1 note 1 ti001/ p05 1 1 1 1 0 0 1 1 slave transmission/ reception note 3 si11 so11 sck11 (input) note 3 ssi11 1 0 0 1 note 1 note 1 0 1 note 1 note 1 master reception si11 p74 sck11 (output) ti001/ p05 1 1 0 note 1 note 1 0 0 0 1 note 1 note 1 master transmission p75 so11 sck11 (output) ti001/ p05 1 1 0 1 0 0 0 1 note 1 note 1 master transmission/ reception si11 so11 sck11 (output) ti001/ p05 notes 1. can be set as port function. 2. to use p76/sck11 as port pins, clear ckp11 to 0. 3. to use the slave mode, set cks112, cks111, and cks110 to 1, 1, 1. remark : don?t care csie11: bit 7 of serial operation mode register 11 (csim11) trmd11: bit 6 of csim11 ckp11: bit 4 of serial clock selection register 11 (csic11) cks112, cks111, cks110: bits 2 to 0 of csic11 pm7: port mode register 7 p7: port 7 output latch pm05: port mode register 05 p05: port 05 output latch chapter 15 serial interfaces csi10 and csi11 user?s manual u17553ej4v0ud 368 (2) communication operation in the 3-wire serial i/o mode, data is tr ansmitted or received in 8-bit units. each bit of the dat a is transmitted or received in synchronization with the serial clock. data can be transmitted or received if bit 6 (trmd1n) of serial operation mode register 1n (csim1n) is 1. transmission/reception is started when a value is writt en to transmit buffer register 1n (sotb1n). in addition, data can be received when bit 6 (trmd1n) of seri al operation mode register 1n (csim1n) is 0. reception is started when dat a is read from serial i/o shift register 1n (sio1n). however, communication is performed as follows if bit 5 (s se11) of csim11 is 1 when serial interface csi11 is in the slave mode. <1> low level input to the ssi11 pin transmission/reception is started when sotb11 is writt en, or reception is star ted when sio11 is read. <2> high level input to the ssi11 pin transmission/reception or reception is held, therefore, even if sotb11 is written or sio11 is read, transmission/reception or rece ption will not be started. <3> data is written to sotb11 or data is read from sio 11 while a high level is input to the ssi11 pin, then a low level is input to the ssi11 pin transmission/reception or reception is started. <4> a high level is input to the ssi11 pi n during transmission/reception or reception transmission/reception or reception is suspended. after communication has been started, bit 0 (csot1n) of csim1n is set to 1. when communication of 8-bit data has been completed, a communication completion interrupt request flag (csiif1n) is set, and csot1n is cleared to 0. then the next communication is enabled. cautions 1. do not access the cont rol register and data register when csot1n = 1 (during serial communication). 2. when using serial interface csi11, wait fo r the duration of at least one clock before the clock operation is started to change the level of the ssi11 pin in the slave mode; otherwise, malfunctioning may occur. remark n = 0, 1 chapter 15 serial interfaces csi10 and csi11 user?s manual u17553ej4v0ud 369 figure 15-10. timing in 3-wire serial i/o mode (1/2) (1) transmission/reception timing (t ype 1; trmd1n = 1, dir1n = 0, ckp1n = 0, dap1n = 0, sse11 = 1 note ) aah abh 56h adh 5ah b5h 6ah d5h 55h (communication data) 55h is written to sotb1n. sck1n sotb1n sio1n csot1n csiif1n so1n si1n (receive aah) read/write trigger intcsi1n ssi11 note note the sse11 flag and ssi11 pin are available only for serial interface csi11, and are used in the slave mode. remark n = 0, 1 chapter 15 serial interfaces csi10 and csi11 user?s manual u17553ej4v0ud 370 figure 15-10. timing in 3-wire serial i/o mode (2/2) (2) transmission/reception timing (t ype 2; trmd1n = 1, dir1n = 0, ckp1n = 0, dap1n = 1, sse11 = 1 note ) abh 56h adh 5ah b5h 6ah d5h sck1n sotb1n sio1n csot1n csiif1n so1n si1n (input aah) aah 55h (communication data) 55h is written to sotb1n. read/write trigger intcsi1n ssi11 note note the sse11 flag and ssi11 pin are available only for serial interface csi11, and are used in the slave mode. remark n = 0, 1 chapter 15 serial interfaces csi10 and csi11 user?s manual u17553ej4v0ud 371 figure 15-11. timing of clock/data phase (a) type 1; ckp1n = 0, dap1n = 0, dir1n = 0 d7 d6 d5 d4 d3 d2 d1 d0 sck1n so1n writing to sotb1n or reading from sio1n si1n capture csiif1n csot1n (b) type 2; ckp1n = 0, dap1n = 1, dir1n = 0 d7 d6 d5 d4 d3 d2 d1 d0 sck1n so1n writing to sotb1n or reading from sio1n si1n capture csiif1n csot1n (c) type 3; ckp1n = 1, dap1n = 0, dir1n = 0 d7 d6 d5 d4 d3 d2 d1 d0 sck1n so1n writing to sotb1n or reading from sio1n si1n capture csiif1n csot1n (d) type 4; ckp1n = 1, dap1n = 1, dir1n = 0 d7 d6 d5 d4 d3 d2 d1 d0 sck1n so1n writing to sotb1n or reading from sio1n si1n capture csiif1n csot1n remarks 1. the above figure illustrates a communication operation where data is transmitted with the msb first. 2. n = 0, 1 chapter 15 serial interfaces csi10 and csi11 user?s manual u17553ej4v0ud 372 (3) timing of output to so1n pin (first bit) when communication is started, the value of transmit buffe r register 1n (sotb1n) is output from the so1n pin. the output operation of the first bit at this time is described below. figure 15-12. output operation of first bit (1/2) (a) type 1: ckp1n = 0, dap1n = 0 sck1n sotb1n sio1n so1n writing to sotb1n or reading from sio1n first bit 2nd bit output latch (b) type 3: ckp1n = 1, dap1n = 0 sck1n sotb1n sio1n output latch so1n writing to sotb1n or reading from sio1n first bit 2nd bit the first bit is directly latched by the sotb1n register to the output latch at the falling (or rising) edge of sck1n, and output from the so1n pin via an output selector. then, the value of the sotb1n regi ster is transferred to the sio1n register at the next rising (or fa lling) edge of sck1n, and shifted one bit. at the same time, the first bit of the receive data is stored in the s io1n register via the si1n pin. the second and subsequent bits are latc hed by the sio1n register to the output latch at the next falling (or rising) edge of sck1n, and the data is output from the so1n pin. remark n = 0, 1 chapter 15 serial interfaces csi10 and csi11 user?s manual u17553ej4v0ud 373 figure 15-12. output operation of first bit (2/2) (c) type 2: ckp1n = 0, dap1n = 1 sck1n sotb1n sio1n so1n writing to sotb1n or reading from sio1n first bit 2nd bit 3rd bit output latch (d) type 4: ckp1n = 1, dap1n = 1 first bit 2nd bit 3rd bit sck1n sotb1n sio1n output latch so1n writing to sotb1n or reading from sio1n the first bit is directly latched by the sotb1n register at the falling edge of the write signal of the sotb1n register or the read signal of the sio1n register, and output from the so1n pin via an output selector. then, the value of the sotb1n register is transfe rred to the sio1n register at the next falling (or rising) edge of sck1n, and shifted one bit. at the same time, the first bit of the rece ive data is stored in the sio1n register via the si1n pin. the second and subsequent bits are latc hed by the sio1n register to the out put latch at the next rising (or falling) edge of sck1n, and the data is output from the so1n pin. remark n = 0, 1 chapter 15 serial interfaces csi10 and csi11 user?s manual u17553ej4v0ud 374 (4) output value of so1n pin (last bit) after communication has been completed, the so1n pin holds the output value of the last bit. figure 15-13. output value of so1n pin (last bit) (1/2) (a) type 1: ckp1n = 0, dap1n = 0 sck1n sotb1n sio1n so1n writing to sotb1n or reading from sio1n ( next request is issued.) last bit output latch (b) type 3: ckp1n = 1, dap1n = 0 last bit ( next request is issued.) sck1n sotb1n sio1n output latch so1n writing to sotb1n or reading from sio1n remark n = 0, 1 chapter 15 serial interfaces csi10 and csi11 user?s manual u17553ej4v0ud 375 figure 15-13. output value of so1n pin (last bit) (2/2) (c) type 2: ckp1n = 0, dap1n = 1 sck1n sotb1n sio1n so1n last bit writing to sotb1n or reading from sio1n ( next request is issued.) output latch (d) type 4: ckp1n = 1, dap1n = 1 last bit ( next request is issued.) sck1n sotb1n sio1n output latch so1n writing to sotb1n or reading from sio1n remark n = 0, 1 chapter 15 serial interfaces csi10 and csi11 user?s manual u17553ej4v0ud 376 (5) so1n output (see (a) in figures 15-1 and 15-2) the status of the so1n output is as follows if bit 7 (csie1n) of seri al operation mode register 1n (csim1n) is cleared to 0. table 15-3. so1n output status trmd1n dap1n dir1n so1n output note 1 trmd1n = 0 note ? ? outputs low level note 2 dap1n = 0 ? value of so1n latch (low-level output) dir1n = 0 value of bit 7 of sotb1n trmd1n = 1 dap1n = 1 dir1n = 1 value of bit 0 of sotb1n notes 1. the actual output of the so10/p12 or so11/p74 pin is determined according to pm12 and p12 or pm74 and p74, as well as the so1n output. 2. status after reset caution if a value is written to trmd1n, dap1n, and dir1n, the output value of so1n changes. remark n = 0, 1 user?s manual u17553ej4v0ud 377 chapter 16 can controller 16.1 outline description this product features an on-chip 1-channel can (contro ller area network) controller that complies with can protocol as standardized in iso 11898. 16.1.1 features - compliant with iso 11898 and tested according to iso/dis 16845 (can conformance test) - standard frame and extended fram e transmission/reception enabled - transfer rate: 1 mbps max. (can clock input 8 mhz) - 16 message buffers/1 channel - receive/transmit history list function - automatic block transmission function - multi-buffer receive block function - mask setting of four patterns is possible for each channel chapter 16 can controller user?s manual u17553ej4v0ud 378 16.1.2 overview of functions table 16-1 presents an overview of the can controller functions. table 16-1. overview of functions function details protocol can protocol iso 11898 (standard and extended frame transmission/reception) baud rate maximum 1 mbps (can clock input 8 mhz) data storage storing messages in the can ram number of messages - 16 message buffers/1 channel - each message buffer can be set to be either a transmit message buffer or a receive message buffer. message reception - unique id can be set to each message buffer. - mask setting of four patterns is possible for each channel. - a receive completion interrupt is generated eac h time a message is received and stored in a message buffer. - two or more receive message buffers can be us ed as a fifo receive buffer (multi-buffer receive block function). - receive history list function message transmission - unique id can be set to each message buffer. - transmit completion interrupt for each message buffer - message buffer number 0 to 7 specified as the transmit message buffer can be used for automatic block transfer. message transmis sion interval is programmable (automatic block transmission function (herea fter referred to as ?abt?)). - transmission history list function remote frame processing remote frame processing by transmit message buffer time stamp function - the time stamp function can be set for a message reception when a 16-bit timer is used in combination. time stamp capture trigger can be select ed (sof or eof in a can message frame can be detected.). diagnostic function - readable error counters - ?valid protocol operation flag? fo r verification of bus connections - receive-only mode - single-shot mode - can protocol error type decoding - self-test mode forced release from bus-off state - forced release from bus- off (by ignoring timing constr aint) possible by software. - no automatic release from bus-off (software must re-enable). power save mode - can sleep mode (can be woken up by can bus) - can stop mode (cannot be woken up by can bus) chapter 16 can controller user?s manual u17553ej4v0ud 379 16.1.3 configuration the can controller is composed of the following four blocks. (1) npb interface this functional block provides an npb (nec perip heral i/o bus) interface and means of transmitting and receiving signals between the can module and the host cpu. (2) mcm (message control module) this functional block controls access to the can prot ocol layer and to the can ram within the can module. (3) can protocol layer this functional block is involved in the oper ation of the can protocol and its related settings. (4) can ram this is the can memory functional block, which is used to store message ids, message data, etc. figure 16-1. block diagram of can module ctxd crxd cpu can module can ram npb (nec peripheral i/o bus) mcm (message control module) npb interface interrupt request inttrx0 intrec0 interr0 intwup0 can protocol layer can transceiver message buffer 0 message buffer 1 message buffer 2 message buffer 3 message buffer 15 c 0 mask1 c 0 mask2 c 0 mask3 c 0 mask4 ... can_h0 can_l0 can bus chapter 16 can controller user?s manual u17553ej4v0ud 380 16.2 can protocol can (controller area network) is a high-speed multiplex communication protocol for real-time communication in automotive applications (class c). can is prescribed by iso 11898. for details, refer to the iso 11898 specifications. the can specification is generally divided into two layers : a physical layer and a data link layer. in turn, the data link layer includes logical link and medium access control. the composition of these layers is illustrated below. figure 16-2. composition of layers physical layer prescription of signal level and bit description data link layer note logical link control (llc) medium access control (mac) acceptance filtering overload report recovery management data capsuled/not capsuled frame coding (stuffing/not stuffing) medium access management error detection error report acknowledgement seriated/not seriated higher lower note can controller specification 16.2.1 frame format (1) standard format frame - the standard format frame uses 11-bit identifiers, wh ich means that it can handle up to 2048 messages. (2) extended format frame - the extended format frame uses 29-bit (11 bits + 18 bits) identifiers which increase the number of messages that can be handled to 2048 x 218 messages. - extended format frame is set when ?recessive level? (cmos level equals ?1?) is set for both the srr and ide bits in the arbitration field. chapter 16 can controller user?s manual u17553ej4v0ud 381 16.2.2 frame types the following four types of frames are used in the can protocol. table 16-2. frame types frame type description data frame frame used to transmit data remote frame frame used to request a data frame error frame frame used to report error detection overload frame frame used to delay the next data frame or remote frame (1) bus value the bus values are divided into dominant and recessive. - dominant level is indicated by logical 0. - recessive level is indicated by logical 1. - when a dominant level and a recessive level are transmitted simultaneously, the bus value becomes dominant level. 16.2.3 data frame and remote frame (1) data frame a data frame is composed of seven fields. figure 16-3. data frame r d interframe space end of frame (eof) ack field crc field data field control field arbitration field start of frame (sof) data frame <1> <2> <3> <4> <5> <6> <7> <8> remark d: dominant = 0 r: recessive = 1 chapter 16 can controller user?s manual u17553ej4v0ud 382 (2) remote frame a remote frame is composed of six fields. figure 16-4. remote frame r d interframe space end of frame (eof) ack field crc field control field arbitration field start of frame (sof) remote frame <1> <2> <3> <5> <6> <7> <8> remarks 1. the data field is not transferred even if the cont rol field?s data length code is not ?0000b?. 2. d: dominant = 0 r: recessive = 1 (3) description of fields <1> start of frame (sof) the start of frame field is located at t he start of a data frame or remote frame. figure 16-5. start of frame (sof) r d 1 bit start of frame (interframe space or bus idle) (arbitration field) remark d: dominant = 0 r: recessive = 1 ? if dominant level is detected in t he bus idle state, a hard-synchroniza tion is performed (the current tq is assigned to be the sync segment). ? if dominant level is sampled at the sample point following such a hard-synchronization, the bit is assigned to be a sof. if recessive level is detect ed, the protocol layer returns to the bus idle state and regards the preceding dominant pulse as a dist urbance only. no error frame is generated in such case. chapter 16 can controller user?s manual u17553ej4v0ud 383 <2> arbitration field the arbitration field is used to set the priori ty, data frame/remote frame, and frame format. figure 16-6. arbitration field (in standard format mode) r d ide (r1) r0 rtr identifier arbitration field (control field) (11 bits) id28 id18 (1 bit) (1 bit) cautions 1. id28 to id18 are identifiers. 2. an identifier is transmitted msb first. remark d: dominant = 0 r: recessive = 1 figure 16-7. arbitration field (in extended format mode) r d r1 r0 rtr ide srr identifier identifier arbitration field (control field) (11 bits) (18 bits) id28 id18 id17 id0 (1 bit) (1 bit) (1 bit) cautions 1. id28 to id18 are identifiers. 2. an identifier is transmitted msb first. remark d: dominant = 0 r: recessive = 1 table 16-3. rtr frame settings frame type rtr bit data frame 0 (d) remote frame 1 (r) table 16-4. frame format setting (ide bit) and number of identifier (id) bits frame format srr bit ide bit number. of bits standard format mode none 0 (d) 11 bits extended format mode 1 (r) 1 (r) 29 bits chapter 16 can controller user?s manual u17553ej4v0ud 384 <3> control field the control field sets ?n? as the number of da ta bytes in the data field (n = 0 to 8). figure 16-8. control field r d r1 (ide) r0 rtr dlc2 dlc3 dlc1 dlc0 control field (data field) (arbitration field) remark d: dominant = 0 r: recessive = 1 in a standard format frame, the control fiel d?s ide bit is the same as the r1 bit. table 16-5. data length setting data length code dlc3 dlc2 dlc1 dlc0 data byte count 0 0 0 0 0 bytes 0 0 0 1 1 byte 0 0 1 0 2 bytes 0 0 1 1 3 bytes 0 1 0 0 4 bytes 0 1 0 1 5 bytes 0 1 1 0 6 bytes 0 1 1 1 7 bytes 1 0 0 0 8 bytes other than above 8 bytes regardless of the value of dlc3 to dlc0 caution in the remote frame, there is no data field even if the data length code is not 0000b. chapter 16 can controller user?s manual u17553ej4v0ud 385 <4> data field the data field contains the am ount of data (byte units) set by the cont rol field. up to 8 units of data can be set. figure 16-9. data field r d data0 (8 bits) msb lsb data7 (8 bits) msb lsb data field (crc field) (control field) remark d: dominant = 0 r: recessive = 1 <5> crc field the crc field is a 16-bit field that is used to check for errors in transmit data. figure 16-10. crc field r d crc sequence crc delimiter (1 bit) (15 bits) crc field (ack field) (data field or control field) remark d: dominant = 0 r: recessive = 1 - the polynomial p(x) used to generate the 15-b it crc sequence is expressed as follows. p(x) = x15 + x14 + x10 + x8 + x7 + x4 + x3 + 1 - transmitting node: transmits the crc sequence calcul ated from the data (before bit stuffing) in the start of frame, arbitration field, control field, and data field. - receiving node: compares the crc sequence calcul ated using data bits t hat exclude the stuffing bits in the receive data with the crc sequ ence in the crc field. if the two crc sequences do not match, the node issues an error frame. chapter 16 can controller user?s manual u17553ej4v0ud 386 <6> ack field the ack field is used to acknowledge normal reception. figure 16-11. ack field r d ack slot (1 bit) ack delimiter (1 bit) ack field (end of frame) (crc field) remark d: dominant = 0 r: recessive = 1 - if no crc error is detected, the receiving node sets the ack slot to the dominant level. - the transmitting node outputs two recessive-level bits. <7> end of frame (eof) the end of frame field indicates the end of data frame/remote frame. figure 16-12. end of frame (eof) r d end of frame (7 bits) (interframe space or overload frame) (ack field) remark d: dominant = 0 r: recessive = 1 chapter 16 can controller user?s manual u17553ej4v0ud 387 <8> interframe space the interframe space is inserted after a data frame, remote frame, error frame, or overload frame to separate one frame from the next. - the bus state differs depend ing on the error status. (a) error active node the interframe space consists of a 3-bit intermission field and a bus idle field. figure 16-13. interframe space (error active node) r d interframe space intermission (3 bits) bus idle (0 to bits) (frame) (frame) remarks 1. bus idle: state in which the bus is not used by any node. 2. d: dominant = 0 r: recessive = 1 (b) error passive node the interframe space consists of an intermission field, a suspend transmission field, and a bus idle field. figure 16-14. interframe space (error passive node) r d interframe space intermission (3 bits) suspend transmission (8 bits) bus idle (0 to bits) (frame) (frame) remarks 1. bus idle: state in which the bus is not used by any node. suspend transmission: sequence of 8 recess ive-level bits transmitted from the node in the error passive status. 2. d: dominant = 0 r: recessive = 1 usually, the intermission field is 3 bits. if the transmi tting node detects a dominant level at the third bit of the intermission field, however, it executes transmission. chapter 16 can controller user?s manual u17553ej4v0ud 388 - operation in error status table 16-6. operation in error status error status operation error active a node in this status can transm it immediately after a 3-bit intermission. error passive a node in this status can tr ansmit 8 bits after the intermission. chapter 16 can controller user?s manual u17553ej4v0ud 389 16.2.4 error frame an error frame is output by a node that has detected an error. figure 16-15. error frame <1> r d <2> <3> 6 bits 0 to 6 bits 8 bits (<4>) (<5>) interframe space or overload frame error delimiter error flag2 error flag1 error bit error frame remark d: dominant = 0 r: recessive = 1 table 16-7. definition error frame fields no. name bit count definition <1> error flag1 6 error active node: output s 6 dominant-level bi ts consecutively. error passive node: outputs 6 rece ssive-level bits consecutively. if another node outputs a dominant level while one node is outputting a passive error flag, the passive error flag is not cleared until the same level is detected 6 bits in a row. <2> error flag2 0 to 6 nodes receiving error flag 1 detect bit stuff errors and issues this error flag. <3> error delimiter 8 outputs 8 rece ssive-level bits consecutively. if a dominant level is detected at the 8th bit, an overload frame is transmitted from the next bit. <4> error bit ? the bit at which the error was detected. the error flag is output from the bit next to the error bit. in the case of a crc error, this bit is output following the ack delimiter. <5> interframe space/overload frame ? an interframe space or overload frame starts from here.5 chapter 16 can controller user?s manual u17553ej4v0ud 390 16.2.5 overload frame an overload frame is transmitted under the following conditions. - when the receiving node has not completed the reception operation note - if a dominant level is detected at the first two bits during intermission - if a dominant level is detected at the last bit (7th bit) of the end of frame or at the last bit (8th bit) of the error delimiter/overload delimiter note the can is internally fast enough to process all received frames not generating overload frames. figure 16-16. overload frame <1> r d <2> <3> 6 bits 0 to 6 bits 8 bits (<4>) (<5>) interframe space or overload frame overload delimiter overload flag overload flag frame overload frame remark d: dominant = 0 r: recessive = 1 table 16-8. definition of overload frame fields no name bit count definition <1> overload flag 6 outputs 6 domin ant-level bits consecutively. <2> overload flag from other node 0 to 6 the node that received an overload flag in the interframe space outputs an overload flag. <3> overload delimiter 8 outputs 8 re cessive-level bits consecutively. if a dominant level is detected at the 8th bit, an overload frame is transmitted from the next bit. <4> frame ? output following an end of frame, error delimiter, or overload delimiter. <5> interframe space/overload frame ? an interframe space or overload frame starts from here. chapter 16 can controller user?s manual u17553ej4v0ud 391 16.3 functions 16.3.1 determining bus priority (1) when a node starts transmission: - during bus idle, the node that out put data first transmits the data. (2) when more than one n ode starts transmission: - the node that outputs the dominant level fo r the longest consecutively from the first bit of the arbitration field acquires the bus priority (if a dominant level and a recessive level are simultaneously transmitted, the dominant level is taken as the bus value). - the transmitting node compares its output arbi tration field and the data level on the bus. table 16-9. determining bus priority level match continuous transmission level mismatch continuous transmission (3) priority of data frame and remote frame - when a data frame and a remote frame are on the bus, t he data frame has priority because its rtr bit, the last bit in the arbitration field, carries a dominant level. remark if the extended-format data fram e and the standard-format remote frame conflict on the bus (if id28 to id18 of both of them are the same), the standard-format remo te frames takes priority. 16.3.2 bit stuffing bit stuffing is used to establish synchronization by appending 1-bit inverted data if the same level continues for 5 bits, in order to prevent a burst error. table 16-10. bit stuffing transmission during the trans mission of a data frame or remote frame, when the same level continues for 5 bits in the data between the start of frame and the ack field, 1 inverted-level bit of data is inserted before the following bit. reception during the reception of a data frame or remote frame, when the same level continues for 5 bits in the data between the start of frame and the ack field, re ception is continued after deleting the next bit. 16.3.3 multi masters as the bus priority (a node acquiring transmit functions) is determined by the identif ier, any node can be the bus master. 16.3.4 multi cast although there is one transmitting node, two or more nodes can receive the same data at the same time because the same identifier can be set to two or more nodes. 16.3.5 can sleep mode/can stop mode function the can sleep mode/can stop mode func tion puts the can controller in waiting mode to achieve low power consumption. chapter 16 can controller user?s manual u17553ej4v0ud 392 the controller is woken up from the can sleep mode by bus operation but it is not woken up from the can stop mode by bus operation (the can stop mode is controlled by cpu access). 16.3.6 error control function (1) error types table 16-11. error types description of error detection state type detection method detection condition transmission/ reception field/frame bit error comparison of output level and level on the bus mismatch of levels transmitting/ receiving node bit that outputting data on the bus at the start of frame to end of frame, error frame and overload frame. stuff error check the receive data at the stuff bit 6 consecutive bits of the same output level receiving node start of frame to crc sequence crc error comparison of the crc sequence generated from the receive data and the received crc sequence mismatch of crc receiving node crc field form error field/fram e check of the fixed format detection of fixed format violation receiving node crc delimiter ack field end of frame error frame overload frame ack error check of the ack slot by the transmitting node detection of recessive level in ack slot transmitting node ack slot (2) output timing of error frame table 16-12. output timing of error frame type output timing bit error, stuff error, form error, ack error error frame output is started at the timing of the bit following the detected error. crc error error frame output is started at the timing of the bit following the ack delimiter. (3) processing in case of error the transmission node re-transmits the data frame or remote frame after the error frame (however, it does not re-transmit the frame in the single-shot mode.). chapter 16 can controller user?s manual u17553ej4v0ud 393 (4) error state (a) types of error states the following three types of error states are defined by the can specification. - error active - error passive - bus-off these types of error states are cl assified by the values of the tec7 to tec0 bits (transmission error counter bits) and the rec6 to rec0 bits (reception er ror counter bits) of the can error counter register (c0erc) as shown in table 16-13. the present error state is indicated by t he can module information register (c0info). when each error counter value becomes equal to or greater than the error warning level (96), the tecs0 or recs0 bit of the c0info register is set to 1. in this case, the bus state must be tested because it is considered that the bus has a serious fault. an error counter value of 128 or more indicates an error passive state and the tecs1 or recs1 bit of the c0info register is set to 1. - if the value of the transmission error counter is gr eater than or equal to 256 (actually, the transmission error counter does not indicate a value greater t han or equal to 256), the bus-off state is reached and the boff bit of the c0info register is set to 1. - if only one node is active on the bus at startup (i.e., a particular case such as when the bus is connected only to the local stati on), ack is not returned even if dat a is transmitted. consequently, re- transmission of the error frame and data is repeat ed. in the error passive state, however, the transmission error counter is not incremen ted and the bus-off state is not reached. chapter 16 can controller user?s manual u17553ej4v0ud 394 table 16-13. types of error states type operation value of error counter indication of c0info register operation specific to given error state error active transmission 0-95 tecs1, tecs0 = 00 reception 0-95 recs1, recs0 = 00 transmission 96-127 tecs1, tecs0 = 01 reception 96-127 recs1, recs0 = 01 - outputs an active erro r flag (6 consecutive dominant-level bits) on detection of the error. error passive transmission 128-255 tecs1, tecs0 = 11 reception 128 or more recs1, recs0 = 11 - outputs a passive error flag (6 consecutive recessive-level bits) on detection of the error. - transmits 8 recessive-level bits, in between transmissions, following an intermission (suspend transmission). bus-off transmission 256 or more (not indicated) note boff = 1, tecs1, tecs0 = 11 - communication is not possible. messages are not stored when receiving frames, however, the following operations of <1>, <2>, and <3> are done. <1> tsout toggles. <2> rec is incremented/decremented. <3> valid bit is set. - if the can module is entered to the initialization mode and then transition request to any operation mode is made, and when 11 consecutive recessive-level bits are detected 128 times, the error counter is reset to 0 and the error active state can be restored. note the value of the transmission error count er (tec) is invalid when the boff bit is set to 1. if an error that increments the value of the transmission error counter by +8 while the counter value is in a range of 248 to 255, the counter is not incremented and the bus-off state is assumed. chapter 16 can controller user?s manual u17553ej4v0ud 395 (b) error counter the error counter counts up when an error has occu rred, and counts down upon successful transmission and reception. the error counter is upd ated immediately after error detection. table 16-14. error counter state transmission error counter (tec7 to tec0) reception error counter (rec6 to rec0) receiving node detects an error (except bit error in the active error flag or overload flag). no change +1 (when reps bit = 0) receiving node detects dominant level following error flag of error frame. no change +8 (when reps bit = 0) transmitting node transmits an error flag. [as exceptions, the error counter does not change in the following cases.] <1> ack error is detected in error passive state and dominant level is not detected while the passive error flag is being output. <2> a stuff error is detected in an ar bitration field that transmitted a recessive level as a stuff bit, but a dominant level is detected. +8 no change bit error detection while active error flag or overload flag is being output (error-active transmitting node) +8 no change bit error detection while active error flag or overload flag is being output (error-active receiving node) no change +8 (when reps bit = 0) when the node detects 14 consecutive dominant-level bits from the beginning of the active error flag or overload flag, and then subsequently detects 8 consecutive dominant-lev el bits. when the node detects 8 consecutive dominant levels after a passive error flag +8 (during transmission) +8 (during reception, when reps bit = 0) when the transmitting node has comple ted transmission without error (0 if error counter = 0) ?1 no change when the receiving node has completed rec eption without error no change - ?1 (1 rec6 to rec0 127, when reps bit = 0) - 0 (rec6 to rec0 = 0, when reps bit = 0) - value of 119 to 255 is set (when reps bit = 1) (c) occurrence of bit error in intermission an overload frame is generated. caution if an error occurs, the error flag output (act ive or passive) is cont rolled according to the contents of the transmission error counter and reception error coun ter before the error occurred. the value of the error counter is incremented after the error flag has been output. chapter 16 can controller user?s manual u17553ej4v0ud 396 (5) recovery from bus-off state when the can module is in the bus-off state, the can module permanently se ts its output signals (ctxd) to recessive level. the can module recovers from the bus-off stat e in the following bus-off recovery sequence. <1> a request to enter the can initialization mode <2> a request to enter a can operation mode (a) recovery operation through normal recovery sequence (b) forced recovery operation that skips recovery sequence (a) recovery operation from bus-off st ate through normal recovery sequence the can module first issues a request to enter the initialization mode (refer to timing <1> in figure 16- 17). this request will be immediately acknowledged, and the opmode bits of t he c0ctrl register are cleared to 000b. processing such as analyzing the fault that has caused the bus-off state, re-defining the can module and message buffer using applicati on software, or stopping t he operation of the can module can be performed by clearing the gom bit to 0. next, the user requests to change the mode from the initialization mode to an operation mode (refer to timing <2> in figure 16-17). this starts an operation to recover the can module from the bus-off state. the conditions under which the module can recover from the bus-off state are defined by the can protocol iso 11898, and it is necessary to detect 11 c onsecutive recessive-level bits 128 times. at this time, the request to change the mode to an operation mode is held pending until the recovery conditions are satisfied. when the recovery conditions are sati sfied (refer to timing <3> in figure 16-17), the can module can enter the operation mode it has reques ted. until the can m odule enters this operation mode, it stays in the initialization mode. comple tion to be requested operation mode can be confirmed by reading the opmode bits of the c0ctrl register. during the bus-off period and bus-off recovery sequence, the boff bit of the c0info register stays set (to 1). in the bus-off recovery sequence, the rec eption error counter (rec[6:0]) counts the number of times 11 consecutive recessive-level bits have been de tected on the bus. theref ore, the recovery state can be checked by reading rec[6:0]. cautions 1 when the transmissi on from the initialization mode to any operation modes is requested to execute bus-off recovery se quence again in the bus-off recovery sequence, reception erro r counter is cleared. therefore it is necessary to detect 11 c onsecutive recessive-level bits 128 times on the bus again. 2. in the bus-off reco very sequence, rec[6:0] c ounts up (+1) each time 11 consecutive recessive-level bi ts have been detected. even during the bus-off period, the can module can en ter the can sleep mode or can stop mode. to start the bus-off recovery sequence, it is necessar y to transit to the initialization mode once. however, when the can module is in either can sleep mode or can stop mode, transition request to the initialization m ode is not accepted, thus you have to release the can sleep mode first. in th is case, as soon as the can sleep mode is released, the bus-off recovery sequence star ts and no transition to initialization mode is necessary. if the can module detects a dominant edge on the can bus while in sleep mode even during bus-off, the sleep mode will be left and the bus-off recovery sequence will start. chapter 16 can controller user?s manual u17553ej4v0ud 397 figure 16-17. recovery operation from bu s-off state through norma l recovery sequence ?error-passive? 00h 00h 00h 00h 80h tec[7:0] ffh boff bit in c0info register opmode[2:0] in c0ctrl register (user writings) opmode[2:0] in c0ctrl register (user readings) tec[7:0] in c0erc register reps, rec[6:0] in c0erc register tec > ffh 00h 00h 00h ffh < tec [7:0] ?bus-off? ?bus-off-recovery-sequence? ?error-active? 00h tec[7:0] < 80h 00h reps, rec[6:0] < 80h <1> <2> <3> undefined 80h reps, rec[6:0] ffh (b) forced recovery operation that skips bus-off recovery sequence the can module can be forcibly released from the bus -off state, regardless of the bus state, by skipping the bus-off recovery sequence. here is the procedure. first, the can module requests to enter the initiali zation mode. for the operation and points to be noted at this time, refer to (a) reco very operation from bus-off state through normal recovery sequence. next, the module requests to enter an operation mode . at the same time, the ccerc bit of the c0ctrl register must be set to 1. as a result, the bus-off recovery sequence defined by the can protocol iso 11898 is skipped, and the module immediately enters the operation mode. in this case, the module is connected to the can bus after it has monitored 11 consecutive recessive-level bits. for details, refer to the processing in figure 16-56. caution this function is not defined by the can protocol iso 11898. when using this function, thoroughly evaluate its effe ct on the network system. (6) initializing can module error counter re gister (c0erc) in initialization mode if it is necessary to initialize the can module erro r counter register (c0erc) and can module information register (c0info) for debugging or evaluating a program , they can be initialized to the default value by setting the ccerc bit of the c0ctrl register in the initialization mode. when initialization has been completed, the ccerc bit is automatically cleared to 0. cautions 1. this function is enabled only in the init ialization mode. even if the ccerc bit is set to 1 in a can operation mode, the c0erc and c0info registers are not initialized. 2. the ccerc bit can be set at the same ti me as the request to enter a can operation mode. chapter 16 can controller user?s manual u17553ej4v0ud 398 16.3.7 baud rate control function (1) prescaler the can controller has a prescaler that divides the clock (f can ) supplied to can. this prescaler generates a can protocol layer basic clock (f tq ) derived from the can module system clock (f canmod ), and divided by 1 to 256 (refer to 16.6 (12) can bit rate prescaler register (c0brp) ). (2) data bit time (8-25 time quanta) one data bit time is defined as shown in figure 16-18. the can controller sets time segment 1, time segment 2, and resynchronization jump width (sjw) as the parameter of data bit time, as shown in figure 16-18. time segment 1 is equivalent to the total of the propagation (prop) segment and phase s egment 1 that are defined by the can protocol specification. time segment 2 is equivalent to phase segment 2. figure 16-18. segment setting data bit time(dbt) phase segment 1 prop segment sync segment phase segment 2 time segment 1(tseg1) time segment 2 (tseg2) sample point (spt) segment name settable range notes on setting to confirm to can specification time segment 1 (tseg1) 2tq-16tq ? time segment 2 (tseg2) 1tq-8tq ipt of the ca n controller is 0tq. to conform to the can protocol specification, therefore, a length equal to phase segment 1 must be set here. this means that the length of time segment 1 minus 1tq is the settable upper limit of time segment 2. resynchronization jump width(sjw) 1tq-4tq the length of time segment 1 minus 1tq or 4 tq, whichever is smaller. remark ipt : information processing time tq : time quanta chapter 16 can controller user?s manual u17553ej4v0ud 399 reference: the can standard iso 11898 specification defines the segments constituting the data bit time as shown in figure 16-19. figure 16-19. reference: configuration of data bit time defined by can specification phase segment 1 prop segment sync segment phase segment 2 sample point (spt) sjw data bit time(dbt) segment name segment length description sync segment (synchronization segment) 1 this segment starts at the edge where the level changes from recessive to dominant when hard-synchronization is established. prop segment programmable to 1 to 8 or more this segment absorbs the delay of the output buffer, can bus, and input buffer. the length of this segment is set so that ack is returned before the start of phase segment 1. time of prop segment (delay of output buffer) + 2 x (delay of can bus) + (delay of input buffer) phase segment 1 programmable to 1 to 8 phase segment 2 phase segment 1 or ipt, whichever greater this segment compensates for an error of data bit time. the longer this segment, the wider the permissible range but the slower the communication speed. sjw programmable from 1tq to length of segment 1 or 4tq, whichever is smaller this width sets the upper limit of expansion or contraction of the phase segment during resynchronization. remark ipt : information processing time tq : time quanta chapter 16 can controller user?s manual u17553ej4v0ud 400 (3) synchronizing data bit - the receiving node establishes synchronization by a level change on the bus because it does not have a sync signal. - the transmitting node transmits data in synchroniz ation with the bit timing of the transmitting node. (a) hard-synchronization this synchronization is established when the receiving node detects the start of frame in the interframe space. - when a falling edge is detected on t he bus, that tq means the sync segment and the next segment is the prop segment. in this case, synchroni zation is established regardless of sjw. figure 16-20. hard-synchroniza tion at recognition of domi nant level during bus idle start of frame interframe space canbus bit timing phase segment 1 prop segment sync segment phase segment 2 chapter 16 can controller user?s manual u17553ej4v0ud 401 (b) resynchronization synchronization is established again if a level change is detected on th e bus during reception (only if a recessive level was sampled previously). - the phase error of the edge is given by the relati ve position of the detected edge and sync segment. chapter 16 can controller user?s manual u17553ej4v0ud 402 16.4 connection with target system the microcontroller incorporated a can has to be connec ted to the can bus using an external transceiver. figure 16-22. connection to can bus microcontroller incorporated a can transceiver ctxd crxd canl canh chapter 16 can controller user?s manual u17553ej4v0ud 403 16.5 internal registers of can controller 16.5.1 can controller configuration table 16-15. list of can controller registers item register name can global registers can global control register (c0gmctrl) can global clock selection register (c0gmcs) can global automatic block transm ission control register (c0gmabt) can global automatic block transm ission delay register (c0gmabtd) can module registers can module mask 1 register (c0mask1l, c0mask1h) can module mask 2 register (c0mask2l, c0mask2h) can module mask3 register (c0mask3l, c0mask3h) can module mask 4 registers (c0mask4l, c0mask4h) can module control register (c0ctrl) can module last error code register (c0lec) can module information register (c0info) can module error counter register (c0erc) can module interrupt enable register (c0ie) can module interrupt status register (c0ints) can module bit rate prescaler register (c0brp) can module bit rate register (c0btr) can module last in-pointer register (c0lipt) can module receive histor y list register (c0rgpt) can module last out-pointer register (c0lopt) can module transmit histor y list register (c0tgpt) can module time stamp register (c0ts) message buffer registers can message data byte 01 register m (c0mdata01m) can message data byte 0 register m (c0mdata0m) can message data byte 1 register m (c0mdata1m) can message data byte 23 register m (c0mdata23m) can message data byte 2 register m (c0mdata2m) can message data byte 3 register m (c0mdata3m) can message data byte 45 register m (c0mdata45m) can message data byte 4 register m (c0mdata4m) can message data byte 5 register m (c0mdata5m) can message data byte 67 register m (c0mdata67m) can message data byte 6 register m (c0mdata6m) can message data byte 7 register m (c0mdata7m) can message data length register m (c0mdlcm) can message configuration register m (c0mconfm) can message id register m (c0midlm, c0midhm) can message control register m (c0mctrlm) remark m = 0 to 15 chapter 16 can controller user?s manual u17553ej4v0ud 404 16.5.2 register access type table 16-16. register access types (1/9) bit manipulation units address register name symbol r/w 1 8 16 default value fa00h can0 message data byte 01 register 00 c0mdata0100 undefined fa00h can0 message data byte 0 register 00 c0mdata000 undefined fa01h can0 message data byte 1 register 00 c0mdata100 undefined fa02h can0 message data byte 23 register 00 c0mdata2300 undefined fa02h can0 message data byte 2 register 00 c0mdata200 undefined fa03h can0 message data byte 3 register 00 c0mdata300 undefined fa04h can0 message data byte 45 register 00 c0mdata4500 undefined fa04h can0 message data byte 4 register 00 c0mdata400 undefined fa05h can0 message data byte 5 register 00 c0mdata500 undefined fa06h can0 message data byte 67 register 00 c0mdata6700 undefined fa06h can0 message data byte 6 register 00 c0mdata600 undefined fa07h can0 message data byte 7 register 00 c0mdata700 undefined fa08h can0 message data length code register 00 c0mdlc00 0000xxxxb fa09h can0 message configuration register 00 c0mconf00 undefined fa0ah c0midl00 undefined fa0ch can0 message id register 00 c0midh00 undefined fa0eh can0 message control register 00 c0mctrl00 00x00000 000xx000b fa10h can0 message data byte 01 register 01 c0mdata0101 undefined fa10h can0 message data byte 0 register 01 c0mdata001 undefined fa11h can0 message data byte 1 register 01 c0mdata101 undefined fa12h can0 message data byte 23 register 01 c0mdata2301 undefined fa12h can0 message data byte 2 register 01 c0mdata201 undefined fa13h can0 message data byte 3 register 01 c0mdata301 undefined fa14h can0 message data byte 45 register 01 c0mdata4501 undefined fa14h can0 message data byte 4 register 01 c0mdata401 undefined fa15h can0 message data byte 5 register 01 c0mdata501 undefined fa16h can0 message data byte 67 register 01 c0mdata6701 undefined fa16h can0 message data byte 6 register 01 c0mdata601 undefined fa17h can0 message data byte 7 register 01 c0mdata701 undefined fa18h can0 message data length code register 01 c0mdlc01 0000xxxxb fa19h can0 message configuration register 01 c0mconf01 undefined fa1ah c0midl01 undefined fa1ch can0 message id register 01 c0midh01 undefined fa1eh can0 message control register 01 c0mctrl01 r/w 00x00000 000xx000b chapter 16 can controller user?s manual u17553ej4v0ud 405 table 16-16. register access types (2/9) bit manipulation units address register name symbol r/w 1 8 16 default value fa20h can0 message data byte 01 register 02 c0mdata0102 undefined fa20h can0 message data byte 0 register 02 c0mdata002 undefined fa21h can0 message data byte 1 register 02 c0mdata102 undefined fa22h can0 message data byte 23 register 02 c0mdata2302 undefined fa22h can0 message data byte 2 register 02 c0mdata202 undefined fa23h can0 message data byte 3 register 02 c0mdata302 undefined fa24h can0 message data byte 45 register 02 c0mdata4502 undefined fa24h can0 message data byte 4 register 02 c0mdata402 undefined fa25h can0 message data byte 5 register 02 c0mdata502 undefined fa26h can0 message data byte 67 register 02 c0mdata6702 undefined fa26h can0 message data byte 6 register 02 c0mdata602 undefined fa27h can0 message data byte 7 register 02 c0mdata702 undefined fa28h can0 message data length code register 02 c0mdlc02 0000xxxxb fa29h can0 message configuration register 02 c0mconf02 undefined fa2ah c0midl02 undefined fa2ch can0 message id register 02 c0midh02 undefined fa2eh can0 message control register 02 c0mctrl02 00x00000 000xx000b fa30h can0 message data byte 01 register 03 c0mdata0103 undefined fa30h can0 message data byte 0 register 03 c0mdata003 undefined fa31h can0 message data byte 1 register 03 c0mdata103 undefined fa32h can0 message data byte 23 register 03 c0mdata2303 undefined fa32h can0 message data byte 2 register 03 c0mdata203 undefined fa33h can0 message data byte 3 register 03 c0mdata303 undefined fa34h can0 message data byte 45 register 03 c0mdata4503 undefined fa34h can0 message data byte 4 register 03 c0mdata403 undefined fa35h can0 message data byte 5 register 03 c0mdata503 undefined fa36h can0 message data byte 67 register 03 c0mdata6703 undefined fa36h can0 message data byte 6 register 03 c0mdata603 undefined fa37h can0 message data byte 7 register 03 c0mdata703 undefined fa38h can0 message data length code register 03 c0mdlc03 0000xxxxb fa39h can0 message configuration register 03 c0mconf03 undefined fa3ah c0midl03 undefined fa3ch can0 message id register 03 c0midh03 undefined fa3eh can0 message control register 03 c0mctrl03 r/w 00x00000 000xx000b chapter 16 can controller user?s manual u17553ej4v0ud 406 table 16-16. register access types (3/9) bit manipulation units address register name symbol r/w 1 8 16 default value fa40h can0 message data byte 01 register 04 c0mdata0104 undefined fa40h can0 message data byte 0 register 04 c0mdata004 undefined fa41h can0 message data byte 1 register 04 c0mdata104 undefined fa42h can0 message data byte 23 register 04 c0mdata2304 undefined fa42h can0 message data byte 2 register 04 c0mdata204 undefined fa43h can0 message data byte 3 register 04 c0mdata304 undefined fa44h can0 message data byte 45 register 04 c0mdata4504 undefined fa44h can0 message data byte 4 register 04 c0mdata404 undefined fa45h can0 message data byte 5 register 04 c0mdata504 undefined fa46h can0 message data byte 67 register 04 c0mdata6704 undefined fa46h can0 message data byte 6 register 04 c0mdata604 undefined fa47h can0 message data byte 7 register 04 c0mdata704 undefined fa48h can0 message data length code register 04 c0mdlc04 0000xxxxb fa49h can0 message configuration register 04 c0mconf04 undefined fa4ah c0midl04 undefined fa4ch can0 message id register 04 c0midh04 undefined fa4eh can0 message control register 04 c0mctrl04 00x00000 000xx000b fa50h can0 message data byte 01 register 05 c0mdata0105 undefined fa50h can0 message data byte 0 register 05 c0mdata005 undefined fa51h can0 message data byte 1 register 05 c0mdata105 undefined fa52h can0 message data byte 23 register 05 c0mdata2305 undefined fa52h can0 message data byte 2 register 05 c0mdata205 undefined fa53h can0 message data byte 3 register 05 c0mdata305 undefined fa54h can0 message data byte 45 register 05 c0mdata4505 undefined fa54h can0 message data byte 4 register 05 c0mdata405 undefined fa55h can0 message data byte 5 register 05 c0mdata505 undefined fa56h can0 message data byte 67 register 05 c0mdata6705 undefined fa56h can0 message data byte 6 register 05 c0mdata605 undefined fa57h can0 message data byte 7 register 05 c0mdata705 undefined fa58h can0 message data length code register 05 c0mdlc05 0000xxxxb fa59h can0 message configuration register 05 c0mconf05 undefined fa5ah c0midl05 undefined fa5ch can0 message id register 05 c0midh05 undefined fa5eh can0 message configuration register 05 c0mctrl05 r/w 00x00000 000xx000b chapter 16 can controller user?s manual u17553ej4v0ud 407 table 16-16. register access types (4/9) bit manipulation units address register name symbol r/w 1 8 16 default value fa60h can0 message data byte 01 register 06 c0mdata0106 undefined fa60h can0 message data byte 0 register 06 c0mdata006 undefined fa61h can0 message data byte 1 register 06 c0mdata106 undefined fa62h can0 message data byte 23 register 06 c0mdata2306 undefined fa62h can0 message data byte 2 register 06 c0mdata206 undefined fa63h can0 message data byte 3 register 06 c0mdata306 undefined fa64h can0 message data byte 45 register 06 c0mdata4506 undefined fa64h can0 message data byte 4 register 06 c0mdata406 undefined fa65h can0 message data byte 5 register 06 c0mdata506 undefined fa66h can0 message data byte 67 register 06 c0mdata6706 undefined fa66h can0 message data byte 6 register 06 c0mdata606 undefined fa67h can0 message data byte 7 register 06 c0mdata706 undefined fa68h can0 message data length code register 06 c0mdlc06 0000xxxxb fa69h can0 message configuration register 06 c0mconf06 undefined fa6ah c0midl06 undefined fa6ch can0 message id register 06 c0midh06 undefined fa6eh can0 message control register 06 c0mctrl06 00x00000 000xx000b fa70h can0 message data byte 01 register 07 c0mdata0107 undefined fa70h can0 message data byte 0 register 07 c0mdata007 undefined fa71h can0 message data byte 1 register 07 c0mdata107 undefined fa72h can0 message data byte 23 register 07 c0mdata2307 undefined fa72h can0 message data byte 2 register 07 c0mdata207 undefined fa73h can0 message data byte 3 register 07 c0mdata307 undefined fa74h can0 message data byte 45 register 07 c0mdata4507 undefined fa74h can0 message data byte 4 register 07 c0mdata407 undefined fa75h can0 message data byte 5 register 07 c0mdata507 undefined fa76h can0 message data byte 67 register 07 c0mdata6707 undefined fa76h can0 message data byte 6 register 07 c0mdata607 undefined fa77h can0 message data byte 7 register 07 c0mdata707 undefined fa78h can0 message data length code register 07 c0mdlc07 0000xxxxb fa79h can0 message configuration register 07 c0mconf07 undefined fa7ah c0midl07 undefined fa7ch can0 message id register 07 c0midh07 undefined fa7eh can0 message control register 07 c0mctrl07 r/w 00x00000 000xx000b chapter 16 can controller user?s manual u17553ej4v0ud 408 table 16-16. register access types (5/9) bit manipulation units address register name symbol r/w 1 8 16 default value fa80h can0 message data byte 01 register 08 c0mdata0108 undefined fa80h can0 message data byte 0 register 08 c0mdata008 undefined fa81h can0 message data byte 1 register 08 c0mdata108 undefined fa82h can0 message data byte 23 register 08 c0mdata2308 undefined fa82h can0 message data byte 2 register 08 c0mdata208 undefined fa83h can0 message data byte 3 register 08 c0mdata308 undefined fa84h can0 message data byte 45 register 08 c0mdata4508 undefined fa84h can0 message data byte 4 register 08 c0mdata408 undefined fa85h can0 message data byte 5 register 08 c0mdata508 undefined fa86h can0 message data byte 67 register 08 c0mdata6708 undefined fa86h can0 message data byte 6 register 08 c0mdata608 undefined fa87h can0 message data byte 7 register 08 c0mdata708 undefined fa88h can0 message data length code register 08 c0mdlc08 0000xxxxb fa89h can0 message configuration register 08 c0mconf08 undefined fa8ah c0midl08 undefined fa8ch can0 message id register 08 c0midh08 undefined fa8eh can0 message control register 08 c0mctrl08 00x00000 000xx000b fa90h can0 message data byte 01 register 09 c0mdata0109 undefined fa90h can0 message data byte 0 register 09 c0mdata009 undefined fa91h can0 message data byte 1 register 09 c0mdata109 undefined fa92h can0 message data byte 23 register 09 c0mdata2309 undefined fa92h can0 message data byte 2 register 09 c0mdata209 undefined fa93h can0 message data byte 3 register 09 c0mdata309 undefined fa94h can0 message data byte 45 register 09 c0mdata4509 undefined fa94h can0 message data byte 4 register 09 c0mdata409 undefined fa95h can0 message data byte 5 register 09 c0mdata509 undefined fa96h can0 message data byte 67 register 09 c0mdata6709 undefined fa96h can0 message data byte 6 register 09 c0mdata609 undefined fa97h can0 message data byte 7 register 09 c0mdata709 undefined fa98h can0 message data length code register 09 c0mdlc09 0000xxxxb fa99h can0 message configuration register 09 c0mconf09 undefined fa9ah c0midl09 undefined fa9ch can0 message id register 09 c0midh09 undefined fa9eh can0 message control register 09 c0mctrl09 r/w 00x00000 000xx000b chapter 16 can controller user?s manual u17553ej4v0ud 409 table 16-16. register access types (6/9) bit manipulation units address register name symbol r/w 1 8 16 default value faa0h can0 message data byte 01 register 10 c0mdata0110 undefined faa0h can0 message data byte 0 register 10 c0mdata010 undefined faa1h can0 message data byte 1 register 10 c0mdata110 undefined faa2h can0 message data byte 23 register 10 c0mdata2310 undefined faa2h can0 message data byte 2 register 10 c0mdata210 undefined faa3h can0 message data byte 3 register 10 c0mdata310 undefined faa4h can0 message data byte 45 register 10 c0mdata4510 undefined faa4h can0 message data byte 4 register 10 c0mdata410 undefined faa5h can0 message data byte 5 register 10 c0mdata510 undefined faa6h can0 message data byte 67 register 10 c0mdata6710 undefined faa6h can0 message data byte 6 register 10 c0mdata610 undefined faa7h can0 message data byte 7 register 10 c0mdata710 undefined faa8h can0 message data length code register 10 c0mdlc10 0000xxxxb faa9h can0 message configurat ion register 10 c0mconf10 undefined faaah c0midl10 undefined faach can0 message id register 10 c0midh10 undefined faaeh can0 message control register 10 c0mctrl10 00x00000 000xx000b fab0h can0 message data byte 01 register 11 c0mdata0111 undefined fab0h can0 message data byte 0 register 11 c0mdata011 undefined fab1h can0 message data byte 1 register 11 c0mdata111 undefined fab2h can0 message data byte 23 register 11 c0mdata2311 undefined fab2h can0 message data byte 2 register 11 c0mdata211 undefined fab3h can0 message data byte 3 register 11 c0mdata311 undefined fab4h can0 message data byte 45 register 11 c0mdata4511 undefined fab4h can0 message data byte 4 register 11 c0mdata411 undefined fab5h can0 message data byte 51 register 11 c0mdata511 undefined fab6h can0 message data byte 67 register 11 c0mdata6711 undefined fab6h can0 message data byte 6 register 11 c0mdata611 undefined fab7h can0 message data byte 71 register 11 c0mdata711 undefined fab8h can0 message data length code register 11 c0mdlc11 0000xxxxb fab9h can0 message configurat ion register 11 c0mconf11 undefined fabah c0midl11 undefined fabch can0 message id register 11 c0midh11 undefined fabeh can0 message control register 11 c0mctrl11 r/w 00x00000 000xx000b chapter 16 can controller user?s manual u17553ej4v0ud 410 table 16-16. register access types (7/9) bit manipulation units address register name symbol r/w 1 8 16 default value fac0h can0 message data byte 01 register 12 c0mdata0112 undefined fac0h can0 message data byte 0 register 12 c0mdata012 undefined fac1h can0 message data byte 1 register 12 c0mdata112 undefined fac2h can0 message data byte 23 register 12 c0mdata2312 undefined fac2h can0 message data byte 2 register 12 c0mdata212 undefined fac3h can0 message data byte 3 register 12 c0mdata312 undefined fac4h can0 message data byte 45 register 12 c0mdata4512 undefined fac4h can0 message data byte 4 register 12 c0mdata412 undefined fac5h can0 message data byte 5 register 12 c0mdata512 undefined fac6h can0 message data byte 67 register 12 c0mdata6712 undefined fac6h can0 message data byte 6 register 12 c0mdata612 undefined fac7h can0 message data byte 7 register 12 c0mdata712 undefined fac8h can0 message data length code register 12 c0mdlc12 0000xxxxb fac9h can0 message configuration register 12 c0mconf12 undefined facah c0midl12 undefined facch can0 message id register 12 c0midh12 undefined faceh can0 message control register 12 c0mctrl12 00x00000 000xx000b fad0h can0 message data byte 01 register 13 c0mdata0113 undefined fad0h can0 message data byte 0 register 13 c0mdata013 undefined fad1h can0 message data byte 1 register 13 c0mdata113 undefined fad2h can0 message data byte 23 register 13 c0mdata2313 undefined fad2h can0 message data byte 2 register 13 c0mdata213 undefined fad3h can0 message data byte 3 register 13 c0mdata313 undefined fad4h can0 message data byte 45 register 13 c0mdata4513 undefined fad4h can0 message data byte 4 register 13 c0mdata413 undefined fad5h can0 message data byte 5 register 13 c0mdata513 undefined fad6h can0 message data byte 67 register 13 c0mdata6713 undefined fad6h can0 message data byte 6 register 13 c0mdata613 undefined fad7h can0 message data byte 7 register 13 c0mdata713 undefined fad8h can0 message data length code register 13 c0mdlc13 0000xxxxb fad9h can0 message configuration register 13 c0mconf13 undefined fadah c0midl13 undefined fadch can0 message id register 13 c0midh13 undefined fadeh can0 message control register 13 c0mctrl13 r/w 00x00000 000xx000b chapter 16 can controller user?s manual u17553ej4v0ud 411 table 16-16. register access types (8/9) bit manipulation units address register name symbol r/w 1 8 16 default value fae0h can0 message data byte 01 register 14 c0mdata0114 undefined fae0h can0 message data byte 0 register 14 c0mdata014 undefined fae1h can0 message data byte 1 register 14 c0mdata114 undefined fae2h can0 message data byte 23 register 14 c0mdata2314 undefined fae2h can0 message data byte 2 register 14 c0mdata214 undefined fae3h can0 message data byte 3 register 14 c0mdata314 undefined fae4h can0 message data byte 45 register 14 c0mdata4514 undefined fae4h can0 message data byte 4 register 14 c0mdata414 undefined fae5h can0 message data byte 5 register 14 c0mdata514 undefined fae6h can0 message data byte 67 register 14 c0mdata6714 undefined fae6h can0 message data byte 6 register 14 c0mdata614 undefined fae7h can0 message data byte 7 register 14 c0mdata714 undefined fae8h can0 message data length code register 14 c0mdlc14 0000xxxxb fae9h can0 message configurat ion register 14 c0mconf14 undefined faeah c0midl14 undefined faech can0 message id register 14 c0midh14 undefined faeeh can0 message control register 14 c0mctrl14 00x00000 000xx000b faf0h can0 message data byte 01 register 15 c0mdata0115 undefined faf0h can0 message data byte 0 register 15 c0mdata015 undefined faf1h can0 message data byte 1 register 15 c0mdata115 undefined faf2h can0 message data byte 23 register 15 c0mdata2315 undefined faf2h can0 message data byte 2 register 15 c0mdata215 undefined faf3h can0 message data byte 3 register 15 c0mdata315 undefined faf4h can0 message data byte 45 register 15 c0mdata4515 undefined faf4h can0 message data byte 4 register 15 c0mdata415 undefined faf5h can0 message data byte 5 register 15 c0mdata515 undefined faf6h can0 message data byte 67 register 15 c0mdata6715 undefined faf6h can0 message data byte 6 register 15 c0mdata615 undefined faf7h can0 message data byte 7 register 15 c0mdata715 undefined faf8h can0 message data length code register 15 c0mdlc15 0000xxxx faf9h can0 message configuration register 15 c0mconf15 undefined fafah c0midl15 undefined fafch can0 message id register 15 c0midh15 undefined fafeh can0 message control register 15 c0mctrl15 r/w 00x00000 000xx000b chapter 16 can controller user?s manual u17553ej4v0ud 412 table 16-16. register access types (9/9) bit manipulation units address register name symbol r/w 1 8 16 default value ff60h can0 module receive histor y list register c0rgpt r/w - ? xx02h ff62h can0 module transmit history list register c0tgpt r/w ? ? xx02h ff64h can0 global control register c0gmctrl r/w ? ? 0000h ff66h can0 global automat ic block transmission control register c0gmabt r/w ? ? 0000h ff68h can0 module last out-pointer register c0lopt r ? ? undefined ff6eh can0 global clock sele ct register c0gmcs r/w ? ? 0fh ff6fh can0 global automat ic block transmission delay setting register c0gmabtd r/w ? ? 00h ff70h c0mask1l ff72h can0 module mask 1 register c0mask1h r/w ? ? undefined ff74h c0mask2l ff76h can0 module mask 2 register c0mask2h r/w ? ? undefined ff78h c0mask3l ff7ah can0 module mask 3 register c0mask3h r/w ? ? undefined ff7ch c0mask4l ff7eh can0 module mask 4 register c0mask4h r/w ? ? undefined ff8ah can0 module time stamp register c0ts r/w ? ? 0000h ff90h can0 module control register c0ctrl r/w ? ? 0000h ff92h can0 module last error information register c0lec r/w ? ? 00h ff93h can0 module information register c0info r ? ? 00h ff94h can0 module error counter register c0erc r ? ? 0000h ff96h can0 module interrupt enable register c0ie r/w ? ? 0000h ff98h can0 module interrupt status register c0ints r/w ? ? 0000h ff9ch can0 module bit rate register c0btr r/w ? ? 370fh ff9eh can0 module bit rate pr escaler register c0brp r/w ? ? ffh ff9fh can0 module last in-pointer register c0lipt r ? ? undefined chapter 16 can controller user?s manual u17553ej4v0ud 413 16.5.3 register bit configuration table 16-17. bit configurat ion of can global registers address symbol bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 ff64h 0 0 0 0 0 0 0 clear gom ff65h c0gmctrl(w) 0 0 0 0 0 0 set efsd set gom ff64h c0gmctrl(r) 0 0 0 0 0 0 efsd gom ff65h mbon 0 0 0 0 0 0 0 ff66h c0gmabt(w) 0 0 0 0 0 0 0 clear abttrg ff67h 0 0 0 0 0 0 set abtclr set abttrg ff66h c0gmabt(r) 0 0 0 0 0 0 abtclr abttrg ff67h 0 0 0 0 0 0 0 0 ff6eh c0gmcs 0 0 0 0 ccp3 ccp2 ccp1 ccp0 ff6fh c0gmabtd 0 0 0 0 abtd3 abtd2 abtd1 abtd0 caution the actual register addr ess is calculated as follows: register address = global register area offset (ch dependent) + offset addr ess as listed in table above remark (r) when read (w) when write chapter 16 can controller user?s manual u17553ej4v0ud 414 table 16-18. bit configuration of can module registers (1/2) address symbol bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 ff60h c0rgpt(w) 0 0 0 0 0 0 0 clear rovf ff61h 0 0 0 0 0 0 0 0 ff60h c0rgpt(r) 0 0 0 0 0 0 rhpm rovf ff61h rgpt[7:0] ff62h c0lopt lopt[7:0] ff64h c0tgpt(w) 0 0 0 0 0 0 0 clear tovf ff65h 0 0 0 0 0 0 0 0 ff64h c0tgpt(r) 0 0 0 0 0 0 thpm tovf ff65h tgpt[7:0] ff70h cm1id [7:0] ff71h c0mask1l cm1id [15:8] ff72h c0mask1h cm1id [23:16] ff73h 0 0 0 cm1id [28:24] ff74h c0mask2l cm2id [7:0] ff75h cm2id [15:8] ff76h c0mask2h cm2id [23:16] ff77h 0 0 0 cm2id [28:24] ff78h c0mask3l cm3id [7:0] ff79h cm3id [15:8] ff7ah c0mask3h cm3id [23:16] ff7bh 0 0 0 cm3id [28:24] ff7ch c0mask4l cm4id [7:0] ff7dh cm4id [15:8] ff7eh c0mask4h cm4id [23:16] ff7fh 0 0 0 cm4id [28:24] ff8ah c0ts(w) 0 0 0 0 0 clear tslock clear tssel clear tsen ff8bh 0 0 0 0 0 set tslock set tssel set tsen ff8ah c0ts(r) 0 0 0 0 0 tslock tssel tsen ff8bh 0 0 0 0 0 0 0 0 caution the actual register addr ess is calculated as follows: register address = global register area offset (ch dependent) + offset addr ess as listed in table above remark (r) when read (w) when write chapter 16 can controller user?s manual u17553ej4v0ud 415 table 16-18. bit configuration of can module registers (2/2) address symbol bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 ff90h c0ctrl(w) clear ccerc clear al clear valid clear psmode 1 clear psmode 0 clear opmode 2 clear opmode 1 clear opmode 0 ff91h set ccerc set al 0 set psmode 1 set psmode 0 set opmode 2 set opmode 1 set opmode 0 ff90h c0ctrl(r) ccerc al valid ps mode1 ps mode0 op mode2 op mode1 op mode0 ff91h 0 0 0 0 0 0 rstat tstat ff92h c0lec(w) 0 0 0 0 0 0 0 0 ff92h c0lec(r) 0 0 0 0 0 lec2 lec1 lec0 ff93h c0info 0 0 0 boff tecs1 tecs0 recs1 recs0 ff94h c0erc tec[7:0] ff95h rec[7:0] ff96h c0ie(w) 0 0 clear cie5 clear cie4 cl ear cie3 clear cie2 clear cie1 clear cie0 ff97h 0 0 set cie5 set cie4 set cie3 set cie2 set cie1 set cie0 ff96h c0ie(r) 0 0 cie5 cie4 cie3 cie2 cie1 cie0 ff97h 0 0 0 0 0 0 0 0 ff98h c0ints(w) 0 0 clear cints5 clear cints4 clear cints3 clear cints2 clear cints1 clear cints0 ff99h 0 0 0 0 0 0 0 0 ff98h c0ints(r) 0 0 cints5 cints4 cints3 cints2 cints1 cints0 ff99h 0 0 0 0 0 0 0 0 ff9ch c0btr 0 0 0 0 tseg1[3:0] ff9dh 0 0 sjw[1:0] 0 tseg2[2:0] ff9eh c0brp tqprs[7:0] ff9fh c0lipt lipt[7:0] caution the actual register addr ess is calculated as follows: register address = global register area offset (ch dependent) + offset addr ess as listed in table above remark (r) when read (w) when write chapter 16 can controller user?s manual u17553ej4v0ud 416 table 16-19. bit configurati on of message buffer registers address symbol bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 fax0h message data (byte 0) fax1h c0mdata01m message data (byte 1) fax0h c0mdata0m message data (byte 0) fax1h c0mdata1m message data (byte 1) fax2h c0mdata23m message data (byte 2) fax3h message data (byte 3) fax2h c0mdata2m message data (byte 2) fax3h c0mdata3m message data (byte 3) fax4h c0mdata45m message data (byte 4) fax5h message data (byte 5) fax4h c0mdata4m message data (byte 4) fax5h c0mdata5m message data (byte 5) fax6h c0mdata67m message data (byte 6) fax7h message data (byte 7) fax6h c0mdata6m message data (byte 6) fax7h c0mdata7m message data (byte 7) fax8h c0mdlcm 0 0 0 0 mdlc3 mdlc2 mdlc1 mdlc0 fax9h c0mconfm ows rtr mt2 mt1 mt0 0 0 ma0 faxah id7 id6 id5 id4 id3 id2 id1 id0 faxbh c0midlm id15 id14 id13 id12 id11 id10 id9 id8 faxch id23 id22 id21 id20 id19 id18 id17 id16 faxdh c0midhm ide 0 0 id28 id27 id26 id25 id24 faxeh 0 0 0 clear mow clear ie clear dn clear trq clear rdy faxfh c0mctrlm (w) 0 0 0 0 set ie 0 set trq set rdy faxeh 0 0 0 mow ie dn trq rdy faxfh c0mctrlm (r) 0 0 muc 0 0 0 0 0 caution the actual register addr ess is calculated as follows: register address = global register area offset (ch dependent) + offset addr ess as listed in table above remarks 1. (r) when read (w) when write 2. m = 0 to 15 chapter 16 can controller user?s manual u17553ej4v0ud 417 16.6 bit set/clear function the can control registers include registers whose bits can be set or cleared via the cpu and via the can interface. an operation error occurs if the following registers are written directly. do not write any values directly via bit manipulation, read/modify/write, or direct writing of target values. ? can global control register (c0gmctrl) ? can global automatic block trans mission control register (c0gmabt) ? can module control register (c0ctrl) ? can module interrupt enable register (c0ie) ? can module interrupt status register (c0ints) ? can module receive history list register (c0rgpt) ? can module transmit history list register (c0tgpt) ? can module time stamp register (c0ts) ? can message control register (c0mctrlm) remark m = 0 to 15 all the 16 bits in the above registers can be read via th e usual method. use the procedure described in figure 16- 23 below to set or clear the lower 8 bits in these registers. setting or clearing of lower 8 bits in the above registers is performed in combination with the higher 8 bits (refer to the 16-bit data after a write operation in figure 16-24 ). figure 16-23 shows how the values of set bits or clear bits relate to set/clear/no change operations in the corresponding register. figure 16-23. example of bi t setting/clearing operations 0000000011010001 0000101111011000 set00001011 0000000000000011 clear 11011000 set set no change no change clear no change clear clear bit status register?s current values write values register?s value after write operations chapter 16 can controller user?s manual u17553ej4v0ud 418 figure 16-24. 16-bit data during write operation 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 set 7 set 6 set 5 set 4 set 3 set 2 set 1 set 0 clear 7 c lear 6 clear 5 clear 4 clear 3 clear 2 clear 1 clear 0 set n clear n status of bit n after bit set/clear operation 0 0 no change 0 1 0 1 0 1 1 1 no change remark n = 0 to 7 chapter 16 can controller user?s manual u17553ej4v0ud 419 16.7 control registers remark m = 0 to 15 (1) can global control register (c0gmctrl) the c0gmctrl register is used to cont rol the operation of the can module. after reset: 0000h r/w address: ff64h, ff65h (a) read 15 14 13 12 11 10 9 8 c0gmctrl mbon 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 efsd gom (b) write 15 14 13 12 11 10 9 8 c0gmctrl 0 0 0 0 0 0 set efsd set gom 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 clear gom (a) read mbon bit enabling access to message buffer register, transmit/receive hist ory list registers 0 write access and read access to the message buff er register and the transmit/receive history list registers is disabled. 1 write access and read access to the message buff er register and the transmit/receive history list registers is enabled. cautions 1. while the mbon bit is cleared (to 0), software access to the message buffers (c0mdata0m, c0mdata1m, c0mdat a01m, c0mdata2m, c0mdata3m, c0mdata23m, c0mdata4m, c0mdat a5m, c0mdata45m, c0mdata6m, c0mdata7m, c0mdata67m, c0mdlcm, c0mconfm, c0midlm, c0midhm, and c0mctrlm), or register s related to transmit history or receive history (c0lopt, c0tgpt, c0lipt, and c0rgpt) is disabled. 2. this bit is read-only. even if 1 is written to mbon while it is 0, the value of mbon does not change, and access to the message buffer registers, or registers related to transmit histor y or receive history remains disabled. remark mbon bit is cleared (to 0) when the ca n module enters can sleep mode/can stop mode or gom bit is cleared (to 0). mbon bit is set (to 1) when the can sl eep mode/the can stop mode is released or gom bit is set (to 1). chapter 16 can controller user?s manual u17553ej4v0ud 420 efsd bit enabling forced shut down 0 forced shut down by gom = 0 disabled. 1 forced shut down by gom = 0 enabled. caution to request forced shutdown, the gom bit must be cleared to 0 in a subsequent, immediately following write access after the efsd bit has been set to 1. if access to another register (including readi ng the c0gmctrl register) is executed without clearing the gom bit immediately a fter the efsd bit has been set to 1, the efsd bit is forcibly cl eared to 0, and the forced shutdown request is invalid. gom global operation mode bit 0 can module is disabled from operating. 1 can module is enabled to operate. caution the gom bit can be cleared only in the initialization mode or immediately after efsd bit is set (to 1). (b) write set efsd efsd bit setting 0 no change in esfd bit . 1 efsd bit set to 1. set gom clear gom gom bit setting 0 1 gom bit cleared to 0. 1 0 gom bit set to 1. other than above no change in gom bit. caution set gom bit and esfd bit always separately. chapter 16 can controller user?s manual u17553ej4v0ud 421 (2) can global clock selection register (c0gmcs) the c0gmcs register is used to select the can module system clock. after reset: 0fh r/w address: ff6eh 7 6 5 4 3 2 1 0 c0gmcs 0 0 0 0 ccp3 ccp2 ccp1 ccp0 ccp3 ccp2 ccp1 ccp1 can module system clock (f canmod ) 0 0 0 0 f can /1 0 0 0 1 f can /2 0 0 1 0 f can /3 0 0 1 1 f can /4 0 1 0 0 f can /5 0 1 0 1 f can /6 0 1 1 0 f can /7 0 1 1 1 f can /8 1 0 0 0 f can /9 1 0 0 1 f can /10 1 0 1 0 f can /11 1 0 1 1 f can /12 1 1 0 0 f can /13 1 1 0 1 f can /14 1 1 1 0 f can /15 1 1 1 1 f can /16 (default value) remark f can = clock supplied to can chapter 16 can controller user?s manual u17553ej4v0ud 422 (3) can global automatic block transm ission control register (c0gmabt) the c0gmabt register is used to control the automatic block transmission (abt) operation. after reset: 0000h r/w address: ff66h, ff67h (a) read 15 14 13 12 11 10 9 8 c0gmabt 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 abtclr abttrg (b) write 15 14 13 12 11 10 9 8 c0gmabt 0 0 0 0 0 0 set abtclr set abttrg 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 clear abttrg caution before changing the normal operati on mode with abt to the initialization mode, be sure to set the c0gmabt regist er to the default value (0000h). (a) read abtclr automatic block transmis sion engine clear status bit 0 clearing the automatic transmission engine is completed. 1 the automatic transmissi on engine is being cleared. remarks 1. set the abtclr bit to 1 while the abttrg bit is cleared (0). the operation is not guaranteed if the abt clr bit is set to 1 while the abttrg bit is set to 1. 2. when the automatic block transmission engine is cleared by setting the abtclr bit to 1, the abtclr bit is automatically cleared to 0 as soon as the requested clearing processing is complete. abttrg automatic block tr ansmission status bit 0 automatic block transmission is stopped. 1 automatic block transmissi on is under execution. caution do not set the abttrg bit (abttrg = 1) in the initialization mode. if the abttrg bit is set in the initialization mode, the operation is not guaranteed after the can module has entered the normal operation mode with abt. chapter 16 can controller user?s manual u17553ej4v0ud 423 (b) write set abtclr automatic block transm ission engine clear request bit 0 the automatic block transmission engine is in idle state or under operation. 1 request to clear the automatic block tran smission engine. after the automatic block transmission engine has been cleared, automatic block transmission is started from message buffer 0 by setting the abttrg bit to 1. set abttrg clear abttrg automatic block tran smission start bit 0 1 request to stop automatic block transmission. 1 0 request to start automatic block transmission. other than above no change in abttrg bit. chapter 16 can controller user?s manual u17553ej4v0ud 424 (4) can global automatic block transmissi on delay setting register (c0gmabtd) the c0gmabtd register is used to set the interval at which the data of the message buffer assigned to abt is to be transmitted in the normal operation mode with abt. after reset: 00h r/w address: ff6fh 7 6 5 4 3 2 1 0 c0gmabtd 0 0 0 0 abtd3 abtd2 abtd1 abtd0 abtd3 abtd2 abtd1 abtd0 data frame interv al during automatic bl ock transmission (unit: data bit time (dbt)) 0 0 0 0 0 dbt (default value) 0 0 0 1 2 5 dbt 0 0 1 0 2 6 dbt 0 0 1 1 2 7 dbt 0 1 0 0 2 8 dbt 0 1 0 1 2 9 dbt 0 1 1 0 2 10 dbt 0 1 1 1 2 11 dbt 1 0 0 0 2 12 dbt other than above setting prohibited cautions 1. do not change the contents of the c0gmabtd register while the abttrg bit is set to 1. 2. the timing at which the abt m essage is actually transmitted onto the can bus differs depending on the status of transmission from the other station or how a request to transmit a messag e other than an abt message (message buffers 8 to 15) is made. chapter 16 can controller user?s manual u17553ej4v0ud 425 (5) can module mask control register (c0mas kal, c0maskah) (a = 1, 2, 3, or 4) the c0maskal and c0maskah registers are used to ex tend the number of receivable messages into the same message buffer by masking part of the id com parison of a message and invalidating the id of the masked part. - can module mask 1 register (c0mask1l, c0mask1h) after reset: undefined r/w address: c0mask1l ff70h, ff71h c0mask1h ff72h, ff73h 15 14 13 12 11 10 9 8 c0mask1l cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 7 6 5 4 3 2 1 0 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 15 14 13 12 11 10 9 8 c0mask1h 0 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 7 6 5 4 3 2 1 0 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16 - can module mask 2 register (c0mask2l, c0mask2h) after reset: undefined r/w address: c0mask2l ff74h, ff75h c0mask2h ff76h, ff77h 15 14 13 12 11 10 9 8 c0mask2l cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 7 6 5 4 3 2 1 0 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 15 14 13 12 11 10 9 8 c0mask2h 0 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 7 6 5 4 3 2 1 0 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16 chapter 16 can controller user?s manual u17553ej4v0ud 426 - can module mask 3 register (c0mask3l, c0mask3h) after reset: undefined r/w address: c0mask3l ff78h, ff79h c0mask3h ff7ah, ff7bh 15 14 13 12 11 10 9 8 c0mask3l cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 7 6 5 4 3 2 1 0 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 15 14 13 12 11 10 9 8 c0mask3h 0 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 7 6 5 4 3 2 1 0 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16 - can module mask 4 register (c0mask4l, c0mask4h) after reset: undefined r/w address: c0mask4l ff7ch, ff7dh c0mask4h ff7eh, ff7fh 15 14 13 12 11 10 9 8 c0mask4l cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 7 6 5 4 3 2 1 0 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 15 14 13 12 11 10 9 8 c0mask4h 0 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 7 6 5 4 3 2 1 0 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16 cmid28-cmid0 sets mask pattern of id bit. 0 the id bits of the message buffer set by the cmid28 to cmid0 bits are compared with the id bits of the received message frame. 1 the id bits of the message buffer set by the cmid28 to cmid0 bits are not compared with the id bits of the received message frame (they are masked). remark masking is always defined by an id length of 29 bits. if a mask is assigned to a message with a standard id, cmid17 to cmid0 are igno red. therefore, only cmid28 to cmid18 of the received id are masked. the same mask can be used for both the standard and extended ids. chapter 16 can controller user?s manual u17553ej4v0ud 427 (6) can module control register (c0ctrl) the c0ctrl register is used to control the operation mode of the can module. after reset: 0000h r/w address: ff90h, ff91h (a) read 15 14 13 12 11 10 9 8 c0ctrl 0 0 0 0 0 0 rstat tstat 7 6 5 4 3 2 1 0 ccerc al valid psmode1 psmode0 opmode2 opmode1 opmode0 (b) write 15 14 13 12 11 10 9 8 c0ctrl set ccerc set al 0 set psmode1 set psmode0 set opmode2 set opmode1 set opmode0 7 6 5 4 3 2 1 0 clear ccerc clear al clear valid clear psmode1 clear psmode0 clear opmode2 clear opmode1 clear opmode0 (a) read rstat reception status bit 0 reception is stopped. 1 reception is in progress. remark - the rstat bit is set to 1 under the following conditions (timing). - the sof bit of a receive frame is detected - on occurrence of arbitration loss during a transmit frame - the rstat bit is cleared to 0 under the following conditions (timing) - when a recessive level is detected at the second bit of the interframe space - on transition to the initialization mode at the first bit of the interframe space chapter 16 can controller user?s manual u17553ej4v0ud 428 tstat transmission status bit 0 transmission is stopped. 1 transmission is in progress. remark - the tstat bit is set to 1 under the following conditions (timing). - the sof bit of a transmit frame is detected - the first bit of an error flag is detected during a transmit frame - the tstat bit is cleared to 0 under the following conditions (timing). - during transition to bus-off state - on occurrence of arbitration loss in transmit frame - on detection of recessive level at the second bit of the interframe space - on transition to the initialization mode at the first bit of the interframe space ccerc error counter clear bit 0 the c0erc and c0info registers are not cleared in the initialization mode. 1 the c0erc and c0info registers are cleared in the initialization mode. remarks 1. the ccerc bit is used to clear the c0erc and c0info registers for re-initialization or forced recovery from the bus-off state. this bit can be set to 1 only in the initialization mode. 2. when the c0erc and c0info registers have been cleared, the ccerc bit is also cleared to 0 automatically. 3. the ccerc bit can be set to 1 at the same time as a request to change the initialization mode to an operation mode is made.4. the ccerc bit is read-only in the can sleep mode or can stop mode. 4. the receive data may be corrupted in case of setting the ccerc bit to (1) immediately after entering the init mode from self-test mode. al bit to set operation in case of arbitration loss 0 re-transmission is not executed in case of an arbitration loss in the single-shot mode. 1 re-transmission is executed in case of an arbitration loss in the single-shot mode. remark the al bit is valid only in the single-shot mode. valid valid receive message frame detection bit 0 a valid message frame has not been received since the valid bit was last cleared to 0. 1 a valid message frame has been received since the valid bit was last cleared to 0. remarks 1 . detection of a valid receive message frame is not dependent upon storage in the receive message buffer (data frame) or transmit message buffer (remote frame). 2. clear the valid bit (0) before changing the initialization mode to an operation mode. 3 . if only two can nodes are connected to the can bus with one transmitting a message frame in the normal operation mo de and the other in the receive-only mode, the valid bit is not set to 1 before the transmitting node enters the error passive state, because in receive-only mode no acknowledge is generated. 4. in order to clear the valid bit, set the cl ear valid bit to 1 first and confirm that the valid bit is cleared. if it is not cleared, perform clearing processing again. chapter 16 can controller user?s manual u17553ej4v0ud 429 psmode1 psmode0 power save mode 0 0 no power save mode is selected. 0 1 can sleep mode 1 0 setting prohibited 1 1 can stop mode cautions 1. transition to and from the can stop mode must be made via can sleep mode. a request for direct transition to a nd from the can stop mode is ignored. 2. the mbon flag of c0gmctrl must be checked after releasing a power save mode, prior to access the message buffers again. 3. can sleep mode requests are kept pending, until cancelle d by software or entered on appropriate bus condition (bus idle). software can check the actual status by reading psmode. opmode2 opmode1 opmo de0 operation mode 0 0 0 no operation mode is selected (can module is in the initialization mode). 0 0 1 normal operation mode 0 1 0 normal operation mode with aut omatic block transmission function (normal operation mode with abt) 0 1 1 receive-only mode 1 0 0 single-shot mode 1 0 1 self-test mode other than above setting prohibited caution transit to initialization mode or pow er saving modes may take some time. be sure to verify the success of mode change by reading the values, before proceeding. remark the opmode[2:0] bits are read-only in the can sleep mode or can stop mode. (b)write set ccerc clear ccerc setting of ccerc bit 1 1 ccerc bit is set to 1. other than above 0 ccerc bit is not changed. set al clear al setting of al bit 0 1 al bit is cleared to 0. 1 0 al bit is set to 1. other than above al bit is not changed. chapter 16 can controller user?s manual u17553ej4v0ud 430 clear valid setting of valid bit 0 valid bit is not changed. 1 valid bit is cleared to 0. set psmode0 clear psmode0 setting of psmode0 bit 0 1 psmode0 bit is cleared to 0. 1 0 psmode bit is set to 1. other than above psmode0 bit is not changed. set psmode1 clear psmode1 setting of psmode1 bit 0 1 psmode1 bit is cleared to 0. 1 0 psmode1 bit is set to 1. other than above psmode1 bit is not changed. set opmode0 clear opmode0 setting of opmode0 bit 0 1 opmode0 bit is cleared to 0. 1 0 opmode0 bit is set to 1. other than above opmode0 bit is not changed. set opmode1 clear opmode1 setting of opmode1 bit 0 1 opmode1 bit is cleared to 0. 1 0 opmode1 bit is set to 1. other than above opmode1 bit is not changed. set opmode2 clear opmode2 setting of opmode2 bit 0 1 opmode2 bit is cleared to 0. 1 0 opmode2 bit is set to 1. other than above opmode2 bit is not changed. chapter 16 can controller user?s manual u17553ej4v0ud 431 (7) can module last error code register (c0lec) the c0lec register provides the erro r information of the can protocol. after reset: 00h r/w address: ff92h 7 6 5 4 3 2 1 0 c0lec 0 0 0 0 0 lec2 lec1 lec0 remarks 1. the contents of the c0lec register are not cleared when the can module changes from an operation mode to the initialization mode. 2. if an attempt is made to write a value other than 00h to the c0lec register by software, the access is ignored. lec2 lec1 lec0 last can protocol error information 0 0 0 no error 0 0 1 stuff error 0 1 0 form error 0 1 1 ack error 1 0 0 bit error (the can module tried to trans mit a recessive-level bit as part of a transmit message (except the arbitration field), but the value on the can bus is a domi nant-level bit.) 1 0 1 bit error (the can module tried to tr ansmit a dominant-level bit as part of a transmit message, ack bit, error frame, or overload frame, but the value on the can bus is a recessive-level bit.) 1 1 0 crc error 1 1 1 undefined chapter 16 can controller user?s manual u17553ej4v0ud 432 (8) can module information register (c0info) the c0info register indicates the status of the can module. after reset: 00h r address: ff93h 7 6 5 4 3 2 1 0 c0info 0 0 0 boff tecs1 tecs0 recs1 recs0 boff bus-off state bit 0 not bus-off state (transmit error counter 255) (the value of the transmit counter is less than 256.) 1 bus-off state (transmit error counter > 255) (the value of the transmit counter is 256 or more.) tecs1 tecs0 transmission error counter status bit 0 0 the value of the transmission error counter is less than that of the warning level (<96). 0 1 the value of the transmission error counter is in the range of the warning level (96 to 127). 1 0 undefined 1 1 the value of the transmission error counter is in the range of the error passive or bus- off state ( 128). recs1 recs0 reception error counter status bit 0 0 the value of the reception error counter is less than that of the warning level (<96). 0 1 the value of the reception error counter is in the range of the warning level (96 to 127). 1 0 undefined 1 1 the value of the reception error c ounter is in the error passive range ( 128). chapter 16 can controller user?s manual u17553ej4v0ud 433 (9) can module error counter register (c0erc) the c0erc register indicates the count value of the transmission/reception error counter. after reset: 0000h r address: ff94h, ff95h 15 14 13 12 11 10 9 8 c0erc reps rec6 rec5 rec4 rec3 rec2 rec1 rec0 7 6 5 4 3 2 1 0 tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 reps reception error passive status bit 0 reception error counter is not error passive (<128) 1 reception error counter is error passive range ( 128) rec6-rec0 reception error counter bit 0-127 number of reception errors. these bits reflect the status of the reception error counter. the number of errors is defined by the can protocol. remark rec6 to rec0 of the reception error count er are invalid in the reception error passive state (recs [1:0] = 11b). tec7-tec0 transmission error counter bit 0-255 number of transmission errors. these bits reflect the status of the transmission error counter. the number of errors is defined by the can protocol. remark tec7 to tec0 of the transmission error c ounter are invalid in the bus-off state (boff = 1). chapter 16 can controller user?s manual u17553ej4v0ud 434 (10) can module interrupt en able register (c0ie) the c0ie register is used to enable or disable the interrupts of the can module. after reset: 0000h r/w address: ff96h, ff97h (a) read 15 14 13 12 11 10 9 8 c0ie 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 cie5 cie4 cie3 cie2 cie1 cie0 (b) write 15 14 13 12 11 10 9 8 c0ie 0 0 set cie5 set cie4 set cie3 set cie2 set cie1 set cie0 7 6 5 4 3 2 1 0 0 0 clear cie5 clear cie4 clear cie3 clear cie2 clear cie1 clear cie0 (a) read cie5-cie0 can module interrupt enable bit 0 output of the interrupt corresponding to interru pt status register cintsx bit is disabled. 1 output of the interrupt corresponding to interrupt status register cintsx bit is enabled. (b) write set cie5 clear cie5 setting of cie5 bit 0 1 cie5 bit is cleared to 0. 1 0 cie5 bit is set to 1. other than above cie5 bit is not changed. set cie4 clear cie4 setting of cie4 bit 0 1 cie4 bit is cleared to 0. 1 0 cie4 bit is set to 1. other than above cie4 bit is not changed. set cie3 clear cie3 setting of cie bit 0 1 cie3 bit is cleared to 0. 1 0 cie3 bit is set to 1. other than above cie3 bit is not changed. chapter 16 can controller user?s manual u17553ej4v0ud 435 set cie2 clear cie2 setting of cie2 bit 0 1 cie2 bit is cleared to 0. 1 0 cie2 bit is set to 1. other than above cie2 bit is not changed. set cie1 clear cie1 setting of cie1 bit 0 1 cie1 bit is cleared to 0. 1 0 cie1 bit is set to 1. other than above cie1 bit is not changed. set cie0 clear cie0 setting of cie0 bit 0 1 cie0 bit is cleared to 0. 1 0 cie0 bit is set to 1. other than above cie0 bit is not changed. chapter 16 can controller user?s manual u17553ej4v0ud 436 (11) can module interrupt st atus register (c0ints) the c0ints register indicates the in terrupt status of the can module. after reset: 0000h r/w address: ff98h, ff99h (a) read 15 14 13 12 11 10 9 8 c0ints 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 cints5 cints4 cints3 cints2 cints1 cints0 (b) write 15 14 13 12 11 10 9 8 c0ints 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 clear cints5 clear cints4 clear cints3 clear cints2 clear cints1 clear cints0 (a) read cints5-cints0 can interrupt status bit 0 no related interrupt source event is pending. 1 a related interrupt source event is pending. interrupt status bit related interrupt source event cints5 wakeup interrupt from can sleep mode note cints4 arbitration loss interrupt cints3 can protocol error interrupt cints2 can error status interrupt cints1 interrupt on completion of reception of valid message frame to message buffer m cints0 interrupt on normal completion of tr ansmission of message frame from message buffer m note the cints5 bit is set only when the ca n module is woken up from the can sleep mode by a can bus operation. the cints5 bit is not set when the can sleep mode has been released by software. (b) write clear cints5-cints0 setting of cints5 to cints0 bits 0 cints5 to cints0 bits are not changed. 1 cints5 to cints0 bits are cleared to 0. caution please clear the status bit of this regi ster with software when the confirmation of each status is necessary in the interrupt processing, because these bits are not cleared automatically. chapter 16 can controller user?s manual u17553ej4v0ud 437 (12) can module bit rate prescaler register (c0brp) the c0brp register is used to select the can protocol layer basic clock (f tq ). the communication baud rate is set to the c0btr register. after reset: ffh r/w address: ff9eh 7 6 5 4 3 2 1 0 c0brp tqprs7 tqprs6 tqprs5 tqprs4 tqprs3 tqprs2 tqprs1 tqprs0 tqprs7-tqprs0 can protocol layer basic system clock (f tq ) 0 f canmod /1 1 f canmod /2 : : n f canmod /(n+1) : : 255 f canmod /256 (default value) figure 16-25. can module clock ccp 3 ccp2 prescaler can module bit-rate prescaler register (c0brp) can module clock selection register (c0gmcs) baud rate generator can bit-rate register (c0btr) ccp1 ccp0 tqprs0 f can f canmod f tq 0 0 0 0 tqprs1 tqprs2 tqprs3 tqprs4 tqprs5 tqprs6 tqprs7 caution the c0brp register can be writ e-accessed only in the initialization mode. remark f can : clock supplied to can (f prs ) f canmod : can module system clock f tq : can protocol layer basic system clock chapter 16 can controller user?s manual u17553ej4v0ud 438 (13) can module bit rate register (c0btr) the c0btr register is used to control the data bit time of the communication baud rate. after reset: 370fh r/w address: ff9ch, ff9dh 15 14 13 12 11 10 9 8 c0btr 0 0 sjw1 sjw0 0 tseg22 tseg21 tseg20 7 6 5 4 3 2 1 0 0 0 0 0 tseg13 t seg12 tseg11 tseg10 figure 16-26. data bit time data bit time (dbt) time segmet 1(tseg1) phase segment 2 phase segment 1 sample point(spt) prop segment sync segment time segmet 2(tseg2) chapter 16 can controller user?s manual u17553ej4v0ud 439 sjw1 sjw0 length of synchronization jump width 0 0 1tq 0 1 2tq 1 0 3tq 1 1 4tq (default value) tseg22 tseg21 tseg20 length of time segment 2 0 0 0 1tq 0 0 1 2tq 0 1 0 3tq 0 1 1 4tq 1 0 0 5tq 1 0 1 6tq 1 1 0 7tq 1 1 1 8tq (default value) tseg13 tseg12 tseg 11 tseg10 length of time segment 1 0 0 0 0 setting prohibited 0 0 0 1 2tq note 0 0 1 0 3tq note 0 0 1 1 4tq 0 1 0 0 5tq 0 1 0 1 6tq 0 1 1 0 7tq 0 1 1 1 8tq 1 0 0 0 9tq 1 0 0 1 10tq 1 0 1 0 11tq 1 0 1 1 12tq 1 1 0 0 13tq 1 1 0 1 14tq 1 1 1 0 15tq 1 1 1 1 16tq (default value) note this setting must not be made when the c0brp register = 00h. remark tq = 1/f tq (f tq : can protocol layer basic system clock) chapter 16 can controller user?s manual u17553ej4v0ud 440 (14) can module last in-pointer register (c0lipt) the c0lipt register indicates the number of the message buffer in which a data frame or a remote frame was last stored. after reset: undefined r address: ff9fh 7 6 5 4 3 2 1 0 c0lipt lipt7 lipt6 lipt5 lipt 4 lipt3 lipt2 lipt1 lipt0 lipt7-lipt0 last in-pointer register (c0lipt) 0 to 15 when the c0lipt register is read, the contents of the element indexed by the last in- pointer (lipt) of the receive history list are read. these contents indicate the number of the message buffer in which a data frame or a remote frame was last stored. remark the read value of the c0lipt register is undefined if a data frame or a remote frame has never been stored in the message buffer. if the rhpm bit of the c0rgpt register is set to 1 after the can module has changed from the initialization mode to an operation mode, therefore, the read value of the c0lipt register is undefined. chapter 16 can controller user?s manual u17553ej4v0ud 441 (15) can module receive history list register (c0rgpt) the c0rgpt register is used to read the receive history list. after reset: xx02h r/w address: ff60h, ff61h (a) read 15 14 13 12 11 10 9 8 c0rgpt rgpt7 rgpt6 rgpt5 rgpt 4 rgpt3 rgpt2 rgpt1 rgpt0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 rhpm rovf (b) write 15 14 13 12 11 10 9 8 c0rgpt 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 clear rovf (a) read rgpt7-rgpt0 receive history list get pointer 0 to 15 when the c0rgpt register is read, the contents of the element indexed by the receive history list get pointer (rgpt) of the rece ive history list are read. these contents indicate the number of the message buffer in which a data frame or a remote frame has been stored. rhpm note receive history list pointer match 0 the receive history list has at least one message buffer number that has not been read. 1 the receive history list has no message buffer numbers that has not been read. note the read value of rgpt0 to rg pt7 is invalid when rhpm = 1. rovf receive history list overflow bit 0 all the message buffer numbers that have not been read are preserved. all the numbers of the message buffer in which a new data frame or remote frame has been received and stored are recorded to the receive history list (the re ceive history list has a vacant element). 1 all the message buffer numbers that are recorded are preserved except the message buffer number recorded last note . the rhl is fully loaded with the unread message buffer number and all rhl elements beside the last one are preserved. message buffer number of subsequent data frame storage or remote frame assignment is alwa ys logged in the rhl element lipt pointer ?1 is pointing to. note that the rhl will be updated, but the lipt pointer will not be incremented. always the position the lipt pointer ?1 is pointing to is overwritten (the receive history list does not have a vacant element). note if rovf is set, rhpm is no longer cleared on message storage, but rhpm is still set, if all entries of c0rgpt are read by software. chapter 16 can controller user?s manual u17553ej4v0ud 442 (b) write clear rovf setting of rovf bit 0 rovf bit is not changed. 1 rovf bit is cleared to 0. (16) can module last out-pointer register (c0lopt) the c0lopt register indicates the number of the message buffer to whic h a data frame or a remote frame was transmitted last. after reset: undefined r address: ff68h 7 6 5 4 3 2 1 0 c0lopt lopt7 lopt6 lopt5 lopt4 lopt3 lo pt2 lopt1 lopt0 lopt7-lopt0 last out-pointer of transmit history list (lopt) 0 to 15 when the c0lopt register is read, the contents of the element indexed by the last out- pointer (lopt) of the receive history list ar e read. these contents indicate the number of the message buffer to which a data frame or a remote frame was transmitted last. remark the value read from the c0lopt register is undefined if a data frame or remote frame has never been transmitted from a message buffer. if the thpm bit is set to 1 after the can module has changed from the initializa tion mode to an operation mode, therefore, the read value of the c0lopt register is undefined. chapter 16 can controller user?s manual u17553ej4v0ud 443 (17) can module transmit history list register (c0tgpt) the c0tgpt register is used to read the transmit history list. after reset: xx02h r/w address: ff62h, ff63h (a) read 15 14 13 12 11 10 9 8 c0tgpt tgpt7 tgpt6 tgpt5 tgpt 4 tgpt3 tgpt2 tgpt1 tgpt0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 thpm tovf (b) write 15 14 13 12 11 10 9 8 c0tgpt 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 clear tovf (a) read tgpt7-tgpt0 transmit history list read pointer 0 to 15 when the c0tgpt register is read, t he contents of the element indexed by the read pointer (tgpt) of the transmit history list ar e read. these contents indicate the number of the message buffer to which a data frame or a remote frame was transmitted last. thpm note transmit history pointer match 0 the transmit history list has at least one message buffer number that has not been read. 1 the transmit history list has no message buffer number that has not been read. note the read value of tgpt0 to tg pt7 is invalid when thpm = 1. tovf transmit history list overflow bit 0 all the message buffer numbers that have not been read are preserved. all the numbers of the message buffers to which a new data frame or remote frame has been transmitted are recorded to the transmit history list (the transmit history list has a vacant element). 1 at least 7 entries have been stored since t he host processor has serviced the thl last time (i.e. read cntgpt). the first 6 entries are sequentially stored while the last entry can have been overwritten whenever a mess age is newly transmitted because all buffer numbers are stored at position lopt-1 when tovf bit is set. thus the sequence of transmissions can not be recovered completely now. note if tovf is set, thpm is no longer cleared on message transmission, but thpm is still set, if all entries of c0tgpt are read by software. remark transmission from message buffer 0 to 7 is not recorded to the transmit history list in the normal operation mode with abt. chapter 16 can controller user?s manual u17553ej4v0ud 444 (b) write clear tovf setting of tovf bit 0 tovf bit is not changed. 1 tovf bit is cleared to 0. (18) can module time stamp register (c0ts) the c0ts register is used to c ontrol the time stamp function. after reset: 0000h r/w address: ff8ah, ff8bh (a) read 15 14 13 12 11 10 9 8 c0ts 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 tslock tssel tsen (b) write 15 14 13 12 11 10 9 8 c0ts 0 0 0 0 0 set tslock set tssel set tsen 7 6 5 4 3 2 1 0 0 0 0 0 0 clear tslock clear tssel clear tsen remark the lock function of the time stamp f unction must not be used when the can module is in the normal operation mode with abt. (a) read tslock time stamp lock function enable bit 0 time stamp lock function stopped. the tsout signal is toggled each time the selected time stamp capture event occurs. 1 time stamp lock function enabled. the tsout signal is toggled each time the selected time stamp capture event occurs. however, the tsout output signal is locked when a data frame has been correctly received to message buffer 0 note . note the tsen bit is automatically cleared to 0. tssel time stamp capture event selection bit 0 the time stamp capture event is sof. 1 the time stamp capture event is the last bit of eof. chapter 16 can controller user?s manual u17553ej4v0ud 445 tsen tsout signal operation setting bit 0 disable tsout signal toggle operation. 1 enable tsout signal toggle operation. remark the signal tsout is output from the can macro to a timer resource, depending on implementation. refer to documentation of device implementation for details. (b) write set tslock clear tslock setting of tslock bit 0 1 tslock bit is cleared to 0. 1 0 tslock bit is set to 1. other than above tslock bit is not changed. set tssel clear tssel setting of tssel bit 0 1 tssel bit is cleared to 0. 1 0 tssel bit is set to 1. other than above tssel bit is not changed. set tsen clear tsen setting of tsen bit 0 1 tsen bit is cleared to 0. 1 0 tsen bit is set to 1. other than above tsen bit is not changed . chapter 16 can controller user?s manual u17553ej4v0ud 446 (19) can message data byte register (c0mdataxm)(x = 0 to 7), (c0mdatazm) (z = 01, 23, 45, 67) the c0mdataxm, c0mdatazm registers are used to store the data of a transmit/receive message. the c0mdatazm registers can access the c0mdataxm registers in 16-bit units. after reset: undefined r/w address: see table 16-16 - c0mdataxm register 7 6 5 4 3 2 1 0 c0mdata0m mdata07 mdata06 mdata05 mda ta04 mdata03 mdata02 mdata01 mdata00 7 6 5 4 3 2 1 0 c0mdata1m mdata17 mdata16 mdata15 mdata14 mdata13 mdata12 mdata11 mdata10 7 6 5 4 3 2 1 0 c0mdata2m mdata27 mdata26 mdata25 mda ta24 mdata23 mdata22 mdata21 mdata20 7 6 5 4 3 2 1 0 c0mdata3m mdata37 mdata36 mdata35 mdata34 mdata33 mdata32 mdata31 mdata30 7 6 5 4 3 2 1 0 c0mdata4m mdata47 mdata46 mdata45 mda ta44 mdata43 mdata42 mdata41 mdata40 7 6 5 4 3 2 1 0 c0mdata5m mdata57 mdata56 mdata55 mda ta54 mdata53 mdata52 mdata51 mdata50 7 6 5 4 3 2 1 0 c0mdata6m mdata67 mdata66 mdata65 mda ta64 mdata63 mdata62 mdata61 mdata60 7 6 5 4 3 2 1 0 c0mdata7m mdata77 mdata76 mdata75 mda ta74 mdata73 mdata72 mdata71 mdata70 chapter 16 can controller user?s manual u17553ej4v0ud 447 - c0mdatazm register 15 14 13 12 11 10 9 8 c0mdata01m mdata011 5 mdata011 4 mdata011 3 mdata011 2 mdata011 1 mdata011 0 mdata019 mdata018 7 6 5 4 3 2 1 0 mdata017 mdata016 mdata015 mdata014 mdata013 mdata012 mdata011 mdata010 15 14 13 12 11 10 9 8 c0mdata23m mdata231 5 mdata231 4 mdata231 3 mdata231 2 mdata231 1 mdata231 0 mdata239 mdata238 7 6 5 4 3 2 1 0 mdata237 mdata236 mdata235 mdata234 mdata233 mdata232 mdata231 mdata230 15 14 13 12 11 10 9 8 c0mdata45m mdata451 5 mdata451 4 mdata451 3 mdata451 2 mdata451 1 mdata451 0 mdata459 mdata458 7 6 5 4 3 2 1 0 mdata457 mdata456 mdata455 mdata454 mdata453 mdata452 mdata451 mdata450 15 14 13 12 11 10 9 8 c0mdata67m mdata671 5 mdata671 4 mdata671 3 mdata671 2 mdata671 1 mdata671 0 mdata679 mdata678 7 6 5 4 3 2 1 0 mdata677 mdata676 mdata675 mdata674 mdata673 mdata672 mdata671 mdata670 chapter 16 can controller user?s manual u17553ej4v0ud 448 (20) can message data length register m (c0mdlcm) the c0mdlcm register is used to set the number of bytes of the data field of a message buffer. after reset: 0000xxxxb r/w address: see table 16-16 7 6 5 4 3 2 1 0 c0mdlcm 0 0 0 0 mdlc3 mdlc2 mdlc1 mdlc0 mdlc3 mdlc2 mdlc1 mdlc0 data length of transmit/receive message 0 0 0 0 0 bytes 0 0 0 1 1 byte 0 0 1 0 2 bytes 0 0 1 1 3 bytes 0 1 0 0 4 bytes 0 1 0 1 5 bytes 0 1 1 0 6 bytes 0 1 1 1 7 bytes 1 0 0 0 8 bytes 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 setting prohibited (if these bits are set during transmi ssion, 8-byte data is transmitted regardless of the set dlc value when a data frame is transmitted. however, the dlc actually transmitted to the can bus is the dlc value set to this register.) note note the data and dlc value actually tr ansmitted to can bus are as follows. type of transmit frame length of transmit data dlc transmitted data frame number of bytes specified by dlc (however, 8 bytes if dlc 8) mdlc[3:0] remote frame 0 bytes cautions 1. be sure to set bits 7 to 4 0000b. 2. receive data is stored in as ma ny c0mdatax as the number of bytes (however, the upper limit is 8) correspond ing to dlc of the received frame. c0mdatax in which no data is stored is undefined. chapter 16 can controller user?s manual u17553ej4v0ud 449 (21) can message configurat ion register (c0mconfm) the c0mconfm register is used to specify t he type of the message buffer and to set a mask. after reset: undefined r/w address: see table 16-16 7 6 5 4 3 2 1 0 c0mconfm ows rtr mt2 mt1 mt0 0 0 ma0 ows overwrite control bit 0 the message buffer that has already received a data frame note is not overwritten by a newly received data frame. the newly received data frame is discarded. 1 the message buffer that has already received a data frame note is overwritten by a newly received data frame. note the ?message buffer that has already received a data frame? is a receive message buffer whose dn bit has been set to 1. remark a remote frame is received and stored, regardless of the setting of ows bit and dn bit. a remote frame that satisfies the other conditions (id matches, rtr = 0, trq = 0) is always received and stored in the corresponding message buffer (interrupt generated, dn flag set, mdlc[3:0] bits updated, and recorded to the receive history list). rtr remote frame request bit note 0 transmit a data frame. 1 transmit a remote frame. note the rtr bit specifies the type of message frame that is transmitted from a message buffer defined as a transmit message buffer.even if a valid remote frame has been received, rtr of the transmit message bu ffer that has received the frame remains cleared to 0.even if a remote frame whose id matches has been received from the can bus with the rtr bit of the transmit message bu ffer set to 1 to transmit a remote frame, that remote frame is not received or stor ed (interrupt generated, dn flag set, mdlc[3:0] bits updated, and recorded to the receive history list). mt2 mt1 mt0 message buffer type setting bit 0 0 0 transmit message buffer 0 0 1 receive message buffer (no mask setting) 0 1 0 receive message buffer (mask 1 set) 0 1 1 receive message buffer (mask 2 set) 1 0 0 receive message buffer (mask 3 set) 1 0 1 receive message buffer (mask 4 set) other than above setting prohibited chapter 16 can controller user?s manual u17553ej4v0ud 450 ma0 message buffer assignment bit 0 message buffer not used. 1 message buffer used. caution be sure to write 0 to bits 2 and 1. (22) can message id register m (c0midlm, c0midhm) the c0midlm and c0midhm registers ar e used to set an identifier (id). after reset: undefined r/w address: see table 16-16 15 14 13 12 11 10 9 8 c0midlm id15 id14 id13 id12 id11 id10 id9 id8 7 6 5 4 3 2 1 0 id7 id6 id5 id4 id3 id2 id1 id0 15 14 13 12 11 10 9 8 c0midhm ide 0 0 id28 id27 id26 id25 id24 7 6 5 4 3 2 1 0 id23 id22 id21 id20 id19 id18 id17 id16 ide format mode specification bit 0 standard format mode (id28 to id18: 11 bits) note 1 extended format mode (id28 to id0: 29 bits) note the id17 to id0 bits are not used. id28 to id0 message id id28 to id18 standard id value of 11 bits (when ide = 0) id28 to id0 extended id value of 29 bits (when ide = 1) cautions 1. be sure to write 0 to bits 14 and 13 of the c0midhm register. 2. be sure to align the id value accord ing to the given bit positions into this registers. note that for standard id, th e id value must be shifted to fit into id28 to id11 bit positions. chapter 16 can controller user?s manual u17553ej4v0ud 451 (23) can message control register m (c0mctrlm) the c0mctrlm register is used to cont rol the operation of the message buffer. after reset: 00x000000 00000000b r/w address: see table 16-16 . (a) read 15 14 13 12 11 10 9 8 c0mctrlm 0 0 muc 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 mow ie dn trq rdy (b) write 15 14 13 12 11 10 9 8 c0mctrlm 0 0 0 0 set ie 0 set trq set rdy 7 6 5 4 3 2 1 0 0 0 0 clear mow clear ie clear dn clear trq clear rdy (a) read muc note message buffer data updating bit 0 the can module is not updating the me ssage buffer (reception and storage). 1 the can module is updating the message buffer (reception and storage). note the muc bit is undefined until the first reception and storage is performed. mow message buffer overwrite status bit 0 the message buffer is not overwritt en by a newly received data frame. 1 the message buffer is overwritten by a newly received data frame. remark mow bit is not set to 1 even if a remote frame is received and stored in the transmit message buffer with dn = 1. ie message buffer interrupt request enable bit 0 receive message buffer: valid message reception completion interrupt disabled. transmit message buffer: normal message tr ansmission completion interrupt disabled. 1 receive message buffer: valid message reception completion interrupt enabled. transmit message buffer: normal message transmission completion interrupt enabled. chapter 16 can controller user?s manual u17553ej4v0ud 452 dn message buffer data updating bit 0 a data frame or remote frame is not stored in the message buffer. 1 a data frame or remote frame is stored in the message buffer. trq message buffer transmission request bit 0 no message frame transmitting request that is pending or being transmitted is in the message buffer. 1 the message buffer is holding transmission of a message frame pending or is transmitting a message frame. caution do not set the trq bit and the rdy bit (1) at the same time. set the rdy bit (1) before setting the trq bit. rdy message buffer ready bit 0 the message buffer can be written by software. the can module cannot write to the message buffer. 1 writing the message buffer by software is ignored (except a write access to the rdy, trq, dn, and mow bits). the can module can write to the message buffer. cautions 1. do not clear the rdy bit (0) during message transmission. follow the transmission abort process about clearing the rdy bit (0) for redefinition of the message buffer. 2. clear again when rdy bit is not cleared even if this bit is cleared. 3. be sure that rdy is cleared befo re writing to the other message buffer registers, by checking the status of the rdy bit. (b) write clear mow setting of mow bit 0 mow bit is not changed. 1 mow bit is cleared to 0. set ie clear ie setting of ie bit 0 1 ie bit is cleared to 0. 1 0 ie bit is set to 1. other than above ie bit is not changed. caution set ie bit and rdy bit always separately. clear dn setting of dn bit 0 dn bit is not changed. 1 dn bit is cleared to 0. caution do not set the dn bit to 1 by so ftware. be sure to write 0 to bit 10. chapter 16 can controller user?s manual u17553ej4v0ud 453 set trq clear trq setting of trq bit 0 1 trq bit is cleared to 0. 1 0 trq bit is set to 1. other than above trq bit is not changed. set rdy clear rdy setting of rdy bit 0 1 rdy bit is cleared to 0. 1 0 rdy bit is set to 1. other than above rdy bit is not changed. caution set ie bit and rdy bit always separately. chapter 16 can controller user?s manual u17553ej4v0ud 454 16.8 can controller initialization 16.8.1 initialization of can module before the can module operation is enabled, the can module system clock needs to be determined by setting the ccp[3:0] bits of the c0gmcs register by software. do not change the setting of the can module system clock after can module operation is enabled. the can module is enabled by setting t he gom bit of the c0gmctrl register. for the procedure of initializ ing the can module, refer to 16.16 operation of can controller. 16.8.2 initialization of message buffer after the can module is enabled, the message buffers cont ain undefined values. a minimum initialization for all the message buffers, even for those not used in the applicat ion, is necessary before switching the can module from the initialization mode to on e of the operation modes. - clear the rdy, trq, and dn bits of the c0mctrlm register to 0. - clear the ma0 bit of the c0mconfm register to 0. remark m = 0 to 15 16.8.3 redefinition of message buffer redefining a message buffer means changing the id and control information of the message buffer while a message is being received or transmitted, without a ffecting other transmissi on/reception operations. (1) to redefine message buffe r in initialization mode place the can module in the initia lization mode once and then change t he id and control information of the message buffer in the initialization mode. after chang ing the id and control information, set the can module in an operation mode. (2) to redefine message buffer during reception perform redefinition as shown in figure 16-40. (3) to redefine message buffer during transmission to rewrite the contents of a transmit message buffe r to which a transmission request has been set, perform transmission abort processing (refer to 16.10.4 (1) transmission abort process except for in normal operation mode with automatic block transmission (abt) and 16.10.4 (2) transmission abort process except for abt transmission in normal operation mode with automatic block transmission (abt) . confirm that transmission has been aborted or comple ted, and then redefine the message buffer. after redefining the transmit message buffer, set a transmissio n request using the procedure described below. when setting a transmission request to a message bu ffer that has been redef ined without aborting the transmission in progress, however, the 1-bit wait time is not necessary. chapter 16 can controller user?s manual u17553ej4v0ud 455 figure 16-27. setting transmission request (trq) to transmit message bu ffer after redefining end redefinition completed execute transmission? wait for 1 bit of can data. set trq bit set trq = 1 clear trq = 0 yes no cautions 1. when a message is recei ved, reception filtering is performe d in accordance with the id and mask set to each receive message buffer. if the pr ocedure in figure 16-40 is not observed, the contents of the message buffer afte r it has been redefined may cont radict the result of reception (result of reception filtering). if this happens, check that the id and ide received first and stored in the message buffer following rede finition are those stored afte r the message buffer has been redefined. if no id and ide are stored after redefinition, redefine th e message buffer again. 2. when a message is transmitte d, the transmission priority is checked in accordance with the id, ide, and rtr bits set to each transmit message buffer to which a transmission request was set. the transmit message buffer havi ng the highest priority is select ed for transmission. if the procedure in figure 16-41 is not observed, a mes sage with an id not having the highest priority may be transmitted after redefinition. 16.8.4 transition from initializ ation mode to operation mode the can module can be switched to the following operation modes. - normal operation mode - normal operation mode with abt - receive-only mode - single-shot mode - self-test mode chapter 16 can controller user?s manual u17553ej4v0ud 456 figure 16-28. transiti on to operation modes can module channel invalid [receive-only mode] opmode[2:0]=03h opmode[2:0] = 00h and can bus is busy. opmode[2:0] = 03h [single-shot mode] opmode[2:0]=04h opmode[2:0] = 04h opmode[2:0] = 05h init mode opmode[2:0] = 00h efsd = 1 and gom = 0 all can modules are in init mode and gom = 0 gom = 1 reset reset released [normal operation mode with abt] opmode[2:0]=02h opmode[2:0] = 00h and can bus is busy. opmode[2:0] = 00h and interframe space opmode[2:0] = 02h opmode[2:0] = 01h opmode[2:0] = 00h and can bus is busy. [normal operation mode] opmode[2:0]=01h opmode[2:0] = 00h and can bus is busy. opmode[2:0] = 00h and interframe space opmode[2:0] = 00h and interframe space opmode[2:0] = 00h and interframe space opmode[2:0] = 00h and interframe space opmode[2:0] = 00h and can bus is busy. [self-test mode] opmode[2:0]=05h the transition from the initia lization mode to an operation mode is contro lled by the bit string opmode[2:0] in the c0ctrl register. changing from one operation mode into another requires sh ifting to the initialization mode in between. do not change one operation mode to another directly; otherwise the operation will not be guaranteed. requests for transition from the operat ion mode to the initialization mode are held pending when the can bus is not in the interframe space (i.e., frame reception or tr ansmission is in progress), and the can module enters the initialization mode at the first bit in the interframe spac e (the value of opmode[2:0] are changed to 00h). after issuing a request to change the mode to the initializati on mode, read the opmode[2:0] bits until their value becomes 000b to confirm that the module has enter ed the initialization mode (refer to figure 16-37 ). 16.8.5 resetting error counter c0erc of can module if it is necessary to reset the can module error counter c0erc and the can module information register c0info when re-initialization or forced recovery from the bus-off st ate is made, set the ccerc bit of the c0ctrl register to 1 in the initialization mode. when this bit is set to 1, the can module error counter c0erc and the can module information register c0info are cleared to their default values. chapter 16 can controller user?s manual u17553ej4v0ud 457 16.9 message reception 16.9.1 message reception in all the operation modes, the complete message buffer ar ea is analyzed to find a suitable buffer to store a newly received message. all message buffers satisfying the followi ng conditions are included in that evaluation (rx-search process). - used as a message buffer (ma0 bit of c0mconfm register set to 1b.) - set as a receive message buffer (mt[2:0] bits of c0mconfm register set to 001b, 010b, 011b, 100b, or 101b.) - ready for reception (rdy bit of c0mctrlm register set to 1.) when two or more message buffers of the can module receive a message, the message is stored according to the priority explained below. the message is always stored in the message buffer with the highest priority, not in a message buffer with a low priority. for example, when an unmasked receive message buffer and a receive message buffer linked to mask 1 have the same id, the received message is not stored in the message buffer linked to mask 1, even if that message buffer has not received a message a nd a message has already been received in the unmasked receive message buffer. in other words, when a condition has been set to store a message in two or more message buffers with different priorities, the message buffer with t he highest priority always stores the message; the message is not stored in message buffers with a lower priority. this also applies when the message buffer with the highest priority is unable to receive and store a message (i.e., when dn = 1 indicating that a message has already been received, but rewriting is disabled because ows = 0). in th is case, the message is not actually received and stored in the candidate message buffer with the highest priority, but neith er is it stored in a message buffer with a lower priority. priority storing condition if same id is set 1 (high) unmasked message buffer dn = 0 dn = 1 and ows = 1 2 message buffer linked to mask 1 dn = 0 dn = 1 and ows = 1 3 message buffer linked to mask 2 dn = 0 dn = 1 and ows = 1 4 message buffer linked to mask 3 dn = 0 dn = 1 and ows = 1 5(low) message buffer linked to mask 4 dn = 0 dn = 1 and ows = 1 remark m = 0 to 15 chapter 16 can controller user?s manual u17553ej4v0ud 458 16.9.2 receive data read to keep data consistency when reading can message buffe rs, perform the data reading according to figure 16-51 to 16-53. during message reception, the can module sets dn of t he c0mctrlm register two times: at the beginning of the storage process of data to the message buffer, and again at the end of this storage process. during this storage process, the muc bit of the c0mctrlm regist er of the message buffer is set. (refer to figure 16-29 .) the receive history list is also updated just before the storage process. in addition, during storage process (muc = 1), the rdy bit of the c0mctrl register of the message buffe r is locked to avoid the coincidental data wr by cpu. note the storage process may be disturbed (del ayed) when the cpu accesses the message buffer. figure 16-29. dn and muc bit setting period (for standard id format) sof (1) id ide rtr r0 dlc data0-data7 crc ack eof can std id format (11) (1) (1) (1) (4) (0-64) (16) (2) recessive dominant dn muc message store mdata,mdlc.midx- > mbuf (7) set dn & clear muc at the same timing cints1 set dn & muc at the same time ifs intrec1 operation of the can contoroller remark m = 0 to 15 chapter 16 can controller user?s manual u17553ej4v0ud 459 16.9.3 receive history list function the receive history list (rhl) function records in the re ceive history list the number of the receive message buffer in which each data frame or remote frame was received and stored. the rhl consists of storage elements equivalent to up to 23 messages, the last in-message pointer (lipt) with the corresponding c0lipt register and the receive history list get pointer (rgpt) with t he corresponding c0rgpt register. the rhl is undefined immediately after the transition of the can module from the initialization mode to one of the operation modes. the c0lipt register holds the contents of the rhl element i ndicated by the value of the lipt pointer minus 1. by reading the c0lipt register, therefore, the number of t he message buffer that received and stored a data frame or remote frame first can be checked. the lipt pointer is utilized as a write pointer that indicates to what part of the rhl a message buffer number is recorded. any time a dat a frame or remote frame is received and stored, the corresponding message buffer number is recorded to the rhl element indicated by the lipt pointer. each time recording to the rhl has been completed, the lipt pointer is automatically incremented. in this way, the number of the message buffer that has received and stored a frame will be recorded chronologically. the rgpt pointer is utilized as a read pointer that reads a recorded message buffer number from the rhl. this pointer indicates the first rhl element that the cpu has not read yet. by readi ng the c0rgpt register by software, the number of a message buffer that has re ceived and stored a data frame or remote frame can be read. each time a message buffer number is read from the c0rgpt regist er, the rgpt pointer is automatically incremented. if the value of the rgpt pointer matc hes the value of the lipt pointer, the rhpm bit (receive history list pointer match) of the c0rgpt register is set to 1. this i ndicates that no message buffer nu mber that has not been read remains in the rhl. if a new message buffer number is re corded, the lipt pointer is incremented and because its value no longer matches the value of the rgpt pointer, the rhpm bit is cleared. in other words, the numbers of the unread message buffers exist in the rhl. if the lipt pointer is incr emented and matches the value of the rgpt pointer minus 1, the rovf bit (receive history list overflow) of the c0rgpt register is set to 1. this indicates that the rhl is full of numbers of message buffers that have not been read. when further message re ception and storing occur, the last recorded message buffer number is overwritten by the num ber of the message buffer that received and stored the new message. in this case, after the rovf bit has been set (1), the recorded message buffer numbers in the rhl do not completely reflect the chronological order. however messages itself are not lost and can be located by cpu search in message buffer memory with the help of the dn-bit. caution if the history list is in the overflow conditi on (rovf is set), reading the history list contents is still possible, until the history list is empty (i ndicated by rhpm flag set). nevertheless, the history list remains in the overflow condition, until rovf is cleared by software. if rovf is not cleared, the rhpm flag will also not be update d (cleared) upon a message storage of newly received frame. this may lead to the situation, that rhpm indicates an empty history list, although a reception has taken place, while the history list is in the overflow state (rovf and rhpm are set). chapter 16 can controller user?s manual u17553ej4v0ud 460 as long as the rhl contains 23 or less entries the sequence of occurrence is main tained. if more receptions occur without reading the rhl by the host processor, comple te sequence of receptions can not be recovered. figure 16-30. receive history list 23 1 2 3 4 5 6 7 receive history list (rhl) 23 1 2 3 4 5 6 7 receive history list(rhl) last in-message pointer(lipt) 23 0 1 2 3 4 5 6 7 23 1 2 3 4 5 6 7 0 when rhl is full rovf is set. : : : when message buffer 6 is read : : : : : : 22 0 0 22 22 22 message buffer 7 message buffer 2 message buffer 9 message buffer 6 if message is stored in message buffers 3, 4, and 8 message buffer 8 message buffer 4 message buffer 3 message buffer 7 message buffer 2 message buffer 9 receive history list get pointer (rgpt) receive history list(rhl) message buffer 1 message buffer 5 message buffer 8 message buffer 4 message buffer 3 message buffer 7 message buffer 2 message buffer 9 message buffer 9 receive history list get pointer (rgpt) last in-message pointer(lipt) lipt is locked. receive history list get pointer (rgpt) receive history list get pointer (rgpt) last in-message pointer(lipt) message buffer 3 message buffer 9 message buffer 7 message buffer 5 message buffer 3 message buffer 4 message buffer 8 message buffer 2 message buffer 9 receive history list (rhl) when rovf = 1, message buffer number is stored (overwritten) to element indicated by lipt-1. last in-message pointer(lipt) when message buffer 3 receives and stores more messages chapter 16 can controller user?s manual u17553ej4v0ud 461 16.9.4 mask function for any message buffer, which is used fo r reception, the assignmen t to one of four global reception masks (or no mask) can be selected. by using the mask function, the message id comparison can be reduced by masked bits, herewith allowing the reception of several different ids into one buffer. while the mask function is in effect, an identifier bit that is defined to be "1" by a mask in the received message is not compared with the corresponding identifier bit in the message buffer. however, this comparison is performed for any bi t whose value is defined as "0" by the mask. for example, let us assume that all messages that have a standard-format id, in which bits id27 to id25 are "0" and bits id24 and id22 are "1", are to be stored in mess age buffer 14. the procedure for this example is shown below. <1> identifier to be stored in message buffer id28 id27 id26 id25 id24 id23 id22 id21 id20 id19 id18 x 0 0 0 1 x 1 x x x x x = don?t care <2> identifier to be configured in message buffer 14 (example) (using cann message id registers l14 and h14 (c0midl14 and c0midh14)) id28 id27 id26 id25 id24 id23 id22 id21 id20 id19 id18 x 0 0 0 1 x 1 x x x x id17 id16 id15 id14 id13 id12 id11 id10 id9 id8 id7 x x x x x x x x x x x id6 id5 id4 id3 id2 id1 id0 x x x x x x x id with id27 to id25 cleared to "0" and id24 and id22 set to "1" is registered (initialized) to message buffer 14. remark message buffer 14 is set as a standard format iden tifier that is linked to mask 1 (mt[2:0] of c0mconf14 register are set to 010b). chapter 16 can controller user?s manual u17553ej4v0ud 462 <3> mask setting for can module 1 (mask 1) (example) (using can1 address mask 1 registers l and h (c1maskl1 and c1maskh1)) cmid28 cmid27 cmid26 cmid25 cmid24 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 1 0 0 0 0 1 0 1 1 1 1 cmid17 cmid16 cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 cmid7 1 1 1 1 1 1 1 1 1 1 1 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 1 1 1 1 1 1 1 not compared (masked) 0: compared the cmid27 to cmid24 and cmid22 bits are cleared to "0", and cmid28, cmid23, and cmid21 to cmid0 bits are set to "1". chapter 16 can controller user?s manual u17553ej4v0ud 463 16.9.5 multi buffer re ceive block function the multi buffer receive block (mbrb) function is used to store a block of data in two or more message buffers sequentially with no cpu interaction, by setting the same id to two or more message buffers with the same message buffer type. suppose, for example, the same message buffer type is set to 5 message buffers, message buffers 10 to 14, and the same id is set to each message buffer. if the firs t message whose id matches the id of the message buffers is received, it is stored in message buffer 10. at this point, the dn bit of message buffer 10 is set, prohibiting overwriting the message buffer when subsequent messages are received. if the next message with a matching id is received, it is received and stored in message buffer 11. each time a message with a matching id is received, it is sequentially (in the ascending order) stored in message buffers 12, 13, and 14. even when a data block consisting of multip le messages is received, the messages can be stored and received without overwriting the prev iously received matching-id data. whether a data block has been received and stored can be checked by setting the ie bit of the c0mctrlm register of each message buffer. fo r example, if a data block consists of k messages, k message buffers are initialized for reception of the data block. the ie bit in message buffers 0 to (k -2) is cleared to 0 (interrupts disabled), and the ie bit in message buffer k-1 is set to 1 (interrupts enabled). in this case, a reception completion interrupt occurs when a message has been received and stored in message buffer k-1, indicating that mbrb has become full. alternatively, by clearing the ie bit of message buffers 0 to (k-3) and setting the ie bit of message buffer k-2, a warning that mbrb is about to overflow can be issued. the basic conditions of storing rece ive data in each message buffer for the mbrb are the same as the conditions of storing data in a single message buffer. cautions 1. mbrb can be configured for each of th e same message buffer types. therefore, even if a message buffer of another mbrb whose id ma tches but whose mes sage buffer type is different has a vacancy, the rece ived message is not stored in that message buffer, but instead discarded. 2. mbrb does not have a ring buffe r structure. therefore, afte r a message is stored in the message buffer having the high est number in the mbrb conf iguration, a newly received message will not be stored in the message buffer having the lowest message buffer number. 3. mbrb operates based on th e reception and storage condi tions; there are no settings dedicated to mbrb, such as function enable bits. by setting the same message buffer type and id to two or more message buffe rs, mbrb is automati cally configured. 4. with mbrb, "matching id" means "matching id after mask". even if the id set to each message buffer is not the same, if the id that is masked by the mask register matches, it is considered a matching id and the buffer th at has this id is treated as the storage destination of a message. 5. the priority between mbrbs is mentioned in 16.9.1 message reception. remark m = 0 to 15 chapter 16 can controller user?s manual u17553ej4v0ud 464 16.9.6 remote frame reception in all the operation modes, when a remote frame is receiv ed, the message buffer that is to store the remote frame is searched from all the message buffers satisfying the following conditions. - used as a message buffer (ma0 bit of c0mconfm register set to 1b.) - set as a transmit message buffer (mt[2:0] bits in c0mconfm register set to 000b) - ready for reception (rdy bit of c0mctrlm register set to 1.) - set to transmit message (rtr bit of c0mconfm register is cleared to 0.) - transmission request is not set. (trq bit of c0mctrlm register is cleared to 1.) upon acceptance of a remote frame, the following actions are executed if the id of the received remote frame matches the id of a message buffer that satisfies the above conditions. - the mdlc[3:0] bit string in the c0mdlcm register stores the received dlc value. - c0mdata0m to c0mdata7m in the data area are not updated (data before reception is saved). - the dn bit of the c0mctrlm register is set to 1. - the cints1 bit of the c0ints register is set to 1 (if the ie bit in the c0mctrlm register of the message buffer that receives and stores the frame is set to 1). - the reception completion interrupt (intc0rec) is output (if the ie bit in the c0mctrlm register of the message buffer that receives and stores the frame is set to 1 and if the cie1 bit of the c0ie register is set to 1). - the message buffer number is recorded to the receive history list. caution when a message buffer is searched for receiving and storing a remote frame, overwrite control by the ows bit of the c0mconfm register of the message buffer a nd the dn bit of the c0mctrlm register are not aff ected. the setting of ows is i gnored, and dn is set in any case. if more than one transmit me ssage buffer has the same id and the id of the received remote frame matches that id, the remote frame is st ored in the transmit message buffer with the lowest message buffer number. remark m = 0 to 15 chapter 16 can controller user?s manual u17553ej4v0ud 465 16.10 message transmission 16.10.1 message transmission in all the operation modes, if the trq bit is set to 1 in a message buffer that satisfies the following conditions, the message buffer that is to tr ansmit a message is searched. - used as a message buffer (ma0 bit of c0mconfm register set to 1b.) - set as a transmit message buffer (mt[2:0] bits of c0mconfm register set to 000b.) - ready for transmission (rdy bit of c0mctrlm register set to 1.) the can system is a multi-master communication system. in a system like this, the priority of message transmission is determined based on message identifiers (ids). to facilitate transmission processing by software when there are several messages awaiting transmission, t he can module uses hardware to check the id of the message with the highest priority and automatically identifies that message. this eliminates the need for software- based priority control. transmission priority is controlled by the identifier (id). figure 16-31. message processing example message no. the can module transmits messages in the following sequence. message waiting to be transmitted id = 120h id = 229h id = 223h id = 023h id = 123h 0 1 2 3 4 5 6 7 8 9 1. message 6 2. message 1 3. message 8 4. message 5 5. message 2 after the transmit message search, the transmit message with the highest priority of the transmit message buffers that have a pending transmission request (message buffers with the trq bit set to 1 in advance) is transmitted. if a new transmission request is set, the transmit message buffer with the new transmission request is compared with the transmit message buffer with a pending transmission request. if the new transmission request has a higher priority, it is transmitted, unless trans mission of a message with a low priority has already started. if transmission of a message with a low priority has already started, however, t he new transmission request is transmitted later. to solve this priority inversion effect, the software can perform a transmission abort request for the lower priority message. the highest priority is determined according to the following rules. chapter 16 can controller user?s manual u17553ej4v0ud 466 priority conditions description 1(high) value of first 11 bits of id [id28 to id18]: the message frame with the lowest value represented by the first 11 bits of the id is transmitted first. if the value of an 11-bit standard id is equal to or smaller than the first 11 bits of a 29-bit extended id, the 11-bit standard id has a higher priority than message frame with the 29-bit extended id. 2 frame type a data frame with an 11-bit standard id (rtr bit is cleared to 0) has a higher priority than a remote frame with a standard id and a message frame with an extended id. 3 id type a message frame with a standard id (ide bit is cleared to 0) has a higher priority than a message frame with an extended id. 4 value of lower 18 bits of id [id17 to id0]: if more than one transmission-pending extended id message frame have equal values in the first 11 bits of the id and the same frame type (equal rtr bit values), the message frame with the lowest value in the lower 18 bits of its extended id is transmitted first. 5(low) message buffer number if two or more message buffers request transmission of message frames with the same id, the message from the message buffer with the lowest message buffer number is transmitted first. remarks 1. if automatic block transmission request bit abttrg is set to 1 in the normal operation mode with abt, the trq bit is set to 1 only for one message buffer in the abt message buffer group. if the abt mode was triggered by abttrg bit, one tr q bit is set to 1 in the abt area (buffer 0 through 7). beyond this trq bit, the application ca n request transmissions (set trq to 1) for other tx-message buffers that do not belong to the abt area. in that case an interval arbitration process (tx-search) evaluates all tx-message buffers wit h trq bit set to 1 and chooses the message buffer that contains the highest prioritized identifier for the next transmission. if there are 2 or more identifiers that have the highest priority (i.e. ident ical identifiers), the message located at the lowest message buffer number is transmitted at first. upon successful transmission of a message fr ame, the following operations are performed. - the trq flag of the corresponding transmit me ssage buffer is automatically cleared to 0. - the transmission completion status bit cints0 of the c0ints register is set to 1 (if the interrupt enable bit (ie) of the corresponding transmit message buffer is set to 1). - an interrupt request signal intc0trx output (if the cie0 bit of the c0ie register is set to 1 and if the interrupt enable bit (ie) of the correspo nding transmit message buffer is set to 1). 2. when changing the contents of a transmit buffer, t he rdy flag of this buffer must be cleared before updating the buffer contents. as during intern al transfer actions, the rdy flag may be locked temporarily, the status of rdy must be checked by software, after changing it. 3. m = 0 to 15 chapter 16 can controller user?s manual u17553ej4v0ud 467 16.10.2 transmit history list function the transmit history list (thl) function records in the tr ansmit history list the number of the transmit message buffer from which data or remote frames have been were sent. t he thl consists of storage elements equivalent to up to seven messages, the last out-message pointer (lopt) wi th the corresponding c0lopt register, and the transmit history list get pointer (tgpt) with the corresponding c0tgpt register. the thl is undefined immediately after t he transition of the can module from t he initialization mode to one of the operation modes. the c0lopt register holds t he contents of the thl element indicated by the value of the lopt pointer minus 1. by reading the c0lopt register, theref ore, the number of the message buffer t hat transmitted a data frame or remote frame first can be checked. the lopt poi nter is utilized as a write pointer that indicates to what part of the thl a message buffer number is reco rded. any time a data frame or remote frame is transmitted, the corresponding message buffer number is recorded to the thl element indica ted by the lopt pointer. each time recording to the thl has been completed, the lopt pointer is automatically incremented. in this way, the number of the message buffer that has received and stored a frame will be recorded chronologically. the tgpt pointer is utilized as a read pointer that reads a recorded message buffer number from the thl. this pointer indicates the first thl element that the cpu has not yet read. by reading the c0 tgpt register by software, the number of a message buffer that has completed transmissi on can be read. each time a message buffer number is read from the c0tgpt register, the tg pt pointer is automatically incremented. if the value of the tgpt pointer matches the value of the lopt pointer, the th pm bit (transmit history list pointer match) of the c0tgpt register is set to 1. this indicates that no messag e buffer numbers that have not been read remain in the thl. if a new message buffer number is re corded, the lopt pointer is incremented and because its value no longer matches the value of the tgpt pointer, the th pm bit is cleared. in other words, the numbers of the unread message buffers exist in the thl. if the lopt pointer is incremented and matches the value of the tgpt pointer minus 1, the tovf bit (transmit history list overflow) of the c0tgpt regi ster is set to 1. this indicates t hat the thl is full of message buffer numbers that have not been read. if a new message is received and stored, the message buffer number recorded last is overwritten by the number of the message buffer that transmitted its mess age afterwards. after the tovf bit has been set (1), therefore, the recorded message buffer numbers in the thl do not completely reflect the chronological order. however the other transmitted messages can be f ound by a cpu search applied to all transmit message buffers unless the cpu has not overwritten a transmit object in one of these buffers beforehand. in total up to six transmission completions can occur without overflowing the thl. caution if the history list is in the overflow condition (tovf is set), reading the history list contents is still possible, until the history list is empty (i ndicated by thpm flag set). nevertheless, the history list remains in the overflow condition, until tovf is cleared by software. if tovf is not cleared, the thpm flag will also not be upda ted (cleared) upon successful transmission of a new message. this may lead to the situation, that thpm i ndicates an empty history list, although a successful tran smission has taken place, while the history list is in the overflow state (tovf and thpm are set). remark m = 0 to 15 chapter 16 can controller user?s manual u17553ej4v0ud 468 figure 16-32. transmit history list 1 2 3 4 5 6 7 transmit history list(thl) 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 when thl is full tovf is set. 0 0 0 when tovf = 1, message buffer number is stored (overwritten) to element indicated by lopt-1. 0 last out-message pointer(lopt) message buffer 7 message buffer 2 message buffer 9 message buffer 6 transmit history list get pointer(tgpt) transmit history list(thl) message buffer 4 message buffer 3 message buffer 7 message buffer 2 message buffer 9 when message buffer 6 is read if transmission from message buffers 3 and 4 is completed last out-message pointer(lopt) transmit history list get pointer(tgpt) transmit history list(thl) transmit history list get pointer(tgpt) last out-message pointer(lopt) lopt is locked. transmit history list get pointer (tgpt) transmit history list(thl) when transmission from message buffer 3 is completed. last out-message pointer(lopt) message buffer 3 message buffer 8 message buffer 4 message buffer 3 message buffer 7 message buffer 2 message buffer 9 message buffer 5 message buffer 8 message buffer 4 message buffer 3 message buffer 7 message buffer 2 message buffer 9 chapter 16 can controller user?s manual u17553ej4v0ud 469 16.10.3 automatic blo ck transmission (abt) the automatic block transmission (abt) function is used to transmit two or more data frames successively with no cpu interaction. the maximum number of transmit messag e buffers assigned to the abt function is eight (message buffer numbers 0 to 7). by setting opmode [2:0] bits of the cnctrl register to 010b, "normal operation mode with automatic block transmission function" (hereafter referred to as abt mode) can be selected. to issue an abt transmission request, define the message bu ffers by software first. set the ma0 bit (1) in all the message buffers used for abt, and define all the buffers as transmit message buffers by setting mt [2:0] bits to 000b. be sure to set the id for each message buffer for abt ev en when the same id is being used for all the message buffers. to use two or more ids, set the id of each me ssage buffer by using the cnmidlm and cnmidhm registers. set the cnmdlcm and cnmdata0m to cnmdata7m registers before issuing a transmission request for the abt function. after initialization of message buffers for abt is finished, the rdy bit needs to be set (1). in the abt mode, the trq bit does not have to be manipulated by software. after the data for the abt message buffers has been prepared, set the abttrg bit to 1. automatic block transmission is then started. when abt is started, the trq bit in the fi rst message buffer (message buffer 0) is automatically set to 1. after transmi ssion of the data of message buffer 0 has finished, trq bit of the next message buffer, message buffer 1, is set automatically. in this way, transmission is executed successively. a delay time can be inserted by program in the interval in which the transmission requ est (trq) is automatically set while successive transmission is being executed. th e delay time to be inserted is defined by the cngmabtd register. the unit of the delay time is dbt (data bit time). dbt depends on the setting of the cnbrp and cnbtr registers. among transmit objects within the abt-ar ea, the priority of the transmission id is not evaluat ed. the data of message buffers 0 to 7 are sequentially transmitted. w hen transmission of the data frame from message buffer 7 has been completed, the abttrg bit is automatically cleared to 0 and the abt operation is finished. if the rdy bit of an abt message buffer is cleared during abt, no data frame is transmitt ed from that buffer, abt is stopped, and the abttrg bit is cleared. after that, transmission can be resumed from the message buffer where abt stopped, by setting the rdy and abttrg bits to 1 by software. to not resume transmission from the message buffer where abt stopped, the internal abt engine can be reset by setting the abtclr bit to 1 while abt mode is stopped and abttrg bit is cleared to 0. in this case, tr ansmission is started from message buffer 0 if the abtclr bit is cleared to 0 and then the abttrg bit is set to 1. an interrupt can be used to check if data frames have been transmitted from all the message buffers for abt. to do so, the ie bit of the cnmctrlm register of each me ssage buffer except the last message buffer needs to be cleared (0). if a transmit message buffer other than those used by the abt function (message buffer 8 to 15) is assigned to a transmit message buffer, the message to be transmitted next is det ermined by the priority of the transmission id of the abt message buffer whose transmission is currently held pending and the transmission id of the message buffers other than those used by the abt function. transmission of a data frame from an abt message buffer is not recorded in the transmit history list (thl). chapter 16 can controller user?s manual u17553ej4v0ud 470 cautions 1. set the abtcl r bit to 1 while the abttrg bit is cleared to 0 in order to resume abt operation at buffer no.0. if the abtclr bit is set to 1 wh ile the abttrg bit is set to 1, the subsequent operati on is not guaranteed. 2. if the automatic block transmission engine is cleared by setting the abtclr bit to 1, the abtclr bit is automati cally cleared immediately after the processing of the clearing request is completed. 3. do not set the abttrg bit in the initialization mode. if the abttrg bit is set in the initialization mode, the proper operation is not guaranteed after the mode is changed from the initialization mode to the abt mode. 4. do not set trq bit of the abt messag e buffers to 1 by software in the normal operation mode with abt. otherwise, the operation is not guaranteed. 5. the c0gmabtd register is used to set the delay time th at is inserted in the period from completion of the preceding abt message to setting of the trq bit for the next abt message when the transm ission requests are set in the order of message numbers for each message for abt that is successively transm itted in the abt mode. the timing at which the messages are actually transmitted onto the can bus varies depending on the status of transmission from other stations and the status of the setting of the transmission request fo r messages other than the abt messages (message buffer 8 to 15). 6. if a transmission request is made fo r a message other than an abt message and if no delay time is inserted in the interval in which transmission requests for abt are automatically set (c0gmabtd = 00h), mess ages other than abt messages may be transmitted not depending on the priority of the abt message. 7. do not clear the rdy bit to 0 when abttrg = 1. 8. if a message is received from another node while normal opera tion mode with abt is active, the tx-message from the abt-area may be transmitted with delay of one frame although cngmabtd register was set up with 00h. remark m = 0 to 15 16.10.4 transmission abort process (1) transmission abort process except for in normal operation mode with automatic blo ck transmission (abt) the user can clear the trq bit of the c0mctrlm regi ster to 0 to abort a transmission request. the trq bit will be cleared immediately if the abort was successful. whether the transmission was successfully aborted or not can be checked using the tsta t bit of the c0ctrl register and t he c0tgpt register, which indicate the transmission status on the can bus (for details, refer to the processing in figure 16-47 ). (2) transmission abort process excep t for abt transmission in normal operation mode with automatic block transmission (abt) the user can clear the abttrg bit of the c0gmabt register to 0 to abort a transmission request. after checking the abttrg bit of the c0gmabt register = 0, clear the trq bit of the c0mctrlm register to 0. the trq bit will be cleared immediately if the abort was successful. whether the transmission was successfully aborted or not can be checked using the tstat bit of t he c0ctrl register and the c0tgpt register, which indicate the transmission status on the can bus (for details, refer to the processing in figure 16-48 ). chapter 16 can controller user?s manual u17553ej4v0ud 471 (3) transmission abort process for abt transmission in normal operati on mode with automatic block transmission (abt) to abort abt that is already started, clear the abttrg bit of the c0gmabt r egister to 0. in this case, the abttrg bit remains 1 if an abt message is curr ently being transmitted and until the transmission is completed (successfully or not), and is cleared to 0 as soon as transmission is finished. this aborts abt. if the last transmission (before abt) was successful, the normal operation mode with abt is left with the internal abt pointer pointing to the next message buffer to be transmitted. in the case of an erroneous transmission, the position of the internal abt pointer depends on the status of the trq bit in the last transmitted message buffer. if the trq bit is set to 1 when clearing the abttrg bit is requested, the internal abt pointer points to the last transmitted message buffer (for details, refer to the process in figure 16-49 ). if the trq bit is cleared to 0 when clearing the abttrg bit is requested, the internal abt pointer is incremented (+1) and points to the next message buffer in the abt area (for details, refer to the process in figure 16-50 ). caution be sure to abort abt by clearing abttr g to 0. the operation is not guaranteed if aborting transmission is requ ested by clearing rdy bit. when the normal operation mode with abt is resumed a fter abt has been aborted and abttrg bit is set to 1, the next abt message buffer to be transmitted can be determined from the following table. status of trq of abt message buffer abort after successful transmission a bort after erroneous transmission set (1) next message buffer in the abt area note same message buffer in the abt area cleared (0) next message buffer in the abt area note next message buffer in the abt area note note the above resumption operation can be performed only if a message buffer ready for abt exists in the abt area. for example, an abort request that is issued while abt of message buffer 7 is in progress is regarded as completion of abt, rather than abor t, if transmission of message buffer 7 has been successfully completed, even if abttrg is cleared to 0. if the rdy bit in the next message buffer in the abt area is cleared to 0, the internal abt pointer is retained, but the resumption operation is not performed even if abttrg is set to 1, and abt ends immediately. remark m = 0 to 15 16.10.5 remote frame transmission remote frames can be transmitted only from transmit mess age buffers. set whether a data frame or remote frame is transmitted via the rtr bit of the c0mconfm register. setting (1) the rt r bit sets remote frame transmission. remark m = 0 to 15 chapter 16 can controller user?s manual u17553ej4v0ud 472 16.11 power save modes 16.11.1 can sleep mode the can sleep mode can be used to set the can cont roller to standby mode in order to reduce power consumption. the can module can en ter the can sleep mode from all operati on modes. release of the can sleep mode returns the can module to exactly the same oper ation mode from which the can sleep mode was entered. in the can sleep mode, the can module does not tr ansmit messages, even when transmission requests are issued or pending. (1) entering can sleep mode the cpu issues a can sleep mode transition request by writing 01b to the psm ode[1:0] bits of the c0ctrl register. this transition request is only acknowledged only under the following conditions. - the can module is already in on e of the following operation modes - normal operation mode - normal operation mode with abt - receive-only mode - single-shot mode - self-test mode - can stop mode in all the above operation modes - the can bus state is bus idle (the 4th bi t in the interframe space is recessive) note - no transmission request is pending note if the can bus is fixed to dominant, the request for transition to the can sleep mode is held pending. also the transition from can stop mode to can sl eep mode is independent of the can bus state. remark if a sleep mode request is pending, and at the same time a message is received in a message box, the sleep mode request is not cancelled, but is executed right after message storage has been finished. this may result in afcan being in sleep mode, while the cpu would execute the rx interrupt routine. therefor e, the interrupt routine must check the access to the message buffers as well as reception history list register s by using the mbon flag, if sleep mode is used. if any one of the conditions mentioned above is not met, the can module will operate as follows. - if the can sleep mode is requested from the initia lization mode, the can sleep mode transition request is ignored and the can module remains in the initialization mode. - if the can bus state is not bus idle (i.e., the can bus state is either transmitting or receiving) when the can sleep mode is requested in one of the operation modes, immediate transit ion to the can sleep mode is not possible. in this case, the can sleep mode transit ion request is held pending until the can bus state becomes bus idle (the 4th bit in the interframe spac e is recessive). in the time from the can sleep mode request to successful transition, the psmode [1:0] bi ts remain 00b. when the module has entered the can sleep mode, psmode [1:0] bits are set to 01b. - if a request for transition to the initialization mode a nd a request for transition to the can sleep are made at the same time while the can module is in one of t he operation modes, the request for the initialization mode is enabled. the can module enters the initialization mode at a predete rmined timing. at this time, the can sleep mode request is not held pending and is ignored. chapter 16 can controller user?s manual u17553ej4v0ud 473 - even when initialization mode and sleep mode are not requested simultaneously (i.e the first request has not been granted while the second reques t is made), the request for initializ ation has priority over the sleep mode request. the sleep mode request is cancelled wh en the initialization mode is requested. when a pending request for initialization mode is pres ent, a subsequent request for sleep mode request is cancelled right at the point in time where it was submitted. (2) status in can sleep mode the can module is in one of the following states after it enters the can sleep mode. - the internal operating clock is stopped a nd the power consumption is minimized. - the function to detect the falling edge of the can reception pin (crxd) remains in effect to wake up the can module from the can bus. - to wake up the can module from the cpu, data can be written to psmode [1:0] of the can module control register (c0ctrl), but nothing can be wr itten to other can module registers or bits. - the can module registers can be read, exc ept for c0lipt, c0rgpt, c0lopt, and c0tgpt. - the can message buffer register s cannot be written or read. - mbon bit of the can global control register (c0gmctrl) is cleared. - a request for transition to the initializati on mode is not acknowledged and is ignored. (3) releasing can sleep mode the can sleep mode is releas ed by the following events. - when the cpu writes 00b to the psmode [1:0] bits of the c0ctrl register - a falling edge at the can reception pin (crxd) (i.e. the can bus level shifts from recessive to dominant) caution even if the falling edge belongs to the so f of a receive message, this message will not be received and stored. if the cpu has turned off the clock to the can while the can was in sleep mode, even subsequently the can sl eep mode will not be released and psmode [1:0] will continue to be 01b unless the clock to the can is supplied again. in addition to this, the receive message will not be received after that. after releasing the sleep mode, the can module return s to the operation mode fr om which the can sleep mode was requested and the psmode [1:0] bits of the c0ct rl register are reset to 00b. if the can sleep mode is released by a change in the ca n bus state, the cints5 bit of t he c0ints register is set to 1, regardless of the cie bit of the c0ie register. after t he can module is released from the can sleep mode, it participates in the can bus again by automatically detecting 11 consecutive recessive-level bits on the can bus. the user application has to wait until mb on = 1, before accessing message buffers again. when a request for transition to the initialization mode is made while the can module is in the can sleep mode, that request is ignored; the cp u has to be released from sleep m ode by software first before entering the initialization mode. caution be aware that the re lease of can sleep mode by can bus event, and thus the wake up interrupt may happen at any time, even right after requesting sleep mode, if a can bus event occurs. remark m = 0 to 15 chapter 16 can controller user?s manual u17553ej4v0ud 474 16.11.2 can stop mode the can stop mode can be used to set the can controller to standby mode to reduce power consumption. the can module can enter the can stop mode only from the ca n sleep mode. release of the can stop mode puts the can module in the can sleep mode. the can stop mode can only be released (entering can sl eep mode) by writing 01b to the psmode [1:0] bits of the c0ctrl register and not by a c hange in the can bus state. no mess age is transmitted even when transmission requests are issued or pending. (1) entering can stop mode a can stop mode transition request is issued by writ ing 11b to the psmode [1:0] bits of the c0ctrl register. a can stop mode request is only acknowledged when the can module is in the can sleep mode. in all other modes, the request is ignored. caution to set the can module to the can stop mode, the module must be in the can sleep mode. to confirm that the module is in the sleep mode, check that psmode [1:0] = 01b, and then request the can stop mode. if a bus change occurs at the can reception pin (crxd) while this process is being perfo rmed, the can sleep mode is automatically released. in this case, the can stop mode transition request cannot be acknowledged. (2) status in can stop mode the can module is in one of the following states after it enters the can stop mode. - the internal operating clock is stopped a nd the power consumption is minimized. - to wake up the can module from the cpu, data can be written to psmode [1:0] of the can module control register (c0ctrl), but nothing can be wr itten to other can module registers or bits. - the can module registers can be read, exc ept for c0lipt, c0rgpt, c0lopt, and c0tgpt. - the can message buffer register s cannot be written or read. - mbon bit of the can global control register (c0gmctrl) is cleared. - an initialization mode transition request is not acknowledged and is ignored. (3) releasing can stop mode the can stop mode can only be released by writing 01b to the psmode [1:0] bits of the c0ctrl register. after releasing the can stop mode, the can module enters the can sleep mode. when the initialization mode is reques ted while the can module is in the can stop mode, that request is ignored; the cpu has to release the stop mode a nd subsequently can sleep mode before entering the initialization mode. it is impossi ble to enter the other operation mode directly fr om the can stop mode not entering the can sleep mode , that request is ignored. remark m = 0 to 15 chapter 16 can controller user?s manual u17553ej4v0ud 475 16.11.3 example of us ing power saving modes in some application systems, it may be necessary to plac e the cpu in a power saving mode to reduce the power consumption. by using the power saving mode specific to the can module and the power saving mode specific to the cpu in combination, the cpu can be woken up fr om the power saving status by the can bus. here is an example of using the power saving modes. first, put the can module in the can sleep mode (psmode = 01b). next, put the cp u in the power saving mode. if an edge transition from recessive to dominant is dete cted at the can reception pin (crxd) in this status, the cints5 bit in the can module is set to 1. if the cie5 bi t of the c0ctrl register is set to 1, a wakeup interrupt (intc0wup) is generated. the can mo dule is automatically released fr om the can sleep mode (psmode = 00b) and returns to the normal operation mode. the cpu, in response to intc0wup, can release its own power saving mode and return to the normal operation mode. to further reduce the power consumpti on of the cpu, the internal clocks, in cluding that of the can module, may be stopped. in this case, the operating clock supplied to the can module is stopped afte r the can module is put in the can sleep mode. then the cpu enters a power saving m ode in which the clock supplied to the cpu is stopped. if an edge transition from recessive to dominant is detected at the can reception pin (crxd) in this status, the can module can set the cints5 bit to 1 and generate the wakeup interrupt (intc0wup) even if it is not supplied with the clock. the other functions, however, do not operate because clock supply to the can module is stopped, and the module remains in the can sleep mode. the cpu, in response to intc0wup, releases its power saving mode, resumes supply of the internal clocks, including the clock to the can module, after the oscillation stabilization time has elapsed, and starts instruction execution. the can module is immediately rel eased from the can sleep mode when clock supply is resumed, and returns to the normal operation mode (psmode = 00b). chapter 16 can controller user?s manual u17553ej4v0ud 476 16.12 interrupt function the can module provides 6 different interrupt sources. the occurrence of these interrupt source s is stored in interrupt status regist ers. four separate interrupt request signals are generated from the six interrupt sources. when an interrupt request signal that corresponds to two or more interrupt sources is generated, the interrupt sources can be identified by us ing an interrupt status register. after an interrupt source has occurred, the corresponding inte rrupt status bit must be cleared to 0 by software. table 16-20. list of can module interrupt sources no. interrupt status bit interrupt enable bit name register name register interrupt request signal interrupt source description 1 cints0 note c0ints cie0 note c0ie intc0trx message fram e successfully transmitted from message buffer m 2 cints1 note c0ints cie1 note c0ie intc0rec valid message frame reception in message buffer m 3 cints2 c0ints cie2 c0ie can module error state interrupt (supplement 1) 4 cints3 c0ints cie3 c0ie can module protocol error interrupt (supplement 2) 5 cints4 c0ints cie4 c0ie intc0err can module arbitration loss interrupt 6 cints5 c0ints cie5 c0ie intc0wup can module wakeup interrupt from can sleep mode (supplement 3) note the ie bit (message buffer interrupt enable bit) in th e c0mctrl register of the corresponding message buffer has to be set to 1 for that message buffer to par ticipate in the interrupt generation process. supplements 1. this interrupt is generated when the transmi ssion/reception error counter is at the warning level, or in the error passive or bus-off state. 2. this interrupt is generated when a stuff error, fo rm error, ack error, bit e rror, or crc error occurs. 3. this interrupt is generated when the can m odule is woken up from the can sleep mode because a falling edge is detected at the can reception pin (can bus transition from recessive to dominant). remark m = 0 to 15 chapter 16 can controller user?s manual u17553ej4v0ud 477 16.13 diagnosis functions and special operational modes the can module provides a receive-only mode, single- shot mode, and self-test mode to support can bus diagnosis functions or the operation of specific can communication methods. 16.13.1 receive-only mode the receive-only mode is used to monitor receive mess ages without causing any interference on the can bus and can be used for can bus analysis nodes. for example, this mode can be used for automatic baud- rate detection. the baud rate in the can module is changed until "valid reception" is detec ted, so that the baud rates in the module match ("valid reception" means a message frame has been received in the can protocol la yer without occurrence of an error and with an appropriate ack between nodes connected to the can bus). a valid rec eption does not require mess age frames to be stored in a receive message buffer (data frames) or transmit message bu ffer (remote frames). the event of valid reception is indicated by setting the valid bit of the c0ctrl register (1). figure 16-33. can module terminal co nnection in receive-only mode can macro rx tx ctxd crxd fixed to the recessive level in the receive-only mode, no message frames can be transm itted from the can module to the can bus. transmit requests issued for message buffers defined as transmit message buffers are held pending. in the receive-only mode, the can transmission pin (ctxd) in the can module is fixed to the recessive level. therefore, no active error flag can be transmitted from t he can module to the can bus even when a can bus error is detected while receiving a message frame. since no transmission can be issued from the can module, the transmission error counter tec is never updated. therefore, a can module in the receive-only mode does not enter the bus-off state. chapter 16 can controller user?s manual u17553ej4v0ud 478 furthermore, ack is not returned to the can bus in th is mode upon the valid reception of a message frame. internally, the local node recognizes that it has transmitted ack. an overload frame cannot be transmitted to the can bus. caution if only two can nodes are connected to the can bus and one of them is operating in the receive-only mode, there is no ack on the can bus . due to the missing ack, the transmitting node will transmit an active error flag, and repeat transmitting a message frame. the transmitting node becomes error passive afte r transmitting the me ssage frame 16 times (assuming that the error counter was 0 in the beginning and no other errors have occurred). after the message frame for the 17th time is transmitted, the transm itting node generates a passive error flag. the receiving node in the receive-only mode detects the first valid message frame at this point, and the valid bi t is set to 1 for the first time. 16.13.2 single-shot mode in the single-shot mode, automatic re-t ransmission as defined in the can protoc ol is switched off (according to the can protocol, a message frame transmission that has been aborted by either arbitration loss or error occurrence has to be repeated without control by software.). all other behavior of single shot mode is identical to normal operation mode. features of single shot mode can not be used in combination with normal mode with abt. the single-shot mode disables the re-transmission of an aborted message frame transmission according to the setting of the al bit of the c0ctrl register. when the al bi t is cleared to 0, re-transmission upon arbitration loss and upon error occurrence is disabled. if the al bit is set to 1, re-transmission upon error occurrence is disabled, but re- transmission upon arbitration loss is enabled. as a cons equence, the trq bit in a message buffer defined as a transmit message buffer is cleared to 0 by the following events. - successful transmission of the message frame - arbitration loss while sending the message frame - error occurrence while sending the message frame the events arbitration loss and error occurrence can be dist inguished by checking the cints4 and cints3 bits of the c0ints register respectively, and the type of the error can be identified by reading th e lec[2:0] bits of the c0lec register. upon successful transmission of the message frame, the transmit completion interrupt bit cints0 of the c0ints register is set to 1. if the cie0 bit of the c0ie register is set to 1 at this time, an in terrupt request signal is output. the single-shot mode can be used when emulating time-t riggered communication method s (e.g. ttcan level 1). caution the al bit is only valid in single-shot mode. it does not influence the operation of re- transmission upon arbitration loss in the other operation modes. chapter 16 can controller user?s manual u17553ej4v0ud 479 16.13.3 self-test mode in the self-test mode, message frame transmission and message frame reception can be tested without connecting the can node to the can bus or without affecting the can bus. in the self-test mode, the can module is completely disconnected from the ca n bus, but transmission and reception are internally looped back. the can transmi ssion pin (ctxd) is fixed to the recessive level. if the falling edge on the can reception pin (crxd) is detected after the can module has entered the can sleep mode from the self-test mode, however, the module is released from the can sl eep mode in the same manner as the other operation modes. to keep the module in the can sle ep mode, use the can reception pin (crxd) as a port pin. figure 16-34. can module terminal connection in self-test mode can macro rx tx ctxd crxd fixed to the recessive level chapter 16 can controller user?s manual u17553ej4v0ud 480 16.13.4 receive/transmit operat ion in each operation mode table 16-21 shows outline of the receive/tr ansmit operation in each operation mode. table 16-21. outline of the receive/transmit in each operation mode operation mode transmission of data/ remote frame transmission of ack transmission of error/ overload frame transmission retry automatic block transmission (abt) set of valid bit store data to message buffer initialization mode no no no no no no no normal operation mode yes yes yes yes no yes yes normal operation mode with abt yes yes yes yes yes yes yes receive- only mode no no no no no yes yes single-shot mode yes yes yes no note 1 no yes yes self-test mode yes note 2 yes note 2 yes note 2 yes note 2 no yes note 2 yes note 2 notes 1. when the arbitration lost occurs, c ontrol of re-transmission is possible by the al bit of c0ctrl register. 2. each signals are not generated to out side, but generated into the can module. chapter 16 can controller user?s manual u17553ej4v0ud 481 16.14 time stamp function can is an asynchronous, serial protocol. all nodes connect ed to the can bus have a local, autonomous clock. as a consequence, the clocks of the nodes have no relation (i.e., the clocks are asynchronous and may have different frequencies). in some applications, however, a common time base over the network (= global time base) is needed. in order to build up a global time base, a time stam p function is used. the essential mechan ism of a time stamp function is the capture of timer values triggered by signals on the can bus. 16.14.1 time stamp function the can controller supports the capturing of timer values triggered by a specific frame. an on-chip 16-bit capture timer unit in a microcontroller system is us ed in addition to the can c ontroller. the 16-bit capture timer unit captures the timer value according to a trigger signal (tsout) for ca pturing that is out put when a data frame is received from the can controller. the cpu can retrie ve the time of occurrence of the capt ure event, i.e., the time stamp of the message received from the can bus, by reading the capt ured value. tsout signal can be selected from the following two event sources and is specified by the tssel bit of the c0ts register. - sof event (start of frame) (tssel = 0) - eof event (last bit of end of frame) (tssel = 1) the tsout signal is enabled by setting the t sen bit of the c0ts register to 1. figure 16-35. timing diagram of capture signal tsout t tsout sof sof sof sof tsout signal toggles its level upon occurrence of the se lected event during data frame reception (in the above timing diagram, the sof is used as the trigger event source ). to capture a timer value by using tsout signal, the capture timer unit must detect the capture signal at both th e rising edge and falling edge. this time stamp function is controlled by the tslock bi t of the c0ts register. when tslock is cleared to 0, tsout bit toggles upon occurrence of the selected event. if tslock bit is set to 1, tsout toggles upon occurrence of the selected event, but the toggle is stopped as the tsen bit is automatically cleared to 0 as soon as the message storing to the message buffer 0 starts. this suppresses the subsequent toggle occurrenc e by tsout, so that the time stamp value toggled last (= captured last) can be sav ed as the time stamp value of the time at which the data frame was received in message buffer 0. chapter 16 can controller user?s manual u17553ej4v0ud 482 caution the time stamp function us ing tslock bit is to stop toggle of tsout bit by receiving a data frame in message buffer 0. therefore, messag e buffer 0 must be set as a receive message buffer. since a receive messag e buffer cannot receive a remote frame, toggle of tsout bit cannot be stopped by reception of a remote frame. toggle of tsout bit does not stop when a data frame is received in a messag e buffer other than message buffer 0. for these reasons, a data frame cannot be r eceived in message buffer 0 when the can module is in the normal operation mode with abt, because message buffer 0 must be set as a transmit message buffer. in this operati on mode, therefore, the function to stop toggle of tsout bit by tslock bit cannot be used. the input source of the timer value according to a tri gger signal (tsout) can be input to the 16-bit timer/event counter 00 by port input switch control (i sc0), without connectingti000, externally. figure 16-36. port input switch control ti000 input p00/ti000 port input switch control (isc0) chapter 16 can controller user?s manual u17553ej4v0ud 483 16.15 baud rate settings 16.15.1 baud rate settings make sure that the settings are within the range of limit values for ensuring co rrect operation of the can controller, as follows. (a) 5tq spt (sampling point) 17 tq spt = tseg1 + 1 (b) 8 tq dbt (data bit time) 25 tq dbt = tseg1 + tseg2 + 1tq = tseg2 + spt (c) 1 tq sjw (synchronization jump width) 4tq sjw dbt ? spt (d) 4 tseg1 16 [3 (setting value of tseg1 [3:0] 15] (e) 1 tseg2 8 [0 (setting value of tseg2 [2:0] 7] remark tq = 1/f tq (f tq : can protocol layer basic system clock) tseg1 [3:0]: bits 3 to 0 of can0 bit rate register (c0btr) tseg2 [2:0]: bits 10 to 8 of can0 bit rate register (c0btr) table 16-22 shows the combinations of bit rate s that satisfy the above conditions. chapter 16 can controller user?s manual u17553ej4v0ud 484 table 16-22. settable bit rate combinations (1/3) valid bit rate setting c0btr register setting value dbt length sync segment prop segment phase segment1 phase segment2 tseg1[3:0] tseg2[2:0] sampling point (unit %) 25 1 8 8 8 1111 111 68.0 24 1 7 8 8 1110 111 66.7 24 1 9 7 7 1111 110 70.8 23 1 6 8 8 1101 111 65.2 23 1 8 7 7 1110 110 69.6 23 1 10 6 6 1111 101 73.9 22 1 5 8 8 1100 111 63.6 22 1 7 7 7 1101 110 68.2 22 1 9 6 6 1110 101 72.7 22 1 11 5 5 1111 100 77.3 21 1 4 8 8 1011 111 61.9 21 1 6 7 7 1100 110 66.7 21 1 8 6 6 1101 101 71.4 21 1 10 5 5 1110 100 76.2 21 1 12 4 4 1111 011 81.0 20 1 3 8 8 1010 111 60.0 20 1 5 7 7 1011 110 65.0 20 1 7 6 6 1100 101 70.0 20 1 9 5 5 1101 100 75.0 20 1 11 4 4 1110 011 80.0 20 1 13 3 3 1111 010 85.0 19 1 2 8 8 1001 111 57.9 19 1 4 7 7 1010 110 63.2 19 1 6 6 6 1011 101 68.4 19 1 8 5 5 1100 100 73.7 19 1 10 4 4 1101 011 78.9 19 1 12 3 3 1110 010 84.2 19 1 14 2 2 1111 001 89.5 18 1 1 8 8 1000 111 55.6 18 1 3 7 7 1001 110 61.1 18 1 5 6 6 1010 101 66.7 18 1 7 5 5 1011 100 72.2 18 1 9 4 4 1100 011 77.8 18 1 11 3 3 1101 010 83.3 18 1 13 2 2 1110 001 88.9 18 1 15 1 1 1111 000 94.4 chapter 16 can controller user?s manual u17553ej4v0ud 485 table 16-22. settable bit rate combinations (2/3) valid bit rate setting c0btr register setting value dbt length sync segment prop segment phase segment1 phase segment2 tseg1[3:0] tseg2[2:0] sampling point (unit %) 17 1 2 7 7 1000 110 58.8 17 1 4 6 6 1001 101 64.7 17 1 6 5 5 1010 100 70.6 17 1 8 4 4 1011 011 76.5 17 1 10 3 3 1100 010 82.4 17 1 12 2 2 1101 001 88.2 17 1 14 1 1 1110 000 94.1 16 1 1 7 7 0111 110 56.3 16 1 3 6 6 1000 101 62.5 16 1 5 5 5 1001 100 68.8 16 1 7 4 4 1010 011 75.0 16 1 9 3 3 1011 010 81.3 16 1 11 2 2 1100 001 87.5 16 1 13 1 1 1101 000 93.8 15 1 2 6 6 0111 101 60.0 15 1 4 5 5 1000 100 66.7 15 1 6 4 4 1001 011 73.3 15 1 8 3 3 1010 010 80.0 15 1 10 2 2 1011 001 86.7 15 1 12 1 1 1100 000 93.3 14 1 1 6 6 0110 101 57.1 14 1 3 5 5 0111 100 64.3 14 1 5 4 4 1000 011 71.4 14 1 7 3 3 1001 010 78.6 14 1 9 2 2 1010 001 85.7 14 1 11 1 1 1011 000 92.9 13 1 2 5 5 0110 100 61.5 13 1 4 4 4 0111 011 69.2 13 1 6 3 3 1000 010 76.9 13 1 8 2 2 1001 001 84.6 13 1 10 1 1 1010 000 92.3 12 1 1 5 5 0101 100 58.3 12 1 3 4 4 0110 011 66.7 12 1 5 3 3 0111 010 75.0 12 1 7 2 2 1000 001 83.3 12 1 9 1 1 1001 000 91.7 chapter 16 can controller user?s manual u17553ej4v0ud 486 table 16-22. settable bit rate combinations (3/3) valid bit rate setting c0btr register setting value dbt length sync segment prop segment phase segment1 phase segment2 tseg1[3:0] tseg2[2:0] sampling point (unit %) 11 1 2 4 4 0101 011 63.6 11 1 4 3 3 0110 010 72.7 11 1 6 2 2 0111 001 81.8 11 1 8 1 1 1000 000 90.9 10 1 1 4 4 0100 011 60.0 10 1 3 3 3 0101 010 70.0 10 1 5 2 2 0110 001 80.0 10 1 7 1 1 0111 000 90.0 9 1 2 3 3 0100 010 66.7 9 1 4 2 2 0101 001 77.8 9 1 6 1 1 0110 000 88.9 8 1 1 3 3 0011 010 62.5 8 1 3 2 2 0100 001 75.0 8 1 5 1 1 0101 000 87.5 7 note 1 2 2 2 0011 001 71.4 7 note 1 4 1 1 0100 000 85.7 6 note 1 1 2 2 0010 001 66.7 6 note 1 3 1 1 0011 000 83.3 5 note 1 2 1 1 0010 000 80.0 4 note 1 1 1 1 0001 000 75.0 note setting with a dbt value of 7 or less is valid only wh en the value of the c0brp re gister is other than 00h. caution the values in table 16-22 do not guarantee th e operation of the network system. thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the can bus and can transceiver. chapter 16 can controller user?s manual u17553ej4v0ud 487 16.15.2 representative examples of baud rate settings tables 16-23 and 16-24 show representative examples of baud rate setting. table 16-23. representative e xamples of baud rate settings (f canmod = 8 mhz) (1/2) valid bit rate setting (unit: kbps) c0btr register setting value set baud rate value (unit: kbps) division ratio of c0brp c0brp register set value length of dbt sync segme nt prop segme nt phase segme nt1 phase segme nt2 tseg1 [3:0] tseg2 [2:0] samplin g point (unit: %) 1000 1 00000000 8 1 1 3 3 0011 010 62.5 1000 1 00000000 8 1 3 2 2 0100 001 75.0 1000 1 00000000 8 1 5 1 1 0101 000 87.5 500 1 00000000 16 1 1 7 7 0111 110 56.3 500 1 00000000 16 1 3 6 6 1000 101 62.5 500 1 00000000 16 1 5 5 5 1001 100 68.8 500 1 00000000 16 1 7 4 4 1010 011 75.0 500 1 00000000 16 1 9 3 3 1011 010 81.3 500 1 00000000 16 1 11 2 2 1100 001 87.5 500 1 00000000 16 1 13 1 1 1101 000 93.8 500 2 00000001 8 1 1 3 3 0011 010 62.5 500 2 00000001 8 1 3 2 2 0100 001 75.0 500 2 00000001 8 1 5 1 1 0101 000 87.5 250 2 00000001 16 1 1 7 7 0111 110 56.3 250 2 00000001 16 1 3 6 6 1000 101 62.5 250 2 00000001 16 1 5 5 5 1001 100 68.8 250 2 00000001 16 1 7 4 4 1010 011 75.0 250 2 00000001 16 1 9 3 3 1011 010 81.3 250 2 00000001 16 1 11 2 2 1100 001 87.5 250 2 00000001 16 1 13 1 1 1101 000 93.8 250 4 00000011 8 1 3 2 2 0100 001 75.0 250 4 00000011 8 1 5 1 1 0101 000 87.5 125 4 00000011 16 1 1 7 7 0111 110 56.3 125 4 00000011 16 1 3 6 6 1000 101 62.5 125 4 00000011 16 1 5 5 5 1001 100 68.8 125 4 00000011 16 1 7 4 4 1010 011 75.0 125 4 00000011 16 1 9 3 3 1011 010 81.3 125 4 00000011 16 1 11 2 2 1100 001 87.5 125 4 00000011 16 1 13 1 1 1101 000 93.8 125 8 00000111 8 1 3 2 2 0100 001 75.0 125 8 00000111 8 1 5 1 1 0101 000 87.5 caution the values in table 16-23 do not guarantee the operation of the network system. thoroughly check the effect on the network system, taking into consideration oscillati on errors and delays of the can bus and can transceiver. chapter 16 can controller user?s manual u17553ej4v0ud 488 table 16-23. representative e xamples of baud rate settings (f canmod = 8 mhz) (2/2) valid bit rate setting (unit: kbps) c0btr register setting value set baud rate value (unit: kbps) division ratio of c0brp c0brp register set value length of dbt sync segme nt prop segme nt phase segme nt1 phase segme nt2 tseg1 [3:0] tseg2 [2:0] samplin g point (unit: %) 100 4 00000011 20 1 7 6 6 1100 101 70.0 100 4 00000011 20 1 9 5 5 1101 100 75.0 100 5 00000100 16 1 7 4 4 1010 011 75.0 100 5 00000100 16 1 9 3 3 1011 010 81.3 100 8 00000111 10 1 3 3 3 0101 010 70.0 100 8 00000111 10 1 5 2 2 0110 001 80.0 100 10 00001001 8 1 3 2 2 0100 001 75.0 100 10 00001001 8 1 5 1 1 0101 000 87.5 83.3 4 00000011 24 1 7 8 8 1110 111 66.7 83.3 4 00000011 24 1 9 7 7 1111 110 70.8 83.3 6 00000101 16 1 5 5 5 1001 100 68.8 83.3 6 00000101 16 1 7 4 4 1010 011 75.0 83.3 6 00000101 16 1 9 3 3 1011 010 81.3 83.3 6 00000101 16 1 11 2 2 1100 001 87.5 83.3 8 00000111 12 1 5 3 3 0111 010 75.0 83.3 8 00000111 12 1 7 2 2 1000 001 83.3 83.3 12 00001011 8 1 3 2 2 0100 001 75.0 83.3 12 00001011 8 1 5 1 1 0101 000 87.5 33.3 10 00001001 24 1 7 8 8 1110 111 66.7 33.3 10 00001001 24 1 9 7 7 1111 110 70.8 33.3 12 00001011 20 1 7 6 6 1100 101 70.0 33.3 12 00001011 20 1 9 5 5 1101 100 75.0 33.3 15 00001110 16 1 7 4 4 1010 011 75.0 33.3 15 00001110 16 1 9 3 3 1011 010 81.3 33.3 16 00001111 15 1 6 4 4 1001 011 73.3 33.3 16 00001111 15 1 8 3 3 1010 010 80.0 33.3 20 00010011 12 1 5 3 3 0111 010 75.0 33.3 20 00010011 12 1 7 2 2 1000 001 83.3 33.3 24 00010111 10 1 3 3 3 0101 010 70.0 33.3 24 00010111 10 1 5 2 2 0110 001 80.0 33.3 30 00011101 8 1 3 2 2 0100 001 75.0 33.3 30 00011101 8 1 5 1 1 0101 000 87.5 caution the values in table 16-23 do not guarantee the operation of the ne twork system. thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the can bus and can transceiver. chapter 16 can controller user?s manual u17553ej4v0ud 489 table 16-24. representative e xamples of baud rate settings (f canmod = 16 mhz) (1/2) valid bit rate setting (unit: kbps) c0btr register setting value set baud rate value (unit: kbps) division ratio of c0brp c0brp register set value length of dbt sync segme nt prop segme nt phase segme nt1 phase segme nt2 tseg1 [3:0] tseg2 [2:0] samplin g point (unit: %) 1000 1 00000000 16 1 1 7 7 0111 110 56.3 1000 1 00000000 16 1 3 6 6 1000 101 62.5 1000 1 00000000 16 1 5 5 5 1001 100 68.8 1000 1 00000000 16 1 7 4 4 1010 011 75.0 1000 1 00000000 16 1 9 3 3 1011 010 81.3 1000 1 00000000 16 1 11 2 2 1100 001 87.5 1000 1 00000000 16 1 13 1 1 1101 000 93.8 1000 2 00000001 8 1 3 2 2 0100 001 75.0 1000 2 00000001 8 1 5 1 1 0101 000 87.5 500 2 00000001 16 1 1 7 7 0111 110 56.3 500 2 00000001 16 1 3 6 6 1000 101 62.5 500 2 00000001 16 1 5 5 5 1001 100 68.8 500 2 00000001 16 1 7 4 4 1010 011 75.0 500 2 00000001 16 1 9 3 3 1011 010 81.3 500 2 00000001 16 1 11 2 2 1100 001 87.5 500 2 00000001 16 1 13 1 1 1101 000 93.8 500 4 00000011 8 1 3 2 2 0100 001 75.0 500 4 00000011 8 1 5 1 1 0101 000 87.5 250 4 00000011 16 1 3 6 6 1000 101 62.5 250 4 00000011 16 1 5 5 5 1001 100 68.8 250 4 00000011 16 1 7 4 4 1010 011 75.0 250 4 00000011 16 1 9 3 3 1011 010 81.3 250 4 00000011 16 1 11 2 2 1100 001 87.5 250 8 00000111 8 1 3 2 2 0100 001 75.0 250 8 00000111 8 1 5 1 1 0101 000 87.5 125 8 00000111 16 1 3 6 6 1000 101 62.5 125 8 00000111 16 1 7 4 4 1010 011 75.0 125 8 00000111 16 1 9 3 3 1011 010 81.3 125 8 00000111 16 1 11 2 2 1100 001 87.5 125 16 00001111 8 1 3 2 2 0100 001 75.0 125 16 00001111 8 1 5 1 1 0101 000 87.5 caution the values in table 16-24 do not guarantee the operation of the network system. thoroughly check the effect on the network system, taking into consideration oscillati on errors and delays of the can bus and can transceiver. chapter 16 can controller user?s manual u17553ej4v0ud 490 table 16-24. representative e xamples of baud rate settings (f canmod = 16 mhz) (2/2) valid bit rate setting (unit: kbps) c0btr register setting value set baud rate value (unit: kbps) division ratio of c0brp c0brp register set value length of dbt sync segme nt prop segme nt phase segme nt1 phase segme nt2 tseg1 [3:0] tseg2 [2:0] samplin g point (unit: %) 100 8 00000111 20 1 9 5 5 1101 100 75.0 100 8 00000111 20 1 11 4 4 1110 011 80.0 100 10 00001001 16 1 7 4 4 1010 011 75.0 100 10 00001001 16 1 9 3 3 1011 010 81.3 100 16 00001111 10 1 3 3 3 0101 010 70.0 100 16 00001111 10 1 5 2 2 0110 001 80.0 100 20 00010011 8 1 3 2 2 0100 001 75.0 83.3 8 00000111 24 1 7 8 8 1110 111 66.7 83.3 8 00000111 24 1 9 7 7 1111 110 70.8 83.3 12 00001011 16 1 7 4 4 1010 011 75.0 83.3 12 00001011 16 1 9 3 3 1011 010 81.3 83.3 12 00001011 16 1 11 2 2 1100 001 87.5 83.3 16 00001111 12 1 5 3 3 0111 010 75.0 83.3 16 00001111 12 1 7 2 2 1000 001 83.3 83.3 24 00010111 8 1 3 2 2 0100 001 75.0 83.3 24 00010111 8 1 5 1 1 0101 000 87.5 33.3 30 00011101 24 1 7 8 8 1110 111 66.7 33.3 30 00011101 24 1 9 7 7 1111 110 70.8 33.3 24 00010111 20 1 9 5 5 1101 100 75.0 33.3 24 00010111 20 1 11 4 4 1110 011 80.0 33.3 30 00011101 16 1 7 4 4 1010 011 75.0 33.3 30 00011101 16 1 9 3 3 1011 010 81.3 33.3 32 00011111 15 1 8 3 3 1010 010 80.0 33.3 32 00011111 15 1 10 2 2 1011 001 86.7 33.3 37 00100100 13 1 6 3 3 1000 010 76.9 33.3 37 00100100 13 1 8 2 2 1001 001 84.6 33.3 40 00100111 12 1 5 3 3 0111 010 75.0 33.3 40 00100111 12 1 7 2 2 1000 001 83.3 33.3 48 00101111 10 1 3 3 3 0101 010 70.0 33.3 48 00101111 10 1 5 2 2 0110 001 80.0 33.3 60 00111011 8 1 3 2 2 0100 001 75.0 33.3 60 00111011 8 1 5 1 1 0101 000 87.5 caution the values in table 16-24 do not guarantee the operation of the network system. thoroughly check the effect on the network system, taking into consideration oscillati on errors and delays of the can bus and can transceiver. chapter 16 can controller user?s manual u17553ej4v0ud 491 16.16 operation of can controller remark m = 0 to 15 figure 16-37. initialization start set cngmcs registe r set cngmctrl register (set gom = 1) set cnie register set cnmask registe r end initialize message buffers set cnbrp register, cnbtr register set cnctrl register (set opmode) remark opmode: normal operation mode, normal operati on mode with abt, receive-only mode, single- shot mode, self-test mode chapter 16 can controller user?s manual u17553ej4v0ud 492 figure 16-38. re-initialization start set c0brp register, c0btr register set c0ie register set c0mask register set c0ctrl register (set opmode) end clear opmode init mode? no yes set ccerc bit yes no initialize message buffers c0erc and c0info register clear? caution after setting the can module to the initia lization mode, avoid setti ng the module to another operation mode immediately after. if it is n ecessary to immediately se t the module to another operation mode, be sure to access registers othe r than the c0ctrl and c0gmctrl registers (e.g. set a message buffer). remark opmode: normal operation mode, normal operati on mode with abt, receive-only mode, single- shot mode, self-test mode chapter 16 can controller user?s manual u17553ej4v0ud 493 figure 16-39. message buffer initialization start set c0mconfm registe r end rdy = 1? no yes rdy = 0? set c0midhm register, c0midlm registe r transmit message buffer? clea r c0mdatam registe r set registe r set registe r no no yes yes start clear rdy bit set rdy bit c0mdlcm c0mctrlm cautions 1. before a message buffer is in itialized, the rdy bit must be cleared. 2. make the following settings for message buffers not u sed by the application. - clear the rdy, trq, and dn bits of the c0mctrlm register to 0. - clear the ma0 bit of th e c0mconfm register to 0. chapter 16 can controller user?s manual u17553ej4v0ud 494 figure 16-40 shows the processing for a receive message buffer (mt [2:0] bits of c0mconfm register = 001b to 101b). figure 16-40. message buffer redefinition start set message buffers end rdy = 1? no yes clear rdy bit rdy = 0? rstat = 0 or valid = 1? note1 no clear valid bit set rdy bit yes yes no note 2 wait for 4 can data bits notes 1. confirm that a message is being received because rdy bit must be set after a message is completely received. 2. avoid message buffer redefinition dur ing store operation of message re ception by waiting additional 4 can data bits. chapter 16 can controller user?s manual u17553ej4v0ud 495 figure 16-41 shows the processing for a transmit message buffer during transmission (mt [2:0] bits of c0mconfm register = 000b). figure 16-41. message buffer re definition during transmission start end rdy = 0? no yes data frame or remote frame? set rdy bit set c0mdataxm register set c0mdlcm register clear rtr bit of c0mconfm register set c0midlm and c0midhm registers set c0mdlcm register set rtr bit of c0mconfm register set c0midlm and c0midhm registers remote frame data frame transmit abort process clear rdy bit transmit? set trq bit yes wait for 1can data bits no chapter 16 can controller user?s manual u17553ej4v0ud 496 figure 16-42 shows the processing for a transmit message buffer (mt [2:0] bits of c0mconfm register = 000b). figure 16-42. message transmit processing start end trq = 0? no yes rdy = 0? data frame or remote frame? set rdy bit yes no set c0mdataxm register set c0mdlcm register clear rtr bit of c0mconfm register set c0midlm and c0midhm registers set c0mdlcm register set rtr bit of c0mconfm register set c0midlm and c0midhm registers remote frame data frame clear rdy bit set trq bit cautions 1. the trq bit should be set after the rdy bit is set. 2. the rdy bit and trq bit should not be set at the same time. chapter 16 can controller user?s manual u17553ej4v0ud 497 figure 16-43 shows the processing for a transmit message buffer (mt [2:0] bits of c0mconfm register = 000b). figure 16-43. abt message transmit processing start set c0mdataxm register set c0mdlcm register clear rtr bit of c0mconfm register set c0midlm and c0midhm registers end abttrg = 0? no yes clear rdy bit rdy = 0? set rdy bit yes no set abttrg bit set all abt transmit messages? tstat = 0? yes no yes no caution the abttrg bit should be set to 1 after th e tstat bit is cleared to 0. checking the tstat bit and setting the abttrg bit to 1 must be processed continuously. remark this processing (normal operati on mode with abs) can only be appli ed to message buffers 0 to 7. for message buffers other than t he abt message buffers, refer to figure 16-42 . chapter 16 can controller user?s manual u17553ej4v0ud 498 figure 16-44. transmission via in terrupt (using c0lopt register) start end clear rdy bit rdy = 0? data frame or remote frame? set rdy bit yes no set c0mdataxm register set c0mdlcm register, clear rtr bit of c0mconfm register. set c0midlm and c0midhm registers set c0mdlcm register set rtr bit of c0mconfm register. set c0midlm and c0midhm registers set trq bit remote frame data frame transmit completion interrupt processing read c0lopt register cautions 1. the trq bit should be set after the rdy bit is set. 2. the rdy bit and trq bit should not be set at the same time. remark also check the mbon flag at the beginning and at the end of the interrupt routine, in order to check the access to the message buffers as well as tx history list registers, in case a pending sleep mode had been executed. if mbon is detected to be cleare d at any check, the actions and results of the processing have to be discarded and processed again, after mbon is set again. it is recommended to cancel any sleep mode requests, before processing tx interrupts. chapter 16 can controller user?s manual u17553ej4v0ud 499 figure 16-45. transmit via inte rrupt (using c0tgpt register) start end tovf = 1? data frame or remote frame? set rdy bit yes no set c0mdataxm register set c0mdlcm register clear rtr bit of c0mconfm register set c0midlm and c0midhm registers set c0mdlcm register set rtr bit of c0mconfm register set c0midlm and c0midhm registers set trq bit remote frame data frame read c0tgpt register clear tovf bit clear rdy bit rdy = 0? thpm = 1? no ye s no ye s transmit completion interrupt processing cautions 1. the trq bit should be set after the rdy bit is set. 2. the rdy bit and trq bit should not be set at the same time. remark also check the mbon flag at the beginning and at the end of the interrupt routine, in order to check the access to the message buffers as well as tx history list registers, in case a pending sleep mode had been executed. if mbon is detected to be cleare d at any check, the actions and results of the processing have to be discarded and processed again, after mbon is set again. it is recommended to cancel any sleep mode requests, before processing tx interrupts. chapter 16 can controller user?s manual u17553ej4v0ud 500 figure 16-46. transmi ssion via software polling start end tovf = 1? data frame or remote frame? set rdy bit yes no set c0mdataxm registe r set c0mdlcm register clear rtr bit of c0mconfm register. set c0midlm and c0midhm registers set c0mdlcm registe r set rtr bit of c0mconfm set c0midlm and c0midhm registers set trq bit remote frame data frame read c0tgpt register clear tovf bit clear rdy bit rdy = 0? thpm = 1? no ye s no ye s cints0 = 1? no clear cints0 bit ye s cautions 1. the trq bit should be set after the rdy bit is set. 2. the rdy bit and trq bit should not be set at the same time. remark also check the mbon flag at the beginning and at the end of the polling routine, in order to check the access to the message buffers as well as tx histor y list registers, in case a pending sleep mode had been executed. if mbon is detected to be clear ed at any check, the actions and results of the processing have to be discarded and processed again, after mbon is set again. chapter 16 can controller user?s manual u17553ej4v0ud 501 figure 16-47. transmission abort processi ng (except normal operation mode with abt) start read c0lopt registe r end no yes clear trq bit tstat = 0? message buffer to be aborted matches c0lopt register? no wait for 11 can data bits transmission successful transmit abort request was successful yes note note there is a possibility of star ting the transmission without being aborted even if trq bit is cleared, because the transmission request to protocol la yer might already been accepted between 11 bits, total of interframe space (3 bits ) and suspend transmission (8 bits). cautions 1. execute transmission request abort processing by clearing the trq bit, not the rdy bit. 2. before making a sleep mode transition re quest, confirm that there is no transmission request left using this processing. 3. the tstat bit can be periodically checked by a user applicati on or can be checked after the transmit completion interrupt. 4. do not execute the new transmission requ est including in the other message buffers while transmission abort processing is in progress. chapter 16 can controller user?s manual u17553ej4v0ud 502 figure 16-48. transmission abort pr ocessing except for abt transmission (normal operation mode with abt) start read c0lopt registe r end no yes clear trq bit tstat = 0? message buffer to be aborted matches c0lopt register? no wait for 11 can data bits transmission successful transmit abort request was successful yes no abttrg = 0? clear abttrg bit yes transmission successful transmit abort request was successful note note there is a possibility of star ting the transmission without being aborted even if trq bit is cleared, because the transmission request to protocol la yer might already been accepted between 11 bits, total of interframe space (3 bits ) and suspend transmission (8 bits). cautions 1. execute transmission request abort processing by clearing the trq bit, not the rdy bit. 2. before making a sleep mode transition re quest, confirm that there is no transmission request left using this processing. 3. the tstat bit can be periodically checked by a user applicati on or can be checked after the transmit completion interrupt. 4. do not execute the new transmission requ est including in the other message buffers while transmission abort processing is in progress. chapter 16 can controller user?s manual u17553ej4v0ud 503 figure 16-49 shows the processing not to skip resump tion of transmitting a message that was stopped when transmission of an abt message buffer was aborted. figure 16-49. abt transmission abort pro cessing (normal operation mode with abt) start end no clear abttrg bit abttrg = 0? transmission start no clear trq bit of message buffer whose transmission was aborted transmit abort yes set abtclr bit yes no tstat = 0? yes cautions 1. do not set any tr ansmission requests while abt tran smission abort processing is in progress. 2. make a can sleep mode/can stop mode transition request after abttrg bit is cleared (after abt mode is aborted) foll owing the procedure shown in figure 16-49 or 16-50. when clearing a transmission requ est in an area other than the abt area, follow the procedure shown in figure 16-47. chapter 16 can controller user?s manual u17553ej4v0ud 504 figure 16-50 shows the processing to skip resumption of transmitting a message that was stopped when transmission of an abt message buffer was aborted. figure 16-50. abt transmission request abort processing (normal operation mode with abt) start end no clear abttrg bit abttrg = 0? transmission start pointer clear? no transmit abort yes set abtclr bit yes clear trq bit of message buffe r undergoing transmission cautions 1. do not set any tr ansmission requests while abt tran smission abort processing is in progress. 2. make a can sleep mode/can stop mode re quest after abttrg is cleared (after abt mode is stopped) following the procedure shown in figure 16-49 or 16-50. when clearing a transmission request in an area other than the abt area, follow the procedure shown in figure 16-47. chapter 16 can controller user?s manual u17553ej4v0ud 505 figure 16-51. reception via inte rrupt (using c0lipt register) start no read c0mdataxm , c0mdlcm , c0midlm, and c0midhm registers dn = 0 and muc = 0 read c0lipt registe r yes generation of receive completion interrupt clear dn bit note end , , note check the muc and dn bits using one read access. remark also check the mbon flag at the beginning and at t he end of the interrupt rout ine, in order to check the access to the message buffers as well as recept ion history list registers, in case a pending sleep mode had been executed. if mbon is detected to be cleared at any check, the actions and results of the processing have to be discarded and pr ocessed again, after mbon is set again. it is recommended to cancel any sleep mode r equests, before processing rx interrupts. chapter 16 can controller user?s manual u17553ej4v0ud 506 figure 16-52. reception via inte rrupt (using c0rgpt register) no start clear rovf bit no rovf = 1? read c0rgpt registe r yes generation of receive completion interrupt clear dn bit dn = 0 and muc = 0 note rhpm = 1? end yes no yes read c0mdataxm , c0mdlcm , c0midlm, c0midhm registers , , , correct data is read ille g al data is read note check the muc and dn bits using one read access. remark also check the mbon flag at the beginning and at t he end of the interrupt rout ine, in order to check the access to the message buffers as well as recept ion history list registers, in case a pending sleep mode had been executed. if mbon is detected to be cleared at any check, the actions and results of the processing have to be discarded and pr ocessed again, after mbon is set again. it is recommended to cancel any sleep mode r equests, before processing rx interrupts. chapter 16 can controller user?s manual u17553ej4v0ud 507 figure 16-53. reception via software polling start cints1 = 1? yes no clear rovf bit no rovf = 1? read c0rgpt registe r ye s clear dn bit dn = 0 and muc = 0 note rhpm = 1? end ye s no yes no read c0mdataxm , c0mdlcm , c0midlm, c0midhm registers , , , correct data is read illegal data is read clear cints1 bit note check the muc and dn bits using one read access. remark also check the mbon flag at the beginning and at t he end of the polling routine, in order to check the access to the message buffers as well as recept ion history list registers, in case a pending sleep mode had been executed. if mbon is detected to be cleared at any check, the actions and results of the processing have to be discarded and pr ocessed again, after mbon is set again. chapter 16 can controller user?s manual u17553ej4v0ud 508 figure 16-54. setting can sleep mode/stop mode start (when psmode[1:0] = 00b) psmode0 = 1? set psmode0 bit can sleep mode can sleep mode end ye s no set psmode1 bit psmode1 = 1? can stop mode can stop mode request can sleep mode again? ye s no ye s no init mode? ye s no clear cints5 bit clear opmode access to registers other than the c0ctrl and c0gmctrl registers set c0ctrl register (set opmode) caution to abort transmission befo re making a request for the can sleep mode, perform processing according to figures 16-47 and 16-48. chapter 16 can controller user?s manual u17553ej4v0ud 509 figure 16-55. clear can sleep/stop mode start can sleep mode end clear psmode1 bit after crxd is dominant level, cints5 = 1 clear psmode0 can stop mode clear cints5 bit released by crxd at cpu not standby state (vpclk is still supplied) after cr x d is dominant level, psmode0 = 0, cints5 = 1 clear cints5 bit released by crxd at cpu standby state (vpclk is stopped) clear psmode0 released by user chapter 16 can controller user?s manual u17553ej4v0ud 510 figure 16-56. bus-off r ecovery (expect normal oper ation mode with abt) start access to registers other than c0ctrl and c0gmctrl registers set c0ctrl register (clear opmode) forced recovery from bus off? end boff = 1? yes no set ccerc bit set c0ctrl register (set opmode) wait for recovery from bus off set c0ctrl register (set opmode) ye s no clear all trq bits note note clear all trq bits when re-initialization of message buffer is executed by clearing rdy bit before bus-off recovery sequence is started. caution when the transmission from the initialization mode to any operation modes is requested to execute bus-off recovery sequen ce again in the bus-off recove ry sequence, reception error counter is cleared. therefore it is necessary to detect 11 c onsecutive recessive-level bi ts 128 times on the bus again. remark opmode: normal operation mode, normal operation mode with abt, receive-only mode, single-shot mode, self-test mode chapter 16 can controller user?s manual u17553ej4v0ud 511 figure 16-57. bus-off recovery (n ormal operation mode with abt) start access to registers other than c0ctrl and c0gmctrl registers set c0ctrl register (clear opmode) forced recovery from bus off? end boff = 1? yes no set ccerc bit set c0ctrl register (set opmode) wait for recovery from bus off set c0ctrl register (set opmode) ye s no clear all trq bits clear abttrg bit note note clear all trq bits when re-initialization of message buffer is executed by clearing rdy bit before bus-off recovery sequence is started. caution when the transmission from the initialization mode to any operation modes is requested to execute bus-off recovery sequen ce again in the bus-off recove ry sequence, reception error counter is cleared. therefore it is necessary to detect 11 con secutive recessive-level bi ts 128 times on the bus again. remark opmode: normal operation mode, normal operation mode with abt, receive-only mode, single-shot mode, self-test mode chapter 16 can controller user?s manual u17553ej4v0ud 512 figure 16-58. normal shutdown process start gom = 0? end yes no clear gom bit init mode shutdown successful gom = 0, efsd = 0 chapter 16 can controller user?s manual u17553ej4v0ud 513 figure 16-59. forced shutdown process start gom = 0? clear gom bit end yes no shutdown successful gom = 0, efsd = 0 set efsd bit must be a subseguent write caution do not read- or write-access any regist ers by software between setting the efsd bit and clearing the gom bit. chapter 16 can controller user?s manual u17553ej4v0ud 514 figure 16-60. error handling start clear cints2 bit cints2 = 1? cints3 = 1? end yes check can protocol error state (read c0lec register) no yes no error interrupt check can module state (read c0info register) cints4 = 1? no yes clear cints3 bit clear cints4 bit chapter 16 can controller user?s manual u17553ej4v0ud 515 figure 16-61. setting cpu standby (from can sleep mode) start psmode0 = 1? end yes set cpu standby mode no can sleep mode set psmode0 bit end caution before the cpu is set in the cpu standby mode, please check the can sleep mode or not. however, after check of the can sleep mode, until the cpu is set in the cpu standby mode, the can sleep mode may be cance lled by wakeup from can bus. chapter 16 can controller user?s manual u17553ej4v0ud 516 figure 16-62. setting cpu st andby (from can stop mode) start psmode0 = 1? yes no can sleep mode clear cints5 bit note set psmode0 bit set psmode1 bit can stop mode psmode1 = 1? end set cpu standby mode yes no note during wakeup interrupts caution the can stop mode can only be released by writing 01b to the psmode[ 1:0] bit of the c0ctrl register and not by a change in the can bus state. user?s manual u17553ej4v0ud 517 chapter 17 interrupt functions 17.1 interrupt function types the following two types of inte rrupt functions are used. (1) maskable interrupts these interrupts undergo mask control. maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority s pecification flag registers (pr0l, pr0h, pr1l, pr1h). multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated. if two or more interrupt requests, each having the same prio rity, are simultaneously generat ed, then they are processed according to the priority of vectored interrupt servicing. for the priority order, see table 17-1 . a standby release signal is generated a nd stop and halt modes are released. 8 external interrupt requests and 29 internal interrupt requests are provided as maskable interrupts. (2) software interrupt this is a vectored interrupt generated by executing the brk instruction. it is acknowledged even when interrupts are disabled. the software interrupt does not undergo interrupt priority control. 17.2 interrupt sources and configuration a total of 38 interrupt sources exist for maskable and software interrupts. in addition, they also have up to four reset sources (see table 17-1 ). chapter 17 interrupt functions user?s manual u17553ej4v0ud 518 table 17-1. interrupt source list (1/2) interrupt source interrupt type default priority note 1 name trigger internal/ external vector table address basic configuration type note 2 0 intlvi low-voltage detection note 3 internal 0004h (a) 1 intp0 0006h 2 intp1 pin input edge detection 0008h intp2 pin input edge detection 3 inttm002 match between tm02 and cr002 (when compare register is specified), ti012 pin valid edge detection (when capture register is specified) 000ah intp3 pin input edge detection 4 inttm012 match between tm02 and cr012 (when compare register is specified), ti002 pin valid edge detection (when capture register is specified) 000ch intp4 pin input edge detection 5 inttm003 match between tm03 and cr003 (when compare register is specified), ti013 pin valid edge detection (when capture register is specified) 000eh intp5 pin input edge detection 6 inttm013 match between tm03 and cr013 (when compare register is specified), ti003 pin valid edge detection (when capture register is specified) external 0010h (b) 7 intc0err afcan0 error occurrence 0012h 8 intc0wup afcan0 wakeup 0014h 9 intc0rec afcan0 reception completion 0016h 10 intc0trx afcan0 transmission completion 0018h 11 intsre60 uart60 reception error generation 001ah 12 intsr60 end of uart60 reception 001ch 13 intst60 end of uart60 transmission 001eh intcsi10 end of csi10 transmission 14 intsre61 uart61 reception error generation internal 0020h (a) intp6 pin input edge detection external (b) 15 intsr61 end of uart61 reception internal 0022h (a) intp7 pin input edge detection external (b) maskable 16 intst61 end of uart61 transmission internal 0024h (a) notes 1. the default priority is the priority applicable when two or more maskable interrupt are generated simultaneously. 0 is the highest priority, and 28 is the lowest. 2. basic configuration types (a) to (c) co rrespond to (a) to (c) in figure 17-1. 3. when bit 1 (lvimd) of the low-voltage detection register (lvim) is set to 0. chapter 17 interrupt functions user?s manual u17553ej4v0ud 519 table 17-1. interrupt source list (2/2) interrupt source interrupt type default priority note 1 name trigger internal/ external vector table address basic configuration type note 2 17 inttmh1 match between tmh1 and cmp01 (when compare register is specified) 0026h 18 inttmh0 match between tmh0 and cmp00 (when compare register is specified) 0028h 19 inttm50 match between tm50 and cr50 (when compare register is specified) 002ah 20 inttm000 match between tm00 and cr000 (when compare register is specified), ti010 pin valid edge detection (when capture register is specified) 002ch 21 inttm010 match between tm00 and cr010 (when compare register is specified), ti000 pin valid edge detection (when capture register is specified) 002eh 22 intad end of a/d conversion 0030h 23 intwti watch timer referenc e time interval signal 0032h intdmu dmu operation end 24 inttm51 note 3 match between tm51 and cr51 (when compare register is specified) 0034h 25 intwt watch timer overflow 0036h 26 intcsi11 end of csi11 communication 0038h 27 inttm001 match between tm01 and cr001 (when compare register is specified), ti011 pin valid edge detection (when capture register is specified) 003ah maskable 28 inttm011 match between tm01 and cr011 (when compare register is specified), ti001 pin valid edge detection (when capture register is specified) internal 003ch (a) software ? brk brk instruction execution ? 003eh (c) reset reset input poc power-on clear lvi low-voltage detection note 4 reset ? wdt wdt overflow ? 0000h ? notes 1. the default priority is the priority applicable when two or more maskable interrupt are generated simultaneously. 0 is the highest priority, and 28 is the lowest. 2. basic configuration types (a) to (c) co rrespond to (a) to (c) in figure 17-1. 3. when the 8-bit timer/event counter 51 is used in t he carrier generator mode, the interrupt source is inttm5h1 (see figure 9-13 transfer timing). 4. when bit 1 (lvimd) of the low-voltage detection register (lvim) is set to 1. chapter 17 interrupt functions user?s manual u17553ej4v0ud 520 figure 17-1. basic configuration of interrupt function (a) internal maskable interrupt internal bus interrupt request if mk ie pr isp priority controller vector table address generator standby release signal (b) external maskable inte rrupt (intp0 to intp7) internal bus interrupt request if mk ie pr isp priority controller vector table address generator standby release signal external interrupt edge enable register (egp, egn) edge detector (c) software interrupt internal bus interrupt request priority controller vector table address generator if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag chapter 17 interrupt functions user?s manual u17553ej4v0ud 521 17.3 registers controlling interrupt functions the following 6 types of registers are used to control the interrupt functions. ? interrupt request flag regist er (if0l, if0h, if1l, if1h) ? interrupt mask flag register (mk0l, mk0h, mk1l, mk1h) ? priority specification flag register (pr0l, pr0h, pr1l, pr1h) ? external interrupt rising edge enable register (egp) ? external interrupt falling edge enable register (egn) ? program status word (psw) table 17-2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources. chapter 17 interrupt functions user?s manual u17553ej4v0ud 522 table 17-2. flags corresponding to interrupt request sources interrupt request flag interrupt mask flag priority specification flag interrupt request register register register intlvi lviif if0l lvimk mk0l lvipr pr0l intp0 pif0 pmk0 ppr0 intp1 pif1 pmk1 ppr1 intp2 pif2 pmk2 ppr2 inttm002 tmif002 dualif3 note 1 tmmk002 dualmk3 note 2 tmpr002 dualpr3 note 2 intp3 pif3 pmk3 ppr3 inttm012 tmif012 dualif4 note 1 tmmk012 dualmk4 note 2 tmpr012 dualpr4 note 2 intp4 pif4 pmk4 ppr4 inttm003 tmif003 dualif5 note 1 tmmk003 dualmk5 note 2 tmpr003 dualpr5 note 2 intp5 pif5 pmk5 ppr5 inttm013 tmif013 dualif6 note 1 tmmk013 dualmk6 note 2 tmpr013 dualpr6 note 2 intc0err c0errif c0errmk c0errpr intc0wup c0wupif if0h c0wupmk mk0h c0wuppr pr0h intc0rec c0recif c0recmk c0recpr intc0trx c0trxif c0trxmk c0trxpr intsre60 sreif60 sremk60 srepr60 intsr60 srif60 srmk60 srpr60 intst60 stif60 stmk60 stpr60 intcsi10 csiif10 csimk10 csipr10 intsre61 sreif61 dualif0 note 1 sremk61 dualmk0 note 2 srepr61 dualpr0 note 2 intp6 pif6 pmk6 ppr6 intsr61 srif61 dualif1 note 1 srmk61 dualmk1 note 2 srpr61 dualpr1 note 2 intp7 pif7 if1l pmk7 mk1l ppr7 pr1l intst61 stif61 dualif2 note 1 stmk61 dualmk2 note 2 stpr61 dualpr2 note 2 inttmh1 tmifh1 tmmkh1 tmprh1 inttmh0 tmifh0 tmmkh0 tmprh0 inttm50 tmif50 tmmk50 tmpr50 inttm000 tmif000 tmmk000 tmpr000 inttm010 tmif010 tmmk010 tmpr010 intad adif admk adpr intwti wtiif wtimk wtipr intdmu dmuif dualif7 note 1 dmumk dualmk7 note 2 dmupr dualpr7 note 2 inttm51 note 3 tmif51 if1h tmmk51 mk1h tmpr51 pr1h intwt wtif wtmk wtpr intcsi11 csiif11 csimk11 csipr11 inttm001 tmif001 tmmk001 tmpr001 inttm011 tmif011 tmmk011 tmpr011 notes 1. if either of the two types of interrupt s ources is generated, these flags are set (1). 2. both types of interrupt sources are supported. 3. when the 8-bit timer/event counter 51 is used in the carrier generator mode, the interrupt source is inttm5h1 (see figure 9-13 transfer timing). chapter 17 interrupt functions user?s manual u17553ej4v0ud 523 (1) interrupt request flag regist ers (if0l, if0h, if1l, if1h) the interrupt request flags are set to 1 when the correspo nding interrupt request is g enerated or an instruction is executed. they are cleared to 0 when an instruction is executed upon acknow ledgment of an interrupt request or upon reset signal generation. when an interrupt is acknowledged, the interrupt req uest flag is automatically cleared and then the interrupt routine is entered. if0l, if0h, if1l, and if1h are set by a 1-bit or 8-bit memory manipulation instruct ion. when if0l and if0h, and if1l and if1h are combined to form 16-bit registers if0 and if1, they are read with a 16-bit memory manipulation instruction. reset signal generation clears these registers to 00h. figure 17-2. format of interrupt request flag registers (if0l, if0h, if1l, if1h) address: ffe0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0l c0errif dualif6 pif5 tmif013 dualif5 pif4 tmif003 dualif4 pif3 tmif012 dualif3 pif2 tmif002 pif1 pif0 lviif address: ffe1h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0h dualif1 pif6 srif61 durlif0 csiif10 sreif61 stif60 srif60 sreif60 c0trxif c0recif c0wupif address: ffe2h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if1l dualif7 wtiif dmuif adif tmif010 tmif000 tmif50 tmifh0 tmifh1 dualif2 pif7 stif61 address: ffe3h after reset: 00h r/w symbol 7 6 5 <4> <3> <2> <1> <0> if1h 0 0 0 tmif011 tmif 001 csiif11 wtif tmif51 xxifx interrupt request flag 0 no interrupt request signal is generated 1 interrupt request is generated, interrupt request status cautions 1. be sure to set bits 5 to 7 of if1h to 0. 2. when operating a timer, seri al interface, or a/d converter a fter standby release, operate it once after clearing the interrupt request flag. an interrupt request flag may be set by noise. chapter 17 interrupt functions user?s manual u17553ej4v0ud 524 cautions 3. when manipulating a flag of the inte rrupt request flag regist er, use a 1-bit memory manipulation instruction (clr1). when descr ibing in c language, u se a bit manipulation instruction such as ?if0l.0 = 0;? or ?_asm(?c lr1 if0l, 0?);? because the compiled assembler must be a 1-bit memory manipulation instruction (clr1). if a program is described in c language using an 8-bit memory manipulation instruction such as ?if0l &= 0xfe;? and compiled, it b ecomes the assembler of three instructions. mov a, if0l and a, #0feh mov if0l, a in this case, even if th e request flag of anothe r bit of the same interrupt request flag register (if0l) is set to 1 at the timi ng between ?mov a, if0l? and ?mov if0l, a?, the flag is cleared to 0 at ?mov if0l, a?. therefore, care mu st be exercised when using an 8-bit memory manipulation instruction in c language. chapter 17 interrupt functions user?s manual u17553ej4v0ud 525 (2) interrupt mask flag regist ers (mk0l, mk0h, mk1l, mk1h) the interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. mk0l, mk0h, mk1l, and mk1h are set by a 1-bit or 8- bit memory manipulation instruction. when mk0l and mk0h, and mk1l and mk1h are combined to form 16-bit registers mk0 and mk1, they are set with a 16-bit memory manipulation instruction. reset signal generation sets these registers to ffh. figure 17-3. format of interrupt mask fl ag registers (mk0l, mk0h, mk1l, mk1h) address: ffe4h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0l c0errmk dualmk6 pmk5 tmmk013 dualmk5 pmk4 tmmk003 dualmk4 pmk3 tmmk012 dualmk3 pmk2 tmmk002 pmk1 pmk0 lvimk address: ffe5h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0h dualmk1 pmk6 srmk61 durlmk0 csimk10 sremk61 stmk60 srmk60 sremk60 c0trxmk c0recmk c0wupmk address: ffe6h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk1l dualmk7 wtimk dmumk admk tmmk010 tmmk000 tmmk50 tmmkh0 tmmkh1 dualmk2 pmk7 stmk61 address: ffe7h after reset: ffh r/w symbol 7 6 5 <4> <3> <2> <1> <0> mk1h 1 1 1 tmmk011 tmmk 001 csimk11 wtmk tmmk51 xxmkx interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled caution be sure to set bits 5 to 7 of mk1h to 1. chapter 17 interrupt functions user?s manual u17553ej4v0ud 526 (3) priority specification flag re gisters (pr0l, pr0h, pr1l, pr1h) the priority specification flag regist ers are used to set the corresponding maskable interrupt priority order. pr0l, pr0h, pr1l, and pr1h are set by a 1-bit or 8-bi t memory manipulation instruction. if pr0l and pr0h, and pr1l and pr1h are combined to form 16-bit registers pr0 and pr1, they are set with a 16-bit memory manipulation instruction. reset signal generation sets these registers to ffh. figure 17-4. format of priority specificati on flag registers (pr0l, pr0h, pr1l, pr1h) address: ffe8h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr0l c0errpr dualpr6 ppr5 tmpr073 dualpr5 ppr4 tmpr003 dualpr4 ppr3 tmpr012 dualpr3 ppr2 tmpr002 ppr1 ppr0 lvipr address: ffe9h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr0h dualpr1 ppr6 srpr61 durlpr0 csipr10 srepr61 stpr60 srpr60 srepr60 c0trxpr c0recpr c0wuppr address: ffeah after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr1l dualpr7 wtipr dmupr adpr tmpr010 tmpr000 tmpr50 tmprh0 tmprh1 dualpr2 ppr7 stpr61 address: ffebh after reset: ffh r/w symbol 7 6 5 <4> <3> <2> <1> <0> pr1h 1 1 1 tmpr011 tmpr 001 csipr11 wtpr tmpr51 xxprx priority level selection 0 high priority level 1 low priority level caution be sure to set bi t 5 to 7 of pr1h to 1. chapter 17 interrupt functions user?s manual u17553ej4v0ud 527 (4) external interrupt rising edge en able register (egp), external interrupt falling edge enable register (egn) these registers specify the valid edge for intp0 to intp7. egp and egn are set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. figure 17-5. format of external interrupt rising edge enable register (egp) and external interrupt falling edge enable register (egn) address: ff48h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egp egp7 epg6 egp5 egp4 egp3 egp2 egp1 egp0 address: ff49h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egn egn7 egn6 egn5 egn4 egn3 egn2 egn1 egn0 egpn egnn intpn pin valid edge selection (n = 0 to 7) 0 0 edge detection disabled 0 1 falling edge 1 0 rising edge 1 1 both rising and falling edges table 17-3 shows the ports corresponding to egpn and egnn. table 17-3. ports correspo nding to egpn and egnn detection enable register edge dete ction port external request signal egp0 egn0 p120 intp0 egp1 egn1 p30 intp1 egp2 egn2 p31 intp2 egp3 egn3 p32 intp3 egp4 egn4 p33 intp4 egp5 egn5 p16 intp5 egp6 egn6 p72 intp6 egp7 egn7 p73 intp7 caution select the port mode by cleari ng egpn and egnn to 0 because an edge may be detected when the external inte rrupt function is switched to the port function. remark n = 0 to 7 chapter 17 interrupt functions user?s manual u17553ej4v0ud 528 (5) program status word (psw) the program status word is a register used to hold the instruction exec ution result and the current status for an interrupt request. the ie flag that sets maskable interr upt enable/disable and the isp fl ag that controls multiple interrupt servicing are mapped to the psw. besides 8-bit read/write, this register can carry out op erations using bit manipulation instructions and dedicated instructions (ei and di). when a vect ored interrupt request is acknowledged, if the brk instruction is executed, the contents of the psw are aut omatically saved into a stack and the ie flag is reset to 0. if a maskable interrupt request is acknowledged, the contents of the priority specification flag of t he acknowledged interrupt are transferred to the isp flag. the psw contents are also saved into the stack with t he push psw instruction. they are restored from the stack with t he reti, retb, and pop psw instructions. reset signal generation sets psw to 02h. figure 17-6. format of program status word <7> ie <6> z <5> rbs1 <4> ac <3> rbs0 2 0 <1> isp 0 cy psw after reset 02h isp high-priority interrupt servicing (low-priority interrupt disabled) ie 0 1 disabled priority of interrupt currently being serviced interrupt request acknowledgment enable/disable used when normal instruction is executed enabled interrupt request not acknowledged, or low- priority interrupt servicing (all maskable interrupts enabled) 0 1 chapter 17 interrupt functions user?s manual u17553ej4v0ud 529 17.4 interrupt servicing operations 17.4.1 maskable interrupt acknowledgement a maskable interrupt becomes acknowledgeable when the in terrupt request flag is set to 1 and the mask (mk) flag corresponding to that interrupt request is cleared to 0. a vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the ie flag is set to 1). however, a low-priority interrupt request is not acknowledged during servicing of a higher priority interrupt request (when the isp flag is reset to 0). the times from generation of a maskable interrupt reques t until interrupt servicing is perfor med are listed in table 17-4 below. for the interrupt request acknowledgement timing, see figures 17-8 and 17-9 . table 17-4. time from generation of maskable inte rrupt until servicing minimum time maximum time note when pr = 0 7 clocks 32 clocks when pr = 1 8 clocks 33 clocks note if an interrupt request is generated just before a di vide instruction, the wait time becomes longer. remark 1 clock: 1/f cpu (f cpu : cpu clock) if two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level specified in the priority specification flag is acknowledge d first. if two or more interrupts requests have the same priority level, the request with the highest default priority is acknowledged first. an interrupt request that is held pending is a cknowledged when it becomes acknowledgeable. figure 17-7 shows the interrupt request acknowledgement algorithm. if a maskable interrupt request is acknowledged, the content s are saved into the stacks in the order of psw, then pc, the ie flag is reset (0), and the contents of the pr iority specification flag corresponding to the acknowledged interrupt are transferred to the isp flag. the vector table data deter mined for each interrupt request is the loaded into the pc and branched. restoring from an interrupt is possible by using the reti instruction. chapter 17 interrupt functions user?s manual u17553ej4v0ud 530 figure 17-7. interrupt request ac knowledgement pr ocessing algorithm start if = 1? mk = 0? pr = 0? ie = 1? isp = 1? interrupt request held pending yes yes no no yes (interrupt request generation) yes no (low priority) no no yes yes no ie = 1? no any high-priority interrupt request among those simultaneously generated with pr = 0? yes (high priority) no yes yes no vectored interrupt servicing interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending vectored interrupt servicing any high-priority interrupt request among those simultaneously generated? any high-priority interrupt request among those simultaneously generated with pr = 0? if: interrupt request flag mk: interrupt mask flag pr: priority specification flag ie: flag that controls acknowledgement of mask able interrupt request (1 = enable, 0 = disable) isp: flag that indicates the priority level of the interrupt currently being serviced (0 = high-priority interrupt servicing, 1 = no interrupt request acknowledg ed, or low-priority interrupt servicing) chapter 17 interrupt functions user?s manual u17553ej4v0ud 531 figure 17-8. interrupt request ac knowledgement timing (minimum time) 8 clocks 7 clocks instruction instruction psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing if ( pr = 1) if ( pr = 0) 6 clocks remark 1 clock: 1/f cpu (f cpu : cpu clock) figure 17-9. interrupt request ac knowledgement timing (maximum time) 33 clocks 32 clocks instruction divide instruction psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing if ( pr = 1) if ( pr = 0) 6 clocks 25 clocks remark 1 clock: 1/f cpu (f cpu : cpu clock) 17.4.2 software interrupt request acknowledgement a software interrupt acknowledge is acknowledged by brk instruction execution. so ftware interrupts cannot be disabled. if a software interrupt request is ackno wledged, the cont ents are saved into the stacks in the order of the program status word (psw), then program counter (pc), the ie flag is reset (0), and t he contents of the ve ctor table (003eh, 003fh) are loaded into the pc and branched. restoring from a software interrupt is possi ble by using the retb instruction. caution do not use the reti instruction fo r restoring from the software interrupt. chapter 17 interrupt functions user?s manual u17553ej4v0ud 532 17.4.3 multiple interrupt servicing multiple interrupt servicing occurs when another interrupt re quest is acknowledged during execution of an interrupt. multiple interrupt servicing does not occur unless the in terrupt request acknowledgem ent enabled state is selected (ie = 1). when an interrupt request is acknowledged, interrupt request acknow ledgement becomes disabled (ie = 0). therefore, to enable multiple interrupt servicing, it is necessary to set (1) the ie flag with the ei instruction during interrupt servicing to enable interrupt acknowledgement. moreover, even if interrupts are enabled, multiple interr upt servicing may not be enabled, this being subject to interrupt priority control. two types of priority control are available: default priority control and programmable priority control. programmable priority control is used for multiple interrupt servicing. in the interrupt enabled state, if an in terrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for mu ltiple interrupt servicing. if an interrupt with a priority lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrupt servicing. inte rrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have a lower prio rity are held pending. when servicing of the current interrupt ends, the pending interrupt request is acknowledged following execution of at least one main processing instruction execution. table 17-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and figure 17-10 shows multiple interrupt servicing examples. table 17-5. relationship between interrupt requests enabled for multiple interrupt servicing during interrupt servicing maskable interrupt request pr = 0 pr = 1 multiple interrupt request interrupt being serviced ie = 1 ie = 0 ie = 1 ie = 0 software interrupt request isp = 0 { { maskable interrupt isp = 1 { { { software interrupt { { { remarks 1. : multiple interrupt servicing enabled 2. : multiple interrupt servicing disabled 3. isp and ie are flags contained in the psw. isp = 0: an interrupt with higher priority is being serviced. isp = 1: no interrupt request has been acknowledged, or an interrupt with a lower priority is being serviced. ie = 0: interrupt request acknowledgement is disabled. ie = 1: interrupt request acknowledgement is enabled. 4. pr is a flag contained in pr0l, pr0h, pr1l, and pr1h. pr = 0: higher priority level pr = 1: lower priority level chapter 17 interrupt functions user?s manual u17553ej4v0ud 533 figure 17-10. examples of multip le interrupt se rvicing (1/2) example 1. multiple inte rrupt servicing occurs twice main processing intxx servicing intyy servicing intzz servicing ei ei ei reti reti reti intxx (pr = 1) intyy (pr = 0) intzz (pr = 0) ie = 0 ie = 0 ie = 0 ie = 1 ie = 1 ie = 1 during servicing of interrupt intxx, two interrupt re quests, intyy and intzz, are acknowledged, and multiple interrupt servicing takes place. before each interrupt re quest is acknowledged, the ei instruction must always be issued to enable interrupt request acknowledgment. example 2. multiple interrupt servicing does not occur due to priority control main processing intxx servicing intyy servicing intxx (pr = 0) intyy (pr = 1) ei reti ie = 0 ie = 0 ei 1 instruction execution reti ie = 1 ie = 1 interrupt request intyy issued during servicing of interrupt intxx is not acknowledged because its priority is lower than that of intxx, and mu ltiple interrupt servicing does not take place. the intyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. pr = 0: higher priority level pr = 1: lower priority level ie = 0: interrupt request acknowledgment disabled chapter 17 interrupt functions user?s manual u17553ej4v0ud 534 figure 17-10. examples of multip le interrupt se rvicing (2/2) example 3. multiple interrupt servicing do es not occur because inte rrupts are not enabled main processing intxx servicing intyy servicing ei 1 instruction execution reti reti intxx (pr = 0) intyy (pr = 0) ie = 0 ie = 0 ie = 1 ie = 1 interrupts are not enabled during servicing of interrupt int xx (ei instruction is not issued), therefore, interrupt request intyy is not acknowledged and multiple interrupt serv icing does not take place. the intyy interrupt request is held pending, and is acknowledged following ex ecution of one main processing instruction. pr = 0: higher priority level ie = 0: interrupt request acknowledgement disabled chapter 17 interrupt functions user?s manual u17553ej4v0ud 535 17.4.4 interrupt request hold there are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgement is held pending until t he end of execution of the next instruction. these instructions (interrupt request hol d instructions) are listed below. ? mov psw, #byte ? mov a, psw ? mov psw, a ? mov1 psw. bit, cy ? mov1 cy, psw. bit ? and1 cy, psw. bit ? or1 cy, psw. bit ? xor1 cy, psw. bit ? set1 psw. bit ? clr1 psw. bit ? retb ? reti ? push psw ? pop psw ? bt psw. bit, $addr16 ? bf psw. bit, $addr16 ? btclr psw. bit, $addr16 ? ei ? di ? manipulation instructions for the if0l, if0h, if1l, if1h, mk0l, mk0h, mk1l, mk1h, pr0l, pr0h, pr1l, and pr1h registers. caution the brk instruction is not one of the a bove-listed interrupt request hold instructions. however, the software interrupt activated by executing the brk in struction causes the ie flag to be cleared. therefore, even if a maskable in terrupt request is gene rated during execution of the brk instruction, the interrupt request is not acknowledged. figure 17-11 shows the timing at which interrupt requests are held pending. figure 17-11. interrupt request hold instruction n instruction m psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing if remarks 1. instruction n: interrupt request hold instruction 2. instruction m: instruction other t han interrupt request hold instruction 3. the pr (priority level) values do not affect the operation of if (instruction request). user?s manual u17553ej4v0ud 536 chapter 18 standby function 18.1 standby function and configuration 18.1.1 standby function the standby function is designed to reduce the operating current of the system. the following two modes are available. (1) halt mode halt instruction execution se ts the halt mode. in the halt mode, the cpu operation clock is stopped. if the high-speed system clock oscillator, in ternal high-speed oscillator, internal low-speed oscillator, or subsystem clock oscillator is operating before the halt mode is set, oscillation of each clock continues. in this mode, the operating current is not decreased as much as in the st op mode, but the halt mode is effective for restarting operation immediately upon interrupt request gener ation and carrying out intermittent operations. (2) stop mode stop instruction execution sets the stop mode. in the stop mode, the high-speed system clock oscillator and internal high-speed oscillator stop, stopping the whole system, thereby considerably reducing the cpu operating current. because this mode can be cleared by an interrupt reques t, it enables intermittent operations to be carried out. however, because a wait time is required to secure th e oscillation stabilization time after the stop mode is released, select the halt mode if it is necessary to start processing immediately upon interrupt request generation. in either of these two modes, all the contents of registers, flags and data me mory just before the standby mode is set are held. the i/o port output latches an d output buffer statuses are also held. cautions 1. the stop mode can be used only when the cpu is operating on the main system clock. the subsystem clock oscillati on cannot be stopped. the halt mode can be used when the cpu is operating on either the main syst em clock or the subsystem clock. 2. when shifting to the stop mode, be sure to stop the peripheral hardware operation operating with main system clock be fore executing stop instruction. 3. the following sequence is recommende d for operating current reduction of the a/d converter when the standby function is used: first clear bit 7 (adcs) and bit 0 (adce) of the a/d converter mode register (adm) to 0 to stop the a/d conversion operation, and then execute the stop instruction. 18.1.2 registers controlling standby function the standby function is controlled by the following two registers. ? oscillation stabilization time c ounter status register (ostc) ? oscillation stabilization time select register (osts) remark for the registers that start, st op, or select the clock, see chapter 6 clock generator . chapter 18 standby function user?s manual u17553ej4v0ud 537 (1) oscillation stabilization time c ounter status register (ostc) this is the register that indicates t he count status of the x1 clock oscill ation stabilization time counter. when x1 clock oscillation starts with the intern al high-speed oscillation clock or su bsystem clock used as the cpu clock, the x1 clock oscillation stabilization time can be checked. ostc can be read by a 1-bit or 8-bit memory manipulation instruction. when reset is released (reset by reset input, poc, lvi and wdt), the stop instruct ion and mstop (bit 7 of moc register) = 1 clear ostc to 00h. figure 18-1. format of oscillation stabilizati on time counter status register (ostc) address: ffa3h after reset: 00h r symbol 7 6 5 4 3 2 1 0 ostc 0 0 0 most11 most 13 most14 most15 most16 oscillation stabilization time status most 11 most 13 most 14 most 15 most 16 f x = 4 mhz f x = 5 mhz f x = 10 mhz f x = 20 mhz 1 0 0 0 0 2 11 /f x min. 512 s min. 409.6 s min. 204.8 s min. 102.4 s min. 1 1 0 0 0 2 13 /f x min. 2.05 ms min. 1.64 ms min. 819.2 s min. 409.6 s min. 1 1 1 0 0 2 14 /f x min. 4.10 ms min. 3.27 ms min. 1.64 ms min. 819.2 s min. 1 1 1 1 0 2 15 /f x min. 8.19 ms min. 6.55 ms min. 3.27 ms min. 1.64 ms min. 1 1 1 1 1 2 16 /f x min. 16.38 ms min. 13.11 ms min. 6.55 ms min. 3.27 ms min. cautions 1. after the above time has elapsed, the bits are set to 1 in order from most11 and remain 1. 2. the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. if the stop m ode is entered and then re leased while th e internal high-speed oscillation clock is being u sed as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc after st op mode is released. 3. the x1 clock oscillation stabilization time does not include the time until clock oscillation starts (?a? below). a stop mode release x1 pin voltage waveform remark f x : x1 clock oscillation frequency chapter 18 standby function user?s manual u17553ej4v0ud 538 (2) oscillation stabilization time select register (osts) this register is used to select the x1 clock oscillati on stabilization time when the st op mode is released. when the x1 clock is selected as the cpu clock, the operati on waits for the time set usin g osts after the stop mode is released. when the internal high-speed oscillation clock is selected as the cpu clock, confirm with ostc that the desired oscillation stabilization time has elaps ed after the stop mode is released. t he oscillation stabilization time can be checked up to the time set using ostc. osts can be set by an 8-bit memory manipulation instruction. reset signal generation sets osts to 05h. figure 18-2. format of oscillation stabiliz ation time select register (osts) address: ffa4h after reset: 05h r/w symbol 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 osts2 osts1 osts0 osts2 osts1 osts0 oscillation stabilization time selection f x = 4 mhz f x = 5 mhz f x = 10 mhz f x = 20 mhz 0 0 1 2 11 /f x 512 s 409.6 s 204.8 s 102.4 s 0 1 0 2 13 /f x 2.05 ms 1.64 ms 819.2 s 409.6 s 0 1 1 2 14 /f x 4.10 ms 3.27 ms 1.64 ms 819.2 s 1 0 0 2 15 /f x 8.19 ms 6.55 ms 3.27 ms 1.64 ms 1 0 1 2 16 /f x 16.38 ms 13.11 ms 6.55 ms 3.27 ms other than above setting prohibited cautions 1. to set the stop mode when the x1 cl ock is used as the cpu cl ock, set osts before executing the stop instruction. 2. do not change the value of the osts register during the x1 clock oscillation stabilization time. 3. the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. if the stop mode is ente red and then released while the internal high-speed oscillation clock is being u sed as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc after st op mode is released. 4. the x1 clock oscillation stabilization time does not include the time until clock oscillation starts (?a? below). a stop mode release x1 pin voltage waveform remark f x : x1 clock oscillation frequency chapter 18 standby function user?s manual u17553ej4v0ud 539 18.2 standby function operation 18.2.1 halt mode (1) halt mode the halt mode is set by executing t he halt instruction. halt mode can be set regardless of whether the cpu clock before the setting was the high-speed system clock, internal high-speed oscill ation clock, or subsystem clock. the operating statuses in t he halt mode are shown below. chapter 18 standby function user?s manual u17553ej4v0ud 540 table 18-1. operating statuses in halt mode (1/2) when halt instruction is executed while cpu is operating on main system clock halt mode setting item when cpu is operating on internal high-speed oscillation clock (f rh ) when cpu is operating on x1 clock (f x ) when cpu is operating on external main system clock (f exclk ) system clock clock supply to the cpu is stopped f rh operation continues (cannot be stopped) status before halt mode was set is retained f x status before halt mode was set is retained operation continues (cannot be stopped) status before halt mode was set is retained main system clock f exclk operates or stops by external cl ock input operation continues (cannot be stopped) f xt status before halt mode was set is retained subsystem clock f exclks operates or stops by external clock input f rl status before halt mode was set is retained cpu operation stopped flash memory operation stopped ram status before halt mode was set is retained port (latch) status before halt mode was set is retained 00 01 02 16-bit timer/event counter 03 50 8-bit timer/event counter 51 h0 8-bit timer h1 watch timer operable watchdog timer operable. clock supply to watchdog ti mer stops when ?internal low-speed oscillator can be stopped by software? is set by option byte. clock output buzzer output a/d converter uart60 uart61 csi10 serial interface csi11 can controller multiplier/divider power-on-clear function low-voltage detection function external interrupt operable remark f rh : internal high-speed oscillation clock f x : x1 clock f exclk : external main system clock f xt : xt1 clock f exclks : external subsystem clock f rl : internal low-speed oscillation clock chapter 18 standby function user?s manual u17553ej4v0ud 541 table 18-1. operating statuses in halt mode (2/2) when halt instruction is executed while cpu is operating on subsystem clock halt mode setting item when cpu is operating on xt1 clock (f xt ) when cpu is operating on external subsystem clock (f exclks ) system clock clock supply to the cpu is stopped f rh f x status before halt mode was set is retained main system clock f exclk operates or stops by external clock input f xt operation continues (cannot be stopped) stat us before halt mode was set is retained subsystem clock f exclks operates or stops by external clock input operation continues (cannot be stopped) f rl status before halt mode was set is retained cpu operation stopped flash memory operation stopped ram status before halt mode was set is retained port (latch) status before halt mode was set is retained 00 note 01 note 02 note 16-bit timer/event counter 03 note 50 note 8-bit timer/event counter 51 note h0 8-bit timer h1 watch timer operable watchdog timer operable. clock supply to watchdog timer st ops when ?internal low-speed oscillator can be stopped by software? is set by option byte. clock output operable buzzer output operable. however, operat ion disabled when peripheral hardware clock (f prs ) is stopped. a/d converter uart60 uart61 csi10 note serial interface csi11 note can controller multiplier/divider power-on-clear function low-voltage detection function external interrupt operable note when the cpu is operating on the s ubsystem clock and the internal high-speed oscillation clock has been stopped, do not start operation of thes e functions on the external clock input from peripheral hardware pins. (remark is listed on the next page.) chapter 18 standby function user?s manual u17553ej4v0ud 542 remark f rh : internal high-speed oscillation clock f x : x1 clock f exclk : external main system clock f xt : xt1 clock f exclks : external subsystem clock f rl : internal low-speed oscillation clock chapter 18 standby function user?s manual u17553ej4v0ud 543 (2) halt mode release the halt mode can be released by the following two sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the halt mode is released. if interrupt acknowledgement is enabled, vectored interrupt servicing is carried out. if interrupt acknowledgement is disabled, the next address instruction is executed. figure 18-3. halt mode release by interrupt request generation halt instruction wait operating mode halt mode operating mode oscillation high-speed system clock, internal high-speed oscillation clock, or subsystem clock status of cpu standby release signal interrupt request note note the wait time is as follows: ? when vectored interrupt servicing is carried out: 8 or 9 clocks ? when vectored interrupt servicing is not carried out: 2 or 3 clocks remark the broken lines indicate the case when the interrupt request which has released the standby mode is acknowledged. chapter 18 standby function user?s manual u17553ej4v0ud 544 (b) release by reset signal generation when the reset signal is generated, halt mode is re leased, and then, as in the case with a normal reset operation, the program is executed after br anching to the reset vector address. figure 18-4. halt mode release by reset (1) when high-speed system clock is used as cpu clock halt instruction reset signal high-speed system clock (x1 oscillation) halt mode reset period oscillates oscillation stopped oscillates status of cpu normal operation (high-speed system clock) oscillation stabilization time (2 11 /f x to 2 16 /f x ) normal operation (internal high-speed oscillation clock) oscillation stopped starting x1 oscillation is specified by software. reset processing (11 to 45 s) (2) when internal high-speed osc illation clock is used as cpu clock halt instruction reset signal internal high-speed oscillation clock normal operation (internal high-speed oscillation clock) halt mode reset period normal operation (internal high-speed oscillation clock) oscillates oscillation stopped oscillates status of cpu wait for oscillation accuracy stabilization (86 to 361 s) reset processing (11 to 45 s) (3) when subsystem clo ck is used as cpu clock halt instruction reset signal subsystem clock (xt1 oscillation) normal operation (subsystem clock) halt mode reset period normal operation mode (internal high-speed oscillation clock) oscillates oscillation stopped oscillates status of cpu oscillation stopped starting xt1 oscillation is specified by software. reset processing (11 to 45 s) remark f x : x1 clock oscillation frequency chapter 18 standby function user?s manual u17553ej4v0ud 545 table 18-2. operation in response to interrupt request in halt mode release source mk pr ie isp operation 0 0 0 next address instruction execution 0 0 1 interrupt servicing execution 0 1 0 1 0 1 0 next address instruction execution 0 1 1 1 interrupt servicing execution maskable interrupt request 1 halt mode held reset signal input ? ? reset processing : don?t care 18.2.2 stop mode (1) stop mode setting and operating statuses the stop mode is set by executing t he stop instruction, and it can be se t only when the cpu clock before the setting was the main system clock. caution because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and th e interrupt mask flag reset, the standby mode is immediately cleared if set. thus, the stop mode is reset to the halt mode immediately after execution of the stop instruction and th e system returns to the operating mode as soon as the wait time set using the oscillation stabiliz ation time select regist er (osts) has elapsed. the operating statuses in t he stop mode are shown below. chapter 18 standby function user?s manual u17553ej4v0ud 546 table 18-3. operating statuses in stop mode when stop instruction is executed while cpu is operating on main system clock stop mode setting item when cpu is operating on internal high-speed oscillation clock (f rh ) when cpu is operating on x1 clock (f x ) when cpu is operating on external main system clock (f exclk ) system clock clock supply to the cpu is stopped f rh f x stopped main system clock f exclk input invalid f xt status before stop mode was set is retained subsystem clock f exclks operates or stops by external clock input f rl status before stop mode was set is retained cpu operation stopped flash memory operation stopped ram status before stop mode was set is retained port (latch) status before stop mode was set is retained 00 note 01 note 02 note 16-bit timer/event counter 03 note operation stopped 50 note operable only when ti50 is se lected as the count clock 8-bit timer/event counter 51 note operable only when ti51 is se lected as the count clock h0 operable only when tm50 output is selected as the count clock during 8- bit timer/event counter 50 operation 8-bit timer h1 operable only when f rl , f rl /2 7 , f rl /2 9 is selected as the count clock watch timer operable only when subsystem clock is selected as the count clock watchdog timer operable. clock supply to watchdog ti mer stops when ?internal low-speed oscillator can be stopped by software? is set by option byte. clock output operable only w hen subsystem clock is selected as the count clock buzzer output operation stopped a/d converter uart60 uart61 operable only when tm50 output is selected as the serial clock during 8-bi t timer/event counter 50 operation csi10 note serial interface csi11 note operable only when external clock is selected as the serial clock can controller operable. can be woken up from sleep mode. multiplier/divider operation stopped power-on-clear function low-voltage detection function external interrupt operable note do not start operation of these func tions on the external clock input from peripheral hardware pins in the stop mode. (remark and cautions are listed on the next page.) chapter 18 standby function user?s manual u17553ej4v0ud 547 remark f rh : internal high-speed oscillation clock f x : x1 clock f exclk : external main system clock f xt : xt1 clock f exclks : external subsystem clock f rl : internal low-speed oscillation clock cautions 1. to use the peripheral ha rdware that stops operation in the stop mode, and the peripheral hardware for which the clock that stops oscillati ng in the stop mode after the stop mode is released, restart the peripheral hardware. 2. even if ?internal low-speed oscillator can be stopped by software? is selected by the option byte, the internal low-speed osc illator continues in the stop mode in the status before the stop mode is set. to stop the internal low-speed oscillator in the stop mode, stop it by software and then execute the stop instruction. 3. to shorten oscillation stabiliz ation time after the stop mode is released when the cpu operates with the high-speed system clock (x1 oscillation) , temporarily switch the cpu clock to the internal high-speed oscillator in ternal oscillation clock before the next execution of the stop instruction. before changing the cpu clock from the internal high-speed oscillator to the high- speed system clock (x1 oscillation) after the stop mode is released, check the oscillation stabilization time with the oscillation stabilizat ion time counter status register (ostc). 4. if the stop instruction is executed when amph = 1, supply of the cpu clock is stopped for 4.06 to 16.12 s after the stop mode is re leased when the internal hi gh-speed oscillation clock is selected as the cpu clock, or for the duration of 160 externa l clocks when th e high-speed system clock (external clock input) is selected as the cpu clock. chapter 18 standby function user?s manual u17553ej4v0ud 548 (2) stop mode release figure 18-5. operation timing wh en stop mode is released (when unmasked interrupt request is generated) stop mode stop mode release high-speed system clock (x1 oscillation) high-speed system clock (external clock input) internal high-speed oscillation clock high-speed system clock (x1 oscillation) is selected as cpu clock when stop instruction is executed high-speed system clock (external clock input) is selected as cpu clock when stop instruction is executed internal high-speed oscillation clock is selected as cpu clock when stop instruction is executed wait for oscillation accuracy stabilization (86 to 361 s) halt status (oscillation stabilization time set by osts) clock switched by software clock switched by software high-speed system clock high-speed system clock wait note2 wait note2 supply of the cpu clock is stopped (4.06 to 16.12 s) note1 high-speed system clock supply of the cpu clock is stopped (160 external clocks) note1 internal high-speed oscillation clock notes 1. when amph = 1 2. the wait time is as follows: ? when vectored interrupt servicing is carried out: 8 or 9 clocks ? when vectored interrupt servicing is not carried out: 2 or 3 clocks the stop mode can be released by the following two sources. chapter 18 standby function user?s manual u17553ej4v0ud 549 (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the stop mode is released. after the oscillation stabilization time has elapsed, if interrupt acknowledg ment is enabled, vectored interrupt servicing is carried out. if interrupt acknowledgment is disabled, the next address instruction is executed. figure 18-6. stop mode release by interrupt request generation (1/2) (1) when high-speed system clock (x 1 oscillation) is used as cpu clock normal operation (high-speed system clock) normal operation (high-speed system clock) oscillates oscillates stop instruction stop mode wait (set by osts) standby release signal oscillation stabilization wait (halt mode status) oscillation stopped high-speed system clock (x1 oscillation) status of cpu oscillation stabilization time (set by osts) interrupt request (2) when high-speed system clock (external clock input) is used as cpu clock (1/2) ? when amph = 1 interrupt request stop instruction standby release signal status of cpu high-speed system clock (external clock input) oscillates normal operation (high-speed system clock) stop mode oscillation stopped oscillates normal operation (high-speed system clock) wait note supply of the cpu clock is stopped (160 external clocks) note the wait time is as follows: ? when vectored interrupt servicing is carried out: 8 or 9 clocks ? when vectored interrupt servicing is not carried out: 2 or 3 clocks remark the broken lines indicate the case when the inte rrupt request that has re leased the standby mode is acknowledged. chapter 18 standby function user?s manual u17553ej4v0ud 550 figure 18-6. stop mode release by interrupt request generation (2/2) (2) when high-speed system clock (external clock input) is used as cpu clock (2/2) ? when amph = 0 interrupt request stop instruction standby release signal status of cpu high-speed system clock (external clock input) normal operation (high-speed system clock) oscillates stop mode oscillation stopped wait note normal operation (high-speed system clock) oscillates (3) when internal high-speed osc illation clock is used as cpu clock ? when amph = 1 (4.06 to 16.12 s) standby release signal status of cpu internal high-speed oscillation clock normal operation (internal high-speed oscillation clock) oscillates stop mode oscillation stopped wait for oscillation accuracy stabilization (86 to 361 s) interrupt request stop instruction wait note normal operation (internal high-speed oscillation clock) supply of the cpu clock is stopped oscillates ? when amph = 0 wait note wait for oscillation accuracy stabilization (86 to 361 s) oscillates normal operation (internal high-speed oscillation clock) stop mode oscillation stopped oscillates normal operation (internal high-speed oscillation clock) internal high-speed oscillation clock status of cpu standby release signal stop instruction interrupt request note the wait time is as follows: ? when vectored interrupt servicing is carried out: 8 or 9 clocks ? when vectored interrupt servicing is not carried out: 2 or 3 clocks remark the broken lines indicate the case when the inte rrupt request that has re leased the standby mode is acknowledged. chapter 18 standby function user?s manual u17553ej4v0ud 551 (b) release by reset signal generation when the reset signal is generated, stop mode is released, and then, as in the case with a normal reset operation, the program is executed after br anching to the reset vector address. figure 18-7. stop mode release by reset (1) when high-speed system clock is used as cpu clock stop instruction reset signal high-speed system clock (x1 oscillation) normal operation (high-speed system clock) stop mode reset period normal operation (internal high-speed oscillation clock) oscillates oscillation stopped oscillates status of cpu oscillation stabilization time (2 11 /f x to 2 16 /f x ) oscillation stopped starting x1 oscillation is specified by software. oscillation stopped reset processing (11 to 45 s) (2) when internal high-speed osc illation clock is used as cpu clock stop instruction reset signal internal high-speed oscillation clock normal operation (internal high-speed oscillation clock) stop mode reset period normal operation (internal high-speed oscillation clock) oscillates oscillation stopped status of cpu oscillates oscillation stopped wait for oscillation accuracy stabilization (86 to 361 s) reset processing (11 to 45 s) remark f x : x1 clock oscillation frequency table 18-4. operation in response to interrupt request in stop mode release source mk pr ie isp operation 0 0 0 next address instruction execution 0 0 1 interrupt servicing execution 0 1 0 1 0 1 0 next address instruction execution 0 1 1 1 interrupt servicing execution maskable interrupt request 1 stop mode held reset signal input ? ? reset processing : don?t care user?s manual u17553ej4v0ud 552 chapter 19 reset function the following four operations are av ailable to generate a reset signal. (1) external reset input via reset pin (2) internal reset by watchdog timer program loop detection (3) internal reset by comparison of supply voltage and detection voltage of power-on-clear (poc) circuit (4) internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (lvi) external and internal resets have no functional differences . in both cases, program ex ecution starts at the address at 0000h and 0001h when the reset signal is generated. a reset is applied when a low level is input to the reset pin, the watchdog timer overflows, or by poc and lvi circuit voltage detection, and each item of hardware is set to the status shown in tables 19-1 and 19-2. each pin is high impedance during reset signal generation or during the osci llation stabilization time just after a reset release, except for p130, which is low-level output. when a low level is input to the reset pin, the device is reset. it is released from the reset status when a high level is input to the reset pin and program execution is started with the internal high- speed oscillation clock after reset processing. a reset by the watchdog timer is autom atically released, and program execution starts using the internal high-speed oscillation clock (see figures 19-2 to 19-4 ) after reset processing. reset by poc and lvi circuit power supply detection is automatically released when v dd v poc or v dd v lvi after the reset, and program execution starts using the internal high-speed oscillation clock (see chapter 21 power-on-clear circuit and chapter 22 low-voltage detector ) after reset processing. cautions 1. for an external reset, input a low level for 10 s or more to the reset pin. 2. during reset input, the x1 clock, xt1 clock, in ternal high-speed o scillation clock, and internal low-speed oscillation clock stop oscilla ting. external main system clock input and external subsystem clock input become invalid. 3. when the stop mode is released by a re set, the stop mode contents are held during reset input. however, the port pins become hi gh-impedance, except for p130, which is set to low-level output. chapter 19 reset function user?s manual u17553ej4v0ud 553 figure 19-1. block di agram of reset function lvirf wdtrf reset control flag register (resf) internal bus watchdog timer reset signal reset power-on-clear circuit reset signal low-voltage detector reset signal reset signal reset signal to lvim/lvis register clear set clear set caution an lvi circuit internal r eset does not reset the lvi circuit. remarks 1. lvim: low-voltage detection register 2. lvis: low-voltage detection level selection register chapter 19 reset function user?s manual u17553ej4v0ud 554 figure 19-2. timing of reset by reset input delay delay (5 s (typ.)) hi-z normal operation cpu clock reset period (oscillation stop) normal operation (internal high-speed oscillation clock) reset internal reset signal port pin (except p130) port pin (p130) note high-speed system clock (when x1 oscillation is selected) internal high-speed oscillation clock starting x1 oscillation is specified by software. reset processing (11 to 45 s) wait for oscillation accuracy stabilization (86 to 361 s) note set p130 to high-level output by software. remark when reset is effected, p130 outputs a low level. if p130 is set to output a high level before reset is effected, the output signal of p130 ca n be dummy-output as the cpu reset signal. figure 19-3. timing of reset du e to watchdog timer overflow normal operation reset period (oscillation stop) cpu clock watchdog timer overflow internal reset signal hi-z port pin (except p130) port pin (p130) note high-speed system clock (when x1 oscillation is selected) internal high-speed oscillation clock starting x1 oscillation is specified by software. normal operation (internal high-speed oscillation clock) reset processing (11 to 45 s) wait for oscillation accuracy stabilization (86 to 361 s) note set p130 to high-level output by software. caution a watchdog timer internal reset resets the watchdog timer. remark when reset is effected, p130 outputs a low level. if p130 is set to output a high level before reset is effected, the output signal of p130 ca n be dummy-output as the cpu reset signal. chapter 19 reset function user?s manual u17553ej4v0ud 555 figure 19-4. timing of reset in stop mode by reset input delay normal operation cpu clock reset period (oscillation stop) reset internal reset signal stop instruction execution stop status (oscillation stop) high-speed system clock (when x1 oscillation is selected) internal high-speed oscillation clock hi-z port pin (except p130) port pin (p130) note starting x1 oscillation is specified by software. normal operation (internal high-speed oscillation clock) reset processing (11 to 45 s) delay (5 s (typ.)) wait for oscillation accuracy stabilization (86 to 361 s) note set p130 to high-level output by software. remarks 1. when reset is effected, p130 outputs a low level. if p130 is set to output a high level before reset is effected, the output signal of p130 ca n be dummy-output as the cpu reset signal. 2. for the reset timing of the power-on-cl ear circuit and low-voltage detector, see chapter 21 power-on-clear circuit and chapter 22 low-voltage detector . chapter 19 reset function user?s manual u17553ej4v0ud 556 table 19-1. operation st atuses during reset period item during reset period system clock clock supply to the cpu is stopped. f rh operation stopped f x operation stopped (pin is i/o port mode) main system clock f exclk clock input invalid (pin is i/o port mode) f xt operation stopped (pin is i/o port mode) subsystem clock f exclks clock input invalid (pin is i/o port mode) f rl cpu flash memory ram operation stopped regulator operable port (latch) 00 01 02 16-bit timer/event counter 03 50 8-bit timer/event counter 51 h0 8-bit timer h1 watch timer watchdog timer clock output buzzer output a/d converter uart60 uart61 csi10 serial interface csi11 can controller multiplier/divider operation stopped power-on-clear f unction operable low-voltage detection function external interrupt operation stopped remark f rh : internal high-speed oscillation clock f x : x1 oscillation clock f exclk : external main system clock f xt : xt1 oscillation clock f exclks : external subsystem clock f rl : internal low-speed oscillation clock chapter 19 reset function user?s manual u17553ej4v0ud 557 table 19-2. hardware statuses after reset acknowledgment (1/3) hardware after reset acknowledgment note 1 program counter (pc) the contents of the reset vector table (0000h, 0001h) are set. stack pointer (sp) undefined program status word (psw) 02h data memory undefined note 2 ram general-purpose registers undefined note 2 port registers (p0, p1, p3 to p9, p12, p13) (output latches) 00h pm0, pm1, pm3 to pm9, pm12 ffh port mode registers pm13 feh pull-up resistor option registers (pu0, pu1, pu3 to pu7, pu12, pu13) 00h internal expansion ram size switching register (ixs) 0ch note 3 internal memory size switching register (ims) cfh note 3 bank select register (bank) 00h processor clock control register (pcc) 01h clock operation mode select register (oscctl) 00h internal oscillator mode register (rcm) 00h note 4 main clock mode register (mcm) 00h main osc control register (moc) 80h oscillation stabilization time select register (osts) 05h oscillation stabilization time counter status register (ostc) 00h timer counters 00-03 (tm00-tm03) 0000h capture/compare registers 000-003, 010-013(cr000-cr003, cr010-cr013) 0000h mode control registers 00-03 (tmc00-tmc03) 00h prescaler mode register s 00-03 (prm00-prm03) 00h capture/compare control registers 00-03 (crc00-crc03) 00h 16-bit timer/event counters 00-03 timer output control registers 00-03 (toc00- toc03) 00h notes 1. during reset signal generation or oscillation st abilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware statuses remain unchanged after reset. 2. when a reset is executed in the standby mode, the pre-reset status is held even after reset. 3. the initial values of the internal memory size s witching register (ims) and internal expansion ram size switching register (ixs) after a reset release are c onstant (ims = cfh, ixs = 0ch) in all the 78k0/ff2 products, regardless of the internal memory capacity. therefore, after a reset is released, be sure to set the following values for each product. flash memory version (78k0/ff2) ims ixs pd78f0891 cfh 08h pd78f0892 cch 04h pd78f0893 cch 00h 4. the value of this register is 00h immediately after a reset release but automatically changes to 80h after internal high-speed oscillation has been stabilized. chapter 19 reset function user?s manual u17553ej4v0ud 558 table 19-2. hardware statuses after reset acknowledgment (2/3) hardware status after reset acknowledgment note 1 timer counters 50, 51 (tm50, tm51) 00h compare registers 50, 51 (cr50, cr51) 00h timer clock selection regist ers 50, 51 (tcl50, tcl51) 00h 8-bit timer/event counters 50, 51 mode control registers 50, 51 (tmc50, tmc51) 00h compare registers 00, 10, 01, 11 (cmp00, cmp10, cmp01, cmp11) 00h mode registers (tmhmd0, tmhmd1) 00h 8-bit timers h0, h1 carrier control register 1 (tmcyc1) note 2 00h watch timer operation m ode register (wtm) 00h clock output/buzzer output controller clock output selection register (cks) 00h watchdog timer enable register (wdte) 1ah/9ah note 3 10-bit a/d conversion result register (adcr) 0000h 8-bit a/d conversion result register (adcrh) 00h mode register (adm) 00h analog input channel specification register (ads) 00h a/d converter a/d port configuration register (adpc) 00h receive buffer register 60, 61 (rxb60, rxb61) ffh transmit buffer register 60, 61 (txb60, txb61) ffh asynchronous serial interface operat ion mode register 60, 61 (asim60, asim61) 01h asynchronous serial interface recept ion error status register 60, 61 (asis60, asis61) 00h asynchronous serial interface transmissi on status register 60, 61 (asif60, asif61) 00h clock selection register 60, 61 (cksr60, cksr61) 00h baud rate generator control register 60, 61 (brgc60, brgc61) ffh asynchronous serial interface control register 60, 61 (asicl60, asicl61) 16h serial interface uart60, uart61 input switch control register (isc) 00h transmit buffer registers 10, 11 (sotb10, sotb11) 00h serial i/o shift registers 10, 11 (sio10, sio11) 00h serial operation mode registers 10, 11 (csim10, csim11) 00h serial interfaces csi10, csi11 serial clock selection register s 10, 11 (csic10, csic11) 00h notes 1. during reset signal generation or oscillation st abilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware statuses remain unchanged after reset. 2. 8-bit timer h1 only. 3. the reset value of wdte is dete rmined by the option byte setting. chapter 19 reset function user?s manual u17553ej4v0ud 559 table 19-2. hardware statuses after reset acknowledgment (3/3) hardware status after reset acknowledgment note 1 remainder data register 0 (sdr0) 0000h multiplication/division data regi ster a0 (mda0h, mda0l) 0000h multiplication/division data register b0 (mdb0) 0000h multiplier/divider multiplier/divider control register 0 (dmuc0) 00h reset function reset control flag register (resf) 00h note2 low-voltage detection register (lvim) 00h note2 low-voltage detector low-voltage detection level selection register (lvis) 00h note2 request flag registers 0l, 0h, 1l, 1h (if0l, if0h, if1l, if1h) 00h mask flag registers 0l, 0h, 1l, 1h (mk0l, mk0h, mk1l, mk1h) ffh priority specification fl ag registers 0l, 0h, 1l, 1h (pr0l, pr0h, pr1l, pr1h) ffh external interrupt rising edge enable register (egp) 00h interrupt external interrupt falling edge enable register (egn) 00h notes 1. during reset signal generation or oscillation st abilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware statuses remain unchanged after reset. 2. these values vary depending on the reset source. reset source register reset input reset by poc reset by wdt reset by lvi wdtrf bit set (1) held resf lvirf bit cleared (0) cleared (0) held set (1) lvim lvis cleared (00h) cleared (00h) cleared (00h) held chapter 19 reset function user?s manual u17553ej4v0ud 560 19.1 register for confirming reset source many internal reset generation sources exist in the 78k0/ ff2. the reset control flag register (resf) is used to store which source has generated the reset request. resf can be read by an 8-bit memory manipulation instruction. reset input, reset input by power-on-clear (poc ) circuit, and reading resf clear resf to 00h. figure 19-5. format of reset control flag register (resf) address: ffach after reset: 00h note r symbol 7 6 5 4 3 2 1 0 resf 0 0 0 wdtrf 0 0 0 lvirf wdtrf internal reset request by watchdog timer (wdt) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. lvirf internal reset request by low-voltage detector (lvi) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. note the value after reset varies depending on the reset source. caution do not read data by a 1-bi t memory manipulation instruction. the status of resf when a reset request is generated is shown in table 19-3. table 19-3. resf status when reset request is generated reset source flag reset input reset by poc reset by wdt reset by lvi wdtrf set (1) held lvirf cleared (0) cleared (0) held set (1) user?s manual u17553ej4v0ud 561 chapter 20 multiplier/divider 20.1 functions of multiplier/divider the multiplier/divider has the following functions. ? 16 bits 16 bits = 32 bits (multiplication) ? 32 bits 16 bits = 32 bits, 16-bit remainder (division) 20.2 configuration of multiplier/divider the multiplier/divider incl udes the following hardware. table 20-1. configuration of multiplier/divider item configuration registers remainder data register 0 (sdr0) multiplication/division data r egisters a0 (mda0h, mda0l) multiplication/division dat a registers b0 (mdb0) control register multiplier/divider control register 0 (dmuc0) figure 20-1 shows the block diagram of the multiplier/divider. chapter 20 multiplier/divider user?s manual u17553ej4v0ud 562 figure 20-1. block diagra m of multiplier/divider internal bus cpu clock start clear 17-bit adder controller multiplication/division data register b0 (mdb0 (mdb0h + mdb0l) remainder data register 0 (sdr0 (sdr0h + sdr0l) 6-bit counter dmusel0 multiplier/divider control register 0 (dmuc0) controller multiplication/division data register a0 ( mda0h (mda0hh + mda0hl) + mda0l (mda0lh + mda0ll) ) controller dmue mda000 intdmu chapter 20 multiplier/divider user?s manual u17553ej4v0ud 563 (1) remainder data register 0 (sdr0) sdr0 is a 16-bit register that stores a remainder. th is register stores 0 in the multiplication mode and the remainder of an operation result in the division mode. sdr0 can be read by an 8-bit or 16-bit memory manipulation instruction. reset signal generation clears sdr0 to 0000h. figure 20-2. format of remainder data register 0 (sdr0) address: ff44h, ff45h after reset: 0000h r symbol ff45h (sdr0h) ff44h (sdr0l) sdr0 sdr 015 sdr 014 sdr 013 sdr 012 sdr 011 sdr 010 sdr 009 sdr 008 sdr 007 sdr 006 sdr 005 sdr 004 sdr 003 sdr 002 sdr 001 sdr 000 cautions 1. the value read from sdr0 during operation pro cessing (while bit 7 (dmue) of multiplier/divider control register 0 (dmuc0) is 1) is not guaranteed. 2. sdr0 is reset when the operation is started (when dmue is set to 1). (2) multiplication/division data register a0 (mda0h, mda0l) mda0 is a 32-bit register that sets a 16-bit multiplier a in the multiplication mode and a 32-bit dividend in the division mode, and stores the 32-bit result of the oper ation (higher 16 bits: mda0h, lower 16 bits: mda0l). figure 20-3. format of mult iplication/division data regi ster a0 (mda0h, mda0l) address: ff4ah, ff4bh, ff4ch, ff4dh after reset: 0000h, 0000h r/w symbol ff4dh (mda0hh) ff4ch (mda0hl) mda0h mda 031 mda 030 mda 029 mda 028 mda 027 mda 026 mda 025 mda 024 mda 023 mda 022 mda 021 mda 020 mda 019 mda 018 mda 017 mda 016 symbol ff4bh (mda0lh) ff4ah (mda0ll) mda0l mda 015 mda 014 mda 013 mda 012 mda 011 mda 010 mda 009 mda 008 mda 007 mda 006 mda 005 mda 004 mda 003 mda 002 mda 001 mda 000 cautions 1. mda0h is cleared to 0 when an operation is starte d in the multiplication mode (when multiplier/divider control regist er 0 (dmuc0) is set to 81h). 2. do not change the value of mda0 durin g operation processing (whi le bit 7 (dmue) of multiplier/divider control regi ster 0 (dmuc0) is 1). even in this case, the operation is executed, but the result is undefined. 3. the value read from mda0 during oper ation processing (while dmue is 1) is not guaranteed. chapter 20 multiplier/divider user?s manual u17553ej4v0ud 564 the functions of mda0 when an operation is executed are shown in the table below. table 20-2. functions of mda0 during operation execution dmusel0 operation mode setting operation result 0 division mode di vidend division result (quotient) 1 multiplication mode higher 16 bits: 0, lower 16 bits: multiplier a multiplication result (product) the register configuration differs between when multiplication is executed and when division is executed, as follows. ? register configuration during multiplication chapter 20 multiplier/divider user?s manual u17553ej4v0ud 565 20.3 register controlling multiplier/divider the multiplier/divider is controlled by mult iplier/divider control register 0 (dmuc0). (1) multiplier/divider c ontrol register 0 (dmuc0) dmuc0 is an 8-bit register that controls the operation of the multiplier/divider. dmuc0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears dmuc0 to 00h. figure 20-5. format of multiplier/divider control register 0 (dmuc0) dmue dmuc0 0 0 0 0 0 0 dmusel0 stops operation starts operation dmue note 0 1 operation start/stop division mode multiplication mode dmusel0 0 1 operation mode (multiplication/division) selection address: ff42h after reset: 00h r/w symbol 4 3 2 1 0 6 <7> 5 note when dmue is set to 1, the operat ion is started. dmue is automatica lly cleared to 0 after the operation is complete. cautions 1. if dmue is cleared to 0 during opera tion processing (when dmue is 1), the operation result is not guaranteed. if the oper ation is completed while the clearing instruction is being executed, the operation result is guaranteed, provided that the interrupt flag is set. 2. do not change the value of dmusel0 during operation processing (w hile dmue is 1). if it is changed, undefined operation results are stored in multiplication/division data register a0 (mda0) and remainder data register 0 (sdr0). 3. if dmue is cleared to 0 during operati on processing (while dmue is 1), the operation processing is stopped. to execute the operati on again, set multiplication/division data register a0 (mda0), multiplicat ion/division data register b0 (mdb0), and multiplier/divider control register 0 (dmuc0), and star t the operation (by setting dmue to 1). chapter 20 multiplier/divider user?s manual u17553ej4v0ud 566 20.4 operations of multiplier/divider 20.4.1 multiplication operation ? initial setting 1. set operation data to multiplication/division data regist er a0l (mda0l) and multiplication/division data register b0 (mdb0). 2. set bits 0 (dmusel0) and 7 (dmue) of multiplier/divi der control register 0 (dmuc0) to 1. operation will start. ? during operation 3. the operation will be completed when 16 internal clocks have been issued after the start of the operation (intermediate data is stored in t he mda0l and mda0h registers during oper ation, and ther efore the read values of these registers are not guaranteed). ? end of operation 4. the operation result data is stor ed in the mda0l and mda0h registers. 5. dmue is cleared to 0 (end of operation). 6. after the operation, an interrup t request signal (intdmu) is generated. ? next operation 7. to execute multiplication next, start from the initial setting in 20.4.1 multiplication operation . 8. to execute division next, start from the initial setting in 20.4.2 division operation . chapter 20 multiplier/divider user?s manual u17553ej4v0ud 567 figure 20-6. timing chart of multiplication operation (00dah 0093h) operation clock mda0 sdr0 mdb0 1 2 345 6 78 9a b cd e f 10 0 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 006d 0000 00da xxxx 00da xxxx xxxx xxxx 0049 8036 0024 c01b 005b e00d 0077 7006 003b b803 0067 5c01 007d 2e00 003e 9700 001f 4b80 000f a5c0 0007 d2e0 0003 e970 0001 f4b8 0000 fa5c 0000 7d2e 0093 xxxx internal clock dmue dmusel0 counter intdmu chapter 20 multiplier/divider user?s manual u17553ej4v0ud 568 20.4.2 division operation ? initial setting 1. set operation data to multiplicati on/division data register a0 (mda0l a nd mda0h) and multiplication/division data register b0 (mdb0). 2. set bits 0 (dmusel0) and 7 (dmue) of multiplier/divider control register 0 (dmuc0) to 0 and 1, respectively. operation will start. ? during operation 3. the operation will be completed when 32 internal clocks have been issued after the start of the operation (intermediate data is stored in the mda0l and mda0 h registers and remainder data register 0 (sdr0) during operation, and theref ore the read values of these registers are not guaranteed). ? end of operation 4. the result data is stored in th e mda0l, mda0h, and sdr0 registers. 5. dmue is cleared to 0 (end of operation). 6. after the operation, an interrup t request signal (intdmu) is generated. ? next operation 7. to execute multiplication next, start from the initial setting in 20.4.1 multiplication operation . 8. to execute division next, start from the initial setting in 20.4.2 division operation . chapter 20 multiplier/divider user?s manual u17553ej4v0ud 569 figure 20-7. timing chart of division operation (dcba2586h 0018h) operation clock mda0 sdr0 mdb0 12345678 19 1a 1b 1c 1d 1e 1f 20 0 0 0000 0001 0003 0006 000d 0003 0007 000e 0004 000b 0016 0014 0010 0008 0011 000b 0016 b974 4b0c dcba 2586 xxxx xxxx xxxx 72e8 a618 e5d1 2c30 cba2 6860 a744 bac1 2e89 6182 6d12 c304 ba25 8609 0c12 64d8 1824 c9b0 3049 9361 6093 26c3 c126 4d87 824c 9b0e 0499 361d 0932 6c3a 0018 xxxx internal clock dmue dmusel0 counter intdmu ?0? user?s manual u17553ej4v0ud 570 chapter 21 power-on-clear circuit 21.1 functions of power-on-clear circuit the power-on-clear circuit (poc) has the following functions. ? generates internal reset signal at power on. in the 1.59 v poc mode (option byte: lvistart = 0), the reset signal is released when the supply voltage (v dd ) exceeds 1.59 v 0.15 v. in the 2.7 v/1.59 v poc m ode (option byte: lvistart = 1), the re set signal is released when the supply voltage (v dd ) exceeds 2.7 v 0.2 v. ? compares supply voltage (v dd ) and detection voltage (v poc = 1.59 v 0.15 v), generates internal reset signal when v dd < v poc . caution if an internal reset signal is generated in the poc circuit, th e reset control flag register (resf) is cleared to 00h. remark the 78k0/ff2 incorporates multip le hardware functions that generate an internal reset signal. a flag that indicates the reset cause is located in the re set control flag register (resf) for when an internal reset signal is generated by the watchdog timer (w dt) or low-voltage-detector (lvi). resf is not cleared to 00h and the flag is set to 1 when an internal reset signal is generated by wdt or lvi. for details of resf, see chapter 19 reset function . chapter 21 power-on-clear circuit user?s manual u17553ej4v0ud 571 21.2 configuration of power-on-clear circuit the block diagram of the power-on-clear circuit is shown in figure 21-1. figure 21-1. block diagram of power-on-clear circuit ? + reference voltage source internal reset signal v dd v dd 21.3 operation of power-on-clear circuit (1) in 1.59 v poc mode (option byte: lvistart = 0) ? an internal reset signal is generated on po wer application. when the supply voltage (v dd ) exceeds the detection voltage (v poc = 1.59 v 0.15 v), the reset status is released. ? the supply voltage (v dd ) and detection voltage (v poc = 1.59 v 0.15 v) are compared. when v dd < v poc , the internal reset signal is generated. it is released when v dd v poc . (2) in 2.7 v/1.59 v poc mode (option byte: lvistart = 1) ? an internal reset signal is generated on po wer application. when the supply voltage (v dd ) exceeds the detection voltage (v ddpoc = 2.7 v 0.2 v), the reset status is released. ? the supply voltage (v dd ) and detection voltage (v poc = 1.59 v 0.15 v) are compared. when v dd < v poc , the internal reset signal is generated. it is released when v dd v ddpoc . the timing of generation of the internal reset signal by the power-on-clear circuit and low-voltage detector is shown below. chapter 21 power-on-clear circuit user?s manual u17553ej4v0ud 572 figure 21-2. timing of generation of intern al reset signal by power-on-clear circuit and low-voltage detector (1/2) (1) in 1.59 v poc mode (option byte: lvistart = 0) note 3 note 3 internal high-speed oscillation clock (f rh ) high-speed system clock (f xh ) (when x1 oscillation is selected) starting oscillation is specified by software. v poc = 1.59 v (typ.) v lvi operation stops wait for voltage stabilization (1.93 to 5.39 ms) normal operation (internal high-speed oscillation clock) note 4 operation stops reset period (oscillation stop) reset period (oscillation stop) wait for oscillation accuracy stabilization (86 to 361 s) normal operation (internal high-speed oscillation clock) note 4 starting oscillation is specified by software. starting oscillation is specified by software. cpu 0 v supply voltage (v dd ) 1.8 v note 1 wait for voltage stabilization (1.93 to 5.39 ms) normal operation (internal high-speed oscillation clock ) note 4 0.5 v/ms (min.) note 2 set lvi to be used for reset set lvi to be used for reset set lvi to be used for interrupt internal reset signal reset processing (11 to 45 s) reset processing (11 to 45 s) reset processing (11 to 45 s) notes 1. the operation guaranteed range is 1.8 v v dd 5.5 v. to make the state at lower than 1.8 v reset state when the supply voltage falls, use the reset func tion of the low-voltage det ector, or input the low level to the reset pin. 2. if the voltage rises to 1.8 v at a rate slower than 0. 5 v/ms (min.) on power application, input a low level to the reset pin after power application and before the voltage reaches 1.8 v, or set the 2.7 v/1.59 v poc mode by using an option byte (lvistart = 1). 3. the internal voltage stabilization time includes the o scillation accuracy stabilization time of the internal high-speed oscillation clock. 4. the internal high-speed oscillation clock and a hi gh-speed system clock or subsystem clock can be selected as the cpu clock. to us e the x1 clock, use the ostc regi ster to confirm the lapse of the oscillation stabilization time. to use the xt1 clock, use the timer function for confirmation of the lapse of the stabilization time. caution set the low-voltage detector by software after the reset status is released (see chapter 22 low-voltage detector). remark v lvi : lvi detection voltage v poc : poc detection voltage chapter 21 power-on-clear circuit user?s manual u17553ej4v0ud 573 figure 21-2. timing of generation of intern al reset signal by power-on-clear circuit and low-voltage detector (2/2) (2) in 2.7 v / 1.59v poc mode (option byte: lvistart = 1) internal high-speed oscillation clock (f rh ) high-speed system clock (f xh ) (when x1 oscillation is selected) starting oscillation is specified by software. internal reset signal v ddpoc = 2.7 v (typ.) v poc = 1.59 v (typ.) v lvi operation stops normal operation (internal high-speed oscillation clock) note 2 normal operation (internal high-speed oscillation clock) note 2 operation stops reset period (oscillation stop) reset period (oscillation stop) normal operation (internal high-speed oscillation clock) note 2 starting oscillation is specified by software. starting oscillation is specified by software. cpu 0 v supply voltage (v dd ) 1.8 v note 1 reset processing (11 to 45 s) reset processing (11 to 45 s) reset processing (11 to 45 s) set lvi to be used for reset set lvi to be used for reset set lvi to be used for interrupt wait for oscillation accuracy stabilization (86 to 361 s) wait for oscillation accuracy stabilization (86 to 361 s) wait for oscillation accuracy stabilization (86 to 361 s) notes 1. the operation guaranteed range is 1.8 v v dd 5.5 v. to make the state at lower than 1.8 v reset state when the supply voltage falls, use the reset func tion of the low-voltage det ector, or input the low level to the reset pin. 2. the internal high-speed oscillation clock and a hi gh-speed system clock or subsystem clock can be selected as the cpu clock. to us e the x1 clock, use the ostc regi ster to confirm the lapse of the oscillation stabilization time. to use the xt1 clock, use the timer function for confirmation of the lapse of the stabilization time. cautions 1. set the low-voltage de tector by software after the reset status is released (see chapter 22 low-voltage detector). 2. a voltage oscillation stabilization time of 1. 93 to 5.39 ms is required after the supply voltage reaches 1.59 v (typ.). if the s upply voltage rises from 1.59 v (t yp.) to 2.7 v (typ.) within 1.93 ms, the power supply oscillation stabilization ti me of 0 to 5.39 ms is automatically generated before reset processing. remark v lvi : lvi detection voltage v poc : poc detection voltage chapter 21 power-on-clear circuit user?s manual u17553ej4v0ud 574 21.4 cautions for power-on-clear circuit in a system where the supply voltage (v dd ) fluctuates for a certain period in the vicinity of the poc detection voltage (v poc ), the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the oper ation of the microcontroller can be arbitrarily set by taking the following action. chapter 21 power-on-clear circuit user?s manual u17553ej4v0ud 575 figure 21-3. example of software pr ocessing after release of reset (2/2) ? checking reset cause yes no check reset cause power-on-clear/external reset generated reset processing by watchdog timer reset processing by low-voltage detector no wdtrf of resf register = 1? lvirf of resf register = 1? yes user?s manual u17553ej4v0ud 576 chapter 22 low-voltage detector 22.1 functions of low-voltage detector the low-voltage detector (lvi ) has the following functions. ? the lvi circuit compares the supply voltage (v dd ) with the detection voltage (v lvi ) or the input voltage from an external input pin (exlvi) with the detection voltage (v exlvi = 1.21 v (typ.): fixed), and generates an internal reset or internal interrupt signal. ? the supply voltage (v dd ) or input voltage from an external input pin (exlvi) can be selected by software. ? reset or interrupt function can be selected by software. ? detection levels (16 levels) of suppl y voltage can be changed by software. ? operable in stop mode. the reset and interrupt signals are generated as follows depending on selection by software. selection of level detection of supply voltage (v dd ) (lvisel = 0) selection level detection of input voltage from external input pin (exlvi) (lvisel = 1) selects reset (lvimd = 1). selects interrupt (lvimd = 0). selects reset (lvimd = 1). selects interrupt (lvimd = 0). generates an internal reset signal when v dd < v lvi and releases the reset signal when v dd v lvi . generates an internal interrupt signal when v dd drops lower than v lvi (v dd < v lvi ) or when v dd becomes v lvi or higher (v dd v lvi ). generates an internal reset signal when exlvi < v exlvi and releases the reset signal when exlvi v exlvi . generates an internal interrupt signal when exlvi drops lower than v exlvi (exlvi < v exlvi ) or when exlvi becomes v exlvi or higher (exlvi v exlvi ). remark lvisel: bit 2 of low-voltage detection register (lvim) lvimd: bit 1 of lvim while the low-voltage detector is operat ing, whether the supply voltage or t he input voltage from an external input pin is more than or less than the detection level can be che cked by reading the low-voltage detection flag (lvif: bit 0 of lvim). when the low-voltage detector is used to reset, bit 0 (lvirf) of the reset control flag regi ster (resf) is set to 1 if reset occurs. for details of resf, see chapter 19 reset function . chapter 22 low-voltage detector user?s manual u17553ej4v0ud 577 22.2 configuration of low-voltage detector the block diagram of the low-voltage detector is shown in figure 22-1. figure 22-1. block diagram of low-voltage detector lvis1 lvis0 lvion ? + reference voltage source v dd internal bus n-ch low-voltage detection level selection register (lvis) low-voltage detection register (lvim) lvis2 lvis3 lvif intlvi internal reset signal 4 lvisel exlvi/p120/ intp0 lvimd v dd low-voltage detection level selector selector selector 22.3 registers controlling low-voltage detector the low-voltage detector is contro lled by the following registers. ? low-voltage detection register (lvim) ? low-voltage detection level selection register (lvis) ? port mode register 12 (pm12) chapter 22 low-voltage detector user?s manual u17553ej4v0ud 578 (1) low-voltage detection register (lvim) this register sets low-voltag e detection and the operation mode. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears lvim to 00h. figure 22-2. format of low-volta ge detection register (lvim) <0> lvif <1> lvimd <2> lvisel 3 0 4 0 5 0 6 0 <7> lvion symbol lvim address: ffbeh after reset: 00h r/w note 1 lvion notes 2, 3 enables low-voltage detection operation 0 disables operation 1 enables operation lvisel note 2 voltage detection selection 0 detects level of supply voltage (v dd ) 1 detects level of input voltage from external input pin (exlvi) lvimd note 2 low-voltage detection operation m ode (interrupt/reset) selection 0 ? lvisel = 0: generates an internal interrupt signal when the supply voltage (v dd ) drops lower than the detection voltage (v lvi ) (v dd < v lvi ) or when v dd becomes v lvi or higher (v dd v lvi ). ? lvisel = 1: generates an interrupt signal when the input voltage from an external input pin (exlvi) drops lower than the detection voltage (v exlvi ) (exlvi < v exlvi ) or when exlvi becomes v exlvi or higher (exlvi v exlvi ). 1 ? lvisel = 0: generates an internal reset signal when the supply voltage (v dd ) < detection voltage (v lvi ) and releases the reset signal when v dd v lvi . ? lvisel = 1: generates an internal reset signal when the input voltage from an external input pin (exlvi) < detection voltage (v exlvi ) and releases the reset signal when exlvi v exlvi . lvif note 4 low-voltage detection flag 0 ? lvisel = 0: supply voltage (v dd ) detection voltage (v lvi ), or when operation is disabled ? lvisel = 1: input voltage from external input pin (exlvi) detection voltage (v exlvi ), or when operation is disabled 1 ? lvisel = 0: supply voltage (v dd ) < detection voltage (v lvi ) ? lvisel = 1: input voltage from external input pin (exlvi) < detection voltage (v exlvi ) notes 1. bit 0 is read-only. 2. lvion, lvimd, and lvisel are cleared to 0 in the case of a reset other than an lvi reset. these are not cleared to 0 in the case of an lvi reset. 3. when lvion is set to 1, operation of the compar ator in the lvi circuit is started. use software to wait for an operation stabilization time and minimum pulse width (10 s (max.)) when lvion is set to 1 until the voltage is confirmed at lvif. 4. the value of lvif is output as the interru pt request signal intlvi when lvion = 1 and lvimd = 0. chapter 22 low-voltage detector user?s manual u17553ej4v0ud 579 cautions 1. to stop lvi, follow either of the procedures below. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0. 2. input voltage from external input pin (exlvi) must be exlvi < v dd . (2) low-voltage detection level selection register (lvis) this register selects the low-voltage detection level. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears lvis to 00h. figure 22-3. format of low-voltage dete ction level selection register (lvis) 0 lvis0 1 lvis1 2 lvis2 3 lvis3 4 0 5 0 6 0 7 0 symbol lvis address: ffbfh after reset: 00h r/w lvis3 lvis2 lvis1 lvis0 detection level 0 0 0 0 v lvi0 (4.24 v 0.1 v) 0 0 0 1 v lvi1 (4.09 v 0.1 v) 0 0 1 0 v lvi2 (3.93 v 0.1 v) 0 0 1 1 v lvi3 (3.78 v 0.1 v) 0 1 0 0 v lvi4 (3.62 v 0.1 v) 0 1 0 1 v lvi5 (3.47 v 0.1 v) 0 1 1 0 v lvi6 (3.32 v 0.1 v) 0 1 1 1 v lvi7 (3.16 v 0.1 v) 1 0 0 0 v lvi8 (3.01 v 0.1 v) 1 0 0 1 v lvi9 (2.85 v 0.1 v) 1 0 1 0 v lvi10 (2.70 v 0.1 v) 1 0 1 1 v lvi11 (2.55 v 0.1 v) 1 1 0 0 v lvi12 (2.39 v 0.1 v) 1 1 0 1 v lvi13 (2.24 v 0.1 v) 1 1 1 0 v lvi14 (2.08 v 0.1 v) 1 1 1 1 v lvi15 (1.93 v 0.1 v) cautions 1. be sure to clear bits 4 to 7 to 0. 2. do not change the value of lvis during lvi operation. 3. when an input voltage from the externa l input pin (exlvi) is detected, the detection voltage (v exlvi = 1.21 v (typ.)) is fixed. therefor e, setting of lvis is not necessary. chapter 22 low-voltage detector user?s manual u17553ej4v0ud 580 (3) port mode register 12 (pm12) when using the p120/exlvi/intp0 pin for external low-volt age detection potential input, set pm120 to 1. at this time, the output latch of p120 may be 0 or 1. pm12 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pm12 to ffh. figure 22-4. format of port mode register 12 (pm12) 0 pm120 1 pm121 2 pm122 3 pm123 4 pm124 5 1 6 1 7 1 symbol pm12 address: ff2ch after reset: ffh r/w pm12n p12n pin i/o mode selection (n = 0 to 4) 0 output mode (output buffer on) 1 input mode (output buffer off) 22.4 operation of low-voltage detector the low-voltage detector can be us ed in the following two modes. (1) used as reset (lvimd = 1) ? if lvisel = 0, compares the supply voltage (v dd ) and detection voltage (v lvi ), generates an internal reset signal when v dd < v lvi , and releases internal reset when v dd v lvi . ? if lvisel = 1, compares the input voltage from external input pin (exlvi) and detection voltage (v exlvi = 1.21 v (typ.)), generates an internal reset signal when exlvi < v exlvi , and releases internal reset when exlvi v exlvi . (2) used as interrupt (lvimd = 0) ? if lvisel = 0, compares the supply voltage (v dd ) and detection voltage (v lvi ). when v dd drops lower than v lvi (v dd < v lvi ) or when v dd becomes v lvi or higher (v dd v lvi ), generates an interrupt signal (intlvi). ? if lvisel = 1, compares the input voltage from external input pin (exlvi) and detection voltage (v exlvi = 1.21 v (typ.)). when exlvi drops lower than v exlvi (exlvi < v exlvi ) or when exlvi becomes v exlvi or higher (exlvi v exlvi ), generates an interrupt signal (intlvi). while the low-voltage detector is operat ing, whether the supply voltage or t he input voltage from an external input pin is more than or less than the detection level can be che cked by reading the low-voltage detection flag (lvif: bit 0 of lvim). remark lvimd: bit 1 of low-voltage detection register (lvim) lvisel: bit 2 of lvim chapter 22 low-voltage detector user?s manual u17553ej4v0ud 581 22.4.1 when used as reset (1) when detecting level of supply voltage (v dd ) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> clear bit 2 (lvisel) of the low-voltage detection r egister (lvim) to 0 (detects level of supply voltage (v dd )) (default value). <3> set the detection voltage using bits 3 to 0 (lvis3 to lvis0) of the low-voltage detection level selection register (lvis). <4> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <5> use software to wait for an operation stabilization time and minimum pulse width (10 s (max.)). <6> wait until it is checked that (supply voltage (v dd ) detection voltage (v lvi )) by bit 0 (lvif) of lvim. <7> set bit 1 (lvimd) of lvim to 1 (generates reset when the level is detected). figure 22-5 shows the timing of the internal reset signal generated by the low-volt age detector. the numbers in this timing chart correspond to <1> to <7> above. cautions 1. <1> must always be executed. when lvimk = 0, an interrupt may occur immediately after the processing in <4>. 2. if supply voltage (v dd ) detection voltage (v lvi ) when lvimd is set to 1, an internal reset signal is not generated. ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvimd to 0 and then lvion to 0. chapter 22 low-voltage detector user?s manual u17553ej4v0ud 582 figure 22-5. timing of low-voltage dete ctor internal reset signal generation (detects level of supply voltage (v dd )) (1/2) (1) in 1.59 v poc mode setup (option byte: lvistart = 0) supply voltage (v dd ) <3> <1> time lvimk flag (set by software lvif flag lvirf flag note 3 note2 lvi reset signal poc reset signal internalreset signal cleared by software not cleared cleared by software <4> <7> clear clear clear <5>wait time lvion flag (set by software) lvimd flag (set by software) h note1 l lvisel flag (set by software) <6> <2> v lvi v poc = 1.59 v (typ.) not cleared not cleared not cleared notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the lvif flag may be set (1). 3. lvirf is bit 0 of the reset control flag re gister (resf). for details of resf, see chapter 19 reset function . remark <1> to <7> in figure 22-5 above correspond to <1> to <7> in the description of ?when starting operation? in 22.4.1 (1) when detecting level of supply voltage (v dd ) . chapter 22 low-voltage detector user?s manual u17553ej4v0ud 583 figure 22-5. timing of low-voltage dete ctor internal reset signal generation (detects level of supply voltage (v dd )) (2/2) (2) in 2.7/1.59 v poc mode setup (option byte: lvistart = 1) supply voltage (v dd ) v lvi <3> <1> time lvimk flag (set by software) lvif flag lvirf flag note 3 note 2 lvi reset signal poc reset signal internal reset signal cleared by software not cleared not cleared not cleared not cleared cleared by software <4> <7> clear clear clear <5> wait time lvion flag (set by software) lvimd flag (set by software) h note 1 l lvisel flag (set by software) <6> <2> 2.7 v (typ.) v poc = 1.59 v (typ.) notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the lvif flag may be set (1). 3. lvirf is bit 0 of the reset control flag re gister (resf). for details of resf, see chapter 19 reset function . remark <1> to <7> in figure 22-5 above correspond to <1> to <7> in the description of ?when starting operation? in 22.4.1 (1) when detecting level of supply voltage (v dd ) . chapter 22 low-voltage detector user?s manual u17553ej4v0ud 584 (2) when detecting level of input vo ltage from external input pin (exlvi) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set bit 2 (lvisel) of the low-voltage detection regist er (lvim) to 1 (detects level of input voltage from external input pin (exlvi)). <3> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <4> use software to wait for an operation stabilization time and minimum pulse width (10 s (max.)). <5> wait until it is checked that (input voltage from external input pin (exlvi) detection voltage (v exlvi = 1.21 v (typ.))) by bit 0 (lvif) of lvim. <6> set bit 1 (lvimd) of lvim to 1 (generates reset signal when the level is detected). figure 22-6 shows the timing of the internal reset signal generated by the low-volt age detector. the numbers in this timing chart correspond to <1> to <6> above. cautions 1. <1> must always be executed. when lvimk = 0, an interrupt may occur immediately after the processing in <3>. 2. if input voltage from external input pin (exlvi) detection voltage (v exlvi = 1.21 v (typ.)) when lvimd is set to 1, an in ternal reset signal is not generated. 3. input voltage from external input pin (exlvi) must be exlvi < v dd . ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvimd to 0 and then lvion to 0. chapter 22 low-voltage detector user?s manual u17553ej4v0ud 585 figure 22-6. timing of low-voltage dete ctor internal reset signal generation (detects level of input voltage fr om external input pin (exlvi)) input voltage from external input pin (exlvi) lvi detection voltage (v exlvi ) <1> time lvimk flag (set by software) lvif flag lvirf flag note 3 note 2 lvi reset signal internal reset signal cleared by software not cleared not cleared not cleared not cleared cleared by software <3> <6> lvion flag (set by software) lvimd flag (set by software) h note 1 lvisel flag (set by software) <5> <2> not cleared not cleared <4> wait time not cleared not cleared not cleared notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the lvif flag may be set (1). 3. lvirf is bit 0 of the reset control flag re gister (resf). for details of resf, see chapter 19 reset function . remark <1> to <6> in figure 22-6 above correspond to <1> to <6> in the description of ? when starting operation? in 22.4.1 (2) when detecting level of input voltage from external input pin (exlvi) . chapter 22 low-voltage detector user?s manual u17553ej4v0ud 586 22.4.2 when used as interrupt (1) when detecting level of supply voltage (v dd ) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> clear bit 2 (lvisel) of the low-voltage detection r egister (lvim) to 0 (detects level of supply voltage (v dd )) (default value). <3> set the detection voltage using bits 3 to 0 (lvis3 to lvis0) of the low-voltage detection level selection register (lvis). <4> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <5> use software to wait for an operation stabilization time and minimum pulse width (10 s (max.)). <6> confirm that ?supply voltage (v dd ) detection voltage (v lvi )? when detecting the falling edge of v dd , or ?supply voltage (v dd ) < detection voltage (v lvi )? when detecting the rising edge of v dd , at bit 0 (lvif) of lvim. <7> clear the interrupt request flag of lvi (lviif) to 0. <8> release the interrupt mask flag of lvi (lvimk). <9> clear bit 1 (lvimd) of lvim to 0 (generates interr upt signal when the level is detected) (default value). <10> execute the ei instruction (w hen vector interrupts are used). figure 22-7 shows the timing of the interrupt signal ge nerated by the low-voltage detector. the numbers in this timing chart correspond to <1> to <9> above. ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0. chapter 22 low-voltage detector user?s manual u17553ej4v0ud 587 figure 22-7. timing of low-voltage de tector interrupt signal generation (detects level of supply voltage (v dd )) (1/2) (1) in 1.59 v poc mode setup (option byte: lvistart = 0) supply voltage (v dd ) time <1> note 1 <8> cleared by software lvimk flag (set by software) lvif flag intlvi lviif flag internal reset signal <4> <6> <7> cleared by software <5> wait time lvion flag (set by software) note 2 note 2 <3> l lvisel flag (set by software) <2> lvimd flag (set by software) l <9> v lvi v poc = 1.59 v (typ.) note 2 notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the interrupt request signal (intlvi) is generat ed and the lvif and lviif flags may be set (1). remark <1> to <9> in figure 22-7 above correspond to <1> to <9> in the description of ?when starting operation? in 22.4.2 (1) when detecting level of supply voltage (v dd ) . chapter 22 low-voltage detector user?s manual u17553ej4v0ud 588 figure 22-7. timing of low-voltage de tector interrupt signal generation (detects level of supply voltage (v dd )) (2/2) (2) in 2.7/1.59 v poc mode setup (option byte: lvistart = 1) supply voltage (v dd ) time <1> note 1 <8> cleared by software lvimk flag (set by software) lvif flag intlvi lviif flag internal reset signal <4> <6> <7> cleared by software <5> wait time lvion flag (set by software) note 2 note 2 <3> l lvisel flag (set by software) <2> lvimd flag (set by software) l <9> v lvi 2.7 v(typ.) v poc = 1.59 v (typ.) note 2 notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the interrupt request signal (intlvi) is generat ed and the lvif and lviif flags may be set (1). remark <1> to <9> in figure 22-7 above correspond to <1> to <9> in the description of ?when starting operation? in 22.4.2 (1) when detecting level of supply voltage (v dd ) . chapter 22 low-voltage detector user?s manual u17553ej4v0ud 589 (2) when detecting level of input vo ltage from external input pin (exlvi) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set bit 2 (lvisel) of the low-voltage detection regist er (lvim) to 1 (detects level of input voltage from external input pin (exlvi)). <3> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <4> use software to wait for an operation stabilization time and minimum pulse width (10 s (max.)). <5> confirm that ?input voltage from external input pin (exlvi) detection voltage (v exlvi = 1.21 v (typ.)? when detecting the falling edge of exlvi, or ?input vo ltage from external input pin (exlvi) < detection voltage (v exlvi = 1.21 v (typ.))? when detecting the rising e dge of exlvi, at bit 0 (lvif) of lvim. <6> clear the interrupt request flag of lvi (lviif) to 0. <7> release the interrupt mask flag of lvi (lvimk). <8> clear bit 1 (lvimd) of lvim to 0 (generates interr upt signal when the level is detected) (default value). <9> execute the ei instruction (w hen vector interrupts are used). figure 22-8 shows the timing of the interrupt signal ge nerated by the low-voltage detector. the numbers in this timing chart correspond to <1> to <8> above. caution input voltage from external i nput pin (exlvi) must be exlvi < v dd . ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0. chapter 22 low-voltage detector user?s manual u17553ej4v0ud 590 figure 22-8. timing of low-voltage detector interrupt signal generation (detects level of input voltage fr om external input pin (exlvi)) input voltage from external input pin (exlvi) v exlvi time <1> note 1 <7> cleared by software lvimk flag (set by software) lvif flag intlvi lviif flag <3> <5> <6> cleared by software <4> wait time lvion flag (set by software) note 2 note 2 lvisel flag (set by software) <2> lvimd flag (set by software) l <8> note 2 notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the interrupt request signal (intlvi) is generat ed and the lvif and lviif flags may be set (1). remark <1> to <8> in figure 22-8 above correspond to <1> to <8> in the description of ?when starting operation? in 22.4.2 (2) when detecting level of input voltage from external input pin (exlvi) . chapter 22 low-voltage detector user?s manual u17553ej4v0ud 591 22.5 cautions for low-voltage detector in a system where the supply voltage (v dd ) fluctuates for a certain period in t he vicinity of the lvi detection voltage (v lvi ), the operation is as follows depending on how the low-voltage detector is used. (1) when used as reset the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action (1) below. (2) when used as interrupt interrupt requests may be frequently generated. take (b) of action (2) below. chapter 22 low-voltage detector user?s manual u17553ej4v0ud 592 figure 22-9. example of software processing after reset release (1/2) ? if supply voltage fluctuation is 50 ms or less in vicinity of lvi detection voltage ; check the reset source note initialize the port. ; setting of detection level by lvis the low-voltage detector operates (lvion = 1). reset initialization processing <1> 50 ms has passed? (tmifh1 = 1?) initialization processing <2> setting 8-bit timer h1 (to measure 50 ms) ; setting of division ratio of system clock, such as setting of timer or a/d converter yes no setting lvi clearing wdt detection voltage or higher (lvif = 0?) yes lvif = 0 restarting timer h1 (tmhe1 = 0 tmhe1 = 1) no ; the low-voltage detection flag is cleared. ; the timer counter is cleared and the timer is started. lvi reset ;f prs = internal high-speed oscillation clock (8.4 mhz (max.)) (default) source: f prs (8.4 mhz (max.))/2 12 , where comparison value = 102: ? 50 ms timer starts (tmhe1 = 1). note a flowchart is shown on the next page. chapter 22 low-voltage detector user?s manual u17553ej4v0ud 593 figure 22-9. example of software processing after reset release (2/2) ? checking reset cause yes no check reset cause power-on-clear/external reset generated reset processing by watchdog timer reset processing by low-voltage detector yes wdtrf of resf register = 1? lvirf of resf register = 1? no user?s manual u17553ej4v0ud 594 chapter 23 option byte 23.1 functions of option bytes the flash memory at 0080h to 0084h of the 78k0/ff2 is an option byte area. when power is turned on or when the device is restarted from the reset status, the device automatically referenc es the option bytes and sets specified functions. when using the product, be sure to set t he following functions by using the option bytes. when the boot swap operation is used du ring self-programming, 0080h to 0084h are switched to 1080h to 1084h. therefore, set values that are the same as thos e of 0080h to 0084h to 1080h to 1084h in advance. caution be sure to set 00h to 0082h and 0083h (0082h/1082h and 0083h/1 083h when the boot swap function is used). (1) 0080h/1080h { internal low-speed oscillator operation ? can be stopped by software ? cannot be stopped { watchdog timer interval time setting { watchdog timer counter operation ? enabled counter operation ? disabled counter operation { watchdog timer window open period setting caution set a value that is the same as that of 0080h to 1080h because 0080h and 1080h are switched during the boot swap operation. (2) 0081h/1081h { selecting poc mode ? during 2.7 v/1.59 v poc mo de operation (lvistart = 1) the device is in the reset state upon power application and until the supply voltage reaches 2.7 v (typ.). it is released from the reset state when the voltage exceeds 2.7 v (typ.). after that , poc is not detected at 2.7 v but is detect ed at 1.59 v (typ.). if the supply voltage rises to 1.8 v after power applicati on at a pace slower than 0.5 v/ms (min.), use of the 2.7 v/1.59 v poc mode is recommended. ? during 1.59 v poc mode operation (lvistart = 0) the device is in the reset state upon power application and until the suppl y voltage reaches 1.59 v (typ.). it is released from the reset state when the voltage exceeds 1.59 v (typ.). after that, poc is detected at 1.59 v (typ.), in the same mann er as on power application. caution lvistart can only be writ ten by using a dedicated flash me mory programmer. it cannot be set during self-programming or boot swap operat ion during self-progra mming (at this time, 1.59 v poc mode (default) is set). however, be cause the value of 1081h is copied to 0081h during the boot swap operation, it is recommended to set a value that is the same as that of 0081h to 1081h when the boot swap function is used. chapter 23 option byte user?s manual u17553ej4v0ud 595 (3) 0084h/1084h { on-chip debug operation control ? disabling on-chip debug operation ? enabling on-chip debug operation and erasing data of th e flash memory in case authentication of the on- chip debug security id fails ? enabling on-chip debug operation and not erasing data of the flash memory even in case authentication of the on-chip debug security id fails caution to use the on-chip debug function, set 02h or 03h to 0084h. set a value that is the same as that of 0084h to 1084h because 0084h and 1084h ar e switched during th e boot operation. chapter 23 option byte user?s manual u17553ej4v0ud 596 23.2 format of option byte the format of the option byte is shown below. figure 23-1. format of option byte (1/2) address: 0080h/1080h note 7 6 5 4 3 2 1 0 0 window1 window0 wdton wdcs2 wdcs1 wdcs0 lsrosc window1 window0 watchdog timer window open period 0 0 25% 0 1 50% 1 0 75% 1 1 100% wdton operation control of watchdog ti mer counter/illegal access detection 0 counter operation disabled (counting stopped afte r reset), illegal access detection operation disabled 1 counter operation enabled (counting started after reset), illegal access detection operation enabled wdcs2 wdcs1 wdcs0 watc hdog timer overflow time 0 0 0 2 10 /f rl (3.88 ms) 0 0 1 2 11 /f rl (7.76 ms) 0 1 0 2 12 /f rl (15.52 ms) 0 1 1 2 13 /f rl (31.03 ms) 1 0 0 2 14 /f rl (62.06 ms) 1 0 1 2 15 /f rl (124.12 ms) 1 1 0 2 16 /f rl (248.24 ms) 1 1 1 2 17 /f rl (496.48 ms) lsrosc internal low-speed oscillator operation 0 can be stopped by software (stopped when 1 is written to bit 0 (lsrstop) of rcm register) 1 cannot be stopped (not stopped even if 1 is written to lsrstop bit) note set a value that is the same as that of 0080h to 1080h because 0080h and 1080h are switched during the boot swap operation. cautions 1. the combination of wdcs2 = wdcs1 = wdcs0 = 0 and window1 = window0 = 0 is prohibited. 2. the watchdog timer continues its operation during self-programming and eeprom emulation of the flash memory. during pr ocessing, the interrupt acknowledge time is delayed. set the overflow ti me and window size taking this delay into consideration. 3. if lsrosc = 0 (oscillation can be stopped by software), the count clock is not supplied to the watchdog timer in the halt and stop modes, rega rdless of the setting of bit 0 (lsrstop) of the internal oscillator m ode register (rcm). when 8-bit timer h1 operates with the internal low-speed oscillation clo ck, the count clock is supplied to 8-bit timer h1 even in the halt/stop mode. 4. be sure to clear bit 7 to 0. remarks 1. f rl : internal low-speed oscillation clock frequency 2. ( ): f rl = 264 khz (max.) chapter 23 option byte user?s manual u17553ej4v0ud 597 figure 23-1. format of option byte (2/2) address: 0081h/1081h notes 1, 2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 lvistart lvistart poc mode selection 0 1.59 v poc mode (default) 1 2.7 v/1.59 v poc mode notes 1. lvistart can only be written by using a dedicat ed flash memory programmer. it cannot be set during self-programming or boot swap operation during self -programming (at this time, 1.59 v poc mode (default) is set). however, because the value of 1081h is copied to 0081h during the boot swap operation, it is recommended to set a value that is the same as that of 0081h to 1081h when the boot swap function is used. 2. to change the setting for the poc mode, set the va lue to 0081h again after batch erasure (chip erasure) of the flash memory. the setting cannot be changed after t he memory of the specified block is erased. caution be sure to clea r bits 7 to 1 to ?0?. address: 0082h/1082h, 0083h/1083h note 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 note be sure to set 00h to 0082h and 0083h, as these addresses are reserved areas. also set 00h to 1082h and 1083h because 0082h and 0083h are switched with 1082h and 1083h when the boot swap operation is used. address: 0084h/1084h note 7 6 5 4 3 2 1 0 0 0 0 0 0 0 ocden1 ocden0 ocden1 ocden0 on-chip debug operation control 0 0 operation disabled 0 1 setting prohibited 1 0 operation enabled. does not erase data of the flash memory in case authentication of the on-chip debug security id fails. 1 1 operation enabled. erases data of the flash memory in case authentication of the on-chip debug security id fails. note to use the on-chip debug function, set 02h or 03h to 0084h. set a value that is the same as that of 0084h to 1084h because 0084h and 1084h are switched during the boot swap operation. remark for the on-chip debug security id, see chapter 25 on-chip debug function . chapter 23 option byte user?s manual u17553ej4v0ud 598 here is an example of description of t he software for setting the option bytes. opt cseg at 0080h option: db 30h ; enables watchdog timer operation (illegal access detection operation), ; window open period of watchdog timer: 50%, ; overflow time of watchdog timer: 2 10 /f rl , ; internal low-speed oscillator can be stopped by software. db 00h ; 1.59 v poc mode db 00h ; reserved area db 00h ; reserved area db 00h ; on-chip debug operation disabled remark referencing of the option byte is performed during reset processing. for the reset processing timing, see chapter 19 reset function . user?s manual u17553ej4v0ud 599 chapter 24 flash memory the 78k0/ff2 incorporates the flash memory to which a program can be written, er ased, and overwritten while mounted on the board. 24.1 internal memory size switching register the internal memory capacity can be selected using t he internal memory size s witching register (ims). ims is set by an 8-bit memory manipulation instruction. reset signal generation sets ims to cfh. caution be sure to set each produc t to the values shown in table 24-1 after a reset release. figure 24-1. format of internal memo ry size switching register (ims) address: fff0h after reset: cfh r/w symbol 7 6 5 4 3 2 1 0 ims ram2 ram1 ram0 0 rom3 rom2 rom1 rom0 ram2 ram1 ram0 internal hi gh-speed ram capacity selection 1 1 0 1024 bytes other than above setting prohibited rom3 rom2 rom1 rom0 internal rom capacity selection 1 1 0 0 48 kb 1 1 1 1 60 kb other than above setting prohibited caution to set the memory size, set im s and then ixs. set the memory si ze so that the internal rom and internal expansion ram areas do not overlap. table 24-1. internal memory si ze switching register settings flash memory versions (78k0/ff2) ims setting pd78f0891 cfh pd78f0892 cch note pd78f0893 cch note note the pd78f0892 and pd78f0893 have internal roms of 96 kb and 128 kb, respectively. however, the set values of the ims of these devices is the same as those for the 48 kb product because banks ar e used. for how to set the banks, see chapter 4 memory bank select function ( pd78f0892, 78f0893 only) . chapter 24 flash memory user?s manual u17553ej4v0ud 600 24.2 internal expansion ram size switching register the internal expansion ram capacity can be selected using the internal expansion ram size switching register (ixs). ixs is set by an 8-bit memory manipulation instruction. reset signal generation sets ixs to 0ch. caution be sure to set each product to the valu es shown in table 24-2 af ter a reset release. figure 24-2. format of internal expans ion ram size switching register (ixs) address: fff4h after reset: 0ch r/w symbol 7 6 5 4 3 2 1 0 ixs 0 0 0 ixram4 ixram3 ixram2 ixram1 ixram0 ixram4 ixram3 ixram2 ixram1 ixram0 internal expansion ram capacity selection 0 1 0 0 0 2048 bytes 0 0 1 0 0 4096 bytes 0 0 0 0 0 6144 bytes other than above setting prohibited caution to set memory size, set ims and then ixs. set memory size so that the inte rnal rom area and internal expansion ram area do not overlap. table 24-2. internal expansion ram size switching register settings flash memory versions (78k0/ff2) ixs setting pd78f0891 08h pd78f0892 04h pd78f0893 00h chapter 24 flash memory user?s manual u17553ej4v0ud 601 24.3 writing with flash memory programmer data can be written to the flash memory on-board or o ff-board, by using a dedicated flash memory programmer. (1) on-board programming the contents of the flash memory c an be rewritten after the 78k0/ff2 ha s been mounted on t he target system. the connectors that connect the dedicated flash memo ry programmer must be mounted on the target system. (2) off-board programming data can be written to the flash memory with a dedicat ed program adapter (fa series) before the 78k0/ff2 is mounted on the target system. remark the fa series is a product of na ito densei machida mfg. co., ltd. table 24-3. wiring between 78k0/ff2 a nd dedicated flash memory programmer pin configuration of dedicated flash memory programmer with csi10 with uart60 signal name i/o pin function pin name pin no. pin name pin no. si/rxd input receive signal so10/p12 52 txd60/p13 51 so/txd output transmit signal si10/rxd61/p11 53 rxd60/p14 50 sck output transfer clock sck10/txd61/p10 54 ? ? clk output clock to 78k0/ff2 ? note 1 ? note 2 note 2 /reset output reset signal reset 10 reset 10 flmd0 output mode signal flmd0 13 flmd0 13 v dd 19 v dd 19 ev dd 20 ev dd 20 v dd i/o v dd voltage generation/ power monitoring av ref 59 av ref 59 v ss 17 v ss 17 ev ss 18 ev ss 18 gnd ? ground av ss 60 av ss 60 notes 1. only the internal high-speed oscillation clock (f rh ) can be used when csi10 is used. 2. only the x1 clock (f x ) or external main system clock (f exclk ) can be used when uart60 is used. when using the clock output of the dedica ted flash memory programmer, pin connection varies depending on the type of the dedicated flash memory programmer used. ? pg-fp4, fl-pr4: connect clk of the programmer to exclk/x2/p122 (pin 14). ? pg-fpl3, fp-lite3: connect clk of the program mer to x1/p121 (pin 15), and connect its inverted signal to x2/exclk/p122 (pin 14). chapter 24 flash memory user?s manual u17553ej4v0ud 602 examples of the recommended connection when using the adapter for flash memory writing are shown below. figure 24-3. example of wiring ad apter for flash memory writing in 3-wire serial i/o (csi10) mode gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 gnd vdd vdd2 v dd (2.3 to 5.5 v) writer interface si so sck clk /reset flmd0 chapter 24 flash memory user?s manual u17553ej4v0ud 603 figure 24-4. example of wiri ng adapter for flash memory wr iting in uart (uart60) mode gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 gnd vdd vdd2 v dd (2.3 to 5.5 v) writer interface si so sck clk /reset flmd0 note note note the above figure illustrates an example of wiring when using the clock output from the pg-fp4 or fl-pr4. when using the clock output from the pg-fpl3 or fp-lite3, connect clk to x1/p121 (pin 15), and connect its inverted signal to x2/exclk/p122 (pin 14). chapter 24 flash memory user?s manual u17553ej4v0ud 604 24.4 programming environment the environment required for writing a program to the flash memory of the 78k0/ff2 is illustrated below. figure 24-5. environment for wr iting program to flash memory rs-232c host machine 78k0/ff2 v dd v ss reset csi10/uart60 dedicated flash memory programmer usb pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy xxxxx xxxxxx xxxx xxxx yyyy statve flmd0 a host machine that controls the dedicated flash memory programmer is necessary. to interface between the dedicated flash memory pr ogrammer and the 78k0/ff2, csi10 or uart60 is used for manipulation such as writing and erasi ng. to write the flash memory off- board, a dedicated program adapter (fa series) is necessary. 24.5 communication mode communication between the dedicated flash memory progr ammer and the 78k0/ff2 is established by serial communication via csi10 or uart60 of the 78k0/ff2. (1) csi10 transfer rate: 2.4 khz to 2.5 mhz figure 24-6. communication with dedica ted flash memory programmer (csi10) 78k0/ff2 reset so10 si10 sck10 v dd gnd /reset si/rxd so/txd sck dedicated flash memory programmer pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xx x y yy xxxxx xxxxxx xxxx x x xx yyy y statve v dd /ev dd /av ref v ss /ev ss /av ss flmd0 flmd0 chapter 24 flash memory user?s manual u17553ej4v0ud 605 (2) uart60 transfer rate: 115200 bps figure 24-7. communication with dedica ted flash memory programmer (uart60) 78k0/ff2 v dd /ev dd /av ref v ss /ev ss /av ss reset txd60 rxd60 v dd gnd /reset si/rxd so/txd dedicated flash memory programmer pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x xx y y y xxxxx xxxxxx xxxx x x x x yy yy statve flmd0 flmd0 exclk note clk note note the above figure illustrates an example of wiring when using the clock output from the pg-fp4 or fl-pr4. when using the clock output from the pg-fpl3 or fp-lite3, connect clk to x1/p121 (pin 15), and connect its inverted signal to x2/exclk/p122 (pin 14). x1 clk x2 the dedicated flash memory programmer generates the fo llowing signals for the 78k0/ff2. for details, refer to the user?s manual for the pg-fp4 , fl-pr4, pg-fpl3, or fp-lite3. table 24-4. pin connection dedicated flash memory programmer 78k0/ff2 connection signal name i/o pin function pin name csi10 uart60 flmd0 output mode signal flmd0 v dd i/o v dd voltage generation/power monitoring v dd , ev dd , av ref gnd ? ground v ss , ev ss , av ss clk output clock output to 78k0/ff2 note 1 note 2 { note 1 /reset output reset signal reset si/rxd input receive signal so10/txd60 so/txd output transmit signal si10/rxd60 sck output transfer clock sck10 notes 1. only the x1 clock (f x ) or external main system clock (f exclk ) can be used when uart60 is used. when using the clock output of the dedica ted flash memory programmer, pin connection varies depending on the type of the dedicated flash memory programmer used. ? pg-fp4, fl-pr4: connect clk of the programmer to exclk/x2/p122 (pin 14). ? pg-fpl3, fp-lite3: connect clk of the program mer to x1/p121 (pin 15), and connect its inverted signal to x2/exclk/p122 (pin 14). 2. only the internal high-speed oscillation clock (f rh ) can be used when csi10 is used. remark : be sure to connect the pin. { : the pin does not have to be connected if the signal is generated on the target board. : the pin does not have to be connected. chapter 24 flash memory user?s manual u17553ej4v0ud 606 24.6 connection of pins on board to write the flash memory on-board, connectors that connect the dedicat ed flash memory programmer must be provided on the target system. first provide a function that selects the no rmal operation mode or flash memory programming mode on the board. when the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after re set. therefore, if the external device does not recognize t he state immediately after reset, the pins must be handled as described below. 24.6.1 flmd0 pin in the normal operation mode, 0 v is input to the flmd 0 pin. in the flash memory programming mode, the v dd write voltage is supplied to the flmd0 pin. an flmd0 pin connection example is shown below. figure 24-8. flmd0 pin connection example 78k0/ff2 flmd0 10 k (recommended) dedicated flash memory programmer connection pin 24.6.2 serial interface pins the pins used by each serial interface are listed below. table 24-5. pins used by each serial interface serial interface pins used csi10 so10, si10, sck10 uart60 txd60, rxd60 to connect the dedicated flash memory programmer to the pins of a serial interface that is connected to another device on the board, care must be exer cised so that signals do not collide or that the other device does not malfunction. chapter 24 flash memory user?s manual u17553ej4v0ud 607 (1) signal collision if the dedicated flash memory programmer (output) is connec ted to a pin (input) of a serial interface connected to another device (output), signal collision ta kes place. to avoid this collision, either isolate the connection with the other device, or make the other device go into an output high-impedance state. figure 24-9. signal collision (i nput pin of serial interface) input pin signal collision dedicated flash memory programmer connection pin other device output pin in the flash memory programming mode, the signal output by the device collides with the signal sent from the dedicated flash memory programmer. therefore, isolate the signal of the other device. 78k0/ff2 (2) malfunction of other device if the dedicated flash memory programmer (output or input) is connected to a pin (input or output) of a serial interface connected to another device (input), a signal ma y be output to the other devic e, causing the device to malfunction. to avoid this malfunction, is olate the connection with the other device. figure 24-10. malfunction of other device pin dedicated flash memory programmer connection pin other device input pin if the signal output by the 78k0/ff2 in the flash memory programming mode affects the other device, isolate the signal of the other device. pin dedicated flash memory programmer connection pin other device input pin if the signal output by the dedicated flash memory programmer in the flash memory programming mode affects the other device, isolate the signal of the other device. 78k0/ff2 78k0/ff2 chapter 24 flash memory user?s manual u17553ej4v0ud 608 24.6.3 reset pin if the reset signal of the dedicated flash memory programm er is connected to the reset pin that is connected to the reset signal generator on the board, signal collision takes pl ace. to prevent this col lision, isolate the connection with the reset signal generator. if the reset signal is input from the user system whil e the flash memory programming mode is set, the flash memory will not be correctly programmed. do not input any signal other than the reset signal of the dedicated flash memory programmer. figure 24-11. signal collision (reset pin) reset dedicated flash memory programmer connection signal reset signal generator signal collision output pin in the flash memory programming mode, the signal output by the reset signal generator collides with the signal output by the dedicated flash memory programmer. therefore, isolate the signal of the reset signal generator. 78k0/ff2 24.6.4 port pins when the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately afte r reset. if external devices connected to the ports do not recognize the port status immediately after reset, the port pin must be connected to v dd or v ss via a resistor. 24.6.5 regc pin connect the regc pin to gnd via a capacitor (0.47 to 1 f: recommended) in the same manner as during normal operation. 24.6.6 other signal pins connect x1 and x2 in the same status as in t he normal operation mode when using the on-board clock. to input the operating clock from the dedicated flas h memory programmer, however, connect as follows. ? pg-fp4, fl-pr4: connect clk of the programmer to exclk/x2/p122. ? pg-fpl3, fp-lite3: connect clk of the progra mmer and x1/p121, and connect its inverted signal to x2/exclk/p122. cautions 1. only the internal high-speed oscillation clock (f rh ) can be used when csi10 is used. 2. only the x1 clock (f x ) or external main system clock (f exclk ) can be used when uart60 is used. 3. connect p31/intp2/ti002 and p121/x1 as fo llows when writing the flash memory with a flash memory programmer. ? p31/intp2/ti002: connect to ev ss via a resistor (10 k : recommended). ? p121/x1: when using this pin as a port, connect it to v ss via a resistor (10 k : recommended) (in the input mode) or leave it open (in the output mode). the above connection is no t necessary when writing the flash memory by means of self programming. chapter 24 flash memory user?s manual u17553ej4v0ud 609 24.6.7 power supply to use the supply voltage output of the flash memory programmer, connect the v dd pin to v dd of the flash memory programmer, and the v ss pin to gnd of the flash memory programmer. to use the on-board supply voltage, connect in compliance with the normal operation mode. however, be sure to connect the v dd and v ss pins to v dd and gnd of the flash memory programmer to use the power monitor function with the flash memory progra mmer, even when using the on-board supply voltage. supply the same other power supplies (ev dd , ev ss , av ref , and av ss ) as those in the normal operation mode. chapter 24 flash memory user?s manual u17553ej4v0ud 610 24.7 programming method 24.7.1 controlling flash memory the following figure illustrates the proc edure to manipulate the flash memory. figure 24-12. flash memory manipulation procedure start selecting communication mode manipulate flash memory end? yes flmd0 pulse supply no end flash memory programming mode is set 24.7.2 flash memory programming mode to rewrite the contents of the flash me mory by using the dedicated flash memory programmer, set the 78k0/ff2 in the flash memory programming mode. to set the mode, set the flmd0 pin to v dd and clear the reset signal. change the mode by using a jumper when writing the flash memory on-board. figure 24-13. flash memory programming mode v dd reset 5.5 v 0 v v dd 0 v flash memory programming mode flmd0 flmd0 pulse v dd 0 v table 24-6. relationship between flmd0 pi n and operation mode after reset release flmd0 operation mode 0 normal operation mode v dd flash memory programming mode chapter 24 flash memory user?s manual u17553ej4v0ud 611 24.7.3 selecting communication mode in the 78k0/ff2, a communication mode is selected by inpu tting pulses (up to 8 pulses) to the flmd0 pin after the dedicated flash memory programming mode is entered. these flmd0 pulses are generated by the flash memory programmer. the following table shows the relationship between the number of pulses and communication modes. table 24-7. communication modes standard setting note 1 communication mode port speed frequency multiply rate pins used peripheral clock number of flmd0 pulses uart-ext-osc f x 0 uart (uart60) uart-ext-fp4ck 115200 bps note 2 2 to 20 mhz note 3 txd60, rxd60 f exclk 3 3-wire serial i/o (csi10) csi-internal-osc 2.4 khz to 2.5 mhz ? 1.0 so10, si10, sck10 f rh 8 notes 1. selection items for standard settings on gu i of the flash memory programmer. 2. because factors other than the baud rate error, such as the signal waveform slew, also affect uart communication, thoroughly evaluate the slew as well as the baud rate error. 3. the possible setting range differs depending on the voltage. for details, refer to the chapter of electrical specifications. caution when uart60 is select ed, the receive clock is calculated based on the reset command sent from the dedicated flash memory programmer a fter the flmd0 pulse has been received. remark f x : x1 clock f exclk : external main system clock f rh : internal high-speed oscillation clock chapter 24 flash memory user?s manual u17553ej4v0ud 612 24.7.4 communication commands the 78k0/ff2 communicates with the dedicated flash memo ry programmer by using commands. the signals sent from the flash memory programmer to the 78k0/ff2 are called commands, and the signals s ent from the 78k0/ff2 to the dedicated flash memory programmer are called response. figure 24-14. communication commands 78k0/ff2 command response dedicated flash memor y p ro g rammer pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xx x y y y xxxxx xxxxxx xxxx xx x x y y y y s tat v e the flash memory control commands of the 78k0/ff2 are listed in the t able below. all these commands are issued from the programmer and the 78k0/ff2 perform proc essing corresponding to the respective commands. table 24-8. flash memory control commands classification command name function verify verify compares the contents of a specified area of the flash memory with data transmitted from the programmer. chip erase erases the entire flash memory. erase block erase erases a specified area in the flash memory. blank check block blank check checks if a specified block in the flash memory has been correctly erased. write programming writes data to a sp ecified area in the flash memory. status gets the current operating status (status data). silicon signature gets 78k0/fx2 information (such as the part number and flash memory configuration). version get gets the 78k0/fx2 version and firmware version. getting information checksum gets the checksum data for a specified area. security security set sets security information. reset used to detect synchronization status of communication. others oscillating frequency set specifies an oscillation frequency. the 78k0/ff2 return a response for the command issued by the dedicated flash memory programmer. the response names sent from t he 78k0/ff2 are listed below. table 24-9. response names command name function ack acknowledges command/data. nak acknowledges illegal command/data. chapter 24 flash memory user?s manual u17553ej4v0ud 613 24.8 security settings the 78k0/ff2 supports a security functi on that prohibits rewriting the user program written to the internal flash memory, so that the program cannot be changed by an unauthorized person. the operations shown below can be perfor med using the security set command. the security setting is valid when the programming mode is set next. ? disabling batch erase (chip erase) execution of the block erase and batch erase (chip eras e) commands for entire blocks in the flash memory is prohibited by this setting during on-board/off-board prog ramming. once execution of the batch erase (chip erase) command is prohibited, all of the prohibition settings (including prohibition of batch erase (chip erase)) can no longer be cancelled. caution after the security setting for the batch erase is set, erasure ca nnot be performed for the device. in addition, even if a write command is executed, data different from that which has already been written to the flash memory cannot be wr itten, because th e erase command is disabled. ? disabling block erase execution of the block erase command fo r a specific block in the flash memo ry is prohibited during on-board/off- board programming. however, blocks can be erased by means of self programming. ? disabling write execution of the write and block erase commands for entire blocks in the flash memory is prohibited during on- board/off-board programming. however, blocks can be written by means of self programming. ? disabling rewriting boot cluster 0 execution of the batch erase (chi p erase) command, block erase command, and write command on boot cluster 0 (0000h to 0fffh) in the flash memo ry is prohibited by this setting. caution if a security setting that rewrites boot cluster 0 has been applied, boot cl uster 0 of that device will not be rewritten. the batch erase (chip erase), block eras e, write commands, and rewriting boot cluster 0 are enabled by the default setting when the flash memory is shipped. security can be set by on-board/off-board programming and self programming. each security setting can be used in combination. prohibition of erasing blocks and wr iting is cleared by ex ecuting the batch erase (chip erase) command. table 24-10 shows the relationship bet ween the erase and write commands when the 78k0/ff2 security function is enabled. chapter 24 flash memory user?s manual u17553ej4v0ud 614 table 24-10. relationship between enabling security function and command (1) during on-board/off-board programming executed command valid security batch erase (chip erase) block erase write prohibition of batch erase (c hip erase) cannot be erased in batch can be performed note . prohibition of block erase can be performed. prohibition of writing can be erased in batch. blocks cannot be erased. cannot be performed. prohibition of rewriting boot cluster 0 cannot be erased in batch boot cluster 0 cannot be erased. boot cluster 0 cannot be written. note confirm that no data has been wri tten to the write area. because dat a cannot be erased after batch erase (chip erase) is prohibited, do not wr ite data if the data has not been erased. (2) during self programming executed command valid security block erase write prohibition of batch erase (chip erase) prohibition of block erase prohibition of writing blocks can be erased. can be performed. prohibition of rewriting boot cluster 0 boot cluster 0 cannot be erased. boot cluster 0 cannot be written. table 24-11 shows how to perform security settings in each programming mode. table 24-11. setting security in each programming mode (1) on-board/off-board programming security security setting how to disable security setting prohibition of batch erase (chip er ase) cannot be disabled after set. prohibition of block erase prohibition of writing execute batch erase (chip erase) command prohibition of rewriting boot cluster 0 set via gui of dedicated flash memory programmer, etc. cannot be disabled after set. (2) self programming security security setting how to disable security setting prohibition of batch erase (chip er ase) cannot be disabled after set. prohibition of block erase prohibition of writing execute batch erase (chip erase) command during on-board/off-board programming (cannot be disabled during self programming) prohibition of rewriting boot cluster 0 set by using information library. cannot be disabled after set. chapter 24 flash memory user?s manual u17553ej4v0ud 615 24.9 processing time for each command when pg-fp4 is used (reference) the following table shows the processing time for eac h command (reference) when the pg-fp4 is used as a dedicated flash memory programmer. table 24-12. processing time for each co mmand when pg-fp4 is used (reference) ? pd78f0893 (internal rom capacity: 128 kb) port: uart-ext-fp4ck (external main system clock (f exclk )), speed: 115,200 bps command of pg-fp4 port: csi-internal-osc (internal high-speed oscillation clock (f rh )), speed: 2.5 mhz frequency: 2.0 mhz frequency: 20 mhz signature 0.5 s (typ.) 0.5 s (typ.) 0.5 s (typ.) blankcheck 1 s (typ.) 1 s (typ.) 1 s (typ.) erase 1.5 s (typ.) 1.5 s (typ.) 1.5 s (typ.) program 9.5 s (typ.) 18 s (typ.) 18 s (typ.) verify 4.5 s (typ.) 13.5 s (typ.) 13.5 s (typ.) e.p.v 11 s (typ.) 19.5 s (typ.) 19.5 s (typ.) checksum 1 s (typ.) 1 s (typ.) 1 s (typ.) security 0.5 s (typ.) 0.5 s (typ.) 0.5 s (typ.) chapter 24 flash memory user?s manual u17553ej4v0ud 616 24.10 flash memory programming by self-programming the 78k0/ff2 supports a self-programmi ng function that can be used to rewr ite the flash memory via a user program. because this function allows a user application to rewrite the flash memory by using the 78k0/ff2 self- programming library, it can be used to upgrade the program in the field. if an interrupt occurs during self-programming, self -programming can be temporarily stopped and interrupt servicing can be executed. to execute interrupt servicing, restore the normal operation mode after self-programming has been stopped, and execute t he ei instruction. after the self-pr ogramming mode is later restored, self- programming can be resumed. remark for details of the self-programming function and the 78k0/ff2 self-programming library, refer to a separate document to be published (document name: 78k0/fx2 applic ation note, release schedule: pending). cautions 1. the self-programming function cannot be used when the cpu ope rates with the subsystem clock. 2. input a high level to the fl md0 pin during self-programming. 3. be sure to execute the di instru ction before starting self-programming. the self-programming function checks the interrupt request fl ags (if0l, if0h, if1l, and if1h). if an interrupt request is generated, self-progr amming is stopped. 4. self-programming is also st opped by an interrupt request that is not masked even in the di status. to prevent this, mask the interrupt by using the interrupt mask flag registers (mk0l, mk0h, mk1l, and mk1h). 5. self-programming is executed with the intern al high-speed oscillati on clock. if the cpu operates with the x1 clock or external main syst em clock, the oscillation stabilization wait time of the internal high-speed oscilla tion clock elapses dur ing self-programming. (cautions 6 and 7 are listed on the next page.) chapter 24 flash memory user?s manual u17553ej4v0ud 617 cautions 6. allocate the entry program for self-p rogramming in the common area of 0000h to 7fffh. figure 24-15. operation mode and memory map for se lf-programming ( pd78f0893) memory bank 1 memory bank 4 memory bank 3 memory bank 5 memory bank 2 normal mode flash memory (common area) 0000h 8000h 7fffh ffffh fb00h faffh c000h bfffh f800h f7ffh e000h dfffh ff00h feffh internal high- speed ram internal expansion ram sfr reserved flash memory control firmware rom disable accessing flash memory (memory bank 0) memory bank 1 memory bank 4 memory bank 3 memory bank 5 memory bank 2 self-programming mode flash memory (common area) 0000h 8000h 7fffh ffffh fb00h faffh c000h bfffh f800h f7ffh fa00h f9ffh fa00h f9ffh e000h dfffh ff00h feffh internal high- speed ram internal expansion ram sfr reserved afcan area afcan area reserved reserved flash memory control firmware rom disable accessing enable accessing instructions can be fetched from common area and selected memory bank. instructions can be fetched from common area and firmware rom. 7. if the flash memory size is 96 kb or 128 kb, specify a flash real address, instead of a cpu address, as a flash write/erase address. table 24-13. correspondence among bank numbers, cpu addresses, and flash real addresses (a) pd78f0892 bank no. cpu address real address of flash memory ? 0000h to 7fffh (common area) 00000h to 07fffh 0 08000h to 0bfffh 1 0c000h to 0ffffh 2 10000h to 13fffh 3 8000h to bfffh 14000h to 17fffh 4 or more setting prohibited (b) pd78f0893 bank no. cpu address real address of flash memory ? 0000h to 7fffh (common area) 00000h to 07fffh 0 08000h to 0bfffh 1 0c000h to 0ffffh 2 10000h to 13fffh 3 14000h to 17fffh 4 18000h to 1bfffh 5 8000h to bfffh 1c000h to 1ffffh 6 or more setting prohibited chapter 24 flash memory user?s manual u17553ej4v0ud 618 the following figure illustrates a flow of rewriting the fl ash memory by using a self programming sample library. figure 24-16. flow of self-pr ogramming (rewriting flash memory) start of self programming flashstart flmd0 pin low level high level normal completion? yes no setting operating environment flashenv checkflmd flashblockblankcheck erased? yes yes no flashblockerase normal completion? flashwordwrite normal completion? flashblockverify normal completion? flashend flmd0 pin high level low level end of self programming yes yes no no no chapter 24 flash memory user?s manual u17553ej4v0ud 619 the following table shows the processing time and interrupt re sponse time for the self programming sample library. table 24-14. processing time and interrupt respon se time for self programming sample library (1/4) (1) when internal high-speed oscillation clock is u sed and entry ram is located outside short direct addressing range processing time ( s) normal model of c compiler static model of c compiler/assembler interrupt response time ( s) library name min. max. min. max. min. max. self programming start library 4.25 ? ? initialize library 977.75 ? ? mode check library 753.875 753.125 ? ? block blank check library 12770.875 12765.875 391.25 1300.5 block erase library 36909.5 356318 36904.5 356296.25 389.25 1393.5 word write library 1214 (1214.375) 2409 (2409.375) 1207 (1207.375) 2402 (2402.375) 394.75 1289.5 program verify library 25618.875 25613.875 390.25 1324.5 self programming end library 4.25 ? ? get information library (option value: 03h) 871.25 (871.375) 866 (866.125) ? ? get information library (option value: 04h) 863.375 (863.5) 858.125 (858.25) ? ? get information library (option value: 05h) 1024.75 (1043.625) 1037.5 (1038.375) ? ? set information library 105524.75 790809.375 105523.75 790808.375 387 852.5 eeprom write library 1496.5 (1496.875) 2691.5 (2691.875) 1489.5 (1489.875) 2684.5 (2684.875) 399.75 1395.5 remark the value in the parentheses indicates the value when a write start address struct ure is located at a place other than the internal high-speed ram. chapter 24 flash memory user?s manual u17553ej4v0ud 620 table 24-14. processing time and interrupt respon se time for self programming sample library (2/4) (2) when internal high-speed oscillation clock is used and entry ram is located in short direct addressing range (fe20h) processing time ( s) normal model of c compiler static model of c compiler/assembler interrupt response time ( s) library name min. max. min. max. min. max. self programming start library 4.25 ? ? initialize library 443.5 ? ? mode check library 219.625 218.875 ? ? block blank check library 12236.625 12231.625 81.25 727.5 block erase library 36363.25 355771.75 36358.25 355750 79.25 820.5 word write library 679.75 (680.125) 1874.75 (1875.125) 672.75 (673.125) 1867.75 (1868.125) 84.75 716.5 program verify library 25072.625 25067.625 80.25 751.5 self programming end library 4.25 ? ? get information library (option value: 03h) 337 (337.125) 331.75 (331.875) ? ? get information library (option value: 04h) 329.125 (239.25) 323.875 (324) ? ? get information library (option value: 05h) 502.25 (503.125) 497 (497.875) ? ? set information library 104978.5 541143.125 104977.5 541142.125 77 279.5 eeprom write library 962.25 (962.625) 2157.25 (2157.625) 955.25 (955.625) 2150.25 (2150.625) 89.75 822.5 remark the value in the parentheses indicates the value when a write start address structure is located at a place other than the internal high-speed ram. chapter 24 flash memory user?s manual u17553ej4v0ud 621 table 24-14. processing time and interrupt respon se time for self programming sample library (3/4) (3) when high-speed system clock (x1 oscillation or external clock input) is used and entry ram is located outside short direct addressing range processing time ( s) normal model of c compiler static model of c compiler/assembler interrupt response time ( s) library name min. max. min. max. min. max. self programming start library 34/f xh ? ? initialize library 49/f xh + 485.8125 ? ? mode check library 35/f xh + 374.75 29/f xh + 374.75 ? ? block blank check library 174/f xh + 6382.0625 134/f xh + 6382.0625 18/f xh + 192 28/f xh + 698 block erase library 174/f xh + 31093.875 174/f xh + 298948.125 134/f xh + 31093.875 134/f xh + 298948.125 18/f xh + 186 28/f xh + 745 word write library 318 (321)/f xh + 644.125 318 (321)/f xh + 1491.625 262 (265)/f xh + 644.125 262 (265)/f xh + 1491.625 22/f xh + 189 28/f xh + 693 program verify library 174/f xh + 13448.5625 134/f xh + 13448.5625 18/f xh + 192 28/f xh + 709 self programming end library 34/f xh ? ? get information library (option value: 03h) 171 (172)/f xh + 432.4375 129 (130)/f xh + 432.4375 ? ? get information library (option value: 04h) 181 (182)/f xh + 427.875 139 (140)/f xh + 427.875 ? ? get information library (option value: 05h) 404 (411)/f xh + 496.125 362 (369)/f xh + 496.125 ? ? set information library 75/f xh + 79157.6875 75/f xh + 652400 67/f xh + 79157.6875 67/f xh + 652400 16/f xh + 190 28/f xh + 454 eeprom write library 318 (321)/f xh + 799.875 318 (321)/f xh + 1647.375 262 (265)/f xh + 799.875 262 (265)/f xh + 1647.375 22/f xh + 191 28/f xh + 783 remarks 1. the value in the parentheses indicates the value w hen a write start address stru cture is located at a place other than the internal high-speed ram. 2. f xh : high-speed system clock frequency chapter 24 flash memory user?s manual u17553ej4v0ud 622 table 24-14. processing time and interrupt respon se time for self programming sample library (4/4) (4) when high-speed system clock (x1 oscillation or external clock input) is used and entry ram is located in short direct addressing range (fe20h) processing time ( s) normal model of c compiler static model of c compiler/assembler interrupt response time ( s) library name min. max. min. max. min. max. self programming start library 34/f xh ? ? initialize library 49/f xh + 224.6875 ? ? mode check library 35/f xh + 113.625 29/f xh + 113.625 ? ? block blank check library 174/f xh + 6120.9375 134/f xh + 6120.9375 18/f xh + 55 28/f xh + 462 block erase library 174/f xh + 30820.75 174/f xh + 298675 134/f xh + 30820.75 134/f xh + 298675 18/f xh + 49 28/f xh + 509 word write library 318 (321)/f xh + 383 318 (321)/f xh + 1230.5 262 (265)/f xh + 383 262 (265)/f xh + 1230.5 22/f xh + 52 28/f xh + 457 program verify library 174/f xh + 13175.4375 134/f xh + 13175.4375 18/f xh + 55 28/f xh + 473 self programming end library 34/f xh ? ? get information library (option value: 03h) 171 (172)/f xh + 171.3125 129 (130)/f xh + 171.3125 ? ? get information library (option value: 04h) 181 (182)/f xh + 166.75 139 (140)/f xh + 166.75 ? ? get information library (option value: 05h) 404 (411)/f xh + 231.875 362 (369)/f xh + 231.875 ? ? set information library 75/f xh + 78884.5625 75/f xh + 527566.875 67/f xh + 78884.5625 67/f xh + 527566.875 16/f xh +53 28/f xh +218 eeprom write library 318 (321)/f xh + 538.75 318 (321)/f x h + 1386.25 262 (265)/f xh + 538.75 262 (265)/f xh + 1386.25 22/f xh +54 28/f xh +547 remarks 1. the value in the parentheses indicates the value w hen a write start address stru cture is located at a place other than the internal high-speed ram. 2. f xh : high-speed system clock frequency chapter 24 flash memory user?s manual u17553ej4v0ud 623 24.10.1 registers used fo r self-programming function the following three registers are used for the self-programming function. ? flash-programming mode control register (flpmc) ? flash protect command register (pfcmd) ? flash status register (pfs) (1) flash-programming mode control register (flpmc) this register is used to enable or disable writing or erasing of the flash memory and to set the operation mode during self-programming. the flpmc can be written only in a specific sequence (see 24.10.1 (2) flash protect command register (pfcmd) ) so that the application system does not stop inadvertently due to malfunction caused by noise or program hang-up. flpmc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 0xh note . note differs depending on the operation mode. ? user mode: 08h ? on-board mode: 0ch chapter 24 flash memory user?s manual u17553ej4v0ud 624 figure 24-17. format of flash-progra mming mode control register (flpmc) 0 symbol flpmc 0 0 0 fwedis fwepr flspm1 flspm0 address: ffc4h after reset: 0 h note 1 r/w note 2 selection of operation mode during self-programming normal mode access (fetch of a command, lead of data) is possible to all the address domains of a flash memory. self-programming mode execution"call #8100 h" of firmware is possible. access (lead of an instruction fetch and data) is possible to a flash memory . setting prohibited flspm1 note 4 0 0 1 1 flspm0 note 4 0 1 1 0 fwedis 0 control of flash memory writing/erasing writing/erasing enabled note 3 writing/erasing disabled 1 status of flmd0 pin low level high level note 3 fwepr 0 1 notes 1. differs depending on the operation mode. ? user mode: 08h ? on-board mode: 0ch 2. bit 2 (fwepr) is read-only. 3. for actual writing/erasing, the flmd0 pin must be high (fwepr = 1), as well as fwedis = 0. fwedis fwepr enable or disable of flash memory writing/erasing 0 1 writing/erasing enabled other than above writing/erasing disabled 4. the user rom (flash memory) or fi rmware rom can be selected by flspm1 and flspm0, and the operation mode set on the application system by the mode pin or the self-programming mode can be selected. cautions 1. be sure to keep fwedis at 0 until writing or erasing of the flash memory is completed. 2. make sure that fwedis = 1 in the normal mode. 3. manipulate flspm1 and flspm0 after execution br anches to the internal ram. the address of the flash memory is specified by an address signal from the cpu when flspm1 = 0 or the set value of the firmware written when flspm1 = 1. in the on-board mode, the specifications of flspm1 and flspm0 are ignored. chapter 24 flash memory user?s manual u17553ej4v0ud 625 (2) flash protect command register (pfcmd) if the application system stops inadver tently due to malfunction caused by noise or program hang-up, an operation to write the flash programmi ng mode control register (flpmc) may have a serious effect on the system. pfcmd is used to protect flpmc from being written, so that the application system does not stop inadvertently. writing flpmc is enabled only when a write operation is performed in the following specific sequence. <1> write a specific value to pfcmd (pfcmd = a5h) <2> write the value to be set to fl pmc (writing in this step is invalid) <3> write the inverted value of the value to be set to flpmc <4> write the value to be set to flpmc (writing in this step is valid) this rewrites the value of the register, so that the register cannot be written illegally. occurrence of an illegal store operation can be checked by bit 0 (fprerr) of the flash status register (pfs). a5h must be written to pfcmd each time the value of flpmc is changed. pfcmd can be set by an 8-bit memory manipulation instruction. reset signal generation makes this register undefined. figure 24-18. format of flash protect command register (pfcmd) reg7 symbol pfcmd reg6 reg5 reg4 reg3 reg2 reg1 reg0 address: ffc0h after reset: undefined w (3) flash status register (pfs) if data is not written to the flash programming mode contro l register (flpmc), which is protected, in the correct sequence (writing the flash protect command register (p fcmd)), flpmc is not written and a protection error occurs. if this happens, bit 0 of pfs (fprerr) is set to 1. this bit is a cumulative fl ag. after checking fprerr, clear it by writing 0 to it. pfs can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 24-19. format of flash status register (pfs) 0 symbol pfs 0 0 0 0 0 0 fprerr address: ffc2h after reset: 00h r/w chapter 24 flash memory user?s manual u17553ej4v0ud 626 the operating conditions of the fprerr flag are as follows. chapter 24 flash memory user?s manual u17553ej4v0ud 627 24.11 boot swap function if rewriting the boot area has failed dur ing self-programming due to a power fa ilure or some other cause, the data in the boot area may be lost and the pr ogram may not be restarted by resetting. the boot swap function is used to avoid this problem. before erasing boot cluster 0 note , which is a boot program area, by self-p rogramming, write a new boot program to boot cluster 1 in advance. when the program has been correctly written to boot cluster 1, swap this boot cluster 1 and boot cluster 0 by using the set information function of the firmw are of the 78k0/ff2, so that boot cluster 1 is used as a boot area. after that, erase or write the or iginal boot program area, boot cluster 0. as a result, even if a power failure occurs while the bo ot programming area is being rewritten, the program is executed correctly because it is booted from boot cluster 1 to be swapped when the program is reset and started next. if the program has been correctly written to boot cluster 0, restore the original bo ot area by using the set information function of the firmware of the 78k0/ff2. note a boot cluster is a 4 kb area and boot clusters 0 and 1 are swapped by the boot swap function. boot cluster 0 (0000h to 0fffh ): original boot program area boot cluster 1 (1000h to 1fffh): area subject to boot swap function figure 24-20. boot swap function boot program (boot cluster 0) new boot program (boot cluster 1) user program self-programming to boot cluster 1 self-programming to boot cluster 0 execution of boot swap by firmware execution of boot swap by firmware user program boot program (boot cluster 0) user program new boot program (boot cluster 1) new boot program (boot cluster 0) user program new boot program (boot cluster 1) new boot program (boot cluster 0) user program new boot program (boot cluster 1) boot program (boot cluster 0) user program xxxxh xxxxh 2000h 0000h 1000h 2000h 0000h 1000h boot boot boot boot boot chapter 24 flash memory user?s manual u17553ej4v0ud 628 figure 24-21. example of executing boot swapping boot cluster 1 booted by boot cluster 0 booted by boot cluster 1 booted by boot cluster 0 block number erasing block 4 boot cluster 0 program program boot program 1000h 0000h 1000h 0000h 0000h 1000h erasing block 5 writing blocks 5 to 7 boot swap boot swap canceled 3 2 1 0 7 6 5 4 boot program boot program boot program program program program program boot program 3 2 1 0 7 6 5 4 boot program boot program boot program program program boot program 3 2 1 0 7 6 5 4 boot program boot program boot program program erasing block 6 erasing block 7 program boot program 3 2 1 0 7 6 5 4 boot program boot program boot program boot program 3 2 1 0 7 6 5 4 boot program boot program boot program boot program 3 2 1 0 7 6 5 4 boot program boot program boot program new boot program new boot program new boot program new boot program boot program 3 2 1 0 7 6 5 4 boot program boot program boot program new boot program new boot program new boot program new boot program erasing block 0 erasing block 1 erasing block 2 erasing block 3 3 2 1 0 7 6 5 4 boot program boot program boot program new boot program new boot program new boot program new boot program 3 2 1 0 7 6 5 4 boot program boot program new boot program new boot program new boot program new boot program 3 2 1 0 7 6 5 4 boot program new boot program new boot program new boot program new boot program 3 2 1 0 7 6 5 4 new boot program new boot program new boot program new boot program writing blocks 0 to 3 3 2 1 0 7 6 5 4 new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program 3 2 1 0 7 6 5 4 new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program user?s manual u17553ej4v0ud 629 chapter 25 on-chip debug function 25.1 outline of functions the 78k0/ff2 uses the v dd , flmd0, reset, x1 (or p31), x2 (or p32), and v ss pins to communicate with the host machine via an on-chip debug emulator (qb-78k0mini). whether x1 and p31, or x2 and p32 are used can be selected. caution do not use this product fo r mass production after the on-chip debug function has been used because its reliability cannot be guaranteed, due to issues with respect to the number of times the flash memory can be rewritten. nec el ectronics does not accept complaints concerning when use this product for mass production afte r the on-chip debug function has been used. chapter 25 on-chip debug function user?s manual u17553ej4v0ud 630 25.2 connection with minicube in order to connect qb-78k0mini, it is necessary to mo unt the connector for emulator connection, and the circuit for connection on a target system. the connector for ocd (a two-row 2.54 pitch type connector, with reverse-insertion blocker) is described below. ? recommended connectors: (straight) hif3fc-10pa-2. 54dsa (manufactured by hirose electric co., ltd.) (right angle) hif3fc-10pa-2.54ds (manuf actured by hirose electric co., ltd.)) pin no. name in/out remark 1 reset_in in target reset input signal 2 reset_out out reset signal output to target device 3 flmd0 out output signal note used to control on-chip debugging functions 4 v dd _in in this signal is used to generate an interface output signal when the target system?s v dd is detected. 5 x2 in/out bidirectional signal used for data communications 6 gnd ? connected to gnd. 7 x1 out output signal used for clock supply 8 gnd ? connected to gnd. 9 reserved ? open 10 reserved ? open note flmd0 is at high level during on-chip debugging. figure 25-1. connector pin layout (top view) 10-pin general-purpose connector target system top view 2 9 10 7 8 5 6 3 4 1 chapter 25 on-chip debug function user?s manual u17553ej4v0ud 631 25.3 connection circuit examples the following are examples of circuits required when connecting the qb-78k0mini to the target system. figure 25-2. connection circuit exam ple (when qb-78k0mini is not used) v dd target device qb-78k0mini target connector p31 flmd0 x1 x2 target reset reset in x2 x1 flmd0 reset v dd reset out gnd shorted by jumper gnd note note note make pull-down resistor 470 or more (10 k : recommended). figure 25-3. connection circuit example (whe n using qb-78k0mini: x1 and x2 are used) v dd target device p31 flmd0 x1 x2 target reset reset in x2 x1 flmd0 reset v dd reset out gnd oscillator is deleted qb-78k0mini target connector gnd note note note make pull-down resistor 470 or more (10 k : recommended). cautions 1. input the clock from th e x1 pin during on-chip debugging. 2. control the x1 and x2 pins by externally pulling down the p31 pin or by using an external circuit using the p130 pin (that outputs a low level when the device is reset). chapter 25 on-chip debug function user?s manual u17553ej4v0ud 632 figure 25-4. connection circuit example (when using qb-78k0mini: ports 31 and 32 are used) qb-78k0mini target connector v dd target device p32 flmd0 p31 x2 target reset reset in x2 x1 flmd0 reset v dd reset out gnd x1 gnd note note note make pull-down resistor 470 or more (10 k : recommended). connect the flmd0 pin as follows when performing se lf programming by means of on-chip debugging. figure 25-5. connection of flmd0 pin for self programming by means of on-chip debugging qb-78k0mini target connector flmd0 flmd0 target device port 1 k (recommended) 10 k (recommended) chapter 25 on-chip debug function user?s manual u17553ej4v0ud 633 25.4 on-chip debug security id the 78k0/ff2 has an on-chip debug operation cont rol flag in the flash memory at 0084h (see chapter 23 option byte ) and an on-chip debug security id setting area at 0085h to 008eh. when the boot swap function is used, also set a value that is the same as that of 1084h and 1085h to 108eh in advance, because 0084h, 0085h to 008eh and 1084h, and 1085h to 108eh are switched. for details on the on-chip debug security id, refer to the qb-78k0mini user?s manual (u17029e) . table 25-1. on-chip debug security id address on-chip debug security id 0085h to 008eh 1085h to 108eh any id code of 10 bytes 25.5 restrictions and caut ions on on-chip debug function when setting to on-chip debugging mode via the normal port, without using pins x1 and x2, two of the user ports will be unavailable for use. a high-level signal is always output from to the flmd0 pi n during emulation when self-writing. be sure to connect a pull-down resistor to the flmd0 pin, and manipulate th is pin based on high/high impedance levels, rather than on high/low levels, when using ports for manipulation. in order to realize on-chip debug function, use the following user resource. (a) flash memory area { addresses 0x02 and 0x03 { addresses 0x7e and 0x7f (when using a software break) { address 0x84 { addresses 0x85 to 0x8e { addresses 0x8f to 0x18f: standard value of program (+256 bytes when using pseudo real-time ram monitor function) (when using a device with 10 or more sfrs the c an be accessed in 16-bit units: +n (the number of exceeding registers x 6 bytes)) (b) internal extended ram area { addresses 0xf7f0 to 0xf7ff (when using pseudo real-time ram monitor function) (c) internal high-speed ram area { 7 bytes as stack area: standard value of stack (+2 bytes when using software breaks) (+7 bytes when using pseudo real-time ram monitor function) for details, refer to the qb-78k0mini user's manual (u17029e). user?s manual u17553ej4v0ud 634 chapter 26 instruction set this chapter lists each instruction set of 78k0/ff2 in t able form. for details of eac h operation and operation code, refer to the separate document 78k/0 series instructions user?s manual (u12326e) . 26.1 conventions used in operation list 26.1.1 operand identifier s and specification methods operands are written in the ?operand? column of each instruction in ac cordance with the specification method of the instruction operand identifier (refer to the assembler s pecifications for details). when there are two or more methods, select one of them. upper case letters and the sym bols #, !, $ and [ ] are keywords and must be written as they are. each symbol has the following meaning. ? #: immediate data specification ? !: absolute address specification ? $: relative address specification ? [ ]: indirect address specification in the case of immediate data, describe an appropriate num eric value or a label. when using a label, be sure to write the #, !, $, and [ ] symbols. for operand register identifiers r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for specification. table 26-1. operand identifi ers and specification methods identifier specification method r rp sfr sfrp x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7), ax (rp0), bc (rp1), de (rp2), hl (rp3) special function register symbol note special function register symbol (16-bit manipulatable register even addresses only) note saddr saddrp fe20h to ff1fh immediate data or labels fe20h to ff1fh immediate data or labels (even address only) addr16 addr11 addr5 0000h to ffffh immediate data or labels (only even addresses for 16-bit da ta transfer instructions) 0800h to 0fffh immediate data or labels 0040h to 007fh immediate data or labels (even address only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label rbn rb0 to rb3 note addresses from ffd0h to ffdfh c annot be accessed with these operands. remark for special function register symbols, see table 3-7. special function register list . chapter 26 instruction set user?s manual u17553ej4v0ud 635 26.1.2 description of operation column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag rbs: register bank select flag ie: interrupt request enable flag ( ): memory contents indicated by addre ss or register contents in parentheses x h , x l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive logical sum (exclusive or) ?? : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 26.1.3 description of flag operation column (blank): not affected 0: cleared to 0 1: set to 1 : set/cleared according to the result r: previously saved value is restored chapter 26 instruction set user?s manual u17553ej4v0ud 636 26.2 operation list clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy r, #byte 2 4 ? r byte saddr, #byte 3 6 7 (saddr) byte sfr, #byte 3 ? 7 sfr byte a, r note 3 1 2 ? a r r, a note 3 1 2 ? r a a, saddr 2 4 5 a (saddr) saddr, a 2 4 5 (saddr) a a, sfr 2 ? 5 a sfr sfr, a 2 ? 5 sfr a a, !addr16 3 8 9 a (addr16) !addr16, a 3 8 9 (addr16) a psw, #byte 3 ? 7 psw byte a, psw 2 ? 5 a psw psw, a 2 ? 5 psw a a, [de] 1 4 5 a (de) [de], a 1 4 5 (de) a a, [hl] 1 4 5 a (hl) [hl], a 1 4 5 (hl) a a, [hl + byte] 2 8 9 a (hl + byte) [hl + byte], a 2 8 9 (hl + byte) a a, [hl + b] 1 6 7 a (hl + b) [hl + b], a 1 6 7 (hl + b) a a, [hl + c] 1 6 7 a (hl + c) mov [hl + c], a 1 6 7 (hl + c) a a, r note 3 1 2 ? a ? r a, saddr 2 4 6 a ? (saddr) a, sfr 2 ? 6 a ? (sfr) a, !addr16 3 8 10 a ? (addr16) a, [de] 1 4 6 a ? (de) a, [hl] 1 4 6 a ? (hl) a, [hl + byte] 2 8 10 a ? (hl + byte) a, [hl + b] 2 8 10 a ? (hl + b) 8-bit data transfer xch a, [hl + c] 2 8 10 a ? (hl + c) notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. chapter 26 instruction set user?s manual u17553ej4v0ud 637 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy rp, #word 3 6 ? rp word saddrp, #word 4 8 10 (saddrp) word sfrp, #word 4 ? 10 sfrp word ax, saddrp 2 6 8 ax (saddrp) saddrp, ax 2 6 8 (saddrp) ax ax, sfrp 2 ? 8 ax sfrp sfrp, ax 2 ? 8 sfrp ax ax, rp note 3 1 4 ? ax rp rp, ax note 3 1 4 ? rp ax ax, !addr16 3 10 12 ax (addr16) movw !addr16, ax 3 10 12 (addr16) ax 16-bit data transfer xchw ax, rp note 3 1 4 ? ax ? rp a, #byte 2 4 ? a, cy a + byte saddr, #byte 3 6 8 (saddr), cy (saddr) + byte a, r note 4 2 4 ? a, cy a + r r, a 2 4 ? r, cy r + a a, saddr 2 4 5 a, cy a + (saddr) a, !addr16 3 8 9 a, cy a + (addr16) a, [hl] 1 4 5 a, cy a + (hl) a, [hl + byte] 2 8 9 a, cy a + (hl + byte) a, [hl + b] 2 8 9 a, cy a + (hl + b) add a, [hl + c] 2 8 9 a, cy a + (hl + c) a, #byte 2 4 ? a, cy a + byte + cy saddr, #byte 3 6 8 (saddr), cy (saddr) + byte + cy a, r note 4 2 4 ? a, cy a + r + cy r, a 2 4 ? r, cy r + a + cy a, saddr 2 4 5 a, cy a + (saddr) + cy a, !addr16 3 8 9 a, cy a + (addr16) + c a, [hl] 1 4 5 a, cy a + (hl) + cy a, [hl + byte] 2 8 9 a, cy a + (hl + byte) + cy a, [hl + b] 2 8 9 a, cy a + (hl + b) + cy 8-bit operation addc a, [hl + c] 2 8 9 a, cy a + (hl + c) + cy notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. only when rp = bc, de or hl 4. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. chapter 26 instruction set user?s manual u17553ej4v0ud 638 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy a, #byte 2 4 ? a, cy a ? byte saddr, #byte 3 6 8 (saddr), cy (saddr) ? byte a, r note 3 2 4 ? a, cy a ? r r, a 2 4 ? r, cy r ? a a, saddr 2 4 5 a, cy a ? (saddr) a, !addr16 3 8 9 a, cy a ? (addr16) a, [hl] 1 4 5 a, cy a ? (hl) a, [hl + byte] 2 8 9 a, cy a ? (hl + byte) a, [hl + b] 2 8 9 a, cy a ? (hl + b) sub a, [hl + c] 2 8 9 a, cy a ? (hl + c) a, #byte 2 4 ? a, cy a ? byte ? cy saddr, #byte 3 6 8 (saddr), cy (saddr) ? byte ? cy a, r note 3 2 4 ? a, cy a ? r ? cy r, a 2 4 ? r, cy r ? a ? cy a, saddr 2 4 5 a, cy a ? (saddr) ? cy a, !addr16 3 8 9 a, cy a ? (addr16) ? cy a, [hl] 1 4 5 a, cy a ? (hl) ? cy a, [hl + byte] 2 8 9 a, cy a ? (hl + byte) ? cy a, [hl + b] 2 8 9 a, cy a ? (hl + b) ? cy subc a, [hl + c] 2 8 9 a, cy a ? (hl + c) ? cy a, #byte 2 4 ? a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 2 4 ? a a r r, a 2 4 ? r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 a a (addr16) a, [hl] 1 4 5 a a [hl] a, [hl + byte] 2 8 9 a a [hl + byte] a, [hl + b] 2 8 9 a a [hl + b] 8-bit operation and a, [hl + c] 2 8 9 a a [hl + c] notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. chapter 26 instruction set user?s manual u17553ej4v0ud 639 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy a, #byte 2 4 ? a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 2 4 ? a a r r, a 2 4 ? r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 a a (addr16) a, [hl] 1 4 5 a a (hl) a, [hl + byte] 2 8 9 a a (hl + byte) a, [hl + b] 2 8 9 a a (hl + b) or a, [hl + c] 2 8 9 a a (hl + c) a, #byte 2 4 ? a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 2 4 ? a a r r, a 2 4 ? r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 a a (addr16) a, [hl] 1 4 5 a a (hl) a, [hl + byte] 2 8 9 a a (hl + byte) a, [hl + b] 2 8 9 a a (hl + b) xor a, [hl + c] 2 8 9 a a (hl + c) a, #byte 2 4 ? a ? byte saddr, #byte 3 6 8 (saddr) ? byte a, r note 3 2 4 ? a ? r r, a 2 4 ? r ? a a, saddr 2 4 5 a ? (saddr) a, !addr16 3 8 9 a ? (addr16) a, [hl] 1 4 5 a ? (hl) a, [hl + byte] 2 8 9 a ? (hl + byte) a, [hl + b] 2 8 9 a ? (hl + b) 8-bit operation cmp a, [hl + c] 2 8 9 a ? (hl + c) notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. chapter 26 instruction set user?s manual u17553ej4v0ud 640 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy addw ax, #word 3 6 ? ax, cy ax + word subw ax, #word 3 6 ? ax, cy ax ? word 16-bit operation cmpw ax, #word 3 6 ? ax ? word mulu x 2 16 ? ax a x multiply/ divide divuw c 2 25 ? ax (quotient), c (remainder) ax c r 1 2 ? r r + 1 inc saddr 2 4 6 (saddr) (saddr) + 1 r 1 2 ? r r ? 1 dec saddr 2 4 6 (saddr) (saddr) ? 1 incw rp 1 4 ? rp rp + 1 increment/ decrement decw rp 1 4 ? rp rp ? 1 ror a, 1 1 2 ? (cy, a 7 a 0 , a m ? 1 a m ) 1 time rol a, 1 1 2 ? (cy, a 0 a 7 , a m + 1 a m ) 1 time rorc a, 1 1 2 ? (cy a 0 , a 7 cy, a m ? 1 a m ) 1 time rolc a, 1 1 2 ? (cy a 7 , a 0 cy, a m + 1 a m ) 1 time ror4 [hl] 2 10 12 a 3 ? 0 (hl) 3 ? 0 , (hl) 7 ? 4 a 3 ? 0 , (hl) 3 ? 0 (hl) 7 ? 4 rotate rol4 [hl] 2 10 12 a 3 ? 0 (hl) 7 ? 4 , (hl) 3 ? 0 a 3 ? 0 , (hl) 7 ? 4 (hl) 3 ? 0 adjba 2 4 ? decimal adjust accumulator after addition bcd adjustment adjbs 2 4 ? decimal adjust accumulator after subtract cy, saddr.bit 3 6 7 cy (saddr.bit) cy, sfr.bit 3 ? 7 cy sfr.bit cy, a.bit 2 4 ? cy a.bit cy, psw.bit 3 ? 7 cy psw.bit cy, [hl].bit 2 6 7 cy (hl).bit saddr.bit, cy 3 6 8 (saddr.bit) cy sfr.bit, cy 3 ? 8 sfr.bit cy a.bit, cy 2 4 ? a.bit cy psw.bit, cy 3 ? 8 psw.bit cy bit manipulate mov1 [hl].bit, cy 2 6 8 (hl).bit cy notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. chapter 26 instruction set user?s manual u17553ej4v0ud 641 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy cy, saddr.bit 3 6 7 cy cy saddr.bit) cy, sfr.bit 3 ? 7 cy cy sfr.bit cy, a.bit 2 4 ? cy cy a.bit cy, psw.bit 3 ? 7 cy cy psw.bit and1 cy, [hl].bit 2 6 7 cy cy (hl).bit cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 ? 7 cy cy sfr.bit cy, a.bit 2 4 ? cy cy a.bit cy, psw.bit 3 ? 7 cy cy psw.bit or1 cy, [hl].bit 2 6 7 cy cy (hl).bit cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 ? 7 cy cy sfr.bit cy, a.bit 2 4 ? cy cy a.bit cy, psw. bit 3 ? 7 cy cy psw.bit xor1 cy, [hl].bit 2 6 7 cy cy (hl).bit saddr.bit 2 4 6 (saddr.bit) 1 sfr.bit 3 ? 8 sfr.bit 1 a.bit 2 4 ? a.bit 1 psw.bit 2 ? 6 psw.bit 1 set1 [hl].bit 2 6 8 (hl).bit 1 saddr.bit 2 4 6 (saddr.bit) 0 sfr.bit 3 ? 8 sfr.bit 0 a.bit 2 4 ? a.bit 0 psw.bit 2 ? 6 psw.bit 0 clr1 [hl].bit 2 6 8 (hl).bit 0 set1 cy 1 2 ? cy 1 1 clr1 cy 1 2 ? cy 0 0 bit manipulate not1 cy 1 2 ? cy cy notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. chapter 26 instruction set user?s manual u17553ej4v0ud 642 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy call !addr16 3 7 ? (sp ? 1) (pc + 3) h , (sp ? 2) (pc + 3) l , pc addr16, sp sp ? 2 callf !addr11 2 5 ? (sp ? 1) (pc + 2) h , (sp ? 2) (pc + 2) l , pc 15 ? 11 00001, pc 10 ? 0 addr11, sp sp ? 2 callt [addr5] 1 6 ? (sp ? 1) (pc + 1) h , (sp ? 2) (pc + 1) l , pc h (00000000, addr5 + 1), pc l (00000000, addr5), sp sp ? 2 brk 1 6 ? (sp ? 1) psw, (sp ? 2) (pc + 1) h , (sp ? 3) (pc + 1) l , pc h (003fh), pc l (003eh), sp sp ? 3, ie 0 ret 1 6 ? pc h (sp + 1), pc l (sp), sp sp + 2 reti 1 6 ? pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3 rrr call/return retb 1 6 ? pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3 rrr psw 1 2 ? (sp ? 1) psw, sp sp ? 1 push rp 1 4 ? (sp ? 1) rp h , (sp ? 2) rp l , sp sp ? 2 psw 1 2 ? psw (sp), sp sp + 1 r r r pop rp 1 4 ? rp h (sp + 1), rp l (sp), sp sp + 2 sp, #word 4 ? 10 sp word sp, ax 2 ? 8 sp ax stack manipulate movw ax, sp 2 ? 8 ax sp !addr16 3 6 ? pc addr16 $addr16 2 6 ? pc pc + 2 + jdisp8 unconditional branch br ax 2 8 ? pch a, pc l x bc $addr16 2 6 ? pc pc + 2 + jdisp8 if cy = 1 bnc $addr16 2 6 ? pc pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 ? pc pc + 2 + jdisp8 if z = 1 conditional branch bnz $addr16 2 6 ? pc pc + 2 + jdisp8 if z = 0 notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. chapter 26 instruction set user?s manual u17553ej4v0ud 643 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy saddr.bit, $addr16 3 8 9 pc pc + 3 + jdisp8 if(saddr.bit) = 1 sfr.bit, $addr16 4 ? 11 pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 ? pc pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr16 3 ? 9 pc pc + 3 + jdisp8 if psw.bit = 1 bt [hl].bit, $addr16 3 10 11 pc pc + 3 + jdisp8 if (hl).bit = 1 saddr.bit, $addr16 4 10 11 pc pc + 4 + jdisp8 if(saddr.bit) = 0 sfr.bit, $addr16 4 ? 11 pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 ? pc pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr16 4 ? 11 pc pc + 4 + jdisp8 if psw. bit = 0 bf [hl].bit, $addr16 3 10 11 pc pc + 3 + jdisp8 if (hl).bit = 0 saddr.bit, $addr16 4 10 12 pc pc + 4 + jdisp8 if(saddr.bit) = 1 then reset(saddr.bit) sfr.bit, $addr16 4 ? 12 pc pc + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit a.bit, $addr16 3 8 ? pc pc + 3 + jdisp8 if a.bit = 1 then reset a.bit psw.bit, $addr16 4 ? 12 pc pc + 4 + jdisp8 if psw.bit = 1 then reset psw.bit btclr [hl].bit, $addr16 3 10 12 pc pc + 3 + jdisp8 if (hl).bit = 1 then reset (hl).bit b, $addr16 2 6 ? b b ? 1, then pc pc + 2 + jdisp8 if b 0 c, $addr16 2 6 ? c c ? 1, then pc pc + 2 + jdisp8 if c 0 conditional branch dbnz saddr, $addr16 3 8 10 (saddr) (saddr) ? 1, then pc pc + 3 + jdisp8 if(saddr) 0 sel rbn 2 4 ? rbs1, 0 n nop 1 2 ? no operation ei 2 ? 6 ie 1(enable interrupt) di 2 ? 6 ie 0(disable interrupt) halt 2 6 ? set halt mode cpu control stop 2 6 ? set stop mode notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. chapter 26 instruction set user?s manual u17553ej4v0ud 644 26.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz second operand first operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] [hl + b] [hl + c] $addr16 1 none a add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc r mov mov add addc sub subc and or xor cmp inc dec b, c dbnz sfr mov mov saddr mov add addc sub subc and or xor cmp mov dbnz inc dec !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl + byte] [hl + b] [hl + c] mov x mulu c divuw note except ?r = a? chapter 26 instruction set user?s manual u17553ej4v0ud 645 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw second operand first operand #word ax rp note sfrp saddrp !addr16 sp none ax addw subw cmpw movw xchw movw movw movw movw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr second operand first operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none a.bit mov1 bt bf btclr set1 clr1 sfr.bit mov1 bt bf btclr set1 clr1 saddr.bit mov1 bt bf btclr set1 clr1 psw.bit mov1 bt bf btclr set1 clr1 [hl].bit mov1 bt bf btclr set1 clr1 cy mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 set1 clr1 not1 chapter 26 instruction set user?s manual u17553ej4v0ud 646 (4) call instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz second operand first operand ax !addr16 !addr11 [addr5] $addr16 basic instruction br call br callf callt br bc bnc bz bnz compound instruction bt bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop user?s manual u17553ej4v0ud 647 chapter 27 electrical specific ations ((a) grade products) 27.1 absolute maximum ratings absolute maximum ratings (t a = 25 c) (1/2) parameter symbol conditions ratings unit v dd ? 0.5 to +6.5 v ev dd ? 0.5 to +6.5 v v ss ? 0.5 to +0.3 v ev ss ? 0.5 to +0.3 v av ref ? 0.5 to v dd +0.3 note v supply voltage av ss ? 0.5 to +0.3 v regc pin input voltage v regc ? 0.5 to +3.6 and v dd v v i1 p00, p01, p05, p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p76, p80 to p87, p90 top97, p120, p131, p132, x1, x2, xt1, xt2, reset ,flmd0 ? 0.3 to v dd +0.3 note v input voltage v i2 p60 to p63 n-ch open drain ? 0.3 to +6.5 v output voltage v o ? 0.3 to v dd +0.3 note v analog input voltage v an ani0 to ani15 ? 0.3 to av ref +0.3 note and ? 0.3 to v dd +0.3 note v per pin p00, p01, p05, p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p76, p120, p130 to p132 ? 10 ma p05, p06, p10 to p17, p30 to p33, p50 to p57, p64 to p67, p70 to p76, p130 ? 55 ma i oh total of all pins ? 80 ma p00, p01, p40 to p47, p120, p131, p132 ? 25 ma per pin ? 0.5 i oh2 total of all pins p80 to p87, p90 to p97 ? 2 ma per pin ? 1 output current, high i oh3 total of all pins p121 to p124 ? 4 ma note must be 6.5 v or lower. caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute m aximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alte rnate-function pins are the same as those of port pins. chapter 27 electrical specifications ((a) grade products) user?s manual u17553ej4v0ud 648 absolute maximum ratings (t a = 25 c) (2/2) parameter symbol conditions ratings unit per pin p00, p01, p05, p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p60 to p67, p70 to p76, p120, p130 to p132 30 ma p05, p06, p10 to p17, p30 to p33, p50 to p57, p60 to p67, p70 to p76, p130 140 ma i ol total of all pins 200 ma p00, p01, p40 to p47, p120, p131, p132 60 ma per pin 1 i ol2 all pins p80 to p87, p90 to p97 5 ma per pin 4 output current, low i ol3 all pins p121 to p124 10 ma in normal operation mode ? 40 to +85 operating ambient temperature t a in flash memory programming mode ? 40 to +85 c storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute m aximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alte rnate-function pins are the same as those of port pins. chapter 27 electrical specifications ((a) grade products) user?s manual u17553ej4v0ud 649 27.2 oscillator characteristics (1) main system clock (crystal/c eramic) oscillator characteristics (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit 4.0 v v dd 5.5 v 4.0 20 2.7 v v dd < 4.0 v 4.0 10 ceramic resonator c1 x2 x1 v ss c2 x1 clock oscillation frequency (f x ) note 1.8 v v dd < 2.7 v 4.0 5.0 mhz 4.0 v v dd 5.5 v 4.0 20 2.7 v v dd < 4.0 v 4.0 10 crystal resonator c1 x2 x1 v ss c2 x1 clock oscillation frequency (f x ) note 1.8 v v dd < 2.7 v 4.0 5.0 mhz note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. cautions 1. when using the x1 oscillator, wire as follo ws in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring leng th as short as possible. ? do not cross the wiring wi th the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as vss. ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. since the cpu is started by the 8 mhz inte rnal oscillator after rese t, check the oscillation stabilization time of the main syst em clock using the oscillation st abilization time counter status register (ostc). determine the oscillation stabiliz ation time of the ostc register and oscillation stabilization time select register (osts) after sufficiently evalua ting the oscillation stabilization time with the resonator to be used. remark for the resonator selection and oscillator const ant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. chapter 27 electrical specifications ((a) grade products) user?s manual u17553ej4v0ud 650 (2) on-chip internal oscillator characteristics (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) resonator parameter conditions min. typ. max. unit 2.7 v v dd 5.5 v 7.6 8 8.4 mhz rsts = 1 1.8 v v dd < 2.7 v 7.6 8 10.4 mhz 8 mhz internal oscillator internal high-speed oscillation clock frequency (f rh ) note rsts = 0 2.48 5.6 9.86 mhz 240 khz internal oscillator 2.7 v v dd 5.5 v 216 240 264 khz internal low-speed oscillation clock frequency (f rl ) 1.8 v v dd < 2.7 v 192 240 264 khz note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. remark rsts: bit 7 of the internal oscillation mode register (rcm) (3) subsystem clock oscillator characteristics (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit crystal resonator xt1 v ss xt2 c4 c3 rd xt1 clock oscillation frequency (f xt ) note 32 32.768 35 khz note indicates only oscillator c haracteristics. refer to ac characteristics for instruction execution time. cautions 1. when using the xt1 osc illator, wire as follows in the area en closed by the bro ken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as vss. ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 2. the subsystem clock oscill ator is designed as a low-amplit ude circuit for reducing power consumption, and is more prone to malfunction due to noise than the high-speed system clock oscillator. particular care is therefore required with the wir ing method when the subsystem clock is used. remark for the resonator selection and oscillator const ant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. chapter 27 electrical specifications ((a) grade products) user?s manual u17553ej4v0ud 651 27.3 dc characteristics dc characteristics (1/7) (t a = ? 40 to +85 c, 4.0 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit per pin for p00, p01, p05, p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p76, p120, p130 to p132 ? 3.0 ma total of pins note2 p05, p06, p10 to p17, p30 to p33, p50 to p57, p64 to p67, p70 to p76, p130 ? 18.0 ma total of pins note2 p00, p01, p40 to p47, p120, p131, p132 ? 12.0 ma output current, high note 1 i oh1 total of pins note2 ? 23.0 ma i oh2 per pin for p80 to p87, p90 to p97 av ref = v dd ? 100 a per pin for p121 to p124 per pin for p00, p01, p05, p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p76, p120, p130 to p132 8.5 ma per pin for p60 to p63 15 ma total of pins note2 p05, p06, p10 to p17, p30 to p33, p50 to p57, p60 to p67, p70 to p76, p130 45 ma total of pins note2 p00, p01, p40 to p47, p120, p131, p132 20 ma output current, low note3 i ol1 note3 total of pins note2 65 ma i ol2 per pin for p80 to p87, p90 to p97 av ref = v dd 400 a per pin for p121 to p124 notes 1. value of current at which the device operation is guaranteed even if the current flows from v dd to an output pin. 2. value of current at which the devic e operation is guaranteed even if the current flow s from an output pin to gnd. 3. specification under conditions where the duty fact or is 70% (time for which current is output is 0.7 t and time for which current is not output is 0.3 t, where t is a specific time). the total output current of the pins at a duty factor of other than 70% can be calculated by the following expression. ? where the duty factor of i oh is n%: total output current of pins = (i oh 0.7) / (n 0.01) chapter 27 electrical specifications ((a) grade products) user?s manual u17553ej4v0ud 652 dc characteristics (2/7) (t a = ? 40 to +85 c, 2.7 v v dd = ev dd < 4.0 v, v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit per pin for p00, p01, p05, p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p76, p120, p130 to p132 ? 2.5 ma total of pins note2 p05, p06, p10 to p17, p30 to p33, p50 to p57, p64 to p67, p70 to p76, p130 ? 15.0 ma total of pins note2 p00, p01, p40 to p47, p120, p131, p132 ? 7.0 ma output current, high note 1 i oh1 total of pins note2 ? 18.0 ma i oh2 per pin for p80 to p87, p90 to p97 av ref = v dd ? 100 a per pin for p121 to p124 per pin for p00, p01, p05, p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p60 to p67, p70 to p76, p120, p130 to p132 5.0 ma total of pins note2 p05, p06, p10 to p17, p30 to p33, p50 to p57, p60 to p67, p70 to p76, p130 35 ma total of pins note2 p00, p01, p40 to p47, p120, p131, p132 15 ma output current, low i ol1 note3 total of pins note2 50 ma i ol2 per pin for p80 to p87, p90 to p97 av ref = v dd 400 a per pin for p121 to p124 notes 1. value of current at which the device operation is guaranteed even if the current flows from v dd to an output pin. 2. value of current at which the devic e operation is guaranteed even if the current flow s from an output pin to gnd. 3. specification under conditions where the duty fact or is 70% (time for which current is output is 0.7 t and time for which current is not output is 0.3 t, where t is a specific time). the total output current of the pins at a duty factor of other than 70% can be calculated by the following expression. ? where the duty factor of i oh is n%: total output current of pins = (i oh 0.7) / (n 0.01) chapter 27 electrical specifications ((a) grade products) user?s manual u17553ej4v0ud 653 dc characteristics (3/7) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd < 2.7 v, v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit per pin for p00, p01, p05, p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p76, p120, p130 to p132 ? 1.0 ma total of pins note2 p05, p06, p10 to p17, p30 to p33, p50 to p57, p64 to p67, p70 to p76, p130 ? 10 ma total of pins note2 p00, p01, p40 to p47, p120, p131, p132 ? 5.0 ma output current, high note 1 i oh1 total of pins note2 ? 15 ma i oh2 per pin for p80 to p87, p90 to p97 av ref = v dd ? 100 a per pin for p121 to p124 per pin for p00, p01, p05, p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p60 to p67, p70 to p76, p120, p130 to p132 2.0 ma total of pins note2 p05, p06, p10 to p17, p30 to p33, p50 to p57, p60 to p67, p70 to p76, p130 20 ma total of pins note2 p00, p01, p40 to p47, p120, p131, p132 9 ma output current, low i ol1 note3 total of pins note2 29 ma i ol2 per pin for p80 to p87, p90 to p97 av ref = v dd 400 a per pin for p121 to p124 notes 1. value of current at which the device operation is guaranteed even if the current flows from v dd to an output pin. 2. value of current at which the devic e operation is guaranteed even if the current flow s from an output pin to gnd. 3. specification under conditions where the duty fact or is 70% (time for which current is output is 0.7 t and time for which current is not output is 0.3 t, where t is a specific time). the total output current of the pins at a duty factor of other than 70% can be calculated by the following expression. ? where the duty factor of i oh is n%: total output current of pins = (i oh 0.7) / (n 0.01) chapter 27 electrical specifications ((a) grade products) user?s manual u17553ej4v0ud 654 dc characteristics (4/7) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit v ih1 p12, p13, p15, p40 to p47, p50 to p57, p64 to p67, p70, p74, p121-p124 0.7v dd v dd v v ih2 p00, p01, p05, p06, p10, p11, p14, p16, p17, p30 to p33, p71 to p73, p75, p76, p120, p131, p132, reset, exclk, exclks 0.8v dd v dd v v ih3 p80 to p87, p90 to p97 av ref = v dd 0.7av ref av ref v input voltage, high v ih4 p60 to p63 0.7v dd 6.0 v v il1 p12, p13, p15, p40 to p47, p50 to p57, p60 to p67, p70, p74, p121 to p124 0 0.3v dd v v il2 p00, p01, p05, p06, p10, p11, p14, p16, p17, p30 to p33, p71, p72, p73, p75, p76, p120, p131, p132, reset, exclk, exclks 0 0.2v dd v input voltage, low v il3 p80 to p87, p90 to p97 av ref = v dd 0 0.3av ref v i oh = ? 3.0 ma 4.0 v v dd 5.5 v v dd ? 0.7 v i oh = ? 2.5 ma 2.7 v v dd < 4.0 v v dd ? 0.5 v v oh1 i oh = ? 1.0 ma p00, p01, p05, p06, p10 to p17, p30 to p33, p40 top47, p50 to p57, p64 to p67, p70 to p76, p120, p130 to p132 1.8 v v dd < 2.7 v v dd ? 0.5 v i oh = ? 100 a p80 to p87, p90 to p97 av ref = v dd v dd ? 0.5 v output voltage, high v oh2 p121 to p124 i ol = 8.5 ma 4.0 v v dd 5.5 v 0.7 v i ol = 5.0 ma 2.7 v v dd < 4.0 v 0.7 v i ol = 2.0 ma 1.8 v v dd < 2.7 v 0.5 v i ol = 1.0 ma 1.8 v v dd < 2.7 v 0.5 v v ol1 i ol = 0.5 ma p00, p01, p05, p06, p10 to p17, p30 to p33, p40 top47, p50 to p57, p64 to p67, p70 to p76, p120, p130 to p132 1.8 v v dd < 2.7 v 0.4 v p80 to p87, p90 to p97 av ref = v dd 0.4 v ol2 i ol = 400 a p121 to p124 v i ol = 15 ma p60 to p63 4.0 v v dd 5.5 v 2.0 v i ol = 5.0 ma 0.4 v i ol = 5.0 ma 2.7 v v dd < 4.0 v 0.6 v i ol = 3.0 ma 2.7 v v dd < 4.0 v 0.4 v output voltage, low v ol3 i ol = 2.0 ma 1.8 v v dd < 2.7 v 0.4 v remark unless specified otherwise, the charac teristics of alternate-function pins are the same as those of port pins. chapter 27 electrical specifications ((a) grade products) user?s manual u17553ej4v0ud 655 dc characteristics (5/7) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit i lih1 v i = v dd p00, p01, p05, p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p60 to p67, p70 to p76, p120, p131, p132, reset, flmd0 1 a i lih2 v i = av ref p80 to p87, p90 to p97 av ref = v dd 1 a i lih3 v i = v dd p121 to p124 i/o port mode 1 a input leakage current, high (x1, x2, xt1, xt2) osc port mode 20 a i lil1 v i = v ss p00, p01, p05, p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p60 to p67, p70 to p76, p120, p131, p132, reset, flmd0 ? 1 a i lil2 p80 to p87, p90 to p97 av ref = v dd ? 1 a i lil3 p121 to p124 i/o port mode ? 1 a input leakage current, low (x1, x2, xt1, xt2) osc port mode ? 20 a pull-up resistor r u v i = v ss 10 20 100 k flmd0 supply voltage v il in normal operation mode 0 0.2v dd v v ih in self programming mode 0.8 v dd v dd v remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. chapter 27 electrical specifications ((a) grade products) user?s manual u17553ej4v0ud 656 dc characteristics (6/7) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 2.3 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit square wave input 3.4 6.8 f xh = 20 mhz note 2 , v dd = 5.0 v resonator connection 4.7 8.2 ma square wave input 1.8 3.6 f xh = 10 mhz notes 2, 3 , v dd = 5.0 v resonator connection 2.5 4.7 ma square wave input 1.7 3.5 f xh = 10 mhz notes 2, 3 , v dd = 3.0 v resonator connection 2.4 4.0 ma square wave input 1.0 2.0 f xh = 5 mhz notes 2, 3 , v dd = 3.0 v resonator connection 1.4 2.4 ma square wave input 0.8 1.7 f xh = 5 mhz notes 2, 3 , v dd = 2.0 v resonator connection 1.1 1.9 ma f rh = 8 mhz note 4 , v dd = 5.0 v 1.5 2.7 ma square wave input 6 30 i dd1 operating mode f sub = 32.768 khz note 5 , v dd = 5.0 v resonator connection 15 35 a square wave input 1.0 3.9 f xh = 20 mhz note 2 , v dd = 5.0 v resonator connection 2.2 5.7 ma square wave input 0.6 2.0 f xh = 10 mhz notes 2, 3 , v dd = 5.0 v resonator connection 1.2 3.1 ma square wave input 0.3 1.0 f xh = 5 mhz notes 2, 3 , v dd = 3.0 v resonator connection 0.6 1.5 ma f rh = 8 mhz note 4 , v dd = 5.0 v 0.5 1.4 ma square wave input 3.0 27 i dd2 halt mode f sub = 32.768 khz note 5 , v dd = 5.0 v resonator connection 12 32 a supply current note 1 i dd3 note 6 stop mode v dd = 5.0 v 1 20 a notes 1. total current flowing into the internal power supply (v dd , ev dd ), including the peripheral operation current and the input leakage current flowing when the level of the input pin are fixed to v dd or v ss . however, the current flowing into the pull-up resistors and t he output current of the port is not included. 2. not including the operating current of the 8 mhz inte rnal oscillator, xt1 oscillation, 240 khz internal oscillator and the current flowing into the a/d converter, watchdog timer and lvi circuit. 3. when amph (bit 0 of clock operation mode select register (oscctl)) = 0. 4. not including the operating current of the x1 oscillation, xt1 oscillati on and 240 khz internal oscillator. not including the current flowing into the a/d conver ter, watchdog timer, lvi circuit and can controller. 5. not including the operating current of the x1 osc illation, 8 mhz internal oscillator and 240 khz internal oscillator, and the current flowing into the a/ d converter, watchdog timer and lvi circuit. 6. not including the operating current of the 240 khz in ternal oscillator and xt1 oscillation, and the current flowing into the a/d converter, watchdog timer and lvi circuit. remarks 1. f xh : high-speed system clock frequency (x1 clock oscill ation frequency or exte rnal main system clock frequency) 2. f rh : internal high-speed oscillation clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillat ion frequency or external subsystem clock frequency) chapter 27 electrical specifications ((a) grade products) user?s manual u17553ej4v0ud 657 dc characteristics (7/7) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 2.3 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit a/d converter operating current i adc note 1 adce = 1 0.86 1.9 ma watchdog timer operating current i wdt note2 during 240 khz internal low-spee d oscillation clock operation 5 10 a lvi operating current i lvi note 3 9 18 a notes 1. current flowing only to the a/d converter (avref-pin ). the current value of the 78k0/ff2 is the sum of i dd1 or i dd2 and i adc when the a/d converter operates in an operation mode or the halt mode. 2. current flowing only to the watchdog timer (v dd -pin) (including the operating current of the 240 khz internal oscillator). the current va lue of the 78k0/ff2 is the sum of i dd2 or i dd3 and iwdt when the watchdog timer operates in the halt or stop mode. 3. current flowing only to the lvi circuit (v dd -pin). the current value of the 78k0/ff2 is the sum of i dd2 or i dd3 and ilvi when the lvi circuit operat es in the halt or stop mode. chapter 27 electrical specifications ((a) grade products) user?s manual u17553ej4v0ud 658 27.4 ac characteristics (1) basic operation (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 0.1 8 s 2.7 v v dd < 4.0 v 0.2 8 s main system clock (f xp ) operation 1.8 v v dd < 2.7 v 0.4 note1 8 s instruction cycle (minimum instruction execution time) t cy subsystem clock (f sub ) operation 114 122 125 s 4.0 v v dd 5.5 v 20 2.7 v v dd < 4.0 v 10 f prs =f xh 1.8 v v dd < 2.7 v 5 mhz 2.7 v v dd 5.5 v 7.6 8.4 peripheral hardware clock frequency f prs f prs =f rh 1.8 v v dd < 2.7 v note2 7.6 10.4 mhz 4.0 v v dd 5.5 v 4.0 20 mhz 2.7 v v dd < 4.0 v 4.0 10 mhz external main system clock frequency f ext 1.8 v v dd < 2.7 v 4.0 5 mhz 4.0 v v dd 5.5 v 24 2.7 v v dd < 4.0 v 48 external clock input high level width, low level width f exth, f extl 1.8 v v dd < 2.7 v 96 ns external subsystem clock frequency f exts 32 32.768 35 khz external sub clock input high level width, low level width f extsh, f extsl 12 s 4.0 v v dd 5.5 v 2/f sam + 0.1 note3 s 2.7 v v dd < 4.0 v 2/f sam + 0.2 note3 s ti000, ti001, ti002, ti003, ti010, ti011 ti012, ti013 input high-level width, low-level width t tih0 , t til0 1.8 v v dd < 2.7 v 2/f sam + 0.5 note3 s 4.0 v v dd 5.5 v 10 mhz 2.7 v v dd < 4.0 v 10 mhz ti50, ti51 input frequency f ti5 1.8 v v dd < 2.7 v 5 mhz 4.0 v v dd 5.5 v 50 ns 2.7 v v dd < 4.0 v 50 ns ti50, ti51 input high-level width, low-level width t tih5 , t til5 1.8 v v dd < 2.7 v 100 ns 1 s interrupt input high-level width, low-level width t inih , t inil reset low-level width t rsl 10 s notes 1. 0.38 s when operating with the 8 mhz internal oscillator. 2. this spec is a definition of the main system clock. therefore, peripheral hardw are must use the clock of f rh /2 or less. (v dd = 1.8 v or less) 3. ti sampling with se lection count clock (f prs , f prs /4, f prs /256) using bits 0 and 1 (prm0n0, prm0n1) of prescaler mode registers 00 (prm0n). note that w hen selecting the ti0n0 valid edge as the count clock, f sam = f prs (n = 0, 1, 2, 3). chapter 27 electrical specifications ((a) grade products) user?s manual u17553ej4v0ud 659 t cy vs. v dd (main system clock operation) supply voltage v dd [v] cycle time t cy [ s] 5.0 1.0 2.0 0.4 0.2 0.1 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 5.5 1.8 20.0 guaranteed operation range 8.0 2.7 chapter 27 electrical specifications ((a) grade products) user?s manual u17553ej4v0ud 660 ac timing test points (excluding x1, xt1) 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd external clock input timing exclk 0.8v dd 0.2v dd 1/f ext t extl t exth 1/f exts t extsl t extsh exclks 0.8v dd 0.2v dd ti timing ti000, ti001, ti002, ti003, ti010, ti011, ti012, ti013 t til0 t tih0 ti50, ti51 1/f ti5 t til5 t tih5 interrupt request input timing intp0 to intp7 t intl t inth chapter 27 electrical specifications ((a) grade products) user?s manual u17553ej4v0ud 661 reset input timing reset t rsl (2) serial interface (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) (a) uart mode (uart6n, dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 625 kbps (b) 3-wire serial i/o mode (master m ode, sck1n... internal clock output) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 200 ns 2.7 v v dd < 4.0 v 400 ns sck1n cycle time t kcy1 1.8 v v dd < 2.7 v 600 ns 4.0 v v dd 5.5 v t kcy1 /2 ? 20 ns 2.7 v v dd < 4.0 v t kcy1 /2 ? 30 ns sck1n high-/low-level width note1 t kh1 , t kl1 1.8 v v dd < 2.7 v t kcy1 /2 ? 60 ns 4.0 v v dd 5.5 v 70 ns 2.7 v v dd < 4.0 v 100 ns si1n setup time (to sck1n ) t sik1 1.8 v v dd < 2.7 v 190 ns si1n hold time (from sck1n ) t ksi1 30 ns delay time from sck1n to so1n output t kso1 c = 50 pf note2 40 ns notes 1. it is value at the time of fx use. keep in mi nd that spec different at the time of fosc8 use. 2. c is the load capacitance of the sck1n and so1n output lines. (c) 3-wire serial i/o mode (slave mode , sck1n... external clock input) parameter symbol conditions min. typ. max. unit sck1n cycle time t kcy2 400 ns sck1n high-/low-level width t kh2 , t kl2 t kcy2 /2 ns si1n setup time (to sck1n ) t sik2 80 ns si1n hold time (from sck1n ) t ksi2 50 ns 4.0 v v dd 5.5 v 120 2.7 v v dd < 4.0 v 120 delay time from sck1n to so1n output t kso2 c = 50 pf note 1.8 v v dd < 2.7 v 180 ns note c is the load capacitance of the so1n output line. remark n = 0, 1 chapter 27 electrical specifications ((a) grade products) user?s manual u17553ej4v0ud 662 serial transfer timing 3-wire serial i/o mode: si1n so1n t kcym t klm t khm t sikm t ksim input data t ksom output data sck1n remark m = 1, 2 n = 0, 1 chapter 27 electrical specifications ((a) grade products) user?s manual u17553ej4v0ud 663 (3) can controller (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit transfer rate 1 mbps internal delay time t node 100 ns can internal clock ctxd pin (transfer data) crxd pin (receive data) t output t input note internal delay time (t node ) = internal transfer delay (t output ) + internal receive delay (t input ) note can internal clock (f can ): can baud rate clock image figure of internal delay 78k0/ff2 ctxd pin crxd pin can macro internal receive delay internal transfer delay chapter 27 electrical specifications ((a) grade products) user?s manual u17553ej4v0ud 664 (4) a/d converter characteristics (t a = ? 40 to +85 c, 2.3 v v dd = ev dd 5.5 v, 2.3 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution res 10 bit 4.0 v av ref 5.5 v 0.4 2.7 v av ref < 4.0 v 0.6 overall error notes 1, 2 a inl 2.3 v av ref < 2.7 v 1.2 %fsr 4.0 v av ref 5.5 v 6.1 36.7 2.7 v av ref < 4.0 v 12.2 36.7 conversion time t conv 2.3 v av ref < 2.7 v 27 66.6 s 4.0 v av ref 5.5 v 0.4 2.7 v av ref < 4.0 v 0.6 zero-scale error notes 1, 2 e zs 2.3 v av ref < 2.7 v 0.6 %fsr 4.0 v av ref 5.5 v 0.4 2.7 v av ref < 4.0 v 0.6 full-scale error notes 1, 2 e fs 2.3 v av ref < 2.7 v 0.6 %fsr 4.0 v av ref 5.5 v 2.5 2.7 v av ref < 4.0 v 4.5 integral non-linearity error note 1 i le 2.3 v av ref < 2.7 v 6.5 lsb 4.0 v av ref 5.5 v 1.5 2.7 v av ref < 4.0 v 2.0 differential non-linearity error note 1 d le 2.3 v av ref < 2.7 v 2.0 lsb analog input voltage v ain 2.3 v av ref 5.5 v av ss av ref v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. chapter 27 electrical specifications ((a) grade products) user?s manual u17553ej4v0ud 665 (5) poc circuit characteristics (t a = ? 40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage v poc0 1.44 1.59 1.74 v power supply rise time t pth v dd : 0 v v poc0 0.5 v/ms minimum pulse width t pw 200 s poc circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t pw t pth caution spec may change after device evaluation. chapter 27 electrical specifications ((a) grade products) user?s manual u17553ej4v0ud 666 (6) lvi circuit characteristics (t a = ? 40 to +85 c, v poc v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit v lvi0 4.14 4.24 4.34 v v lvi1 3.99 4.09 4.19 v v lvi2 3.83 3.93 4.03 v v lvi3 3.68 3.78 3.88 v v lvi4 3.52 3.62 3.72 v v lvi5 3.37 3.47 3.57 v v lvi6 3.22 3.32 3.42 v v lvi7 3.06 3.16 3.26 v v lvi8 2.91 3.01 3.11 v v lvi9 2.75 2.85 2.95 v v lvi10 2.60 2.70 2.80 v v lvi11 2.45 2.55 2.65 v v lvi12 2.29 2.39 2.49 v v lvi13 2.14 2.24 2.34 v v lvi14 1.98 2.08 2.18 v supply voltage level v lvi15 1.83 1.93 2.03 v external input pin note 1 ex lvi ex lvi < v dd , 1.8 v v dd 5.5 v 1.11 1.21 1.31 v detection voltage detection voltage on application of supply voltage vdd lvi lvistart (option bye) = 1 2.50 2.70 2.90 v minimum pulse width t lw 200 s operation stabilization wait time note 2 t lwait1 10 s notes 1. external input pin is alternate p120/intp pin. 2. time required from setting lvion to 1 to operation stabilization. remarks 1. v lvin ? 1 > v lvin (n = 1 to 15) 2. v poc < v lvim (v poc : power-on clear detection voltage, m = 0 to 15) lvi circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t lwait1 t lw lvion < -1 chapter 27 electrical specifications ((a) grade products) user?s manual u17553ej4v0ud 667 (7) power supply starting time (t a = ? 40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit starting maximum time to v dd min (1.8 v) note1 (v dd : 0 v 1.8 v) t pup1 lvi starting option invalid when pin reset intact 3.6 ms starting maximum time to v dd min (1.8 v) note1 (pin reset release v dd : 1.8 v) t pup2 lvi starting option invalid when pin reset use 1.9 ms notes 1. start a power supply in time shorter than this when lvi staring option invalid. 2. it is base on the spec of poc. 1.8 v 0 v poc t pup1 v dd 1.8 v 0 v poc t pup2 v dd reset pin pin reset intact pin reset use chapter 27 electrical specifications ((a) grade products) user?s manual u17553ej4v0ud 668 27.5 data retention characteristics data memory stop mode low supply vo ltage data retention characteristics (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.44 note 5.5 v note the value depends on the poc det ection voltage. when the voltage drop s, the data is retained until a poc reset is effected, but data is not re tained when a poc reset is effected. data retention timing v dddr data retention characteristics v dd stop instruction execution stop mode standby release signal (interrupt request) operation chapter 27 electrical specifications ((a) grade products) user?s manual u17553ej4v0ud 669 27.6 flash eeprom programming characteristics (1) basic characteristics (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit v dd supply current i dd f xp = 10 mhz (typ.), 20 mhz (max.) 4.5 11.0 ma all block t eraca 20 200 ms erase time notes 1, 2 block unit t erasa 20 200 ms write time (in 8-bit units) note 1 t wrwa 10 100 s number of rewrites per chip c erwr retention: 15 years 1 erase + 1 write after erase = 1 rewrite note 3 100 times notes 1. characteristic of the flash memory. for the char acteristic when a dedicated flash memory programmer, pg-fp4, is used and the rewrite ti me during self programming, 2. the prewrite time before erasure and the erase verify time (writeback time) are not included. 3. when a product is first written after shipment, ?erase write? and ?write only? are both taken as one rewrite. remark spec may change after device evaluation. user?s manual u17553ej4v0ud 670 chapter 28 electrical specifi cations ((a2) grade products) 28.1 absolute maximum ratings absolute maximum ratings (t a = 25 c) (1/2) parameter symbol conditions ratings unit v dd ? 0.5 to +6.5 v ev dd ? 0.5 to +6.5 v v ss ? 0.5 to +0.3 v ev ss ? 0.5 to +0.3 v av ref ? 0.5 to v dd +0.3 note v supply voltage av ss ? 0.5 to +0.3 v regc pin input voltage v regc ? 0.5 to +3.6 and v dd v v i1 p00, p01, p05, p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p76, p80 to p87, p90 to p97, p120, p131, p132, x1, x2, xt1, xt2, reset, flmd0 ? 0.3 to v dd +0.3 note v input voltage v i2 p60 to p63 n-ch open drain ? 0.3 to +6.5 v output voltage v o ? 0.3 to v dd +0.3 note v analog input voltage v an ani0 to ani15 ? 0.3 to av ref +0.3 note and ? 0.3 to v dd +0.3 note v per pin p00, p01, p05, p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p76, p120, p130, p131, p132 ? 10 ma p05, p06, p10 to p17, p30 to p33, p50 to p57, p64 to p67, p70 to p76, p130 ? 55 ma i oh total of all pins ? 80 ma p00, p01, p40 to p47, p120, p131, p132 ? 25 ma per pin ? 0.5 i oh2 total of all pins p80 to p87, p90 to p97 ? 2 ma per pin ? 1 output current, high i oh3 total of all pins p121 to p124 ? 4 ma note must be 6.5 v or lower. caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute m aximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alte rnate-function pins are the same as those of port pins. chapter 28 electrical specifications ((a2) grade products) user?s manual u17553ej4v0ud 671 absolute maximum ratings (t a = 25 c) (2/2) parameter symbol conditions ratings unit per pin p00, p01, p05, p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p60 to p67, p70 to p76, p120, p130, p131, p132 30 ma p05, p06, p10 to p17, p30 to p33, p50 to p57, p60 to p67, p70 to p76, p130 140 ma i ol total of all pins 200 ma p00, p01, p40 to p47, p120, p131, p132 60 ma per pin 1 i ol2 all pins p80 to p87, p90 to p97 5 ma per pin 4 output current, low i ol3 all pins p121 to p124 10 ma in normal operation mode ? 40 to +125 operating ambient temperature t a in flash memory programming mode ? 40 to +125 c storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute m aximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alte rnate-function pins are the same as those of port pins. chapter 28 electrical specifications ((a2) grade products) user?s manual u17553ej4v0ud 672 28.2 oscillator characteristics (1) main system clock (crystal/c eramic) oscillator characteristics (t a = ? 40 to +125 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit 4.0 v v dd 5.5 v 4.0 20 ceramic resonator c1 x2 x1 v ss c2 x1 clock oscillation frequency (f x ) note 2.7 v v dd < 4.0 v 4.0 10 mhz 4.0 v v dd 5.5 v 4.0 20 crystal resonator c1 x2 x1 v ss c2 x1 clock oscillation frequency (f x ) note 2.7 v v dd < 4.0 v 4.0 10 mhz note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. cautions 1. when using the x1 oscillator, wire as follo ws in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring leng th as short as possible. ? do not cross the wiring wi th the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the o scillator capacitor th e same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. since the cpu is started by the 8 mhz inte rnal oscillator after rese t, check the oscillation stabilization time of the main syst em clock using the oscillation st abilization time counter status register (ostc). determine the oscillation stabiliz ation time of the ostc register and oscillation stabilization time select register (osts) after sufficiently evalua ting the oscillation stabilization time with the resonator to be used. remark for the resonator selection and oscillator const ant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. chapter 28 electrical specifications ((a2) grade products) user?s manual u17553ej4v0ud 673 (2) on-chip internal oscillator characteristics (t a = ? 40 to +125 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) resonator parameter conditions min. typ. max. unit rsts = 1 2.7 v v dd 5.5 v 7.6 8 8.46 mhz 8 mhz internal oscillator internal high-speed oscillation clock frequency (f rh ) note rsts = 0 2.48 5.6 9.86 mhz 240 khz internal oscillator internal low-speed oscillation clock frequency (f rl ) 2.7 v v dd 5.5 v 216 240 264 khz note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. remark rsts: bit 7 of the internal oscillation mode register (rcm) (3) subsystem clock oscillator characteristics (t a = ? 40 to +125 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit crystal resonator xt1 v ss xt2 c4 c3 rd xt1 clock oscillation frequency (f xt ) note 32 32.768 35 khz note indicates only oscillator c haracteristics. refer to ac characteristics for instruction execution time. cautions 1. when using the xt1 osc illator, wire as follows in the area en closed by the bro ken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 2. the subsystem clock oscill ator is designed as a low-amplit ude circuit for reducing power consumption, and is more prone to malfunction due to noise than the high-speed system clock oscillator. particular care is therefore required with the wir ing method when the subsystem clock is used. remark for the resonator selection and oscillator const ant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. chapter 28 electrical specifications ((a2) grade products) user?s manual u17553ej4v0ud 674 28.3 dc characteristics dc characteristics (1/6) (t a = ? 40 to +125 c, 4.0 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit per pin for p00, p01, p05, p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p76, p120, p130 to p132 ? 1.5 ma total of pins note2 p05, p06, p10 to p17, p30 to p33, p50 to p57, p64 to p67, p70 to p76, p130 ? 10.0 ma total of pins note2 p00, p01, p40 to p47, p120, p131, p132 ? 6.0 ma output current, high note 1 i oh1 total of pins note2 ? 14.0 ma i oh2 per pin for p80 to p87, p90 to p97 av ref = v dd ? 100 a per pin for p121 to p124 per pin for p00, p01, p05, p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p76, p120, p130 to p132 4.0 ma per pin for p60 to p63 8.0 ma total of pins note2 p05, p06, p10 to p17, p30 to p33, p50 to p57, p60 to p67, p70 to p76, p130 20 ma total of pins note2 p00, p01, p40 to p47, p120, p131, p132 10 ma output current, low note3 i ol1 note3 total of pins note2 30 ma i ol2 per pin for p80 to p87, p90 to p97 av ref = v dd 400 a per pin for p121 to p124 notes 1. value of current at which the device operation is guaranteed even if the current flows from v dd to an output pin. 2. value of current at which the devic e operation is guaranteed even if the current flow s from an output pin to gnd. 3. specification under conditions where the duty fact or is 70% (time for which current is output is 0.7 t and time for which current is not output is 0.3 t, where t is a specific time). the total output current of the pins at a duty factor of other than 70% can be calculated by the following expression. ? where the duty factor of i oh is n%: total output current of pins = (i oh 0.7) / (n 0.01) chapter 28 electrical specifications ((a2) grade products) user?s manual u17553ej4v0ud 675 dc characteristics (2/6) (t a = ? 40 to +125 c, 2.7 v v dd = ev dd < 4.0 v, v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit per pin for p00, p01, p05, p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p76, p120, p130 to p132 ? 1.0 ma total of pins note2 p05, p06, p10 to p17, p30 to p33, p50 to p57, p64 to p67, p70 to p76, p130 ? 8.0 ma total of pins note2 p00, p01, p40 to p47, p120, p131, p132 ? 4.0 ma output current, high note 1 i oh1 total of pins note2 ? 12.0 ma i oh2 per pin for p80 to p87, p90 to p97 av ref = v dd ? 100 a per pin for p121 to p124 per pin for p00, p01, p05, p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p60 to p67, p70 to p76, p120, p130 to p132 2.0 ma total of pins note2 p05, p06, p10 to p17, p30 to p33, p50 to p57, p60 to p67, p70 to p76, p130 16.0 ma total of pins note2 p00, p01, p40 to p47, p120, p131, p132 8.0 ma output current, low i ol1 note3 total of pins note2 24.0 ma i ol2 per pin for p80 to p87, p90 to p97 av ref = v dd 400 a per pin for p121 to p124 notes 1. value of current at which the device operation is guaranteed even if the current flows from v dd to an output pin. 2. value of current at which the devic e operation is guaranteed even if the current flow s from an output pin to gnd. 3. specification under conditions where the duty fact or is 70% (time for which current is output is 0.7 t and time for which current is not output is 0.3 t, where t is a specific time). the total output current of the pins at a duty factor of other than 70% can be calculated by the following expression. ? where the duty factor of i oh is n%: total output current of pins = (i oh 0.7) / (n 0.01) chapter 28 electrical specifications ((a2) grade products) user?s manual u17553ej4v0ud 676 dc characteristics (3/6) (t a = ? 40 to +125 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit v ih1 p12, p13, p15, p40 to p47, p50 to p57, p64 to p67, p70, p74, p121 to p124 0.7v dd v dd v v ih2 p00, p01, p05, p06, p10, p11, p14, p16, p17, p30 to p33, p71 to p73, p75, p76, p120, p131, p132, reset, exclk, exclks 0.8v dd v dd v v ih3 p80 to p87, p90 to p97 av ref = v dd 0.7av ref av ref v input voltage, high v ih4 p60 to p63 0.7v dd 6.0 v v il1 p12, p13, p15, p40 to p47, p50 to p57, p60 to p67, p70, p74, p121 to p124 0 0.3v dd v v il2 p00, p01, p05, p06, p10, p11, p14, p16, p17, p30 to p33, p71, p72, p73, p75, p76, p120, p131, p132, reset, exclk, exclks 0 0.2v dd v input voltage, low v il3 p80 to p87, p90 to p93 av ref = v dd 0 0.3av ref v i oh = ? 1.5 ma 4.0 v v dd 5.5 v v dd ? 0.7 v v oh1 i oh = ? 1.0 ma p00, p01, p05, p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p76, p120, p130 to p132 2.7 v v dd < 4.0 v v dd ? 0.7 v i oh = ? 100 a p80 to p87, p90 to p97 av ref = v dd v dd ? 0.5 v output voltage, high v oh2 p121 to p124 i ol = 4.0ma 4.0 v v dd 5.5 v 0.7 v v ol1 i ol = 2.0 ma p00, p01, p05, p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p76, p120, p130 to p132 2.7 v v dd < 4.0 v 0.7 v p80 to p87, p90 to p97 av ref = v dd 0.4 v ol2 i ol = 400 a p121 to p124 v i ol = 8 ma p60 to p63 4.0 v v dd 5.5 v 2.0 v i ol = 2.0 ma 0.6 v output voltage, low v ol3 i ol = 2.0 ma 2.7 v v dd < 4.0 v 0.6 v remark unless specified otherwise, the charac teristics of alternate-function pins are the same as those of port pins. chapter 28 electrical specifications ((a2) grade products) user?s manual u17553ej4v0ud 677 dc characteristics (4/6) (t a = ? 40 to +125 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit i lih1 v i = v dd p00, p01, p05, p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p60 to p67, p70 to p76, p120, p131, p132, reset, flmd0 5 a i lih2 v i = av ref p80 to p87, p90 to p97 av ref = v dd 5 a i lih3 v i = v dd p121 to p124 i/o port m ode 5 a input leakage current, high (x1, x2, xt1, xt2) osc port mode 20 a i lil1 v i = v ss p00, p01, p05, p06, p10 to p17, p30 to p33, p40 to p47, p50 to p57, p60 to p67, p70 to p76, p120, p131, p132, reset, flmd0 ? 5 a i lil2 p80 to p87, p90 to p97 av ref = v dd ? 5 a i lil3 p121 to p124 i/o port m ode ? 5 a input leakage current, low (x1, x2, xt1, xt2) osc port mode ? 20 a pull-up resistor r u v i = v ss 10 20 100 k flmd0 supply voltage v il in normal operation mode 0 0.2v dd v v ih in self programming mode 0.8 v dd v dd v remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. chapter 28 electrical specifications ((a2) grade products) user?s manual u17553ej4v0ud 678 dc characteristics (5/6) (t a = ? 40 to +125 c, 2.7 v v dd = ev dd 5.5 v, 2.7 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit square wave input 3.4 10.3 f xh = 20 mhz note 2 , v dd = 5.0 v resonator connection 4.7 12.5 ma square wave input 1.8 5.4 f xh = 10 mhz notes 2, 3 , v dd = 5.0 v resonator connection 2.5 7.2 ma square wave input 1.7 5.4 f xh = 10 mhz notes 2, 3 , v dd = 3.0 v resonator connection 2.4 6.0 ma square wave input 1.0 3.0 f xh = 5 mhz notes 2, 3 , v dd = 3.0 v resonator connection 1.4 3.6 ma f rh = 8 mhz note 4 , v dd = 5.0 v 1.5 4.2 ma square wave input 6 138 i dd1 operating mode f sub = 32.768 khz note 5 , v dd = 5.0 v resonator connection 15 145 a square wave input 1.0 5.9 f xh = 20 mhz note 2 , v dd = 5.0 v resonator connection 2.2 8.6 ma square wave input 0.6 3.1 f xh = 10 mhz notes 2, 3 , v dd = 5.0 v resonator connection 1.2 4.7 ma square wave input 0.3 1.6 f xh = 5 mhz notes 2, 3 , v dd = 3.0 v resonator connection 0.6 2.4 ma f rh = 8 mhz note 4 , v dd = 5.0 v 0.5 2.1 ma square wave input 3.0 133 i dd2 halt mode f sub = 32.768 khz note 5 , v dd = 5.0 v resonator connection 12 138 a supply current note 1 i dd3 note 6 stop mode v dd = 5.0 v 1 100 a notes 1. total current flowing into the internal power supply (v dd , ev dd ), including the peripheral operation current and the input leakage current flowing when the level of the input pin are fixed to v dd or v ss . however, the current flowing into the pull-up resistors and t he output current of the port is not included. 2. not including the operating current of the 8 mhz inte rnal oscillator, xt1 oscillation, 240 khz internal oscillator and the current flowing into the a/d converter, watchdog timer and lvi circuit. 3. when amph (bit 0 of clock operation mode select register (oscctl)) = 0. 4. not including the operating current of the x1 oscillation, xt1 oscillati on and 240 khz internal oscillator. not including the current flowing into the a/d conver ter, watchdog timer, lvi circuit and can controller. 5. not including the operating current of the x1 osc illation, 8 mhz internal oscillator and 240 khz internal oscillator, and the current flowing into the a/ d converter, watchdog timer and lvi circuit. 6. not including the operating current of the 240 khz in ternal oscillator and xt1 oscillation, and the current flowing into the a/d converter, watchdog timer and lvi circuit. remarks 1. f xh : high-speed system clock frequency (x1 clock oscill ation frequency or exte rnal main system clock frequency) 2. f rh : internal high-speed oscillation clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillat ion frequency or external subsystem clock frequency) chapter 28 electrical specifications ((a2) grade products) user?s manual u17553ej4v0ud 679 dc characteristics (6/6) (t a = ? 40 to +125 c, 2.7 v v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit a/d converter operating current i adc note 1 adce = 1 0.86 2.9 ma watchdog timer operating current i wdt note 2 during 240 khz internal low-spee d oscillation clock operation 5 15 a lvi operating current i lvi note 3 9 27 a notes 1. current flowing only to the a/d converter (avref-pin ). the current value of the 78k0/ff2 is the sum of i dd1 or i dd2 and i adc when the a/d converter operates in an operation mode or the halt mode. 2. current flowing only to the watchdog timer (v dd -pin) (including the operating current of the 240 khz internal oscillator). the current va lue of the 78k0/ff2 is the sum of i dd2 or i dd3 and i wdt when the watchdog timer operates in the halt or stop mode. 3. current flowing only to the lvi circuit (v dd -pin). the current value of the 78k0/ff2 is the sum of i dd2 or i dd3 and i lvi when the lvi circuit operates in the halt or stop mode. chapter 28 electrical specifications ((a2) grade products) user?s manual u17553ej4v0ud 680 28.4 ac characteristics (1) basic operation (t a = ? 40 to +125 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 0.1 8 s main system clock (f xp ) operation 2.7 v v dd < 4.0 v 0.2 8 s instruction cycle (minimum instruction execution time) t cy subsystem clock (f sub ) operation 114 122 125 s 4.0 v v dd 5.5 v 20 f prs = f xh 2.7 v v dd < 4.0 v 10 mhz peripheral hardware clock frequency f prs f prs = f rh 2.7 v v dd 5.5 v 7.6 8.46 mhz 4.0 v v dd 5.5 v 4.0 20 mhz external main system clock frequency f ext 2.7 v v dd < 4.0 v 4.0 10 mhz 4.0 v v dd 5.5 v 24 external clock input high level width, low level width f exth , f extl 2.7 v v dd < 4.0 v 48 ns external subsystem clock frequency f exts 32 32.768 35 khz external sub clock input high level width, low level width f extsh , f extsl 12 s 4.0 v v dd 5.5 v 2/f sam + 0.1 note s ti000, ti001, ti002, ti003, ti010, ti011 ti012, ti013 input high-level width, low-level width t tih0 , t til0 2.7 v v dd < 4.0 v 2/f sam + 0.2 note s 4.0 v v dd 5.5 v 10 mhz ti50, ti51 input frequency f ti5 2.7 v v dd < 4.0 v 10 mhz 4.0 v v dd 5.5 v 50 ns ti50, ti51 input high-level width, low-level width t tih5 , t til5 2.7 v v dd < 4.0 v 50 ns 1 s interrupt input high-level width, low-level width t inih , t inil reset low-level width t rsl 10 s note ti sampling with selection count clock (f prs , f prs /4, f prs /256) using bits 0 and 1 (prm0n0, prm0n1) of prescaler mode registers 00 (prm0n). note that when selecting the ti0n0 valid edge as the count clock, f sam = f prs (n = 0, 1, 2, 3) . chapter 28 electrical specifications ((a2) grade products) user?s manual u17553ej4v0ud 681 t cy vs. v dd (main system clock operation) supply voltage v dd [v] cycle time t cy [ s] 5.0 1.0 2.0 0.4 0.2 0.1 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 5.5 20.0 guaranteed operation range 8.0 2.7 chapter 28 electrical specifications ((a2) grade products) user?s manual u17553ej4v0ud 682 ac timing test points (excluding x1, xt1) 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd external clock input timing exclk 0.8v dd 0.2v dd 1/f ext t extl t exth 1/f exts t extsl t extsh exclks 0.8v dd 0.2v dd ti timing ti000, ti001, ti002, ti003, ti010, ti011, ti012, ti013 t til0 t tih0 ti50, ti51 1/f ti5 t til5 t tih5 interrupt request input timing intp0 to intp7 t intl t inth chapter 28 electrical specifications ((a2) grade products) user?s manual u17553ej4v0ud 683 reset input timing reset t rsl (2) serial interface (t a = ? 40 to +125 c, 2.7v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) (a) uart mode (uart6n, dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 625 kbps (b) 3-wire serial i/o mode (master m ode, sck1n... internal clock output) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 200 ns sck1n cycle time t kcy1 2.7 v v dd < 4.0 v 400 ns 4.0 v v dd 5.5 v t kcy1 /2 ? 20 ns sck1n high-/low-level width note1 t kh1 , t kl1 2.7 v v dd < 4.0 v t kcy1 /2 ? 30 ns 4.0 v v dd 5.5 v 70 ns si1n setup time (to sck1n ) t sik1 2.7 v v dd < 4.0 v 100 ns si1n hold time (from sck1n ) t ksi1 30 ns delay time from sck1n to so1n output t kso1 c = 50 pf note2 40 ns notes 1. it is value at the time of f x use. keep in mind that spec different at the time of f osc8 use. 2. c is the load capacitance of the sck1n and so1n output lines. (c) 3-wire serial i/o mode (slave mode , sck1n... external clock input) parameter symbol conditions min. typ. max. unit sck1n cycle time t kcy2 400 ns sck1n high-/low-level width t kh2 , t kl2 t kcy2 /2 ns si1n setup time (to sck1n ) t sik2 80 ns si1n hold time (from sck1n ) t ksi2 50 ns 4.0 v v dd 5.5 v 120 delay time from sck1n to so1n output t kso2 c = 50 pf note 2.7 v v dd < 4.0 v 120 ns note c is the load capacitance of the so1n output line. remark n = 0, 1 chapter 28 electrical specifications ((a2) grade products) user?s manual u17553ej4v0ud 684 serial transfer timing 3-wire serial i/o mode: si1n so1n t kcym t klm t khm t sikm t ksim input data t ksom output data sck1n remark m = 1, 2 n = 0, 1 chapter 28 electrical specifications ((a2) grade products) user?s manual u17553ej4v0ud 685 (3) can controller (t a = ? 40 to +125 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit transfer rate 1 mbps internal delay time t node 100 ns can internal clock ctxd pin (transfer data) crxd pin (receive data) t output t input note internal delay time (t node ) = internal transfer delay (t output ) + internal receive delay (t input ) note can internal clock (f can ): can baud rate clock image figure of internal delay 78k0/ff2 ctxd pin crxd pin can macro internal receive delay internal transfer delay chapter 28 electrical specifications ((a2) grade products) user?s manual u17553ej4v0ud 686 (4) a/d converter characteristics (t a = ? 40 to +125 c, 2.7 v v dd = ev dd 5.5 v, 2.7 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution res 10 bit 4.0 v v dd 5.5 v 0.4 overall error notes 1, 2 a inl 2.7 v v dd < 4.0 v 0.6 %fsr 4.0 v v dd 5.5 v 6.1 36.7 conversion time t conv 2.7 v v dd < 4.0 v 12.2 36.7 s 4.0 v v dd 5.5 v 0.4 zero-scale error notes 1, 2 e zs 2.7 v v dd < 4.0 v 0.6 %fsr 4.0 v v dd 5.5 v 0.4 full-scale error notes 1, 2 e fs 2.7 v v dd < 4.0 v 0.6 %fsr 4.0 v v dd 5.5 v 2.5 integral non-linearity error note 1 i le 2.7 v v dd < 4.0 v 4.5 lsb 4.0 v v dd 5.5 v 1.5 differential non-linearity error note 1 d le 2.7 v v dd < 4.0 v 2.0 lsb analog input voltage v ain av ss av ref v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. chapter 28 electrical specifications ((a2) grade products) user?s manual u17553ej4v0ud 687 (5) poc circuit characteristics (t a = ? 40 to +125 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage v poc0 1.44 1.59 1.74 v power supply rise time t pth v dd : 0 v v poc0 0.5 v/ms minimum pulse width t pw 200 s poc circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t pw t pth caution spec may change after device evaluation. chapter 28 electrical specifications ((a2) grade products) user?s manual u17553ej4v0ud 688 (6) lvi circuit characteristics (t a = ? 40 to +125 c, v poc v dd = ev dd 5.5 v, av ref v dd , v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit v lvi0 4.14 4.24 4.34 v v lvi1 3.99 4.09 4.19 v v lvi2 3.83 3.93 4.03 v v lvi3 3.68 3.78 3.88 v v lvi4 3.52 3.62 3.72 v v lvi5 3.37 3.47 3.57 v v lvi6 3.22 3.32 3.42 v v lvi7 3.06 3.16 3.26 v v lvi8 2.91 3.01 3.11 v supply voltage level v lvi9 2.75 2.85 2.95 v external input pin note 1 ex lvi ex lvi < v dd , 2.7 v v dd 5.5 v 1.11 1.21 1.31 v detection voltage detection voltage on application of supply voltage vdd lvi lvistart (option bye) = 1 2.50 2.70 2.90 v minimum pulse width t lw 200 s operation stabilization wait time note 2 t lwait1 10 s notes 1. external input pin is alternate p120/intp pin. 2. time required from setting lvion to 1 to operation stabilization. remarks 1. v lvin ? 1 > v lvin (n = 1 to 15) 2. v poc < v lvim (v poc : power-on clear detection voltage, m = 0 to 15) lvi circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t lwait1 t lw lvion < -1 chapter 28 electrical specifications ((a2) grade products) user?s manual u17553ej4v0ud 689 (7) power supply starting time (t a = ? 40 to +125 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit starting maximum time to v dd min (2.7v) note1 (v dd : 0 v 2.7v) t pup1 lvi starting option invalid when pin reset intact 3.6 ms starting maximum time to v dd min (2.7v) note1 (pin reset release v dd : 2.7v) t pup2 lvi starting option invalid when pin reset use 1.9 ms notes 1. start a power supply in time shorter than this when lvi staring option invalid. 2. it is base on the spec of poc. 2.7 v 0 v poc t pup1 v dd 2.7 v 0 v poc t pup2 v dd reset pin pin reset intact pin reset use chapter 28 electrical specifications ((a2) grade products) user?s manual u17553ej4v0ud 690 28.5 data retention characteristics data memory stop mode low supply vo ltage data retention characteristics (t a = ? 40 to +125 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.44 note 5.5 v note the value depends on the poc det ection voltage. when the voltage drop s, the data is retained until a poc reset is effected, but data is not re tained when a poc reset is effected. data retention timing v dddr data retention characteristics v dd stop instruction execution stop mode standby release signal (interrupt request) operation chapter 28 electrical specifications ((a2) grade products) user?s manual u17553ej4v0ud 691 28.6 flash eeprom programming characteristics (1) basic characteristics (t a = ? 40 to +125 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit v dd supply current i dd f xp = 10 mhz (typ.), 20 mhz (max.) 4.5 16 ma all block t eraca 20 200 ms erase time notes 1, 2 block unit t erasa 20 200 ms write time (in 8-bit units) note 1 t wrwa 10 100 s number of rewrites per chip c erwr retention: 15 years 1 erase + 1 write after erase = 1 rewrite note 3 100 times notes 1. characteristic of the flash memory. for the char acteristic when a dedicated flash memory programmer, pg-fp4, is used and the rewrite ti me during self programming, 2. the prewrite time before erasure and the erase verify time (writeback time) are not included. 3. when a product is first written after shipment, ?erase write? and ?write only? are both taken as one rewrite. remark spec may change after device evaluation. user?s manual u17553ej4v0ud 692 chapter 29 package drawings ? pd78f0891gc(a)-gad-ax, 78f0891gc(a2)-gad-ax , 78f0892gc(a)-gad-ax, 78f0892gc(a2)-gad-ax, 78f0893gc(a)-gad-ax, 78 f0893gc(a2)-gad-ax s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.125 + 0.075 ? 0.025 (unit:mm) item dimensions d e hd he a a1 a2 a3 14.00 0.20 14.00 0.20 17.20 0.20 17.20 0.20 1.70 max. 0.125 0.075 1.40 0.05 0.25 c e x y zd ze 0.65 0.13 0.10 0.825 0.825 l lp l1 0.80 0.886 0.15 1.60 0.20 p80gc-65-gad 3 + 5 ? 3 note each lead centerline is located within 0.13 mm of its true position at maximum material condition. detail of lead end 80-pin plastic lqfp (14x14) 0.30 b 20 40 80 21 41 60 1 + 0.08 ? 0.04 61 chapter 29 package drawings user?s manual u17553ej4v0ud 693 ? pd78f0891gk(a)-gak-ax, 78f0891gk(a2)-gak-ax , 78f0892gk(a)-gak-ax, 78f0892gk(a2)-gak-ax, 78f0893gk(a)-gak-ax, 78 f0893gk(a2)-gak-ax s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.125 + 0.075 ? 0.025 (unit:mm) item dimensions d e hd he a a1 a2 a3 12.00 0.20 12.00 0.20 14.00 0.20 14.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 1.25 1.25 l lp l1 0.50 0.60 0.15 1.00 0.20 p80gk-50-gak 3 + 5 ? 3 note each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 0.20 b 20 40 1 80 21 41 61 60 80-pin plastic lqfp (fine pitch) (12x12) + 0.07 ? 0.03 user?s manual u17553ej4v0ud 694 chapter 30 recommended soldering conditions these products should be soldered and mount ed under the following recommended conditions. for soldering methods and conditions other than those recommended below, please contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (h ttp://www.necel.com/pkg/en/mount/index.html) table 30-1. surface mounting ty pe soldering conditions ? 80-pin plastic lqfp (14 14) pd78f0891gc(a)-gad-ax, 78f0891g c(a2)-gad-ax, 78f0892gc(a)-gad -ax, 78f0892gc(a2)-gad-ax, 78f0893gc(a)-gad-ax, 78f0893gc(a2)-gad-ax ? 80-pin plastic lqfp (12 12) pd78f0891gk(a)-gak-ax, 78f0891g k(a2)-gak-ax, 78f0892gk(a)-gak- ax, 78f0892gk(a2)-gak-ax, 78f0893gk(a)-gak-ax, 78f0893gk(a2)-gak-ax soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. (at 220 c or higher), count: 3 times or less, exposure limit: 7 days note (after that, prebake at 125 c for 20 to 72 hours) ir60-207-3 partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together ( except for partial heating). user?s manual u17553ej4v0ud 695 chapter 31 cautions for wait 31.1 cautions for wait this product has two internal system buses. one is a cpu bus and the other is a peripheral bus t hat interfaces with the low-speed peripheral hardware. because the clock of the cpu bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the cpu conflict s with an access to the peripheral hardware. when accessing the peripheral hardware that may cause a conflict, therefore, the cpu repeatedly executes processing, until the correct data is passed. as a result, the cpu does not start the next instruction processing but waits. if this happens, the number of execution clocks of an instruction incr eases by the number of wait clocks (f or the number of wait clocks, see table 31- 1 ). this must be noted when r eal-time processing is performed. chapter 31 cautions for wait user?s manual u17553ej4v0ud 696 31.2 peripheral hardware that generates wait table 31-1 lists the register s that issue a wait request when accessed by the cpu, and the number of cpu wait clocks. table 31-1. registers that generate wait and number of cpu wait clocks peripheral hardware register access number of wait clocks serial interface uart60 asis60 read 1 clock (fixed) serial interface uart61 asis61 read 1 clock (fixed) adm write ads write adpc write adcr read 1 to 5 clocks (when f ad = f prs /2 is selected) 1 to 7 clocks (when f ad = f prs /3 is selected) 1 to 9 clocks (when f ad = f prs /4 is selected) 2 to 13 clocks (when f ad = f prs /6 is selected) 2 to 17 clocks (when f ad = f prs /8 is selected) 2 to 25 clocks (when f ad = f prs /12 is selected) a/d converter the above number of clocks is when the same source clock is selected for f cpu and f prs . the number of wait clocks can be calculated by the following expression and under the following conditions. chapter 31 cautions for wait user?s manual u17553ej4v0ud 697 table 31-2 ram access that generate wait and number of cpu wait clocks number of wait clocks peripheral hardware register access min. max. cause global reg. canmodule reg. read/write 1 1 synchronizaition of npb signals with vpclk chapter 31 cautions for wait user?s manual u17553ej4v0ud 698 31.3 example of wait occurrence ? serial interface uart61 user?s manual u17553ej4v0ud 699 appendix a development tools the following development t ools are available for the development of systems that employ the 78k0/ff2. figure a-1 shows the developm ent tool configuration. ? support for pc98-nx series unless otherwise specified, products supported by ibm pc/at tm compatibles are compatible with pc98-nx series computers. when using pc98-nx series computer s, refer to the explanation for ibm pc/at compatibles. ? windows tm unless otherwise specified, ?windows? means the following oss. ? windows 98 ? windows nt tm ? windows 2000 ? windows xp tm caution for the development tools of the 78k0/ff2, contact an ne c electronics sales representative. appendix a development tools user?s manual u17553ej4v0ud 700 figure a-1. development tool configuration (1/3) (1) when using the in-circu it emulator qb-78k0fx2 language processing software ? assembler package ? c compiler package ? device file note 1 ? c library source file note 2 debugging software ? integrated debugger note 4 ? system simulator host machine (pc or ews) qb-78k0fx2 note 4 emulation probe target system flash memory programmer note 4 flash memory write adapter flash memory ? software package ? project manager software package flash memory write environment control software (windows only) note 3 power supply unit note 4 usb interface cable note 4 notes 1. download the device file for 78k0/ff2 (df780893) from the download site for development tools (http://www.necel.com/micro/ods/eng/index.html). 2. the c library source file is not included in the software package. 3. the project manager pm+ is in cluded in the assembler package. pm+ is only used for windows. 4. in-circuit emulator qb-78k0fx2 is supplied with integrated debugger id78k0-qb, simple flash memory programmer pg-fpl3, power supply unit, and usb in terface cable. any other products are sold separately. appendix a development tools user?s manual u17553ej4v0ud 701 figure a-1. development tool configuration (2/3) (2) when using the on-chip debug emulator qb-78k0mini language processing software ? assembler package ? c compiler package ? device file note 1 ? c library source file note 2 debugging software ? integrated debugger note 4 ? system simulator host machine (pc or ews) usb interface cable note 4 qb-78k0mini note 4 connection cable note 4 target connector target system flash memory programmer flash memory write adapter flash memory ? software package ? project manager software package flash memory write environment control software (windows only) note 3 notes 1. download the device file for 78k0/ff2 (df780893) from the download site for development tools (http://www.necel.com/micro/ods/eng/index.html). 2. the c library source file is not included in the software package. 3. the project manager pm+ is in cluded in the assembler package. pm+ is only used for windows. 4. on-chip debug emulator qb-78k0mini is s upplied with integrated debugger id78k0-qb, usb interface cable, and connection cable. any other products are sold separately. appendix a development tools user?s manual u17553ej4v0ud 702 figure a-1. development tool configuration (3/3) (3) when using the on-chip debug emulat or with programming function qb-mini2 language processing software ? assembler package ? c compiler package ? device file note 1 ? c library source file note 2 debugging software ? integrated debugger note 1 ? system simulator host machine (pc or ews) usb interface cable note 4 qb-mini2 note 4 78k0-ocd board note 4 target connector target system ? software package ? project manager software package appendix a development tools user?s manual u17553ej4v0ud 703 a.1 software package development tools (software) common to the 78k/0 series are combined in this package. sp78k0 78k/0 series software package part number: s sp78k0 remark in the part number differs depending on the host machine and os used. s sp78k0 host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom a.2 language processing software this assembler converts programs written in mnemonics into object codes executable with a microcontroller. this assembler is also provided with functi ons capable of automatically creating symbol tables and branch instruction optimization. this assembler should be used in combination with a device file (df780893). appendix a development tools user?s manual u17553ej4v0ud 704 remark in the part number differs depending on the host machine and os used. s ra78k0 s cc78k0 s cc78k0-l host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) 3p17 hp9000 series 700 tm hp-ux tm (rel. 10.10) 3k17 sparcstation tm sunos tm (rel. 4.1.4), solaris tm (rel. 2.5.1) cd-rom s df780893 host machine os supply medium ab13 windows (japanese version) bb13 pc-9800 series, ibm pc/at compatibles windows (english version) 3.5-inch 2hd fd a.3 control software pm+ project manager this is control software designed to enable e fficient user program development in the windows environment. all operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from pm+. appendix a development tools user?s manual u17553ej4v0ud 705 a.4 flash memory programming tools a.4.1 when using flash memory programme r fg-fp4, fl-pr4, pg-fpl3, and fp-lite3 pg-fp4, fl-pr4 flash memory programmer flash memory programmer dedica ted to microcontrollers with on-chip flash memory. pg-fpl3, fp-lite3 simple flash memory programmer simple flash memory programmer dedicated to microcontrollers with on-chip flash memory. remark fl-pr4, fp-lite3 are products of naito densei machida mfg. co., ltd. tel: +81-45-475-4191 naito densei machida mfg. co., ltd. a.4.2 when using on-chip debug emul ator with programming function qb-mini2 qb-mini2 on-chip debug emulator with programming function this is a flash memory programmer dedicat ed to microcontrollers with on-chip flash memory. it is available also as on-chip debug emulator which serves to debug hardware and software when developing application syst ems using the 78k0/fx2. when using this as flash memory programmer, it should be us ed in combination with a connection cable (16-pin cable) and a usb interface cable that is used to connect the host machine. target connector specific ations 16-pin general-purpose connector (2.54 mm pitch) remarks 1. the qb-mini2 is supplied with a usb interface cable and connection cables (10-pin cable and 16-pin cable), and the 78k0-ocd board. a connection cable (10-pin cable) and the 78k0-ocd board are used only when using the on-chip debug function. 2. download the software for operating the qb-mini2 from the download site for development tools (http://www.necel.com/micro/ods/eng/index.html). appendix a development tools user?s manual u17553ej4v0ud 706 a.5 debugging tools (hardware) a.5.1 when using in-circu it emulator qb-78k0fx2 qb-78k0fx2 note in-circuit emulator the in-circuit emulator serves to debug har dware and software when developing application systems using the 78k0/fx2. it supports t he integrated debugger (id78k0-qb). this emulator should be used in combination with a power supply unit and emulation probe, and the usb is used to connect this emulator to the host machine. qb-144-ca-01 check pin adapter this adapter is used in waveform monitoring using the oscilloscope, etc. qb-80-ep-01t emulation probe this emulation probe is flexible type and used to connect the in-circuit emulator and target system. qb-80gc-ea-01t qb-80gk-ea-01t exchange adapter this adapter is used to perform the pin conversion from the in-circuit emulator to the target connector. ? qb-80gc-ea-01t: for 80-pin plas tic lqfp (gc-ubt, gc-gad type) ? qb-80gk-ea-01t: for 80-pin pl astic lqfp (gk-8eu, ga-gak type) qb-80gc-ys-01t qb-80gk-ys-01t space adapter this space adapter is used to adjust the height between the target system and in-circuit emulator. ? qb-80gc-ys-01t: for 80-pin plas tic lqfp (gc-ubt, gc-gad type) ? qb-80gk-ys-01t: for 80-pin pl astic lqfp (gk-8eu, ga-gak type) qb-80gc-yq-01t qb-80gk-yq-01t yq connector this yq connector is used to connect the target connector and exchange adapter. ? qb-80gc-yq-01t: for 80-pin pl astic lqfp (gc-ubt, gc-gad type) ? qb-80gk-yq-01t: for 80-pin pl astic lqfp (gk-8eu, ga-gak type) qb-80gc-hq-01t qb-80gk-hq-01t mount adapter this mount adapter is used to mount the target device with socket. ? qb-80gc-hq-01t: for 80-pin pl astic lqfp (gc-ubt, gc-gad type) ? qb-80gk-hq-01t: for 80-pin pl astic lqfp (gk-8eu, ga-gak type) qb-80gc-nq-01t qb-80gk-nq-01t target connector this target connector is used to mount on the target system. ? qb-80gc-nq-01t: for 80-pin pl astic lqfp (gc-ubt, gc-gad type) ? qb-80gk-nq-01t: for 80-pin pl astic lqfp (gk-8eu, ga-gak type) note the qb-78k0fx2 is supplied with a power supply unit, usb interface cable, and flash memory programmer pg-fpl3. it is also supplied with integr ated debugger id78k0-qb as control software. remark the package contents differ depending on the part number. package contents part number in-circuit emulator emulation probe exch ange adapter yq connector target connector qb-78k0fx2-zzz (-ee) not included qb-78k0fx2-t80gc qb-80gc-ea-01t qb-80gc-yq-01t qb-80gc-nq-01t qb-78k0fx2-t80gk qb-78k0fx2 qb-80-ep-01t qb-80gk-ea-01t qb-80gk-yq-01t qb-80gk-nq-01t a.5.2 when using on-chip debug emulator qb-78k0mini qb-78k0mini on-chip debug emulator this on-chip debug emulator serves to debug hardware and software when developing application systems using the 78k0/fx2. it supports the integrated debugger (id78k0- qb). this emulator should be used in combination with connection cable and a usb interface cable that is used to connect the host machine. target connector specific ations 10-pin general-purpose connector (2.54 mm pitch) remark the qb-78k0mini is supplied with a usb interface c able and a connection cable. as control software, the integrated debugger id78k0-qb is supplied. appendix a development tools user?s manual u17553ej4v0ud 707 a.5.3 when using on-chip debug emul ator with programming function qb-mini2 qb-mini2 on-chip debug emulator with programming function this on-chip debug emulator serves to debug hardware and software when developing application systems using the 78k0/fx2. it is available also as flash memory programmer dedicated to microcontrollers with on-chip flash memory. when using this as on-chip debug emulator, it should be used in combination with a connection cable (10- pin cable or 16-pin cable), a usb interfac e cable that is used to connect the host machine, and the 78k0-ocd board. target connector specificati ons 10-pin general-purpose connector (2.54 mm pi tch) or 16-pin general-purpose connector (2.54 mm pitch) remarks 1. the qb-mini2 is supplied with a usb interface cabl e and connection cables (10-pin cable and 16-pin cable), and the 78k0-ocd board. a connection cable (10-pin cable) and the 78k0-ocd board are used only when using the on-chip debug function. 2. download the software for operating the qb-mini2 from the download site for development tools (http://www.necel.com/micro/ods/eng/index.html). a.6 debugging tools (software) sm+ for 78k0/fx2 note system simulator sm+ for 78k0/fx2 is windows-based software. it is used to perform debugging at the c source level or assembler level while simulating the operation of the target system on a host machine. use of sm+ for 78k0/fx2 allows the exec ution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development e fficiency and software quality. sm+ for 78k0/fx2 should be used in combination with the device file (df780893). this debugger supports the in-circuit emulator s for the 78k/0 series. the id78k0-qb is windows-based software. it has improved c-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory di splay with the trace result. it should be used in combination with the device file. id78k0-qb integrated debugger part number: s id78k0-qb note this product is under development remark in the part number differs depending on the host machine and os used. s id78k0-qb host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom user?s manual u17553ej4v0ud 708 appendix b notes on target system design this chapter shows areas on the tar get system where component mounting is prohibited and areas where there are component mounting height restrictions when the qb-78k0fx2 is used. (a) case of 80-pin gc package figure b-1. the restriction domain on a target system (case of 80-pin gc package) 15 12.05 13.375 10 15 12.05 17.375 10 : exchange adapter area: com ponents up to 17.45 mm in height can be mounted note : emulation probe tip area: co mponents up to 24.45 mm in height can be mounted note note height can be adjusted by using space adapters (each adds 2.4 mm) appendix b notes on target system design user?s manual u17553ej4v0ud 709 (b) case of 80-pin gk package figure b-2. the restriction domain on a target system (case of 80-pin gk package) 15 10.5 13.375 10 15 10.5 17.375 10 : exchange adapter area: com ponents up to 17.45 mm in height can be mounted note : emulation probe tip area: co mponents up to 24.45 mm in height can be mounted note note height can be adjusted by using space adapters (each adds 2.4 mm) user?s manual u17553ej4v0ud 710 appendix c register index c.1 register index (in alphabetical or der with respect to register names) [1] 10-bit a/d conversion resu lt register (adcr)................................................................................... ...........................290 16-bit timer capture/compar e register 000 (c r000) .............................................................................. ......................165 16-bit timer capture/compar e register 001 (c r001) .............................................................................. ......................165 16-bit timer capture/compar e register 002 (c r002) .............................................................................. ......................165 16-bit timer capture/compar e register 003 (c r003) .............................................................................. ......................165 16-bit timer capture/compar e register 010 (c r010) .............................................................................. ......................167 16-bit timer capture/compar e register 011 (c r011) .............................................................................. ......................167 16-bit timer capture/compar e register 012 (c r012) .............................................................................. ......................167 16-bit timer capture/compar e register 013 (c r013) .............................................................................. ......................167 16-bit timer count er 00 (t m00)................................................................................................. ...................................164 16-bit timer count er 01 (t m01)................................................................................................. ...................................164 16-bit timer count er 02 (t m02)................................................................................................. ...................................164 16-bit timer count er 03 (t m03)................................................................................................. ...................................164 16-bit timer mode contro l register 00 (tmc 00).................................................................................. ..........................170 16-bit timer mode contro l register 01 (tmc 01).................................................................................. ..........................170 16-bit timer mode contro l register 02 (tmc 02).................................................................................. ..........................170 16-bit timer mode contro l register 03 (tmc 03).................................................................................. ..........................170 16-bit timer output cont rol register 00 (t oc00)................................................................................ ...........................179 16-bit timer output cont rol register 01 (t oc01)................................................................................ ...........................179 16-bit timer output cont rol register 02 (t oc02)................................................................................ ...........................179 16-bit timer output cont rol register 03 (t oc03)................................................................................ ...........................179 [8] 8-bit a/d conversion resu lt register (adcrh) ................................................................................... ..........................291 8-bit timer compare re gister 50 (cr50) ......................................................................................... ..............................224 8-bit timer compare re gister 51 (cr51) ......................................................................................... ..............................224 8-bit timer coun ter 50 (t m50).................................................................................................. ....................................223 8-bit timer coun ter 51 (t m51).................................................................................................. ....................................223 8-bit timer h carrier cont rol register 1 (tmc yc1).............................................................................. ..........................246 8-bit timer h compare register 00 (cmp00)...................................................................................... ...........................242 8-bit timer h compare register 01 (cmp01)...................................................................................... ...........................242 8-bit timer h compare register 10 (cmp10)...................................................................................... ...........................242 8-bit timer h compare register 11 (cmp11)...................................................................................... ...........................242 8-bit timer h mode re gister 0 (tmhmd0) ......................................................................................... ...........................243 8-bit timer h mode re gister 1 (tmhmd1) ......................................................................................... ...........................243 8-bit timer mode contro l register 50 (tmc 50)................................................................................... ...........................227 8-bit timer mode contro l register 51 (tmc 51)................................................................................... ...........................227 [a] a/d converter mode register (adm) .............................................................................................. ..............................287 appendix c register index user?s manual u17553ej4v0ud 711 a/d port configuratio n register (adpc) ......................................................................................... ..............................293 analog input channel specification re gister (ads) .............................................................................. ........................292 asynchronous serial interface control register 60 (asi cl60) .................................................................... ..................328 asynchronous serial interface control register 61 (asi cl61) .................................................................... ..................328 asynchronous serial interface operat ion mode register 60 (asim60) .............................................................. ...........315 asynchronous serial interface operat ion mode register 61 (asim61) .............................................................. ...........315 asynchronous serial interface recepti on error status regi ster 60 ( asis60)...................................................... ...........320 asynchronous serial interface recepti on error status regi ster 61 ( asis61)...................................................... ...........320 asynchronous serial interface transmissi on status regist er 60 ( asif60) ......................................................... ...........322 asynchronous serial interface transmissi on status regist er 61 ( asif61) ......................................................... ...........322 [b] bank select r egister (bank) .................................................................................................... ...................................80 baud rate generator contro l register 60 (brg c60)............................................................................... ......................326 baud rate generator contro l register 61 (brg c61)............................................................................... ......................326 [c] can global automatic block transmi ssion control regist er (c0gmabt)............................................................. .........422 can global automatic block transmissi on delay setting regi ster (c0g mabtd)...................................................... ....424 can global clock select ion register (c0gmcs) ................................................................................... .......................421 can global control r egister (c 0gmctrl) ......................................................................................... .........................419 can message configuratio n register (c0mconfm) .................................................................................. ................449 can message control re gister m (c 0mctrlm) ...................................................................................... ...................451 can message data byte regi ster xm (c 0mdataxm) .................................................................................. ...............446 can message data byte regi ster zm (c 0mdatazm) .................................................................................. ...............446 can message data length r egister m (c 0mdlcm) ................................................................................... .................448 can message id regist er hm (c 0midhm) ........................................................................................... ......................450 can message id regist er lm (c 0midlm)........................................................................................... ........................450 can module bit rate pre scaler register (c0brp) ................................................................................ .......................437 can module bit rate register (c0btr)........................................................................................... .............................438 can module control register (c0ctrl)........................................................................................... ...........................427 can module error counter register (c0erc)...................................................................................... ........................433 can module information register (c0info) ....................................................................................... ........................432 can module interrupt ena ble register (c0ie) .................................................................................... .........................434 can module interrupt stat us register (c0i nts) .................................................................................. ........................436 can module last error code register (c0le c) .................................................................................... ........................431 can module last in-point er register (c0lipt)................................................................................... ..........................440 can module last out-point er register (c0lopt).................................................................................. .......................442 can module mask control re gister 1h (c0ma sk1h) ................................................................................. ................425 can module mask control register 1l (c0ma sk1l) ................................................................................. .................425 can module mask control re gister 2h (c0ma sk2h) ................................................................................. ................425 can module mask control re gister 2h (c0ma sk2l)................................................................................. .................425 can module mask control re gister 3h (c0ma sk3h) ................................................................................. ................425 can module mask control register 3l (c0ma sk3l) ................................................................................. .................425 can module mask control re gister 4h (c0ma sk4h) ................................................................................. ................425 can module mask control register 4l (c0ma sk4l) ................................................................................. .................425 user?s manual u17553ej4v0ud 712 can module receive history list register (c0rgpt).............................................................................. ......................441 can module time stam p register (c0ts) .......................................................................................... ..........................444 can module transmit history list register (c0tgpt)............................................................................. ......................443 capture/compare contro l register 00 (crc0 0).................................................................................... ........................175 capture/compare contro l register 01 (crc0 1).................................................................................... ........................175 capture/compare contro l register 02 (crc0 2).................................................................................... ........................175 capture/compare contro l register 03 (crc0 3).................................................................................... ........................175 clock operation mode select register (oscctl) .................................................................................. ......................132 clock output selectio n register (cks) .......................................................................................... ...............................280 clock selection regi ster 60 (cksr60)........................................................................................... ..............................324 clock selection regi ster 61 (cksr61)........................................................................................... ..............................324 [e] external interrupt falling edg e enable regist er (egn).......................................................................... ........................527 external interrupt rising e dge enable regist er (egp)........................................................................... ........................527 [f] flash-programming mode co ntrol register (flpmc) ................................................................................ ...................623 flash protect command register (pfcmd)......................................................................................... .........................625 flash status re gister (pfs).................................................................................................... ......................................625 [i] input switch contro l register (isc) ............................................................................................ ...................................332 internal expansion ram size switching regi ster (ixs)........................................................................... ......................600 internal memory size s witching regist er (ims).................................................................................. ...........................599 internal oscillator mode register (rcm)........................................................................................ ...............................129 interrupt mask flag re gister 0h (mk0h)......................................................................................... ..............................525 interrupt mask flag re gister 0l (mk0l)......................................................................................... ...............................525 interrupt mask flag re gister 1h (mk1h)......................................................................................... ..............................525 interrupt mask flag re gister 1l (mk1l)......................................................................................... ...............................525 interrupt request flag register 0h (if0h) ...................................................................................... ...............................523 interrupt request flag register 0l (if 0l)...................................................................................... .................................523 interrupt request flag register 1h (if1h) ...................................................................................... ...............................523 interrupt request flag register 1l (if 1l)...................................................................................... .................................523 [l] low-voltage detection level selection regi ster (l vis).......................................................................... ........................579 low-voltage detecti on register (lvim).......................................................................................... ...............................578 [m] main clock mode register (mcm) ................................................................................................. ...............................130 main osc control register (moc) ................................................................................................ ...............................131 multiplication/division dat a register a0h (md a0h).............................................................................. ........................563 multiplication/division dat a register a0l (md a0l) .............................................................................. .........................563 multiplication/division dat a register b0 (mdb0) ................................................................................ ...........................564 multiplier/divider contro l register 0 (dm uc0).................................................................................. .............................565 appendix c register index user?s manual u17553ej4v0ud 713 [o] oscillation stabilization time c ounter status r egister (ostc) .................................................................. ....................134 oscillation stabilization time select regi ster (osts).......................................................................... ..........................135 [p] port mode regist er 0 (p m0)..................................................................................................... ....................................116 port mode regist er 1 (p m1)..................................................................................................... ....................................116 port mode regist er 12 (p m12)................................................................................................... ..................................116 port mode regist er 13 (p m13)................................................................................................... ..................................116 port mode regist er 3 (p m3)..................................................................................................... ....................................116 port mode regist er 4 (p m4)..................................................................................................... ....................................116 port mode regist er 5 (p m5)..................................................................................................... ....................................116 port mode regist er 6 (p m6)..................................................................................................... ....................................116 port mode regist er 7 (p m7)..................................................................................................... ....................................116 port mode regist er 8 (p m8)..................................................................................................... ....................................116 port mode regist er 9 (p m9)..................................................................................................... ....................................116 port regist er 0 (p0)........................................................................................................... ...........................................119 port regist er 1 (p1)........................................................................................................... ...........................................119 port register 12 (p12) ......................................................................................................... .........................................119 port register 13 (p13) ......................................................................................................... .........................................119 port regist er 3 (p3)........................................................................................................... ...........................................119 port regist er 4 (p4)........................................................................................................... ...........................................119 port regist er 5 (p5)........................................................................................................... ...........................................119 port regist er 6 (p6)........................................................................................................... ...........................................119 port regist er 7 (p7)........................................................................................................... ...........................................119 port regist er 8 (p8)........................................................................................................... ...........................................119 port regist er 9 (p9)........................................................................................................... ...........................................119 prescaler mode regi ster 00 (prm00)............................................................................................. .............................184 prescaler mode regi ster 01 (prm01)............................................................................................. .............................184 prescaler mode regi ster 02 (prm02)............................................................................................. .............................184 prescaler mode regi ster 03 (prm03)............................................................................................. .............................184 priority specification fl ag register 0h (p r0h) ................................................................................. .............................526 priority specification fl ag register 0l (p r0l) ................................................................................. ..............................526 priority specification fl ag register 1h (p r1h) ................................................................................. .............................526 priority specification fl ag register 1l (p r1l) ................................................................................. ..............................526 processor clock cont rol regist er (pcc) ......................................................................................... ..............................127 program stetaus word ( psw) ..................................................................................................... ................................528 pull-up resistor opti on register 0 (pu0) ....................................................................................... ................................120 pull-up resistor opti on register 1 (pu1) ....................................................................................... ................................120 pull-up resistor opti on register 12 (pu 12) ..................................................................................... ..............................120 pull-up resistor opti on register 13 (pu 13) ..................................................................................... ..............................120 pull-up resistor opti on register 3 (pu3) ....................................................................................... ................................120 pull-up resistor opti on register 4 (pu4) ....................................................................................... ................................120 pull-up resistor opti on register 5 (pu5) ....................................................................................... ................................120 pull-up resistor opti on register 6 (pu6) ....................................................................................... ................................120 user?s manual u17553ej4v0ud 714 pull-up resistor opti on register 7 (pu7) ....................................................................................... ................................120 [r] receive buffer regi ster 60 (rxb60) ............................................................................................. ...............................314 receive buffer regi ster 61 (rxb61) ............................................................................................. ...............................314 receive shift regi ster 60 (rxs60) .............................................................................................. .................................314 receive shift regi ster 61 (rxs61) .............................................................................................. .................................314 remainder data regi ster 0 (sdr0)............................................................................................... ...............................563 reset control flag register (resf) ............................................................................................. .................................560 [s] serial clock selection register 10 (csic10) .................................................................................... .............................361 serial clock selection register 11 (csic11) .................................................................................... .............................361 serial operation mode register 10 (csim 10) ..................................................................................... ..........................359 serial operation mode register 11 (csim 11) ..................................................................................... ..........................359 serial i/o shift regi ster 10 (sio10) ........................................................................................... ...................................358 serial i/o shift regi ster 11 (sio11) ........................................................................................... ...................................358 [t] timer clock selection register 50 (tcl50)...................................................................................... .............................225 timer clock selection register 51 (tcl51)...................................................................................... .............................225 transmit buffer regi ster 10 (s otb10) ........................................................................................... ..............................358 transmit buffer regi ster 11 (s otb11) ........................................................................................... ..............................358 transmit buffer regi ster 60 (txb60)............................................................................................ ................................314 transmit buffer regi ster 61 (txb61)............................................................................................ ................................314 transmit shift regi ster 60 (txs60) ............................................................................................. .................................314 transmit shift regi ster 61 (txs61) ............................................................................................. .................................314 [w] watchdog timer enable register (wdte) .......................................................................................... ..........................273 watch timer operation mode register (wtm) ...................................................................................... ........................266 appendix c register index user?s manual u17553ej4v0ud 715 c.2 register index (in al phabetical order with respect to register symbol) [a] adcr: 10-bit a/d conv ersion result regi ster .................................................................................. .................290 adcrh: 8-bit a/d conv ersion result register.................................................................................. ...................291 adm: a/d conver ter mode re gister ............................................................................................. ..................287 adpc: a/d port conf igureation register ....................................................................................... ...................293 ads: analog in put channel specif ication re gister............................................................................. ............292 asicl60: asynchronous serial interface contro l regist er 60 ................................................................... ............328 asicl61: asynchronous serial interface contro l regist er 61 ................................................................... ............328 asif60: asynchronous serial interf ace transmission stat us regist er 60 ........................................................ ...322 asif61: asynchronous serial interf ace transmission stat us regist er 61 ........................................................ ...322 asim60: asynchronous serial inte rface operation mode register 60 ............................................................. ....315 asim61: asynchronous serial inte rface operation mode register 61 ............................................................. ....315 asis60: asynchronous serial interfac e reception error st atus regi ster 60 ..................................................... ...320 asis61: asynchronous serial interfac e reception error st atus regi ster 61 ..................................................... ...320 [b] bank: bank se lect r egister ................................................................................................... ...........................80 brgc60: baud rate genera tor control r egister 60 .............................................................................. ................326 brgc61: baud rate genera tor control r egister 61 .............................................................................. ................326 [c] c0brp: can module bit rate prescale r register ................................................................................ ...............437 c0btr: can module bit rate regist er.......................................................................................... .....................438 c0ctrl: can module control register.......................................................................................... .....................427 c0erc: can module error counter register ..................................................................................... ................433 c0gmabt: can global automatic block transmission co ntrol r egist er ............................................................ ......422 c0gmabtd: can global automatic bl ock transmission dela y setting re gister...................................................... ...424 c0gmcs: can global cl ock selectio n regi ster .................................................................................. ..................421 c0gmctrl: can global control regist er ......................................................................................... ........................419 c0ie: can module in terrupt enabl e regi ster................................................................................... ..............434 c0info: can module information register...................................................................................... ..................432 c0ints: can module in terrupt status regi ster ................................................................................. .................436 c0lec: can module la st error c ode regi ster................................................................................... ................431 c0lipt: can module la st in-pointer register .................................................................................. ..................440 c0lopt: can module la st out-pointer register ................................................................................. .................442 c0mconfm: can message c onfiguration regist er ................................................................................... ...............449 c0mctrlm: can message control regi ster m ...................................................................................... ..................451 c0mdataxm: can message data byte re gister xm ................................................................................... ...............446 c0mdatazm: can message data byte re gister zm ................................................................................... ...............446 c0mdlcm: can message data length r egister m .................................................................................. ...............448 c0mask1h: can module ma sk control re gister 1h................................................................................. ...............425 c0mask1l: can module mask c ontrol regi ster 1l .......................................................................................... ......425 c0mask2h: can module ma sk control re gister 2h................................................................................. ...............425 c0mask2l: can module mask c ontrol regi ster 2h.......................................................................................... ......425 user?s manual u17553ej4v0ud 716 c0mask3h: can module ma sk control re gister 3h.................................................................................. .................425 c0mask3l: can module mask c ontrol regi ster 3l ........................................................................................... ........425 c0mask4h: can module ma sk control re gister 4h.................................................................................. .................425 c0mask4l: can module mask c ontrol regi ster 4l ........................................................................................... ........425 c0midhm: can message id regi ster hm ........................................................................................... .....................450 c0midlm: can message id regi ster lm ........................................................................................... ......................450 c0rgpt: can module receiv e history list regi ster .............................................................................. ..................441 c0tgpt: can module transmi t history list regi ster ............................................................................. ..................443 c0ts: can module ti me stamp register .......................................................................................... .................444 cks: clock output se lection re gister.......................................................................................... .....................280 cksr60: clock select ion regist er 60........................................................................................... ..........................324 cksr61: clock select ion regist er 61........................................................................................... ..........................324 cmp00: 8-bit timer h compare regi ster 00 ...................................................................................... ....................242 cmp01: 8-bit timer h compare regi ster 01 ...................................................................................... ....................242 cmp10: 8-bit timer h compare regi ster 10 ...................................................................................... ....................242 cmp11: 8-bit timer h compare regi ster 11 ...................................................................................... ....................242 cr000: 16-bit timer captur e/compare regi ster 000 .............................................................................. ...............165 cr001: 16-bit timer captur e/compare regi ster 001 .............................................................................. ...............165 cr002: 16-bit timer captur e/compare regi ster 002 .............................................................................. ...............165 cr003: 16-bit timer captur e/compare regi ster 003 .............................................................................. ...............165 cr010: 16-bit timer captur e/compare regi ster 010 .............................................................................. ...............167 cr011: 16-bit timer captur e/compare regi ster 011 .............................................................................. ...............167 cr012: 16-bit timer captur e/compare regi ster 012 .............................................................................. ...............167 cr013: 16-bit timer captur e/compare regi ster 013 .............................................................................. ...............167 cr50: 8-bit timer co mpare regi ster 50 ......................................................................................... .....................224 cr51: 8-bit timer co mpare regi ster 51 ......................................................................................... .....................224 crc00: capture/compare control regi ster 00 .................................................................................... .................175 crc01: capture/compare control regi ster 01 .................................................................................... .................175 crc02: capture/compare control regi ster 02 .................................................................................... .................175 crc03: capture/compare control regi ster 03 .................................................................................... .................175 csic10: serial clock selection re gister 10 .................................................................................... .......................361 csic11: serial clock selection re gister 11 .................................................................................... .......................361 csim10: serial operat ion mode regi ster 10..................................................................................... .....................359 csim11: serial operat ion mode regi ster 11..................................................................................... .....................359 [d] dmuc0: multiplier/divider control re gister 0 .................................................................................. .......................565 [e] egn: external interrupt falling edge enabl e regi ster .......................................................................... .............527 egp: external interrupt rising edge enabl e regi ster ........................................................................... .............527 [f] flpmc: flash-programmi ng mode contro l regi ster ................................................................................ .............623 [i] if0h: interrupt req uest flag regi ster 0h ...................................................................................... .....................523 appendix c register index user?s manual u17553ej4v0ud 717 if0l: interrupt req uest flag regi ster 0l ...................................................................................... .....................523 if1h: interrupt req uest flag regi ster 1h ...................................................................................... .....................523 if1l: interrupt req uest flag regi ster 1l ...................................................................................... .....................523 ims: internal memory size switchin g regi ster.................................................................................. ...............599 isc: input switch control regist er............................................................................................ .......................332 ixs: internal expansion ra m size switch ing regi ster ........................................................................... .........600 [l] lvim: low-voltage de tection re gister ........................................................................................... .....................578 lvis: low-voltage detection level selecti on regi ster ........................................................................... ..............579 [m] mcm: main clo ck mode re gister .................................................................................................. ......................130 mda0h: multiplication/div ision data regi ster a0h............................................................................... ...................563 mda0l: multiplication/div ision data regi ster a0l ............................................................................... ...................563 mdb0: multiplication/div ision data r egister b0 ................................................................................. ...................564 mk0h: interrupt mask flag regist er 0h .......................................................................................... ......................525 mk0l: interrupt mask flag regist er 0l.......................................................................................... .......................525 mk1h: interrupt mask flag regist er 1h .......................................................................................... ......................525 mk1l: interrupt mask flag regist er 1l.......................................................................................... .......................525 moc: main osc c ontrol r egister ................................................................................................. ......................131 [o] oscctl: clock operation mode select regist er ................................................................................... ...................132 ostc: oscillation stabilization ti me counter stat us regi ster ................................................................... .............134 osts: oscillation stabilizati on time select register ........................................................................... ..................135 [p] p0: port r egister 0............................................................................................................ ..............................119 p1: port r egister 1............................................................................................................ ..............................119 p12: port r egister 12.......................................................................................................... ..............................119 p13: port r egister 13.......................................................................................................... ..............................119 p3: port r egister 3............................................................................................................ ..............................119 p4: port r egister 4............................................................................................................ ..............................119 p5: port r egister 5............................................................................................................ ..............................119 p6: port r egister 6............................................................................................................ ..............................119 p7: port r egister 7............................................................................................................ ..............................119 p8: port r egister 8............................................................................................................ ..............................119 p9: port r egister 9............................................................................................................ ..............................119 pcc: processor cloc k control register .......................................................................................... ....................127 pfcmd: flash protec t command r egist er.......................................................................................... ....................625 pfs: flash stat us regi ster ..................................................................................................... ...........................625 pm0: port mode register 0...................................................................................................... ..........................116 pm1: port mode register 1...................................................................................................... ..........................116 pm12: port mode register 12.................................................................................................... ..........................116 pm13: port mode register 13.................................................................................................... ..........................116 pm3: port mode register 3...................................................................................................... ..........................116 user?s manual u17553ej4v0ud 718 pm4: port mode register 4 ...................................................................................................... ..........................116 pm5: port mode register 5 ...................................................................................................... ..........................116 pm6: port mode register 6 ...................................................................................................... ..........................116 pm7: port mode register 7 ...................................................................................................... ..........................116 pm8: port mode register 8 ...................................................................................................... ..........................116 pm9: port mode register 9 ...................................................................................................... ..........................116 pr0h: priority specificat ion flag r egister 0h .................................................................................. .....................526 pr0l: priority specificat ion flag r egister 0l .................................................................................. ......................526 pr1h: priority specificat ion flag r egister 1h .................................................................................. .....................526 pr1l: priority specificat ion flag r egister 1l .................................................................................. ......................526 prm00: prescaler m ode register 00 .............................................................................................. .......................184 prm01: prescaler m ode register 01 .............................................................................................. .......................184 prm02: prescaler m ode register 02 .............................................................................................. .......................184 prm03: prescaler m ode register 03 .............................................................................................. .......................184 psw: program st etaus word ...................................................................................................... .......................528 pu0: pull-up resistor option regi ster 0 ........................................................................................ ......................120 pu1: pull-up resistor option regi ster 1 ........................................................................................ ......................120 pu12: pull-up resistor option regi ster 12 ...................................................................................... ......................120 pu13: pull-up resistor option regi ster 13 ...................................................................................... ......................120 pu3: pull-up resistor option regi ster 3 ........................................................................................ ......................120 pu4: pull-up resistor option regi ster 4 ........................................................................................ ......................120 pu5: pull-up resistor option regi ster 5 ........................................................................................ ......................120 pu6: pull-up resistor option regi ster 6 ........................................................................................ ......................120 pu7: pull-up resistor option regi ster 7 ........................................................................................ ......................120 [r] rcm: internal oscill ator mode register ......................................................................................... .....................129 resf: reset contro l flag re gister.............................................................................................. ..........................560 rxb60: receive bu ffer regist er 60 .............................................................................................. .........................314 rxb61: receive bu ffer regist er 61 .............................................................................................. .........................314 rxs60: receive sh ift register 60 ............................................................................................... ...........................314 rxs61: receive sh ift register 61 ............................................................................................... ...........................314 [s] sdr0: remainder dat a regist er 0 ............................................................................................... .......................563 sio10: serial i/o sh ift register 10 ............................................................................................ ............................358 sio11: serial i/o sh ift register 11 ............................................................................................ ............................358 sotb10: transmit bu ffer regist er 10 ............................................................................................ ..........................358 sotb11: transmit bu ffer regist er 11 ............................................................................................ ..........................358 [t] tcl50: timer clock sele ction regi ster 50 ....................................................................................... ......................225 tcl51: timer clock sele ction regi ster 51 ....................................................................................... ......................225 tm00: 16-bit time r counter 00.................................................................................................. ...........................164 tm01: 16-bit time r counter 01.................................................................................................. ...........................164 tm02: 16-bit time r counter 02.................................................................................................. ...........................164 tm03: 16-bit time r counter 03.................................................................................................. ...........................164 appendix c register index user?s manual u17553ej4v0ud 719 tm50: 8-bit time r counte r 50 ................................................................................................... ...........................223 tm51: 8-bit time r counte r 51 ................................................................................................... ...........................223 tmc00: 16-bit timer mode control regi ster 00................................................................................... ....................170 tmc01: 16-bit timer mode control regi ster 01................................................................................... ....................170 tmc02: 16-bit timer mode control regi ster 02................................................................................... ....................170 tmc03: 16-bit timer mode control regi ster 03................................................................................... ....................170 tmc50: 8-bit timer mode control re gister 50.................................................................................... .....................227 tmc51: 8-bit timer mode control re gister 51.................................................................................... .....................227 tmcyc1: 8-bit timer h carri er control r egister 1 ............................................................................... .......................246 tmhmd0: 8-bit timer h mode regi ster 0.......................................................................................... .........................243 tmhmd1: 8-bit timer h mode regi ster 1.......................................................................................... .........................243 toc00: 16-bit timer output control re gister 00................................................................................. .....................179 toc01: 16-bit timer output control re gister 01................................................................................. .....................179 toc02: 16-bit timer output control re gister 02................................................................................. .....................179 toc03: 16-bit timer output control re gister 03................................................................................. .....................179 txb60: transmit bu ffer regist er 60 ............................................................................................. .........................314 txb61: transmit bu ffer regist er 61 ............................................................................................. .........................314 txs60: transmit sh ift register 60.............................................................................................. ...........................314 txs61: transmit sh ift register 61.............................................................................................. ...........................314 [w] wdte: watchdog timer enable re gister ........................................................................................... ...................273 wtm: watch timer oper ation mode regist er ....................................................................................... ...............266 user?s manual u17553ej4v0ud 720 appendix d revision history the mark appendix d revision history user?s manual u17553ej4v0ud 721 d.2 revision history of preceding editions here is the revision history of the preceding editi ons. chapter indicates the chapter of each edition. (1/10) edition description 3rd addition of pg-fpl3 in documents related to flash memory programming addition of caution 1 to 4 to 1.4 pin configuration (top view) change of 10-bit a/d converter number for 78k0/fc2 in 1.5.1 78k0/fx2 product lineup change of ev dd and v dd in table 2-1. pin i/o buffer power supplies change of regc in table 2-3. non-port pins (2/2) change of 2.2.15 regc change of figure 3-1. memory map ( pd78f0891) addition of note 3 and 4 and remark in figure 3-1. memory map ( pd78f0891) change of figure 3-2. memory map ( pd78f0892) addition of note 3 and 4 and remark in figure 3-2. memory map ( pd78f0892) change of figure 3-3. memory map ( pd78f0893) addition of note 3 and 4 and remark in figure 3-3. memory map ( pd78f0893) addition of table 3-2. correspondence between address values and block numbers in flash memory addition of (5) on-chip debug security id setting area in 3.1.1 internal program memory space addition of caution 4 in 3.1.2 bank area ( pd78f0889 and 78f0890 only) addition of note 1 in table 3-7. special function register list (4/6) change of note in table 3-7. special function register list (6/6) addition of chapter 4 memory bank select function ( pd78f0892, 78f0893 only) change of ev dd and v dd in table 5-1. pin i/o buffer power supplies addition of caution in 5.2.1 port 0 addition of caution in 5.2.2 port 1 addition of caution 1 in 5.2.3 port 3 change of the explanation in 5.2.6 port 6 5.2.8 port 8 ? change of the explanation ? addition of table 5-3. setting functions of p80/ani0 to p87/ani7 pins and caution 5.2.9 port 9 ? change of the explanation ? addition of table 5-4. setting functions of p90/ani8 to p93/ani11 pins and caution addition of caution 1 in 5.2.10 port 12 change of figure 5-18. block diagram of p120 change of figure 5-19. block diagram of p121 to p124 addition of adpc in 5.3 registers controlling port function addition of (4) a/d port configuration register (adpc) in 5.3 registers controlling port function addition of 5.5 cautions on 1-bit manipulation instruction for port register n (pn) change of caution 1 and addition of caution 3 in 6.3 (4) main osc control register (moc) change of caution 2 and 3 in 6.3 (5) clock operation mode select register (oscctl) addition of the explanation in 6.4.1 x1 oscillator and 6.4.2 xt1 oscillator addition of (b) external clock in figure 6-9. example of external circuit of x1 oscillator and figure 6-10. example of external circuit of xt1 oscillator change of explanation and remark in 6.4.3 when subsystem clock is not used appendix d revision history user?s manual u17553ej4v0um 722 (2/10) edition description 3rd figure 6-12 operation of the clock generating circuit when power supply voltage injection (when 1.59 v poc mode setup (option byte: lvistart = 0)) ? change of figure 6-12 and note 2 ? addition of note 1 figure 6-13 operation of the clock generating circuit wh en power supply voltage injection (when 2.7 v/1.59v poc mode setup (option byte: lvistart = 1)) ? change of figure 6-13 and caution 2 ? addition of caution 1 change of 6.6.1 controlling high-speed system clock change of explanation and addition of note in 6.6.1 (2) example of setting procedure when using the external main system clock change of 6.6.2 example of controlling internal high-speed oscillation clock change of 6.6.3 example of controlling subsystem clock figure 6-14. cpu clock status transition diagram ? change of figure 6-14 ? addition of remark change of table 6-5. changing cpu clock addition of 6.6.8 time required for switchover of cpu clock and main system clock addition of 6.6.9 conditions before clock oscillation is stopped change of explanation and addition of caution 1 and 2 in 7.2 (1) 16-bit timer counter 0n (tm0n) addition of caution in 7.2 (2) 16-bit timer capture/compare register 00n (cr00n) addition of 7.2 (4) setting range when cr00n or cr01n is used as a compare register change of explanation in 7.3 (1) 16-bit timer mode control register 0n (tmc0n) change of figure 7-8. format of 16-bit timer mode control register 00 (tmc00) change of figure 7-9. format of 16-bit timer mode control register 01 (tmc01) change of figure 7-10. format of 16-bit timer mode control register 02 (tmc02) change of figure 7-11. format of 16-bit timer mode control register 03 (tmc03) change of explanation in 7.3 (2) capture/compare control register 0n (crc0n) change of figure 7-12. format of capture/compare control register 00 (crc00) addition of figure 7-13. example of cr01n capture operation (when rising edge is specified) change of figure 7-14. format of capture/compare control register 01 (crc01) change of figure 7-15. format of capture/compare control register 02 (crc02) change of figure 7-16. format of capture/compare control register 03 (crc03) change of explanation and addition of caution in 7.3 (3) 16-bit timer output control register 0n (toc0n) change of figure 7-17. format of 16-bit timer output control register 00 (toc00) change of figure 7-18. format of 16-bit timer output control register 01 (toc01) change of figure 7-19. format of 16-bit timer output control register 02 (toc02) change of figure 7-20. format of 16-bit timer output control register 03 (toc03) change of explanation and caution 1 to 3 in 7.3 (4) prescaler mode register 0n (prm0n) addition of 7.5 special use of tm0n addition of 7.6 cautions for 16-bit timer/event counters 00 and 01 change of explanation and caution in 9.2 (1) 8-bit timer h compare register 0n (cmp0n) change of 9.2 (2) 8-bit timer h compare register 1n (cmp1n) appendix d revision history user?s manual u17553ej4v0ud 723 (3/10) edition description 3rd change of caution 1 in figure 9-5. format of 8-bit timer h mode register 0 (tmhmd0) change of figure 9-6. format of 8-bit timer h mode register 1 (tmhmd1) change of caution 1 in figure 9-6. format of 8-bit timer h mode register 1 (tmhmd1) change of figure 9-7. format of 8-bit timer h carrier control register 1 (tmcyc1) change of wtm0 bit in figure 10-2. format of watch timer operation mode register (wtm) change of explanation in 10.4.1 watch timer operation change of table 10-4. watch timer interrupt time change of figure 10-3. operation timing of watch timer/interval timer change of explanation in 11.1 functions of watchdog timer change of explanation in table 11-2. setting of option bytes and watchdog timer and figure 11-1. block diagram of watchdog timer change of explanation in 11.4.1 controlling operation of watchdog timer change of caution 4 and 5 in 11.4.1 controlling operation of watchdog timer change of note 2 in table 11-3. setting of overflow time of watchdog timer change of explanation in 11.4.3 setting window open period of watchdog timer change of note 2 in table 11-4. setting window open period of watchdog timer addition of note1, caution1 and 2 in figure 12-2. format of clock output selection register (cks) change of explanation in 13.2 (2) sample & hold circuit, (3) series resistor string, (4) voltage comparator and (5) successive approximation register (sar) change of explanation in 13.2 (8) controller change of note 2 in figure 13-3. format of a/d converter mode register (adm) change of table 13-1. settings of adcs and adce figure 13-4. timing chart when comparator is used ? change of figure 13-4 and note change of (1), (2) and caution 1 and addition of caution 4 in table 13-2. a/d conversion time selection change of explanation and caution 1 in 13.3 (5) a/d port configuration register (adpc) change of figure 13-9. format of a/d port configuration register (adpc) addition of explanation in 13.3 (6) port mode register 8 (pm8) and (7) port mode register 9 (pm9) change of table 13-3. setting functions of p80/ani0 to p87/ani7, p90/ani8 to p93/ani11 pins change of 13.4.1 basic operations of a/d converter change of explanation in 13.4.3 (1) a/d conversion operation change of 13.6 cautions for a/d converter change of explanation and addition of caution 3 to 5 in 14.1 (2) asynchronous serial interface (uart) mode change of figure 14-1. lin transmission operation figure 14-2. lin reception operation ? change of figure 14-2 and explanation addition of figure 14-4. port configuration for lin reception operation (uart61) addition of caution 3 in 14.2 (3) transmit buffer register 6n (txb6n) change of note 1 in figure 14-7. format of asynchronous serial interface operation mode register 60 (asim60) (1/2) addition of caution 4 and 5 in figure 14-7. format of asynchronous serial interface operation mode register 60 (asim60) (2/2) change of note 1 in figure 14-8. format of asynchronous serial interface operation mode register 61 (asim61) (1/2) appendix d revision history user?s manual u17553ej4v0um 724 (4/10) edition description 3rd addition of caution 4 and 5 in figure 14-8. format of asynchronous serial interface operation mode register 61 (asim61) (2/2) change of bit 0 from intsr6n to txsf6n of 14.3 (3) asynchronous serial interface transmission status register 6n (asif6n), figure 14-11. format of asynchronous serial interface transmission status register 60 (asif60) and figure 14-12. format of asynchronous serial interface transmission status register 61 (asif61) figure 14-15. format of baud rate generator control register 60 (brgc60) ? change of figure 14-15 and remark 2 figure 14-16. format of baud rate generator control register 61 (brgc61) ? change of figure 14-16 and remark 2 change of caution in 14.3 (6) asynchronous serial interface control register 6n (asicl6n) change of caution 1, 2 and 4 and addition of caution 6 in figure 14-17. format of asynchronous serial interface control register 60 (asicl60) (2/2) change of caution 1, 2 and 4 and addition of caution 6 in figure 14-18. format of asynchronous serial interface control register 61 (asicl61) (2/2) change of caution in 14.4.1 (1) register used change of explanation in 14.4.2 (2) (c) normal transmission change of bit 0 from intsr6n to txsf6n of 14.4.2 (d) continuous transmission change of bit 0 from intsr6n to txsf6n of figure 14-24. example of continuous transmission processing flow change of bit 0 from intsr6n to txsf6n of figure 14-25. timing of starting continuous transmission change of bit 0 from intsr6n to txsf6n of figure 14-26. timing of ending continuous transmission change of caution 1 in 14.4.2 (2) (e) normal reception change of explanation in 14.4.2 (2) (h) sbf transmission change of explanation in 14.4.3 (2) (a) baud rate table 14-4. set data of baud rate generator ? change of table 14-4 and remark change of table 14-5. maximum/minimum permissible baud rate error change of table 15-1. configuration of serial interfaces csi10 and csi11 figure 15-1. block diagram of serial interface csi10 ? change of figure 15-1 ? addition of remark figure 15-2. block diagram of serial interface csi11 ? change of figure 15-2 ? addition of remark change of caution 2 in (1) transmit buffer register 1n (sotb1n) a nd (2) serial i/o shift register 1n (sio1n) change of note 2 and 5 in figure 15-3. format of serial operation mode register 10 (csim10) change of note 2 and 5 in figure 15-4. format of serial operation mode register 11 (csim11) change of note 1 in 15.4.1 (1) (a) ? serial operation mode register 10 (csim10) and ? serial operation mode register 11 (csim11) addition of remark 1 in figure 15-11. timing of clock/data phase change of 15.4.2 (3) timing of output to so1n pin (first bit) change of 15.4.2 (4) output value of so1n pin (last bit) change of 15.4.2 (5) so1n output (see (a) in figures 15-1 and 15-2) change of table 16-1. overview of functions change of caution 2 in figure 15-5. format of serial clock selection register 10 (csic10) change of caution 2 in figure 15-6. format of serial clock selection register 11 (csic11) appendix d revision history user?s manual u17553ej4v0ud 725 (5/10) edition description 3rd change of table 16-11. error types change of table 16-13. types of error states change of explanation in 16.3.6 (4) (b) error counter change of caution in 16.3.6 (4) (c) occurrence of bit error in intermission change of explanation in 16.3.6 (5) recovery from bus-off state change of explanation and caution 2 and addition of caution 1 in 16.3.6 (5) (a) recovery operation from bus-off state through normal recovery sequence change of explanation in 16.3.7 (1) prescaler addition of remark in figure 16-18. segment setting and figure 16-19. reference: configuration of data bit time defined by can specification addition of caution in table 16-17. bit configuration of can global registers to table 16-19. bit configuration of message buffer registers movement of 16.6 bit set/clear function change of caution in efsd bit in 16.7 (1) (a) read addition of caution in gom bit in 16.7 (1) (b) write change of remark 4 in ccerc bit and remark 3 in vaild bit in 16.7 (6) (a) read addition of caution 2, 3 in psmode1 and psmode2 bits and caution in opmode2-opmode0 bits in 16.7 (6) (a) read addition of caution in cints5 to cints0 bit in 16.7 (11) (b) write addition of note in rovf bit in 16.7 (15) (a) read addition of note in tovf bit in 16.7 (17) (a) read addition of remark in tsen bit in 16.7 (18) (a) read change of caution 2 in 16.7 (20) can message data length register m (c0mdlcm) addition of caution 2 in id28 to id0 in 16.7 (22) can message id register m (c0midlm, c0midhm) addition of caution in trq bit and caution 2 and 3 in rdy bit in 16.7 (23) (a) read addition of caution in ie bit in 16.7 (23) (b) write addition of caution in rdy bit in 16.7 (23) (b) write addition of 16.9.2 receive data read addition of caution in 16.9.3 receive history list function change of the explanation in 16.9.4 mask function change of caution in 16.9.6 remote frame reception change of the explanation in 16.10.1 message transmission change of remark 2 in 16.10.1 message transmission addition of caution in 16.10.2 transmit history list function addition of remark in 16.11.1 (1) entering can sleep mode change of the explanation in 16.11.1 (2) status in can sleep mode change of the explanation and addition of caution in 16.11.1 (3) releasing can sleep mode change of the explanation in 16.11.2 (2) status in can stop mode addition of 16.13.4 receipt/transmit operation in each operation mode change of explanation in figure 16-35. timing diagram of capture signal tsout addition of note 2 in figure 16-40. message buffer redefinition addition of remark in figure 16-44. transmission via interrupt (using c0lopt register) addition of remark in figure 16-45. transmission via interrupt (using c0tgpt register) addition of remark in figure 16-46. transmission via software polling appendix d revision history user?s manual u17553ej4v0um 726 (6/10) edition description 3rd addition of note in figure 16-47. transmission abort processing (except normal operation mode with abt) addition of note in figure 16-48. transmission abort processing except for abt transmission (normal operation mode with abt) change of figure 16-51. reception via interrupt (using c0lipt register) and addition of remark change of figure 16-52. reception via interrupt (using c0rgpt register) and addition of remark change of figure 16-53. reception via software polling and addition of remark change of figure 16-54. setting can sleep mode/stop mode change of figure 16-55. clear can sleep/stop mode addition of note, caution and remark in figure 16-56. bus-off recovery (except normal operation mode with abt) addition of note, caution and remark in figure 16-57. bus-off recovery (normal operation mode with abt) change of figure 16-61. setting cpu standby (from can sleep mode) and addition of caution change of figure 16-62. setting cpu standby (from can stop mode) change of explanation in 17.1 (1) maskable interrupts change of explanation in 17.2 interrupt sources and configuration addition of note 3 in table 17-1. interrupt source list (2/2) addition of note 3 in table 17-2. flags corresponding to interrupt request sources change of caution 3 in 18.1.1 (2) stop mode figure 18-1. format of oscillation stabilization time counter status register (ostc) ? change of figure 18-1 and caution 2 change of explanation and caution 3 in 18.1.2 (2) oscillation stabilization time select register (osts) change of table 18-1. operating statuses in halt mode addition of note in table 18-1. operating statuses in halt mode (2/2) change of figure 18-4. halt mode release by reset change and addition of note in table 18-3. operating statuses in stop mode change of caution 4 in table 18-3. operating statuses in stop mode figure 18-5. operation timing when stop mode is released ? change of figure 18-5 ? addition of note1 and 2 change of figure 18-6. stop mode release by interrupt request generation change of 18.2.2 (2) (b) release by reset signal generation and figure 18-7. stop mode release by reset change of explanation in chapter 19 reset function change of figure 19-2. timing of reset by reset input and figure 19-3. timing of reset due to watchdog timer overflow change of figure 19-4. timing of reset in stop mode by reset input change of table 19-1. operation statuses during reset period addition of note in table 19-2. hardware statuses after reset acknowledgment (2/3) addition of note 1 and change of note 2 in table 19-2. hardware statuses after reset acknowledgment (3/3) change of explanation in 21.1 functions of power-on-clear circuit change of 21.3 operation of power-on-clear circuit figure 21-2. timing of generation of internal reset signal by power-on-clear circuit and low-voltage detector (1/2) ? change of figure and note 2, 4 ? addition of note 1, 3 appendix d revision history user?s manual u17553ej4v0ud 727 (7/10) edition description 3rd figure 21-2. timing of generation of internal reset signal by power-on-clear circuit and low-voltage detector (2/2) ? change of figure and note 2 ? addition of note 1 and caution 2 change of figure 21-3. example of software processing after reset release (1/2) change of explanation in 22.1 functions of low-voltage detector change of figure 22-1. block diagram of low-voltage detector figure 22-2. format of low-voltage detection register (lvim) ? change of figure and note 3 change of caution 3 in figure 22-3. format of low-voltage detection level selection register (lvis) change of explanation and remark in 22.4 operation of low-voltage detector change of explanation in 22.4.1 (1) when detecting level of supply voltage (v dd ) change of explanation and caution 2 in 22.4.2 (2) when detecting level of input voltage from external input pin (exlvi) change of figure 22-6. timing of low-voltage detector in ternal reset signal generation (detects level of input voltage from external input pin (exlvi)) change of explanation in 22.4.2 (1) when detecting level of supply voltage (v dd ) figure 22-7. timing of low-voltage detector interrupt signal generation (detects level of supply voltage (v dd )) ? change of figure 22-7 and note 2 change of explanation in 22.4.2 (2) when detecting level of input voltage from external input pin (exlvi) figure 22-8. timing of low-voltage detector interrupt si gnal generation (detects level of input voltage from external input pin (exlvi)) ? change of figure 22-8 and note 2 change of explanation in 22.5 cautions for low-voltage detector change of figure 22-9. example of software processing after reset release (1/2) change of chapter 23 option byte addition of caution in 24.1 internal memory size switching register addition of caution in 24.2 internal expansion ram size switching register change of note 2 in table 24-3. wiring between 78k0/fc2 and dedicated flash memory programmer change of figure 24-3. example of wiring adapter for flash memory writing in 3-wire serial i/o (csi10) mode figure 24-4. example of wiring adapter for flash memory writing in uart (uart60) mode ? change of figure 24-4 ? addition of note change of explanation in 24.5 (1) csi10 change of figure 24-6. communication with dedicated flash memory programmer (csi10) figure 24-7. communication with dedicated flash memory programmer (uart60) ? change of figure and note change of explanation in 24.5 (2) uart60 table 24-4. pin connection ? change of table and note 1 change of explanation in 24.6.5 regc pin change of explanation and caution 3 in 24.6.6 other signal pins change of explanation in 24.6.7 power supply appendix d revision history user?s manual u17553ej4v0um 728 (8/10) edition description 3rd change of note 1 in table 24-7. communication modes addition of 24.8 security settings addition of 24.9 processing time for each command when pg-fp4 is used (reference) change of figure 24-16. self-programming procedure addition of table 24-14. processing time and interrupt response time for self programming sample library change of 24.11 boot swap function change of caution in 25.1 outline of functions addition of note and caution in figure 25-2. connection circuit example (when qb-78k0mini is not used) and figure 25-3. connection circuit example (when using qb-78k0mini: x1 and x2 are used) addition of note in figure 25-4. connection circuit example (when using qb-78k0mini: ports 31 and 32 are used) addition of figure 25-5. connection of flmd0 pin for self programming by means of on-chip debugging addition of 25.4 on-chip debug security change of 25.5 restrictions and cautions on on-chip debug function 27.1 absolute maximum ratings ? addition of regc pin input voltage of absolute maximum ratings ? addition of i oh2 and i oh3 in output current, high of absolute maximum ratings ? addition of i ol2 and i ol3 in output current, low of absolute maximum ratings 27.2 oscillator characteristics ? addition of rsts = 1 and rsts = 0 in the condition of 8 mhz internal oscillator ? change of max. and min. value of 240 khz internal oscillator ? addition of remark in (2) on-chip internal oscillator characteristics 27.3 dc characteristics ? change of max. value of output current, high in 4.0 v v dd = ev dd 5.5 v and 2.7 v v dd = ev dd < 4.0 v ? addition of note 1 to 3 and change of remark of output current, high and output current, low ? change of max. value of output current, high ? addition of v ih 4 of input voltage, high ? addition of i ol = 5.0 ma, 2.0 ma in the condition of output voltage, low ? change of max. value of output voltage, low (i ol = 1.0 ma and v ol3 , i ol = 5.0 ma, 3.0 ma, 1.0 ma) ? change of supply current, a/d converter operating current, watchdog timer operating current, lvi operating current 27.4 (1) basic operation ? change of min. value of external clock input high level width, low level width, external sub clock input high level width, low level width and ti000, ti001, ti002, ti003, ti010, ti011, ti012, ti013 input high-level width, low-level width ? addition of peripheral hardware clock frequency and note 1, 2 ? change of tcy vs. v dd (main system clock operation) ? change of external clock input timing change of max. value of transfer rate in (a) uart mode (uart6n, dedicated baud rate generator output) change of min. value of sck1n cycle time, sck1n hi gh-/low-level width, si1n setup time (to sck1n ) in 27.4 (2) (b) 3-wire serial i/o mode (master mode, sck1n... internal clock output) change of max. value of delay time from sck1n to so1n output in 27.4 (2) (c) 3-wire serial i/o mode (slave mode, sck1n... external clock input) appendix d revision history user?s manual u17553ej4v0ud 729 (9/10) edition description 3rd 27.4 (4) a/d converter characteristics ? addition of max. value of overall, conversion time, zero-scale error, full-scale error, integral non-linearity error, differential non-linearity error change of min. value of power supply rise time, minimum pulse width in 27.4 (5) poc circuit characteristics 27.4 (6) lvi circuit characteristics ? addition of condition ? addition of min. and max. value of external input pin ? addition of detection voltage on application of supply voltage of detection voltage ? change of value of minimum pulse width ? change of lvi circuit timing change of value of starting maximum time to vdd min (1.8 v) (v dd : 0 v 1.8 v) and starting maximum time to v dd min (1.8 v) (pin reset release v dd : 1.8 v) in 27.4 (7) power supply starting time change of note in 27.5 data retention characteristics change of 27.6 flash eeprom programming characteristics addition of chapter 28 electrical specifications ((a2) grade products) change of 64-pin plastic lqfp(fine pitch)( 10x10) and 64-pin plastic lqfp (12x12) in chapter 29 package drawings addition of chapter 30 recommended soldering conditions change of table 31-1. registers that generate wait and number of cpu wait clocks change of 31.3 example of wait occurrence change of explanation in windows addition of note 1 in figure a-1. development tool configuration addition of (3) when using the on-chip debug emulator with programming function qb-mini2 in figure a-1. development tool configuration change of df780893 device file, note 1 and remark in a.2 language processing software change of a.4 flash memory programming tools change of explanation and note in a.5.1 when using in-circuit emulator qb-78k0fx2 addition of remark in a.5.2 when using on-chip debug emulator qb-78k0mini addition of a.5.3 when using on-chip debug emulator with programming function qb-mini2 change of a.6 debugging tools (software) 2nd modification of part number in 1. 3 ordering information addition of caution 2 in 2.2.3 p30 to p33 (port 3) addition of caution in 2.2.10 p120 to p124 (port 12) addition of note in table 2-4 pin i/o circuit types (1/2) addition of note 3 in table 2-4 pin i/o circuit types (2/2) addition of caution 2 in 4.2.3 port 3 addition of caution in 4.2.10 port 12 modification of processing time in figure 5-12 operation of the clock generating circuit when power supply voltage injection (when 1.59 v poc mode setup (option byte: lvistart = 0)) modification of processing time in figure 5-13 operation of the clock generating circuit when power supply voltage injection (when 2.7 v/1.59v poc mo de setup (option byte: lvistart = 1)) modification of address to ff8fh in figure 9-2 format of watch timer operation mode register (wtm) appendix d revision history user?s manual u17553ej4v0um 730 (10/10) edition description 2nd addition of caution in 23.7.4 port pins addition of caution 3 in 23.7.6 other signal pins modification of standard setting in table 23-7 communication modes modification of note 4 in 26.3 dc characteristics user?s manual u17553ej4v0ud 731 [memo] nec electronics corporation 1753, shimonumabe, nakahara-ku, kawasaki, kanagawa 211-8668, japan tel: 044-435-5111 http://www.necel.com/ [america] nec electronics america, inc. 2880 scott blvd. santa clara, ca 95050-2554, u.s.a. tel: 408-588-6000 800-366-9782 http://www.am.necel.com/ [asia & oceania] nec electronics (china) co., ltd 7th floor, quantum plaza, no. 27 zhichunlu haidian district, beijing 100083, p.r.china tel: 010-8235-1155 http://www.cn.necel.com/ nec electronics shanghai ltd. room 2511-2512, bank of china tower, 200 yincheng road central, pudong new area, shanghai p.r. china p.c:200120 tel: 021-5888-5400 http://www.cn.necel.com/ nec electronics hong kong ltd. unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: 2886-9318 http://www.hk.necel.com/ nec electronics taiwan ltd. 7f, no. 363 fu shing north road taipei, taiwan, r. o. c. tel: 02-8175-9600 http://www.tw.necel.com/ nec electronics singapore pte. ltd. 238a thomson road, #12-08 novena square, singapore 307684 tel: 6253-8311 http://www.sg.necel.com/ nec electronics korea ltd. 11f., samik lavied?or bldg., 720-2, yeoksam-dong, kangnam-ku, seoul, 135-080, korea tel: 02-558-3737 http://www.kr.necel.com/ for further information, please contact: g07.1a [europe] nec electronics (europe) gmbh arcadiastrasse 10 40472 dsseldorf, germany tel: 0211-65030 http://www.eu.necel.com/ hanover office podbielskistrasse 166 b 30177 hannover tel: 0 511 33 40 2-0 munich office werner-eckert-strasse 9 81829 mnchen tel: 0 89 92 10 03-0 stuttgart office industriestrasse 3 70565 stuttgart tel: 0 711 99 01 0-0 united kingdom branch cygnus house, sunrise parkway linford wood, milton keynes mk14 6np, u.k. tel: 01908-691-133 succursale fran?aise 9, rue paul dautier, b.p. 52 78142 velizy-villacoublay cdex france tel: 01-3067-5800 sucursal en espa?a juan esplandiu, 15 28007 madrid, spain tel: 091-504-2787 tyskland filial t?by centrum entrance s (7th floor) 18322 t?by, sweden tel: 08 638 72 00 filiale italiana via fabio filzi, 25/a 20124 milano, italy tel: 02-667541 branch the netherlands steijgerweg 6 5616 hs eindhoven the netherlands tel: 040 265 40 10 |
Price & Availability of UPD78F0893GCA2-GAD-AX
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |