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[ak5367a] general description ak5367a is a high-performance 24-bi t, 96khz sampling adc for consum er audio and digital recording applications. the ak5367a us es an enhanced dual-bit m odulator architecture, this analog-to-digital converter has an impressive dynamic range of 102db with high level integration. the ak5367a has a 4-channel stereo input selector, an input programmable gain amplifier with resistance. all this integration with high-performance makes the ak5367a well su ited for cd and dvd recording systems. the integrated charge pump circuit c an generate the negative power supply and remove the output coupling capacitor. features 1. 24bit stereo adc ? 4:1 0v bias stereo input selector ? digital hpf for offset cancellation (fc=1.0hz@fs=48khz) ? decimation lpf: -0.2db@ 20kh z, -3.0db@23khz (fs=48khz) ? soft mute ? single-end inputs ? s/(n+d): 90db ? dr, s/n: 102db ? audio i/f format: 24bit msb justified, i 2 s 2. control interface: i 2 c-bus 3. master mode / slave mode 4. master clock: ? 256fs/384fs (32khz 96khz) ? 512fs/768fs (32khz 48khz) 5. sampling rate: 32khz to 96khz 6. power supply ? analog supply: 4.5 5.5v ? digital supply: 3.0 3.6v 7. ta = ? 20 85 c 8. package: 30pin vsop 96khz 24-bit adc with 0v bias selector ak5367a = preliminary = ms0967-e-00 2008/05 - 1 -
[ak5367a] block diagram rout adc audio i/f adc hpf adc rin1 rin2 rin3 rin4 lopin lisel risel ropin hpf pdn avdd vss1 lrck bick sdto mclk dvdd vss2 cvdd sda lin1 lin2 lin3 lin4 lout 2vrms 2vrms 0v 0v 47k 24k 47k 47k 24k vcom=0v 0v 1vrms cp cn cvee scl charge pump vcom 0.1 p 1 p 10 p 10 p 47k + + 47k 47k 47k 47k figure 1. ak5367a block diagram ms0967-e-00 2008/05 - 2 -
[ak5367a] ordering guide AK5367AEF 20 a +85 q c 30pin vsop (0.65mm pitch) akd5367a evaluation board for ak5367a pin layout 6 5 4 3 2 1 vcom lin1 lin2 rin2 lin3 7 lin4 8 avdd vss1 dvdd lrck mclk bick sdto AK5367AEF top view 10 9 rin4 risel rout 11 ropin 12 scl sda pdn cp 25 26 27 28 29 30 24 23 21 22 20 19 rin3 lopin 13 lout 14 cn cvdd 18 17 lisel 15 cvee 16 vss2 rin1 ms0967-e-00 2008/05 - 3 -
[ak5367a] pin/function no. pin name i/o function common voltage output pin, avdd/2 1 vcom o bias voltage of adc input. 2 lin1 i lch analog input 1 pin 3 rin1 i rch analog input 1 pin 4 lin2 i lch analog input 2 pin 5 rin2 i rch analog input 2 pin 6 lin3 i lch analog input 3 pin 7 rin3 i rch analog input 3 pin 8 lin4 i lch analog input 4 pin 9 rin4 i rch analog input 4 pin 10 risel i rch analog input pin rout o rch feedback resistor output pin 11 ropin o rch feedback resistor input pin 12 lopin o lch feedback resistor intput pin 13 lout o lch feedback resistor output pin 14 15 lisel i lch analog input pin negative voltage output pin connect to vss2 with a 1.0 f capacitor which is low esr (equivalent series resistance) over all temperature range. when this capacitor has the polarity, the positive polarity pin must be connected to the vss2 pin. non polarity capacitors can also be used. 16 cvee o charge pump ground pin, 0v 17 vss2 - connect to cvee with a 1.0 f capacitor which is low esr (equivalent series resistance) over all temperature range. when this capacitor has the polarity, the positive polarity pin must be connected to the vss2 pin. non polarity capacitors can also be used. cvdd - charge pump power supply pin, 3.0v 3.6v 18 negative charge pump capacitor terminal pin 19 cn i connect to cp with a 0.1 f capacitor which is low esr (equivalent series resistance) over all temperature range. when this capacitor has the polarity, the positive polarity pin must be connected to the cp pin. non polarity capacitors can also be used. positive charge pump capacitor terminal pin 20 cp o connect to cn with a 0.1 f capacitor which is low esr (equivalent series resistance) over all temperature range. when this capacitor has the polarity, the positive polarity pin must be connected to the cp pin. non polarity capacitors can also be used. power down mode & reset pin 21 pdn i ?h?: power up, ?l?: power down & reset the ak5367a must be reset once upon power-up. control data input / output pin in i 2 c control sda i/o 22 control data clock pin in i 2 c control scl i 23 audio serial data output pin 24 sdto o ?l? output at power-down mode. audio serial data clock pin 25 bick i/o ?l? output in master mode at pwn bit= ?0?. 26 mclk i master clock input pin ms0967-e-00 2008/05 - 4 -
[ak5367a] no. pin name i/o function channel clock pin 27 lrck i/o ?l? output in master mode at pwn bit= ?0?. 28 dvdd - digital power supply pin, 3.0 3.6v 29 vss1 - analog ground pin 30 avdd - analog power supply pin, 4.5 5.5v note: all input pins except analog input pins (risel, lisel, lin1-4, rin1-4) must not be left floating. v handling of unused pin the unused input pins should be processed appropriately as below. classification pin name setting lin1-4,rin1-4,lisel,risel analog these pins must be open. lopin,lout,ropin,rout ms0967-e-00 2008/05 - 5 -
[ak5367a] absolute maximum ratings (vss1=vss2=0v; note 1 , note 2 ) parameter symbol min max units power supplies: analog avdd ? 0.3 6.0 v digital dvdd ? 0.3 6.0 v charge pump cvdd ? 0.3 4.0 v input current, any pin except supplies iin - 10 ma analog input voltage(lisel,risel,lin1-4, rin1-4 pins) vina ? 0.3 avdd+0.3 v digital input voltage ( note 3 ) vind ? 0.3 dvdd+0.3 v ambient temperature (powered applied) ta ? 20 85 c storage temperature tstg ? 65 150 c note 1. all voltages with respect to ground. note 2. vss1 and vss2 must be connected to the same analog ground plane. note 3. pdn, scl, sda, mclk, bick, lrck pins warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (vss1=vss2=0v; note 1 ) parameter symbol min typ max units analog avdd 4.5 5.0 5.5 v power supplies digital dvdd 3.0 3.3 3.6 v ( note 4 ) charge pump cvdd 3.0 3.3 3.6 v dvdd-cvdd vdd -0.3 0 +0.3 v note 4. the power up sequence between avdd, dvdd and cvdd is not critical. in slave mode, the ak5367a must be power up at the pdn pin = ?l?. in master mode, the ak5367a must be power up at the pdn pin = ?l?, or when dvdd is powered up, mclk clock must input and the ak 5367a must be reset by the pdn pin=?l?. the internal register data is unknown until pdn pin=?l?. the power on/off sequence between avdd, dvdd and cvdd is not critical, however when dvdd is powered off, all digital input pins must be left floating or held to vss. the power off is means that avdd, cvdd a nd dvdd are floating or short to vss. warning: akemd assumes no responsibility for the usage beyond the conditions in this datasheet. ms0967-e-00 2008/05 - 6 -
[ak5367a] analog characteristics (ta=25 c; avdd=5.0v, dvdd=cvdd=3.3v; vss1=vss2=0v; fs=48khz,96khz; bick=64fs; signal frequency=1khz; 24bit data; measurement frequency=20hz 20khz at fs=48khz, 40hz 40khz at fs=96khz; unless otherwise specified) parameter min typ max units pre-amp characteristics: feedback resistance 10 50 k s/(n+d) ( note 5 ) - 100 db s/n (a-weighted) ( note 5 ) - 108 db load resistance r l ( note 6 ) 15 k load capacitance c l ( note 6 ) 20 pf adc analog input characteristics: ( ) note 7 resolution 24 bits input voltage ( note 8 ) 2.7 3.0 3.3 vpp ? 1dbfs 82 90 db fs=48khz bw=20khz ? 60dbfs - 39 db s/(n+d) ? 1dbfs - 90 db fs=96khz bw=40khz ? 60dbfs - 37 db dr ( ? 60dbfs, a-weighted) 94 102 db s/n (a-weighted) 94 102 db interchannel isolation (fs=48khz) ( note 9 ) 85 96 db interchannel gain mismatch 0.1 0.5 db gain drift 100 - ppm/ c power supply rejection ( note 10 ) - 50 db power supplies power supply current normal operation (pdn pin = ?h?) ma 23 15.5 avdd ma 4 2.5 cvdd ma 3 2 dvdd (fs=48khz) ma 6 4 dvdd (fs=96khz) power down mode (pdn pin = ?l?) ( note 11 ) a 100 10 avdd+dvdd note 5. this value is measured at lout and rout pins using ri= 47k , rf= 24 k when the input signal voltage is 2vrms. note 6. this value of r l and c l are load resistance and capac itance that the lout and rout pins can drive. r l does not include the feedback resistor (rf) and the input impedance of the lisel/risel pins. the value of c l does not include the internal impedance of the ak5367a. note 7. this value is measured via the following path. pre-amp adc.(ri= 47k , rf= 24 k ) note 8. input voltage to lisel and risel pins is proportional to avdd voltage. typ. vin = 0.6 x avdd (vpp) note 9. 93db(typ.) at fs=96khz. note 10. psr is applied to avdd a nd dvdd with 1khz, 50mvpp sine wave. note 11. all digital input pins are held dvdd or vss2. ms0967-e-00 2008/05 - 7 -
[ak5367a] adc lopin lisel lin1 lout 0v r i r f r i r i 0v c1=10 f r i lin2 lin3 lin4 ak5367a r l c l - + figure 2. pre-amp circuit ms0967-e-00 2008/05 - 8 -
[ak5367a] filter characteristics (fs=48khz) (ta= ? 20 85 c; avdd=4.5 5.5v; dvdd=cvdd=3.0 3.6v) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 12 ) 0.1db pb 0 18.9 khz ? 0.2db - 20.0 - khz ? 3.0db - 23.0 - khz stopband sb 28 khz passband ripple pr 0.04 db stopband attenuation sa 68 db group delay distortion gd 0 s group delay ( note 13 ) gd 20 1/fs adc digital filter (hpf): frequency response ( note 12 ) ? 3db fr 1.0 hz ? 0.1db 6.5 hz filter characteristics (fs=96khz) (ta= ? 20 85 c; avdd=4.5 5.5v; dvdd=cvdd=3.0 3.6v) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 12 ) 0.1db pb 0 37.8 khz ? 0.2db - 40.0 - khz ? 3.0db - 46.0 - khz stopband sb 56 khz passband ripple pr 0.04 db stopband attenuation sa 68 db group delay distortion gd 0 s group delay ( note 13 ) gd 20 1/fs adc digital filter (hpf): frequency response ( note 12 ) ? 3db fr 2.0 hz ? 0.1db 13.0 hz note 12. the passband and stopband frequencies scale with fs. for example, pb= 18.9khz@ 0.1db is 0.39375 x fs, (fs=48khz). note 13. the calculated delay time induced by digital f iltering. this time is from the input of an analog signal to the setting of 24bit data both channels to the adc output register for adc. dc characteristics (ta=-20 c 85 c; avdd=4.5 5.5v; dvdd=cvdd=3.0 3.6v) parameter symbol min typ max units high-level input voltage vih 70%dvdd - - v low-level input voltage vil - - 30%dvdd v high-level output voltage (iout= ? 1ma) voh dvdd ? 0.5 - - v low-level output voltage (except sda pin: iout=1ma) vol - - 0.5 v (sda pin: iout=3ma) vol - - 0.4 v input leakage current iin - - 10 a ms0967-e-00 2008/05 - 9 -
[ak5367a] switching characteristics (ta=-20 c 85 c; avdd=4.5 5.5v; dvdd=cvdd=3.0 3.6v; c l =20pf) parameter symbol min typ max units master clock timing mhz 24.576 8.192 fclk 512fs, 256fs frequency ns 16 tclkl pulse width low ns 16 tclkh pulse width high mhz 36.864 12.288 fclk 768fs, 384fs frequency ns 10.5 tclkl pulse width low ns 10.5 tclkh pulse width high lrck frequency fs 32 96 khz duty cycle slave mode 45 55 % master mode 50 % audio interface timing slave mode ns 160 tsck bick period ns 65 tsckl bick pulse width low ns 65 tsckh pulse width high ns 30 tlrsh lrck edge to bick ? ? ( note 14 ) ns 30 tshlr bick ? ? to lrck edge ( note 14 ) lrck to sdto (msb) (except i 2 s mode) bick ? ? to sdto tlrs tssd 35 35 ns ns master mode bick frequency fsck 64fs hz bick duty dsck 50 % bick ? ? to lrck tmslr ? 20 20 ns bick ? ? to sdto tssd ? 20 35 ns control interface timing (i 2 c bus mode): scl clock frequency - 400 khz fscl bus free time between transmissions 1.3 - s tbuf start condition hold time 0.6 - s thd:sta (prior to first clock pulse) clock low time 1.3 - s tlow clock high time 0.6 - s thigh setup time for repeated start condition 0.6 - s tsu:sta sda hold time from scl falling ( note 15 ) 0 - s thd:dat sda setup time from scl rising 0.1 - s tsu:dat rise time of both sda and scl lines - 0.3 s tr fall time of both sda and scl lines - 0.3 s tf setup time for stop condition 0.6 - s tsu:sto pulse width of spike noise 0 50 ns tsp suppressed by input filter cb capacitive load on bus - 400 pf note 14. bick rising edge must not occur at the same time as lrck edge. note 15. data must be held long enough to bridge the 300ns-transition time of scl. ms0967-e-00 2008/05 - 10 -
[ak5367a] parameter symbol min typ max units reset timing tpd 150 ns pdn pulse width ( note 16 ) tpdv 4388 1/fs pdn ? ? to sdto valid at slave mode ( note 17 ) tpdv 4385 1/fs pdn ? ? to sdto valid at master mode ( note 17 ) note 16. the ak5367a can be reset by bringing the pdn pin = ?l?. note 17. this cycle is the number of lrck rising edges from the pdn pin = ?h?. ms0967-e-00 2008/05 - 11 -
[ak5367a] timing diagram 1/fclk mclk tclkh tclkl vih vil 1/fs lrck vih vil tsck bick tsckh tsckl vih vil figure 3. clock timing lrck vih vil tshlr bick vih vil tlrs sdto 50%dvdd tlrsh tssd figure 4. audio interface timing (slave mode) ms0967-e-00 2008/05 - 12 -
[ak5367a] lrck bick 50%dvdd sdto 50%dvdd tssd tmslr dsck 50%dvdd figure 5. audio interf ace timing (master mode) thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp figure 6. i 2 c bus mode timing tpd pdn vil pdn vih vil tpdv sdto 50%dvdd figure 7. power down & reset timing ms0967-e-00 2008/05 - 13 -
[ak5367a] operation overview system clock mclk, bick and lrck clocks are required. the lrck clock input must be synchronized with mclk, however the phase is not critical. table 1 shows the relationship of typical sampling frequency and the system clock frequency. the mclk, bick and master/slave mode setting are selected by cks2-0 bits( table 2 ). in slave mode, all external clocks (mclk, bick and lrck) must be present unless the pdn pin = ?l?. if these clocks are not provided, the ak5367a may draw excess current due to its use of internal dynamically refreshed logic. if the external clocks are not present, place the ak5367a in powe r-down mode (pdn pin = ?l?). in master mode, the master clock (mclk) must be provided unless the pdn pin = ?l?. it is not necessary to reset by bringing the pdn pin ?l? when clocks and fs are changed. they should be changed afte r soft mute (smute bit = ?1?) to avoid switching noise. mclk fs 256fs 384fs 512fs 768fs 32khz 8.192mhz 12.288mhz 16.384mhz 24.576mhz 44.1khz 11.2896mhz 16.9344mhz 22.5792mhz 33.8688mhz 48khz 12.288mhz 18.432mhz 24.576mhz 36.864mhz 96khz 24.576mhz 36.864mhz n/a n/a table 1. system clock example (n/a: not available) mode cks2 cks1 cks0 master/slave mclk bick 256/384fs (32k d fs d 96k) t 48fs or 32fs 0 0 0 0 slave 512/768fs (32k d fs d 48k) ( note 18 ) (default) 1 0 0 1 reserved 2 0 1 0 master 256fs (32k d fs d 96k) 64fs 3 0 1 1 master 512fs (32k d fs d 48k) 64fs 4 1 0 0 reserved 5 1 0 1 reserved 6 1 1 0 master 384fs (32k d fs d 96k) 64fs 7 1 1 1 master 768fs (32k d fs d 48k) 64fs note 18. the sdto output is 16bit when bick=32fs input. table 2. operation mode select ms0967-e-00 2008/05 - 14 -
[ak5367a] audio interface format table 3 two kinds of data formats can be chosen with the dif bit ( ). in both modes, the serial data is in msb first, 2?s compliment format. the sdto is clocked out on the falling e dge of bick. the audio interface supports both master and slave modes. in master mode, bick and lrck are output with the bick frequency fixed to 64fs and the lrck frequency fixed to 1fs. mode dif bit sdto lrck bick(slave) bick(master) figure 64fs 0 0 24bit, msb justified h/l t 48fs or 32fs figure 8 (default) 1 1 24bit, i 2 s compatible 64fs l/h t 48fs or 32fs figure 9 table 3. audio interface format lrck bick(64fs) sdto(o) 0 23 22 1 2 4 0 20 21 24 31 0 12 23 22 0 10 23 2220 21 31 23:msb, 0:lsb lch data rch data 24 321 22 23 23 1234 figure 8. mode 0 timing lrck bick(64fs) sdto(o) 0 23 22 1 2 4 0 25 21 24 0 12 23 22 0 10 22 25 21 24 321 22 23 23 1234 3 23:msb, 0:lsb lch data rch data figure 9. mode 1 timing master mode and slave mode the ak5367a becomes slave mode when it is in the power-down mode (pdn pin = ?l?) or exiting power-down. after exiting the power-down mode, master mode should be set by cks2-0 bits. in master mode, lrck and bick pins are floating until cks2 -0 bits fixed. therefore bick and lrck pins must be connected with 100 k : pull-up or pull-down resistance. ms0967-e-00 2008/05 - 15 -
[ak5367a] digital high pass filter the adc has a digital high pass filter for dc offset cancellation. the cut-off frequency of the hpf is 1.0hz (@fs=48khz) and scales with sampling rate (fs). power-down the ak5367a is placed in the power-down mode by bringing the pdn pin = ?l? and the digital filter is also reset at the same time. this reset must always be executed after power-up. at the power-down mode, the vcom voltage is vss1. after exiting the power-down mode, the charge pump circuit is powered up, then pre-amp circuit is automatically powered up and an analog initialization cycle starts( figure 10 ). therefore, the output data sdto becomes available after 4388 x lrck cycles at slave mode, and 4385 x lrck cycles in master mode. in the initialization, the both channel of adc output is ?0? of 2?s complement. af ter the initialization, the adc output is settled equal to anal og input signal.(the setting time is long as group delay) a dc internal state pdn pre-amp in (analog) a dc out (digital) clock in mclk,lrck,bick charge pump internal state cvee pin power-down initialize normal operation (1) idle noise gd gd ?0?data (2) (3) (4) idle noise power-down normal operation 0v -cvdd (5) power-up power-down initialize normal operation gd (3) ?0?data idle noise power-down normal operation 0v -cvdd ( 5 ) power-up (1) power supply (avdd, dvdd, cvdd) (2) power-up power-up (2) notes: (1) 4388/fs at slave mode, 4385/fs at master mode. (2) analog output corresponding to digital input has group delay (gd). (3) adc output is ?0? data at the power-down mode. (4) place the ak5367a in power-down mode if mclk, bick and lrck are not present. (5) power-up time of charge pump circuit. 260/fs (slave mode), 257/fs (master mode). figure 10. power-down/up sequence example ms0967-e-00 2008/05 - 16 -
[ak5367a] system reset the ak5367a must be reset once by bringing the pdn pin ?l? after power-up. at the slave mode, the internal timing starts clocking by the rising edge (falling edge at mode 1) of lrck after exiting from reset and power down state by mclk. the ak5367a is in power-down stat es until the lrck is input. at master mode, bringing the pdn pin ?h? and exiting from reset and power down state by mclk input. soft mute operation soft mute operation is performed in the digital domain of the adc output. when smute bit goes ?1?, the adc output data is attenuated to f within 1024 lrck cycles. when the smute bit returned ?0?, the mute is cancelled and the output attenuation gradually changes to 0db within 1024 lrck cycles. if the soft mute is cancelled before mute state after starting of the operation, the attenuation is discontinued a nd returned to 0db. the soft mu te is effective for changing the signal source without stopping the signal transmission. smute bit attenuation 1024/fs 0db - f 1024/fs (1) (2) sdto output data ?0? data figure 11. soft mute function notes: (1) the output signal is attenuated by f within 1024 lrck cycles (1024/fs). (2) if the soft mute is cancelled before the mute, the attenuation is discontinued and returned to 0db by the same cycle. input selector the ak5367a includes 4ch stereo input selectors. the input selector is 4 to 1 selector and set by sel2-0 bits ( table 4 ). sel2 bit sel1 bit sel0 bit input selector 0 0 0 lin1 / rin1 0 0 1 lin2 / rin2 0 1 0 lin3 / rin3 0 1 1 lin4 / rin4 1 0 0 all off (note) (default) table 4. input selector note: the lout, rout pin are 0v. ms0967-e-00 2008/05 - 17 -
[ak5367a] [input selector switching sequence] the input selector should be changed after soft mute to avoid the switching noise of the input selector ( figure 12 ). 1. enable soft mute before changing channel. 2. change channel. 3. disable soft mute. smute bit a ttenuation channel 0db - (1) (2) lin1/rin1 lin2/rin2 (1) figure 12. input channel switching sequence example note: (1) the output signal is attenuated by ? within 1024 lrck cycles (1024/fs). (2) when changing channels, the input channel should be changed during (2). the period of (2) should be around 200ms because there is some dc difference between the channels. ms0967-e-00 2008/05 - 18 -
[ak5367a] pre-amp and input attenuator the input atts are constructed by adding the input resistor (ri) for lin1-4/rin1-4 pins and the feedback resistor (rf) between lopin/ropin pin and lout/rout pin ( figure 13 ). the input voltage range of the lisel/risel pin is typically 0.6 x avdd (vpp). if the input volta ge of the input selector exceeds typ. 0.6 x avdd, the input voltage of the lisel/risel pins must be attenuated to 0.6 x avdd by the input atts. table 5 shows the example of ri and rf. lin1 lin2 lin3 lin4 rin1 rin2 rin3 rin4 lisel ropin rout risel lopin lout pre-amp pre-amp ri ri ri ri ri ri ri ri rf rf c1=10 f adc adc c1=10 f figure 13. pre-amp and input att x example for input range input range att gain [db] lisel/risel pin ri [k : ] rf [k : ] 4vrms 47 12 1.02vrms 11.86 2vrms 47 24 1.02vrms 5.84 1vrms 47 47 0 1vrms table 5. input att example note: the value of ri is over 10k : . ms0967-e-00 2008/05 - 19 -
[ak5367a] charge pump circuit the internal charge pump circuit generates negative voltage (cvee) from cvdd voltage. the generated voltage is used for pre-amp. vss2 cp cn ak5367a charge pump cp=0.1 f cout=1 f cvdd cvee negative voltage to pre-amp figure 14. charge pump circuit ms0967-e-00 2008/05 - 20 -
[ak5367a] serial control interface the ak5367a supports the first-mode i 2 c-bus system (max: 400khz). the pull-up resistance of sda,scl pins should be connected below the voltage of dvdd+0.3v. 1. write operations figure 15 shows the data transfer sequence for the i 2 c-bus mode. all commands are preceded by start condition. a high to low transition on the sda line while scl is high indicates start condition ( figure 21 ). after the start condition, a slave address is sent. this address is 7 bits long followed by the eighth bit that is a data direction bit (r/w). the most significant 7 bits of the slave address are fixed as ?0110001?. if the slave address matches that of the ak5367a, the ak5367a generates an acknowledge and the operati on is executed. the master must generate the acknowledge-related clock pulse and release the sda line (high) during the acknowledge clock pulse ( figure 22 ). a r/w bit value of ?1? indicates that the r ead operation is to be executed. ?0? indicates that the write operation is to be executed. the second byte consists of the control register address of the ak5367a. the format is msb first, and those most significant 6-bits are fixed to zeros ( figure 17 ). the data after the second byte contains control data. the format is msb first, 8bits ( figure 18 ). the ak5367a generates an acknowledge after each by te is received. a data transfer is always terminated by a stop condition generated by the master. a low to high transition on the sda line while scl is high defines a stop condition ( figure 21 ). the ak5367a can perform more than one byte write operation pe r sequence. the master can transmit more than one byte instead of terminating the write cycle afte r the first data byte is transferred. af ter receiving each data packet the internal 2-bit address counter is incremented by one, and the next data is automatically taken into the next address. if the address exceeds 02h prior to generating the stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the data on the sda line must remain stable during the high period of the clock. the high or low state of the data line can only change when the cloc k signal on the scl line is low ( figure 23 ) except for the start and stop conditions. sda slave address s s t a r t r/w="0" a c k sub address(n) a c k data(n) a c k data(n+1) a c k a c k data(n+x) a c k p s t o p figure 15. data transfer sequence at the i 2 c-bus mode 0 1 1 0 0 0 1 r/w figure 16. the first byte 0 0 0 0 0 0 a1 a0 figure 17. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 18. byte structure after the second byte ms0967-e-00 2008/05 - 21 -
[ak5367a] 2. read operations set the r/w bit = ?1? for the read operation of the ak5367a. the master can read the next address?s data by generating an acknowledge instead of terminating the write cycle after the receipt of the fi rst data word. after receiving each data packet the internal 2-bit address counter is incremented by one, and the next data is automatically taken into the next address. if the address exceeds 02h prior to generating a stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the ak5367a supports two basic read operations: current address read and random address read. 2-1. current address read the ak5367a contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) were to address ?n ?, the next current read operation would access data from the address ?n+1?. after r eceipt of the slave address with r/w b it set to ?1?, the ak5367a generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. if the master doe s not generate an acknowle dge but generates a stop condition, the ak5367a ceases transmission. sda slave address s s t a r t r/w="1" a c k a c k data(n+1) a c k data(n+2) a c k a c k data(n+x) a c k p s t o p data(n) figure 19. current address read 2-2. random address read the random read operation allows the master to access any memo ry location at random. prior to issuing the slave address with the r/w bit ?1?, the master must first perform a ?dummy? write operation. th e master issues start request, a slave address (r/w bit = ?0?) and then the register address to read. after the register address is acknowledged, the master immediately reissues start request and the slave addre ss with the r/w bit ?1?. the ak5367a then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. if the master does not generate an acknowledge but generates stop conditi on, the ak5367a ceases transmission. sda slave address s s t a r t r/w="0" a c k a c k a c k data(n) a c k data(n+x) a c k p s t o p sub address(n) s slave address r/w="1" s t a r t data(n+1) a c k a c k figure 20. random address read ms0967-e-00 2008/05 - 22 -
[ak5367a] scl sda stop condition start condition s p figure 21. start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 22. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 23. bit transfer on the i 2 c-bus ms0967-e-00 2008/05 - 23 -
[ak5367a] register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power down control 0 0 0 0 0 0 0 pwn 01h input selector control 0 0 0 0 0 sel2 sel1 sel0 02h clock & format control 0 0 0 dif cks2 cks1 cks0 smute pdn pin = ?l? resets the registers to their default values. note: unused bits must contain a ?0? value. only write to address 00h to 02h. register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power down control 0 0 0 0 0 0 0 pwn r/w rd rd rd rd rd rd rd r/w default 0 0 0 0 0 0 0 1 pwn: power down control 0: power down. all registers are not initialized. 1: normal operation (default) ?0? powers down all sections and then adc do not operate. the contents of all register are not initialized and enabled to write to the registers. addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h input selector control 0 0 0 0 0 sel2 sel1 sel0 r/w rd rd rd rd rd rd r/w r/w default 0 0 0 0 0 1 0 0 table 4 ) sel2-0: input selector ( initial values are ?100?. addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h clock & format control 0 0 0 dif cks2 cks1 cks0 smute r/w rd rd rd r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 smute: soft mute control 0: normal operation (default) 1: sdto outputs soft-muted. cks2-0: operation mode select ( table 2 ) initial values are ?000?. dif: audio interface format ( table 3 ) initial values are ?0? (24bit, msb justified). ms0967-e-00 2008/05 - 24 -
[ak5367a] system design figure 24 shows the system connection diagram. the evaluati on board (akd5367a) demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. lin1 2 rin1 3 lin2 4 rin2 5 lin3 6 rin3 7 lin4 8 rin4 9 lisel 10 risel 11 rout 12 ropin 13 vss1 29 dvdd 28 lrck 27 mclk 26 bick 25 sdto 24 scl 23 sda 22 pdn 21 cp 20 cn 19 cvdd 18 ak5367a 14 15 17 16 lopin lout vss2 cvee analog vcom 1 avdd 30 + 0.1u 10u a nalog 5v + 0.1u dsp or p digital 3.3v + 0.1u 10u digital 3.3v 0.1u + 10u + 1u 10u + 24k ground digital ground analog in 47k 47k 47k 47k 47k 47k 47k 47k 0.1u 2.2u + 24k + 10u figure 24. typical connection diagram ms0967-e-00 2008/05 - 25 -
[ak5367a] 1. grounding and power supply decoupling the ak5367a requires careful attention to power s upply and grounding arrangements. avdd, dvdd and cvdd are usually supplied from the analog supply in the system. alternatively if avdd, dvdd and cvdd are supplied separately, the power up sequence is not critical. vss1 and vss2 of the ak5367a must be connected to analog ground plane. system analog ground and digital ground must be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors must be as near to the ak5367a as possible, with the small value ceramic capacitor being the closest. 2. voltage reference inputs the differential voltage between avdd and vss1 sets the an alog input range. vcom is a signal common of this chip. an electrolytic capacitor 2.2f parallel with a 0.1f ceramic capacitor attached to the vcom pin eliminates the effects of high frequency noise. no load current may be drawn from the vcom pin. all signals, especially clocks, should be kept away from the vcom pins in order to avoid unwanted coupling into the ak5367a. 3. analog inputs an analog input of ak5367a is single-ended input to pre-amp through the external resistor. for input signal range, adjust feedback resistor so that pre-amp output may become the input range (typ. 0.6 x avdd vpp) of adc (lisel,risel pin). between the pre-amp output (lout, rout pin) and the adc input (lisel,risel pin) is ac coupled with capacitor. when the impedance of lisel/risel pins is ?r? and the capacitor of between the pre-amp output and the adc input is ?c?, the cut-off frequency is fc = 1/(2 rc). the adc output data format is 2?s compliment. the internal hpf removes the dc offset. the ak5367a samples the analog inputs at 64fs. the digital filter rejects noise above the stop band except for multiples of 64fs. the ak5367a includes an anti-aliasing filter (rc filter) to attenuate a noise around 64fs. 4. attention to the pcb wiring lin1-4 and rin1-4 pins are the summing nodes of the pre-amp. attention should be given to avoid coupling with other signals on those nodes. this can be accomplis hed by making the wire lengt h of the input resistors as short as possible. the same theory also applies to the lopin/ropin pins and feedback resistors; keep the wire length to a minimum. unused input pins among lin1-4 and rin1-4 pins should be left open. when external devices are connected to lout and rout pin, the input impedance is min. 15k . 4. i 2 c bus connection scl and sda pins should be connected to dvdd through the resistor based on i 2 c standard. as there is a protection between each pin and dvdd, the pulled up voltage must be dvdd or lower( figure 25 ). vss2 dvdd ak5367a +3.3v sda pin figure 25. sda pin output ms0967-e-00 2008/05 - 26 -
[ak5367a] package detail a note: dimension "*" does not include mold flash. 0.22 0.1 0.65 *9.7 0.1 1.5max a 1 15 16 30 30pin vsop (unit: mm) 5.6 0.1 7.6 0.2 0.45 0.2 -0.05 +0.10 0.3 0.15 0.12 m 0.08 1.2 0.10 0.10 +0.10 -0.05 material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatme nt: solder (pb free) plate ms0967-e-00 2008/05 - 27 -
[ak5367a] marking akm AK5367AEF xxxbyyyyc xxxbyyyyc date code identifier xxxb: lot number (x: digit num ber, b: alpha character) yyyyc: assembly date (y: digit number, c: alpha character) revision history date (yy/mm/dd) revision reason page contents 08/05/23 00 first edition mportant notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei emd corporation (akemd) or authorized distributors as to current status of the products. z akemd assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akemd products are neither intended nor au thorized for use as critical components note 1) in any safety, life support, or other hazard related device or system note 2) , and akemd assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akemd. as used here: note1) a critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fi elds, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akemd pr oducts, who distributes, dis poses of, or otherwise places the product with a third party, to notify such third party in advance of the above cont ent and conditions, and the buyer or distributor agrees to assume any and all re sponsibility and liability for and hold akemd harmless from any and all claims arising from the use of said product in the absence of such notification. ms0967-e-00 2008/05 - 28 -

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