View LC749880T_4112073.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

51408hkim 20080319-s00007 no.a1186-1/17 LC749880T overview LC749880T is an lsi to display the converted ntsc/pal analog video signals in the liquid crystal panel of maximum vga size. this product performs a/d conversion, yc separation, color decoding, ip conversion, resolution conversion, and various enhancements according to the panel. when combined with a microcomputer and lcd panel, this product can readily makes up a video signal processing circuit for flat panel display features (1) analog input ? 3ch a/d converter incorporated ? cvbs, s-video,ycbcr/ypbpr input (2) yc separation video decoder ? adaptive 3-line comb filter ? agc, acc (3) resolution conversion ? interlace - progressive conversion ? expansion/compression possible independently in horizontal and vertical directions (4) enhancing functions ? adjusting the tv picture quality: contour co rrection, color, hue, luminance, contrast ? adjusting the panel display picture quality: white balance, black balance, correction ? color exciter (6-phase rgbymc independent saturation adjustment) ? shadow adjuster (emphaizing the three-dimensionality) ? dither (8bit/6bit) continued on next page. ordering number : ena1186 cmos ic silicon gate image controller lsi for lcd-tv specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
LC749880T no.a1186-2/17 continued from preceding page. (5) panel interface ? video signal of either rgb 24-bit (single phase) or 18-bit signal output ? timing controller output for panel driver (6) others ? osd i/f: r, g, b, en ? clock generator (pll) incorporated ? i 2 c bus interface incorporated lsi specifications ? supply voltage core: 1.8v, i/o block: 3.3v ? maximum operating frequency: 27mhz ? package: tqfp120 principal applications ? lcd tv analog input cvbs 2ch: composite video input 2channels s-video: s video input 1channel ycbcr/ypbpr (480i/576i input compatible): component input 1channel yc separation video decoder a video decoder that converts either the ntsc/pal video signal or component video signal into the digital video signal is incorporated, which is compatible with the composite video signal, s video signal, and component video signal (480i). resolution conversion two-dimensional ip conversion, and expansion/contraction processings available 1. interlace progressive co nversion (ip conversion) two-dimensional ip conversion possible for ntsc/pal input 2. horizontal vertical scaler functions expansion/contraction to vga size possible. expansion/contraction possible independently in horizontal and vertical directions. full-screen display and zoom display possible. enhancement functions various enhancement functions are available. picture quality adjustment can be made ap propriate to characteristics of lcd-tv. 1. adjusting the tv picture quality 1-1. contour correction (horizontal vertical) contour correction of the input luminance signal . adquate peaks are added around the contour. in this case, coring adjustment is possible to prevent emphasizing of the peak amount and extremely small noises. 1-2. color saturation can be adjusted by adjusting the color gain of input color-difference signal. 1-3. hue the hue of the screen as a whole can be adjusted. 1-4. luminance luminance of the screen as a whole can be adjusted. 1-5. contrast brightness of the screen as a whole can be adjusted.
LC749880T no.a1186-3/17 2. adjusting the panel picture quality 2-1. white balance white balance adjustment appropriate to lcd-tv is possible. 2-2. black balance black balance adjustment approp riate to lcd-tv is possible. 2-3. correction correction appropriate to lcd-tv is possible. the correction curve may be made programmable by means of lut correction can be made independently by rgb. 3. color exciter a total of 12 colors including red, green, blue, magenta, yellow, cyan, and colors between these colors can be adjusted independently in terms of saturation. 4. shadow adjuster the three-dimensionality can be emphasized by adding the shading through addition of the adequate peaks before and after the detected input signal contour. 5. dither in the case of 6-bit output, pseudo-mulltiple tone processing enables the output equivalent to the 8-bit output. panel interface 1. video output digital rgb 24-bit/18-bit output possible 2. synchronizing signal (timing controller) output timing controller output and synchronizing signal output (horizontal/vertical synchronizing signal, data enable) possible. the output can be selected according to specifications of lcd module. others 1. osd interface this lsi has no osd. osd can be interfaced with the external osd microcomputer by means of the input pin (pin nos.: 105 to 108) and output pin (pin nos.: 96,103,104). interlace synchronization/progressive synchronization can be changed over according to register setting. the closed caption can be displayed. 2. i 2 c bus interface the internal register is controlled by means of i 2 c. the slave address can be changed over by controlling the ?i 2 csel? pin (pin no: 33) according to the system. i 2 csel ?l? slave address ?88h? i 2 csel ?h? slave address ?8ah? i/o specifications 1. input signals signal type no. of pins pin symbol description remarks 1 cvbs1 composite video signal input 1 1 cvbs2 composite video signal input 2 1 crin component video signal input cr 1 cbin component video signal input cb 1 yin component video signal input y 1 sy s-video signal input y video signal 1 sc analog i/f s-video signal input c 1 vsi vertical synchronization vertical sync hronizing signal input pin (from sync. sep) synchronizing signal 1 hsi horizontal synchronization horizontal synchronizing signal input pin (from sync. sep.) 1 blkin osd signal input enable (from -con) 1 rin osd signal r input pin (from -con) 1 gin osd signal g input pin (from -con) osd signal 1 bin osd i/f osd signal b input pin (from -con) continued on next page
LC749880T no.a1186-4/17 continued from preceding page. signal type no. of pins pin symbol description remarks 1 xin clock crystal oscillator input pin (27mhz) clock (1) (dclko3) clock (gpio pin) clock input when mode 0, 1 system reset 1 reset sy stem reset system reset input pin (lo-active) i/f mode selection 3 mode i/f mode select ion i/f mode selection signal input pin 0: two-phase 6-bit output (tcon signal output) 1: single-phase 8-bit/6-bit output (rgb, tcon signal output) dclko3; 3.375mhz output 2: single-phase 8-bit/6-bit output (rgb, tcon signal output) dclko3; clock input 3,4: decoder output (rgb/ycbcr/yc (register setting), synchronizing signal output) 5: single-phase 8-bit/6-bit output (rgb, synchronizing signal output) * others not applicable because they are not defined. 2. output signals signal type no. of pins pin symbol description remarks (36) (vp) digital i/f (gpio pin) video signal output pin. mode pin. pin function changed through register setting. 6-bit output for output after dither processing for single-phase 8-bit output(mode 0) vp00 to vp07: r0 to r7(cb0 to cb7) vp08 to vp15: b0 to b7(cb0 to cr7/cbcr0 to cbcr7) vp16 to vp23: g0 to g7(y0 to y7) * ( ) shows the ycbcr 4:4:4/4:2:2 output (mode=3,4) for single-phase 6-bit output (mode 0) vp00 to vp05: r0 to r5 vp08 to vp13: b0 to b5 vp16 to vp21: g0 to g5 for two-phase 6-bit output (mode=0) vp00 to vp05: ro0 to ro5 vp18 to vp23: re0 to re5 vp06 to vp11: bo0 to bo5 vp24 to vp29: be0 to be5 vp12 to vp17: go0 to go5 vp30 to vp35: ge0 to ge5 * xo: odd-numbered picture elements xe: even-numbered picture elements video signal 1 svo analog i/f internal analog video signal output (1) (tim1) vertical synchronizing (gpio pin) applicable when mode=3, 4, and 5. synchronizing period, polarity reversal possible synchronizing signal (1) (tim2) horizontal synchronization (gpio pin) applicable when mode 0. synchronizing period. polarity reversal possible data enable signal (1) (tim0) data enable (gpio pin) applicable when mode=3, 4, and 5. h,v composite data enable output. position, polarity reversal possible continued on next page
LC749880T no.a1186-5/17 continued from preceding page. signal type no. of pins pin symbol description remarks (1) (grst) when mode=0, the gate reset signal output/clamp pulse output/pwm3 output selectable through register selection when mode 0, the gate reset signal output/clamp pulse output selectable through register selection grst: pulse width, position, and polarity reversal possible 1 flm when mode=0, 1, and 2, gate start pulse signal output pulse width, position, polarity reversal possible. hi-z when flm2 is used 1 oe when mode=0, 1, and 2, gate output enable signal output. pulse width, position, pola rity reversal possible. 1 cpv when mode=0, 1, and 2, gate clock signal output. pulse width, position, pola rity reversal possible. 1 strb when mode=0, 1, and 2, source strobe signal output. pulse width, position, pola rity reversal possible. 1 sp when mode=0, 1, and 2, source start pulse signal output. pulse width, position, polarity reversal possible. hi-z when sp2 is used 1 dexr when mode=0, 1, and 2, source picture element reversal signal output. when mode=0, dexr output of odd-numbered picture elements 1 pol when mode=0, 1, and 2, source voltage polarity selection signal output. position adjustment, 1 line/2 line reversal and 1 frame/2 frame reversal possible (1) (tim0) when mode=0, 1, and 2, flm2 output through register setting pulse width, position, polarity reversal possible. hi-z when flm is used (1) (tim1) when mode=0,1, and 2, sp2 output through register setting pulse width, position, polarity reversal possible. hi-z when sp2 is used tcon signal (1) (tim2) tcon signal (gpio pin) when mode=0, dexr (dexr_e) output of even-numbered picture elements 1 dclko dot clock picture element clock output. polarity reversal, 1/2 output possible 1 (dclko3) when mode=0 and 1, clock output (3.357mhz) clock 1 xout clock crystal oscillator output pin 1 vso vertical synchronizing signal output for osd (to -con) pulse width, position, pola rity reversal possible. 1 hso horizontal synchronizing signal output for osd (to -con) pulse width, position, pola rity reversal possible. for osd signal 1 dclko2 osd i/f picture-element clock output for osd (to -con) polarity reversal, 1/2 output possible (1) (vp32) when mode 0, pwm1 output through register setting. pulse width, position, pola rity reversal possible. (1) (vp35) when mode 0, pwm2 output/pwm3 output/clamp pulse output selectable through register setting. pwm2, 3: pulse width, position, polarity reversal possible. pwm output (1) (grst) pwm signal (gpio pin) when mode=0, pwm3 output/gr st output/clamp pulse output selectable through register setting pwm3: pulse width, position, polarity reversal possible. (1) (vp35) when mode 0, clamp pulse output/pwm2 output/pwm3 output selectable through register setting clamp pulse: pulse width and position adjustment possible. clamp pulse (1) (grst) clamp pulse (gpio pin) when mode=0, clamp pulse output/grst output/pwm3 output selectable through register setting. when mode 0, clamp pulse output/grst output selectable through register setting clamp pulse: pulse width and position adjustment possible. * the signals in parentheses show that one pin has multiple functions or acts as the i/o pin. selection can be made with the mode pin or through register setting.
LC749880T no.a1186-6/17 3. control signal signal type no. of pins pin symbol description remarks 1 i 2 csel slave changeover i 2 c bus bus slave address setting (normally ?l?) ?l?: 88 h , ?h?: 8a h 1 sda data bus i 2 c bus 1 scl bus clock slave address for internal register setting and internal status output: ?1000100+(r/w)? 4. other signals signal type no. of pins pin symbol description remarks 1 scanen test pin (normally, ?l?) scan test 1 scanmod scan test test pin (normally, ?l?) test 1 test test test pin (normally, ?l?) 3 vrt adc top level reference output 3 vrb adc bottom level reference output 1 nbias adc bias voltage output adc/afe 1 vref adc/afe adc reference output 1 vrtc agc control voltage input 1 lpfo agc pwm output agc 1 lpfv dd agc agc pwm output buffer power supply 1 chagpup charge pump output for built-in pll pll 1 vcor pll range resistor for built-in pll package dimensions unit : mm (typ) 3257a sanyo : tqfp120(14x14) 0.125 120 0.15 0.4 (1.2) 1 14.0 16.0 14.0 16.0 1.2max 0.1 (1.0) 0.5
LC749880T no.a1186-7/17 pin assignment * 1: nc for the mode in which built-in tcon is not to be used. 90 60 5 31 120 91 61 LC749880T crin vrt1 vrb1 av ss 33 cbin av ss 33 sc av dd 33 vrt2 vrb2 nbias vref1 av ss 18 svo av dd 18 yin av ss 33 sy av ss 33 cvbs1 av ss 33 cvbs2 av ss 33 vrt3 vrb3 vrtc rv ss 33 rv dd 33 lpfo lpfv dd vp11(bo5/b3) vp10(bo4/b2) vp09(bo3/b1) vp08(bo2/b0) vp07(bo1/r7) vp06(bo0/r6) vp05(ro5/r5) vp04(ro4/r4) vp03(ro3/r3) vp02(ro2/r2) vp01(ro1/r1) vp00(ro0/r0) tim2(dexr_e/hsync) tim1(flm2/vsync) tim0(sp2/de) pol(*1) dexr(*1) dv dd 18 dv ss dv dd 33 sp(*1) strb(*1) cpv(*1) oe(*1) flm(*1) grst reset i 2 csel scanmod scanen av ss 18 chagpup vcor av dd 18 dclko3 dclko2 dv dd 18 dv dd 33 xin xout dv ss dclko vsi hsi rin gin bin blkin hso vso pdwn scl sda test mode0 mode1 mode2 dv dd 33 dv ss dv dd 18 vp35(ge5/pwm2 or pwm3) vp34(ge4/-) vp33(ge3/exctr2) vp32(ge2/exctr1 or pwm1) vp31(ge1/-) vp30(ge0/-) vp29(be5/-) dv dd 18 dv ss dv dd 33 vp28(be4/-) vp27(be3/-) vp26(be2/-) vp25(be1/-) vp24(be0/-) vp23(re5/g7) vp22(re4/g6) vp21(re3/g5) vp20(re2/g4) vp19(re1/g3) vp18(re0/g2) vp17(go5/g1) vp16(go4/g0) vp15(go3/b7) vp14(go2/b6) vp13(go1/b5) vp12(go0/b4) dv dd 18 dv ss dv dd 33 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 120 115 top view
LC749880T no.a1186-8/17 pin functions i/o format pin no. pin symbol i/o format connected to remarks 1 crin i a analog if analog cr input (adc1) 2 vrt1 o a top level reference voltage connection pin for adc1 3 vrb1 o a bottom level reference voltage connection pin for adc1 4 av ss 33 p analog gnd 5 cbin i a analog if analog cb input (or s-c) (adc2) 6 av ss 33 p analog gnd 7 sc i a analog if analog s-c input (adc2) 8 av dd 33 p analog 3.3v 9 vrt2 o a top level reference voltage connection pin for adc2 10 vrb2 o a bottom level reference voltage connection pin for adc2 11 nbias o a bias voltage connection pin for adc 12 vref1 o a reference voltage connection pin for adc 13 av ss 18 p analog gnd 14 svo o a adc3 input internal analog video signal output 15 av dd 18 p analog 1.8v 16 yin i a analog if analog y input (or s-y,cvbs) (adc3) 17 av ss 33 p analog gnd 18 sy i a analog if analog s-y input (or cvbs) (adc3) 19 av ss 33 p analog gnd 20 cvbs1 i a analog if analog cvbs1 input (adc3) 21 av ss 33 p analog gnd 22 cvbs2 i a analog if analog cvbs2 input (adc3) 23 av ss 33 p analog gnd 24 vrt3 o a top level reference voltage connection pin for adc3 25 vrb3 o a bottom level reference voltage connection pin for adc3 26 vrtc i a agc control voltage input 27 rv ss 33 p analog gnd vref generator circuit analog gnd 28 rv dd 33 p analog 3.3v vref generator circuit analog 3.3v 29 lpfo o a agc pwm output 30 lpfv dd i a agc pwm output buffer power supply 31 scanen i c test pin (normally, lo) 32 scanmod i c test pin (normally, lo) 33 i 2 csel i c i 2 c slave addresses l=0 88, h=0 8a 34 reset i b system reset (active lo) 35 grst i/o g gate reset signal (or test input) 36 flm i/o g gate start signal (or test input) 37 oe i/o g gate oe signal (or test input) 38 cpv i/o g gate lock signal (or test input) 39 strb i/o g source strobe signal (or test input) 40 sp i/o g source start signal (or test input) 41 dv dd 33 p digital 3.3v 42 dv ss p digital gnd 43 dv dd 18 p digital 1.8v 44 dexr i/o g source picture element reversal signal (or test input) 45 pol i/o g source line reversal signal (or test input) 46 tim0 o e data enable signal output/flm2 (register selection) 47 tim1 o e vertical synchronizing si gnal output/sp2 (register selection) 48 tim2 o e horizontal synchronizing signal output 49 vp00 o e video signal output r0/r_odd_0 (mode pin select=0) 50 vp01 o e video signal output r1/r_odd_1 (mode pin select=0) 51 vp02 o e video signal output r2/r_odd_2 (mode pin select=0) continued on next page.
LC749880T no.a1186-9/17 continued from preceding page. i/o format pin no. pin symbol i/o format connected to remarks 52 vp03 o e video signal output r3/r_odd_3 mode pin select=0) 53 vp04 o e video signal output r4/r_odd_4 (mode pin select=0) 54 vp05 o e video signal output r5/r_odd_5 (mode pin select=0) 55 vp06 o e video signal output r6/b_odd_0 (mode pin select=0) 56 vp07 o e video signal output r7/b_odd_1 (mode pin select=0) 57 vp08 o e video signal output b0/b_odd_2 (mode pin select=0) 58 vp09 o e video signal output b1/b_odd_3 (mode pin select=0) 59 vp10 o e video signal output b2/b_odd_4 (mode pin select=0) 60 vp11 o e video signal output b3/b_odd_5 (mode pin select =0) 61 dv dd 33 p digital 3.3v 62 dv ss p digital gnd 63 dv dd 18 p digital 1.8v 64 vp12 o e video signal output b4/g_odd_0 (mode pin select=0) 65 vp13 o e video signal output b5/g_odd_1 (mode pin select=0) 66 vp14 o e video signal output b6/g_odd_2 (mode pin select=0) 67 vp15 o e video signal output b7/g_odd_3 (mode pin select=0) 68 vp16 o e video signal output g0/g_odd_4 (mode pin select=0) 69 vp17 o e video signal output g1/g_odd_5 (mode pin select=0) 70 vp18 o e video signal output g2/r_even_0 (mode pin select=0) 71 vp19 o e video signal output g3/r_even_1 (mode pin select=0) 72 vp20 o e video signal output g4/r_even_2 (mode pin select=0) 73 vp21 o e video signal output g5/r_even_3 (mode pin select=0) 74 vp22 o e video signal output g6/r_even_4 (mode pin select=0) 75 vp23 o e video signal output g7/r_even_5 (mode pin select=0) 76 vp24 i/o g -/video signal output b_even_0 (mode pin select=0) 77 vp25 i/o g -/video signal output b_even_1 (mode pin select=0) 78 vp26 i/o g -/video signal output b_even_2 (mode pin select=0) 79 vp27 i/o g -/video signal output b_even_3 (mode pin select=0) 80 vp28 i/o g -/video signal output b_even_4 (mode pin select=0) 81 dv dd 33 p digital 3.3v 82 dv ss p digital gnd 83 dv dd 18 p digital 1.8v 84 vp29 i/o g -/video signal output b_even_5 (mode pin select=0) 85 vp30 i/o g -/video signal output g_even_0 (mode pin select=0) 86 vp31 i/o g -/video signal output g_even_1 (mode pin select=0) 87 vp32 i/o g -/video signal output g_even_2 (mode pin select=0) 88 vp33 i/o g -/video signal output g_even_3 (mode pin select=0) 89 vp34 i/o g pwm signal/video signal output g_even_4 (mode pin select=0) 90 vp35 i/o g pwm signal/video signal output g_even_5 (mode pin select=0) 91 av ss 18 p analog gnd 92 chagpup o a charge pump output 93 vcor i a range resistor for pll 94 av dd 18 p analog 1.8v 95 dclko3 i/o h clock i/o 96 dclko2 o f clock output (dedicated to microcomputer, with 1/2 or de) 97 dv dd 18 p digital 1.8v 98 dv dd 33 p digital 3.3v 99 xin i crystal oscillator connection pin (27mhz) 100 xout o d crystal oscillator connection pin 101 dv ss p digital gnd 102 dclko o f panel clock output 103 vsi i b vertical synchronizing signal input 104 hsi i b horizontal synchronizing signal input continued on next page.
LC749880T no.a1186-10/17 continued from preceding page. i/o format pin no. pin symbol i/o format connected to remarks 105 rin i c r input of microcomputer osd 106 gin i c g input of microcomputer osd 107 bin i c b input of microcomputer osd 108 blkin i c blk input of microcomputer osd 109 hso o e horizontal synchronizing signal output for microcomputer 110 vso o e vertical synchronizing signal output for microcomputer 111 pdwn i b power down (active lo) 112 scl i b i 2 c bus clock 113 sda i/o g i 2 c bus data 114 test i c test pin (normally, lo) 115 mode0 i c i/f mode pin 116 mode1 i c i/f mode pin 117 mode2 i c i/f mode pin 118 dv dd 33 p digital 3.3v 119 dv ss p digital gnd 120 dv dd 18 p digital 1.8v
LC749880T no.a1186-11/17 pin type i/o type function equivalent circuit applicable pins a analog i/o crin, vrt1, vr b1, cbin, sc, vrt2, vrb2, nbias, vref1, svo, yin, sy, cvbs1, cvbs2, vrt3, vrb3, vrtc, lpfo, lpfvdd, chagpup, vcor b 5v withstand schmidt trigger cmos input* reset, vsi, hsi, pdwn, scl c 5v withstand with pull-down cmos input* scanen, scanmod, i 2 csel, rin, gin, bin, blkin, test, mode0, mode1, mode2 d oscillator circuit i/o xin, xout e 8ma 3-state drive cmos output* tim0, tim1, tim2, vp00, vp01, vp02, vp03, vp04, vp05, vp06, vp07, vp08, vp09, vp10, vp11, vp12, vp13, vp14, vp15, vp16, vp17, vp18, vp19, vp20, vp21, vp22, vp23, hso, vso f 12ma 3-state drive cmos output* dclko2, dclko g 8ma 3-state drive cmos i/o* grst, flm, oe, cpv, strb, sp, dexr, pol, vp24, vp25, vp26, vp27, vp28, vp29, vp30, vp31, vp32, vp33, vp34, vp35, sda h 12ma 3-state drive cmos i/o* dclko3 * : 5v tolerant
LC749880T no.a1186-12/17 electrical characteristics absolute maximum ratings at ta = 25 c, dv ss = 0v, av ss = 0v parameter symbol rating unit maximum supply voltage (i/o) dv dd 33 av dd 33 -0.3 to +4.0 v maximum supply voltage (core) dv dd 18 av dd 18 -0.3 to +2.2 v digital input voltage v i -0.5 to 6.0 v digital output voltage v o -0.3 to v dd + 0.3 v storage temperature tstg -55 to +125 c operating temperature topr -30 to +70 c maximum allowable loss pd max 0.6 w allowable operation range at ta = -30 to +70 c parameter symbol min typ max unit supply voltage (i/o) dv dd 33 av dd 33 3.15 3.3 3.45 v supply voltage (core) dv dd 18 av dd 18 1.71 1.8 1.89 v input voltage range v in 05.5 v i/o pin capacity at ta = 25 c , v dd = v i = 0v parameter symbol conditions min typ max unit input pin cin f=1mhz 10 pf output pin cout f=1mhz 10 pf i/o pin ci/o f=1mhz 10 pf dc characteristics at ta = -30 to +70 c, dv dd 33 = 3.3v5%, dv dd 18 = 1.8v5% parameter symbol conditions min typ max unit cmos compatible 2.0 5.5 v cmos compatible schmidt 2.0 5.5 v input high-level voltage v ih oscillator circuit input 2.0 3.465 v cmos compatible -0.3 +0.8 v cmos compatible schmidt -0.3 +0.8 v input low-level voltage v il oscillator circuit input -0.3 +0.8 v v i =v dd -10 +10 a input high-level current i ih v i =v dd with pull-down resistor +10 +100 a input low-level current i il v i =v ss -10 +10 a cmos 2.4 v output high-level voltage v oh oscillator circuit output 2.4 v cmos 0.4 v output low-level voltage v ol oscillator circuit output 0.4 v output leak current ioz at output of high-impedance -10 +10 a pull-down resistor rdn 43 58 118 k operating current iddop tck=27mhz ma operating current (av dd 33) iddop tck=27mhz gray scale 15 ma operating current (av dd 18) tck=27mhz gray scale 70 ma operating current (dv dd 33) tck=27mhz gray scale 20 ma operating current (dv dd 18) tck=27mhz gray scale 90 ma current drain at rest *1 iddst output release,v i =v ss or v dd 10 a * 1: there is an input pin incorporating pull-down resistor. note that, depending on circuit composition, the current drain at rest may not be guaranteed.
LC749880T no.a1186-13/17 a/d convertor characteristics at ta = -30 to +70 c, dv ss = 0v, av ss = 0v parameter symbol/pin min typ max unit clock frequency fclk 27 mhz clamp pulse width tcl 0.45 s external capacitance analog input coupling capacitance analog video pin 0.01 10 f top level reference fixed capacitance vrtx pin 0.01 f bottom level reference capacitance vrbx pin 0.01 f vref1 bias fixed capacitance vref1 pin 0.01 f nbias bias fixed capacitance nbias pin 0.01 f analog input frequency fain 4mhz analog input amplitude (max amplitude) in the non-agc operation mode fs1ain 1.0 vp-p in the agc operation mode *1 fs2ain 0.6 1.1 vp-p adc reference input voltage in the non-agc operation mode bottom level reference input vrbi 0.65 v in the agc operation mode bottom level reference input vrbi 0.65 v dc characteristics at ta=25 c, v dd 3=3.3v5%,v dd =1.8v5%, dv ss = 0v, av ss = 0v parameter symbol conditions min typ max unit operating supply current 3.3v power supply i dd 3 v dd 3=3.3v 16 ma 1.8v power supply i dd v dd =1.8v fclk=27mhz 16 ma standby supply current 3.3v power supply isb3 v dd 3=3.3v -10 +10 a 1.8v power supply isb v dd =1.8v fclk=0mhz -10 +10 a adc conversion characteristics at ta=25 c,v dd 3=3.3v5%,v dd =1.8v5%, dv ss = 0v, av ss = 0v parameter symbol conditions min typ max unit resolution res 10 bits i/o data timing (1) input data timing 1 pin name parameter symbol min max unit clock l-level time t lo 18.5 ns clock h-level time t hi 18.5 ns xin clock cycle t ck 37 ns input data setup time t su 3.5 ns vp24-34 pol, flm, oe, cpv, strb sp, dexr rin, gin, bin, blkin input data hold time t hd 3.5 ns * the recommended duty ratio of input clock is 50% t hi t lo t ck t su t hd xin in p ut data v dd 33/2 v dd 33/2
LC749880T no.a1186-14/17 (2) input data timing 2 pin name parameter symbol min max unit clock l-level time t lo 18.5 ns clock h-level time t hi 18.5 ns dclko3 clock cycle t ck 37 ns input data setup time t su 3.5 ns vsi hsi input data hold time t hd 3.5 ns (3) output data timing (1) pin name parameter symbol min max unit clock l-level time t lo 18.5 ns clock h-level time t hi 18.5 ns dclko clock cycle t ck 37 ns output data delay time t ac -3.5 +3.5 ns vp00-31 tim0, tim1, tim2 pol, flm, oe, cpv, strb sp, dexr, grst output data hold time t hd 30.0 ns (3) output data timing (2) pin name parameter symbol min max unit clock l-level time t lo 18.5 ns clock h-level time t hi 18.5 ns dclko2 clock cycle t ck 37 ns output data delay time t ac -3.5 +3.5 ns vso,hso output data hold time t hd 30.0 ns t hi t lo t ck t su t hd dclko3 sdclk in p ut data v dd 33/2 v dd 33/2 t hi t lo t ac t hd dclko output data v dd 33/2 v dd 33/2 t ck t hi t lo t ck t ac t hd dclko2 output data v dd 33/2 v dd 33/2
LC749880T no.a1186-15/17 i/o clock timing (1) input system clock timing pin name parameter symbol min max unit clock l-level time t lo 18.5 ns clock h-level time t hi 18.5 ns xin clock cycle t ck 37 ns dclko dclko delay time t out1 18.5 ns dcklo2 dclko2 delay time t out2 18.5 ns dcklo3 dclko3 delay time t out3 12.5 ns input xin output dclko t hi t ck t lo t out1 v dd 33/2 v dd 33/2 output dclko2 t out2 v dd 33/2 output dclko3 t out3 v dd 33/2
LC749880T no.a1186-16/17 sample application circuit 27.0mhz tuner (2in1) afe & adc cvbs1 cvbs2 s-y s-c y cb cr svo hsi vsi au1 au2 yc sep. & chroma dec. noisecanceller color tint color exitor shadow adjuster sharpness brightness contrast & white balance & black balance & correction timing controller r g b dclk timings lv1116 la4635a lcd panel (vga) x?tal lc87xxxx ( -con) xin xout sda scl LC749880T inverter cnt1 hso vso clko rin gin bin en others (for test ? ? ? ) x?tal multiplex pll dhs dvs dde lv78200 (sync. sep.) 32.768khz scaler
LC749880T no.a1186-17/17 ps this catalog provides information as of may, 2 008. specifications and info rmation herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibil ity for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these probabilistic failures or malfunction could give rise to accident s or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the us e of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

▲Up To Search▲

Price & Availability of LC749880T

	To Download LC749880T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .