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ethernet clock generator, 10 clock outputs ad9571 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2009 analog devices, inc. all rights reserved. f e at u res fully integrated vco /pll core 0.17 ps rms jitter from 1.875 mhz to 20 mhz at 156.25 mhz 0.41 ps rms jitter from 12 khz to 20 mhz at 1 25 mhz input crystal or clock frequency of 25 mhz preset divide ratios for 156.25 mhz, 33.33 mhz, 100 m hz, and 125 mhz choice of lvpecl or lvds ou t put format integrated loop filter 6 copies of reference clock output rates configured via strapping pins space saving 6 mm 6 mm 40 - lead lfcsp 0.48 w power dissipation (lvds operation) 0.69 w power dissipation (lvpecl opera tion) 3.3 v operation applications ethernet line cards, switches, and routers scsi, sata, and pci - express pci support included low jitter, low phase noise clock generation f unctional block diag ram xtal osc refclk refsel 6 25mhz cmos 1 33.33mhz 2 100mhz or 125mhz 1 156.25mhz force_low cmos lvpecl or lvds vco pfd/cp 3rd-order lpf freqsel dividers ad9571 07499-001 figure 1 . g eneral descriptio n the ad9571 provides a multi output clock generator f unction comprising a dedicated pll core that is optimized for ethernet line card applications . the i nteger - n pll design is based on the analog devices, inc., proven portfolio of high performance, low jit ter frequency sy n thesizers to maximize network performance. other applications with demanding phase noise and jitter requirements also benefit from this part. the pll section consists of a low noise phase frequency detector (pfd ), a precision charge pump (cp), a low phase noise voltage controlled oscillator (vco), and a pre programmed feedback divider and output divider . by connecting an external crystal or reference clock to the refclk pin, frequencies up to 156.25 mhz can be locked to the input reference. each output divider and feedback divide r ratio is pre pro - grammed for the required output rates. no external loop filter components are required, thus conserving valuable design time and board space. the ad957 1 is available in a 40 - lead 6 mm 6 mm lead frame c hip s cale p ackage and can be oper ated from a single 3.3 v supply . the operating temperature range is ?40c to +85c. 2 octal gbe phy 2 octal gbe phy 2 octal gbe phy 2 octal gbe phy 48 + 2 switch/mac optional cx-4 phy cpu island ad9571 xaui 6 25mhz 2 125mhz 1 156.25mhz 1 33.33mhz 07499-002 figure 2 . typical application
ad9571 rev. 0 | page 2 of 20 table of contents feature s .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 pll characteristics ...................................................................... 3 lvds clock output jitter ............................................................ 4 lvpecl clock output jitter ....................................................... 5 cmos clock output jitter .......................................................... 5 reference input ............................................................................. 5 clock outputs ............................................................................... 6 timing characteristics ................................................................ . 6 control pins .................................................................................. 7 power .............................................................................................. 7 crystal oscillator .......................................................................... 7 timing diagrams .......................................................................... 8 absolute maximum ratings ............................................................ 9 thermal resistance ...................................................................... 9 esd caution ...................................................................................9 pin configuration and function descriptions ............................ 10 typical p erformance characteristics ............................................ 12 terminology ..................................................................................... 13 theory of operation ....................................................................... 14 outputs .........................................................................................14 phase frequency detector (pfd) and charge pum p .............15 power supply ................................................................................ 15 cmos clock distribution ......................................................... 15 lvpecl clock distribution ......................................................16 lvds clock distribution ...........................................................16 reference input ............................................................................ 16 power and grounding considerations and power supply rejection ....................................................................................... 16 outline dimensions ........................................................................17 ordering guide ............................................................................ 17 revision history 8/0 9 rev ision 0: initial version
ad9571 rev. 0 | page 3 of 20 specifications pll characteristics typical (typ) is giv en for v s = 3.3 v , t a = 25c, unless otherwise no ted. table 1. parame ter min typ max unit test conditions/comments phase noise characteristics pll noise (156.25 mhz lvds output) @ 1 khz ?1 20 dbc/hz 33.33 mhz output disabled @ 10 k hz ?12 6 dbc/hz 33.33 mhz output disabled @ 10 0 khz ?12 6 dbc/hz 33.33 mh z output disabled @ 1 mhz ?14 5 dbc/hz 33.33 mhz output disabled @ 10 mhz ?15 1 dbc/hz 33.33 mhz output disabled @ 3 0 mhz ?15 2 dbc/hz 33.33 mhz output disabled pll noise (125 mhz lvds output ) @ 1 khz ?1 22 dbc/hz 33.33 mhz output disable d @ 10 k hz ?1 28 dbc/hz 33.33 mhz output disabled @ 10 0 khz ?12 8 dbc/hz 33.33 mhz output disabled @ 1 mhz ?14 7 dbc/hz 33.33 mhz output disabled @ 10 mhz ?15 2 dbc/hz 33.33 mhz output disabled @ 3 0 mhz ? 152 dbc/hz 33.33 mhz output disabled pll noise (100 mhz lvds output ) @ 1 khz ?12 2 dbc/hz 33.33 mhz output disabled @ 10 k hz ?12 9 dbc/hz 33.33 mhz output disabled @ 10 0 khz ?1 29 dbc/hz 33.33 mhz output disabled @ 1 mhz ?147 dbc/hz 33.33 mhz output disabled @ 10 mhz ?1 50 dbc/hz 33.33 mhz output disabled @ 3 0 mhz ?150 dbc/hz 33.33 mhz output disabled pll noise (156.25 mhz lvpecl output) @ 1 khz ?1 20 dbc/hz 33.33 mhz output disabled @ 10 k hz ?125 dbc/hz 33.33 mhz output disabled @ 10 0 khz ?12 5 dbc/h z 33.33 mhz output disabled @ 1 mhz ?14 5 dbc/hz 33.33 mhz output disabled @ 10 mhz ?15 1 dbc/hz 33.33 mhz output disabled @ 3 0 mhz ?15 2 dbc/hz 33.33 mhz output disabled
ad9571 rev. 0 | page 4 of 20 parame ter min typ max unit test conditions/comments pll noise (125 mhz lvpecl outp ut ) @ 1 khz ?12 1 dbc/hz 33.33 mhz ou tput disabled @ 10 k hz ?127 dbc/hz 33.33 mhz output disabled @ 10 0 khz ?12 8 dbc/hz 33.33 mhz output disabled @ 1 mhz ?148 dbc/hz 33.33 mhz output disabled @ 10 mhz ?152 dbc/hz 33.33 mhz output disabled @ 3 0 mhz ? 15 3 dbc/hz 33.33 mhz out put disabled p ll noise (100 mhz lvpecl output ) @ 1 khz ?1 15 dbc/hz 33.33 mhz output disabled @ 10 k hz ?12 1 dbc/hz 33.33 mhz output disabled @ 10 0 khz ?1 28 dbc/hz 33.33 mhz output disabled @ 1 mhz ?14 8 dbc/hz 33.33 mhz output disabled @ 10 mhz ?150 dbc/hz 33.33 mhz output disabled @ 3 0 mhz ?15 0 dbc/hz 33.33 mhz output disabled pha se noise (33.33 mhz cmos output ) @ 1 khz ?13 1 dbc/hz @ 10 k hz ?1 38 dbc/hz @ 10 0 khz ?1 39 dbc/hz @ 1 mhz ?1 51 dbc/hz @ 5 mhz ?1 52 dbc/hz phase noise (25 mhz cmos output ) @ 1 khz ?13 3 dbc/hz @ 10 k hz ?14 3 dbc/hz @ 10 0 khz ?14 7 dbc/hz @ 1 mhz ?14 8 dbc/hz @ 5 mhz ?14 8 dbc/hz spurious content 1 ? 70 dbc dominant amplitude with all outputs active pll figure s of merit ?21 7.5 dbc/hz 1 when the 33.33 mh z, 100 mhz, and 125 mhz clocks are enabled simultaneously, a worst - case ?50 dbc spurious content m ay be p resented on pin 21 and pin 22 only. lvds clock output jitter typical (typ) is giv en for v s = 3.3 v , t a = 25c, unless otherwise no ted. table 2. jitter integration bandwidth (typ) 100 mhz 125 mhz 1 , 33.33 m hz = off/on 156.25 mhz unit test conditions/comments 12 khz to 20 mhz 0.50 0.41/0.77 0.41 ps rms lvds output frequency combinations are 1 156.25 mhz, 1 100 mhz, 1 125 mhz, 1 33.33 mhz 1.875 mhz to 20 mhz 0.17 ps rms lvds output frequency combinations are 1 156.25 mhz, 1 100 mhz, 1 125 mhz, 1 33.33 mhz 200 khz to 10 mhz 0.30 0.24/0.66 ps rms lvds output frequency combinations are 1 156.25 mhz, 1 100 mhz, 1 125 mhz, 1 33.33 mhz 1 the typical 125 m hz rms jitter data collected from the differential pai r of pin 21 and p in 22, unless otherwise no ted.
ad9571 rev. 0 | page 5 of 20 lvpecl clock output jitter typical (typ) is giv en for v s = 3.3 v , t a = 25c, unless otherwise no ted. table 3. jitter integration bandwidth (typ) 100 mhz 125 mhz 1 , 33.33 m hz = off/on 156.25 mhz unit test conditions/comments 12 khz to 20 mhz 0.54 0.42 / 2.0 0.45 ps rms lvpecl output frequency combinat ions are 1 156.25 mhz, 1 100 mhz, 1 125 mhz , 1 33.33 mhz 1.875 mhz to 20 mhz 0.2 2 ps rms lvpecl output frequency combinations are 1 156.25 mhz, 1 100 mhz, 1 125 mhz , 1 33.33 mhz 200 khz to 10 mhz 0.31 0.25 /1 .9 ps rms lvpecl output freq uency combinations are 1 156.25 mhz, 1 100 mhz, 1 125 mhz , 1 33.33 mhz 1 the typical 125 m hz rms jitter data collected from the differential pai r of pin 21 and p in 22, unless otherwise no ted. cmos clock output jitter typical (typ) is giv en for v s = 3.3 v , t a = 25c, unless otherwise no ted. table 4. jitter integration bandwidth 25 mhz 33.3 3 mhz unit test conditions/comments 12 khz to 5 mhz 0.82 0.53 ps rms n/a 200 khz to 5 mhz 0.80 0.43 ps rms n/a reference input typical (typ) is giv en for v s = 3.3 v 10% , t a = 25c, unless otherwise no ted. minimum (min) and maximum (max) values are given over full v s and t a ( ?40c to +85c) variation. table 5. parameter min typ max unit test conditions/comments c lock input (refclk) input frequency 25 m hz input high voltage 2.0 v input low voltage 0.8 v inp ut c urrent ?1.0 +1.0 a input capacitance 2 pf
ad9571 rev. 0 | page 6 of 20 clock outputs typical (typ) is giv en for v s = 3.3 v 10% , t a = 25c, unless otherwise no ted. minimum (min) and maximum (max) values are given over full v s and t a ( ?40c to +85c) variation. table 6. parameter min typ max unit test conditions/comments lvpecl clock outputs output frequency 156.25 mhz output high voltage (v oh ) v s ? 1.24 v s ? 1.05 v s ? 0.83 v output low voltage (v ol ) v s ? 2.07 v s ? 1. 87 v s ? 1. 62 v output differential voltage (v od ) 700 825 950 mv duty cycle 45 55 % lvds clock outputs output frequency 156.25 mhz differential output voltage (v od ) 250 35 0 475 mv delta v od 25 mv output offset voltage (v os ) 1.125 1.25 1.375 v delta v os 25 mv short - circuit current (i sa , i sb ) 14 24 ma output shorted to gnd duty cycle 45 55 % cmos clock outputs output frequency 33.33 mhz output high voltage (v oh ) v s ? 0.1 v sourcing 1.0 ma current output low voltage (v ol ) 0.1 v sinking 1.0 ma current duty cycle 42 58 % t iming characteristic s typical (typ) is giv en for v s = 3.3 v 10% , t a = 25c, unless otherwise no ted. minimum (min) and maximum (max) values are given over full v s and t a ( ?40c to +85c) variation. table 7. parameter min typ max unit test conditions/comments lvpecl termination = 20 0 ? to 0 v; c load = 0 pf output rise time, t rp 480 625 810 ps 20% to 80%, measure d differentially output fall time, t fp 480 625 810 ps 80% to 20%, measured differentially lvds t ermination = 100 ? differential; c load = 0 pf output rise time, t rl 160 350 540 ps 20% to 80%, measured differentially output fall time, t fl 160 3 50 540 ps 80% to 20%, measured differentially cmos termination = 50 ? to 0 v; c load = 5 pf output rise time, t rc 0.25 0.50 2.5 ns 20% to 80% output fall time, t fc 0.25 0.70 2.5 ns 80% to 20%
ad9571 rev. 0 | page 7 of 20 control pins typical (typ) is giv en for v s = 3.3 v 10% , t a = 25c, unless otherwise no ted. minimum (min) and maximum (max) values are given over full v s and t a ( ?40c to +85c) variation. table 8. parameter min typ max unit test conditions/comments input characteristics refsel pin refsel has a 30 k ? pull - up resistor. logic 1 voltage 2.0 v logic 0 voltage 0.8 v logic 1 current 1.0 a logic 0 current 155 a freqsel pin freqsel has a 150 k ? pull - up resistor and a 100 k ? pull - down resistor. logic 1 voltage 2/3( vs ) + 0.2 v logic 0 voltage 1/3( vs )- 0.2 v logic 1 current 45 a logic 0 current 30 a force_low pin force_low has a 16 k ? pull - down resistor. logic 1 voltage 2.0 v logic 0 voltage 0.8 v logic 1 current 240 a logic 0 current 2.0 a power typical (typ) is giv en for v s = 3.3 v 10% , t a = 25c, unless otherwise no ted. minimum (min) and maximum (max) values are given over full v s and t a ( ?40c to +85c) variation. table 9. parameter min typ m ax unit test conditions/comments power supply 3.0 3.3 3.6 v lvds power dissipation 480 600 mw lvpecl power dissipation 690 860 mw c rystal oscillator typical (typ) is giv en for v s = 3.3 v 10% , t a = 25c, unless otherwise no ted. minimum (min) and maximum (max) values are given over full v s and t a ( ?40c to +85c) variation. table 10. parameter min typ max unit test conditions/comments crystal specification fundamental mode frequency 25 mhz esr 50 ? load capacitance 14 pf phase noise ? 135 dbc/hz @1 khz offset stability ? 30 +30 ppm
ad9571 rev. 0 | page 8 of 20 timing diagrams differential lvpecl 80% 20% t rp t fp 07499-003 figure 3 . lvpecl timing, differential differential lvds 80% 20% t rl t fl 07499-004 figure 4 . lvds timing, differential single-ended cmos 5pf load 80% 20% t rc t fc 07499-005 figure 5. cmos timing, single - ended, 5 pf loa d
ad9571 rev. 0 | page 9 of 20 absolute maximum rat ings table 11. parameter rating vs to gnd ?0.3 v to +3.6 v refclk to gnd ?0.3 v to vs + 0.3 v b y pass x to gnd ?0.3 v to vs + 0.3 v xo to gnd ?0.3 v to vs + 0.3 v force_low , freqsel , and refsel to gnd ?0.3 v to vs + 0.3 v 25m, 33m, 100 m /125m, and 156m to gnd ?0.3 v to vs + 0.3 v junction temperature 1 150c storage temperature range ?65 c to + 150c 1 see table 12 for ja . stresses above those listed under absolute maximum ra tings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. thermal impedance measurements were taken on a 4 - layer board in still air in accordance with eia/jesd51 - 7. table 12 . thermal resistance package type ja unit 40- lead lfcsp 27.5 c/w esd caution
ad9571 rev. 0 | page 10 of 20 pin configuration and function descripti ons notes 1. * = short to pin 36. 2. ** = short to pin 14. 3. note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. for the device to function properly, the paddle must be attached to ground (gnd). pin 1 indicator 1 gnd 2vs 3 25m 4 25m 5vs 6xo 7xo 8 refclk 9 refsel 10gnd 23 33m 24 vs 25 vs 26 vs 27 freqsel 28 vs 29 25m 30 25m 22 100m/ 125m 21 100m/125m 11 vs 12** 13** 15 vs 17156m 16 vs 18156m 19 100m/125m 20 100m/125m 14 bypass2 33 vs 34 gnd 35 vs 36 bypass1 37 force_low 38 * 39 vs 40 vs 32 25m 31 25m top view (not to scale) ad9571 lvpecl/ lvds 07499-006 figure 6. pin configuration table 13 . pin function descriptions 1 p in no. mnemonic description 2 vs power supply c onnection for the 25m cmos b uffer. 3, 4 , 29, 30, 31, 32 25m cmos 25 mhz o utput . 5 vs power supply c onnection for the crystal o scillator. 6, 7 xo external 25 mhz c rystal . 8 refclk 25 mhz reference clock input . tie low when not in use. 9 refsel logic i nput . u sed to select the reference source . 11 vs power supply c onnection for the gbe pll. 1, 10, 34 gnd ground p ins. the external paddle must be attached to gnd . 14, 36 bypass2 , bypass1 these pins are f or bypassing each ldo to ground with a 220 nf capacitor . 15 vs power supply c onnection for the gbe vco. 16 vs power supply c onnection for the 156m lvds out put b uf fer and output d ividers. 17 156m lvpecl / lvds o utput at 156.25 mhz . 18 156m complementary lvpecl/lvds o utput at 156.25 mhz . 19, 21 100m /125m lvpecl/lvds o utput at 100 mhz or 125 mhz . s elected by freqsel pin strapping . 20, 22 100m / complementary lvpecl / lvds o utput at 100 mhz or 125 mhz. 125m 23 33m cmos 33 .33 mhz o utput . 24 vs power supply c onnection for the 33m cmos output buffer and output d ividers. 25 vs power supply c onnection for the 100 m /125m lvds output buffer and output d ividers. 26 vs power supply c onnection for the gbe pll feedba ck d ivider. 27 freqsel logic input. used to configure output drivers . 28 vs power supply c onnection for the fc pll f eedback d ivider.
ad9571 rev. 0 | page 11 of 20 p in no. mnemonic description 33 vs power supply c onnection for the 106.25 mhz lvds output buffer and output d ividers. 35 vs power supply c onnection for the fc vco. 37 force_low forces the 33 .33 mhz output into a low state . 39 vs power supply c onnection for the fc pll. 40 vs power supply connection for m iscellaneous l ogic. 1 t he exposed paddle on this package is an electrical connection as well as a thermal enhancement. for the device to function p roperly, the pa ddle must be attached to ground ( gnd ).
ad9571 rev. 0 | page 12 of 20 typical performance characteristics both 100 mhz and 125 mhz outputs enab led; 33.3 3 mhz output disabled. ?100 ?160 ?150 ?140 ?130 ?120 ?110 1k 10k 100k 1m 100m 10m phase noise (dbc/hz) frequency (hz) 07499-007 figure 7 . 125 mhz phase noise ?100 ?160 ?150 ?140 ?130 ?120 ?110 1k 10k 100k 1m 100m 10m phase noise (dbc/hz) frequency (hz) 07499-008 figure 8 . 25 mhz phase noise ?100 ?160 ?150 ?140 ?130 ?120 ?110 1k 10k 100k 1m 100m 10m phase noise (dbc/hz) frequency (hz) 07499-009 figure 9 . 156.25 mhz phase nois e ?100 ?160 ?150 ?140 ?130 ?120 ?110 1k 10k 100k 1m 100m 10m phase noise (dbc/hz) frequency (hz) 07499-010 figure 10. 100 mhz phase noise
ad9571 rev. 0 | page 13 of 20 terminology phase jitter an ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 degrees to 360 degrees for each cycle. actual signals, however, display a certain amount of variation from ideal phase progression over time. this phenomenon is called phase jitter. although many causes can contribute to phase jitter, one major c ause is random noise , which is char acterized statistically as g aussian (normal) in distribution. this phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. this power spectrum is usually reported as a series of values whose units are dbc/hz at a given offset in frequency from the sine wave (carrier). the value is a ratio (expressed in db) of the power contained within a 1 hz bandwidth with respect to the power at the carrier frequency. for each measurement, the offset from the carrier frequency is also given. phase noise when the total power contained within some interval of off set frequencies (for example, 12 khz to 2 0 mhz) is integrated, it is called the integrated phase noise over that frequency offset interval , and it can be readily related to the time jitter due to the phase noise within that offset frequency interval. phase noise has a detriment al effect on error rate performance by increas ing eye closure at the transmitter output and reducing the jitter tolerance/sensitivity of the receiver. time jitter phase noise is a frequency domai n phenomenon. in the time domain, the same effect is exhibited as time jitter. when observing a sine wave, the time of successive zero crossings is seen to vary. in a square wave, the time jitter is seen as a displacement of the edges from their ideal (reg ular) times of occurrence. in both cases, the variations in timing from the ideal are the time jitter. because these variations are random in nature, the time jitter is specified in units of seconds root mean square (rms) or 1 sigma of the g aussian distrib ution. additive phase noise additive p hase n oise is the amount of phase noise that is attributable to the device or subsystem being measured. the phase noise of any external oscillators or clock sources has been subtracted. this makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contribute s its own phase noise to the total. in many cases, the phase noise of one element dominates the system phase noise. additive time jitter additive time jitter is the amount of time jitter that is attributable to the device or subsystem being measured. the time jitter of any external oscillators or clock sources has been subtracted. this makes it possible to predict the degree to which the device impact s the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contribute s its own time jitter to the total. in many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter.
ad9571 rev. 0 | page 14 of 20 theory of operation xtal osc refclk refsel vs gnd phase frequency detector charge pump divide by 25 divide by 4 divide by 4 divide by 5 divide by 4 divide by 5 divide by 3 25m cmos 25mhz 25m 25m cmos 25m 25m cmos 25m 33m 33.33mhz cmos 1 0 v ldo vco 0 1 1 0 125mhz/ 100mhz lvpecl/ lvds 100m/125m 100m/125m 125mhz/ 100mhz lvpecl/ lvds 100m/125m 100m/125m 156.25mhz lvpecl/ lvds 156m 156m freqsel ad9571 level decode force_low 07499-011 figure 11 . detailed block diagram figure 11 shows a block diagram of the ad957 1 . the chip consists of a pll core , which is configured to generate the specific clock frequencies required for ethernet applications, without any user programming. this pll is based on proven analog devices syn t hesizer technology, noted for its exceptional phase noise performance. the ad957 1 is highly integrated and includes loop filters, regulators for supply noise immunity, all the necessary dividers with multiple output buffers in a choice of formats , and a crystal oscillator. a user need only supply a 25 mhz reference clock or an external crystal to implement an entire line card clocking solution that does not requi re any processor intervention. six copies of the 25 mhz reference source are also available. o utputs table 14 provides a summary of the outputs available . table 14 . output formats frequency format copies 25 mhz cmos 6 156.25 mhz lvpecl/lvds 1 100 mhz or 125 mhz lvpecl/lvds 2 33 .33 mhz cmos 1 note that the pins labeled 100 m /125m can provide 100 mhz or 125 mhz by strapping the freqsel pin as shown in table 15 .
ad9571 rev. 0 | page 15 of 20 table 15. freqsel definition freqsel frequency available from p in 19 and pin 20 (mhz) frequency available from p in 21 and pin 22 (mhz) 0 12 5 125 1 100 100 nc 125 100 3.5ma 3.5ma out out 07499-012 figure 12 . lvds output simplified equivalent circuit the simplified equivalent circuit s of the lvds and lvpecl outputs are shown in figure 12 and figure 13 . 3.3v out out gnd 07499-013 figure 13 . lvpecl output simplified equivalent circuit the differential outputs are factory programmed to either lvpecl or lvds format , and either option can e sampled on request . cmos drivers tend to g ener at e more noise than differential outputs and , as a result, the proimity of the 33 .33 mhz output to p in 21 and pin 22 does affect the itter performance when feqsel 0 ( that is, when the differential output is generating 125 mhz) . for this reason, th e 33 .33 mhz pin can e forc ed to a low state y asserting the foce_low signal on p in 37 (see tale 16 ). an internal pull - down enale s the 33 .33 mhz output if the pin is not connected. table 16. force_low ( pin 37) definition force_low 33.33 mhz output (pin 23) 0 or nc 33.33 mhz 1 0 mhz phase frequency dete ctor (pfd) and charge pu mp the pfd takes inputs from the reference clock and feedback divider to produce an output proportional to the phase and freque ncy difference between them. figure 14 shows a simplified schematic . d1 q1 clr1 refclk high up d2 q2 clr2 high down cp charge pump 3.3v gnd feedback divider 07499-014 figure 14 . pfd si mplified schematic p ower supply the ad9571 requires a 3.3 v 10 power supply for v s . the specifications section give s the performance expected from the ad957 1 with the power supply voltage within this range. t he absolute maximum range of ( 0.3 v ) ( 3.6 v ) , with respect to gnd, must never be exceeded on the vs pin. good engine ering practice should be followed in the layout of power supply traces and the ground plane of the pcb. bypass t he power supply on the pcb with adequate c apacitance (10 f). bypass t he ad9571 with adequate capacitors (0.1 f) at all power pins as close as possible to th e part. the layout of the ad9571 evaluation board is a good example. the ex posed metal paddle on the ad9571 package is an electrical connection, as well as a thermal enhancement. for the device to function properly, the paddle must be proper ly attached to ground (gnd). the pcb acts as a heat sink for the ad 957 1 therefore, this gnd connection should provide a good thermal path to a larger dissipation area, such as a ground plane on the pcb. cmos clock distribut ion the ad9571 provides seven cm os clock outputs ( six 25 m hz and one 33 .33 m hz ) that are dedicated cmos levels. whenever single - ended cmos clocking is used, some of the following general guidelines should be followed. point - to - point nets should be designed such that a driver has one receiver only on the net, if possible. this allows for simple termination schemes and minimizes ringing due to possible mismatched impedances on the net. series termination at the source is generally required to provide transmission line matc h ing and/or to red uce current transients at the driver.
ad9571 rev. 0 | page 16 of 20 the value of the resistor is dependent on the board design and timing r e quirements (typically 10 ? to 100 ? is used). cmos outputs are limited in terms of the capacitive load or trace length that they can drive . t ypically , trace lengths less than 6 inches are re c ommended to preserve signal rise/fall times and signal integrity . 10? microstrip gnd 5pf 60.4 ? 1.0 inch cmos 07499-015 figure 15 . series termination of cmos output termination at the far end of the pcb trace is a second option. the cmos outputs of the ad957 1 do not supply enough curren t to provide a full voltage swing with a low impedance res istive, far - end termination, as shown in figure 16 . the far - end termin - ation network should match the pcb trace impedance and provide the desired switching point. the reduced signal swing may still meet r e ceiver inp ut requirements in some applications. this can be useful when driving long trace lengths on less critical nets. 50? 10? v pullup = 3.3v cmos 5pf 100? 100? 07499-016 figure 16 . cmos output with far- end termination lvpecl clock distrib ution the low voltage, posit ive emitter - coupled logic (lvpecl) ou t puts of the ad 9571 provide the lowest jitter clock signals available from the ad 9571 . the lvpecl outputs (because they are open emitter) require a dc termination to bias the output transistors. the simpl i fied equivalent circuit i n figure 13 shows the lvpecl output stage. in most applications, a standard lvpecl far - end termination is recommended, as shown in figure 17 . the resistor network is designed to match the transmiss i on line impedance (50 ?) and the desired switching threshold (1.3 v). 3.3v lvpecl 50? 50? single-ended (not coupled) 3.3v 3.3v lvpecl 127? 127? 83? 83? v t = v cc ? 1.3v 07499-017 figure 17. lvpec l far - end termination 3.3v lvpecl differential (coupled) 3.3v lvpecl 100? 0.1nf 0.1nf 200? 200? 07499-018 figure 18. lvpecl with parallel transmission line lvds clock distribut ion low voltage differe ntial signaling ( lvds) is a second differ - ential output option for the ad 957 1 . lvds uses a current mode output st age with a factory programmed current level . the normal value (default) for this current is 3.5 ma, which yields a 350 mv output swing across a 100 ? resistor. the lvds outputs meet or exceed all ansi/tia/eia - 644 specifications. a recommended termination circuit for the lvds outputs is shown in figure 19 . 50? 50? lvds lvds 100? 07499-019 figure 19 . lvds output termination se e the an - 586 application note on the analog devices website at www.analog.com for more information about lvds. r eference input by default, the crystal oscillator is enabled and used as the reference source, which requ ires the connection of an external 25 mhz crystal. the refsel pin is pulled high internally by about 30 k to support default operation. when refsel is tied low, the crystal oscillator is powered down , and the refclk pin must provide a good quality 25 mhz reference clock instead. this single - ended input can be driven by either a dc - coupled lvcmos level signal or an ac - coupled sine wave or square wave, provided that an external divider is used to bias the input at vs /2. table 17. refsel definition refsel reference s ource 0 refclk input 1 internal crystal oscillator power and grounding considerations and power supply rejecti on many applications seek high speed and performance under less than ideal operating conditions. in these application cir cuits, the implementation and construction of the pcb is as important as the circuit design. p roper rf tec h niques must be used for device selection, placement, and rou t ing, as well as for power su p ply bypassing and grounding to ensure optimum performance.
ad9571 rev. 0 | page 17 of 20 outline dimensions 072709-a 0.50 bsc bottom view top view pin 1 indicator exposed pad pin 1 indicator seating plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 6.10 6.00 sq 5.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.45 0.40 0.35 0.25 min * 4.80 4.70 sq 4.50 compliant to jedec standards mo-220-wjjd-5 with exception to exposed pad dimension. 40 1 11 20 21 30 31 10 figure 20. 40 - lead lead frame chip scale package [lfcsp_wq] 6 mm 6 mm body, very very thin quad (cp - 40 -7) dimensions shown in millimeters ordering guide model temperature range package description package option ad957 1 acpzlvd 1, 2 ?40c to +85c 40- lead lead frame chip scale package [ lfcsp_wq ] cp - 40 -7 ad9571acpzlvd - rl 1 , 2 ?40c to +85c 40- lead lead frame chip scale package [ lfcsp_wq ], 7 tape reel, 2,500 pieces cp - 40 -7 ad9571acpzlv d- r7 1 , 2 ?40c to +85c 40- lead lead frame chip scale package [ lfcsp_wq ], 7 tape reel, 750 pieces cp - 40 -7 ad9571acpzpec 1, 3 ?40c to +85c 40- lead lead frame chip scale package [ lfcsp_wq ] cp - 40 -7 ad9571ac pzpec - r7 1, 3 ?40c to +85c 40- lead lead frame chip scale package [ lfcsp_wq ], 7 tape reel, 750 pieces cp - 40 -7 ad9571acpzpec - rl 1, 3 ?40c to +85c 40- lead lead frame chip scale package [ lfcsp_wq ], 7 tape reel, 2,500 pieces cp - 40 -7 ad9571 - evalz - lvd 1 , 2 evaluation board ad9571 - evalz - pec 1, 3 evaluation board 1 z = rohs compliant part. 2 lvd indicates lvds compliant, differential clock outputs . 3 pec indicates lvpecl compliant, differential clock outputs .
ad9571 rev. 0 | page 18 of 20 notes
ad9571 rev. 0 | page 19 of 20 notes
ad9571 rev. 0 | page 20 of 20 notes ? 2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07499 -0- 8/09(0)

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