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scd7365 rev b features ? upscreened pmc-sierra rm7065c ? military and industrial grades available ? dual issue symmetric superscalar microprocessor with instruction prefetch optimized for system level price/performance o 450mhz operating frequency ? high-performance system interface o multiplexed address/data bus (sysad ) supports 2.5v, 3.3v i/o logic o processor clock multipliers 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9 o support for 64-bit or 32-bit external agents ? integrated primary and secondary caches o all are 4-way set associative with 32-byte line size o 16-kbytes instruction, 16-kbytes data, 256-kbytes on-chip secondary o per line cache locking in primaries and secondary o fast packet cache? increases system efficiency in networking applications ? high-performance floating-poin t unit ? 1600mflops maximum o single cycle repeat rate for comm on single-precision operations an d some double-precision operations o single cycle repeat rate for single-pre cision combined multiply-add operations o two cycle repeat rate for double-p recision multiply and double-precisi on combined multiply-add operations ? mips iv superset instruction set architecture o data prefetch instruction allows the processor to overlap cache miss latency and instruction execution o single-cycle floating-point multiply-add ? integrated memory management unit o fully associative joint tlb (s hared by i and d translations) o 64/48 dual entries map 128/96 pages o variable page size ? embedded application enhancements o specialized dsp integer multiply-accumulate inst ructions, (mad/madu) an d three-operand multiply instruction (mul) o i&d test/break-point (watch) registers for emulation & debug o performance counter for system and software tuning & debug o fourteen fully prioritized vectored inte rrupts ? 10 external, 2 internal, 2 software ? fully static cmos design w ith dynamic power down logic ? 216-epad lqfp 24x24mm are pin compatible wi th the rm7965 and rm5261a epad? products note: 216-enhanced pad package, epad mips64 and fast packet cache are trademarks of pmc-sierra mip7365 standard products january 11, 2007 64-bit superscaler microprocessor
2 scd7365 rev b 1/11/07 aeroflex plainview block diagram
3 scd7365 rev b 1/11/07 aeroflex plainview description the mip7365 microprocessor is a highly integrated symmetric superscalar mi croprocessor capable of issuing two instructions each processor cycle. it has two highperfo rmance 64-bit integer units as we ll as a high-throughput, fully pipelined 64-bit fl oating point unit. the mip7365 integrates 16 kbytes 4-way set associative instru ction and data caches along with an integrated 256 kbytes 4-way set associative secondary cache. the primary data and secondary caches are write-back and non-blocking. the memory management unit contains a 64/48-entry fully associative tlb and a 64-bit system interface supporting multiple outstanding reads with out- of-order return and hardware pr ioritized and vectored interrupts. the mip7365 is available in a 216-epad lqfp package. the 216-epad package is pin compatible with previous rm7965 and the rm5261a exposedpad products. the mip7365 ideally suits high-end embedded control applic ations such as internetworkin g, high-performance image manipulation, high-speed printing, and 3-d visualization. th e mip7365 is also applicable to the low end workstation market where its balanced integer and floating-point performance provides outstanding price/performance. for additional detail information regarding the operation of the pmc-sierra see the latest pmc-sierra datasheet for the rm7065c family microprocessors data sheet, issue no. 5: august 2006; document no. pmc-2021816, issue 5
4 scd7365 rev b 1/11/07 aeroflex plainview pin descriptions the following is a list of cont rol, data, clock, interrupt, and miscellaneous pins of mip7365. system interface pin name type description extrqst* input external request signals that the external agent is submitting an external request. release* output release interface signals that the processor is releasi ng the system interface to slave state rdrdy* input read ready signals that an external agen t can now accept a processor read. wrrdy* input write ready signals that an extern al agent can now accept a processor write request. validin* input valid input signals that an external agent is now driving a valid address or data on the bus and a valid command or data identifier on the syscmd bus. validout* output valid output signals that the processor is now driving a valid address or data on the sysad bus and a valid command or data identifier on the syscmd bus. prqst* output processor request when asserted this signal requests that cont rol of the system interface be returned to the processor. this is enabled by mode bit 26 pack* input processor acknowledge when asserted, in response to prqst*, this si gnal indicates to the processor that it has been granted control of the system interface. rspswap* input response swap rspswap* is used by the external agent to si gnal the processor when it is about to return a memory reference out of order; i.e., of two ou tstanding memory references, the data for the second reference is being returned ahead of the data for the first reference. in order that the processor will have time to switch the address to the tertiary cache, this signal must be asserted a minimum of two cycles prior to the data itself being presented. note that this signal works as a toggle; i.e., for each cycle that it is held assert ed the order of return is reversed. by default, anytime the processor issues a second read it is assumed that the reads will be returned in order; i.e., no action is required if the reads are indeed returned in order. this is enabled by mode bit 26. rdtype output read type during the address cycle of a read request, rd type indicates whether the read request is an instruction read or a data read. sysad[63:0] input/output system address/data bus a 64-bit address and data bus for communication between the processor and an external agent. sysadc[7:0] input/output system address/data check bus an 8-bit bus containing parity check bits for the sysad bus during data cycles. syscmd[8:0] input/output system command/data identifier bus a 9-bit bus for command and data identifier transmission between the processor and an external agent. syscmdp input/output system command/data identifier bus parity for the mip7365, unused on input and zero on output.
5 scd7365 rev b 1/11/07 aeroflex plainview clock/control interface pin name type description master clock input system clock master clock input used as the system interface reference clock. all output timings are relative to this input clock. pipeline operation frequency is derived by multiplying this clock up by the factor selected during boot initialization. power supply pin name type description vccint input power supply for core. vccio input power supply for i/o. vccp input vcc for pll quiet vccint for the internal ph ase locked loop. must be connect ed to vccint through a filter circuit. vccj input power supply used for jtag. vss input ground return. vssp input vss for pll quiet vss for the internal phase locked loop. must be connected to vss through a filter circuit. interrupt interface pin name type description int[9:0]* input interrupt ten general processor interrupts, bit-wise ored with bits 9:0 of the interrupt register. nmi* input non-maskable interrupt non-maskable interrupt, ored with bit 15 of the interrupt register (bit 6 in r5000 compatibility mode). jtag interface pin name type description jtdi input jtag data in jtck input jtag clock input jtdo output jtag data out jtms input jtag command jtrst* input jtag reset. notes: 1. the jtrst* input was added to the rm70xxc and rm79xx cp us to directly control the reset to the jtag state machine. jtag boundary scan test equipment must be able to drive jtrst* high to allow jtag boundary scan operation. 2. the jtrst* input must be connected to gnd ( vss ) through a 220 to 1 k pull-down resistor to force th e jtag state machine into the reset state to allow normal operation (jtag boundary scan mode disabled). 3. the jtag interface electrical characteristics are dependent on the vccj level chosen (2.5 v or 3.3 v).
6 scd7365 rev b 1/11/07 aeroflex plainview initialization interface pin name type description bigendian input big endian / little endian control allows the system to change the processor addressing vccok input vcc is ok when asserted, this signal indicate s to the mip7365 that the vccint power supply has been above the recommended value for more than 100 milliseconds and will remain stable. the assertion of vccok initiates the reading of the boot-time mode control serial stream. coldreset* input cold reset this signal must be asserted for a power on reset or a cold reset. coldreset must be de-asserted synchronously with sysclock. reset* input reset this signal must be asserted for any reset se quence. it may be asserted synchronously or asynchronously for a cold reset, or synchr onously to initiate a warm reset. reset must be de-asserted synchronously with sysclock. modeclock output boot mode clock serial boot-mode data clock output at the system clock frequency divided by two hundred and fifty six. modein input boot mode data in serial boot-mode data input.
7 scd7365 rev b 1/11/07 aeroflex plainview absolute maximum ratings 1 symbol rating range units v term terminal voltage with respect to vss -0.5 2 to 3.9 v tc operating temperature i = industrial r = extended t = military m = military, screened -40 to +85 -55 to +110 -55 to +125 -55 to +125 c c c c t stg storage temperature -55 to +125 c i in dc input current 20 ma i out dc output current 4 20 ma notes: 1. stresses above those listed under " absolutemaximums rating " may cause permanent damage to the device. this is a stress rating only and functional operation of the device at th ese or any other conditions above those i ndicated in the operational sections of th is specification is not implied. ex posure to absolute maximum rating conditions for extended periods may affe ct device reliability . 2. v in minimum = -2.0v for pulse width less than 15ns. v in maximum should not exceed +3.95 volts. 3. when v in < 0v or v in > vccio. 4. no more than one output should be shorted at one time. duration of the short should not exceed more than 30 second. recommended operating conditions grade cpu speed temp (case) vss vccint vccio vccp vccj industrial 450 mhz -40c to+85c 0 v 1.3 v 50 mv 3.3 v 150 mv or 2.5 v 200 mv 1.3 v 50 mv 3.3 v 150 mv or 2.5 v 200 mv extended 450 mhz -55c to +110c 0 v 1.3 v 50 mv 3.3 v 150 mv or 2.5 v 200 mv 1.3 v 50 mv 3.3 v 150 mv or 2.5 v 200 mv military 450 mhz -55c to +125c note 5 0 v 1.3 v 50 mv 3.3 v 150 mv or 2.5 v 200 mv 1.3 v 50 mv 3.3 v 150 mv or 2.5 v 200 mv notes 1. vccio should not exceed vccint by greater than 2.5 v during the power-up sequence. 2. applying a logic high state to any i/o pin before vccint becomes stable is not recommended. 3. as specified in ie ee 1149.1 (jtag), the jtms pin must be held high during reset to avoi d entering jtag test mode. refer to the rm7000 user manual. 4. vccp must be connect ed to vccint through a passive filter ci rcuit. see rm7000 user manua l fo recommended circuit. 5. contact factory for extended mil itary temperature range products (cqfp hermetic mcm packages will be screened at -55c to + 125c).
8 scd7365 rev b 1/11/07 aeroflex plainview dc electrical characteristics vccio = 3.15 - 3.45v parameter minimum maximum conditions v ol -0 . 2 v | i out | = 100a v oh vccio - 0.2v - v ol -0 . 4 v | i out | = 2ma v oh 2.4v - v il -0.3v 0.8v - v ih 2.0v vccio + 0.3v - i in - - 5a 5a v in = 0 v in = vccio vccio = 2.3v ? 2.7v parameter minimum maximum conditions v ol -0 . 2 v | i out | = 100a v oh 2.1v - v ol -0 . 4 v | i out | = 1ma v oh 2.0v - v ol -0 . 7 v | i out | = 2ma v oh 1.7v - v il -0.3v 0.7v - v ih 1.7v vccio + 0.3v - i in - - 15a 15a v in = 0 v in = vccio power consumption parameter conditions cpu speed 450mhz (ind) 450mhz (mil) max max v ccint power (mwatts) standby 1350 1350 active maximum with no fpu operation 2 3100 3250 maximum worst case instruction mix 3250 3400 notes: 1. worst case supply voltage (maximum vccint) with worst case temperature (maximum t case ). 2. dhrystone 2.1 instruction mix. 3. i/o supply power is appl ication dependant, but t ypically <20% of vccint.
9 scd7365 rev b 1/11/07 aeroflex plainview ac characteristics capacitive load deration symbol parameter minimum maximum units mode c ld load derate - 2 ns/25pf lvttl clock parameters parameter symbol test conditions bus speed units lvttl m i n m a x sysclock high t schigh transition < 2ns 3 - ns sysclock low t sclow transition < 2ns 3 - ns sysclock frequency 1 33.3 133 mhz sysclock period t scp 7.5 30 ns clock jitter for sysclock t jitterin -150ps sysclock rise time t scrise -2ns sysclock fall time t scfall -2ns modeclock period t modeckp - 256 ns jtag clock period t jtagckp 4-ns notes: 1. operation of the mip7365 is only guaranteed with the phase loop enabled. system interface parameters parameter 1 sym test conditions 5,6 i/o type units lvttl i/o m i n m a x data output 2,6,7 t do lvttl (vccio = 3.3v): mode[14:13] = 10 (fastest) 0.75 4.5 ns lvttl (vccio = 3.3v): mode[14:13] = 01 (slowest) 0.75 5.5 ns data setup 4 t ds t rise = see above table 2.5 - ns data hold 4 t dh t fall = see above table 1.0 - ns notes 1. in lvttl mode , timings are measured from 0.425 x vccio of clock to 0.425 x vccio of signal for 3.3v i/o, and from 0.48 x vccio of clock to 0.48 x vccio of signal for 2.5v i/o. input rise/fall time = 1v/1ns. 2. capacitive load for all lvttl maximum output timings is 50 pf. minimum output ti mings are for theoretical no load conditions - untested. 4. data output timing applie s to all signal pins whether tristate i/o or output only. 5. setup and hold parameters apply to all signal pins whethe r tristate i/o or input only. 6. only mode 14:13 = 01 is tested and guaranteed. 7. data shown is for 3.3 v i/ o. for 2.5 v i/o: derate t do min by 0.25 ns, and t do max by 0.5 ns. mode setting is mode [14:13] = 10 (fastest) or 01 (slowest).
10 scd7365 rev b 1/11/07 aeroflex plainview
11 scd7365 rev b 1/11/07 aeroflex plainview thermal information this product is designed to operate over a wide temperature range when used with a heat sink. notes 1. short-term is understood as the definition stated in telcordi a generic requirements gr-63-core. 2. jc , the junction-to-case thermal resistance, jb , the junction-to-board thermal resist ance are obtained from package vendor. 3. sa is the thermal resistance of the heat sink to ambient. cs is the thermal resistance of the heat sink attached material. 4. the actual sa required may vary accord ing to the air speed at the location of the device in the system with al l the components in place. maximum long-term operating junction temperature to ensure adequate long-term life tbd at 450 mhz maximum junction temperature for short-term excursions with guaranteed continued functional performance tbd at 450 mhz minimum ambient temperature tbd device compact model 2 jt (c/w) 4.19 jb (c/w) 5.43 ja (c/w) 11.65 operating power is dissipated in any package (watts) offered at worst case power supply power at 450mhz vccint = 1.3 v, vccio = 3.3 v 2.8w sa cs jt jb ambient heat sink case junction board device compact model
12 scd7365 rev b 1/11/07 aeroflex plainview mip7365 216-pin epad lq fp package outline molded depression in plastic - do not solder exposed pad option the solderable exposed pad must be connected to ground on the pcb 6.6(.260) 6.0(.236) 26.20(1.031) 25.80(1.015) 4 24.20(.953) 23.80(.937) 12.10(.476) 11.90(.485) 12.10(.476) 11.90(.485) -e- -a- 7 3 1 216 pin #1 id -d- 24.20(.953) 23.80(.937) 26.20(1.031) 25.80(1.015) 4 -d- 3 -b- 3 4x 4x 4x top view side view bottom view datum plane 0.25(.010) 0.15(.006) 0.05(.002) seating plane base plane -c- detail "b" detail "a" detail "c" gage plane 0~7 1.00(.039) ref. 0.75(.029) 0.45(.018) 0.20(.008)min -h- 2 0.08(.003) 0.20(.008) r0.08(.003) min. typ. min 0 r 0.08(.003) c 0.40(.0157) bsc. 12 typ. 0.20(.008) 0.10(.004) after plating 0.09/0.20 0.09/0.16 0.13/0.23 0.13/0.18 0.20(.008) detail "a" detail "b" 1.60(.063) max. 1.45(.057) 1.35(.053) - 0.05 s m 0.07(.003) sd c a-b s xx y c n u o r t see detail "c" (exposed pad corner detail) typ. (0.35) typ. (0.35) 0.20 bsc 0.30 max. 5 15 13.10(.516) 12.90(.508) 13.10(.516) 12.90(.508) -a,b, or d - 3 7 8 5 7 5 7 5 base metal with lead finish 9 0.05 8 13
13 scd7365 rev b 1/11/07 aeroflex plainview notes 1. all dimensions and tolerancing conform to an si y14.5-1982. inches ar e shown in parentheses. 2. datum plane -h- located at mold parting line and coincident with lead, where lead exits plastic body at bottom of parting line. 3. datums a-b and -d- to be determined at center line between leads where leads exit plastic body at datum plane -h-. 4. to be determined at seating plane -c-. 5. dimensions do not include mold protrusion. a llowable mold protrusion is 0.254 mm on dimensions. 6. 216 is the total number of terminals. 7. these dimensions to be determined at datum plane -h-. 8. package top dimensions are sm aller than bottom dimens ions and top of pack age will not overhang bottom of package. 9. dimension does not include dambar protrusion. a llowable dambar protrusion shall be 0.08 mm total in excess of the dimension at maximum material condition . dambar cannot be located on the lower radius or the foot. 10. controlling dimension: millimeter. 11. maximum allowable die thickness to be asse mbled in this package family is 0.38 mm. 12. this outline conforms to jedec publication 95, registration ms-026, variation bgb. 13. defined as the distance from the seating plane to the lowest point of the package body. 14. exposed pad shall be coplanar with bottom of package within 0.05. 15. corner chamfer of exposed die pad shall be within 0.30 mm. mip7365 216-pin epad lqfp package outline notes
14 scd7365 rev b 1/11/07 aeroflex plainview mip7365 216- epad lqfp numerical pinout vs function 1, 2 pin function pin function pin function pin function 1 vccio 39 sysad48 77 vccio 115 jtdo 2 do not connect 40 sysad16 78 syscmd5 116 vccio 3 do not connect 41 vccint 79 syscmd4 117 modeclock 4 do not connect 42 bigendian 80 syscmd3 118 vccint 5 do not connect 43 vccio 81 syscmd2 119 prqst* 6 vccint 44 vccok 82 vccint 120 pack* 7 sysad59 45 coldreset* 83 syscmd1 121 rspswap* 8 sysad27 46 reset* 84 syscmd0 122 vccio 9 sysad58 47 extrqst* 85 do not connect 123 vccint 10 vccint 48 nmi* 86 do not connect 124 sysad47 11 vccio 49 vccint 87 do not connect 125 sysad15 12 sysad26 50 int9* 88 vccint 126 vccint 13 vccint 51 int8* 89 do not connect 127 sysad46 14 sysad57 52 int7* 90 do not connect 128 sysad14 15 sysad25 53 int6* 91 vccint 129 sysad45 16 sysad56 54 vccio 92 do not connect 130 sysad13 17 sysad24 55 vccj 93 do not connect 131 sysad44 18 sysad55 56 vccio 94 do not connect 132 sysad12 19 sysad23 57 int5* 95 vccint 133 vccint 20 vccint 58 int4* 96 do not connect 134 sysad43 21 sysad54 59 int3* 97 master clock 135 sysad11 22 sysad22 60 int2* 98 vssp 136 vccio 23 sysad53 61 int1* 99 vccp 137 vccio 24 sysad21 62 int0* 100 release* 138 sysad42 25 vccio 63 vccint 101 validout* 139 sysad10 26 vccio 64 vccint 102 validin* 140 sysad41 27 vccio 65 do not connect 103 wrrdy* 141 sysad9 28 sysad52 66 do not connect 104 rdrdy* 142 vccint 29 sysad20 67 do not connect 105 do not connect 143 sysad40 30 vccint 68 vccio 106 modein 144 sysad8 31 sysad51 69 do not connect 107 rdtype 145 sysad39 32 sysad19 70 do not connect 108 do not connect 146 sysad7 33 sysad50 71 do not connect 109 vccj 147 sysad38 34 sysad18 72 vccint 110 jtrst* 148 sysad6 35 sysad49 73 syscmdp 111 vccio 149 vccint 36 sysad17 74 syscmd8 112 jtms 150 sysad37 37 vccio 75 syscmd7 113 jtck 151 sysad5 38 vccint 76 syscmd6 114 jtdi 152 sysad36
15 scd7365 rev b 1/11/07 aeroflex plainview mip7365 216- epad lqfp numerical pinout vs function 1, 2 con?t pin function pin function 153 sysad4 191 vccio 154 vccint 192 sysadc7 155 do not connect 193 sysadc3 156 do not connect 194 vccint 157 vccint 195 sysadc6 158 do not connect 196 vccio 159 do not connect 197 sysadc2 160 do not connect 198 sysad63 161 do not connect 199 sysad31 162 vccio 200 do not connect 163 do not connect 201 sysad62 164 vccio 202 sysad30 165 vccio 203 vccio 166 do not connect 204 vccio 167 do not connect 205 vccint 168 do not connect 206 sysad61 169 do not connect 207 sysad29 170 sysad35 208 vccint 171 sysad3 209 sysad60 172 vccint 210 sysad28 173 sysad34 211 do not connect 174 sysad2 212 do not connect 175 vccint 213 do not connect 176 vccio 214 do not connect 177 vccint 215 vccio 178 sysad33 216 vccio 179 sysad1 180 sysad32 181 sysad0 182 sysadc5 183 sysadc1 184 vccio 185 vccint 186 sysadc4 187 sysadc0 188 do not connect 189 vccint 190 vccio notes: 1. the exposed pad on the botto m of the epad lqfp package acts as the sole device ground and as the primary heat conduction path. as such, it must be soldered to the printed circuit board. 2. see pmc- 2030256 , 216-epad lqfp design guidelines application note for details.
16 plainview, new york toll free: 800-the-1553 fax: 516-694-6715 se and mid-atlantic tel: 321-951-4164 fax: 321-951-4254 international tel: 805-778-9229 fax: 805-778-1980 west coast tel: 949-362-2260 fax: 949-362-2266 northeast tel: 603-888-3975 fax: 603-888-4585 central tel: 719-594-8017 fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com scd7365 rev b 1/11/07 plainview, new york toll free: 800-the-1553 fax: 516-694-6715 se and mid-atlantic tel: 321-951-4164 fax: 321-951-4254 international tel: 805-778-9229 fax: 805-778-1980 west coast tel: 949-362-2260 fax: 949-362-2266 northeast tel: 603-888-3975 fax: 603-888-4585 central tel: 719-594-8017 fax: 719-594-8468 aeroflex microelectronic solutions reserves the right to change at any time without notice the specifications, design, function, or form of its products described herein. all parameters must be validated for each customer's application by engineering. no liability is assumed as a result of use of this product. no patent licenses are implied. all trademarks are acknowledged. parent company aeroflex, inc. 2003. our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused sample ordering information part number screening pipeline freq (mhz) note 2 package mip7365-450pi industrial temperature range -40c to +85c testing 450 216-epad lqfp mip7365-450pr extended temperature range -55c to +110c testing note 1 notes 1. contact factory for extended military temp erature range products (cqfp hermetic mcm pa ckage will be screened at -55c to + 1 25c). 2. contact factory for higher speed product options. 3. contact factory for availability. 4. the eepad "m" pkg eol is nov 2006. the epad lqfp "p" package is the replacement. part number breakdown base processor type 450 = 450mhz package type & size screening maximum pipeline frequency mip 7365 ? 450 p r mips series p = 26mm sq, 216-epad lqfp note 4 b1 = 26mm sq, 256-tgba note 3 f17 = 1.20'' sq, 208-lead cqfp* f24 = 1.20'' sq, 208-lead inverted cqfp* * optional - contact factory i = industrial temp, -40c to +85c r = extended temp, -55c to +110c note 1 t = military temp, -55c to +125c m = military temp, -55c to +125c, screened * * screened to the individual test methods of mil-std-883

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