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data sheet mindspeed technologies ? 28250-dsh-002-c june 2005 cx28250 atm physical interface (phy) devices the cx28250 is an atm-sonet physical layer (phy) device with an integrated, pll clock and data recovery (cdr) circuit. this device has optimized sonet framer functions for mapping atm cells to sonet payloads for edge switch applications, and optional enhanced feature sets for at m-wan access applications. it provides atm forum-compliant service termination, and ma ps the 53-byte cells from an atm switch fabric or an adaptation layer processor (s ar) into the sonet payload. the cx28250 device is tailored to meet a wide variety of atm oc-3 applications. these include wan terminals, atm lan and wan switches, at m oc-3 nics, and ethernet-atm uplink cards. the cx28250 uses an atm forum utopia l evel 2-compliant host interface designed for a multi-phy environment. the atm framer provides g.804 cell processing, with hec generation, checking, and alignment oper ations. it provides a 155 mbps sonet termination with all of the counters needed for capturi ng both sonet and atm error events as specified by the atm forum. a proprietary protecti on scheme allows for near-instantaneous switching between active and stand-by phys. the cx28250 uses a pseudo-emitter couple d logic (pecl) line interface compliant with the atm forum?s wire definition. thus, designers can connect directly to either fiber optic or cat 5 physical media dependa nt (pmd) devices. for diagnostics, three loopback modes are provided: source loopback, line loopback before the atm processor, and line loopback at the utopia block. in addition, the cx28250 can generate bip-8 errors and insert invalid hecs. the cx28250 supports the following: compliance with the jitter requir ements of bellcore?s gr-253-core. automatic protecti on switching (aps) using the k1/k2 over head octets and a bit error rate (ber) integrator. compatible with mindspeed cx28297 software driver. access to the s1 octet for system timing. data transmission/reception over the data link message channels, d1-d3 and d4-d12. two new input pins ha ve been added: inspth ais and inslnais. when asserted high, these pins cause the cx28250 to generate an ais in the appropriate overhead. two new output pins have also been added: lpout and pfout. the se indicate that an ais alarm has been received. functional block diagram atm wire interface cx28250 utopia level 2 utopia level 2 interface microprocessor interface sonet framer and overhead processor sts-3c/stm-1 (gr-253-core) atm formatter (g.804 cell processing) pmd interface 8/16 bits 8/16 bits 8 bits clock recovery tx 4-cell fifo rx 4-cell fifo microprocessor bus line interface host interface 500035_001 distinguishing features tested aps software driver available from mindspeed synthesizes a 155.52 mhz clock from an 19.44 mhz input utopia level 2 interface meets itu, ansi, and atm forum standards atm forum wire in terface for pmds using pecl d1-d3, d4-d12 external data link supports aps (k1/k2 bytes) line fail and path fail outputs sram-style microprocessor interface for all control and configuration registers glueless interface to the cx2823x segmentation a nd reassembly devices jtag (ieee 1149.1a-1993) compliant 8 khz and 19.44 mhz selectable sync outputs sonet overhead processing automatic collec tion of one-second statistics low power consumption-500 mw 3.3 v, ( ? 40 c to 85 c) package: 156-pin bga applications switches, hubs, routers lan nic cards dslam uplinks line interface atm forum wire interface specification compliant pecl i/o, compatible with pmd optical and utp interface devices clock recovery from nrz input data recovery of receive-octet alignment and octet clock from f6/28 framing pattern select transmit clock from input or recovered receive clock
28250-dsh-002-c mindspeed technologies ? ? 2002, 2003 mindspeed technologies inc., a dela ware corporation (?mindspeed ??) all rights reserved. information in this document is provided in connection with products of mindspeed tec hnologies (?mindspeed?). these materials a re provided by mindspeed as a service to its customers and ma y be used for informational purposes only. mindspeed assumes no responsibility for errors or omissions in these materials. mindspeed may make changes to specifications and product description s at any time, without notice. mindspeed makes no commitment to update the information and s hall have no responsibility whatsoever f or conflicts or incompatibilities aris ing from future changes to its spec ifications and product descriptions. no license, express or implied, by est oppel or otherwise, to any intellectual proper ty rights is granted by this document. in t he event of a conflict between the terms contained herein and those of any applicable agreement (?agreement ?) governing the sale of mindspeed?s products (incl uding without limitation mindspeed?s terms and conditions of sale) the terms of such agreement shall control. these materials are provided ?as is? without warranty of any kind, either express or implied, relating to sale and/or use of mindspeed products including liability or warranties relating to fitness for a particular purpose, consequential or incidental damages, merchantability, or infringement of any patent, copyright or other intellectual property right. mindspeed further does not warrant the accuracy or completeness of the information, text , graphics or other items contained within these materials. mindspeed shall not be liable for any damages which may result from the use of these materials. mindspeed products are not intended for use in medical, lifesavi ng or life sustaining applications . mindspeed customers using o r selling mindspeed products for use in such applications do so at their own risk and agree to fully indemnify mindspeed for any damages resulting from such improper use or sale. the following are trademarks of mindspeed technologies?, the minds peed? logo, and ?build it first? ?. product names or services listed in this publication are for identific ation purposes only, and may be trademarks of third parties. third-party brands and names are the property of their respective owners. mindspeed product definitions a ? chip ? is an integrated circuit, a piece of sili con or other semiconduc tor on which is etched or imprinted a network of electronic components such as transistors, diodes, resistors, etc. and thei r interconnections, which is full y assembled with packaging pro viding pins for connection to other circuits or systems. a ? die ? is an unassembled integrated circuit manufactured from a semi conductor material without pack aging or pins for connections to other circuits or systems. dies may be shipped on a wafer separated from each other by scribe lines, or they may be cut, separated and placed into appropriate packaging for shipping. ? board-level products ? are larger electrical circuits that are set out on a board containing one or more chips and circuitry to perform a specialized function. ? software products ? shall mean all software, in executable code, that is embedded, bundled or included with chips or die. a ? prototype ? product is a chip or die that has just begun the qualification process. it is marked with a capital ?p? at the end of its unique part number. ? pre-production ? products are chips or die that have not completed the qualification process but have results from some of the qualification tests. such products are marked with a capital ?r? at the end of their unique part number. a ? production ? product is a chip or die that is fully qualified and has no letter marked at the end of its unique part number. a ? sample ? product is any product that a buyer may sample, in any stage of qualification, in small numbers. all such sample products shall be noted as such on an acknowledgment, invoice, shipping document or other writing issued by seller.
28250-dsh-002-c mindspeed technologies ? ordering information revision history model number manufacturing part number product revision package operating temperature cx28250 -26 CX28250-26 b 156-pin, 15 mm bga -40 c to 85 c revision level date description c ? june 2005 added note to tie jtag trst* low when not using jtag. b ? november 2003 modified table 5-7. changed references to cn part numbers. a ? december 2002 revise document number: 28250-dsh-002-a.pdf) revised ordering information revised 0x03?version (part number/version status register)
28250-dsh-002-c mindspeed technologies ? sonet framer functions recovers frame location us ing f6/28 framing pattern processes pointer to locate payload envelope provides out-of-fra me (oof), loss-of-p ointer (lop), and alarm indication status (ais) status provides frame and payload pos ition information to other blocks generates clocks and frame counters maps cell data into payload envelope generates all section, line, and path overhead and alarms performs cell and frame scrambling before transmission detects and integrates alarms for reporting in status registers detects bip and remote error indication (rei ) errors for error counters recovers d1-d3 and d4-d12 data link cell alignment framing section recovers cell alignment from hec performs hec error correction strobes and cell sync for utopia interface generates cell status bits, cell counts, and error counts reads cell data from the utopia fifo inserts headers and generates hec inserts idle cells when no traffic is ready microprocessor interface sram-like interface mode with high-performance or low-power access selection glueless cx2823x sar interface mode 8-bit data bus open-drain interrupt output support for automatic pr otection switching (aps) aps driver source code available from mindspeed. register control allows for support of aps software support: ? cx28297 device driver ? cx28299 aps driver k1/k2 transmit control register allows transmission of any value separate control bits for ais, line rei k1/k2 receive status register allows observation of incoming octet values maskable interrupt on any change in received value software interrupt routine can easily implement aps protocol signal fail/signal detect ber threshold monitoring line fail and path fail hardware outputs line ais and path ais can be generated by ha rdware input pins counters/status and interrupt registers summary interrupt indications configuration of interrupt enables one-second status latching one-second counter latching eight general purpose outputs, configurable as status indicator pins the following diagram is a network interface card (nic) application of the cx28250 500035_002 cx28250 cx28234/cx28236 sram fiber or cat 5 pci bus pmd interface utopia bus interface local bus interface pci interface utopia interface microprocessor interface utopia bus local bus note(s): 1. the cx28234 sar has an 8 bit utopia level 1 interface. 2. the cx28236 sar has a 8/16 bit utopia level 1/2 interface and supports multi-phy operation.
28250-dsh-002-c mindspeed technologies ? line interface (continued) pmd (line) and framer (s ource) loopbacks for diagnostic testing loss of signal (los) detection 19.44 mhz refe rence clock utopia level 2 interface phy cell to utopia interface 50 mhz maximum data rate 8/16-bit data path interface multi-phy support mode-compatible with utopia level 1 configurable cell buffer depth sonet sts-3c/stm-1 framer section overhead octets supported line overhead octets supported path overhead octets supported transmit receive a1/a2 f6/28 hex or disable 00 monitor out of frame state machine j0 01 hex or 64-byte trace buffer monitor rx trace buffer, interrupt on change z0 1 , z0 2 02, 03 hex/user defined not checked b1 calculated, error insertion checked, errors counted d1, d2, d3 00 hex or external data link external data link transmit receive h1/h2 620a/93ff hex pointer full gr.253 pointer processor h3 set to 00 used in pointer processor b2 calculated, error insertion checked, errors counted k1/k2 insertable via register checked, interrupt on change d4-d12 00 hex or external data link external data link s1 insertable via register checked, interrupt on change m1 line rei inserted checked, errors counted transmit receive j1 00 hex or 64-byte trace buffer monitor rx trace buffer, interrupt on change b3 calculated, error insertion checked, errors counted c2 13 hex for atm mapping checked for 01 or 13 hex g1 path rei , rdi inserted checked, errors counted, status z2 monitored
28250-dsh-002-c mindspeed technologies ?
28250-dsh-002-c mindspeed technologies ? i table of contents table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -i list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-vii list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-ix 1.0 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 cx28250 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 applications overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.4 cx28250 pinout and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.5 block diagram and descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 2.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 line interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -3 2.1.1 pecl interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.1.1 pecl layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.1.2 signal detect interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.1.3 pll filter network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.2 clock circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -8 2.2.1 loss of lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.3 sonet/sdh framer and overhead processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.3.1 loss of signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.3.2 section overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.3.2.1 a1, a2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.3.2.2 loss of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.3.2.3 b1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.3.2.4 d1-d3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.3.2.5 j0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.3.2.6 z0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.3.3 line overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.3.3.1 h1, h2, and h3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.3.3.2 loss of pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.3.3.3 b2-1, b2-2, and b2-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
table of contents cx28250 atm physical interface (phy) devices ii mindspeed technologies ? 28250-dsh-002-c 2.3.3.4 aps threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.3.3.5 k1 and k2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.3.6 line rdi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.3.7 line ais . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.3.8 d4-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.3.9 s1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 2.3.3.10 m1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 2.3.4 path overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 2.3.4.1 j1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2.3.4.2 b3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 2.3.4.3 c2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 2.3.4.4 g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.3.4.5 inspthais input pin (insert path ais) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 2.3.4.6 pfout output pin (path fail) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 2.3.5 sonet frame scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 2.4 atm cell processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 2.4.1 atm cell transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 2.4.1.1 hec generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30 2.4.2 atm cell receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30 2.4.2.1 cell delineation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30 2.4.2.2 processing non-standard traffic using the cx28250 . . . . . . . . . . . . . . . . . . 2-32 2.4.2.3 cell screening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33 2.4.3 cell payload scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34 2.5 utopia interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35 2.5.1 utopia transmit and receive fifos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35 2.5.2 utopia 8-bit and 16-bit bus widths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36 2.5.2.1 user defined udf2 value (receive only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37 2.5.3 utopia parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37 2.5.4 utopia multi-phy operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38 2.5.5 handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39 2.6 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40 2.6.1 microprocessor clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40 2.6.2 status and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41 2.6.3 counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41 2.6.4 one-second latching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42 2.6.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43 2.6.5.1 interrupt routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43 2.6.5.2 interrupt suppression during error conditions . . . . . . . . . . . . . . . . . . . . . . . 2-46 2.6.5.3 interrupt servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47 2.7 loopback modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48 2.7.1 line loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48 2.7.2 utopia loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49 2.7.3 source loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50
cx28250 table of contents atm physical interface (phy) devices 28250-dsh-002-c mindspeed technologies ? iii 3.0 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 system application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2 board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.1 analog power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 the cx28250/cx28236 network interface card reference design . . . . . . . . . . . . . . . . . . . . . . . 3-7 4.0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.1 0x42?apsint (aps interrupt indication status register) . . . . . . . . . . . . . . . . . . . . . . . 4-12 (1) 0x09?apsthresh (aps thr eshold control register) . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 (1) 0x55?b1cnth (section bip error counter [high byte]) . . . . . . . . . . . . . . . . . . . . . . . . 4-13 (1) 0x54?b1cntl (section bip error counter [low byte]) . . . . . . . . . . . . . . . . . . . . . . . . 4-14 (1) 0x52?b2cnth (line bip error counter [high byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 (1) 0x50?b2cntl (line bip error counter [low byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 (1) 0x51?b2cntm (line bip error counter [mid byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 (1) 0x57?b3cnth (path bip error counter [high byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 (1) 0x56?b3cntl (path bip error counter [low byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 (1) 0x3b?b3thresh (b3 thr eshold control register) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 (1) 0x70?0x71?cdr test registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 (1) 0x04?cgen (cell generation control register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 (1) 0x01?clkrec (clock r ecovery control register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 note: 0x4d?corrcnt (corrected hec error counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 note: 0x08?cval (cell validation control register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 note: 0x3a?enaps (aps interr upt mask control register) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 note: 0x39?encellr (receive cell in terrupt mask control register) . . . . . . . . . . . . . . . . . . 4-21 note: 0x38?encellt (transmit cell interrupt mask control register) . . . . . . . . . . . . . . . . . . 4-22 note: 0x6e?enlfout (enable line fail output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 note: 0x36?enlin (receive line interrupt mask control register) . . . . . . . . . . . . . . . . . . . . 4-23 note: 0x6f?enpfout (enable path fail output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 note: 0x37?enpth (receive path in terrupt mask control register) . . . . . . . . . . . . . . . . . . . 4-24 note: 0x35?ensec (receive section interrupt m ask control register) . . . . . . . . . . . . . . . . . 4-24 note: 0x34?ensumint (s ummary interrupt m ask control register) . . . . . . . . . . . . . . . . . . . 4-25 note: 0x06?errins (error insertion control register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25 note: 0x07?errpat (error pattern control register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 note: 0x00?gen (general control register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27 note: 0x30?idlmsk1 (receive idle cell mask control register 1) . . . . . . . . . . . . . . . . . . . . . 4-28 note: 0x31?idlmsk2 (receive idle cell mask control register 2) . . . . . . . . . . . . . . . . . . . . . 4-28 note: 0x32?idlmsk3 (receive idle cell mask control register 3) . . . . . . . . . . . . . . . . . . . . . 4-29 note: 0x33?idlmsk4 (receive idle cell mask control register 4) . . . . . . . . . . . . . . . . . . . . . 4-29 note: 0x05?idlpay (transmit idle cell payload control register) . . . . . . . . . . . . . . . . . . . . . 4-30 note: 0x72?inlk (in lock coefficient register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 note: 0x5a?lfcnth (line rei error counter [high byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 note: 0x58?lfcntl (line rei error counter [low byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 note: 0x59?lfcntm (line rei error counter [mid byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 note: 0x3e?linint (receive line inte rrupt indication status register) . . . . . . . . . . . . . . . . . 4-32
table of contents cx28250 atm physical interface (phy) devices iv mindspeed technologies ? 28250-dsh-002-c (2) 0x4c?locdcnt (locd event counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32 (2) 0x5f?noncnth (non-matching cell counter [high byte]) . . . . . . . . . . . . . . . . . . . . . . 4-33 (2) 0x5e?noncntl (non-matching cell counter [low byte]) . . . . . . . . . . . . . . . . . . . . . . 4-33 (2) 0x4f?oofcnt (oof event counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34 (2) 0x73?outlk (out of lo ck coefficient register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34 (2) 0x02?outstat (output pin control register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34 (2) 0x5d?pfcnth (path rei error counter [high byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35 (2) 0x5c?pfcntl (path rei error counter [low byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35 (2) 0x3f?pthint (receive path interr upt indication status register) . . . . . . . . . . . . . . . . 4-36 (2) 0x4a?rxaps (receive ap s status register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36 (2) 0x18?rxc2 (receive c2 o verhead status register) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37 (2) 0x49?rxcell (receive ce ll status register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37 (2) 0x41?rxcellint (recei ve cell interrupt indicat ion status register) . . . . . . . . . . . . . . 4-38 (2) 0x66?rxcnth (received cell counter [high byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38 (2) 0x64?rxcntl (received cell counter [low byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 (2) 0x65?rxcntm (received cell counter [mid byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 (2) 0x19?rxg1 (receive g1 overhead status register) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40 (2) 0x24?rxhdr1 (receive cell header control register 1) . . . . . . . . . . . . . . . . . . . . . . . 4-40 (2) 0x25?rxhdr2 (receive cell header control register 2) . . . . . . . . . . . . . . . . . . . . . . . 4-41 (2) 0x26?rxhdr3 (receive cell header control register 3) . . . . . . . . . . . . . . . . . . . . . . . 4-41 (2) 0x27?rxhdr4 (receive cell header control register 4) . . . . . . . . . . . . . . . . . . . . . . . 4-42 (2) 0x2c?rxidl1 (recei ve idle cell header control register 1) . . . . . . . . . . . . . . . . . . . . . 4-42 (2) 0x2d?rxidl2 (receive idle ce ll header control register 2) . . . . . . . . . . . . . . . . . . . . 4-43 (2) 0x2e?rxidl3 (receive idle cell header control register 3) . . . . . . . . . . . . . . . . . . . . . 4-43 (2) 0x2f?rxidl4 (receive idle ce ll header control register 4) . . . . . . . . . . . . . . . . . . . . . 4-44 (2) 0x14?rxk1 (receive k1 o verhead status register) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44 (2) 0x15?rxk2 (receive k2 o verhead status register) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45 (2) 0x46?rxlin (receive line o verhead status register) . . . . . . . . . . . . . . . . . . . . . . . . . 4-45 (2) 0x28?rxmsk1 (receive cell mask control register 1) . . . . . . . . . . . . . . . . . . . . . . . . 4-46 (2) 0x29?rxmsk2 (receive cell mask control register 2) . . . . . . . . . . . . . . . . . . . . . . . . 4-46 (2) 0x2a?rxmsk3 (receive cell mask control register 3) . . . . . . . . . . . . . . . . . . . . . . . . 4-47 (2) 0x2b?rxmsk4 (receive cell mask control register 4) . . . . . . . . . . . . . . . . . . . . . . . . 4-47 (2) 0x47?rxpth (receive path overhead status register) . . . . . . . . . . . . . . . . . . . . . . . . 4-48 (2) 0x6b?rxpthbuf (receive path trace circular buffer, j1) . . . . . . . . . . . . . . . . . . . . . . 4-48 (2) 0x16?rxs1 (receive s1 o verhead status register) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-49 (2) 0x45?rxsec (receive section overhead status register) . . . . . . . . . . . . . . . . . . . . . . 4-49 (2) 0x6a?rxsecbuf (receive sect ion trace circular buffer) . . . . . . . . . . . . . . . . . . . . . . 4-50 (2) 0x1a?rxz01 (receive sectio n z01 overhead register) . . . . . . . . . . . . . . . . . . . . . . . . 4-50 (2) 0x1b?rxz02 (receive sectio n z02 overhead register) . . . . . . . . . . . . . . . . . . . . . . . . 4-51 (2) 0x3d?secint (r eceive section interrupt i ndication status register) . . . . . . . . . . . . . . 4-51 (2) 0x3c?sumint (summary interrupt indication status register) . . . . . . . . . . . . . . . . . . 4-52 (2) 0x13?txc2 (transmit c2 overhead control register) . . . . . . . . . . . . . . . . . . . . . . . . . 4-53 (2) 0x48?txcell (transmit cell status register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53 (1) 0x40?txcellint (transmit cell interrupt indication status register) . . . . . . . . . . . . . 4-54 (1) 0x62?txcnth (transmitted cell counter [high byte]) . . . . . . . . . . . . . . . . . . . . . . . . . 4-54 (1) 0x60?txcntl (transmitted cell counter [low byte]) . . . . . . . . . . . . . . . . . . . . . . . . . 4-55
cx28250 table of contents atm physical interface (phy) devices 28250-dsh-002-c mindspeed technologies ? v (1) 0x61?txcntm (transmitted cell counter [mid byte]) . . . . . . . . . . . . . . . . . . . . . . . . . 4-55 (1) 0x1c?txhdr1 (transmit cell header control register 1) . . . . . . . . . . . . . . . . . . . . . . 4-56 (1) 0x1d?txhdr2 (transmit cell header control register 2) . . . . . . . . . . . . . . . . . . . . . . 4-56 (1) 0x1e?txhdr3 (transmit cell header control register 3) . . . . . . . . . . . . . . . . . . . . . . 4-57 (1) 0x1f?txhdr4 (transmit cell header control register 4) . . . . . . . . . . . . . . . . . . . . . . . 4-57 (1) 0x20?txidl1 (transmit idle cell header control register 1) . . . . . . . . . . . . . . . . . . . . 4-58 (1) 0x21?txidl2 (transmit idle cell header control register 2) . . . . . . . . . . . . . . . . . . . . 4-58 (1) 0x22?txidl3 (transmit idle cell header control register 3) . . . . . . . . . . . . . . . . . . . . 4-59 (1) 0x23?txidl4 (transmit idle cell header control register 4) . . . . . . . . . . . . . . . . . . . . 4-59 (1) 0x10?txk1 (transmit k1 overhead control register) . . . . . . . . . . . . . . . . . . . . . . . . . 4-60 (1) 0x11?txk2 (transmit k2 overhead control register) . . . . . . . . . . . . . . . . . . . . . . . . . 4-60 (1) 0x0d?txlin (transmit line overhead control register) . . . . . . . . . . . . . . . . . . . . . . . 4-61 (1) 0x0e?txpth (transmit path overhead control register) . . . . . . . . . . . . . . . . . . . . . . . 4-62 (1) 0x69?txpthbuf (transmit path trace circular buffer) . . . . . . . . . . . . . . . . . . . . . . . . 4-62 (1) 0x12?txs1 (transmit s1 overhead control register) . . . . . . . . . . . . . . . . . . . . . . . . . 4-63 (1) 0x0c?txsec (transmit sectio n overhead control register) . . . . . . . . . . . . . . . . . . . . . 4-63 (1) 0x68?txsecbuf (transmit sect ion trace circular buffer, j0) . . . . . . . . . . . . . . . . . . . 4-64 (1) 0x6c?txz01 (transmit section z01 overhead control register) . . . . . . . . . . . . . . . . . . 4-64 (1) 0x6d?txz02 (transmit section z02 overhead control register) . . . . . . . . . . . . . . . . . . 4-65 (1) 0x74?udf2 (user defined field 2; overwrite control register) . . . . . . . . . . . . . . . . . . . 4-65 (1) 0x4e?unccnt (uncorrected hec error counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-66 (1) 0x0a?utop1 (utopia control register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-66 (1) 0x0b?utop2 (utopia control register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67 (1) 0x03?version (part number /version status register) . . . . . . . . . . . . . . . . . . . . . . . . 4-67 5.0 electrical and mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.1 microprocessor interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.1.2 transmit utopia interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.1.3 receive utopia interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.1.4 jtag interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 5.1.5 one-second interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 5.1.6 data link timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 5.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 5.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5.3.1 pecl?input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.3.2 pecl?output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.3.3 single-ended pecl input (sigdet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.4 cx28250 electrical and mechanical description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 5.4.1 cx28250 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 appendix apecl applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 a.1 cx28250 to 3.3 v pmd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 a.2 cx28250 to 5 v pmd inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-3
table of contents cx28250 atm physical interface (phy) devices vi mindspeed technologies ? 28250-dsh-002-c a.3 cx28250 to 5 v pmd outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-6 appendix b related standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1 appendix cregister summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-1
cx28250 list of figures atm physical interface (phy) devices 28250-dsh-002-c mindspeed technologies ? vii list of figures figure 1-1. cx28250 connected to a sar (cx28234/cx28236) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 figure 1-2. cx28250 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 figure 1-3. cx28250 pinout diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 figure 1-4. cx28250 detailed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 figure 2-1. cx28250 transmitter block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 figure 2-2. cx28250 receiver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2 figure 2-3. cx28250 low voltage pecl (lvpecl) interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 figure 2-4. single-ended pecl diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 figure 2-5. schematic detail of analog components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2- 7 figure 2-6. bellcore gr-253-core jitter specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2- 8 figure 2-7. sts-3c/stm-1 basic frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10 figure 2-8. sts-3c/stm-1 frame timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11 figure 2-9. switch initiation time graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 figure 2-10. j0/j1 buffer behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 figure 2-11. cell delineation process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 figure 2-12. header error check process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 figure 2-13. interrupt indication diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44 figure 2-14. line and path fail indication diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-45 figure 2-15. near-end line loopback diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48 figure 2-16. utopia loopback diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49 figure 2-17. source loopback diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50 figure 3-1. cx28250 and cx28236 sar application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 figure 3-2. schematic detail of analog components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 4 figure 3-3. tx and rx filter layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 figure 3-4. analog power supply connections (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 figure 3-5. cx28250/cx28236 evm block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 figure 5-1. input waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 figure 5-2. output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 figure 5-3. synchronous mode, read timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 figure 5-4. synchronous mode, write timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 figure 5-5. asynchronous mode, read timing (high-performance access time) . . . . . . . . . . . . . . . 5-10 figure 5-6. asynchronous mode, write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 12 figure 5-7. transmit utopia interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 figure 5-8. receive utopia interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 figure 5-9. jtag timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 figure 5-10. one-second timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 figure 5-11. data link receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-19 figure 5-12. data link transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 figure 5-13. 156-pin ball gate array (bga) package?top and side views . . . . . . . . . . . . . . . . . . . . . 5-25 figure 5-14. 156-pin ball gate array (bga) package?bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 figure 5-15. land patterns for the cx28250 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26
list of figures cx28250 atm physical interface (phy) devices viii mindspeed technologies ? 28250-dsh-002-c figure a-1. cx28250 to 3.3 v pmd diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-2 figure a-2. cx28250 pecl to 5 v pecl (capacitive coupled) in terface . . . . . . . . . . . . . . . . . . . . . . . . a-4 figure a-3. cx28250 to 5 v pmd inputs diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a- 5 figure a-4. cx28250 to 5 v pmd outputs diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-7 figure a-5. pecl layout diagram (3.3 v inputs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-7
cx28250 list of tables atm physical interface (phy) devices 28250-dsh-002-c mindspeed technologies ? ix list of tables table 1-1. cx28250 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 table 2-1. pecl input logic table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 table 2-2. sonet overhead byte definitions and values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 table 2-3. section overhead transmit and receive functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 table 2-4. lstatout configuratio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 table 2-5. line overhead transmit and receive functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 table 2-6. h1, h2, and h3 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 table 2-7. signal fail/signal degrade. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 table 2-8. s1 byte description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 table 2-9. path overhead transmit and receive functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 table 2-10. transmitted rdi-p values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 table 2-11. receiver rdi-p interpretation (f or the cx28250-23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 table 2-12. erdi interrupt (CX28250-26 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-27 table 2-13. control bit functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32 table 2-14. cell screening - matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33 table 2-15. cell screening - accept/reject cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33 table 2-16. cell format for 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36 table 2-17. cell format for 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36 table 2-18. utop1 register, bits [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39 table 2-19. interrupt suppression during error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46 table 4-1. control and status registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 table 4-2. general use registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 table 4-3. cell transmit control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 table 4-4. cell receive control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 table 4-5. utopia control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 table 4-6. sonet overhead transm it control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 table 4-7. sonet overhead recei ve control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 table 4-8. status and interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 table 4-9. counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 table 4-10. clkrec valid configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 table 5-1. timing diagram nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 table 5-2. synchronous mode, read timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 7 table 5-3. synchronous mode, write timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 -9 table 5-4. asynchronous mode, read timing table (high-performance access time). . . . . . . . . . . . 5-11 table 5-5. asynchronous mode, write timing table (high-performance access time) . . . . . . . . . . . 5-12 table 5-6. transmit utopia interface timing table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 14 table 5-7. receive utopia interface timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 16 table 5-8. jtag timing table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 table 5-9. one-second timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 table 5-10. data link receive timing table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 table 5-11. data link transmit timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 table 5-12. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 table 5-13. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 table 5-14. pecl-input dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 table 5-15. pecl-output dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
list of tables cx28250 atm physical interface (phy) devices x mindspeed technologies ? 28250-dsh-002-c table 5-16. single-ended pecl table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 table c-1. cx28250 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-2
28250-dsh-002-c mindspeed technologies ? 1-1 1 1.0 product description the cx28250 atm physical layer interface (phy) device is a transmitter/receiver that converts sonet/sdh frames to atm cells and vice versa, like the transmission convergence (tc) sublayer. this chapter provides an overview of the cx28250, including its primary features and applications. a logic diagram, package pinouts, an d pin descriptions are also presented. a block diagram is in cluded to show the data flow in the device.
1.0 product description cx28250 1.1 cx28250 features atm physical interface (phy) devices 1-2 mindspeed technologies ? 28250-dsh-002-c 1.1 cx28250 features the cx28250, operating at up to 155 mbps (duplex), provides a single-access atm service termination for user-to-network interfacing (uni) and network-to-network interfacing (nni) in conformance with the atm forum uni specification 94/0317, itu recommendation i.432 , and other industry standards. this phy device consists of several fu nctional blocks: the sonet framer, the atm cell formatter, the utopia level 2 interface, and the microprocessor interface. together these blocks and th e clock recovery block provide efficient conversion of sonet frames to atm cells and vice versa. the cx28250 is implemented in 0.35 micron cmos technology, which runs on 3.3 v, and is packaged in a 156-pin ball grid array (bga). this low-power device processes sts-3c/stm-1 data stre ams at 155 mbps (duplex) and provides a pseudo-emitter coupled logic (pecl) interface for serial connection to a physical media dependent (pmd) device. it has a synchronous 16-bit wide, four-cell deep fifo buffer and an 8-bi t microprocessor bus interface, which is used for configuration, status, and co ntrol of the device. furthermore, the cx28250 output control signals can drive light emitting diodes (leds) for monitoring data and alarm activity. the cx28250 descrambles received data, then uses the payload pointer (h1, h2) to locate and retrieve the sonet payload envelope. it also processes section, line, and path overhead. atm cells are extracted from the payload envelope according to the atm cell delineatio n standards. the cx28250 optionally performs payload descrambling, header error checking (hec) error detection and correction, and idle cell filtering. error counts are kept at all levels for performance monitoring. the cx28250 generates a transmit payload pointer (h1, h2) and framing bytes (a1, a2). the device also performs hec generation, idle cell insertion, and atm cell payload scrambling. the cx28250 synthesizes the 155.52 mhz transmit clock from a 19.44 mhz, 8 khz frequency reference, or can use the clock from the internal clock recovery circuit. when necessary, the cx28250 inserts lin e and path alarm signals and remote defect indications (rdis). it also in serts path and line rei codes to allow performance monitoring at the far end. ad ditionally, all-0s data can be inserted for diagnostic purposes. the two far end status output pins indicate whether a path fail or line fail alarm condition has occurred. these pins are software configurable.
cx28250 1.0 product description atm physical interface (phy) devices 1.2 applications overview 28250-dsh-002-c mindspeed technologies ? 1-3 1.2 applications overview the cx28250 can be used in a number of applications: ? atm lans over optical fibers workstations and pc network interface cards (nics) lan switches and hubs sonet or sdh compliant atm unis the device is typically used in combination with a segmentation and reassembly (sar) device, such as the cx28236 sar, to provide framing along with segmentation and reassembly of atm traffic. it can be used in switch-to-switch links and switch-to-terminal links. the cx28250 connects to the sar via the utopia and micr oprocessor interfaces (see figure 1-1 ). it can be either loop-timed or source-timed. the device can be configured and controlled through a generic microproce ssor interface. for more info rmation on applications for the cx28250, see chapter 3.0 . figure 1-1. cx28250 connected to a sar (cx28234/cx28236) 500035_002 cx28250 cx28234/cx28236 sram fiber or cat 5 pci bus pmd interface utopia bus interface local bus interface pci interface utopia interface microprocessor interface utopia bus local bus note(s): 1. the cx28234 sar has an 8 bit utopia level 1 interface. 2. the cx28236 sar has a 8/16 bit utopia level 1/2 interface and supports multi-phy operation.
1.0 product description cx28250 1.3 logic diagram atm physical interface (phy) devices 1-4 mindspeed technologies ? 28250-dsh-002-c 1.3 logic diagram figure 1-2 is a logic diagram of the cx28250 functional blocks. there are seven general purpose clock and control pins . the pmd interface is comprised of 12 pins. the microprocessor interface consis ts of six clock and control inputs, an 8-bit data bus, and a 7-bit address bus. th ere are five jtag pins and eight status pins. the utopia interface consists of 26 transmit pins and 26 receive pins. there are 10 power pins and 13 ground pins. pin descriptions are given in table 1-1 .
cx28250 1.0 product description atm physical interface (phy) devices 1.3 logic diagram 28250-dsh-002-c mindspeed technologies ? 1-5 figure 1-2. cx28250 logic diagram signal detection phase lock loop clock transmit clock input receive data input receive clock input utopia transmit address utopia transmit start-of-cell utopia transmit parity input reset one-second clock sync 8 khz ref. clock input transmit data link input processor clock address strobe,write control write/read~,read control chip select utopia transmit clock address bus utopia transmit enable sync/async mode select microprocessor transmit clock output transmit data output lsigdet lpllclk ltxclki+/- lrxdata+/- ltxclko+/- ltxdata+/- pmd line interface i i i i lrxclk+/- i o o o o o i/o mdata[7:0] interface i i i i i mclk, macssel mas*, mwr* mw/r*, mrd* mcs* maddr[6:0] mint* o reset onesecin 8khzin txdl clock and control one-second output onesecout i msyncmode i = input, o = output 8 khz transmit frame clock txframeref 8 khz receive frame clock rxframeref i i i processor data bus microprocessor interrupt test reset test clock test data output tdo utxaddr[4:0] trst* tck o status o status output utopia receive cell available utopia receive start of cell statout[7:0] urxclav urxsoc urxprty utxsoc utxprty utopia transmit urxdata[15:0] o utopia receive data bus utxclk utxenb* utxclav utopia transmit cell available jtag test mode select tms test data input tdi utopia receive utopia transmit data utxdata[15:0] i utopia receive clock urxclk utopia receive enable urxenb* utopia receive address urxaddr[4:0] i i i i i i i i i i i i o o o o data link i 500035_003 insert path ais insert line ais inspthais inslnais i i o o line fail output lfout path fail clock pfout mrdy o microprocessor ready receive pll filter neg. input lrxpfn i utopia receive parity receive pll filter pos. input lrxpfp i ltxpfn o transmit pll filter pos. output ltxpfp o transmit pll filter neg. output
1.0 product description cx28250 1.4 cx28250 pinout and pin descriptions atm physical interface (phy) devices 1-6 mindspeed technologies ? 28250-dsh-002-c 1.4 cx28250 pinout and pin descriptions figure 1-3 is a pinout diagram of the cx2825 0 atm transmitter/receiver. it is a cmos integrated circuit p ackaged in a 156- pin bga. all unused input pins should be connected to ground. unused outputs should be left unconnected. figure 1-3. cx28250 pinout diagram (top view) 1234567891011121314 1234567891011121314 a b c d e f g h j k l m n p a b c d e f g h j k l m n p statout[4] urxaddr[1] urxdata[13] urxdata[8] urxdata[3] inslnais statout[1] mint- statout[2] urxaddr[3] urxdata[14] urxdata[7] urxdata[2] lfout statout[0] mcs* pwr pwr urxaddr[4] nc urxdata[10] urxdata[4] pwr statout[3] urxaddr[2] pwr urxdata[9] gnd urxenb* mw/r*,mrd* mas*,mwr* gnd maddr[6] gnd maddr[3] maddr[2] maddr[4] gnd mdata[7] maddr[0] mdata[6] gnd mdata[5] mdata[4] pwr pwr mdata[2] mdata[0] gnd ltxclki- msyncmode reset* pwr pwr pwr gnd nc onesecin onesecout 8khzin tdo gnd pwr vgg utxaddr[4] txframeref txdl lpllclk ltxclk0- gnd lrxpfp utxaddr[3] rxframeref tms gnd ltxdata- lrxdata- utxaddr[0] tck gnd ltxdata+ gnd utxaddr[2] utopmode trst* ltxpfp ltxclk0+ lrxdata+ utxaddr[1] utxdata[0] mclk,macssel pwr nc lsigdet nc utxdata[1] tdi ltxpfn lrxpfn lrxclk+ utxdata[2] gnd mdata[1] ltxclki+ mdata[3] mrdy gnd maddr[1] maddr[5] gnd urxaddr[0] pwr pwr gnd utxenb* utxsoc utxciav inspthais utxdata[15] pfout nc utxdata[13] utxdata[11] utxdata[10] utxdata[8] ubuswidth utxdata[7] gnd utxdata[6] pwr utxdata[3] lrxclk- utxdata[4] utxdata[5] utxdata[9] utxdata[12] utxdata[14] utxprty utxclk statout[6] urxprty urxdata[12] pwr urxciav urxcik statout[5] gnd urxdata[11] urxdata[5] urxdata[0] urxsoc statout[7] urxdata[15] urxdata[6] urxdata[1] gnd 500035_042
cx28250 1.0 product description atm physical interface (phy) devices 1.4 cx28250 pinout and pin descriptions 28250-dsh-002-c mindspeed technologies ? 1-7 pin names and numbers are listed in table 1-1 . an asterisk (*) following a pin label indicates that the pin logic level is active low. table 1-1. cx28250 pin definitions (1 of 12) pin label signal name no. type i/o description clock and control reset* device reset m3 ttl i this pin is used to reset the device when asserted low. onesecin one-second strobe m2 ttl i this input is us ed to latch device status, typically at 1-second intervals. onesecout one-second output n1 ttl o this pin is a 1-second count derive d from the 8khzin input. txframeref transmit frame clock n 2 ttl o this pin can be either an 8 khz output derived from the transmit sonet/sdh frame or a 19.44 mhz output derived from the transm it clock, as selected by bit 1 of the txsec (0x0c) register. rxframeref receive frame clock p2 ttl o the output of this pin is either an 8 khz or 19.44 mhz reference derived from th e recovered clock. the frequency is determined by bit 1 in the rxsec register. during a los condition the ne west versions of the cx28250, (-26 and above), auto matically de rive this output from the lpllclk i nput until the recovered clock is available. 8khzin 8 khz reference clock input n3 ttl i this pin is an 8 khz clock input used to derive onesecout. pll filters ltxpfn transmit pll filter negative input l6 ? i this pin connects to the rc filter as shown in figure 2-5 . ltxpfp transmit pll filter positive input m6 ? i this pin connects to the rc filter as shown in figure 2-5 . lrxpfn receive pll filter negative input l10 ? i this pin connects to the rc filter as shown in figure 2-5 . lrxpfp receive pll filter positive input p11 ? i this pin connects to th e rc filter as shown in figure 2-5 .
1.0 product description cx28250 1.4 cx28250 pinout and pin descriptions atm physical interface (phy) devices 1-8 mindspeed technologies ? 28250-dsh-002-c pmd line interface ltxclk? line transmit clock input negative polarity l2 pecl i 155.52 mhz line transmit clock input. an external line-rate clock may optiona lly be provided on this input to drive the sonet/sdh transmit line data when the transmit synt hesizer nor loop timing mode is enabled. this clock source is selected by bits 3 and 4 in the clkrec register (0x01). the clock source should be 155.52 mhz with an accuracy of +/- 20 ppm. tie this pin high through a 10k resistor if unused. ltxclk+ line transmit clock input positive polarity k4 pecl i complement of the abov e pecl line transmit clock input. tie this pin low through a 10 k resistor if unused. ltxclko? line transmit clock output negative polarity p7 pecl o 155.52 mhz clock output derived from one of three clock sources: transmit synthesizer, recovered receive clock, or the ltxclki+/- inputs. the clock source is selected by bi ts 3 and 4 of the clkrec register (0x01). it is gene rally used for diagnostic purposes. ltxclko+ line transmit clock output positive polarity m8 pecl o complement of the abov e pecl line transmit clock output. ltxdata? line transmit output negative polarity p8 pecl o sonet/sdh formatte d line transmit data. ltxdata+ line transmit output positive polarity n8 pecl o complement of the abov e pecl line transmit data output. lrxclk? line receive clock negative k12 pecl i 155.52 mhz line recei ve clock input. an external line-rate clock may optiona lly be provided on this input to clock the sonet/sd h receive line data when the internal cdr is not be ing used. this clock source can be selected by bit 5 of the clkrec register (0x01). the clock source should be 155.52 mhz with an accuracy of +/- 20 ppm. tie this pin high through a 10k resistor if unused. lrxclk+ line receive clock positive l12 pecl i complement of the abov e pecl line receive clock input. tie this pin low through a 10k resistor if unused. lrxdata? line receive input negative p10 pecl i sonet/sdh li ne receive data. lrxdata+ line receive input positive m10 pecl i complement of the a bove pecl line receive data input. lsigdet line signal detection l9 ttl i this pin is normally connected to the signal valid output of the pmd and must be asserted high when the pmd is receiving a vali d signal. designs that do not use a signal valid from the pmd must tie this input high. table 1-1. cx28250 pin definitions (2 of 12) pin label signal name no. type i/o description
cx28250 1.0 product description atm physical interface (phy) devices 1.4 cx28250 pinout and pin descriptions 28250-dsh-002-c mindspeed technologies ? 1-9 pmd line interface (cont) lpllclk line phase loop lock clock p5 ttl i 19.44 mhz reference clock input used by the cdr and the transmit sy nthesizer plls. the cdr uses this clock as a reference to recover the 155.52 mhz clock from the line receive data. the transmit synthesizer uses this clock to generate a 155.52 mhz line transmit clock. this clock should have an accuracy of 20 ppm. microprocessor interface mclk, macssel microprocessor clock, access time select l3 ttl i when msyncmode is set to a logic 1, the mclk pin is a clock signal that samples the microprocessor interface pins (mcs*, mw /r*, mas*, maddr[6:0], mdata[7:0]) on its rising e dge. additionally, the rising edge of mclk may cause th e microprocessor interface output pins (mdata[7:0], mi nt*) to change states. when msyncmode is set to a logic 0, the macssel pin selects the asynchronous interface access time. a logic 0 selects a power-sav ing access mode (130 ns) while a logic 1 selects th e high-performa nce access mode (80 ns). msyncmode microprocessor synchronous/asynch ronous bus mode select m1 ttl i a logic 1 selects the synchronous bus mode compatible with mindspeed atm sar devices. in this mode, the microprocessor pins are defined as follows: mclk, mw/r*, mas*, mcs*, mint*, maddr, and mdata. a logic 0 selects the asynchronous sram-type bus mode. in this mode, the pins are defined as follows: macssel, mrd*, mwr*, mcs*, mint*, maddr, and mdata. mcs* microprocessor chip select c1 ttl i when mcs* is set to a logic 0, the device is enabled for read and write accesses. when mcs* is set to a logic 1, the device does not respond to input signal transitions on mclk, macs sel; mw/r*, mrd*; or mas*, mwr*. additionally, when mcs* is set to a logic 1, the mdata[7:0] pi ns are in a high-impedance state but the int* pin remains operational. table 1-1. cx28250 pin definitions (3 of 12) pin label signal name no. type i/o description
1.0 product description cx28250 1.4 cx28250 pinout and pin descriptions atm physical interface (phy) devices 1-10 mindspeed technologies ? 28250-dsh-002-c microprocessor interface (cont.) mw/r*, mrd* microprocessor write/read, read control c2 ttl i when msyncmode is set to a logic 1, this pin is a read/write control pin. in this mode, when mw/r* is set to a logic 1, a write access is enabled, and the mdata[7:0] pin values are written to the memory location indicated by the madd r[6:0] pins. also in this mode, when mw/r* is set to a logic 0, a read access is enabled and the memory location indicated by the maddr[6:0] pins is read and its value placed on the mdata[7:0] pins. both read and write accesses assume the device is chip selected (mcs* = 0), the address is valid (mas* = 0) , and the device is not being reset (reset* = 1). when msyncmode is set to a logic 0, this pin is a read control pin. in this mode, when rd* is set to a logic 0, a read access is enabled and the memory location indicated by the ma ddr[6:0] pins is read and its value placed on the md ata[7:0] pins. the read access assumes the device is chip selected (mcs* = 0), a write access is not being requested (mwr* = 1), and the device is not be ing reset (reset* = 1). mas*, mwr* microprocessor address strobe, write control d2 ttl i when msyncmode is set to a logic 1, this pin is an address strobe pin. when the mas* pin is set to a logic 0, it indicates a valid address, maddr[6:0]. this signal is used to qualify read and write accesses. when msyncmode is set to a logic 0, this pin is a write control pin. when mwr* is set to a logic 0, a write access is enabled and the mdata[7:0] pin values are written to the memory location indicated by the maddr[6:0] pins. the writ e access assumes the device is chip selected (mcs* = 0), a read access is not being requested (mrd* = 1), and th e device is not being reset (reset* = 1). maddr[6] microprocessor address bus e3 ttl i these seven bits are an address input for identifying the register that is accessed. maddr[5] e4 ttl i maddr[4] f2 ttl i maddr[3] f1 ttl i maddr[2] f3 ttl i maddr[1] f4 ttl i maddr[0] g2 ttl i table 1-1. cx28250 pin definitions (4 of 12) pin label signal name no. type i/o description
cx28250 1.0 product description atm physical interface (phy) devices 1.4 cx28250 pinout and pin descriptions 28250-dsh-002-c mindspeed technologies ? 1-11 microprocessor interface (cont.) mdata[7] microprocessor data bus g3 ttl i/o these eight bits are a bidirectional data bus for transferring the read and write data. mdata[6] h1 ttl i/o mdata[5] h2 ttl i/o mdata[4] j1 ttl i/o mdata[3] j4 ttl i/o mdata[2] k1 ttl i/o mdata[1] k3 ttl i/o mdata[0] k2 ttl i/o mint* microprocessor interrupt b1 ttl o when a logic 0 is read on this pin, the device needs servicing. it remains asserted until the pending interrupt is acknowledged. this pin is an open drain output for an external wi red or logic implementation. mrdy microprocessor ready h4 ttl o when active high, th e current read or write transaction has been completed. for a read transaction, the data is ready to be transferred to the microprocessor. for a write transaction, the data provided by the microprocessor has been written. this pin is an open drain out put for an external wired or logic implementation. an external pull-up resistor is required for this pin. jtag (see ieee 1149.1a-1993) trst* test reset m4 ttl i when this pin is asserted, the internal boundary-scan logic is reset. this pin has a pullup resistor. note: when jtag is not used , this pin should be tied either directly to ground or through a 1k or less pull down resistor. tck test clock n4 ttl i this pin samples the value of tms and tdi on its rising edge in order to control the boundary scan operations. tms test mode select p4 ttl i this pin contro ls the boundary-scan test access port (tap) controller operation. this pin has a pullup resistor. tdi test data input l4 ttl i this pin is the serial test data input. this pin has an internal pullup resistor. tdo test data output n5 ttl o this pin is the serial test data output. table 1-1. cx28250 pin definitions (5 of 12) pin label signal name no. type i/o description
1.0 product description cx28250 1.4 cx28250 pinout and pin descriptions atm physical interface (phy) devices 1-12 mindspeed technologies ? 28250-dsh-002-c external ais inslnais insert line ais a 13 ttl i when asserted high, the cx28250 will send a line ais indication. this pin has an internal pulldown resistor. inspthais insert path ais f11 ttl i when asse rted high, the cx282 50 will send a path ais indication. this pin has an internal pulldown resistor. lfout line fail output b13 ttl o a high level ou tput on this pin indicates that one (or more) of the line fail status bits in the enlfout, 0x6e, register have been asserted. pfout path fail output f12 ttl o a high level output on this pin indicates that one (or more) of the path fail stat us bits in the enpthout, 0x6f, register have been asserted. table 1-1. cx28250 pin definitions (6 of 12) pin label signal name no. type i/o description
cx28250 1.0 product description atm physical interface (phy) devices 1.4 cx28250 pinout and pin descriptions 28250-dsh-002-c mindspeed technologies ? 1-13 status statout[7] status outputs[7:0] a4 ttl o this pin re flects either the value in bit 7 of the outstat register (0x41) or los, as selected by bit 2 of register gen (0x00). if selected by bit 0 or 1 of rxlin (0x46), this pin will be the d1-d3 or d4-d12 receive data link serial clock output. statout[6] c4 ttl o this pin reflects ei ther the value in bit 6 of the outstat register (0x41) or oof, as selected by bit 2 of register gen (0x00). if selected by bit 0 or 1 of rxlin (0x46), this pin will be the d1-d3 or d4-d12 receive data link serial data output. statout[5] b4 ttl o this pin reflects ei ther the value in bit 5 of the outstat register (0x41) or lop, as selected by bit 2 of register gen (0x00). if selected by bit 0 or 1 of rxlin (0x46), this pin will be the d1-d3 or d4-d12 receive data link indication output. this output is high during the time that clock/da ta outputs c ontain pulses for d1-d3 octets. it is low during the time that clock/data outputs contai n pulses for d4-d12 octets. statout[4] a3 ttl o this pin reflects ei ther the value in bit 4 of the outstat register (0x41) or ais-l, as selected by bit 2 of register gen (0x00). if selected by bit 4 of txlin (0x0d) or bit 6 of txsec (0x0c), this pin will be the d1-d3 or d4-d12 transmit data link serial clock output. statout[3] c3 ttl o this pin reflects ei ther the value in bit 3 of the outstat register (0x41) or rdi-l, as selected by bit 2 of register gen (0x00). if selected by bit 4 of txlin (0x0d) or bit 6 of txsec (0x0c), this pin will be the d1-d3 or d4-d12 transmit da ta link indication output. this output is high during th e time that clock/data inputs are expected for d1-d3 octets, and low for d4-d12. statout[2] b3 ttl o this pin reflects ei ther the value in bit 2 of the outstat register (0x41) or ais-p, as selected by bit 2 of register gen (0x00). if selected by bit 4 of txlin (0x0d) or bit 6 of txsec (0x0c), this pin will output a pulse at the beginning of ev ery cell slot time (both idle and data cells), sy nchronized to the utopia transmit side. statout[1] a2 ttl o this pin reflects ei ther the value in bit 1 of the outstat register (0x41) or rdi-p, as selected by bit 2 of register gen (0x00). statout[0] b2 ttl o this pin reflects ei ther the value in bit 0 of the outstat register (0x41) or locd, as selected by bit 2 of register gen (0x00). data link txdl transmit data link input p3 ttl i this pin is used to seri ally transmit data over the d1-d3 and d4-d12 data link. table 1-1. cx28250 pin definitions (7 of 12) pin label signal name no. type i/o description
1.0 product description cx28250 1.4 cx28250 pinout and pin descriptions atm physical interface (phy) devices 1-14 mindspeed technologies ? 28250-dsh-002-c utopia transmit utxclk utopia transmit clock d14 ttl i the data transfer/interfa ce byte clock is provided by the atm layer to the phy layer for synchronizing transfers on utxdata. utxenb* utopia transmit enable e11 ttl i the enable data transfers signal is active low. it is asserted by the atm layer during cycles when utxdata contains valid cell data. utxaddr[0] lsb utopia transmit address msb p12 ttl i these pins are the addr ess of the phy device being selected. the address is driven from the atm to the multi-phy layer to poll a nd select the appropriate multi-phy device. each multi-phy device must maintain its address. address 31 indicates a null phy port. utxaddr[1] m12 ttl i utxaddr[2] n12 ttl i utxaddr[3] p13 ttl i utxaddr[4] n13 ttl i utxdata[0] utopia transmit data m14 ttl i the data bus is driven from the atm layer to the phy. utxdata[15] is the msb of the high octet and utxdata[7] is the msb of the lower octet. utxdata[1] l13 ttl i utxdata[2] l14 ttl i utxdata[3] k13 ttl i utxdata[4] k14 ttl i utxdata[5] j14 ttl i utxdata[6] j12 ttl i utxdata[7] j11 ttl i utxdata[8] h13 ttl i utxdata[9] h14 ttl i utxdata[10] h11 ttl i utxdata[11] g12 ttl i utxdata[12] g14 ttl i utxdata[13] g13 ttl i utxdata[14] f14 ttl i utxdata[15] f13 ttl i utxprty utopia transmit parity input e14 ttl i the transmit data bus checks for odd parity over utxdata [7:0] coming from the atm layer. in 16-bit mode, it checks for odd pa rity over utxdata[15:0]. table 1-1. cx28250 pin definitions (8 of 12) pin label signal name no. type i/o description
cx28250 1.0 product description atm physical interface (phy) devices 1.4 cx28250 pinout and pin descriptions 28250-dsh-002-c mindspeed technologies ? 1-15 utopia transmit (cont.) utxsoc utopia transmit start of cell e13 ttl i the start of cell signal is active high. it is asserted by the atm layer during cycles when utxdata contains the first valid byte of the cell. utxclav utopia transmit cell available e12 ttl o this signal indicates fifo full or cell buffer available. for octet-level flow control, this signal is active low from the phy layer to the atm layer. it is asserted to indicate that a maximum of four more transmit data writes will be accepted. for cell-level flow cont rol in an multi-phy environment, utxclav is an active high signal with high impedance potential going from the multi-phy layer to the atm layer. a polled multi-phy device drives this signal only during each cycle following one with its address on the utxaddr lines. the polled multi-phy device asserts ut xclav high to indicate it can accept the transfer of a complete cell, otherwise it deasserts the signal. (1) utopia receive urxclk utopia receive clock c14 ttl i the data transfer/interfa ce byte clock is provided by the atm layer to the phy layer for synchronizing transfers on urxdata. urxenb* utopia receive enable c13 ttl i the enable rece ive data signal is active low. it is asserted by the atm layer to indicate that urxdata and urxsoc will be sampled at the end of the next cycle. in support of mult iple phy configurations, when urxenb* is asserted, the urxdata and urxsoc phy layer ou tputs change to a high-impedance state. urxd ata and urxsoc must be enabled only in cycles foll owing those with urxenb* asserted. urxaddr[0] utopia receive address d6 ttl i this is the address of th e phy device being selected. it is driven from the atm to the multi-phy layer to poll and select the appropriate multi-phy device. urxaddr [4] is the msb. ea ch multi-phy device must maintain its address. address 31 indicates a null phy port. urxaddr[1] a5 ttl i urxaddr[2] c5 ttl i urxaddr[3] b5 ttl i urxaddr[4] d5 ttl i table 1-1. cx28250 pin definitions (9 of 12) pin label signal name no. type i/o description
1.0 product description cx28250 1.4 cx28250 pinout and pin descriptions atm physical interface (phy) devices 1-16 mindspeed technologies ? 28250-dsh-002-c utopia receive (cont.) urxdata[0] utopia receive data bus b12 ttl o the data bus is driven from the atm layer to the phy layer. urxdata[15] is the msb of the high octet and urxdata[7] is the msb of the lower octet. to support multiple phy configurations , urxdata can be placed in a high-impedance state which is enabled only when urxenb* is asserted. urxdata[1] a12 ttl o urxdata[2] b11 ttl o urxdata[3] a11 ttl o urxdata[4] d11 ttl o rxdata[5] b10 ttl o urxdata[6] a10 ttl o urxdata[7] b9 ttl o urxdata[8] a9 ttl o urxdata[9] c9 ttl o urxdata[10] d9 ttl o urxdata[11] b8 ttl o urxdata[12] c8 ttl o urxdata[13] a7 ttl o urxdata[14] b7 ttl o urxdata[15] a6 ttl o urxprty utopia receive parity c6 ttl o the data bus pa rity is odd parity for urxdata[7:0], driven by the phy layer. in 16-bit mode, this is the odd parity bit over ur xdata[15:0]. to support multiple phy configurations , urxprty can be placed in a high-impedance state which is enabled only in cycles following those with urxenb* asserted. (1) urxsoc utopia receive start of cell b14 ttl o the start of cell signal is active high. it is asserted by the phy layer when rxdata contains the first valid byte of the cell. in support of multiple phy configurations, when urxenb* is asserted, the urxdata and urxsoc phy layer outputs change to a high-impedance state. urxd ata and urxsoc must be enabled only in cycles foll owing those with urxenb* asserted. (1) ubuswidth utopia bus width h12 ttl i this pin sele cts the default value for the utopia bus width. the state of this pin w ill be latched into bit 3 of the utop1 register on power-up or reset. tie it low for 16 bit utopia; tie high for 8 bit utopia. it has an internal pull-down resistor. note that this pin is a ?no connect? on the cx28250-23. table 1-1. cx28250 pin definitions (10 of 12) pin label signal name no. type i/o description
cx28250 1.0 product description atm physical interface (phy) devices 1.4 cx28250 pinout and pin descriptions 28250-dsh-002-c mindspeed technologies ? 1-17 utopia receive (cont.) utopmode utopia mode n14 ttl i this pin sele cts the default value for the utopia mode. the state of this pin wi ll be latched into bit 5 of the utop1 register on power-up or reset. tie it low for utopia level 1; tie it high for utopia level 2. it has an internal pull-up resistor. note that this pin is a ?no connect? on the cx28250-23. urxclav utopia receive cell available c12 ttl o this signal indicates fifo empty or cell buffer available. for octet-level fl ow control, this signal is active low from the phy layer to the atm layer. it is asserted to indicate that in the current cycle there is no valid data for delive ry to the atm layer. for cell-level flow cont rol in an multi-phy environment, urxclav is an active high signal with high impedance potential going from the multi-phy layer to the atm layer. a polled multi-phy device drives this signal only during each cycle following one with its address on the urxaddr lines. the polled multi-phy device asserts ur xclav high to indicate it has a complete cell available for transfer to the atm layer, otherwise it deasserts the signal. (1) supply voltage pwr 3.3 v digital supply voltage c7 c10 d1 d3 d8 d10 d13 j2 j3 k11 ? ? digital power supply pins. analog pwr 3.3 v analog supply voltage l5 m5 m7 m9 n9 ? ? analog power pins. see section 3.2.1 . table 1-1. cx28250 pin definitions (11 of 12) pin label signal name no. type i/o description
1.0 product description cx28250 1.4 cx28250 pinout and pin descriptions atm physical interface (phy) devices 1-18 mindspeed technologies ? 28250-dsh-002-c supply voltage (cont.) gnd ground a8 b6 c11 d4 d12 e1 e2 g1 g4 h3 j13 l1 m11 n6 n7 n10 p6 l8 p9 ? ? these pins are ground connections. v gg electrostatic discharge (esd) supply voltage n11 ? ? this pin is an esd suppl y connection. if using this device in a system with 5 v logic, this pin must be connected to 5 v. if using in a 3.3 v system only, connect to 3.3v. note(s): (1) cx28250 defaults to utopia level 2 when reset causing the txclav , rxclav, rxsoc, and rxpr ty signals to be in high-impedance state. this ma y cause initialization problems for atm layer utopia level 1 device s. therefore, it is recommended that pulldown resist ors be used for these devices. table 1-1. cx28250 pin definitions (12 of 12) pin label signal name no. type i/o description
cx28250 1.0 product description atm physical interface (phy) devices 1.5 block diagram and descriptions 28250-dsh-002-c mindspeed technologies ? 1-19 1.5 block diagram and descriptions figure 1-4 is a detailed block diagram of the cx28250. when traffic is transmitted from the host sy stem, octet-wide or 16-bit data enters the cx28250 via the utopia port. the cx28250 assemb les the host data into atm cells and formats it for serial-line transmi ssion by the sonet line framer. in the receive direction, the sonet line framer frames serial network data into octets and passes it to the atm cell processing block. octet data is then aligned into atm cells, checked, and sent to the utopia port. the line framer block connects to extern al interfaces for data reception and transmission. also included are overhead interfaces, data links, and event counters. the hec atm cell alignment block accept s octet data from the line framer block. it generates cells for transmission and validates received cells. included are hec generators and detectors, data scramblers, and counters. the utopia interface communicates with the next layer of atm processing. it controls transmit priori ty and rate, and has counters for events and errors. figure 1-4. cx28250 detailed block diagram mrdy atm wire interface utopia level 2 interface host interface transmit utopia level 2 4-cell fifo pecl logic level utxclk urxclk sonet line framer microprocessor interface cell counters performance monitoring interrupt control rx cell validation rx vpi/vci screening tx cell generation tx overhead insert transmit line interface loopback control sts-3c/stm-1 receive framer receive line interface and clock recovery receive cell alignment clock and control sts-3c/stm-1 transmit framer rx overhead extract atm cell framer host interface receive utopia level 2 4-cell fifo mint* maddr[6:0] mdata[7:0] control lines ltxdata+/- ltxclki+/- ltxclko+/- lrxdata+/- lrxclk+/- sigdet utxclav utxenb* utxsoc utxaddr[4:0] urxclav urxenb* urxsoc urxprty urxaddr[4:0] tck onesecin 8khzin onesecout rxframeref jtag controller trst* tms tdi tdo status statout[0:7] pllclk (19.44 mhz) 500035_005 txframeref utxdata[15:0] txprty urxdata[15:0] txdl inspthais inslnais pfout lfout
1.0 product description cx28250 1.5 block diagram and descriptions atm physical interface (phy) devices 1-20 mindspeed technologies ? 28250-dsh-002-c
28250-dsh-002-c mindspeed technologies ? 2-1 2 2.0 functional description this chapter describes the cx28250 architecture and functional blocks. figure 2-1 shows the cx28250 transmit signal path. the cx28250 calculates the hec for incoming atm cells from the utop ia interface and inserts it into the fifth octet of each cell. the result is formatted into sonet frames and converted to serial data. one of three clock sources is used to synchronize the outgoing data stream over the pecl interface. figure 2-1. cx28250 transmitter block diagram framer overhead input at m cell gen. parallel data out utopia fifo parallel to serial serial pecl nrz data pecl interface tx data tx clock clock select 19.44 mhz rx clock 155.52 mhz (external) 500035_006
2.0 functional description cx28250 atm physical interface (phy) devices 2-2 mindspeed technologies ? 28250-dsh-002-c figure 2-2 shows the cx28250 receive signal path. the cx28250 recovers the clock from the incoming data stream and converts the serial data stream to parallel and passes it to the framer block, which extracts the overhead bytes. hec alignment is performed to recover the star t of cell boundary. the cells are then sent over the utopia bus to the atm layer device. figure 2-2. cx28250 receiver block diagram mux serial to parallel framer pecl nrz data octets clock recovery hec align. at m cell receiver overhead output utopia fifo overhead processor rx clock external clock recovery 500035_007
cx28250 2.0 functional description atm physical interface (phy) devices 2.1 line interface 28250-dsh-002-c mindspeed technologies ? 2-3 2.1 line interface the cx28250 communications with the external network through its line interface. this is a pseudo-emitter couple d logic interface also referred to as a low voltage pecl. this requires the same voltage differentials as on standard emitter coupled logic (ecl) devices but is referenced to a positive voltage rather than ground. it uses the voltage differential to determine the logical value as shown in table 2-1 . absolute values are given in section 5.3 . note that unused inputs of a pecl pair should be connected to ground or vcc (one input to ground and the other to vcc). this prevents internal circuitr y from toggling due to noise on the inputs. this interface uses the workable inte rface requirements example (wire) modulation as defined by the atm forum. it can connect to industry standard physical media dependent (pmd) devices for either fiber optic cable or cat 5 utp (unshielded twisted pair). 2.1.1 pecl interface the selection of the correct pecl bias network is dependant on the pmd device selected. for 3.3 volt pmd's th at can both source and sink current (that is they do not put their outputs into a high z condition for a logic 0). see figure 2-3 for pmd's that run at 5 volts or that require that the logic low output voltage be set by an external resistor networ k, the designer should consult the pmd manufacturer's data sheet and appendix a of this document. table 2-1. pecl input logic table input + input - internal logic level 00 invalid 01 0 10 1 11 invalid
2.0 functional description cx28250 2.1 line interface atm physical interface (phy) devices 2-4 mindspeed technologies ? 28250-dsh-002-c figure 2-3. cx28250 low voltage pecl (lvpecl) interface 500035_054 optical transceiver rd- rd+ z=50 z=50 130r 130r 100r 100r z=50 z=50 cx28250-23, -25 td+ td- 82r 130r vcc(3.3 v) sd lrxdata- lrxdata+ ltxdata+ ltxdata- lsigdet place near transceiver place near cx28250 3.3 v 3.3 v note(s): 1. the 100 ohm resistor is built in the cx28250 for the lrxdata+ and lrxdata- termination. 2. the ltxdata+ and ltxdata- outputs are internally biased and therefore do not require external bias resistors. 3. the termination resistors on the lsigdet input are necessary only for transceivers with a pecl level signal detect (sd) output.
cx28250 2.0 functional description atm physical interface (phy) devices 2.1 line interface 28250-dsh-002-c mindspeed technologies ? 2-5 2.1.1.1 pecl layout all pecl traces must be treated as tr ansmission lines. therefore, standard high-speed practices must be followed: keep traces as short as reasonable. do not allow traces to cross disconti nuities in the ground/power planes. use separate power and ground planes. terminate all inputs and outputs as described above. place the terminating resistors as cl ose to the destination ic as possible. do not route signal traces through the board through vias. check that each ic has two high-quality rf bypass capacitors that are at least an order of magnitude apart; e.g., 200 pf and 0.1 f. avoid 90 degree turns in trace routing. ensure that the trace width results in a line impedance that matches the input impedance of the load. trace width can be calculated from the following equation: where: w = trace width z 0 = characteristic line impedance h = board thickness (not including copper layers) t = thickness of copper layers e r = relative dielectric constant of the board using the generic values z 0 = 50 ?, h = 0.060, t = 0.0015 and e r = 4.8 results in a width (w) of 0.11 inches. w 7.745 he e r 1.41 + z 0 87 -------------------------------------- ? ?? ?? ?? t 0.8 ------- ? =
2.0 functional description cx28250 2.1 line interface atm physical interface (phy) devices 2-6 mindspeed technologies ? 28250-dsh-002-c 2.1.2 signal detect interface the lsigdet pin on the cx28250 indicate s when the pmd has lost its signal. if the lsigdet goes low, the cx28250 internally forces its receive data to logic ?0? to prevent false framing indications. de signs that don?t use the lsigdet input must tie this pin high and then ensure that they either externally force the receive data to a logic ?0? or detect false fr aming/cell delineation indications with software. the lsigdet pin can be driven by ttl or pecl drivers. the cx28250 can be connected directly to a ttl interface without external components. when using a single-ended pecl interface, a st andard pecl termination of 50 ? to v cc ? 2 v is required for most pmds. the pecl te rmination can be implemented by using the thevenin equivale nt circuit shown in figure 2-4 . figure 2-4. single-ended pecl diagram +3.3 v r 2 = 82 ? r 1 = 130 ? pmd cx28250 lsigdet signal detect (sd) internal logic ? + vsref 500035_008 note: the termination network shown is valid for a 3.3 v pmd. for a 5.0 v pmd, please refer to figure 3-4. 3.3 v 3.3 v
cx28250 2.0 functional description atm physical interface (phy) devices 2.1 line interface 28250-dsh-002-c mindspeed technologies ? 2-7 2.1.3 pll filter network three external networks ar e required as shown in figure 2-5 . it is important that these components are located as cl ose to the cx28250 as possible. note that the ground side of the tx filt ers are tied together and then run to an analog ground pin. it is important that both filters are at the same ground potential relative to the analog ground pins. there is also a 'guard ring' around these networks to provide immunity from low frequency noise. these rings should have numerous ground vias tying them directly to the ground plane. mindspeed recommends using a 5% npo grade capacitor for c27. this is to ensure that the design will meet jitter sp ecifications over the temperature range of -40 to +85 c. the customer may relax this tolerance based on their own requirements. figure 2-5. schematic detail of analog components 500035_049 note: 1. all capacitors are 10% ceramic unless noted otherwise. 2. all resistors are 1%. 3. connections between filter networks and n6 should be as short as possible. 4. r1 and c1 are not populated. they are used for device verification, and are not needed in production. m6 l10 p11 2.2 f 470 pf 0.015f 270 pf 604 ? 68.1 ? n6 0.015f 604 ? 1 f l6 r1 c1
2.0 functional description cx28250 2.2 clock circuits atm physical interface (phy) devices 2-8 mindspeed technologies ? 28250-dsh-002-c 2.2 clock circuits the clock circuit has a receiver sectio n and a transmit section. the transmit section synthesizes the 155.52 mhz clock used for transmitting data. one of three clock sources can be selected by bits 3 and 4 of the clkrec register (0x01). by default, this clock is synthesized from the 19.44 mhz lpllclk reference input pin. if a 155.52 mhz clock is provided, it can be used directly as the transmit clock (bypassing synthesis altogether). the external clock must be accurate to within 20 ppm of 155.52 mhz. the clock can be synthesized from the received data via the cdr section. the receiver section uses an internal ph ase locked loop (pll) to recover the clock from the incoming nrz data stream. the clock recovery circuit requires the 19.44 mhz clock from an independent external source that meets 20 ppm accuracy. when no nrz data is present or when the signal detect input (lsigdet) is low, indicating that the signal has b een lost by the optical transceiver, the receive clock recovery circuit free-runs at a nominal 155.52 mhz so that there is always a receive clock present for the receive data path and the transmit path for loop-timed applications. the recovered clock meets jitter tolerance and jitter transfer specifications according to bellcore gr-253 (see figure 2-6 ). jitter tolerance is defined as how much jitter the receiver can tolerate and still extract the correct data from the incoming signal. jitter transf er is the maximum amount of jitter that any device is allowed to add to the data stream. figure 2-6. bellcore gr-253-core jitter specifications the jitter generation shall be less than 0.01 ui rms and shall also be less than 0.10 ui pp . slope = -20 db/decade 15ui 1.5ui 0.15ui jitter tolerance jitter generation: slope = -20 db/decade 0.1db 130 khz jitter transfer 10 hz 30 hz 300 hz 6.5 khz 65 khz 500035_009
cx28250 2.0 functional description atm physical interface (phy) devices 2.2 clock circuits 28250-dsh-002-c mindspeed technologies ? 2-9 2.2.1 loss of lock loss of lock (lol) status indicate s that the receive pll has lost synchronization. when lol occurs, bit 6 of the secint register (0x3d) is asserted if it has been enabled by bit 6 of the ensec register (0x35). lol also appears in bit 6 of the rxsec register (0x45). lol can also be enabled to appear on lfout and pfout outputs via the registers enlfout and enpfout. the cx28250 provides the following two clock outputs that are phase locked to the transmit and receive clocks. txframeref: this is an 8 khz or 19.44 mhz reference derived from the transmit clock. its frequency and polari ty are controlled by bits 0 and 1 in the txsec register. rxframeref: the output of this pi n is either an 8 khz or 19.44 mhz reference derived from the recovered cl ock. its frequency and polarity are controlled by bits 0 and 1 in the rxsec register. during a los condition the newest versions of the cx28250, (-26 and above), automatically derive this ou tput from the lpllclk input until the recovered clock is available. on older versions, (such as the -23), this output is shut off during los and lof conditions.
2.0 functional description cx28250 2.3 sonet/sdh framer and overhead processor atm physical interface (phy) devices 2-10 mindspeed technologies ? 28250-dsh-002-c 2.3 sonet/sdh framer and overhead processor mindspeed?s cx28250 sonet/sdh framer has an extensive sonet overhead processing section with external access for d1 -d3 and d4-d12 data link message processing. the framer provides da ta transmission at a standard bit rate, frequency justification, pointer proce ssing, and sonet frame delineation. the sonet overhead processor provides frame synchronization, byte scrambling and descrambling, and byte mul tiplexing and demultiplexing. the frame structure for sts-3c/stm-1 ca n be envisioned as a 270-column by nine-row rectangle of bytes (octets) shown in figure 2-7 . the transmission of the block starts with the first row, working from left to right, then moves to the second row, left to right, and so on down to the byte in the bottom right corner. thus, the transport overhead octets are actually transmitted in nine groups of nine octets, equally spaced throughout the frame. since there are 270 x 9 bytes, the data rate is 270 x 9 x 8 (bits/bytes) x 8,000 fps. (the frame period is 125 micro-seconds) = 155.52 mbps. figure 2-7. sts-3c/stm-1 basic frame 500035_010 column row transport path section spe payload line a1-1 a1-2 a1-3 a2-1 a2-2 a2-3 h1-1 h1-2 h1-3 h2-1 h2-2 h2-3 h3-1 h3-2 h3-3 j0 z0 1 z0 2 j1 b1 b3 00 00 00 000 00 000 d1 d4 0 0 d5 0 0 d6 00 d7 0 0 d8 0 0 d9 00 00z20 000 d10 s1 m1 00 d11 0 0 d12 d2 0 0 0 0 d3 c2 g1 b2-1 b2-2 b2-3 k1 0 0 0 0 0 0 0 k2
cx28250 2.0 functional description atm physical interface (phy) devices 2.3 sonet/sdh framer and overhead processor 28250-dsh-002-c mindspeed technologies ? 2-11 figure 2-8 provides a linear representation of sts-3c/stm-1 framing. this framing is similar to t1 framing except that sonet delineates the frame with a block of octets, a1 and a2, instead of just one bit. there is payload data in the areas between overhead blocks. in sts-3c , the payload is called the synchronous payload envelope (spe). in sdh, the payload is called virtual container 4 (vc4). this document uses spe to re fer to the payload in either format. figure 2-8. sts-3c/stm-1 frame timing transport overhead payload row 1 13.88 row 9 125 time in micro-seconds 0 sts-3c/stm-1 frame 500035_011
2.0 functional description cx28250 2.3 sonet/sdh framer and overhead processor atm physical interface (phy) devices 2-12 mindspeed technologies ? 28250-dsh-002-c the sonet framer block recovers the a1/a2 framing location from octet-delineated data provided by the cl ock recovery front-end. this block also performs the pointer processing and generates row and byte counts to identify locations within the frame to the s onet overhead proc essor. the sonet framer block interfaces directly with the sonet overhead block and provides status bits to the sonet overhead processor for presentation in status registers. the sonet overhead block uses defined overhead bytes in an sts-3c/stm-1 frame for performance monitoring, fault management, and facility testing. the sonet overhead bytes used in the cx28250 are listed in table 2-2 . table 2-2. sonet overhead byte definitions and values layer byte function value section a1 framing f6 h a2 framing 28 h j0 section trace 01 h or 64-byte section trace message z0 1 z0 2 section growth ?national bytes? 02 h (default: see the txz0 1 register) 03 h (default; see the txz0 2 register) b1 section error monitoring bip-8 d1, d2, d3 data link channel ? line h1, h2, h3 pointer/concatenation indicator path ais see table 2-6 b2-1, b2-2, b2-3 line error monitoring bip-24 k1, k2 (bits 1-5) aps channel 0000 h (default) k2 (bits 6-8) no alarm line ais line rdi 0 h (default) 7 h 6 h d4-d12 data link channel ? s1 synchronization status programmable z1 line growth 00 (default : see the rxz2 register) m1 line rei b2 error count path j1 path trace 00 h or 64-byte path trace message b3 path error monitoring bip-8 c2 path signal label: atm path signal label: equipped nonspecific path signal label: unequipped user defined for non-atm applications 13 h (default) 01 h 00 h xx g1 (bits 1-4) path rei b3 error count g1 (bits 5-7) no alarm path rdi alarms 0 h (default) 2 h, 5 h, 6 h z2 received value monitored
cx28250 2.0 functional description atm physical interface (phy) devices 2.3 sonet/sdh framer and overhead processor 28250-dsh-002-c mindspeed technologies ? 2-13 2.3.1 loss of signal by default, the scrambled sts-3c/stm-1 data is monitored for the absence of 1s. when 1620 consecutive octets (6 sonet rows) of 0s are detected, los is declared. los is cleared when two va lid framing words (a1/a2) are received with no intervening los detection. the los condition is reflected in register rxsec (0x45) bit 5. in addition, statout[ 7] is asserted if status output pin mode, bit 2 of the gen register (0x00), is enabled. the CX28250-26 version can also be configured to detect the lack of transitions on the incoming data. thus ei ther the all zeroes or a ?stuck at 1? condition will result in the device d eclaring los. this on ly applies to the CX28250-26 version. note: if the lsigdet pin goes low, then the rece ive data is internally forced to all zeros to ensure that los is recognized. 2.3.2 section overhead the section overhead handles the transp ort of the sts-3c/stm-1 frame across the physical medium and section-level communications. its functions are framing and scrambling on the transmit side, and section error monitori ng on the receive side. the transmit and receive function s of the section overhead bytes are described in table 2-3 . 2.3.2.1 a1, a2 the sts-3c/stm-1 framing by tes, a1 and a2, are used to determine oof status. when these octets match the framing patter n, the status is ?in-frame.? when there are four consecutive frames with one or more framing pattern errors, oof is declared. this condit ion asserts statout[6] and is reflected in register rxsec (0x45) bit 4. the transmit a1/a2 bytes can be disabled by writing bit 4 in the txsec (0x0c) register to 1. a1 can be inverted by writing bit 7 in the errins (0x06) register to 1. one valid a1/a2 frame clears oof status. 2.3.2.2 loss of frame a loss of frame (lof) condition is declared when out-of-frame (oof) status exists for 24 consecutive frames. this condition is cleared when oof status has been clear for 8 consecutive frames. lof is reflected in register rxsec (0x45) bit 3. table 2-3. section overhead transmit and receive functions byte transmit receive a1/a2 f6/28 hex or disable 00 moni tor out of frame state machine b1 calculated, error insertion option checked, errors counted d1, d2, d3 00 hex or external serial access external serial access j0 01 hex or 64-byte trace buffer moni tor rx trace buffer, interrupt on change z0 1 , z0 2 controlled by the txz01 and txz02 registers (defaults to 02 and 03 respectively) stored in the rxz01 and rxz02 registers (interrupt generated on change)
2.0 functional description cx28250 2.3 sonet/sdh framer and overhead processor atm physical interface (phy) devices 2-14 mindspeed technologies ? 28250-dsh-002-c 2.3.2.3 b1 the section bit interleaved parity (bip)-8 byte, b1, is allocated for section layer error monitoring. this byte contains a bip-8 code using even parity. the code is calculated using all the bits of th e previous sts-3c/stm-1 frame after scrambling. each piece of section termin ating equipment calculates the b1 byte of the current sts-3c/stm-1 frame and compares it with the b1 byte received from the next sts-3c/stm-1 frame. if the b1 bytes match, there is no error. if the b1 bytes do not match, the alarm indicator is set. the b1 bytes of the rest of the sts-3c/stm-1 frame are not defined. as many as 64 kb errors per second can be detected. these section level bit errors are gathered in a 16-bit counter (registers b1cntl [0x54] and b1cnth [0x55]). the counter is latched so that it can continue to count while the latch is being read. this prevents the loss of any error counts. 2.3.2.4 d1-d3 the cx28250 provides access to two data link channels, d1?d3 and d4?d12, via the statout pins and the txdl pin. independent control is provided for receiving and/or transmitting data ov er each channel, as outlined in table 2-4 . table 2-4. lstatout configuration bit 2 genregister txsec register txlin register rxsec register rxlin register statout[7] statout[6] statout[5] statout[4] statout[3] statout[2] statout[1] statout[0] 0 0 0 0 0 los oof lop ais-l rdi-l ais-p rdi-p locd 1 0 0 0 0 outstat[7] outstat[6] outstat[5] outstat[4] outstat[3] outstat[2] outstat[1] outstat[0] x x x 1 x rx clock output rx data output rx channel indicator note 1note 1note 1note 2note 2 x x x x 1 rx clock output rx data output rx channel indicator note 1note 1note 1note 2note 2 x 1 x x x note 1 note 1 note 1 tx clock output tx channel indicator tx cell sync note 2 note 2 x x 1 x x note 1 note 1 note 1 tx clock output tx channel indicator tx cell sync note 2 note 2 note(s): (1) any combination of the four data link control bits is allowed and overrides the statpinmode bit for statout[7:2]. statout pins not being used for the data link operate as determined by statpinmode. (2) statout[1] and statout[0] are only co ntrolled by statpinmode and are unaffect ed by the data link control bits.
cx28250 2.0 functional description atm physical interface (phy) devices 2.3 sonet/sdh framer and overhead processor 28250-dsh-002-c mindspeed technologies ? 2-15 data link transmit the cx28250 can insert data into the d1?d12 octets of the outgoing data stream. this function is controlled by entxsecdl, bit 6 of the txsec, 0x0c register and entxlindl, bit 4 of the txlin, 0x0 d register. when entxsecdl is set to 1, serial data input on the dltxdata pi n is inserted into the d1, d2, and d3 octets. likewise, setting entxlindl to 1 results in the serial data from the dltxdata pin being inserted in the d4 through d12 octets of the outgoing stream. the cx28250 indicates that it is ready for d1, d2, and d3 octets by outputting a logic high on the statout[3] pin; it outputs a logic low when d4-d12 data is expected. if either entxsecdl or entxlindl is set, the corresponding octets will be filled with 0x00. statout [2], statout [3] and statout [4] are redefined whenever entxsecdl or entxlindl are set. statout [2]: this pin outputs a pulse at the beginning of ever y cell slot time, (both idle and data cells), synchronized to the utopia transmit side. this is provided for sar scheduling activities. statout [3]: this becomes the transmit data link indicator, txdli, output. serial data provided on dltxdata when this pin is high is transmitted in octets d1, d2, and d3. when this line is low, da ta from the dltxdata pin is inserted into octets d4 through d12. statout [4]: the transmit clock for dl data is output on this pin. data link receive access to incoming octets d1?d12 is provided via the statout[5], statout[6], and statout[7] pins. this function is controlled by bits 0 and 1 of the rxlin, 0x46, register as shown on page 45. when either of these bits is set high, the statout pins are defined as follows: statout[5]: this becomes the receive data link indicator, rxdli, output. incoming octets d1, d2, and d3 are output serially on statout[6] pin when this output is high. when this line is low, da ta from octets d4 through d12 are output serially on statout [6] pin. statout [6]: this pin outputs the inco ming data in a serial bit stream synchronized to the clock on statout[7]. statout [7]: this output is the serial data clock for incoming data and is synchronized with statout [6]. refer to section 5.1.6 for the data link timing.
2.0 functional description cx28250 2.3 sonet/sdh framer and overhead processor atm physical interface (phy) devices 2-16 mindspeed technologies ? 28250-dsh-002-c 2.3.2.5 j0 the section trace byte, j0, is connected to a circular 64 -byte buffer, carrying the section trace message, which allows sect ion elements to track a continuous connection. this buffer over writes when full. this message is user-programmable but generally is an 8-bit ascii clli? code padded with ascii null characters and terminated with cr and lf characters making up 64 bytes total. if section trace is enabled, the user is re quired to enter a message or the current contents of the transmit buffer will be transmitted. the j0 transmit buffer is located in register txsecbuf (0x68). j0 can be disabled via register txsec (0x0c), bit 5. if j0 is disabled the transmit ted j0 byte will be set to 0x01. the j0 receive buffer is accessed via rxsecbuf (0x6a). if the incoming message differs from the previous message stored in the receive buffer an interrupt appears in register secint (0x3d) bit 1. the j0 transmit and receive circular buffers operate the same as the j1 byte circular buffers; see figure 2-10 . a receive trace message must be received three times before a new value is latched into the receive trace buffer. at the completion of the three frame integration period an interrupt will be generated to signal that the trace message contents have changed. inte rmittent changes to these bytes over consecutive frames will not trigger er roneous interrupts. this reduces the impact on software performance and effort. receive j0 trace buffer contents are updated as described above at all times except during los or oof conditions. during these conditions, buffer contents will remain unchanged from previous values. transmit buffer contents are tran smitted at all times (when enabled) regardless of any incoming receive errors. note: it takes 192 sonet frames to tran smit 3 complete trace buffers. in the -23 version only the cx28250-23 version does not have a three-frame integrator. therefore, any change in the incoming messa ges generates an interrupt. 2.3.2.6 z0 full access to both z0 transmit and receive octects is provided. z0 transmit the section growth bytes, z0 1 and z0 2 , are set to defaults of 02 and 03, respectively. these values can be overwritten by changing the contents of the txz0 1 and txz0 2 registers. z0 receive value the incoming z0 octets from the sonet overhead are latched into the rxz0 1 , 0x1a, and rxz0 2 , 0x1b, registers after a 3 frame integration period. if either value changes and the interrupt is enabled, a single event interrupt is generated in bit 1 of the linint register, 0x3e. note th at this interrupt is shared with the z2 octet. z2 receive value the incoming z2 octet from the sonet overhead is latched into the rxz 2 , 0x17, registers after a 3 frame integration peri od. if the value changes and the interrupt is enabled, a single event interrupt is generated in bit 1 of the linint register, 0x3e. note that this interrupt is shared with the z0 1 and z0 2 octets.
cx28250 2.0 functional description atm physical interface (phy) devices 2.3 sonet/sdh framer and overhead processor 28250-dsh-002-c mindspeed technologies ? 2-17 2.3.3 line overhead the line overhead handles the transport of path-level payloads across the physical medium. this layer of the ov erhead provides synchronization and multiplexing functions for the line layer. these functions include maintenance and line protection. the section overhead must be terminated before the line overhead can be accessed. the transm it and receive functions of the line overhead are described in table 2-5 . table 2-5. line overhead transmit and receive functions byte transmit receive h1/h2 620a/93ff hex pointer full gr.253 pointer processor h3 00 hex used in pointer processor b2 calculated, error insert ion checked, errors counted k1/k2 insertable via register checked, interrupt on change d4-12 00 hex or external serial access external serial access s1 insertable via register checked, interrupt on change z2 generated from the contents of txz2 checked, interrupt on change after a 3 frame integration m1 line rei inserted checked, errors counted
2.0 functional description cx28250 2.3 sonet/sdh framer and overhead processor atm physical interface (phy) devices 2-18 mindspeed technologies ? 28250-dsh-002-c 2.3.3.1 h1, h2, and h3 bytes h1, h2, and h3 in the sts-3c/stm-1 frame are fixed on the transmit side to locate path overhead byte j1 immediately after the z0 2 byte of the section overhead. the receive side performs all processing according to gr-253. 2.3.3.2 loss of pointer a loss of pointer (lop) condition is declared when eight frames of invalid h1, h2 octets are detected. this condition is cleared when three valid h1, h2 pointer frames occur. lop is described in register rxlin (0x46) bit 7. table 2-6. h1, h2, and h3 functions overhead byte sts-3c value (in hex) stm-1 value (in hex) error conditions h1-1 transmit 62 6a ff hex is inserted via line ai s control bit, inslnais (bit 3) in the txlin register (0x0d). 33 hex is inserted for invalid pointer via control bit dispntr (bit 6) in the txlin register (0x0d). h1-2 transmit 93 93 ff hex is inserted via line ai s control bit, inslnais (bit 3) in the txlin register (0x0d). h1-3 transmit 93 93 ff hex is inserted via line ai s control bit, inslnais (bit 3) in the txlin register (0x0d). h2-1 transmit 0a 0a ff hex is inserted via line ai s control bit, inslnais (bit 3) in the txlin register (0x0d). 33 is inserted for invalid pointer via control bit dispntr (bit 6) in the txlin register (0x0d). h2-2 transmit ff ff ff hex is inserted via line ai s control bit, inslnais (bit 3) in the txlin register (0x0d). h2-3 transmit ff ff ff hex is inserted via line ai s control bit, inslnais (bit 3) in the txlin register (0x0d). h3-1 transmit 00 00 ff hex is inserted via line ai s control bit, inslnais (bit 3) in the txlin register (0x0d). h3-2 transmit 00 00 ff hex is inserted via line ai s control bit, inslnais (bit 3) in the txlin register (0x0d). h3-3 transmit 00 00 ff hex is inserted via line ai s control bit, inslnais (bit 3) in the txlin register (0x0d).
cx28250 2.0 functional description atm physical interface (phy) devices 2.3 sonet/sdh framer and overhead processor 28250-dsh-002-c mindspeed technologies ? 2-19 2.3.3.3 b2-1, b2-2, and b2-3 the line bip-8 bytes, b2-1, b2-2, and b2 -3, are used for line error monitoring. similar to the b1 byte in the section over head, b2 also uses bit interleaved parity (bip-24) code with even parity. it contai ns the result from the calculation of all the bits of the line overhead and sts-1 envelope capacity of the previous sts-1 frame before scrambling. one byte (either b2-1, b2-2, or b2-3) in the line overhead is allocated for a line bip-8 calculation on each sts-1 line within the sts-3c/stm-1 section. the line bip-8 is calculated for all the bits of the sts-1 line overhead and envelope capacity of the previous frame before scrambling. thus, in an sts-3c/stm-1 signal, 3 bytes (b2-1, b2-2, and b2-3) ar e used for the error monitoring function. as many as 192 k errors per second can be detected. the errors are accumulated in an 18-bit counter (b 2cntl, b2cntm, b2 cnth; 0x50, 0x51, 0x52). the counter is latched so that it can continue counting while the latch is being read. this prevents loss of any error counts. errors can be inserted via register e rrins (0x06), bits 5, 4, and 3. bit 5 corresponds to b2-1, bit 4 corresponds to b2-2, and bit 3 corresponds to b2-3.
2.0 functional description cx28250 2.3 sonet/sdh framer and overhead processor atm physical interface (phy) devices 2-20 mindspeed technologies ? 28250-dsh-002-c 2.3.3.4 aps threshold automatic protection switching (aps) thre sholds are monitored by estimating the incoming bit error rate (ber) and se tting an alarm status bit and interrupt when the programmed threshold is crossed. two thresholds are supported: one for signal degrade (sd) and one for signal fail (sf). each threshold is programmable for ber levels from 10 -3 to 10 -9 in the apsthresh register (0x09). table 2-7 describes the programming range for the thresholds in apsthresh. the alarm clearing threshold and observation time are automatically set to 1/10 of the pr ogrammed alarm detection threshold. the implementation supports the aps switch initiation time requirements shown in figure 2-9 (from bellcore standard gr-253-core ). the implementation estimates the incoming ber to a >95% confidence level by observing the number of errors per frame as monitored by the b2 line bip bytes. table 2-11 describes the required confidence interval for estimating ber versus programmed threshold level. in additio n, table 2-8 describes the actual observation time implemented by the cx 28250 threshold monitor. this time is the maximum interval for the cx28250 to notify via status/interrupt that the programmed threshold has been crossed. these alarm notification times allow software time to process the interrupt an d initiate the switchi ng function within the required switch initiation time. if the incoming ber is actually hi gher than the programmed threshold, notification takes place in the amount of time listed for the threshold that matches the incoming ber. for example, if the sf threshold is programmed to monitor for ber at a level of 10 -5 (notification time 16 ms or less) but the actual incoming ber is 10 -3 the sf status/interrupt is set within 1 ms instead of waiting until the end of the 16 ms window. this allows switch initiation to begin based on the actual incoming ber level versus the pr ogrammed level as required by bellcore standard gr-000253-core. alarm clearing (when the ber drops below 1/10 of the programmed threshold) requires observation of the ber for the entire duration of the window as listed for th e programmed threshold level. interrupts occur both when the detection threshol d is crossed (ber exceeds programmed threshold) and when the alarm is cleared (ber is below 1/10 of the programmed threshold). table 2-7. signal fail/signal degrade sf thresh (bits 7-4) sd thresh (bits 3-0) detection threshold clearing threshold 95% confidence interval cx28250 observation time required switch initiation time 0 h to 3 h 10 -3 10 -4 64.5 s1 ms 8 ms 4 h 10 -4 10 -5 645 s 2 ms 13 ms 5 h 10 -5 10 -6 6.45 ms 16 ms 100 ms 6 h 10 -6 10 -7 64.5 ms 128 ms 1 s 7 h 10 -7 10 -8 645 ms 2.048 s 10 s 8 h 10 -8 10 -9 6.45 s 16.384 s 83 s 9 h to f h 10 -9 10 -10 64.5 s 131 s 667 s note(s): in the cx28250-23 and earlier versions, the sf/sd thres holds should not be cha nged during alarm conditions. mindspeed recommends setting the logi c reset bit when changing values.
cx28250 2.0 functional description atm physical interface (phy) devices 2.3 sonet/sdh framer and overhead processor 28250-dsh-002-c mindspeed technologies ? 2-21 figure 2-9. switch initiation time graph 0.001 0.01 0.1 1.0 10 100 1000 10,000 10 -10 10 -9 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 100,000 ber switch initiation time 10 .008 .013 0.1 1.0 83 667 500035_012
2.0 functional description cx28250 2.3 sonet/sdh framer and overhead processor atm physical interface (phy) devices 2-22 mindspeed technologies ? 28250-dsh-002-c 2.3.3.5 k1 and k2 the aps channel bytes, k1 and k2, ar e allocated for automatic protection switching (aps) signaling between line level entities. these bytes are defined only once in an sts-3c/stm-1 signal. the k1/k2 transmit control registers (0x10/0x11) allow transmission of any value in support of aps. the k2 byte, bits 6-8, remote defect indicato r (rdi), and alarm indication signal (ais), are used to indicate sts line yellow, an alarm condition to the downstream line equipment. the k2 receive status register (0x15) allows observation of incoming octet values. an interrupt can be generated for any change in the received value. the k1/k2 status bit is set when the receive k1/k2 values are the same for three consecutive frames, but different from th e previously latched values. when this occurs, the new values are latched, and an interrupt is generated. a protection switching byte failure (psbf) alarm is declared if no three adjacent frames contain the same k1 value in 12 consecut ive frames. bit 4 of the rxaps register (0x4a) indicates psbf. 2.3.3.6 line rdi the remote defect indication-line (r di-l) signal indicates to a line terminating equipment (lte) that the remote equipment is detecting a defect somewhere along the sonet line. a line rd i condition is declared when bits 6,7, and 8 of the received k2 octet cont ain 110 for five consecutive frames. a line rdi condition is cleared when bits 6,7, an d 8 of the received k2 octet contain any other pattern for five consecutive frames. an interrupt is generated when entering and exiting the rdi-l alarm state. line rdi is inserted into the transmit frame by asserting the inslnrdi bit in the txlin register. this sends the binary code 110 in bits 6, 7, and 8 of the k2 octet. when the autolnrdi bit in the txlin register is assert ed line rdi is automatically generated upon reception of los, lof, or ais-l. if the autolnrdi bit is asserted and none of th e above alarm conditions are present the value of the rdi-l field will be selected from the txk2 register. 2.3.3.7 line ais the alarm indication signal-line (ais-l) is sent to alert the downstream lte that a defect has been detected on the incoming sonet section. bits 6-8 of the k2 octet are also used to convey this information. if the received pattern is 111 for five consecutive frames, an ais-l condition is declared. an ais-l condition is cleared when five consecutive frames do not contain the 111 pattern. an interrupt is generated when entering and exiting the ais-l alarm state. line ais can be transmitted by set ting the inslnais bit in the txlin register. line ais sets all frame values except for the section overhead to 1?s before scrambling. it is sync hronized to frame boundaries. inslnais pin (insert line ais) when asserted high, this input forces th e cx28250 to generate an ais-l, which has the same effect as setting insl nais, bit 3 of the txlin register. lfout (line fail output pin) this output is controlled by the enlfout register, 0x6e. if any of the status bits shown in figure 2-14 are asserted, the lfout pin goes high and stays high until all enabled status bits are low. 2.3.3.8 d4-12 see section 2.3.2.4 .
cx28250 2.0 functional description atm physical interface (phy) devices 2.3 sonet/sdh framer and overhead processor 28250-dsh-002-c mindspeed technologies ? 2-23 2.3.3.9 s1 bits 5?8 of the synchronization status byte, s1, are used to convey the synchronization status of the network elements. bits 1?4 are currently undefined. these status messages provide an indicatio n of the quality of the synchronization source of the sonet signal. this allows the network elements to determine the best synchronization reference availabl e and reconfigure their synchronization references autonomously without creating timing loops. the s1 byte can be read from rxs1 (0x16). it can be transmitted by writing to txs1 (0x12). the values of the s1 byte are described in table 2-8 . 2.3.3.10 m1 the m1 byte handles automatic line rei. it is used to inform the far end transmitting equipment that the receiving en d is getting errors on the data blocks being sent to it. in practice, the receiv er counts the block errors received in a frame (based on b2 bytes) and uses m1 to transmit the number of errors back to the sending equipment. an interrupt is generated when the received m1 octet indicates error counts other than 0. 2.3.4 path overhead the path overhead checks for end-to-end communication integrity. the section and line overhead must be terminated be fore the path overhead can be accessed. the transmit and receive functions of the path overhead are listed in table 2-9 . table 2-8. s1 byte description acronym description quality level lower nibble bits 5,6,7,8 prs stratum 1 traceable 1 0001 stu sync - tracea bility unknown 2 0000 st2 stratum 2 traceable 3 0111 st3 stratum 3 traceable 4 1010 smc sonet min clock traceable 5 1100 st4 stratum 4 traceable 5 1100 dus do not use for sync 7 1111 res reserved for network sync use - 1110 table 2-9. path overhead transmit and receive functions byte transmit receive j1 00 hex or 64-byte trace buffer moni tor rx trace buffer, interrupt on change b3 calculated, error insert ion checked, errors counted c2 13 hex for atm mapping checked for 01 or 13 hex g1 path rei, rdi inserted chec ked, errors counted, status
2.0 functional description cx28250 2.3 sonet/sdh framer and overhead processor atm physical interface (phy) devices 2-24 mindspeed technologies ? 28250-dsh-002-c 2.3.4.1 j1 the path trace byte, j1, is a circular 64 -byte buffer that carries the path trace message, so a receiving path terminating equipment (pte) can verify continued connection to the transmit ting pte. this buffer overwrites when full. this message is user programmable but generally is an 8-bit ascii clli ? code padded with ascii null characters and terminated with cr and lf characters making up 64 bytes total. if path trace is enabled, the user is required to enter a message or the current contents of the tran smit buffer will be tr ansmitted. if j1 is disabled, then 64 zeros are transmitted. j1 can be disabled via register txpth (0x0e), bit 7. the j1 transmit buffer is located in register txpthbuf (0x69). the j1 receive buffer is rxpthbuf (0x6 b). if the incoming message differs from the data stored in the receive buffer from the previous message received, an interrupt appears in register pthint (0x3f) bit 1. figure 2-10 illustrates how the j1 buffer behaves during transmission and reception. figure 2-10. j0/j1 buffer behavior . . . 100992_012a string to be transmitted: 00 01 02 03 04 05 06 07 08 09 0a ... 3b 3c 3d 3e 3f state of the j1 buffer after the 1st frame 0x6b, octet 0 transmitter was at this point in the string when the receiver obtained frame alignment. state of the j1 buffer after the 2nd frame state of the j1 buffer after the 3rd frame state of the j1 buffer after the 64th frame 05 undefined undefined undefined undefined undefined undefined undefined 05 06 undefined undefined 05 06 07 05 06 07 08 09 undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined 3b 3c 3d 3e 3f 00 01 02 03 04 octet 1 octet 2 octet 3 octet 4 octet 54 octet 55 octet 56 octet 57 octet 58 octet 59 octet 60 octet 61 octet 62 octet 63 . . .
cx28250 2.0 functional description atm physical interface (phy) devices 2.3 sonet/sdh framer and overhead processor 28250-dsh-002-c mindspeed technologies ? 2-25 in the -26 version only a receive trace message must be received three times before a new value is latched into the receive trace buffer. at the completion of the three frame integration period an interrupt will be generated to signal that the trace message contents have changed. inte rmittent changes to these bytes over consecutive frames will not trigger er roneous interrupts. this reduces the impact on software performance and effort. receive j1 trace buffer contents are updated as described above at all times except during los, lof, ais-l, ais-p, or lop-p conditions. during these conditions, the buffer contents will remain unchanged from previous values. transmit buffer contents are transm itted at all times (when enabled) regardless of any incoming receive errors. note: it takes 192 sonet frames to tran smit 3 complete trace buffers. 2.3.4.2 b3 the path bip-8 byte, b3, is allocated for path error monitoring . the path b3 byte is calculated over all bits of the previo us sts spe frame before scrambling, using bit-interleaved parity 8 code with even parity. as many as 64 k errors per second can be detected. b3 can be disabled by writing bit 6 in the txpth (0x0e) register to 1. in addition to counting b3 errors, th e CX28250-26 version of the device has programmable ber thresholds to allow th e generation of interrupts. this is identical to the aps (b2) error reporting except the thresholds are programmable from 10 ?4 to 10 ?9 (refer to table 2-7 ). this only applies to the CX28250-26 version. 2.3.4.3 c2 the path signal label byte, c2, identifies the type of payload being received. the default code transmitted by the cx28250 is 13 hex for atm mapping. however, it can be changed to any other value in the txc2 register (0x13). the receiver expects 01, 13, fc, or ff hex to be received as valid code words. the sonet block monitors the incoming c2 and genera tes one of two possible interrupts if 5 consecutive invalid values are received. if the received value is 00 hex, an unequipped path (uneq-p) interrupt is generated in bit 2 in the pthint register (0x3f). if any other invalid value is received, a payload label mismatch in path (plm-p) interrupt is generated in bit 3 in the pthint register.
2.0 functional description cx28250 2.3 sonet/sdh framer and overhead processor atm physical interface (phy) devices 2-26 mindspeed technologies ? 28250-dsh-002-c 2.3.4.4 g1 the path status byte, g1, is used to convey path terminating status and performance monitoring information back to an originating sts pte. this feature permits the status and performance of the complete duplex path to be monitored at either end, at any point alon g that path. bits 1?4 contain the remote error indication (rei) count, which is the number of errors indicated by the b3 byte. the rei bits have nine valid values (0000?1000). a value greater than 8 is counted as having no errors. bits 5?7 are a path rdi (yellow alarm) indication. bits 5?7 in the g1 byte are used for path rdi (rdi-p) indications. the transmitter automatically generates rdi-p indications in these three bits if the autopthrdi control (bit 1 in txpth 0x0e) is set to a 1. table 2-10 lists the values that are transmitted for various receiver alarm conditions. the user can override these values by se tting autopthrdi to 0 and directly writing the desired value to be transmitted into txpth bits 3?1. the receiver observes the incoming g1 byte to monitor for rdi-p alarms. when 10 consecutive frames of the same value are received, the value is latched into rxg1 (0x19) so that it can be read. an interrup t is generated if the new value represents an alarm condition change. interrupts are generated when entering and exiting alarm conditions. the enhancerdi control bit (enpth 0x37 bit 0) determines whether only bit 5 is observ ed (set to 0 to interwork with old equipment) or bits 5?7 are observed (set to 1 to conform to new equipment standards). table 2-11 summarizes the receiver rdi-p interpretation. table 2-10. transmitted rdi-p values receiver defect transmitter g1 (bits 5-7) none 000 plm-p 010 ais-p, lop-p, los, lof, ais-l 101 uneq-p 110 table 2-11. receiver rdi-p interpretation (for the cx28250-23) incoming rdi-p g1 bits 5-7 enhancerdi=0 interpretation enhancerdi=1 interpretation 000 no remote defect no remote defect 001 no remote defect no remote defect 010 no remote defect remote payload defect 011 no remote defect no remote defect 100 remote defect no remote defect 101 remote defect remote server defect 110 remote defect remote connectivity defect 111 remote defect no remote defect
cx28250 2.0 functional description atm physical interface (phy) devices 2.3 sonet/sdh framer and overhead processor 28250-dsh-002-c mindspeed technologies ? 2-27 path rdi (rdi-p) interrupt generation and rxg1 byte monitoring has been enhanced as follows in the -26 version of the device: 1. a received rdi-p signal is considered valid when the same value in bit 5, 6, 7 of the g1 byte is received in 10 consecutive frames 2. the following rdi-p signals are consid ered ?non defect-indicating?: 000, 011 (non-enhanced), and 001 (enhanced) 3. the following rdi-p signals are consid ered ?defect-indicating?: 100, 111 (non-enhanced), and 010, 101, 110 (enhanced) 4. the status bit (in rxpth) now reflects the state of the last valid rdi-p signal received (i.e. defect, or no defect) 5. interrupts are generated only when a newly received rdi-p signal satisfies one of the following, as compared to the previous rdi-p signal: a. if the newly received rdi-p signal represents a transition of ?defect-indicating? state (i.e., from ?non defect-indicating? to ?defect-indicating ?, or vis-a-vis) b. a new (different) defect-indicating signal has been received as compared to the previous defect-indicating signal. table 2-12 summarizes rdi-p signal transi tions in accord ance with the gr-253 requirements outlined. 2.3.4.5 inspthais input pin (insert path ais) when asserted high, this input forces th e cx28250 to generate an ais-p, which has the same effect as setting the in spthais, bit 4 of the txpth register. 2.3.4.6 pfout output pin (path fail) this output is controlled by the enpfout register, 0x6f. if any of the status bits shown in figure 2-14 are asserted, the pfout pin goes high and stays high until all enabled status bits are low. table 2-12. erdi interrupt (CX28250-26 only) from g1[5:7] 000 001 010 011 100 101 110 111 to g1[5:7] 000 no no yes no yes yes yes yes 001 no no yes no yes yes yes yes 010 yes yes no yes yes yes yes yes 011 no no yes no yes yes yes yes 100 yes yes yes yes no yes yes no 101 yes yes yes yes yes no yes yes 110 yes yes yes yes yes yes no yes 111 yes yes yes yes no yes yes no
2.0 functional description cx28250 2.3 sonet/sdh framer and overhead processor atm physical interface (phy) devices 2-28 mindspeed technologies ? 28250-dsh-002-c 2.3.5 sonet frame scrambler each sonet network element (ne) must have the capability to derive the clock timing from the incoming oc-3c signal. all transmitted oc-3c signals are timed from this clock. therefore, it is importan t to maintain the 1s density in the data stream to ensure enough data transitions for robust clock recovery. the technique commonly used with modems, called scra mbling and descramb ling, is used in sonet to make the data appear to be more random. this process uses a frame synchronous scrambler with a sequence length of 127, operating at the line rate. the generating polynomial is 1+x 6 +x 7 . the scrambler is reset to 1111111 on the most -significant bit of the j1 byte. this bit and all the subsequent bits to be scrambled are added, modulo 2, to the output from the x 7 position of the scrambler. everything but the first row of the section overhead is scrambled. this scrambling o ccurs just before the signal is passed to the pmd sublayer. scrambling can be disabled by setting bit 7 in register txsec (0x0c). all 0s can be sent after scrambling for diagnostic purposes.
cx28250 2.0 functional description atm physical interface (phy) devices 2.4 atm cell processor 28250-dsh-002-c mindspeed technologies ? 2-29 2.4 atm cell processor the cx28250 atm cell processor block is responsible for recovering cell alignment using the hec octet, perfo rming header error correction, and descrambling the payload octets. the resu lting atm cells are then passed to the atm layer via the utopia interface. simultaneously, the atm block is receiving data from the atm layer, opti onally calculating the hec, formatting the 48-octet payload segments into 53-oct et atm cells, and sending the cells to the sonet block. if no data is being received from the atm layer, the cell processor generates idle cells based on the data programmed into the associated registers. the cx28250 has all the counters nece ssary for capturing atm error events and performs the payload crc calculations as required by the aal formats. it generates cell status bits, cell counts, and error counts. 2.4.1 atm cell transmitter the atm cell transmitter controls the gene ration and formatting of 53-octet atm cells that are sent to the framer bloc k. the atm transmitter block formats an octet stream containing atm data cells from the atm layer device when such cells are available. all 53 octets of the da ta cells can be obtained from the external data source and formatted into the outgoing octet stream. this block calculates the hec octet in th e outgoing cell from the header field. the calculated hec octet can be inserted in place of the incoming data octet by writing dishec (bit 7) in the cgen regi ster (0x04) to a logic 0. for testing purposes, this hec octet can be corrupted by xoring the calculated value with a specific error pattern input set in the errp at register (0x07). this hec error is achieved by writing inshecerr (bit 1) in the errins register (0x06) to a logic 1. the remaining 48-octet payload field of the outgoing cell is obtained from the external data source. the payload is normal ly scrambled. this can be disabled by setting bit 2 of the txsec register. when no data is coming from the atm layer, the cx28250 inserts idle cells automatically in the ou tgoing data stream unless bit 0 of txc ell is set to 1. the payload of these cells is read from the tran smit idle cell payload control register, idlpay (0x05). the 4-octet header field for these idle cells comes from the txidl1-4 registers (0x20-23). the he c octet is calculated and inserted automatically. the payload field is filled with the octet contained in the idlpay register (0x05). in normal operation, the 4- octet header field in the outgoing cell is passed on from the atm layer device. header patte rns can be modified in the txhdr1-4 registers (0x1c - 0x1f) and in serted into outgoing cells in place of header bytes received from the atm layer. bits 0-4 in the cgen register (0x04) control whether the original header cells or the replacement cells are sent.
2.0 functional description cx28250 2.4 atm cell processor atm physical interface (phy) devices 2-30 mindspeed technologies ? 28250-dsh-002-c 2.4.1.1 hec generation in normal operation, the cx28250 calculates the hec fo r the 4 header bytes of each cell coming from the atm layer. it then adds the hec coset and inserts the result in octet 5 of the outgoing cell. he c calculation can be disabled by setting bit 7 of cgen (0x04) to a 1. when hec is disabled, the cx28250 leaves the contents of hec field unchanged and transm its whatever data is placed in that field by the atm layer. the hec coset (55 hex, by atm standards) is used to maintain a value other than 0 in the hec field. if the first 4 by tes in the header are 0, the hec derived from these bytes is also 0. when this occurs and there are strings of 0s in the data, the receiver cannot determine cell boundari es. therefore, it is recommended that the value 55 hex be added to the hec be fore transmission. to enable the hec coset on the transmit side, set bit 6 in re gister cgen (0x04) to 1. to enable the receive hec coset, set bit 4 in register cval (0x08) to 1. 2.4.2 atm cell receiver the atm cell receiver performs cell delineation on incoming data cells by searching for the position of a valid hec field within the cell. the hec coset can be either active or inactive, which is determined in bit 4 in the cval (0x08) register. 2.4.2.1 cell delineation the atm block receives octets from the sonet block and recovers atm cells by means of cell delineation. cell delineation is achieved by framing atm cell boundaries using hec coding. four cons ecutive bytes are chosen, and the hec value is calculated. the result is compar ed with the value of the following byte. this ?hunt? is continued by shifting this 4-byte window, one byte at a time, until the calculated hec value equals the received hec value. when this occurs, a pre-sync state is declared, and the next 48 bytes are assumed to be payload. the atm block calculates hec on the 4 bytes fo llowing this payload, assuming that a new cell has begun. if seven consecutive header blocks are found, synchronization is declared. if any hec calculation fails in the pre-sync state, the process begins again (see figure 2-11 ). synchronization is held un til seven consecutive incorrect hecs are received. at this time, the hunt state is reinitiated. when locd occurs, an interrupt is generated and the cx28250 automatically enters the hunt mode. however, the payload is still being scrambled by the far-end transmitter, leaving only the headers un scrambled. this means that the only repetitive byte patterns in the data stream that meet the cell delineation criteria are valid headers.
cx28250 2.0 functional description atm physical interface (phy) devices 2.4 atm cell processor 28250-dsh-002-c mindspeed technologies ? 2-31 when in the sync state of cell delineatio n, cells are passed to the atm block if the hec is valid. if a single -bit error in the header is detected, the error is corrected, optionally, and th e cell is passed to the atm block. if hec checking is enabled and hec correcting is disabled (bit 3 in the cval register [0x08]), cells with single-bit hec errors ar e discarded. if a multi-bit error is detected, the cell is dropped. once either type of error is noted, all subsequent errored cells are dropped until a valid cell is received. this rule applies even for single-bit errors that could be corrected. once a valid ce ll is detected, the process begins again. (see figure 2-12 .) figure 2-11. cell delineation process pre-sync 7 errored hecs 6 correct hecs 1 errored hec 1 correct hec sync hunt 500035_013 figure 2-12. header error check process header error processing in sync state apparent multi-bit error (drop cell) apparent single-bit error (correct error and pass cell) no errors detected (pass cell) correction mode detection mode no errors detected (pass cell) errors detected (drop cell) 500035_014
2.0 functional description cx28250 2.4 atm cell processor atm physical interface (phy) devices 2-32 mindspeed technologies ? 28250-dsh-002-c 2.4.2.2 processing non-standard traffic using the cx28250 the cx28250 contains two independent ?h ec check? state machines. the cell delineator (cd) state machine is used to find cell delineation and, conversely, to declare loss of cell delineation (locd). the other is the cell valid (cv) state machine, which is used to validate the cells to pass to the utopia fifos. these state machines are controlled by two register bits, (cval register, 0x0c), that allow the cx28250 to be programmed for special applications. table 2-13 shows the control bits function. table 2-13. control bit functions dislocd dishecchk description 0 0 normal operation; used for standard atm traffic. cells are output to the utopia fifo only after cell delineation is foun d. only cells with valid hecs are passed (this includes cells with single bit errors that have been corrected). 0 1 ignore hec errors mode; used for ima applications. the cell delineator state machine is active and looking for valid at m cells. it will follow the atm forum?s cell delineation process. however, since the cell valid state machine is turned off, the cx28250 will pass all cells, including those with hec e rrors, to the utopia fifos. the cx28250 will not transf er cells during locd. 1 0 the cell delineation functi on is disabled and every 53 bytes of in coming data is treated as a ?cell?. however, since the cv machine is still active, only ce lls with valid hecs will be output. as a result, almost all data will be dropped. occasionally, random data will ha ve what appears to be a valid hec and will be output. mindspeed is not aware of any use for this mode. 1 1 raw data mode; allows the cx 28250 to be used as a generic ?serial to parallel? convertor. all data received will be passed across the utopia bus in blocks of 53 byte s. no attempt is made to find atm cells. note(s): 1. the hec error correction circui t is independent of th e dishecchk control bit. the cx28250 will correc t single bit errors even when the dishecchk is enabled (assumi ng that the enheccor bit is set to 1).
cx28250 2.0 functional description atm physical interface (phy) devices 2.4 atm cell processor 28250-dsh-002-c mindspeed technologies ? 2-33 2.4.2.3 cell screening the cx28250 provides two optional types of cell screening. the first type, idle cell rejection, prevents idle cells from being passed on. the second type, user traffic screening, compares the incoming bits to the va lues in the receive cell header registers. cells are rejected or accepted based on the bit patterns of their headers. idle cell rejection is enabled in bit 6 of the cval register (0x08). if this bit is set to 1, all incoming cells that match th e contents of the receive idle cell header control registers, rxidl1-4 (0x2c-2f), are rejected. individual bits in the receive idle cell mask control registers, idlmsk1-4 (0x30-33), can be set to be treated as matching, regardless of their value. if idle cell rejection is disabled, cells pass directly to user traffic screening. user traffic cell screening is similar to idle cell screening in that the incoming cells are compared to the receive cell header control registers, rxhdr1-4 (0x24-27). individual bits in the receive cell mask control registers, rxmsk1-4 (0x28-2b), can be set to 1 or a don?t care state, causing the corresponding bits of the incoming cell to be treated as matching, regardless of their values. the rejhdr bi t (bit 7) in the cval regi ster (0x08) determines whether matching cells are rejected or accepte d. if it is set to 0, matching cells are accepted. if set to 1, matching cells are rejected. see table 2-14 and table 2-15 . table 2-14. cell screening - matching receive cell mask bit receive cell header bit incoming bit result 0 0 0 match 001fail 010fail 0 1 1 match 1 x x match table 2-15. cell screening - accept/reject cell cell reject header result match 0 accept cell match 1 reject cell fail 0 reject cell fail 1 accept cell
2.0 functional description cx28250 2.4 atm cell processor atm physical interface (phy) devices 2-34 mindspeed technologies ? 28250-dsh-002-c 2.4.3 cell payload scrambler the atm standard requires cell payload scrambling in order to ensure that only valid headers are found in the cell delin eation process. scrambling randomizes any repeated patterns or other data strings that could be mistaken for valid headers. payload scrambling uses the polynomial x 43 +1 to scramble the payload, leaving the 5 header bytes untouched. payload scrambling is enabled by setting bit 5 in register cgen (0x04). descrambling uses the same polynomial to recover the 48-byte cell payload. the descrambler polynomial is self-synchronizing. it can be enabled by writing bit 5 in register cval (0x08) to 1.
cx28250 2.0 functional description atm physical interface (phy) devices 2.5 utopia interface 28250-dsh-002-c mindspeed technologies ? 2-35 2.5 utopia interface the cx28250 uses the atm forum?s utopia interface as its host interface to communicate with the atm layer device . this interface is utopia level 2 compliant and utopia level 1 compatible. in brief, th ese two specifications are described as follows: utopia level 1: this is an 8- or 16 -bit interface designed for data rates up to 200 mbps. both octet-level an d cell-level handshaking are supported at a clock rate of 25 mhz. octet-level handshaking requires the phy to guarantee the acceptance of at least 4 bytes before it asserts the txfull control line. in cell level, it must guarantee the transfer of at least one entire 53-byte cell. utopia level 2: this interface provides all the features of level 1 plus several enhancements. level 2 defines multi-phy functionality, allowing up to 31 phys to interface to one atm layer device.this interface uses either 8-bit or 16-bit wide data buses and cell-level handshaking. the 16-bit mode, which can run at 50 mhz, supports data rates up to 800 mbps. when using a single phy, mindspeed recommends using the 8-bit, level 1 interface with cell handshaking unless the higher data rates are required. this reduces board size, layout complexity, an d emi with no performance impact at 155.52 mbps. the utopia mode is selected by bit 5 of the utop1 register. the power-on default value of this bit is controlled by the utopmode pin (for the CX28250-26 only). refer to table 1-1 for a description of this pin. 2.5.1 utopia transmit and receive fifos the cx28250 utopia block has two sections, transmit and receive, each of which has a 4-cell fifo buffer. atm cell data is placed in the transmit fifos where it can then be passed to the son et framing block. on the receive side of the utopia interface, incoming cell s are stripped of sonet overhead, converted to atm formatted cells, and pla ced in the receive fifo until sent out. note: by convention, data being transferre d from the phy to the atm layer is labelled received data and data from the atm layer to the phy is called transmitted data.
2.0 functional description cx28250 2.5 utopia interface atm physical interface (phy) devices 2-36 mindspeed technologies ? 28250-dsh-002-c 2.5.2 utopia 8-bit and 16-bit bus widths the cx28250 has two bus width options, 8-bit or 16-bit, which are selected in bit 3 of the utop1 register (0x0a). the protocols and timing are the same in both modes except that 8-bit mode uses only the lower half of the data bus (txdata[7:0] and rxdata[7:0]). note that the power-on default value fo r the utop1 register bit 3 is controlled by the ubuswidth pin (for the CX28250-26 only). refer to table 1-1 for a description of this pin. in 8-bit mode, each atm cell consists of 53 bytes (see table 2-16 ). the first 5 bytes are used for header information. th e remaining bytes are used for payload. in 16-bit mode, the cells consists of 54 bytes (see table 2-17 ). the first 5 bytes contain header information. the sixt h byte, udf2, is requ ired to maintain alignment but is not read by the cx28250. the remaining bytes are used for payload. note: normally, the hec is calculated by the phy and put in byte 5, udf1. however, setting bit 7 of the cgen register (0x04) to 1 disables hec calculation. in this case, data inserted by the atm layer into byte 5 is transmitted by the phy. table 2-16. cell format for 8-bit mode bit 7 ... bit 0 header 1 header 2 header 3 header 4 udf1 (hec) (byte 5) payload 1 ... payload 48 table 2-17. cell format for 16-bit mode bit 15 ... bit 8 bit7 ... bit 0 header 1 header 2 header 3 header 4 udf1 (hec) (byte 5) udf2 (use r definable, see udf2, 0x74) payload 1 payload 2 ... ... payload 47 payload 48
cx28250 2.0 functional description atm physical interface (phy) devices 2.5 utopia interface 28250-dsh-002-c mindspeed technologies ? 2-37 2.5.2.1 user defined udf2 value (receive only) when running in utopia level 2, 16 bit mode, specify the contents of the udf2 octet being sent from the phy to the atm layer by writing the desired value to the udf2 control register, 0x74. this can be used to ?label? incoming cells with the utopia port number that received them. this octet is ignored in utopia leve l 1 or utopia level 2, 8 bit mode. 2.5.3 utopia parity the cx28250 supports even and odd parity, which is controlled by bit 2 of the utop1 register (0x0a). the parity on receiv ed data is calculated for either 8 bits or 16 bits, according to the selected bus width in bit 3 of the utop1 register (0x0a). the result is output on urxprty. likewise, the parity on tran smitted data is calculated for either 8 bits or 16 bits, according to the selected bus width. the calculated result should match the bit present on utxprty. if it does not match, a parity error has occurred. this error can be observed either in the pare rr bit (bit 7) in the txcell register (0x48) or in the parerrint bit (bit 7) in the txcellint register (0x40). systems that do not use parity should disable the ge neration of interrupts caused by parity errors by writing bit 7 of the encellt register (0x38) to 0.
2.0 functional description cx28250 2.5 utopia interface atm physical interface (phy) devices 2-38 mindspeed technologies ? 28250-dsh-002-c 2.5.4 utopia multi-phy operation the cx28250 supports multi-phy operation as described in the utopia level specification (af-phy-0039.000; visit the web site: http://www.atmforum.com). three primary functions are involved in th is operation: polling, selection, and data transfer. these functions are basical ly the same for both the transmit and receive sides of the utopia bus. the following example describes the transmit functions. the atm layer utopia controller polls the connected phy ports by transmitting the port addresses on the utxaddr lines. if a port is ready to transfer data, it asserts utxclav. the controller determines which port is to transfer data and selects that port by transmitting it s address. the contro ller then asserts utxenb* to allow the phy to transfer data on the utxdata lines. utxenb* is deasserted when the transfer is completed. polling can continue during the data transfer process but not during port sel ection. it operates independently of the state of utxenb*. to pause the data transfer process, utxenb* can be deasserted. to continue the transfer, the controller must reselect the port by transmitting its address one clock cycle before asserting utxenb*. th e controller must ensure that the cell transfer from this port has been comp leted, to avoid a start-of-cell error. the cx28250 has a utopia receiver outp ut disable feature which allows the user to set up redundant or back-up p hys with the same utopia address on the same utopia bus. in this setup, both phys? transmitters are enabled, sending out identical data streams. both phys? receivers are enabled, but only one is transferring data to the atm device. the re ceiver output is disabled in the backup phy by writing the utopdis, bit 5, in the utop2 register (0x0b) to a logic 1. this disable places five of the back up phy?s signals; urxdata, urxprty, urxsoc, urxclav, and utxclav; in a hi gh-impedance state, preventing data and control signals from being passed to the atm layer device. the disabled receiver flushes its fifos at the same rate as the enabled one, but all data it has received, except the last four cells, is lost. should the primary phy device encounter an unacceptable error rate, so ftware can quickly enable the backup phy and disable the primary phy, redu cing cell loss in the transition. note: to facilitate multi-phy operation, the cx28250 assigns a different address to each of its ports by default.
cx28250 2.0 functional description atm physical interface (phy) devices 2.5 utopia interface 28250-dsh-002-c mindspeed technologies ? 2-39 2.5.5 handshaking the cx28250 provides both cell-level and octet-level handshaking on its utopia interface (only cell-level is used in level 2). the primary distinction between these two levels is th e amount of data that is sent or received. octet-level sends and receives four octets at a time, while cell-level sends and receives a full cell at a time, depending on fifo size and availability. in octet-level handshaking, utxclav is an active low, fifo full indicator. in cell-level, it is an active high, cell buffer available indicator. these two options are selectable in the handshake bit, bit 4, of the utop1 register (0x0a). txclav (transmit cell available): the cx28250 implementation of txclav is designed to provide a 'look ahead' feature to allow the atm layer to anticipate when the fifos will be full. the utopia la yer polls the port to determine if that port has room for a cell. in response, the po rt asserts (logic 1), the txclav line if it has room and de-asserts (0) the line if it does not have room. the threshold is controlled by bits [1:0] in the utop1 register as listed in table 2-18 . for maximum performance when using a standard atm layer device, mindspeed recommends leaving these set to 00. table 2-18. utop1 register, bits [1:0] bit default name description 1 0 txfill[1] these bits set th e transmit fifo fill leve l threshold for utxclav pin. 00?the txclav line will be asserted if th e utopia fifo can accept at least 1 more complete cell. 01?the txclav line will be asserted onl y if the utopia fifo has room for least 2 more cells. 10?the txclav line will be asserted only if the utopia fifo has room for at least 3 more cells. 11?the txclav line will be asserted only if the utopia fifo can accept at least 3 more cells. 0 0 txfill[0]
2.0 functional description cx28250 2.6 microprocessor interface atm physical interface (phy) devices 2-40 mindspeed technologies ? 28250-dsh-002-c 2.6 microprocessor interface the microprocessor interface transfers contro l and status information in 8-bit data transfers between the external micropro cessor and cx28250 by means of write and/or read access to internal registers. this interface allows the microprocessor to configure the cx28250 by writing various control registers. these control registers can also be read for configur ation confirmation. th is interface also provides the ability to read the device?s current condition via its status registers and counters. summary status is available for rapid interrupt identification. the microprocessor interface has two primary modes of operation: an asynchronous, sram-like interface and a synchronous interface. the msyncmode pin determines which mode is active. for the asynchronous interface, the mi croprocessor interface pins are defined as follows: macssel, mcs*, mrd*, mwr*, mint*, mrdy, maddr, mdata. in this mode, the mrd* and mwr* strobes direct the data transfers. the asynchronous interface has two secondar y operating modes: a high-performance access mode and a low-power access mode. the macssel pin determines which access mode is active. these modes allow for trade-offs between speed and power required for various applications. for the synchronous interface, the microp rocessor interface pins are defined as follows: mclk, mcs*, mw/r*, mas*, mint*, maddr, mdata. in this mode, the timing of these signals is synchroni zed to mclk, which is intended to be directly driven by the external microp rocessor. the synchronous interface is compatible with the bt8230 and bt8233 sar devices, providing no-wait-state operation. 2.6.1 microprocessor clock two pins determine the behavior of the micro interface clock circuits: mclk (pin l3) and msyncmode (pin m1). mclk-macssel: this is a dual mode pin. if the device is configured for synchronous operation this is the clock input for the microprocessor interface. see the timing diagrams in chapter 5.0 . msyncmode selects either the synchronous mode or the asynchronous mode. when tied high the async mode is selected; this is used mainly for mindspeed sars. when tied low, it configures the device for the async mode as used by most general purpose processors. when using the asynchronous mode, this pin selects either the high speed access or low power access. in either case, the microprocessor clock is internally derived from the lpllclk input. when tied high, for high speed access, the internal clock samples the microprocessor in puts at an 80 ns rate. when tied low, for low power, the internal clock samples the inputs at 130 ns.
cx28250 2.0 functional description atm physical interface (phy) devices 2.6 microprocessor interface 28250-dsh-002-c mindspeed technologies ? 2-41 2.6.2 status and control several registers provide status and cont rol information to the microprocessor. status information includes interrupts, counters, and generic functional status. control information includes configuration and real-time control, according to the specific function of each control regi ster. there are two types of status input: live and latched. live status provides the current status of the device. latched status is used for rapidly changing stat es to capture information until it can be read. this device contains general purpose st atus and control functions, such as a master reset, output status, and device part number and revision. the software-controlled master reset, gen regi ster (0x00) bit 0, restarts all device functions and sets the control and status registers to their default values. the outstat register (0x02) provides a mean s for controlling external devices via the outstat pins (1-5 and 126-128). it is enabled by setting the statpinmode (bit 2) of the gen register (0x00). the ver register (0x03) uniquely identifies the device and revision level. 2.6.3 counters the cx28250 counters record events within the device. there are two types of events: error events, such as section bip errors, and tran smission events, such as transmitted atm cells. counters which are comprised of more than one register must be accessed by reading the least significant byte first. th is guarantees that the value contained in each component register accurately reflec ts the composite counter value at the time the least significant byte was read since the counter may be updated while the component regist ers are being read. each counter is large enough to acco mmodate the maximum number of events that may occur within a one- second interval. the counte rs are cleared after being read. therefore, if the coun ters are read every second, the application receives an accurate recording of all event occurrences.
2.0 functional description cx28250 2.6 microprocessor interface atm physical interface (phy) devices 2-42 mindspeed technologies ? 28250-dsh-002-c 2.6.4 one-second latching mindspeed?s implementation of one-second latching ensures th e integrity of the statistics being gathered by the network management software. internal statistics counters can be latched at one-second in tervals, which are synchronized to the onesecin pin. therefore, the data read from the statistic counters represents the same ?one second? of real-time data, independent of network management software timing. the cx28250 implements one-second la tching for both status signals and counter values. when the enstatlat bit (5) in the gen register (0x00) is written to a logic 1, a read from any of the status registers returns the state of the device at the time of the previous on esecin pin assertion. when the encntrlat bit (4) in the gen register (0x00) is written to a logic 1, a read from any of the counters returns the state of the device at the time of the previous onesecin pin assertion. thus the counters are updated once per second. the onesecin pin is intended to be assert ed at one-second intervals. this can be achieved by connecting the onesec in pin to the onesecout pin. the onesecout signal is derived from the 8khzin pin. this signal is asserted for one 8khzin clock period, every 8,000 8khzin periods. if 8khzin is being driven by an 8 khz clock, the onesecout signal is asserted every second. note: when latching is disabled and a counter is wider than one byte, the lsb should be read first which retains the values of the other bytes for a subsequent read.
cx28250 2.0 functional description atm physical interface (phy) devices 2.6 microprocessor interface 28250-dsh-002-c mindspeed technologies ? 2-43 2.6.5 interrupts the cx28250?s interrupt indications can be classified as either single-event or dual-event. a single-event interrupt is triggered by a status assertion. a dual-event interrupt is triggered by either a status assertion or deassertion. both types of interrupts are further described in the following examples. single-event interrupt: when a parity error occurs on the utopia transmit data bus, an interrupt is generated on pa rerrint, bit 7 in the txcellint register (0x40). this bit is cleared when read. dual-event interrupt: when locd occurs, locdint, bit 7 of the corresponding rxcellint register (0x41) is set to 1. this bit is cleared when the register is read. once cell delineation is recovered, bit 7 is set to 1 again, generating another interrupt. all interrupt bits have a corresponding enable bit. this allows software to disable or mask interrupts as required. 2.6.5.1 interrupt routing the cx28250 uses two levels of interrupt indications. the first level consists of section, line, path, aps, receive, and tr ansmit interrupt indications. the second level summarizes first-level interrupts and indicates one- second interrupts. the first level interrupt indications ar e located in registers secint, linint, pthint, apsint, txcellint, and rxcell int. each interrupt bit in these registers can be disabled in the corresponding ensec, enlin, enpth, enaps, encellt, or encellr register s, respectively. the result is then ored into the appropriate bit in the sumint register. the second level consists of summary interrupt indications, located in the sumint register. it also includes the on esecint indications. e ach interrupt bit in these registers can be disabled in th e corresponding ensumint register. the result is ored to the mint* pin. the mint* pin can be enabled or disabled by setting the enintpin (bit 6) in the gen register (0x00).
2.0 functional description cx28250 2.6 microprocessor interface atm physical interface (phy) devices 2-44 mindspeed technologies ? 28250-dsh-002-c figure 2-13 illustrates the registers involv ed in the interrupt generation process. figure 2-13. interrupt indication diagram 7 6 5 4 3 2 1 0 or 7 6 5 4 3 2 1 0 or 7 6 5 4 3 2 1 0 or 7 6 5 4 3 2 1 0 or 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 or 7 6 5 4 3 2 1 0 or 7 6 5 4 3 2 1 0 or reserved sectraceint sigdetint lolint losint oofint lofint b1errint outputs enabled by ensec (0x35) secint (0x3d) s1int zint lopint k1k2int ais-lint rdi-lint b2errint rei-lint outputs enabled by enlin (0x36) linint (0x3e) reserved pthtraceint ais-pint rdi-pint b3errint rei-pint plm-pint uneq-pint outputs enabled by enpth (0x37) pthint (0x3f) sigdegradeint sigfailint reserved reserved reserved psbfint reserved reserved outputs enabled by enaps (0x3a) apsint (0x42) nonzergfcint nonmatchint locdint hecdetint heccorrint reserved cellrcvdint idlercvdint outputs enabled by encellr (0x39) rxcellint (0x41) reserved reserved parerrint socerrint txovflint rxovflint cellsentint reserved outputs enabled by encellt (0x38) txcellint (0x040) txcellint rxcellint secint linint pthint onesecint reserved apsint outputs enabled by ensumint (0x34) sumint (0x3c) gen (0x00) enintpin mint* 500035_017
cx28250 2.0 functional description atm physical interface (phy) devices 2.6 microprocessor interface 28250-dsh-002-c mindspeed technologies ? 2-45 figure 2-14 illustrates the alarms which can cause the line fail or the path fail output to be asserted. figure 2-14. line and path fail indication diagram 7 6 5 4 3 2 1 0 or 7 6 5 4 3 2 1 0 or lfout pfout locd lop-p los lol oof lof ais-l ais-p outputs enabled by lfout (0x6e) line fail indication outputs enabled by pfout (0x6f) path fail indication 500035_017 locd lop-p los lol oof lof ais-l ais-p
2.0 functional description cx28250 2.6 microprocessor interface atm physical interface (phy) devices 2-46 mindspeed technologies ? 28250-dsh-002-c 2.6.5.2 interrupt suppression during error conditions a single, high level error condition can generate numerous false interrupts. for example, an lof error can generate almo st all atm related errors, hec errors, locd, etc. to simplify software interr upt routines, the cx28250 automatically suppresses lower level interrupts when the errors shown in table 2-19 occur. table 2-19. interrupt suppression during error conditions (1 of 2) interrupts suppressed during: los lof oof ais-l ais-p lop-p rdi-p rdi-l uneq-p locd (2) interrupts suppressed b1err 3 3 (2) 3 sectrace 3 3 (2) 3 (3) k1k2 33 3 3 (3) ais-l 33 rei-l 33 3 (2) 33 rdi-l 33 3 b2err 33 3 (2) 3 s1 33 3 z2 33 3 psbf 33 3 sigfail-l 33 3 sigdeg-l 33 3 ais-p 33 3 3 (3) lop-p 33 3 3 (2) rdi-p 33 3 3 3 b3err 33 3 (2) 33 3 3 sigfail-p 33 3 33 3 sigdeg-p 33 3 33 3 rei-p 33 3 (2) 33 3 3 (1) 3 plm-p 33 3 3 3 uneq-p 33 3 3 3 pthtrace 33 3 3 3 counters suppressed b1 bip 3 3 (2) 3 b2 bip 33 3 line rei 33 3 3 b3 bip 33 3 3 3 3 path rei 33 3 3 3 3 (1) 3
cx28250 2.0 functional description atm physical interface (phy) devices 2.6 microprocessor interface 28250-dsh-002-c mindspeed technologies ? 2-47 2.6.5.3 interrupt servicing when an interrupt occurs on the mint* pin, it could have been generated by any of 35 events. the cx28250?s interrup t indication process ensures that a maximum of two register reads are nece ssary to determine the source of an interrupt. the interrupt is traced back to its source using the following steps: 1. read the sumint register to see which bit(s) shows an interrupt. ? bit 0, txcellint, re flects activity in the txcellint register. ? bit 1, rxcellint, reflects activity in the rxcellint register. ? bit 2, apsint, reflects activity in the apsint register. ?bit 3 is reserved. ? bit 4, onesecint, indicates a one-second interrupt. ? bit 5, pthint, reflects activity in the pthint register. ? bit 6, linint, reflects activity in the linint register. ? bit 7, secint, reflects activity in the secint register. 2. if necessary, read the appropriat e txcellint, rxcellint, apsint, pthint, linint, or secint register. all level 1 bits are cleared when the regi ster is read. once the register is read, all bits in that register are reset to their default values. therefore, interrupt service routines must be designed to ha ndle multiple interrupts in the same registers. in level 2, onesecint is cleared when the register is read. however, the summary bits are cleared only when the corresponding level 1 register is read and cleared. cell delineation (valid for the -26 version only) locd 333 3 3 3 3 hecdet 3 heccorr 3 cellrcvd 3 idlercvd 3 nonmatch 3 nonzergfc 3 note(s): (1) suppressed when rdi-p equals 110 or 101. (2) this is not suppressed in the cx28250-23 version. (3) this is not suppressed in the CX28250-26 version. table 2-19. interrupt suppression during error conditions (2 of 2) interrupts suppressed during: los lof oof ais-l ais-p lop-p rdi-p rdi-l uneq-p locd (2)
2.0 functional description cx28250 2.7 loopback modes atm physical interface (phy) devices 2-48 mindspeed technologies ? 28250-dsh-002-c 2.7 loopback modes loopbacks are diagnostic tools that veri fy the data path. the cx28250 has three loopback modes: line lo opback and utopia loopba ck, which check the line between a remote device and the phy, and source loopback, which checks that the host (the atm layer) is communicating with the phy. line loopback is illustrated in figure 2-15 , utopia loopback is illustrated in figure 2-16 , and source loopback is illustrated in figure 2-17 . 2.7.1 line loopback line loopback is enabled or disabled by bit 1 of the clkrec register (0x01). when line loopback is enabled, all inco ming data on the receive line interface is retransmitted out the transmit line inte rface. the received data is also passed through the phy?s normal path to be output on the utopia interface. in this mode, the incoming signal is processed by the receive block and the data is output on the utopia bus. however, the receive pecl inputs are directly connected to the transmit pecl output s and the internal transmit block is disabled. thus, there is no processing performed in the transmit direction. the cx28250 simply retransmits whatever signal is received. figure 2-15. near-end line loopback diagram mrdy atm wire interface utopia level 2 interface host interface transmit utopia level 2 4-cell fifo pecl logic level utxclk urxclk sonet line framer microprocessor interface cell counters performance monitoring interrupt control rx cell validation rx vpi/vci screening tx cell generation tx overhead insert transmit line interface loopback control sts-3c/stm-1 receive framer receive line interface and clock recovery receive cell alignment clock and control sts-3c/stm-1 transmit framer rx overhead extract atm cell framer host interface receive utopia level 2 4-cell fifo mint* maddr[6:0] mdata[7:0] control lines ltxdata+/- ltxclki+/- ltxclko+/- lrxdata+/- lrxclk+/- sigdet utxclav utxenb* utxsoc utxaddr[4:0] urxclav urxenb* urxsoc urxprty urxaddr[4:0] tck onesecin 8khzin onesecout rxframeref jtag controller trst* tms tdi tdo status statout[0:7] pllclk (19.44 mhz) 500035_018 txframeref utxdata[15:0] txprty urxdata[15:0] txdl inspthais inslnais pfout lfout tx pecl rx pecl
cx28250 2.0 functional description atm physical interface (phy) devices 2.7 loopback modes 28250-dsh-002-c mindspeed technologies ? 2-49 2.7.2 utopia loopback utopia loopback is enabled or disabled by bit 0 of the clkrec register (0x01). when utopia loopback is enabled, all received cells in the utopia fifo are passed to the transmit fifo for transmission on the transmit line interface. the receive utopia bus is placed in a high-impedance state. figure 2-16. utopia loopback diagram mrdy atm wire interface utopia level 2 interface host interface transmit utopia level 2 4-cell fifo pecl logic level utxclk urxclk sonet line framer microprocessor interface cell counters performance monitoring interrupt control rx cell validation rx vpi/vci screening tx cell generation tx overhead insert transmit line interface loopback control sts-3c/stm-1 receive framer receive line interface and clock recovery receive cell alignment clock and control sts-3c/stm-1 transmit framer rx overhead extract atm cell framer host interface receive utopia level 2 4-cell fifo mint* maddr[6:0] mdata[7:0] control lines ltxdata+/- ltxclki+/- ltxclko+/- lrxdata+/- lrxclk+/- sigdet utxclav utxenb* utxsoc utxaddr[4:0] urxclav urxenb* urxsoc urxprty urxaddr[4:0] tck onesecin 8khzin onesecout rxframeref jtag controller trst* tms tdi tdo status statout[0:7] pllclk (19.44 mhz) 500035_019 txframeref utxdata[15:0] txprty urxdata[15:0] txdl inspthais inslnais pfout lfout
2.0 functional description cx28250 2.7 loopback modes atm physical interface (phy) devices 2-50 mindspeed technologies ? 28250-dsh-002-c 2.7.3 source loopback source loopback is enabled and disabled by bit 2 the clkrec register (0x01). when source loopback is enabled, all da ta transmitted by th e cx28250 is also looped back through the r eceive line interface. data from the pmd is ignored. figure 2-17. source loopback diagram mrdy atm wire interface utopia level 2 interface host interface transmit utopia level 2 4-cell fifo pecl logic level utxclk urxclk sonet line framer microprocessor interface cell counters performance monitoring interrupt control rx cell validation rx vpi/vci screening tx cell generation tx overhead insert transmit line interface loopback control sts-3c/stm-1 receive framer receive line interface and clock recovery receive cell alignment clock and control sts-3c/stm-1 transmit framer rx overhead extract atm cell framer host interface receive utopia level 2 4-cell fifo mint* maddr[6:0] mdata[7:0] control lines ltxdata+/- ltxclki+/- ltxclko+/- lrxdata+/- lrxclk+/- sigdet utxclav utxenb* utxsoc utxaddr[4:0] urxclav urxenb* urxsoc urxprty urxaddr[4:0] tck onesecin 8khzin onesecout rxframeref jtag controller trst* tms tdi tdo status statout[0:7] pllclk (19.44 mhz) 500035_020 txframeref utxdata[15:0] txprty urxdata[15:0] txdl inspthais inslnais pfout lfout
28250-dsh-002-c mindspeed technologies ? 3-1 3 3.0 applications this chapter provides details of the cx28250 reference design. the cx28250-cx28236 evaluation module (evm) is an atm over sonet network interface card reference de sign. the main components of the design are the cx28250 (atm-phy) and the cx28236 (atm-sar) from mindspeed. figure 3-1 shows the interface between the cx28250 and the cx28236. the cx28236 has a pci interface that allows the host to control the device. control for the cx28250 is provided through the phy interface of the cx28236 and does not require glue logic. figure 3-5 shows the evm block diagram. the board layout, schematics, and parts list are available for mindspeed customers. a complete built and tested cx28250-cx28236 evaluation module (evm) is also available. sample source code for the cx28250 and the cx28236 can be obtained from mindspeed. customers can quickly become familia r with the cx28250 by using the cx28250-cx28236 evm. the board plugs into a standard pci interface slot. the board utilizes the vxworks embedded operating system. other embedded operating systems can be used. details on porting the mindspeed drivers are documented in the cx28297 atm phy device driver software programming guide . sonet automatic protection switchin g (aps) can also be evaluated and tested by utilizing two cx28250-cx28236 evms in one pci chassis. mindspeed has the aps software stac k as well as software for the cx28236 sar and the cx28250 to allow customers to demonstrate this configuration easily. the resources provided by mindspeed allow customers to achieve a fast time to market. customers can design and build systems quickly that require only minor customization, verification, and compliance testing prior to oem production. for more information on the cx28250-cx28236 evm please contact your local sales person. 3.1 system application figure 3-1 illustrates how the cx28250 (atm-phy) and the cx28236 (atm-sar) from mindspeed interconnect.
3.0 applications cx28250 3.1 system application atm physical interface (phy) devices 3-2 mindspeed technologies ? 28250-dsh-002-c figure 3-1. cx28250 and cx28236 sar application diagram note(s): (1) can be driven by external circuitry to extend cycles. (2) can be used by external circuitry. (3) a pulldown resistor is required on utxc lav, urxclav, urxsoc, and urxprty to ensure correct startup of the cx28236 utopia interface. cx28250 cx28236 sram paddr[0] paddr[1] mdata[7:0] ldata[31:0] pbsel[1,0] mcs* mw/r*, mrd* mas*, mwr* prdy* pbe[3:0]* pblast* mclk, macssel pwait* pwnr prst* pdaen* pfail* pas* sysclk a[18:0] d[31:0] laddr[18:0] maddr[6:0] sramcs* sramcs* sramcs* mint* we[3:0]* mwr[3:0]* oe* moe* sramcs* mcs[3]* mcs[2]* mcs[1]* mcs[0]* reset* pcs* gnd n/c (2) gnd gnd gnd gnd open pullup procmode mwr* for x16 sram rammode gnd for x8 or x4 pullup for x16 pullup pullup (1) msyncmode fiber pmd device pci bus utxdata[15:0] utxclav utxenb* utxsoc utxprty utxaddr[4:0] utxclk urxclk urxdata[15:0] urxclav urxenb* urxsoc urxprty urxaddr[4:0] txdata[15:0] txflag* txen txmark txpar clkd3 rxdata[15:0] rxflag* rxen* rxmark rxpar vcc (3) (3) (3) (3) 500035_021 txaddr[4:0] rxaddr[4:0]
cx28250 3.0 applications atm physical interface (phy) devices 3.2 board layout 28250-dsh-002-c mindspeed technologies ? 3-3 3.2 board layout mindspeed has completed jitter testin g of the cx28250-23 oc-3/stm1 phy device and verified that it meets all jitter requirem ents of bellcore gr-253-core while passing bi-directi onal traffic at the full line rate. a partial schematic of the board used by mindspeed is shown in figure 3-2 and the layout is shown in figure 3-3 (the full schematic is available online; contact your field engineer for details). complete board layout files, including gerber plots, are also available online. the external filter networks and analog power warrant special attention. 3.2.1 analog power during testing it was found that under normal conditions the device meets all jitter specifications with significant ma rgin. however, increasing the noise level on the 3.3 volt supply will eventually impa ct the intrinsic jitter, especially if the noise is low frequency, (100 khz range), non-periodic pulses. the designer has the following options: ensure that their board is electrically quiet. in general, 50-75 mv of white noise will not affect jitter generation. install passive filters on the analog power pins. unfortunately, due to the low frequencies involved, the inductor s required need be in the 2-3 mh range. these are quite large and expensive. provide a separate 3.3 volt regulator for the analog supply pins. this is the approach taken by mindspeed. these devices are relatively inexpensive and take very little board space. the current requirement is only 150 ma. recommended layout : use the layout of the separate regulator as shown in figure 3-4 . lay the board out such that the regulator can be bypassed by a 0 ? resistor. the regulator can then be omitted, (?no stuff ?), in production if not needed.
3.0 applications cx28250 3.2 board layout atm physical interface (phy) devices 3-4 mindspeed technologies ? 28250-dsh-002-c figure 3-2. schematic detail of analog components 2.2 f c27 1 f c48 c17 470 pf l10 lrxpfn p11 lrxpfp l6 ltxpfn m6 ltxpfp n9 m9 m7 m5 l5 cx28250-23 m6 l5, m5, m7, m9, n9 digital power pins d10, d13, j2, j3, k11 c7, c10, d1, d3, d8 cx28250 d7, g11, h12, m13, n14 no connect pins this point should be routed to the analog ground pins: n6, n7, and p6 of the cx28250. ground note c42 270 pf c28 0.015 f r49 604 68.1 r48 ground pins a8, b6, c11, d4, d12 e1, e2, g1, g4, h3 j13, l1, l8, m11, n6 n7, n10, p6, p9 analog power pins h+5v c54 100 pf c89 2.2 f c80 470 pf analog+3v 4 byp 3 en gnd 1 vin 5 vout sot23-5 vreg 4 5 2 3 1 vr2 500035_052 vdda vdda vdda vdda vdda vssa vssa vssa n6 n7 p6 keep these components as close together as possible and locate them next to the cx28250. keep these components as close together as possible and locate them next to the cx28250. note: for clarity, not all pins are shown. c51 and r36 are not populated. used for device verification, not needed in production. all capacitors are 10% ceramic and all resistors are 1%. these traces should be equal in length on your board. r36 c51
cx28250 3.0 applications atm physical interface (phy) devices 3.2 board layout 28250-dsh-002-c mindspeed technologies ? 3-5 figure 3-3. tx and rx filter layout 500035_051 c42 c51 c28 r49 c17 r48 r36 ab cde f 2 3 1 (1) (3) (2) c27 c48 bottom view of the cx28250 note: this is an artist's rendering of analog power connections. c51 and r36 are not populated. used for device verification, not needed in production. (1) guard ring for tx filter. (2) common analog ground point. see "ground note" in figure 6. (3) guard ring for rx filter.
3.0 applications cx28250 3.2 board layout atm physical interface (phy) devices 3-6 mindspeed technologies ? 28250-dsh-002-c figure 3-4. analog power supply connections (top view) 500035_053 t o bypass capacitor t o analog v oltage regulator a p 1 14 note: this is an artist's rendering of analog power connections.
cx28250 3.0 applications atm physical interface (phy) devices 3.3 the cx28250/cx28236 network interface card reference design 28250-dsh-002-c mindspeed technologies ? 3-7 3.3 the cx28250/cx28 236 network interface card reference design figure 3-5 shows the block diagram of the cx28236 sar connected to the cx28250. schematics illustrating this co nnection in more detail are presented on the following pages. figure 3-5. cx28250/cx28236 evm block diagram 500035_038 laddr[18:0] laddr[18:0] stat7=los stat6=oof stat5=lop stat4=ais-l stat3=rdi-l stat2=ais-p stat1=rdi-p pecl local bus had[31:0] ldata[7:0] ldata[31:0] rxdat+&- txd[15:0] xmit rcv serial eeprom status leds memory bank cx28250 cx28236 sar phy rxd[15:0] txdat+&- ldata[31:0] laddr[6:0] stat[7:0] pci bus pmd (1) stat0=locd 8 control bits for utopia bus control 2mbyte note(s): (1). fiber optic oc-3 transceiver amp part #: 269146-3
3.0 applications cx28250 3.3 the cx28250/cx28236 network interface card reference design atm physical interface (phy) devices 3-8 mindspeed technologies ? 28250-dsh-002-c 500035_039 l2 l1 utopia mode 12 j1 12 j43 cc r23 130 y1 and j2 are +5v parts utopia testing, or when jumper installed at h+5v for locate near the transceiver cc r4 130 1 10 11 12 13 14 15 16 2 3 4 5 6 7 89 51 ra2 1 10 11 12 13 14 15 16 2 3 4 5 6 7 89 51 ra13 8khzin n3 addr[0] g2 addr[1] f4 addr[2] f3 addr[3] f1 addr[4] f2 addr[5] e4 addr[6] e3 dat[0] k2 dat[1] k3 dat[2] k1 dat[3] j4 dat[4] j1 dat[5] h2 dat[6] h1 dat[7] g3 inslnais a13 inspthais f11 lfout b13 l10 lrxpfn p11 lrxpfp l6 ltxpfn m6 ltxpfp mclk l3 mrdy h4 n/c1 l7 n/c2 l11 onesecin m2 onesecout n1 pfout f12 pllclk p5 rxaddr[0] d6 rxaddr[1] a5 rxaddr[2] c5 rxaddr[3] b5 rxaddr[4] d5 rxclav c12 l12 rxclk+ k12 rxclk- rxdat+ m10 rxdat- p10 rxdata[0] b12 rxdata[10] d9 rxdata[11] b8 rxdata[12] c8 rxdata[13] a7 rxdata[14] b7 rxdata[15] a6 rxdata[1] a12 rxdata[2] b11 rxdata[3] a11 rxdata[4] d11 rxdata[5] b10 rxdata[6] a10 rxdata[7] b9 rxdata[8] a9 rxdata[9] c9 rxframeref p2 rxprty c6 rxsoc b14 sigdet l9 statout[0] b2 statout[1] a2 statout[2] b3 statout[3] c3 statout[4] a3 statout[5] b4 statout[6] c4 statout[7] a4 syncmode m1 tck n4 tdi l4 tdo n5 tms p4 txaddr[0] p12 txaddr[1] m12 txaddr[2] n12 txaddr[3] p13 txaddr[4] n13 txclav e12 k4 txclki+ l2 txclki- txclko+ m8 txclko- p7 txdat+ n8 txdat- p8 txdata[0] m14 txdata[10] h11 txdata[11] g12 txdata[12] g14 txdata[13] g13 txdata[14] f14 txdata[15] f13 txdata[1] l13 txdata[2] l14 txdata[3] k13 txdata[4] k14 txdata[5] j14 txdata[6] j12 txdata[7] j11 txdata[8] h13 txdata[9] h14 txframeref n2 txprty e14 txserdl p3 txsoc e13 utoprxclk c14 utoptxclk d14 n11 vgg w/r c2 as d2 cs c1 int b1 reset m3 rxenb c13 trst m4 txenb e11 micro jtag status utopia xmit utopia rcv clock & control pmd pll cx28250-25 utopmode n14 ubuswidth h12 n3 g2 f4 f3 f1 f2 e4 e3 k2 k3 k1 j4 j1 h2 h1 g3 a13 f11 b13 l10 p11 l6 m6 l3 h4 l7 l11 m2 n1 f12 p5 d6 a5 c5 b5 d5 c12 l12 k12 m10 p10 b12 d9 b8 c8 a7 b7 a6 a12 b11 a11 d11 b10 a10 b9 a9 c9 p2 c6 b14 l9 b2 a2 b3 c3 a3 b4 c4 a4 m1 n4 l4 n5 p4 p12 m12 n12 p13 n13 e12 k4 l2 m8 p7 n8 p8 m14 h11 g12 g14 g13 f14 f13 l13 l14 k13 k14 j14 j12 j11 h13 h14 n2 e14 p3 e13 c14 d14 n11 c2 d2 c1 b1 m3 c13 m4 e11 n14 h12 see artwork in cx28250 pf lf cx28250 n6, n7, & p6 of cx28250 a common gnd via should be routed to rxclk+ rxclk- txclki+ txclki- no bottom bracket cc r43 47.5 cc 82 r44 1 2 j38 ldata[7:0] ldata7 ldata6 ldata0 ldata5 ldata1 ldata2 ldata3 ldata4 +3v lais pcitdo rdy pais lais syncmode tck tdo-tdi tms trst 12 j84 2 1 j85 laddr0 laddr[6:0] laddr6 laddr5 laddr4 laddr3 laddr2 laddr1 2 1 j82 byteclk 2 1 j33 12 j32 12 j31 cc r47 2.2k cc r52 49.9 cc r48 68.1 pcs mcs3 2 1 j47 +3v bga a b c d e f g h +3v +3v +3v +3v 1 g8 +3v cc c81 .01 cc 82 r25 cc 130 r24 cd b a d 4 c b a 4 3 2 1 1 2 3 scale: size b code ident no. drawing no. sheet of rev none 11-13-2001_12:44 bt00-d700-011.003p 3 6 bt00-x700 8236/8250 cc .01 c82 h+5v -no -no for shorts both cc .01 c55 hp-txpar hp-txd14 hp-txd[15:0] hp-txd15 hp-txd13 hp-txd12 hp-txd11 hp-txd10 hp-txd9 hp-txd8 hp-txd7 hp-txd6 hp-txd5 hp-txd4 hp-txd3 hp-txd2 hp-txd1 hp-txd0 hp-rxaddr[4:0] hp-rxaddr4 hp-rxaddr3 hp-rxaddr2 hp-rxaddr1 hp-rxaddr0 hp-txsoc hp-rxenb cc .01 c86 +3v +3v cc + 10 c85 2 1 j50 hp-txenb hp-txaddr[4:0] hp-txaddr0 hp-txaddr1 hp-txaddr2 hp-txaddr3 hp-txaddr4 2 1 1uh l2 2 1 1uh l1 solder remove utopia testing vcc 14 7 vss 8 out 19.44mhz y1 12 j48 hp-utoptxclk 12 j49 hp-utoprxclk 1 g9 1 g1 gnd 1234567891011121314 j k l m n p cc 2.2k r50 cc r46 2.2k 2 1 j42 12 j41 -nc -nc cc r26 82 cc 604 r49 cc .015uf c28 cc 270pf c42 l3 l4 cc 47.5 r42 bead 0805 bead 0805 top bracket cc 10k r66 cc 10k r67 sysclk pas pwnr prst phy_int 21 j39 stat0 stat1 stat[7:0] stat7 stat6 stat5 stat4 stat3 stat2 nc no no nc gnd note these two gnd points near analog gnd pins j119 2 1 j83 cc 470pf c17 cc c27 2.2uf vcc2 1 2 3 j102 3 2 1 j101 +3v datasheet. cc 100 r8 cc 130 r6 locate near cx28250 1 g10 1 j107 pais 1 2 j86 21 j87 12 j28 1 j109 locate near the cx28250 rxdat- +3v no vgg1 cc c48 1uf see gnd note cc 130 r45 cc r1 100 locate near transceiver vcc1 txdata- txdata+ +3v syncmode 2 1 j30 cc 49.9 r69 cc 49.9 r71 hp-rxsoc hp-rxclav hp-rxpar cc r72 49.9 hp-rxd[15:0] hp-rxd8 hp-rxd9 hp-rxd10 hp-rxd11 hp-rxd12 hp-rxd13 hp-rxd14 hp-rxd15 hp-rxd7 hp-rxd6 hp-rxd5 hp-rxd0 hp-rxd1 hp-rxd2 hp-rxd3 hp-rxd4 hp-txclav 2 1 j29 12 j51 2 1 j34 rxdat+ cc r5 130 cc 130 r7 urxclk utoprxclk utxclk 2-3 nc 1-2 nc 2-3 no 1-2 no 1-2 nc 2-3 no 1-2 no 2-3 nc utopia level 1 default settings: bit 8 bit 16 utoptxclk utopia bus width 8 nc 10 td- vee1 7 td+ 9 6 vcc1 2 vcc2 1 vee2 3 sd 5 rd+ 4 rd- tx rx tranceiver mt-rj sff 8 10 7 9 6 2 1 3 5 4 j2 do not stuff do not stuff f
cx28250 3.0 applications atm physical interface (phy) devices 3.3 the cx28250/cx28236 network interface card reference design 28250-dsh-002-c mindspeed technologies ? 3-9 500035_045 +3v clka1 2 clka2 3 clka3 14 clka4 15 clkb1 6 clkb2 7 clkb3 10 clkb4 11 clkin 1 fbin 16 512 s1 9 s2 8 413 gnd gnd vdd vdd ics9112m-18 soic16 13 4 89 12 5 16 1 11 10 7 6 15 14 3 2 u7 txaddr1 12 j24 1 10 11 12 13 14 15 16 17 18 19 2 20 21 22 23 24 25 26 27 28 29 3 30 31 32 33 34 35 36 37 38 39 4 40 41 42 43 44 45 46 47 48 49 5 50 51 52 53 54 55 56 57 58 59 6 60 61 62 63 64 65 66 67 68 69 7 70 71 72 73 74 75 76 77 78 79 8 80 9 polarity peg j81 2 1 j27 12 j26 2 1 j25 hp-txaddr3 12 j35 rxaddr4 rxaddr3 rxaddr2 rxaddr1 rxaddr0 rxclav 2 1 j73 12 j74 2 1 j75 12 j72 2 1 j71 hp-rxaddr1 12 j70 2 1 j76 rxenb rxsoc rxpar rxd15 rxd14 rxd13 rxd12 rxd11 rxd10 rxd9 rxd8 hp-rxd8 hp-rxd9 12 j67 2 1 j66 12 j65 2 1 j64 12 j63 2 1 j62 12 j61 2 1 j60 12 j68 txd15 txd14 txd13 txd12 txd11 txd10 txd9 txd8 ad00 a58 b58ad01 a57 ad02 ad03 b56 a55 ad04 b55ad05 a54 ad06 b53ad07 b52ad08 a49 ad09 b48ad10 a47 ad11 ad12 b47 ad13 a46 ad14 b45 ad15 a44 a32 ad16 ad17 b32 a31 ad18 ad19 b30 a29 ad20 ad21 b29 a28 ad22 ad23 b27 a25 ad24 ad25 b24 a23 ad26 ad27 b23 ad28 a22 ad29 b21 ad30 a20 ad31 b20 clk b16 idsela26 par a43 rsvd1 b10 rsvd2 b14 a9 rsvd3 a11 rsvd4 rsvd5a14 rsvd6a19 sdone a40 b2tck a4 tdi tdo b4 a3 tms b60 ack64 a52 c_be0 c_be1 b44 c_be2 b33 c_be3 b26 b37 devsel framea34 gnt a17 a6 inta intb b7 intc a7 intd b8 irdy b35 lock b39 b40 perr prsnt1 b9 prsnt2 b11 req b18 req64 a60 rst a15 sbo a41 b42 serr stop a38 trdy a36 trst a1 h+5v h+5v h+5v h+5v h+5v h+5v h+5v h+5v h+5v h+5v h+5v h+5v h+5v gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd a58 b58 a57 b56 a55 b55 a54 b53 b52 a49 b48 a47 b47 a46 b45 a44 a32 b32 a31 b30 a29 b29 a28 b27 a25 b24 a23 b23 a22 b21 a20 b20 b16 a26 a43 b10 b14 a9 a11 a14 a19 a40 b2 a4 b4 a3 b60 a52 b44 b33 b26 b37 a34 a17 a6 b7 a7 b8 b35 b39 b40 b9 b11 b18 a60 a15 a41 b42 a38 a36 a1 j40 cc r22 150 cc r21 150 smt 0805 d9 smt 0805 d8 smt 0805 d2 smt 0805 d3 smt 0805 d4 smt 0805 d7 txclav hint had8 had7 had9 had6 had4 had0 had2 had11 had13 had15 had16 had18 had20 had22 had24 had26 had28 had30 hidsel hpar hstop htrdy hframe hgnt hrst pcitdi tms trst hserr hperr hdevsel hirdy hc/be0 hc/be1 hc/be2 hc/be3 had1 had3 had5 had10 had12 had14 had17 had19 had21 had23 had25 had27 had29 had31 hreq hclk gnd gnd pcitdo tck stat7 stat5 stat3 stat2 stat6 cc 150 r20 cc r19 150 cc 150 r18 cc r17 150 stat4 stat1 cc 150 r16 cc r15 150 cc 150 r14 cc 150 r13 12 j58 txd3 hp-txd9 hp-txd10 hp-txd11 hp-txd12 hp-txd13 hp-txd14 hp-txd15 2 1 j19 12 j18 2 1 j17 12 j16 2 1 j15 12 j14 2 1 j13 hp-txd8 2 1 j12 pci connector los oof lop ais-l rdi-l ais-p rdi-p hp-txclav hp-txenb hp-txsoc txpar hp-txpar 2 1 j11 hp-txd7 12 j10 hp-txd6 2 1 j9 txd5 hp-txd5 txd4 hp-txd4 12 j8 2 1 j7 hp-txd3 12 j6 txd2 hp-txd2 2 1 j5 txd1 hp-txd1 hp-txd0 hp-rxpar 2 1 j69 hp-rxsoc hp-rxenb hp-rxclav hp-rxd0 2 1 j53 rxd1 hp-rxd1 12 j54 rxd2 hp-rxd2 2 1 j55 rxd3 hp-rxd3 12 j56 rxd4 hp-rxd4 2 1 j57 rxd5 hp-rxd5 hp-rxd6 rxd6 hp-rxd7 12 j20 2 1 j21 12 j22 txd0 txd7 txsoc 12 j4 txd6 txenb 12 j52 2 1 j59 key rxd7 rxd0 cd b a d 4 c b a 4 3 2 1 1 2 3 scale: size b code ident no. drawing no. sheet of rev none 11-13-2001_12:44 bt00-x700 2 6 bt00-d700-011.002p 8236/8250 smt 0805 d5 smt 0805 d6 smt 0805 d10 smt 0805 d11 d1 red locd lf lf pf pwr pf +3v green cc 150 r51 stat0 tx eliminated on production version of this board all components inside dashed line will be rx hp-rxd10 hp-rxd11 hp-rxd12 hp-rxd13 hp-rxd14 hp-rxd15 hp-utoprxclk hp-utoptxclk hp-rxaddr0 hp-rxaddr4 hp-rxaddr3 hp-rxaddr2 hp-txaddr0 hp-txaddr1 hp-txaddr2 hp-txaddr4 txaddr0 2 1 j23 txaddr2 txaddr3 txaddr4 1 10 11 12 13 14 15 16 17 18 19 2 20 21 22 23 24 25 26 27 28 29 3 30 31 32 33 34 35 36 37 38 39 4 40 41 42 43 44 45 46 47 48 49 5 50 51 52 53 54 55 56 57 58 59 6 60 61 62 63 64 65 66 67 68 69 7 70 71 72 73 74 75 76 77 78 79 8 80 9 polarity peg j80 +3v cc r41 10k cc r11 33 clkd3 cc r9 33 cc r10 33 cc r12 33 utoptxclk utoprxclk zero delay buffer cc .01 c8 cc .01 c2 sarutoprxclk sarutoptxclk f
3.0 applications cx28250 3.3 the cx28250/cx28236 network interface card reference design atm physical interface (phy) devices 3-10 mindspeed technologies ? 28250-dsh-002-c 500035_048 sr_laddr[18:0] sr_laddr0 sr_laddr1 sr_laddr2 sr_laddr3 sr_laddr4 sr_laddr5 sr_laddr6 sr_laddr7 sr_laddr8 sr_laddr9 sr_laddr10 sr_laddr11 sr_laddr12 sr_laddr13 sr_laddr14 sr_laddr15 sr_laddr16 sr_laddr17 sr_laddr18 laddr0 laddr1 laddr2 laddr3 laddr4 laddr5 laddr6 laddr7 laddr8 laddr9 laddr10 laddr11 laddr12 laddr13 laddr14 laddr15 laddr16 laddr17 laddr18 laddr[18:0] 1 2 3 45 6 7 8 ra3 51 series termination ldata0 ldata1 ldata2 ldata3 ldata4 ldata5 ldata6 ldata7 ldata8 ldata9 ldata10 ldata11 ldata12 ldata13 ldata14 ldata15 ldata16 ldata17 ldata18 ldata19 ldata20 ldata21 ldata22 ldata23 ldata24 ldata25 ldata26 ldata27 ldata28 ldata29 ldata30 ldata31 ldata[31:0] sr_ldata0 sr_ldata1 sr_ldata2 sr_ldata3 sr_ldata4 sr_ldata5 sr_ldata6 sr_ldata7 sr_ldata8 sr_ldata9 sr_ldata10 sr_ldata11 sr_ldata12 sr_ldata13 sr_ldata14 sr_ldata15 sr_ldata16 sr_ldata17 sr_ldata18 sr_ldata19 sr_ldata20 sr_ldata21 sr_ldata22 sr_ldata23 sr_ldata24 sr_ldata25 sr_ldata26 sr_ldata27 sr_ldata28 sr_ldata29 sr_ldata30 sr_ldata31 sr_ldata[31:0] 1 10 11 12 13 14 15 16 2 3 4 5 6 7 89 ra7 51 1 10 11 12 13 14 15 16 2 3 4 5 6 7 89 51 ra5 1 10 11 12 13 14 15 16 2 3 4 5 6 7 89 51 ra4 1 g6 1 g2 a0 1 a1 2 a10 20 a11 21 a12 22 a13 23 a14 24 a15 32 a16 33 34 a17 35 a18 3 a2 a3 4 5 a4 14 a5 15 a6 a7 16 a8 17 a9 18 io1 7 io2 8 io3 11 io4 12 io5 25 io6 26 29 io7 io8 30 19 nc1 36 nc2 9 vcc1 27 vcc2 10 vss1 28 vss2 6 cs oe 31 we 13 512kx8 16 17 22 27 23 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 36 19 20 21 24 25 26 28 29 30 31 32 33 34 35 u5 1 g4 a0 1 a1 2 a10 20 a11 21 a12 22 a13 23 a14 24 a15 32 a16 33 34 a17 35 a18 3 a2 a3 4 5 a4 14 a5 15 a6 a7 16 a8 17 a9 18 io1 7 io2 8 io3 11 io4 12 io5 25 io6 26 29 io7 io8 30 19 nc1 36 nc2 9 vcc1 27 vcc2 10 vss1 28 vss2 6 cs oe 31 we 13 512kx8 35 34 33 32 31 30 29 28 26 25 24 21 20 19 36 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 18 23 27 22 17 16 u6 1 g5 1 g3 ldata11 mwe3 mwe2 mwe1 mwe0 laddr18 laddr4 laddr3 laddr2 laddr1 laddr0 mcs0 laddr11 laddr12 laddr13 laddr17 laddr14 +3v gnd gnd +3v laddr5 laddr6 laddr7 laddr8 laddr9 laddr10 moe laddr15 laddr16 laddr16 laddr15 moe laddr10 laddr9 laddr8 laddr7 laddr6 laddr5 +3v gnd gnd +3v laddr14 laddr17 laddr13 laddr12 laddr11 mcs0 laddr0 laddr1 laddr2 laddr3 laddr4 laddr18 laddr16 laddr15 moe laddr10 laddr9 laddr8 laddr7 laddr6 laddr5 +3v gnd gnd +3v laddr14 laddr17 a0 1 a1 2 a10 20 a11 21 a12 22 a13 23 a14 24 a15 32 a16 33 34 a17 35 a18 3 a2 a3 4 5 a4 14 a5 15 a6 a7 16 a8 17 a9 18 io1 7 io2 8 io3 11 io4 12 io5 25 io6 26 29 io7 io8 30 19 nc1 36 nc2 9 vcc1 27 vcc2 10 vss1 28 vss2 6 cs oe 31 we 13 512kx8 35 34 33 32 31 30 29 28 26 25 24 21 20 19 36 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 18 23 27 22 17 16 u4 laddr13 laddr12 laddr11 mcs0 laddr0 laddr1 laddr2 laddr3 laddr4 laddr18 laddr18 laddr4 laddr3 laddr2 laddr1 laddr0 mcs0 laddr11 laddr12 laddr13 a0 1 a1 2 a10 20 a11 21 a12 22 a13 23 a14 24 a15 32 a16 33 34 a17 35 a18 3 a2 a3 4 5 a4 14 a5 15 a6 a7 16 a8 17 a9 18 io1 7 io2 8 io3 11 io4 12 io5 25 io6 26 29 io7 io8 30 19 nc1 36 nc2 9 vcc1 27 vcc2 10 vss1 28 vss2 6 cs oe 31 we 13 512kx8 16 17 22 27 23 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 36 19 20 21 24 25 26 28 29 30 31 32 33 34 35 u3 laddr17 laddr14 +3v gnd gnd +3v laddr5 laddr6 laddr7 laddr8 laddr9 laddr10 moe laddr15 laddr16 ldata0 ldata1 ldata2 ldata3 ldata4 ldata5 ldata6 ldata7 ldata8 ldata9 ldata10 ldata12 ldata13 ldata14 ldata15 ldata16 ldata17 ldata18 ldata19 ldata20 ldata21 ldata22 ldata23 ldata24 ldata25 ldata26 ldata27 ldata28 ldata29 ldata30 ldata31 cd b a d 4 c b a 4 3 2 1 1 2 3 scale: size b code ident no. drawing no. sheet of rev none 8236/8250 bt00-x700 4 6 11-13-2001_12:43 1 10 11 12 13 14 15 16 2 3 4 5 6 7 89 ra6 51 1 10 11 12 13 14 15 16 2 3 4 5 6 7 89 ra9 51 1 10 11 12 13 14 15 16 2 3 4 5 6 7 89 ra8 51 series termination bottom side top side bt00-d700-011.004p f
cx28250 3.0 applications atm physical interface (phy) devices 3.3 the cx28250/cx28236 network interface card reference design 28250-dsh-002-c mindspeed technologies ? 3-11 500035_047 sda 12 j77 2 1 j78 pci5v tied high = 5v signaling pci voltage select pci5v tied low = 3.3v signaling j114 txaddr0 txaddr2 txaddr4 txaddr[4:0] txaddr1 txaddr3 clk66 txd[15:0] txd10 txd6 txd0 txd1 txd7 txd2 txd3 txd4 txd5 txd8 txd9 txd11 txd12 txd13 txd14 txd15 1 10 11 12 13 14 15 16 2 3 4 5 6 7 89 51 ra1 1 10 11 12 13 14 15 16 2 3 4 5 6 7 89 51 ra10 cc r3 10k +3v 2 1 1 2 jp1 cc r2 10k +3v j112 j110 2 3 1 j37 pci5v cc r55 10k txpar cc r70 49.9 hc/be0 hc/be1 hc/be2 txclav txsoc 2 1 j115 12 j116 +3v gnd hrst hclk hperr hgnt hidsel hdevsel hstop htrdy hirdy hframe hpar hc/be3 had[31:0] had31 had30 had29 had28 had27 had26 had25 had24 had23 had22 had21 had20 had19 had18 had17 had16 had15 had14 had13 had12 had11 had10 had9 had8 had7 had6 had5 had4 had3 had2 had1 had0 sr_laddr1 sr_laddr[1:0] sr_laddr0 sr_laddr18 sr_laddr[18:2] sr_laddr2 sr_laddr3 sr_laddr4 sr_laddr5 sr_laddr6 sr_laddr7 sr_laddr8 sr_laddr9 sr_laddr10 sr_laddr11 sr_laddr12 sr_laddr13 sr_laddr14 sr_laddr15 sr_laddr16 sr_laddr17 sr_ldata31 sr_ldata[31:0] sr_ldata0 sr_ldata1 sr_ldata2 sr_ldata3 sr_ldata4 sr_ldata5 sr_ldata6 sr_ldata7 sr_ldata8 sr_ldata9 sr_ldata10 sr_ldata11 sr_ldata12 sr_ldata13 sr_ldata14 sr_ldata15 sr_ldata16 sr_ldata17 sr_ldata18 sr_ldata19 sr_ldata20 sr_ldata21 sr_ldata22 sr_ldata23 sr_ldata24 sr_ldata25 sr_ldata26 sr_ldata27 sr_ldata28 sr_ldata29 sr_ldata30 cc r33 49.9 cc r32 cc r29 cc r28 cc r30 cc r27 cc r34 cc r35 cc r31 no nc 128x8 1 a0 2 a1 3 a2 4 gnd 5 sda 6 scl 7 wp 8 vcc 8 7 6 5 4 3 2 1 u19 date approvals contract no. drawn checked engineer schematic 4 rev code ident no. drawing no. sheet of b size none scale: approved date ltr zone revisions a initial release 1 2 3 d c b a 4 3 2 1 ab c d description mindspeed technologies, inc. boulder, co 80301 8236/8250 10/01 dan scott /project/pcbbdc/8236-8250/bt00-d700-011.001p 1 6 bt00-x700 pcb: bt00-d705-011 11-13-2001_12:45 12 j100 2 1 j93 12 j92 2 1 j91 12 j94 2 1 j89 12 j95 2 1 j96 12 j90 1 g7 moe gnd +3v gnd gnd gnd gnd gnd gnd gnd gnd +3v j98 j97 j104 sar-stat0 sar-stat1 +3v cc r38 sysclk cc 49.9 r53 66mhz cc c99 .01 cc 10k r54 tdo-tdi prst phy_int hserr hint hreq pas pwnr trst tck tms pcitdi +3v vcc 14 7 vss 8 out y2 j103 mwe1 mwe2 mwe[3:0] mwe3 mwe0 all cc r40 12 j99 pcs 2 1 j88 rxclav rxsoc +3v rxpar rdy +3v +3v open = ul1 ground = ul2 1 10 11 12 13 14 15 16 2 3 4 5 6 7 89 51 ra12 1 10 11 12 13 14 15 16 2 3 4 5 6 7 89 51 ra11 rxaddr4 rxaddr[4:0] rxaddr0 rxaddr1 rxaddr2 rxaddr3 j108 1 j106 mcs[3:0] mcs3 mcs0 scl h+5v david jones (303)545-5088 rxd[15:0] rxd15 rxd0 rxd2 rxd3 rxd4 rxd5 rxd6 rxd7 rxd8 rxd9 rxd10 rxd11 rxd12 rxd13 rxd14 rxd1 cc 49.9 r37 j113 j111 sysclkx clkd3 rxenb sarutoprxclk b1 spare-b1 d4 spare-d4 d17 spare-d17 c17 spare-c17 c3 spare-c3 c22 spare-c22 ae24 spare-ae24 clk2x n4 clkd3 l2 d22 eepwr frcfg0 ae12 frcfg1 af12 frctrl/rxclk ac13 had0 d24 had1 d25 had10 h23 had11 h24 had12 h25 had13 j24 had14 j25 had15 j26 had16 p26 had17 p25 had18 p24 had19 r26 had2 d26 had20 r25 had21 r24 had22 r23 had23 t25 had24 u24 had25 u23 had26 v26 had27 v25 had28 v24 had29 w26 had3 e23 had30 w25 had31 w24 had4 e26 had5 f23 had6 f24 had7 f25 had8 g25 had9 g26 hclk n23 c25 hfiford0 b26 hfiford1 c24 hfiford2 d23 hfiford3 a25 hfiford4 c23 hfiford5 c2 hfifowr0 d3 hfifowr1 d2 hfifowr2 d1 hfifowr3 e3 hfifowr4 f4 hfifowr5 hidsel t24 hpar k24 laddr0 a3 laddr1 c4 laddr10 d7 laddr11 c7 laddr12 b7 laddr13 a7 laddr14 b8 laddr15 a8 laddr16 d9 laddr17 c9 laddr18 b9 laddr2 b4 laddr3 a4 laddr4 d5 laddr5 c5 laddr6 b5 laddr7 a5 laddr8 b6 laddr9 a6 ldata0 ac3 ldata1 ac2 ldata10 y3 ldata11 y2 ldata12 y1 ldata13 w3 ldata14 w2 ldata15 w1 ldata16 v4 ldata17 v3 ldata18 v1 ldata19 u4 ldata2 ac1 ldata20 u3 ldata21 u1 ldata22 t4 ldata23 t3 ldata24 r4 ldata25 r3 ldata26 r2 ldata27 r1 ldata28 p3 ldata29 p2 ldata3 ab4 ldata30 p1 ldata31 n1 ldata4 ab2 ldata5 ab1 ldata6 aa4 ldata7 aa3 ldata8 aa1 ldata9 y4 paddr0 c10 paddr1 b10 pbsel0 a10 pbsel1 d11 pci5v ab26 procmode b16 pwnr c13 rammode g4 ae4 rxaddr0 ad4 rxaddr1 af3 rxaddr2 ae3 rxaddr3 af2 rxaddr4 rxd0 af9 rxd1 ac9 af6 rxd10 ae6 rxd11 ad6 rxd12 ac6 rxd13 af5 rxd14 ae5 rxd15 rxd2 af8 rxd3 ae8 rxd4 ad8 rxd5 ac8 rxd6 af7 rxd7 ae7 ad7 rxd8 ac7 rxd9 rxmark ac10 rxpar ad5 ae1 schref ab23 scl ab24 sda stat0 f1 stat1 f2 sysclk m2 tclk ac23 tdi ac25 tdo ac24 spare-ab25 ab25 spare-af25 af25 tms ad26 ac22 txaddr0 ad22 txaddr1 ae22 txaddr2 af22 txaddr3 ac21 txaddr4 txd0 ae21 txd1 af21 ae18 txd10 ac17 txd11 ad17 txd12 ae17 txd13 af17 txd14 ac16 txd15 txd2 ac20 txd3 ad20 txd4 ae20 txd5 af20 txd6 ae19 txd7 af19 ac18 txd8 ad18 txd9 txmark af15 txpar ae16 hc/be0 f26 hc/be1 k23 hc/be2 n26 hc/be3 t23 hdevsel l26 b23 henum hframe m25 hgnt y25 aa25 hint hirdy m24 l4 hled hperr l24 hreq y26 hrst y23 l23 hserr hstop l25 f3 hswitch htrdy m23 mcs0 k3 mcs1 k4 mcs2 j1 mcs3 j2 moe h1 mwe0 h2 mwe1 h3 mwe2 g2 mwe3 g3 mwr j4 pas d14 pbe0 c11 pbe1 d12 pbe2 c12 pbe3 b12 pblast c14 pcs a15 pdaen b15 pfail c15 pint d15 prdy b13 prst a16 pwait a13 rxen ad10 rxflag ae11 trst ad25 txen ac14 txflag af16 serial eeprom test signals interface processor atm physical local bus local bus interface interface boundary scan memory host pci interface signals clocks/status hdcsm cn8236 ad3 spare-ad3 vgg e4 ad14 utopia1 ad12 txclk b1 d4 d17 c17 c3 c22 ae24 n4 l2 d22 ae12 af12 ac13 d24 d25 h23 h24 h25 j24 j25 j26 p26 p25 p24 r26 d26 r25 r24 r23 t25 u24 u23 v26 v25 v24 w26 e23 w25 w24 e26 f23 f24 f25 g25 g26 n23 c25 b26 c24 d23 a25 c23 c2 d3 d2 d1 e3 f4 t24 k24 a3 c4 d7 c7 b7 a7 b8 a8 d9 c9 b9 b4 a4 d5 c5 b5 a5 b6 a6 ac3 ac2 y3 y2 y1 w3 w2 w1 v4 v3 v1 u4 ac1 u3 u1 t4 t3 r4 r3 r2 r1 p3 p2 ab4 p1 n1 ab2 ab1 aa4 aa3 aa1 y4 c10 b10 a10 d11 ab26 b16 c13 g4 ae4 ad4 af3 ae3 af2 af9 ac9 af6 ae6 ad6 ac6 af5 ae5 af8 ae8 ad8 ac8 af7 ae7 ad7 ac7 ac10 ad5 ae1 ab23 ab24 f1 f2 m2 ac23 ac25 ac24 ab25 af25 ad26 ac22 ad22 ae22 af22 ac21 ae21 af21 ae18 ac17 ad17 ae17 af17 ac16 ac20 ad20 ae20 af20 ae19 af19 ac18 ad18 af15 ae16 f26 k23 n26 t23 l26 b23 m25 y25 aa25 m24 l4 l24 y26 y23 l23 l25 f3 m23 k3 k4 j1 j2 h1 h2 h3 g2 g3 j4 d14 c11 d12 c12 b12 c14 a15 b15 c15 d15 b13 a16 a13 ad10 ae11 ad25 ac14 af16 ad3 e4 ad14 ad12 u1 txenb sarutoptxclk cn8236-cx28250 evm 2.2k 2.2k f
3.0 applications cx28250 3.3 the cx28250/cx28236 network interface card reference design atm physical interface (phy) devices 3-12 mindspeed technologies ? 28250-dsh-002-c 500035_050 +3v l5, m5, m7, m9, n9 digital power pins d10, d13, j2, j3, k11 c7, c10, d1, d3, d8 cx28250 no connect pins ground pins a8, b6, c11, d4, d12 e1, e2, g1, g4, h3 j13, l1, l8, m11, n6 n7, n10, p6, p9 analog power pins d7, g11, m13 l11 to l16 a1, c1, e2, g1, k2, m3 b2, e1, h4, j3, k1, l3 l1, n3, p4, t2, u2, ab3 ad2, ae2, ac5, ae9, ac12 ae13, ae14, ad16, ac19 ad21, ae23, af24, ae25 ae26, ac26, aa24, aa26 v23, u26, t26, n24, k25 j23, g23, e24, b25, a24 d21, b19, c16, a14, a12 b11, a9, d8, d6, a2 m1, n2, t1, v2, w4, aa2 ad1, af1, ac4, af4, ad9 ae10, ad13, af14, af18 ad19, af23, af26, aa23 y24, w23, u25, p23, n25 m26, k26, h26, g24, e25 c26, a26, b24, a23, c20 a18, d16, b14, d13, a11 d10, c8, c6, b3 power pins gnd pins thermal pins m11 to m16 n11 to n16 p11 to p16 r11 to r16 t11 to t16 +3v cc c39 100pf h+5v cc + 10 c7 power cd b a d 4 c b a 4 3 2 1 1 2 3 scale: size b code ident no. drawing no. sheet of rev none 5 6 bt00-d700-011.5 bt00-x700 f cc 100pf c33 cc 100pf c35 cc 100pf c36 cc 100pf c37 cc 100pf c38 cc 100pf c41 cc 100pf c34 cc + 10 c15 cc + 10 c13 cc .01 c29 cc .01 c30 cc .01 c25 cc .01 c24 cc .01 c23 cc .01 c22 cc .01 c31 cc .01 c32 cc .01 c18 cc .01 c19 cc .01 c20 cc .01 c21 cc .01 c26 cc + 10 c14 cc + 10 c12 cc .01 c87 cc .01 c90 cc .01 c75 cc .01 c91 cc .01 c92 cc .01 c77 cc .01 c83 cc .01 c76 cc .01 c84 cc .01 c46 cc + 10 c5 cc .01 c73 cc .01 c64 cc .01 c95 cc .01 c61 cc .01 c62 cc .01 c98 cc .01 c63 cc .01 c60 cc .01 c66 cc .01 c68 cc .01 c65 cc .01 c72 cc .01 c71 cc .01 c70 cc .01 c69 cc .01 c96 cc .01 c74 cc .01 c88 cc .01 c58 cc .01 c52 cc .01 c53 cc .01 c50 cc .01 c49 cc .01 c78 cc .01 c93 cc .01 c100 cc .01 c45 cc .01 c16 cc + 10 c10 cc + 10 c9 cc c56 .01 cc .01 c57 cc + 10 c6 cc .01 c94 cc .01 c79 cc c97 .01 cc c44 .01 cc .01 c43 cc .01 c101 cc .01 c47 cc c67 100pf +3v +3v +3v h+5v cc c54 100pf cc c89 2.2uf cc c80 470pf cc + 10 c11 cc + 10 c3 note: analog+3v cc c40 100pf cc c59 100pf 4 byp 3 en 2 gnd 1 vin 5 vout sot23-5 vreg 4 5 2 3 1 vr2 cn8236 cc + 10 c4 cc + 10 c1 h+5v lm3940 gnd 2 3_3v 3 5v 1 vr1 analog voltage pins only h+5v is +5v from host pci bus the cx28250 phy analog+3v is supply for +3v = sar supply is +3.3v +3v
28250-dsh-002-c mindspeed technologies ? 4-1 4 4.0 registers the cx28250 registers are used to control and observe the device?s oper ations. a complete list of these registers are presented in table 4-1 . table 4-2 through table 4-9 list the registers according to type. all registers are 8 bits wide. all control registers ca n be read to verify contents. note: control bits that do not have a defined function are reserved and must be written to zero. table 4-1. control and status registers (1 of 5) address name type onesec latching description page number 0x00 gen r/w ? general cont rol register page 27 0x01 clkrec r/w ? clock recovery control register page 19 0x02 outstat r/w ? output pin control register page 34 0x03 version r ? part number/version status register page 67 0x04 cgen r/w ? cell generation control register page 18 0x05 idlpay r/w ? transmit idle cell payload control register page 30 0x06 errins r/w (1) ? error insertion control register page 25 0x07 errpat r/w ? error pattern control register page 26 0x08 cval r/w ? cell validation control register page 20 0x09 apsthresh r/w ? aps threshold c ontrol register page 13 0x0a utop1 r/w ? utopia control register 1 page 66 0x0b utop2 r/w ? utopia control register 2 page 67 0x0c txsec r/w ? transmit section over head control register page 63 0x0d txlin r/w ? transmit line overhead control register page 61 0x0e txpth r/w ? transmit path overhead control register page 62 0x0f ? ? ? unused ? 0x10 txk1 r/w ? transmit k1 overhead control register page 60 0x11 txk2 r/w ? transmit k2 overhead control register page 60 0x12 txs1 r/w ? transmit s1 overhead status register page 63
4.0 registers cx28250 atm physical interface (phy) devices 4-2 mindspeed technologies ? 28250-dsh-002-c 0x13 txc2 r/w ? transmit c2 overhead control register page 53 0x14 rxk1 r ? receive k1 overhead status register page 44 0x15 rxk2 r ? receive k2 overhead status register page 45 0x16 rxs1 r ? receive s1 overhead status register page 49 0x17 ? ? ? unused ? 0x18 rxc2 r ? receive c2 overhead status register page 37 0x19 rxg1 r ? receive g1 overhead status register page 40 0x1a rxz01 r ? receive section z0 1 overhead register page 50 0x1b rxz02 r ? receive section z0 2 overhead register page 51 0x1c txhdr1 r/w ? transmit cell header control register 1 page 56 0x1d txhdr2 r/w ? transmit cell header control register 2 page 56 0x1e txhdr3 r/w ? transmit cell header control register 3 page 57 0x1f txhdr4 r/w ? transmit cell header control register 4 page 57 0x20 txidl1 r/w ? transmit idle cell header control register 1 page 58 0x21 txidl2 r/w ? transmit idle cell header control register 2 page 58 0x22 txidl3 r/w ? transmit idle cell header control register 3 page 59 0x23 txidl4 r/w ? transmit idle cell header control register 4 page 59 0x24 rxhdr1 r/w ? receive cell header control register 1 page 40 0x25 rxhdr2 r/w ? receive cell header control register 2 page 41 0x26 rxhdr3 r/w ? receive cell header control register 3 page 41 0x27 rxhdr4 r/w ? receive cell header control register 4 page 42 0x28 rxmsk1 r/w ? receive cell mask control register 1 page 46 0x29 rxmsk2 r/w ? receive cell mask control register 2 page 46 0x2a rxmsk3 r/w ? receive cell mask control register 3 page 47 0x2b rxmsk4 r/w ? receive cell mask control register 4 page 47 0x2c rxidl1 r/w ? receive idle cell header control register 1 page 42 0x2d rxidl2 r/w ? receive idle cell header control register 2 page 43 0x2e rxidl3 r/w ? receive idle cell header control register 3 page 43 0x2f rxidl4 r/w ? receive idle cell header control register 4 page 44 0x30 idlmsk1 r/w ? receive idle cell mask control register 1 page 28 table 4-1. control and status registers (2 of 5) address name type onesec latching description page number
cx28250 4.0 registers atm physical interface (phy) devices 28250-dsh-002-c mindspeed technologies ? 4-3 0x31 idlmsk2 r/w ? receive idle cell mask control register 2 page 28 0x32 idlmsk3 r/w ? receive idle cell mask control register 3 page 29 0x33 idlmsk4 r/w ? receive idle cell mask control register 4 page 29 0x34 ensumint r/w ? summary interrupt mask control register page 25 0x35 ensec r/w ? receive section interrupt mask control register page 24 0x36 enlin r/w ? receive line interrupt mask control register page 23 0x37 enpth r/w ? receive path interrupt mask control register page 24 0x38 encellt r/w ? transmit cell interrupt mask control register page 22 0x39 encellr r/w ? receive cell interrupt mask control register page 21 0x3a enaps r/w ? aps interrupt mask control register page 21 0x3b b3thresh r/w ? b3 threshold control register page 17 0x3c sumint r ? summary interrupt indica tion status register page 52 0x3d secint r ? receive section in terrupt indication status register page 51 0x3e linint r ? receive line interrupt i ndication status register page 32 0x3f pthint r ? receive path interrupt i ndication status register page 36 0x40 txcellint r ? transmit cell interrupt in dication status register page 54 0x41 rxcellint r ? receive cell interrupt i ndication status register page 38 0x42 apsint r ? aps interrupt indicati on status register page 12 0x43 ? ? ? unused ? 0x44 ? ? ? unused ? 0x45 rxsec r[7:2] r/w[1:0] 3 (2) receive section overhead status register page 49 0x46 rxlin r[7:2] r/w[1:0] 3 (2) receive line overhe ad status register page 45 0x47 rxpth r 3 (2) receive path overhead status register page 48 0x48 txcell r 3 (2) transmit cell status register page 53 0x49 rxcell r 3 (2) receive cell status register page 37 0x4a rxaps r ? receive aps status register page 36 0x4b ? ? ? unused ? 0x4c locdcnt r 3 (3) locd event counter page 32 table 4-1. control and status registers (3 of 5) address name type onesec latching description page number
4.0 registers cx28250 atm physical interface (phy) devices 4-4 mindspeed technologies ? 28250-dsh-002-c 0x4d corrcnt r 3 (3) corrected hec error counter page 20 0x4e unccnt r 3 (3) uncorrected hec error counter page 66 0x4f oofcnt r 3 (3) oof event counter page 34 0x50 b2cntl r 3 (3) line bip error counter (low byte) page 15 0x51 b2cntm r 3 (3) line bip error counter (mid byte) page 15 0x52 b2cnth r 3 (3) line bip error counter (high byte) page 14 0x53 ? ? ? unused ? 0x54 b1cntl r 3 (3) section bip error counter (low byte) page 14 0x55 b1cnth r 3 (3) section bip error counter (high byte) page 13 0x56 b3cntl r 3 (3) path bip error counter (low byte) page 16 0x57 b3cnth r 3 (3) path bip error counter (high byte) page 16 0x58 lfcntl r 3 (3) line rei error counter (low byte) page 31 0x59 lfcntm r 3 (3) line rei error counter (mid byte) page 31 0x5a lfcnth r 3 (3) line rei error counter (high byte) page 30 0x5b ? ? ? unused ? 0x5c pfcntl r 3 (3) path rei error counter (low byte) page 35 0x5d pfcnth r 3 (3) path rei error counter (high byte) page 35 0x5e noncntl r 3 (3) non-matching cell c ounter (low byte) page 33 0x5f noncnth r 3 (3) non-matching cell counter (high byte) page 33 0x60 txcntl r 3 (3) transmitted cell counter (low byte) page 55 0x61 txcntm r 3 (3) transmitted cell counter (mid byte) page 55 0x62 txcnth r 3 (3) transmitted cell counter (high byte) page 54 0x63 ? ? ? unused ? 0x64 rxcntl r 3 (3) received cell count er (low byte) page 39 0x65 rxcntm r 3 (3) received cell counter (mid byte) page 39 0x66 rxcnth r 3 (3) received cell count er (high byte) page 38 0x67 ? ? ? unused ? table 4-1. control and status registers (4 of 5) address name type onesec latching description page number
cx28250 4.0 registers atm physical interface (phy) devices 28250-dsh-002-c mindspeed technologies ? 4-5 0x68 txsecbuf r/w ? transmit section trace circular buffer page 64 0x69 txpthbuf r/w ? transmit path trace circular buffer page 62 0x6a rxsecbuf r/w ? receive section trace circular buffer page 50 0x6b rxpthbuf r/w ? receive path trace circular buffer page 48 0x6c txz01 r/w ? transmit section z0 1 overhead control register page 64 0x6d txz02 r/w ? transmit section z0 2 overhead control register page 65 0x6e enlfout r/w ? enable line fail output page 22 0x6f enpfout r/w ? enable path fail output page 23 0x70?0x071 cdr test r ? reserved?do not write page 17 0x72 inlk ? in lock coefficient register page 30 0x73 outlk ? out of lock coefficient register page 34 0x74 udf2 r/w ? udf2 overwrite control register page 65 0x75?0x7f ? ? ? unused ? note(s): (1) these bits are cleared automatically by internal circuitry after the indicated error insertion has taken place. clearing takes precedence over a simultaneous write operation to this register. (2) enabled by setting enstatlat in the general control register (0x00), bit 5 to a logic 1. (3) enabled by setting encntrlat in general cont rol register (0x00), bit 4 to a logic 1. table 4-2. general use registers address name type onesec latching description page number 0x00 gen r/w ? general cont rol register page 27 0x02 outstat r/w ? output pin control register page 34 0x03 version r ? part number/version status register page 67 table 4-1. control and status registers (5 of 5) address name type onesec latching description page number
4.0 registers cx28250 atm physical interface (phy) devices 4-6 mindspeed technologies ? 28250-dsh-002-c table 4-3. cell transmit control registers address name type onesec latching description page number 0x04 cgen r/w ? cell generation control register page 18 0x05 idlpay r/w ? transmit idle cell payload control register page 30 0x1c txhdr1 r/w ? transmit cell header control register 1 page 56 0x1d txhdr2 r/w ? transmit cell header control register 2 page 56 0x1e txhdr3 r/w ? transmit cell header control register 3 page 57 0x20 txidl1 r/w ? transmit idle cell header control register 1 page 58 0x21 txidl2 r/w ? transmit idle cell header control register 2 page 58 0x22 txidl3 r/w ? transmit idle cell header control register 3 page 59 0x23 txidl4 r/w ? transmit idle cell header control register 4 page 59
cx28250 4.0 registers atm physical interface (phy) devices 28250-dsh-002-c mindspeed technologies ? 4-7 table 4-4. cell receive control registers address name type onesec latching description page number 0x08 cval r/w ? cell validation control register page 20 0x24 rxhdr1 r/w ? receive cell header control register 1 page 40 0x25 rxhdr2 r/w ? receive cell header control register 2 page 41 0x26 rxhdr3 r/w ? receive cell header control register 3 page 41 0x27 rxhdr4 r/w ? receive cell header control register 4 page 42 0x28 rxmsk1 r/w ? receive cell mask control register 1 page 46 0x29 rxmsk2 r/w ? receive cell mask control register 2 page 46 0x2a rxmsk3 r/w ? receive cell mask control register 3 page 47 0x2b rxmsk4 r/w ? receive cell mask control register 4 page 47 0x2c rxidl1 r/w ? receive idle cell header control register 1 page 42 0x2d rxidl2 r/w ? receive idle cell header control register 2 page 43 0x2e rxidl3 r/w ? receive idle cell header control register 3 page 43 0x2f rxidl4 r/w ? receive idle cell header control register 4 page 44 0x30 idlmsk1 r/w ? receive idle cell mask control register 1 page 28 0x31 idlmsk2 r/w ? receive idle cell mask control register 2 page 28 0x32 idlmsk3 r/w ? receive idle cell mask control register 3 page 29 0x33 idlmsk4 r/w ? receive idle cell mask control register 4 page 29 table 4-5. utopia control registers address name type onesec latching description page number 0x0a utop1 r/w ? utopia control register 1 page 66 0x0b utop2 r/w ? utopia control register 2 page 67 0x74 udf2 r/w ? user defined field 2 page 65
4.0 registers cx28250 atm physical interface (phy) devices 4-8 mindspeed technologies ? 28250-dsh-002-c table 4-6. sonet overhead transmit control registers address name type onesec latching description page number 0x06 errins r/w (1) ? error insertion control register page 25 0x07 errpat r/w ? error pattern control register page 26 0x0c txsec r/w ? transmit section over head control register page 63 0x0d txlin r/w ? transmit line overhead control register page 61 0x0e txpth r/w ? transmit path overhead control register page 62 0x10 txk1 r/w ? transmit k1 overhead control register page 60 0x11 txk2 r/w ? transmit k2 overhead control register page 60 0x12 txs1 r/w ? transmit s1 overhead status register page 63 0x13 txc2 r/w ? transmit c2 overhead control register page 53 0x68 txsecbuf r/w ? transmit section trace circular buffer page 64 0x69 txpthbuf r/w ? transmit path trace circular buffer page 62
cx28250 4.0 registers atm physical interface (phy) devices 28250-dsh-002-c mindspeed technologies ? 4-9 table 4-7. sonet overhead receive control registers address name type onesec latching description page number 0x09 apsthresh r/w ? aps threshold c ontrol register page 13 0x14 rxk1 r ? receive k1 overhead status register page 44 0x15 rxk2 r ? receive k2 overhead status register page 45 0x16 rxs1 r ? receive s1 overhead status register page 49 0x18 rxc2 r ? receive c2 overhead status register page 37 0x19 rxg1 r ? receive g1 overhead status register page 40 0x1a rxz01 r ? receive section z0 1 overhead register page 50 0x1b rxz02 r ? receive section z0 2 overhead register page 51 0x6a rxsecbuf r/w ? receive section trace circular buffer page 50 0x6b rxpthbuf r/w ? receive path trace circular buffer page 48 0x6c txz01 r/w ? transmit section z0 1 overhead control register page 64 0x6d txz02 r/w ? transmit section z0 2 overhead control register page 65 0x6e enlfout r/w ? enable line fail output page 22 0x6f enpfout r/w ? enable path fail output page 23
4.0 registers cx28250 atm physical interface (phy) devices 4-10 mindspeed technologies ? 28250-dsh-002-c table 4-8. status and interrupt registers address name type onesec latching description page number 0x34 ensumint r/w ? summary interrupt mask control register page 25 0x35 ensec r/w ? receive section interrupt mask control register page 24 0x36 enlin r/w ? receive line interrupt mask control register page 23 0x37 enpth r/w ? receive path interrupt mask control register page 24 0x38 encellt r/w ? transmit cell interrupt mask control register page 22 0x39 encellr r/w ? receive cell interrupt mask control register page 21 0x3a enaps r/w ? aps interrupt mask control register page 21 0x3c sumint r ? summary interrupt indica tion status register page 52 0x3d secint r ? receive section in terrupt indication status register page 51 0x3e linint r ? receive line interrupt i ndication status register page 32 0x3f pthint r ? receive path interrupt i ndication status register page 36 0x40 txcellint r ? transmit cell interrupt in dication status register page 54 0x41 rxcellint r ? receive cell interrupt i ndication status register page 38 0x42 apsint r ? aps interrupt indicati on status register page 12 0x45 rxsec r[7:2] r/w[1:0] 3 (1) receive section overhead status register page 49 0x46 rxlin r[7:2] r/w[1:0] 3 (1) receive line overhe ad status register page 45 0x47 rxpth r 3 (1) receive path overhead status register page 48 0x48 txcell r 3 (1) transmit cell status register page 53 0x49 rxcell r 3 (1) receive cell status register page 37 0x4a rxaps r ? receive aps status register page 36 note(s): (1) enabled by setting enstatlat in the general control register (0x00), bit 5 to a logic 1.
cx28250 4.0 registers atm physical interface (phy) devices 28250-dsh-002-c mindspeed technologies ? 4-11 table 4-9. counters address name type onesec latching description page number 0x4c locdcnt r 3 (2) locd event counter page 32 0x4d corrcnt r 3 (2) corrected hec error counter page 20 0x4e unccnt r 3 (2) uncorrected hec error counter page 66 0x4f oofcnt r 3 (2) oof event counter page 34 0x50 b2cntl r 3 (2) line bip error counter (low byte) page 15 0x51 b2cntm r 3 (2) line bip error counter (mid byte) page 15 0x52 b2cnth r 3 (2) line bip error counter (high byte) page 14 0x54 b1cntl r 3 (2) section bip error counter (low byte) page 14 0x55 b1cnth r 3 (2) section bip error counter (high byte) page 13 0x56 b3cntl r 3 (2) path bip error counter (low byte) page 16 0x57 b3cnth r 3 (2) path bip error counter (high byte) page 16 0x58 lfcntl r 3 (2) line rei error counter (low byte) page 31 0x59 lfcntm r 3 (2) line rei error counter (mid byte) page 31 0x5a lfcnth r 3 (2) line rei error counter (high byte) page 30 0x5c pfcntl r 3 (2) path rei error counter (low byte) page 35 0x5d pfcnth r 3 (2) path rei error counter (high byte) page 35 0x5e noncntl r 3 (2) non-matching cell c ounter (low byte) page 33 0x5f noncnth r 3 (2) non-matching cell counter (high byte) page 33 0x60 txcntl r 3 (2) transmitted cell counter (low byte) page 55 0x61 txcntm r 3 (2) transmitted cell counter (mid byte) page 55 0x62 txcnth r 3 (2) transmitted cell counter (high byte) page 54 0x64 rxcntl r 3 (2) received cell count er (low byte) page 39 0x65 rxcntm r 3 (2) received cell counter (mid byte) page 39 0x66 rxcnth r 3 (2) received cell count er (high byte) page 38 note(s): (1) these bits are cleared automatically by internal circuitry after the indicated error insertion has taken place. clearing takes precedence over a simultaneous write operation to this register. (2) enabled by setting encntrlat in general cont rol register (0x00), bit 4 to a logic 1.
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-12 mindspeed technologies ? 28250-dsh-002-c 4.1 registers this section describes the registers. 0x42?apsint (aps interrupt in dication status register) the apsint register indicates that a change of stat us has occurred within its affiliated status signals. bit default name description 7 0 ? reserved, set to 0. 6 0 ? reserved, set to 0. 5 0 ? reserved, set to 0. 4x psbfint (1) when a logic 1 is read, this bit indicate s that a protection sw itching byte failure (psbf) alarm interrupt has occurred. 3 0 b3failint when a logic 1 is read, this bit indicates that the b3 error count exceeded the programmed threshold. this bit is on ly valid for the CX28250-26 and above. 2 0 b3degradeint when a logic 1 is read, this bit indicates that the b3 error count exceeded the programmed threshold. this bit is on ly valid for the CX28250-26 and above. 1x sigfailint (1) when a logic 1 is read, this bit indicate s that a signal fail interrupt has occurred. 0x sigdegradeint (1) when a logic 1 is read, this bit indicates that a signal degrade interrupt has occurred. note(s): (1) dual event?a 0?> 1 and 1?> 0 transition on the corresponding status bit ca uses this interrupt to oc cur provided that this interrupt has been enabled by the corre sponding enable bit. reading the inte rrupt register clears the interrupt.
cx28250 4.0 registers atm physical interface (phy) devices 4.1 registers 28250-dsh-002-c mindspeed technologies ? 4-13 0x09?apsthresh (aps threshold control register) the apsthresh register sets the threshold value for si gnal fail and signal degr ade alarm generation. bits 7?4 are the signal fail threshold exponent (default = 10 -3 ) and bits 3?0 are the signal degrade threshold exponent (default = 10 -6 ). 0x55?b1cnth (section bip er ror counter [high byte]) the b1cnth counter tr acks the number of section bip errors. bit default name description 7 0 sfthresh[3] threshold exponent value for setting signal fail status?bit 3 (msb) 6 0 sfthresh[2] threshold exponent value fo r setting signal fail status?bit 2 5 1 sfthresh[1] threshold exponent value fo r setting signal fail status?bit 1 4 1 sfthresh[0] threshold exponent value for setting signal fail status?bit 0 (lsb) 3 0 sdthresh[3] threshold exponent value for setting signal degrad e status?bit 3 (msb) 2 1 sdthresh[2] threshold exponent value fo r setting signal degr ade status?bit 2 1 1 sdthresh[1] threshold exponent value fo r setting signal degr ade status?bit 1 0 0 sdthresh[0] threshold exponent value for se tting signal degrade status?bit 0 (lsb) bit default name description 7 x b1cnt[15] section bip error counter bit 15 (msb). 6 x b1cnt[14] section bip error counter bit 14. 5 x b1cnt[13] section bip error counter bit 13. 4 x b1cnt[12] section bip error counter bit 12. 3 x b1cnt[11] section bip error counter bit 11. 2 x b1cnt[10] section bip error counter bit 10. 1 x b1cnt[9] section bip error counter bit 9. 0 x b1cnt[8] section bip error counter bit 8.
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-14 mindspeed technologies ? 28250-dsh-002-c 0x54?b1cntl (section bip error counter [low byte]) the b1cntl counter tracks the nu mber of section bip errors. 0x52?b2cnth (line bip e rror counter [high byte]) the b2cnth counter tracks the number of line bip errors. bit default name description 7 x b1cnt[7] section bip error counter bit 7. 6 x b1cnt[6] section bip error counter bit 6. 5 x b1cnt[5] section bip error counter bit 5. 4 x b1cnt[4] section bip error counter bit 4. 3 x b1cnt[3] section bip error counter bit 3. 2 x b1cnt[2] section bip error counter bit 2. 1 x b1cnt[1] section bip error counter bit 1. 0 x b1cnt[0] section bip error counter bit 0 (lsb). bit default name description 7 0 ? reserved, set to 0. 6 0 ? reserved, set to 0. 5 0 ? reserved, set to 0. 4 0 ? reserved, set to 0. 3 0 ? reserved, set to 0. 2 0 ? reserved, set to 0. 1 x b2cnt[17] line bip error counter bit 17 (msb). 0 x b2cnt[16] line bip error counter bit 16.
cx28250 4.0 registers atm physical interface (phy) devices 4.1 registers 28250-dsh-002-c mindspeed technologies ? 4-15 0x50?b2cntl (line bip e rror counter [low byte]) the b2cntl counter tracks the number of line bip errors. 0x51?b2cntm (line bip error counter [mid byte]) the b2cntm counter tracks the number of line bip errors. bit default name description 7 x b2cnt[7] line bip error counter bit 7. 6 x b2cnt[6] line bip error counter bit 6. 5 x b2cnt[5] line bip error counter bit 5. 4 x b2cnt[4] line bip error counter bit 4. 3 x b2cnt[3] line bip error counter bit 3. 2 x b2cnt[2] line bip error counter bit 2. 1 x b2cnt[1] line bip error counter bit 1. 0 x b2cnt[0] line bip error counter bit 0 (lsb). bit default name description 7 x b2cnt[15] line bip error counter bit 15. 6 x b2cnt[14] line bip error counter bit 14. 5 x b2cnt[13] line bip error counter bit 13. 4 x b2cnt[12] line bip error counter bit 12. 3 x b2cnt[11] line bip error counter bit 11. 2 x b2cnt[10] line bip error counter bit 10. 1 x b2cnt[9] line bip error counter bit 9. 0 x b2cnt[8] line bip error counter bit 8.
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-16 mindspeed technologies ? 28250-dsh-002-c 0x57?b3cnth (path bip e rror counter [high byte]) the b3cnth counter tracks the number of path bip errors. 0x56?b3cntl (path bip error counter [low byte]) the b3cntl counter tracks the number of path bip errors. bit default name description 7 x b3cnt[15] path bip error counter bit 15 (msb). 6 x b3cnt[14] path bip error counter bit 14. 5 x b3cnt[13] path bip error counter bit 13. 4 x b3cnt[12] path bip error counter bit 12. 3 x b3cnt[11] path bip error counter bit 11. 2 x b3cnt[10] path bip error counter bit 10. 1 x b3cnt[9] path bip error counter bit 9. 0 x b3cnt[8] path bip error counter bit 8. bit default name description 7 x b3cnt[7] path bip error counter bit 7. 6 x b3cnt[6] path bip error counter bit 6. 5 x b3cnt[5] path bip error counter bit 5. 4 x b3cnt[4] path bip error counter bit 4. 3 x b3cnt[3] path bip error counter bit 3. 2 x b3cnt[2] path bip error counter bit 2. 1 x b3cnt[1] path bip error counter bit 1. 0 x b3cnt[0] path bip error counter bit 0 (lsb).
cx28250 4.0 registers atm physical interface (phy) devices 4.1 registers 28250-dsh-002-c mindspeed technologies ? 4-17 0x3b?b3thresh (b3 threshold control register) this registers sets the control threshol ds for the b3 path fail and path degrade interrupts. bits 7?4 are the signal fail threshold exponent (default = 10 ?4 ) and bits 3?0 are the signal degrade threshold exponent (default = 10 ?6 ). 0x70?0x71?cdr test registers reserved registers: the following loca tions are reserved for factory test purposes and should not be written to. bit default name description 7 0 b3fthresh[3] threshold exponent value fo r setting signal fail status bit 3 (msb) 6 1 b3fthresh[2] threshold exponent value for setting signal fa il status bit 2 5 0 b3fthresh[1] threshold exponent value for setting signal fa il status bit 1 4 0 b3fthresh[0] threshold exponent value fo r setting signal fail status bit 0 (lsb) 3 0 b3dthresh[3] threshold exponent value fo r setting signal degrade status bit 3 (msb) 2 1 b3dthresh[2] threshold exponent value for setting signal degr ade status bit 2 1 1 b3dthresh[1] threshold exponent value for setting signal degr ade status bit 1 0 0 b3dthresh[0] threshold exponent value for setting signal degrade status bit 0 (lsb) address default name description 0x70 0x03 cdrtest_0 reserved; do not write to this address 0x71 0xff cdrtest_1 reserved; do not write to this address
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-18 mindspeed technologies ? 28250-dsh-002-c 0x04?cgen (cell generati on control register) the cgen register controls the device?s cell generation functions. bit default name description 7 0 dishec when written to a logic 1, this bit disables internal ge neration of the hec field. when disabled, the hec field from the utopia interface remains unc hanged in the outgoing cell. when written to 0, he c is internally calculated a nd inserted in the outgoing cell. 6 1 entxcos when written to a logic 1, this bit enab les the transmitter hec coset. when written to 0, the hec coset is disabled. 5 1 entxcellscr when written to a logic 1, this bit enables the x 43 +1 transmit cell scrambler in the cell generator. when written to 0, the cell scrambler is disabled. 4 0 insgfc when written to a logic 1, this bit in serts a generic flow cont rol (gfc) field in the outgoing header from the txhdr registers. when written to 0, the gfc field comes from the utopia interface. 3 0 insvpi when written to a logic 1, this bit inserts a virtual path identifier (vpi) field in the outgoing header from the txhdr registers. when written to 0, the vpi field comes from the utopia interface. 2 0 insvci when written to a logic 1, this bit inserts a virtual channel identifier (vci) field in the outgoing header from the txhdr registers. when written to 0, the vci field comes from the utopia interface. 1 0 inspt when written to a logic 1, this bit inse rts a payload type (pt) field in the outgoing header from the txhdr registers. when wr itten to 0, the pt field comes from the utopia interface. 0 0 insclp when written to a logic 1, this bit inse rts a cell loss priority (clp) bit in the outgoing header from bit 0 in the txhdr4 register (0x1f). when written to 0, the clp field comes from the utopia interface.
cx28250 4.0 registers atm physical interface (phy) devices 4.1 registers 28250-dsh-002-c mindspeed technologies ? 4-19 0x01?clkrec (clock reco very control register) the clkrec register controls the clock recovery an d loopback testing capabilities of the device. see table 4-10 for a list of the valid configuration for the clkrec register. note: only one loopback may be selected at a time. bit default name description 7 0 invtxclk when written to a logic 1, this bit inverts the transmit clock output on ltxclk0+/-. 6 0 invrxclk this bit selects the type of receive clock sampling when using external clock recovery (bit 5 is written to 1). when written to 1, the receive clock samples data on the falling edge. when written to 0, the receive clock samples data on the rising edge. when bit 5 is written to 0, the settin g of this bit has no effect. 5 0 extclkrec when written to a logic 1, this bit en ables external clock recovery. when enabled, the internal clock recovery circuit is bypassed. when written to 0, internal clock recovery is used. 4 0 txclksel(1) these bits in combination prov ide the transmit clock select as follows: 00?tx clock synthesized from ex ternal 19.44 mhz input on pllclk 01?tx clock synthesized from reco vered receive clock (loop timing) 10?tx clock from external 155. 52 mhz input on txclki+/- 11?reserved; do not use 3 0 txclksel(0) 2 0 srcloop when written to a logic 1, this bit in vokes a source loopback. the receiver clock and data inputs are connected to the tr ansmitter clock and data inputs. see section 2.7 for more information. when source loopback is en abled, bit 5 of this register must be set to 0. 1 0 linloop1 when written to a logic 1, this bit enables line loopback 1. when enabled, the received line clock and data inputs are c onnected to line tran smitter outputs. see section 2.7 for more information. 0 0 linloop2 when written to a logic 1, this bit enables line loopback 2. when enabled, the received utopia clock and data outputs are connected to utopia tran smitter inputs. the utopia bus is placed in a high-impedanc e state. see section 2.7 for more information. table 4-10. clkrec valid configurations extclkrec txclksel(1) txclksel(0) srcloop linloop 1 linloop 2 description 0 0 0 0 0 0 normal operation 19.44 mhz transmit clock (default) 0 0 1 0 0 0 normal operation loop timed 1 x x 0 0 0 external clock recovery mode 0 0 0 1 0 0 source loopback x x x 0 1 0 line loopback 1. see section 2.7 . x x x 0 0 1 line loopback 2. see section 2.7 . 1 x x 1 0 0 illegal?do not use x 1 1 x x x illegal?do not use
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-20 mindspeed technologies ? 28250-dsh-002-c 0x4d?corrcnt (corrected hec error counter) the corrcnt counter tracks the nu mber of corrected hec errors. 0x08?cval (cell valida tion control register) the cval register controls the validation of incoming cells to be received acr oss the utopia interface. bit default name description 7 x corrcnt[7] corrected hec error counter bit 7 (msb). 6 x corrcnt[6] corrected hec error counter bit 6. 5 x corrcnt[5] corrected hec error counter bit 5. 4 x corrcnt[4] corrected hec error counter bit 4. 3 x corrcnt[3] corrected hec error counter bit 3. 2 x corrcnt[2] corrected hec error counter bit 2. 1 x corrcnt[1] corrected hec error counter bit 1. 0 x corrcnt[0] corrected hec error counter bit 0 (lsb). bit default name description 7 0 rejhdr when written to a logic 1, this bit enables the reject header function. when enabled, cells with matching headers are rejected and all others are accepted. when written to 0, cells with headers matching the rx hdrx/rxmskx definition are accepted. 6 1 delidle when written to a logic 1, this bit enables the deletion of idle cells. when enabled, cells matching the rxid l/idlmsk definition ar e deleted from the received cell stream. when written to 0, idle cells are included in the received stream. 5 1 enrxcellscr when written to a logic 1, this bit enables the x 43 +1 cell scrambler in the cell receiver. 4 1 enrxcos when written to a logic 1, this bit enables the receiver hec coset. 3 0 enhdrcorr when written to a logi c 1, this bit enables the hec correction state machine. when written to 0, only hec erro r detection is performed. 2 0 dishecchk when written to a l ogic 1, this bit disa bles hec checking. when disabled, hec checking is not performed as a cell validation criteria. 1 0 discellrcvr when written to a logi c 1, this bit disables the cell receiver. when disabled, all cell reception is disabled on the next cell bo undary. when written to 0, cell reception begins or resumes on the next cell bounda ry. (see also utopdis (bit 5) in the 0x0b?utop2 register, on page 4-25.) 0 0 dislocd when written to a logic 1, this bit disables loss of cell delinea tion. when disabled, cells are passed to the utopia port even if cell delineation has not been found. when written to 0, cells are passed to the utop ia port only while cell alignment has been achieved.
cx28250 4.0 registers atm physical interface (phy) devices 4.1 registers 28250-dsh-002-c mindspeed technologies ? 4-21 0x3a?enaps (aps interrupt mask control register) the enaps register controls which of the interrupts listed in the apsint register (0x42) appear on the mint* pin, provided that enapsint (bit 2) in the ensumint register (0x34) is enabled, and enintpin (bit 6) in the gen register (0x00) is enabled. 0x39?encellr (receive cell in terrupt mask control register) the encellr register controls which of the interrupts listed in the rxcell int register (0x41) appear on the mint* pin, provided that enrxcellint (bit 1) in the ensu mint register (0x34) is enab led, and enintpin (bit 6) in the gen register (0x00) is enabled. bit default name description 7 0 ? reserved, set to 0. 6 0 ? reserved, set to 0. 5 0 ? reserved, set to 0. 4 1 enpsbf when written to a logic 1, this bit enables the protection switch byte failure (psbf) interrupt. 3 0 enb3fail when written to a logic 1, this bit enables the b3 failure interrupt. 2 0 enb3degrade when written to a logic 1, th is bit enables the b3 degrade interrupt. 1 1 ensigfail when written to a logic 1, this bit enables the signal fa ilure (sf) interrupt. 0 1 ensigdegrade when written to a logic 1, this bit enables the signal degrade (sd) interrupt. bit default name description 7 1 enlocd when written to a logic 1, this bit enables a loss of ce ll delineation interrupt. when enabled, the interrupt appears on the mint* pin for the locd interrupt indication bit. 6 1 enhecdet when written to a logi c 1, this bit enables a hec error detected interrupt. when enabled, the interrupt appears on the mint* pin for the hecdet in terrupt indication bit. 5 1 enheccorr when written to a l ogic 1, this bit enables a hec error corrected interrupt. when enabled, the interrupt appears on the mint * pin for the heccorr interrupt indication bit. 4 0 ? reserved, set to 0. 3 1 encellrcvd when written to a logic 1, this bit enables a cell received interrupt. when enabled, the interrupt appears on the mint* pin for the cellrcvd interrupt indication bit. 2 1 enidlercvd when written to a logi c 1, this bit enables an idle cell received interrupt. when enabled, the interrupt appears on the mint* pin for the idlercvd interrupt indication bit. 1 1 ennonmatch when written to a l ogic 1, this bit enables a non- matching cell rece ived interrupt. when enabled, the interrupt appears on the mint* pin for the nonmatch interrupt indication bit. 0 1 ennonzergfc when written to a l ogic 1, this bit enables a non- 0 gfc received interrupt. when enabled, the interrupt appears on the mint* pin for the nonzergfc interrupt indication bit.
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-22 mindspeed technologies ? 28250-dsh-002-c 0x38?encellt (transmit cell in terrupt mask cont rol register) the encellt register controls which of the interrupts listed in the txcelli nt register (0x40) appear on the mint* pin, provided that entxcellint (bit 0) in the ensu mint register (0x34) is enabled, and enintpin (bit 6) in the gen register (0x00) is enabled. 0x6e?enlfout (enable line fail output) this register controls which events wi ll cause the lfout pin to be asserted: bit default name description 7 1 enparerr when written to a logic 1, this bit enab les the parity error inte rrupt. when enabled, the interrupt appears on the mint* pin for the parerr interrupt indication bit. 6 1 ensocerr when written to a logic 1, this bit en ables the start of cell alignment error interrupt. when enabled, the interrupt appears on the mint* pin for the socerr interrupt indication bit. 5 1 entxovfl when written to a logic 1, this bit enab les the transmit fifo overflow interrupt. when enabled, the interrupt appears on the mint* pi n for the txovfl interrupt indication bit. 4 1 enrxovfl when written to a logic 1, this bit en ables the receive fifo overflow interrupt. when enabled, the interrupt appears on the mint* pin for the rxovfl in terrupt indication bit. 3 1 encellsent when written to a logic 1, this bit enables the cell sent interrupt. when enabled, the interrupt appears on the mint* pin for the cellsent interrupt indication bit. 2 0 ? reserved, set to 0. 1 0 ? reserved, set to 0. 0 0 ? reserved, set to 0. bit default name description 7 0 los when enabled, assertion of los status bit will cause th e lfout pin to be asserted. 6 1 lol when enabled, assertion of lol status bit will cause th e lfout pin to be asserted. 5 0 oof when enabled, assertion of oof status bit will cause th e lfout pin to be asserted. 4 0 lof when enabled, assertion of lof status bit will cause the lfout pin to be asserted. 3 0 ais-l when enabled, assertion of ais-l status bit will cause the lfout pin to be asserted. 2 0 ais-p when enabled, assertion of ais-p status bit will cause the lfout pin to be asserted. 1 0 lop-p when enabled, assertion of lop-p status bit will cause the lfout pin to be asserted. 0 0 locd when enabled, assertion of locd status bit will cause the lfout pin to be asserted.
cx28250 4.0 registers atm physical interface (phy) devices 4.1 registers 28250-dsh-002-c mindspeed technologies ? 4-23 0x36?enlin (receive line interrupt mask control register) the enlin register controls which of the interrupts listed in the linint register (0x3e) appear on the mint* pin, provided that enlinint (bit 6) in the ensumint register (0x34) is enabled, and enintpin (bit 6) in the gen register (0x00) is enabled. 0x6f?enpfout (enable path fail output) this register controls which events wi ll cause the pfout pin to be asserted: bit default name description 7 1 enlop when written to a logic 1, this bit enables the lop interrupt. 6 1 enk1k2 when written to a logic 1, th is bit enables the k1k2 interrupt. 5 1 enais-l when written to a logic 1, this bit enables the ais-l interrupt. 4 1 enrdi-l when written to a logic 1, this bit enables the rdi-l interrupt. 3 1 enb2err when written to a logic 1, this bit enables the b2 error interrupt. 2 1 rei-l when written to a logic 1, this bit enables the rei-l error interrupt. 1 1 zint when written to a logi c 1, this bit enables the z0 1 , z0 2 , or z2 interrupts. 0 1 ens1intr when written to a l ogic 1, this bit enables the s1 byte change interrupt. bit default name description 7 0 los when enabled, assertion of los status bit will cause th e pfout pin to be asserted. 6 0 lol when enabled, assertion of lol status bit will cause th e pfout pin to be asserted. 5 0 oof when enabled, assertion of oof status bit will cause th e pfout pin to be asserted. 4 0 lof when enabled, assertion of lof status bit will cause th e pfout pin to be asserted. 3 0 ais-l when enabled, assertion of ais-l status bit will cause the pfout pin to be asserted. 2 0 ais-p when enabled, assertion of ais-p status bit will cause the pfout pin to be asserted. 1 0 lop-p when enabled, assertion of lop-p status bit will cause the pfout pin to be asserted. 0 0 locd when enabled, assertion of locd status bit will cause the pfout pin to be asserted.
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-24 mindspeed technologies ? 28250-dsh-002-c 0x37?enpth (receive path in terrupt mask control register) the enpth register controls which of the interrupts listed in the pthint register (0x3f) appear on the mint* pin, provided that enpthint (bit 5) in the ensumint re gister (0x34) is enabled, and enintpin (bit 6) in the gen register (0x00) is enabled. 0x35?ensec (receive section in terrupt mask control register) the ensec register controls which of the interrupts list ed in the secint register (0x3d) appear on the mint* pin, provided that ensecint (bit 7) in the ensumint re gister (0x34) is enabled, an d enintpin (bit 6) in the gen register (0x00) is enabled. bit default name description 7 1 enais-p when written to a logic 1, this bit enables the ais-p interrupt. 6 1 enrdi-p when written to a logic 1, this bit enables the rdi-p interrupt. 5 1 enb3err when written to a logic 1, this bit enables the b3 error interrupt. 4 1 enrei-p when written to a logic 1, this bit enables the rei-p interrupt. 3 1 enplm-p when written to a logic 1, this bit enables the payload label mismatch-path (plm-p) interrupt. 2 1 enuneq-p when written to a logic 1, this bi t enables the sts path unequipped (uneq-p) interrupt. 1 1 enpthtrace when written to a logic 1, th is bit enables the path trace interrupt. 0 1 enhancerdi (-23) when written to a logic 1, this bi t enables the enhanced rd i function. when written to 0, reduced rdi functionalit y detection is performed. ? (-26) reserved, write to 0. bit default name description 7 1 ensigdet when written to a logic 1, this bit enables the signal detect interrupt. 6 1 enlol when written to a l ogic 1, this bit enables the loss of lock interrupt. 5 1 enlos when written to a logi c 1, this bit enables the loss of signal interrupt. 4 1 enoof when written to a l ogic 1, this bit enables the out of frame interrupt. 3 1 enlof when written to a logi c 1, this bit enables th e loss of frame interrupt. 2 1 enb1err when written to a logi c 1, this bit enables the section bip error interrupt. 1 1 ensectrace when written to a logic 1, this bit enables the section trace interrupt. 0 0 disrxscr when written to a logic 1, this bit disables the receive frame scrambler. when written to 0, scrambling is enabled.
cx28250 4.0 registers atm physical interface (phy) devices 4.1 registers 28250-dsh-002-c mindspeed technologies ? 4-25 0x34?ensumint (summary inte rrupt mask control register) the ensumint register determines which of the interrupts listed in register 0x3c (sumint) are observed on the mint*. 0x06?errins (error insert ion control register) the errins register controls error in sertion into various octets for diagnostic purposes. these bits are cleared automatically by internal circuitry after the indicated error insertion has taken pl ace. clearing takes precedence over a simultaneous write operation to this register. bit default name description 7 1 ensecint when written to a logic 1, this bit enab les the sonet section overhead interrupt. it is a global disable for the son et section interrupt sources. 6 1 enlinint when written to a logi c 1, this bit enables the sonet line overhead interrupt. it is a global disable for the son et line interrupt sources. 5 1 enpthint when written to a logic 1, this bit enab les the sonet path overhe ad interrupt. it is a global disable for the son et path interrupt sources. 4 1 enonesecint when written to a l ogic 1, this bit enables the one second interrupt generated by the onesecin pin to appear on the mint* output pin. 3 0 ? reserved, set to 0. 2 1 enapsint when written to a logic 1, this bit en ables the aps interrupt. it is a global disable for the aps interrupt sources. 1 1 enrxcellint when written to a logi c 1, this bit enables the receive cell interrupt. it is a global disable for the rxcellint interrupt sources. 0 1 entxcellint when written to a logic 1, this bit en ables the transmit cell interrupt. it is a global disable for the txcelli nt interrupt sources. bit default name description 7 0 insfrerr when written to a logic 1, this bit in verts the a1 bytes for one transmit frame. when written to 0, the a1 bytes are not inverted. 6 0 insb1err this bit xors the b1 bip calculation with the errpat register (0x07) value and inserts the new value into the transmitted b1 byte for one transmit frame only. 5 0 insb2err1 this bit xors the b2-1 bip calculati on with the errpat register (0x07) value and inserts the new value into the transmitted b2-1 byte for one transmit frame only. 4 0 insb2err2 this bit xors the b2-2 bip calculati on with the errpat register (0x07) value and inserts the new value into the transmitted b2-2 byte for one transmit frame only. 3 0 insb2err3 this bit xors the b2-3 bip calculati on with the errpat register (0x07) value and inserts the new value into the transmitted b2-3 byte for one transmit frame only. 2 0 insb3err this bit xors the b3 bip calculation with the errpat register (0x07) value and inserts the new value into the transmitted b3 byte for one transmit frame only. 1 0 inshecerr this bit xors the hec byte with the er rpat register (0x07) value and inserts the new value into the transmitted hec byte for one transmit cell only. 0 0 enonesdet when written to a logic 1, this bit al lows the cx28250 to detect an ?all one? pattern on the receive interface and declare los.
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-26 mindspeed technologies ? 28250-dsh-002-c 0x07?errpat (error patt ern control register) the errpat register provides the error pattern for the er ror insertion functions listed in the errins register. each bit in the error pattern register is xored with the corresponding bit of the octet to be errored. bit default name description 7 0 errpat[7] error pattern bit 7. 6 0 errpat[6] error pattern bit 6. 5 0 errpat[5] error pattern bit 5. 4 0 errpat[4] error pattern bit 4. 3 0 errpat[3] error pattern bit 3. 2 0 errpat[2] error pattern bit 2. 1 0 errpat[1] error pattern bit 1. 0 0 errpat[0] error pattern bit 0.
cx28250 4.0 registers atm physical interface (phy) devices 4.1 registers 28250-dsh-002-c mindspeed technologies ? 4-27 0x00?gen (general control register) the gen register controls the receiver hold input pin, one-second latch enables, block mode error counting, status pin selection, and device reset. bit default name description 7 0 ? reserved, set to 0. 6 0 enintpin when written to a logic 1, this bit enables the mint* pin. 5 0 enstatlat when written to a logic 1, this bi t enables 1-second status latching. when one-second status latching is enabled, the registers indicated in table 4-1 , footnote 2 is updated with new status information af ter a rising edge of the onesec in pin. status information in these registers is update d continuously if one -second status latc hing is disabled. 4 0 encntrlat when written to a logic 1, this bit enables 1-second counter latching. when one-second counter latching is enable d, the registers indicated in table 4-1 , footnote 3 is updated with new c ount information a fter a rising edge of th e onesecin pin. count information in these registers is updated continuously if one-second counter latching is disabled. 3 0 blkmode when written to a logic 1, this bit enables the block error m ode operation for bip and rei counters. when this mode is enabled, a received bip (section, line, and path) or rei (line and path) error increments the c ounter value by one c ount for each errored frame. there are 5 count ers; b1cnt, b2cnt, b3cnt, lfcn t and pfcnt. when this bit is written to 0, the actual number of bip or re i errors received is added to the counter value. 2 0 user-defined mode when written to a logic 1, this bit enables the status ou tput pin mode. when this mode is enabled, the statout[7:0] pins reflect the values in the outstat control register (0x02). when this bit is written to 0, output status for lo s, oof, lop, ais-l, rdi-l, ais-p, rdi-p and locd appears on th e statout[7:0] pins or data link outputs. note: this feature is overridden by the data link enables: entxsecdl (bit 6) in the txsec register (0x0c), entxlindl (bit 4) in the txlin register (0x0d), enrx- secdl (bit 0), and enrxlindl (bit 1) in the rxlin regi ster (0x46). see section 2.3.3.4 . 1 0 lgcrst when written to a logic 1, this bit init iates a logic reset. when the device resets, all internal state machines are reset, but all registers (0x00 to 0x7f) listed as ?type: w/r? in table 4-1 are unaltered. 0 0 mstrst when written to a logic 1, this bit in itiates a device master reset. when the device resets, internal state machines are held in reset, all registers (0x00 to 0x7f) assume their default values a nd bits 1-7 in this register ar e overwritten with their default values.
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-28 mindspeed technologies ? 28250-dsh-002-c 0x30?idlmsk1 (receive idle cell mask control register 1) the idlmsk1 register contains the first byte of the rece ive idle cell mask. it modifies the atm cell screen in the rxidl1 register. setting a bit in the mask register causes the corresponding bi t in the received atm idle cell header to be disregarded for screening. for exampl e, setting idlmsk1, bit 0 to 1, causes cells to be accepted as atm idle cells with either 1 or 0 in the octet 1, bit 0 position. this header consists of 32 bits divided among four registers. 0x31?idlmsk2 (receive idle cell mask control register 2) the idlmsk2 register contains the seco nd byte of the receive idle cell mask. it modifies the atm cell screen in the rxidl1 register. setting a bit in the mask register causes the corres ponding bit in the received atm idle cell header to be disregarded for screening. for exampl e, setting idlmsk1, bit 0 to 1, causes cells to be accepted as atm idle cells with either 1 or 0 in the octet 1, bit 0 position. this header consists of 32 bits divided among four registers. bit default name description 7 0 idlmsk1[7] these bits hold the re ceive idle cell header mask for octet 1 of the incoming cell. 6 0 idlmsk1[6] 5 0 idlmsk1[5] 4 0 idlmsk1[4] 3 0 idlmsk1[3] 2 0 idlmsk1[2] 1 0 idlmsk1[1] 0 0 idlmsk1[0] bit default name description 7 0 idlmsk2[7] these bits hold the re ceive idle cell header mask for octet 2 of the incoming cell. 6 0 idlmsk2[6] 5 0 idlmsk2[5] 4 0 idlmsk2[4] 3 0 idlmsk2[3] 2 0 idlmsk2[2] 1 0 idlmsk2[1] 0 0 idlmsk2[0]
cx28250 4.0 registers atm physical interface (phy) devices 4.1 registers 28250-dsh-002-c mindspeed technologies ? 4-29 0x32?idlmsk3 (receive idle cell mask control register 3) the idlmsk3 register contains the third byte of the rece ive idle cell mask. it modifies the atm cell screen in the receive cell header register. setting a bit in the ma sk register causes the corresponding bit in the received atm cell header to be disregarded for screening. for ex ample, setting rxmsk1, bit 0 to 1, causes atm cells to be accepted with either 1 or 0 in the octet 1, bit 0 position. combinations of receive header mask bits can select groups of atm vpi/vcis for reception. this mask consists of 32 bits divided among four registers. 0x33?idlmsk4 (receive idle cell mask control register 4) the idlmsk4 register contains the four th byte of the receive idle cell ma sk. it modifies the atm cell screen in the receive cell header register. setting a bit in the mask register causes the corresponding bit in the received atm cell header to be disregarded for screenin g. for example, setting rxmsk1, bit 0 to 1, causes atm cells to be accepted with either 1 or 0 in the octet 1, bit 0 position. combinations of receive header mask bits can select groups of atm vpi/vc is for reception. this mask consists of 32 bits divided among four registers. bit default name description 7 0 idlmsk3[7] these bits hold the re ceive idle cell header mask for octet 3 of the incoming cell. 6 0 idlmsk3[6] 5 0 idlmsk3[5] 4 0 idlmsk3[4] 3 0 idlmsk3[3] 2 0 idlmsk3[2] 1 0 idlmsk3[1] 0 0 idlmsk3[0] bit default name description 7 0 idlmsk4[7] these bits hold the re ceive idle cell header mask for octet 4 of the incoming cell. 6 0 idlmsk4[6] 5 0 idlmsk4[5] 4 0 idlmsk4[4] 3 0 idlmsk4[3] 2 0 idlmsk4[2] 1 0 idlmsk4[1] 0 0 idlmsk4[0]
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-30 mindspeed technologies ? 28250-dsh-002-c 0x05?idlpay (transmit idle ce ll payload control register) the idlpay register contains the transmit idle cell payload. 0x72?inlk (in lock coefficient register) the value in this regist er configures the pll. 0x5a?lfcnth (line rei e rror counter [high byte]) the lfcnth counter tracks the number of line rei errors. bit default name description 7 0 idlpay[7] these bits hold the transmit idle cell payload values for outgoing idle cells. 61 idlpay[6] 51 idlpay[5] 40 idlpay[4] 31 idlpay[3] 20 idlpay[2] 11 idlpay[1] 00 idlpay[0] bit default name description 7?0 0x15 (-26) 0x40 (-23) ? sets the window threshold for the phase lock loop once the loop has acquired lock. this register should be reprogram med to 0x15 in the -23 version. bit default name description 7 0 ? reserved, set to 0. 6 0 ? reserved, set to 0. 5 0 ? reserved, set to 0. 4 0 ? reserved, set to 0. 3 0 ? reserved, set to 0. 2 0 ? reserved, set to 0. 1 x lfcnt[17] line rei error counter bit 17 (msb). 0 x lfcnt[16] line rei error counter bit 16.
cx28250 4.0 registers atm physical interface (phy) devices 4.1 registers 28250-dsh-002-c mindspeed technologies ? 4-31 0x58?lfcntl (line rei er ror counter [low byte]) the lfcntl counter tracks the number of line rei errors. 0x59?lfcntm (line rei e rror counter [mid byte]) the lfcntm counter tracks the number of line rei errors. bit default name description 7 x lfcnt[7] line rei error counter bit 7. 6 x lfcnt[6] line rei error counter bit 6. 5 x lfcnt[5] line rei error counter bit 5. 4 x lfcnt[4] line rei error counter bit 4. 3 x lfcnt[3] line rei error counter bit 3. 2 x lfcnt[2] line rei error counter bit 2. 1 x lfcnt[1] line rei error counter bit 1. 0 x lfcnt[0] line rei error counter bit 0 (lsb). bit default name description 7 x lfcnt[15] line rei error counter bit 15. 6 x lfcnt[14] line rei error counter bit 14. 5 x lfcnt[13] line rei error counter bit 13. 4 x lfcnt[12] line rei error counter bit 12. 3 x lfcnt[11] line rei error counter bit 11. 2 x lfcnt[10] line rei error counter bit 10. 1 x lfcnt[9] line rei error counter bit 9. 0 x lfcnt[8] line rei error counter bit 8.
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-32 mindspeed technologies ? 28250-dsh-002-c 0x3e?linint (receive line interru pt indication status register) the linint register indicates that a change of status has occurred wi thin its affiliated status signals. 0x4c?locdcnt (loc d event counter) the locdcnt counter tracks th e number of locd events. bit default name description 7x lopint (1) when a logic 1 is read, this bit indi cates that a lop interrupt has occurred. 6x k1k2int (2) when a logic 1 is read, this bit indica tes that a k1/k2 interrupt has occurred. 5x ais-lint (1) when a logic 1 is read, this bit indica tes that a ais-l interrupt has occurred. 4x rdi-lint (1) when a logic 1 is read, this bit indica tes that a rdi-l interrupt has occurred. 3x b2errint (2) when a logic 1 is read, this bit indicates that a b2 error interrupt has occurred. 2x rei-lint (2) when a logic 1 is read, this bit indica tes that a rei-l interrupt has occurred. 1 0 zint when a logic 1 is read, this bit indicates that a z0 1 , z0 2 , or z2 interrupt has occurred. 0x s1intr 2 when a logic 1 is read, this bit indicate s that an s1 byte change interrupt has occurred. note(s): (1) dual event?either a 0 ?> 1 or a 1 ?> 0 transition on the correspondi ng status bit causes this inte rrupt to occur provided that this interrupt has been enabled by the corresponding enable bit. reading the in terrupt register clears the interrupt. (2) single event?a 0 ?> 1 transition on the correspon ding status bit causes this interrupt to occur provided that this interrupt ha s been enabled by the corresponding en able bit. reading the interrupt register clears the interrupt. bit default name description 7 x locdcnt[7] locd even t counter bit 7 (msb). 6 x locdcnt[6] locd ev ent counter bit 6. 5 x locdcnt[5] locd ev ent counter bit 5. 4 x locdcnt[4] locd ev ent counter bit 4. 3 x locdcnt[3] locd ev ent counter bit 3. 2 x locdcnt[2] locd ev ent counter bit 2. 1 x locdcnt[1] locd ev ent counter bit 1. 0 x locdcnt[0] locd even t counter bit 0 (lsb).
cx28250 4.0 registers atm physical interface (phy) devices 4.1 registers 28250-dsh-002-c mindspeed technologies ? 4-33 0x5f?noncnth (non-matching cell counter [high byte]) the noncnth counter tracks the number of non-matching cells. 0x5e?noncntl (non-matching cell counter [low byte]) the noncntl counter tracks the number of non-matching cells. bit default name description 7 x noncnt[15] non-matching ce ll counter bit 15 (msb). 6 x noncnt[14] non-matching cell counter bit 14. 5 x noncnt[13] non-matching cell counter bit 13. 4 x noncnt[12] non-matching cell counter bit 12. 3 x noncnt[11] non-matching cell counter bit 11. 2 x noncnt[10] non-matching cell counter bit 10. 1 x noncnt[9] non-matching cell counter bit 9. 0 x noncnt[8] non-matching cell counter bit 8. bit default name description 7 x noncnt[7] non-matching cell counter bit 7. 6 x noncnt[6] non-matching cell counter bit 6. 5 x noncnt[5] non-matching cell counter bit 5. 4 x noncnt[4] non-matching cell counter bit 4. 3 x noncnt[3] non-matching cell counter bit 3. 2 x noncnt[2] non-matching cell counter bit 2. 1 x noncnt[1] non-matching cell counter bit 1. 0 x noncnt[0] non-matching ce ll counter bit 0 (lsb).
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-34 mindspeed technologies ? 28250-dsh-002-c 0x4f?oofcnt (oof event counter) the oofcnt counter tracks the number oof events. 0x73?outlk (out of lock coefficient register) this register sets the coefficient for the pll when the loop is out of lock. 0x02?outstat (output pin control register) the outstat register contains the values that are reflected on the statout[7:0] pins when register 0x00 (gen), bit 2 is written to 1, en abling status output pin mode. bit default name description 7 x oofcnt[7] oof event counter bit 7 (msb). 6 x oofcnt[6] oof event counter bit 6. 5 x oofcnt[5] oof event counter bit 5. 4 x oofcnt[4] oof event counter bit 4. 3 x oofcnt[3] oof event counter bit 3. 2 x oofcnt[2] oof event counter bit 2. 1 x oofcnt[1] oof event counter bit 1. 0 x oofcnt[0] oof event counter bit 0 (lsb). bit default name description 7?0 0x08 (-26) 0x15 (-23) ? this is a control coefficient for the pll during the acquisition phase. this register should be reprogrammed to 0x08 in the -23 version. bit default name description 7 0 outstat[7] value to be reflected to statout[7] pin. 6 0 outstat[6] value to be reflected to statout[6] pin. 5 0 outstat[5] value to be reflected to statout[5] pin. 4 0 outstat[4] value to be reflected to statout[4] pin. 3 0 outstat[3] value to be reflected to statout[3] pin. 2 0 outstat[2] value to be reflected to statout[2] pin. 1 0 outstat[1] value to be reflected to statout[1] pin. 0 0 outstat[0] value to be reflected to statout[0] pin.
cx28250 4.0 registers atm physical interface (phy) devices 4.1 registers 28250-dsh-002-c mindspeed technologies ? 4-35 0x5d?pfcnth (path rei error counter [high byte]) the pfcnth counter tracks the number of path rei errors. 0x5c?pfcntl (path rei error counter [low byte]) the pfcntl counter tracks the nu mber of path rei errors. bit default name description 7 x pfcnt[15] path rei error counter bit 15 (msb). 6 x pfcnt[14] path rei error counter bit 14. 5 x pfcnt[13] path rei error counter bit 13. 4 x pfcnt[12] path rei error counter bit 12. 3 x pfcnt[11] path rei error counter bit 11. 2 x pfcnt[10] path rei error counter bit 10. 1 x pfcnt[9] path rei error counter bit 9. 0 x pfcnt[8] path rei error counter bit 8. bit default name description 7 x pfcnt[7] path rei error counter bit 7. 6 x pfcnt[6] path rei error counter bit 6. 5 x pfcnt[5] path rei error counter bit 5. 4 x pfcnt[4] path rei error counter bit 4. 3 x pfcnt[3] path rei error counter bit 3. 2 x pfcnt[2] path rei error counter bit 2. 1 x pfcnt[1] path rei error counter bit 1. 0 x pfcnt[0] path rei error counter bit 0 (lsb).
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-36 mindspeed technologies ? 28250-dsh-002-c 0x3f?pthint (receive path interru pt indication status register) the pthint register indicates that a change of status has occurred wi thin its affiliated status signals. 0x4a?rxaps (receive aps status register) the rxaps register contains status in formation for the receiver aps functions. bit default name description 7x ais-pint (1) when a logic 1 is read, this bit indica tes that an ais-p in terrupt has occurred. 6x rdi-pint (2) when a logic 1 is read, this bit indicate s that an rdi-p interrupt has occurred. 5x b3errint (2) when a logic 1 is read, this bit indicate s that a b3 error interrupt has occurred. 4x rei-pint (2) when a logic 1 is read, this bit indica tes that a rei-p interrupt has occurred. 3x plm-pint (1) when a logic 1 is read, this bit indicate s that a plm-p interrupt has occurred. this means that the contents of path overhead byte c2 is not e qual to 13 hex for atm mapping. 2x uneq-pint (1) when a logic 1 is read, this bit indicates that an uneq-p interr upt has occurred. this means that the contents of path overhead byte c2 is equal to 0. 1x pthtraceint (2) when a logic 1 is read, this bit indicate s that a path trace interrupt has occurred. 0 0 ? reserved, set to 0. note(s): (1) dual event?a 0 ?> 1 and 1?> 0 transition on the corresponding status bit causes this in terrupt to occur provided that this interrupt has been enabled by the corre sponding enable bit. reading the inte rrupt register clears the interrupt. (2) single event?a 0 ?> 1 transition on the corresp onding status bit causes this interrupt to occur provid ed that this interrupt ha s been enabled by the corresponding en able bit. reading the interrupt register clears the interrupt. bit default name description 7 0 ? reserved, set to 0. 6 0 ? reserved, set to 0. 5 0 ? reserved, set to 0. 4x psbf (1)(2) when a logic 1 is read, this bit indicates a protection byte switching failure (psbf). 30 b3fail (1) when a logic 1 is read, this bit indicates that the b3 error count exceeded the programmed threshold. this bit is only valid for the CX28250-26 and above. 20 b3degrade (1) when a logic 1 is read, this bit indicates that the b3 error count exceeded the programmed threshold. this bit is only valid for the CX28250-26 and above. 1x sigfail (1) when a logic 1 is read, this bit indicates a signal failure (sf). 0x sigdegrade (1) when a logic 1 is read, this bit indicates a signal degradation (sd). note(s): (1) this status reflects the current state of the circuit. (2) for the cx28250-23, the psbf bit is cleare d upon reading. for the CX28250-26, the psbf bit reflects the cu rrent state of the circuit.
cx28250 4.0 registers atm physical interface (phy) devices 4.1 registers 28250-dsh-002-c mindspeed technologies ? 4-37 0x18?rxc2 (receive c2 ov erhead status register) the rxc2 register provides c2 overhead status. this byte is allocated to identify the construction and content of the sts-level spe, and for sts path defect indicatio n (pdi-p). pdi-p indicates to downstream equipment that there is a payload defect. 0x49?rxcell (receive ce ll status register) the rxcell register contains status for the cell alignment, header error co rrection, and he ader screening functions in the cell receiver. bit default name description 7 x rxc2[1] receive value for c2 overhead octet?bit 1 (msb) 6 x rxc2[2] receive value for c2 overhead octet?bit 2 5 x rxc2[3] receive value for c2 overhead octet?bit 3 4 x rxc2[4] receive value for c2 overhead octet?bit 4 3 x rxc2[5] receive value for c2 overhead octet?bit 5 2 x rxc2[6] receive value for c2 overhead octet?bit 6 1 x rxc2[7] receive value for c2 overhead octet?bit 7 0 x rxc2[8] receive value for c2 overhead octet?bit 8 (lsb) bit default name description 7x locd (1) when a logic 1 is read, this bit indicate s that there is a loss of cell delineation. 6x hecdet (2) when a logic 1 is read, this bit indicates that an uncorrected hec error was detected. 5x heccorr (2) when a logic 1 is read, this bit indi cates that a hec error was corrected. 4 0 ? reserved, set to 0. 3x cellrcvd (2) when a logic 1 is read, this bit indicates that a cell with a header matching the receive header value and mask criteria was received. 2x idlercvd (2) when a logic 1 is read, this bit indicates that a cell with a header matching the receive idle cell header value and mask criteria was received. 1x nonmatch (2) when a logic 1 is read, this bit indicates that a cell with a header not matching either the receive cell or idle ce ll criteria was received. 0x nonzergfc (2) when a logic 1 is read, this bit indicates that a cell with a non-zero gfc field in the header was received. note(s): (1) this status reflects the current state of the circuit. (2) this status shows an event that has occurred since the register was last read.
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-38 mindspeed technologies ? 28250-dsh-002-c 0x41?rxcellint (receive cell interrupt indicati on status register) the rxcellint register indicat es that a change of status has occurred within its affiliated status signals. 0x66?rxcnth (received ce ll counter [high byte]) the rxcnth counter tracks the number of received cells. bit default name description 7x locdint (1) when a logic 1 is read, this bit indicates that a loss of cell de lineation ha s occurred. 6x hecdetint (2) when a logic 1 is read, this bit indica tes that a hec error has been detected. 5x heccorrint (2) when a logic 1 is read, this bit indicates that a hec error has been corrected. 4 0 ? reserved, set to 0. 3x cellrcvdint (2) when a logic 1 is read, this bit indicates that a cell received in terrupt has occurred. 2x idlercvdint (2) when a logic 1 is read, this bit indicates that an idle cell received interrupt has occurred. 1x nonmatchint (2) when a logic 1 is read, this bit indicates that a non-matching cell received interrupt has occurred. 0x nonzergfcint (2) when a logic 1 is read, this bit indicates that a non-zero gfc received interrupt has occurred. note(s): (1) dual event?either a 0?> 1 or a 1 ?> 0 transition on the corresponding status bit causes this interr upt to occur provided that this interrupt has been enabled by the corresponding enable bit. reading the in terrupt register clears the interrupt. (2) single event?a 0?> 1 transition on the correspondi ng status bit causes this interrupt to occur provided that this interrupt has been enabled by the corresponding en able bit. reading the interrupt register clears the interrupt. bit default name description 7 0 ? reserved, set to 0. 6 0 ? reserved, set to 0. 5 0 ? reserved, set to 0. 4 0 ? reserved, set to 0. 3 0 ? reserved, set to 0. 2 x rxcnt[18] received cell counter bit 18 (msb). 1 x rxcnt[17] received cell counter bit 17. 0 x rxcnt[16] received cell counter bit 16.
cx28250 4.0 registers atm physical interface (phy) devices 4.1 registers 28250-dsh-002-c mindspeed technologies ? 4-39 0x64?rxcntl (received ce ll counter [low byte]) the rxcntl counter tracks the number of received cells. 0x65?rxcntm (received cell counter [mid byte]) the rxcntm register tracks th e number of received cells. bit default name description 7 x rxcnt[7] received cell counter bit 7. 6 x rxcnt[6] received cell counter bit 6. 5 x rxcnt[5] received cell counter bit 5. 4 x rxcnt[4] received cell counter bit 4. 3 x rxcnt[3] received cell counter bit 3. 2 x rxcnt[2] received cell counter bit 2. 1 x rxcnt[1] received cell counter bit 1. 0 x rxcnt[0] received cell counter bit 0 (lsb). bit default name description 7 x rxcnt[15] received cell counter bit 15. 6 x rxcnt[14] received cell counter bit 14. 5 x rxcnt[13] received cell counter bit 13. 4 x rxcnt[12] received cell counter bit 12. 3 x rxcnt[11] received cell counter bit 11. 2 x rxcnt[10] received cell counter bit 10. 1 x rxcnt[9] received cell counter bit 9. 0 x rxcnt[8] received cell counter bit 8.
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-40 mindspeed technologies ? 28250-dsh-002-c 0x19?rxg1 (receive g1 ov erhead status register) the rxg1 register is used to provide path st atus information to the originating terminal. 0x24?rxhdr1 (receive cell header contro l register 1) the rxhdr1 register contains the first byte of the rece ive cell header. the header values direct atm cells to the utopia port. if an incoming atm cell header matches the value in the header regi ster, the cell is directed to the utopia port. receive header mask registers furthe r qualify atm cell reception. this header consists of 32 bits divided among four registers. bit default name description 7 0 ? reserved, set to 0. 6 0 ? reserved, set to 0. 5 0 ? reserved, set to 0. 4 0 ? reserved, set to 0. 3 x rxrdi[5] received value of bit 5 of the g1 octet. 2 x rxrdi[6] received value of bit 6 of the g1 octet. 1 x rxrdi[7] received value of bit 7 of the g1 octet. 0 0 ? reserved, set to 0. bit default name description 7 0 rxhdr1[7] these bits hold th e receive header values for octet 1 of the incoming cell. 6 0 rxhdr1[6] 5 0 rxhdr1[5] 4 0 rxhdr1[4] 3 0 rxhdr1[3] 2 0 rxhdr1[2] 1 0 rxhdr1[1] 0 0 rxhdr1[0]
cx28250 4.0 registers atm physical interface (phy) devices 4.1 registers 28250-dsh-002-c mindspeed technologies ? 4-41 0x25?rxhdr2 (receive cell header contro l register 2) the rxhdr2 register contains the second byte of the re ceive cell header. the header values direct atm cells to the utopia port. if an incoming atm cell header matches the value in the header register, the cell is directed to the utopia port. receiv e header mask registers further qua lify atm cell reception. this header consists of 32 bits divided among four registers. 0x26?rxhdr3 (receive cell header contro l register 3) the rxhdr3 register contains the third byte of the rece ive cell header. the header values direct atm cells to the utopia port. if an incoming atm cell header matches the value in the header regi ster, the cell is directed to the utopia port. receive header mask registers furthe r qualify atm cell reception. this header consists of 32 bits divided among four registers. bit default name description 7 0 rxhdr2[7] these bits hold th e receive header values for octet 2 of the incoming cell. 6 0 rxhdr2[6] 5 0 rxhdr2[5] 4 0 rxhdr2[4] 3 0 rxhdr2[3] 2 0 rxhdr2[2] 1 0 rxhdr2[1] 0 0 rxhdr2[0] bit default name description 7 0 rxhdr3[7] these bits hold th e receive header values for octet 3 of the incoming cell. 6 0 rxhdr3[6] 5 0 rxhdr3[5] 4 0 rxhdr3[4] 3 0 rxhdr3[3] 2 0 rxhdr3[2] 1 0 rxhdr3[1] 0 0 rxhdr3[0]
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-42 mindspeed technologies ? 28250-dsh-002-c 0x27?rxhdr4 (receive cell header contro l register 4) the rxhdr4 register contains the four th byte of the receive cell header. the header values direct atm cells to the utopia port. if an incoming atm cell header matches the value in the header register, the cell is directed to the utopia port. receiv e header mask registers further qua lify atm cell reception. this header consists of 32 bits divided among four registers. 0x2c?rxidl1 (receive idle cell header control register 1) the rxidl1 register contains the firs t byte of the receive idle cell header. it defines atm idle cells for the cell receiver. idle cells are counted an d discarded from the received stream if delidle, bit 6 in the cval register (0x08), is set to 1. this header consists of 32 bits divided among four registers. bit default name description 7 0 rxhdr4[7] these bits hold the receive header values for octet 4 of the incoming cell. 6 0 rxhdr4[6] 5 0 rxhdr4[5] 4 0 rxhdr4[4] 3 0 rxhdr4[3] 2 0 rxhdr4[2] 1 0 rxhdr4[1] 0 0 rxhdr4[0] bit default name description 7 0 rxidl1[7] these bits hold the receive idle cell header for octet 1 of the incoming cell. 60 rxidl1[6] 50 rxidl1[5] 40 rxidl1[4] 30 rxidl1[3] 20 rxidl1[2] 10 rxidl1[1] 00 rxidl1[0]
cx28250 4.0 registers atm physical interface (phy) devices 4.1 registers 28250-dsh-002-c mindspeed technologies ? 4-43 0x2d?rxidl2 (receive idle cell header control register 2) the rxidl2 register contains the second byte of the recei ve idle cell header. it de fines atm idle cells for the cell receiver. idle cells are counted an d discarded from the received stream if delidle, bit 6 in the cval register (0x08), is set to 1. this header consists of 32 bits divided among four registers. 0x2e?rxidl3 (receive idle cell header control register 3) the rxidl3 register contains the thir d byte of the receive idle cell header. it defines atm idle cells for the cell receiver. idle cells are counted an d discarded from the received stream if delidle, bit 6 in the cval register (0x08), is set to 1. this header consists of 32 bits divided among four registers. bit default name description 7 0 rxidl2[7] these bits hold the receive idle cell header fo r octet 2 of the incoming cell. 60 rxidl2[6] 50 rxidl2[5] 40 rxidl2[4] 30 rxidl2[3] 20 rxidl2[2] 10 rxidl2[1] 00 rxidl2[0] bit default name description 7 0 rxidl3[7] these bits hold the receive idle cell header fo r octet 3 of the incoming cell. 60 rxidl3[6] 50 rxidl3[5] 40 rxidl3[4] 30 rxidl3[3] 20 rxidl3[2] 10 rxidl3[1] 00 rxidl3[0]
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-44 mindspeed technologies ? 28250-dsh-002-c 0x2f?rxidl4 (receive idle cell header control register 4) the rxidl4 register contains the fourth byte of the r eceive idle cell header. it defines atm idle cells for the cell receiver. idle cells are counted an d discarded from the received stream if delidle, bit 6 in the cval register (0x08), is set to 1. this header consists of 32 bits divided among four registers. 0x14?rxk1 (receive k1 ov erhead status register) the rxk1 register provides k1 overhead status. the k1 and k2 bytes are allocate d for automatic protection switching (aps) signaling between line level entities. th ese bytes are defined only for the first sts-1 of the sts-3c signal. bit default name description 7 0 rxidl4[7] these bits hold the receive idle cell header for octet 4 of the incoming cell. 60 rxidl4[6] 50 rxidl4[5] 40 rxidl4[4] 30 rxidl4[3] 20 rxidl4[2] 10 rxidl4[1] 01 rxidl4[0] bit default name description 7 x rxk1[1] receive value for k1 overhead octet?bit 1 (msb) 6 x rxk1[2] receive value for k1 overhead octet?bit 2 5 x rxk1[3] receive value for k1 overhead octet?bit 3 4 x rxk1[4] receive value for k1 overhead octet?bit 4 3 x rxk1[5] receive value for k1 overhead octet?bit 5 2 x rxk1[6] receive value for k1 overhead octet?bit 6 1 x rxk1[7] receive value for k1 overhead octet?bit 7 0 x rxk1[8] receive value for k1 overhead octet?bit 8 (lsb)
cx28250 4.0 registers atm physical interface (phy) devices 4.1 registers 28250-dsh-002-c mindspeed technologies ? 4-45 0x15?rxk2 (receive k2 ov erhead status register) the rxk2 register controls the k2 byte in the transport overhead. the k1 by te and bits 0?5 of the k2 byte are allocated for automatic protection switching (aps) sign aling between line level entities. these bytes are defined only for the first sts-1 of the sts-3c signal. bits 6?8 of the k2 byte are allocated for alarm indicat ion signal (ais) and remote defect indi cator (rdi). these bytes are defined only for the first sts-1 of the sts-3c signal. 0x46?rxlin (receive line overhead status register) the rxlin register contains status info rmation for the receiv er line overhead. bit default name description 7 x rxk2[1] receive value for k2 overhead octet?bit 1 (msb) 6 x rxk2[2] receive value for k2 overhead octet?bit 2 5 x rxk2[3] receive value for k2 overhead octet?bit 3 4 x rxk2[4] receive value for k2 overhead octet?bit 4 3 x rxk2[5] receive value for k2 overhead octet?bit 5 2 x rxk2[6] receive value for k2 overhead octet?bit 6 1 x rxk2[7] receive value for k2 overhead octet?bit 7 0 x rxk2[8] receive value for k2 overhead octet?bit 8 (lsb) bit default name description 7x lop (1) when a logic 1 is read, this bit indicate s that a loss of pointer condition exists. 6x k1k2 (2) when a logic 1 is read, this bit indicate s that an k1k2 value change was received. 5x ais-l (1) when a logic 1 is read, this bit indi cates that an ais- l condition exists. 4x rdi-l (1) when a logic 1 is read, this bit indicates that an rdi-l condition exists. 3x b2err (2) when a logic 1 is read, this bit indicates that a line bip error was received. 2x rei-l (2) when a logic 1 is read, this bit indicates that a rei-l error was received. 1 0 enrxlindl when written to a logic 1, this bit en ables the receive d4-12 bytes of the data link. 0 0 enrxsecdl when written to a logic 1, this bit enab les the receive d1/d2/d3 bytes of the data link. note(s): (1) this status reflects the current state of the circuit. (2) this status shows an event that has occurred since the register was last read.
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-46 mindspeed technologies ? 28250-dsh-002-c 0x28?rxmsk1 (receive cell mask control register 1) the rxmsk1 register contains the firs t byte of the receive cell mask. it modifies the atm cell screen in the receive cell header register. setting a bit in the mask register causes the correspo nding bit in the received atm cell header to be disregarded for screening. for ex ample, setting rxmsk1, bit 0 to 1, causes atm cells to be accepted with either 1 or 0 in the octet 1, bit 0 position. combinations of receive header mask bits can select groups of atm vpi/vcis for reception. this mask consists of 32 bits divided among four registers. 0x29?rxmsk2 (receive cell mask control register 2) the rxmsk2 register contains the seco nd byte of the receive cell mask. it modifies the atm cell screen in the receive cell header register. setting a bit in the ma sk register causes the corresponding bit in the received atm cell header to be disregarded for screening. for ex ample, setting rxmsk1, bit 0 to 1, causes atm cells to be accepted with either 1 or 0 in the octet 1, bit 0 position. combinations of receive header mask bits can select groups of atm vpi/vcis for reception. this mask consists of 32 bits divided among four registers. bit default name description 7 1 rxmsk1[7] these bits hold the receive header mask for octet 1 of the incoming cell. 61 rxmsk1[6] 51 rxmsk1[5] 41 rxmsk1[4] 31 rxmsk1[3] 21 rxmsk1[2] 11 rxmsk1[1] 01 rxmsk1[0] bit default name description 7 1 rxmsk2[7] these bits hold the receive head er mask for octet 2 of the incoming cell. 61 rxmsk2[6] 51 rxmsk2[5] 41 rxmsk2[4] 31 rxmsk2[3] 21 rxmsk2[2] 11 rxmsk2[1] 01 rxmsk2[0]
cx28250 4.0 registers atm physical interface (phy) devices 4.1 registers 28250-dsh-002-c mindspeed technologies ? 4-47 0x2a?rxmsk3 (receive cell mask control register 3) the rxmsk3 register contains the third byte of the receive cell mask. it modifies the atm cell screen in the receive cell header register. setting a bit in the mask register causes the correspo nding bit in the received atm cell header to be disregarded for screening. for ex ample, setting rxmsk1, bit 0 to 1, causes atm cells to be accepted with either 1 or 0 in the octet 1, bit 0 position. combinations of receive header mask bits can select groups of atm vpi/vcis for reception. this mask consists of 32 bits divided among four registers. 0x2b?rxmsk4 (receive cell mask control register 4) the rxmsk4 register contains the fourth byte of the re ceive cell mask. it modifies the atm cell screen in the receive cell header register. setting a bit in the mask register causes the correspo nding bit in the received atm cell header to be disregarded for screening. for ex ample, setting rxmsk1, bit 0 to 1, causes atm cells to be accepted with either 1 or 0 in the octet 1, bit 0 position. combinations of receive header mask bits can select groups of atm vpi/vcis for reception. this mask consists of 32 bits divided among four registers. bit default name description 7 1 rxmsk3[7] these bits hold the receive head er mask for octet 3 of the incoming cell. 61 rxmsk3[6] 51 rxmsk3[5] 41 rxmsk3[4] 31 rxmsk3[3] 21 rxmsk3[2] 11 rxmsk3[1] 01 rxmsk3[0] bit default name description 7 1 rxmsk4[7] these bits hold the receive head er mask for octet 4 of the incoming cell. 61 rxmsk4[6] 51 rxmsk4[5] 41 rxmsk4[4] 31 rxmsk4[3] 21 rxmsk4[2] 11 rxmsk4[1] 01 rxmsk4[0]
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-48 mindspeed technologies ? 28250-dsh-002-c 0x47?rxpth (receive path overhead status register) the rxpth register contains status info rmation for the receiv er path overhead. 0x6b?rxpthbuf (receive path trace circular buffer, j1) the rxsecbuf buffer is used to receive repeatedly a 64-b yte, fixed-length string so that a receiving terminal in a path can verify its continued co nnection to the in tended transmitter. bit default name description 7x ais-p (1) when a logic 1 is read, this bit indicates that an ais-p condition exists. 6x rdi-p (1) when a logic 1 is read, this bit indi cates that an rdi- p condition exists. 5x b3err (2) when a logic 1 is read, this bit indicates that a b3 error was received. 4x rei-p (2) when a logic 1 is read, this bit indicates that a rei-p error was received. 3x plm-p (1) when a logic 1 is read, this bit i ndicates that a plm- p condition exists. 2x uneq-p (1) when a logic 1 is read, this bit indi cates that a uneq-p condition exists. 1 0 ? reserved, set to 0. 0 0 ? reserved, set to 0. note(s): (1) this status reflects the current state of the circuit. (2) this status shows an event that has occurred since the register was last read. bit default name description 7 x rxpthbuf[7] receive path trace circular buffer bit 7. 6 x rxpthbuf[6] receive path trace circular buffer bit 6. 5 x rxpthbuf[5] receive path trace circular buffer bit 5. 4 x rxpthbuf[4] receive path trace circular buffer bit 4. 3 x rxpthbuf[3] receive path trace circular buffer bit 3. 2 x rxpthbuf[2] receive path trace circular buffer bit 2. 1 x rxpthbuf[1] receive path trace circular buffer bit 1. 0 x rxpthbuf[0] receive path trace circular buffer bit 0.
cx28250 4.0 registers atm physical interface (phy) devices 4.1 registers 28250-dsh-002-c mindspeed technologies ? 4-49 0x16?rxs1 (receive s1 ov erhead status register) the rxs1 register provides s1 overhead status. this by te is allocated for transporting synchronization status messages. this byte is defined only for the first sts-1 of the sts-3c signal. these messages provide an indication of the quality level of the sync hronization source of the sonet signal. 0x45?rxsec (receive section overhead status register) the rxsec register provides section overhead status. bit default name description 7 x rxs1[1] receive value for s1 overhead octet?bit 1 (msb) 6 x rxs1[2] receive value for s1 overhead octet?bit 2 5 x rxs1[3] receive value for s1 overhead octet?bit 3 4 x rxs1[4] receive value for s1 overhead octet?bit 4 3 x rxs1[5] receive value for s1 overhead octet?bit 5 2 x rxs1[6] receive value for s1 overhead octet?bit 6 1 x rxs1[7] receive value for s1 overhead octet?bit 7 0 x rxs1[8] receive value for s1 overhead octet?bit 8 (lsb) bit default name description 7x sigdet (1) when a logic 1 is read, this bit indicates that a signal detect condition exists on the lsigdet input pin. 6x lol (1) when a logic 1 is read, this bit indicate s that a loss of loc k condition exists. 5x los (1) when a logic 1 is read, this bit indicate s that a loss of si gnal condition exists. 4x oof (1) when a logic 1 is read, this bit indicate s that an out of frame condition exists. 3x lof (1) when a logic 1 is read, this bit indicate s that a loss of frame condition exists. 2x b1err (2) when a logic 1 is read, this bit indicate s that a section bip error was received. 1 0 rxfrmpulout this bit selects the type of output sent to the rxframeref pin. when written to a logic 1, the receive octet clock (19.44 mhz) is present. when written to a logic 0, a receive frame pulse (8 khz) is present. 0 0 rxfrmpulpol this bit selects the polarity of the rxfr ameref output pin. when written to a logic 1, the frame pulse output is an active high. wh en written to 0, the frame pulse output is an active low. note(s): (1) this status reflects the current state of the circuit. (2) this status shows an event that has occurred since the register was last read.
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-50 mindspeed technologies ? 28250-dsh-002-c 0x6a?rxsecbuf (receive sectio n trace circular buffer) the rxsecbuf buffer, the j0 byte, is used to receive repeatedly a 64-byte, fixed-length string so that a receiving terminal in a section can veri fy its continued connection to the intended transmitte r. this buffer is also used as a section trace for sdh. 0x1a?rxz01 (receive section z0 1 overhead register) the register contains the value of the received z0 1 overhead octet. bit default name description 7 x rxsecbuf[7] receive section trace circular buffer bit 7. 6 x rxsecbuf[6] receive section trace circular buffer bit 6. 5 x rxsecbuf[5] receive section trace circular buffer bit 5. 4 x rxsecbuf[4] receive section trace circular buffer bit 4. 3 x rxsecbuf[3] receive section trace circular buffer bit 3. 2 x rxsecbuf[2] receive section trace circular buffer bit 2. 1 x rxsecbuf[1] receive section trace circular buffer bit 1. 0 x rxsecbuf[0] receive section trace circular buffer bit 0. bit default name description 7 0 rxz01[7] receive z0 1 bit 7 6 0 rxz01[6] receive z0 1 bit 6 5 0 rxz01[5] receive z0 1 bit 5 4 0 rxz01[4] receive z0 1 bit 4 3 0 rxz01[3] receive z0 1 bit 3 2 0 rxz01[2] receive z0 1 bit 2 1 0 rxz01[1] receive z0 1 bit 1 0 0 rxz01[0] receive z0 1 bit 0
cx28250 4.0 registers atm physical interface (phy) devices 4.1 registers 28250-dsh-002-c mindspeed technologies ? 4-51 0x1b?rxz02 (receive section z0 2 overhead register) the register contains the value of the received z0 2 overhead octet. 0x3d?secint (receive se ction interrupt indicati on status register) the secint register indicates that a change of stat us has occurred within its affiliated status signals. bit default name description 7 0 rxz02[7] receive z0 2 bit 7 6 0 rxz02[6] receive z0 2 bit 6 5 0 rxz02[5] receive z0 2 bit 5 4 0 rxz02[4] receive z0 2 bit 4 3 0 rxz02[3] receive z0 2 bit 3 2 0 rxz02[2] receive z0 2 bit 2 1 0 rxz02[1] receive z0 2 bit 1 0 0 rxz02[0] receive z0 2 bit 0 bit default name description 7x sigdetint (1) when a logic 1 is read, this bit indicates that a signal detect interrupt has occurred. 6x lolint (1) when a logic 1 is read, this bit indicates that a loss of lock interrupt has occurred. 5x losint (1) when a logic 1 is read, this bit indicates that a loss of signal interrupt has occurred. 4x oofint (1) when a logic 1 is read, this bit indicates that a out of frame interrupt has occurred. 3x lofint (1) when a logic 1 is read, this bit indicates that a loss of frame interrupt has occurred. 2x b1errint (2) when a logic 1 is read, this bit indicate s that a section bip error interrupt has occurred. 1x sectraceint (2) when a logic 1 is read, this bit indicates that a section trace interrupt has occurred. 0 0 ? reserved, set to 0. note(s): (1) dual event?either a 0?> 1 or a 1 ?> 0 transition on the corresponding status bit causes this interr upt to occur provided that this interrupt has been enabled by the corresponding enable bit. reading the in terrupt register clears the interrupt. (2) single event?a 0?> 1 transition on the correspondi ng status bit causes this interrupt to occur provided that this interrupt has been enabled by the corresponding en able bit. reading the interrupt register clears the interrupt.
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-52 mindspeed technologies ? 28250-dsh-002-c 0x3c?sumint (summary interrupt indication status register) the sumint register indicates data li nk interrupts, one-second interrupts , and additional summary interrupts. bit default name description 7x secint (2) when a logic 1 is read, this bit indicates a son et section interrupt. this interrupt is a summary interrupt and signifies that an interrupt indication has occurred in the secint register (0x3d). 6x linint (2) when a logic 1 is read, this bit indicates a sonet line interrupt. this interrupt is a summary interrupt and signifies that an interrupt indication has occurred in the linint register (0x3e). 5x pthint (2) when a logic 1 is read, this bit indicates a sonet path interrupt . this interrupt is a summary interrupt and signifies that an interrupt indication has occurred in the pthint register (0x3f). 4x onesecint (1) when a logic 1 is read, this bit indica tes a one second interrupt. this interrupt signifies that a rising edge occurred on the onesecin pin. the in terrupt is generated for each rising edge on the onesecin pin a nd is cleared upon a read of this status register. 3 0 ? reserved, set to 0. 2x apsint (2) when a logic 1 is read, this bit indicates an aps interrupt . this interrupt is a summary interrupt and signifies that an interrupt i ndication has occurred in the apsint register (0x42). set this bit to 0 on lan parts. 1x rxcellint (2) when a logic 1 is read, this bit indicates a receive cell interrupt. this interrupt is a summary interrupt and signifies that an interrupt indication has occurred in the receive cell indicati on register (0x41). 0x txcellint (2) when a logic 1 is read, this bit indica tes a transmit cell/utopia interrupt. this interrupt is a summary interr upt and signifies that an in terrupt indicati on has occurred in the transmit cell indi cation register (0x40). note(s): (1) single event?a 0?> 1 transition on the correspondi ng status bit causes this interrupt to occur provided that this interrupt has been enabled by the corresponding enab le bit. reading this interrupt register clears this interrupt. (2) these bits are summary indications of any interrupt events set in the indicated regist ers. these bits can serve as direction to which status registers need to be read ne xt. these bits are cleared when the interr upt bits in the indi cated individual interru pt registers are read and cleared.
cx28250 4.0 registers atm physical interface (phy) devices 4.1 registers 28250-dsh-002-c mindspeed technologies ? 4-53 0x13?txc2 (transmit c2 ov erhead control register) the txc2 register controls the c2 byte in the transport overhead. this byte is allocated to identify the construction and content of the sts-level spe. 0x48?txcell (transmit cell status register) the txcell register contains status for the cell transmitter and the utopia interface. bit default name description 7 0 txc2[1] transmit value for c2 overhead octet?bit 1 (msb) 6 0 txc2[2] transmit value for c2 overhead octet?bit 2 5 0 txc2[3] transmit value for c2 overhead octet?bit 3 4 1 txc2[4] transmit value for c2 overhead octet?bit 4 3 0 txc2[5] transmit value for c2 overhead octet?bit 5 2 0 txc2[6] transmit value for c2 overhead octet?bit 6 1 1 txc2[7] transmit value for c2 overhead octet?bit 7 0 1 txc2[8] transmit value for c2 overhead octet?bit 8 (lsb) bit default name description 7x parerr (1) when a logic 1 is read, this bit indicate s that a parity error was received on the transmit utopia input data octet. 6x socerr (1) when a logic 1 is read, this bit indicates that a start of cell alignment error was received on the utxsoc input pin. 5x txovfl (1) when a logic 1 is read, this bit indicate s that a transmit fifo overflow condition occurred in the transmit utopia fifo. 4x rxovfl (1) when a logic 1 is read, this bit indicate s that a receive fifo overflow condition occurred in the receive utopia fifo. 3x cellsent (1) when a logic 1 is read, this bit indica tes that a non-idle ce ll was formatted and transmitted from the utopia interface. 2 0 ? reserved, set to 0. 1 0 ? reserved, set to 0. 0 0 disidlecell when set to a logic 1, the cx28250 does not generate idle cells. note(s): (1) this status shows an event that has occurred since the register was last read.
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-54 mindspeed technologies ? 28250-dsh-002-c 0x40?txcellint (transmit cell interr upt indication status register) the txcellint register indicates that a change of stat us has occurred within its affiliated status signals. 0x62?txcnth (transmitted cell counter [high byte]) the txcnth coun ter tracks the number of transmitted cells. bit default name description 7x parerrint (1) when a logic 1 is read, this bit indi cates that a parity error has occurred. 6x socerrint (1) when a logic 1 is read, this bit indicate s that a start of cell alignment error has occurred. 5x txovflint (1) when a logic 1 is read, this bit indicates that a transmit fifo overflow has occurred. 4x rxovflint (1) when a logic 1 is read, this bit indicates that a receive fifo overflow has occurred. 3x cellsentint (1) when a logic 1 is read, this bit indicates that a cell sent interrupt has occurred. 2 0 ? reserved, set to 0. 1 0 ? reserved, set to 0. 0 0 ? reserved, set to 0. note(s): (1) single event?a 0?> 1 transition on the correspondi ng status bit causes this interrupt to occur provided that this interrupt has been enabled by the corresponding en able bit. reading the interrupt register clears the interrupt. bit default name description 7 0 ? reserved, set to 0. 6 0 ? reserved, set to 0. 5 0 ? reserved, set to 0. 4 0 ? reserved, set to 0. 3 0 ? reserved, set to 0. 2 x txcnt[18] transmitted ce ll counter bit 18 (msb). 1 x txcnt[17] transmitted cell counter bit 17. 0 x txcnt[16] transmitted cell counter bit 16.
cx28250 4.0 registers atm physical interface (phy) devices 4.1 registers 28250-dsh-002-c mindspeed technologies ? 4-55 0x60?txcntl (transmitted cell counter [low byte]) the txcntl counter tracks the number of transmitted cells. 0x61?txcntm (transmitted ce ll counter [mid byte]) the txcntm counter tracks the number of transmitted cells. bit default name description 7 x txcnt[7] transmitte d cell counter bit 7. 6 x txcnt[6] transmitte d cell counter bit 6. 5 x txcnt[5] transmitte d cell counter bit 5. 4 x txcnt[4] transmitte d cell counter bit 4. 3 x txcnt[3] transmitte d cell counter bit 3. 2 x txcnt[2] transmitte d cell counter bit 2. 1 x txcnt[1] transmitte d cell counter bit 1. 0 x txcnt[0] transmitted ce ll counter bit 0 (lsb). bit default name description 7 x txcnt[15] transmitted cell counter bit 15. 6 x txcnt[14] transmitted cell counter bit 14. 5 x txcnt[13] transmitted cell counter bit 13. 4 x txcnt[12] transmitted cell counter bit 12. 3 x txcnt[11] transmitted cell counter bit 11. 2 x txcnt[10] transmitted cell counter bit 10. 1 x txcnt[9] transmitted cell counter bit 9. 0 x txcnt[8] transmitted cell counter bit 8.
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-56 mindspeed technologies ? 28250-dsh-002-c 0x1c?txhdr1 (transmit cell header control register 1) the txhdr1 register contains the first byte of the transmit cell header. this header consists of 32 bits divided among four registers. cell gene ration is described in detail in section 2.4 . 0x1d?txhdr2 (transmit cell header control register 2) the txhdr2 register contains the second byte of the tr ansmit cell header. this h eader consists of 32 bits divided among four registers. cell gene ration is described in detail in section 2.4 . bit default name description 7 0 txhdr1[7] these bits hold the tran smit header values for octet 1 of the outgoing cell. insertion of the bits is controlled by register 0x04 (cgen). gfc bits. (bit 7 is the gfc msb.) 6 0 txhdr1[6] 5 0 txhdr1[5] 4 0 txhdr1[4] 3 0 txhdr1[3] vpi bits. (bit 3 is the gfc msb.) 2 0 txhdr1[2] 1 0 txhdr1[1] 0 0 txhdr1[0] bit default name description 7 0 txhdr2[7] these bits hold the transmit header va lues for octet 2 of the outgoing cell. insertion of the bits is controlled by the cgen register (0x04). vpi bits. (bit 4 is the vpi lsb.) 6 0 txhdr2[6] 5 0 txhdr2[5] 4 0 txhdr2[4] 3 0 txhdr2[3] vci bits. (bit 3 is the vci msb.) 2 0 txhdr2[2] 1 0 txhdr2[1] 0 0 txhdr2[0]
cx28250 4.0 registers atm physical interface (phy) devices 4.1 registers 28250-dsh-002-c mindspeed technologies ? 4-57 0x1e?txhdr3 (transmit cell header control register 3) the txhdr3 register contains the third byte of the tr ansmit cell header. this head er consists of 32 bits divided among four registers. cell gene ration is described in detail in section 2.4 . 0x1f?txhdr4 (transmit cell header control register 4) the txhdr4 register contains the fourth byte of the tr ansmit cell header. this header consists of 32 bits divided among four registers. cell gene ration is described in detail in section 2.4 . bit default name description 7 0 txhdr3[7] these bits hold the tran smit header values for octet 3 of the outgoing cell. insertion of the bits is contro lled by the cgen register (0x04). vci bits. (bit 0 is the vci lsb.) 6 0 txhdr3[6] 5 0 txhdr3[5] 4 0 txhdr3[4] 3 0 txhdr3[3] 2 0 txhdr3[2] 1 0 txhdr3[1] 0 0 txhdr3[0] bit default name description 7 0 txhdr4[7] these bits hold the tran smit header values for octet 4 of the outgoing cell. insertion of the bits is controlled by the cgen register (0x04). vci bits. (bit 4 is the vci lsb). 6 0 txhdr4[6] 5 0 txhdr4[5] 4 0 txhdr4[4] 3 0 txhdr4[3] payload-type bits 2 0 txhdr4[2] 1 0 txhdr4[1] 0 0 txhdr4[0] cell loss priority bit
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-58 mindspeed technologies ? 28250-dsh-002-c 0x20?txidl1 (transmit idle ce ll header control register 1) the txidl1 register contains the first byte of the transmit idle cell header. it contains the header value that is inserted in idle cells transmitted from the device. this h eader consists of 32 bits divided among four registers. cell generation is described in detail in section 2.4 . 0x21?txidl2 (transmit idle ce ll header control register 2) the txidl2 register contains the second byte of the tran smit idle cell header. it contains the header value that is inserted in idle cells transmitted from the device. this header consists of 32 bits divided among four registers. cell generation is described in detail in section 2.4 . bit default name description 7 0 txidl1[7] these bits hold the transmit idle ce ll header values for octe t 1 of the outgoing cell. gfc bits. (bit 7 is the gfc msb.) 6 0 txidl1[6] 5 0 txidl1[5] 4 0 txidl1[4] 3 0 txidl1[3] vpi bits. (bit 3 is the vpi msb.) 2 0 txidl1[2] 1 0 txidl1[1] 0 0 txidl1[0] bit default name description 7 0 txidl2[7] these bits hold the tran smit idle cell header values for octet 2 of the outgoing cell. vpi bits. (bit 4 is the vpi lsb.) 60 txidl2[6] 50 txidl2[5] 40 txidl2[4] 30 txidl2[3] vci bits. ((bit 3 is the vci msb.) 20 txidl2[2] 10 txidl2[1] 00 txidl2[0]
cx28250 4.0 registers atm physical interface (phy) devices 4.1 registers 28250-dsh-002-c mindspeed technologies ? 4-59 0x22?txidl3 (transmit idle ce ll header control register 3) the txidl3 register contains the third byte of the transmit idle cell header. it contains the header value that is inserted in idle cells transmitted from the device. this h eader consists of 32 bits divided among four registers. cell generation is described in detail in section 2.4 . 0x23?txidl4 (transmit idle ce ll header control register 4) the txidl4 register contains the fourth byte of the transmit idle cell head er. it contains the header value that is inserted in idle cells transmitted from the device. this header consists of 32 bits divided among four registers. cell generation is described in detail in section 2.4 . bit default name description 7 0 txidl3[7] these bits hold the tr ansmit idle cell header values for octet 3 of the outgoing cell. vci bits 6 0 txidl3[6] 5 0 txidl3[5] 4 0 txidl3[4] 3 0 txidl3[3] 2 0 txidl3[2] 1 0 txidl3[1] 0 0 txidl3[0] bit default name description 7 0 txidl4[7] these bits hold the tran smit idle cell header values for octet 4 of the outgoing cell. vci bits. (bit 4 is the vci lsb.) 60 txidl4[6] 50 txidl4[5] 40 txidl4[4] 30 txidl4[3] payload-type bits 20 txidl4[2] 10 txidl4[1] 0 1 txidl4[0] cell loss priority bit
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-60 mindspeed technologies ? 28250-dsh-002-c 0x10?txk1 (transmit k1 ov erhead control register) the txk1 register controls the k1 byte in the tran sport overhead. the k1 and k2 bytes are allocated for automatic protection switching (aps) si gnaling between line level entities. these bytes are defined only for the first sts-1 of the sts-3c signal. 0x11?txk2 (transmit k2 ov erhead control register) the txk2 register controls the k2 byte in the transport overhead. the k1 by te and bits 0-5 of the k2 byte are allocated for automatic protection switching (aps) sign aling between line level entities. these bytes are defined only for the first sts-1 of the sts-3c signal. bits 6-8 of the k2 byte are allocated for alarm indica tion signal (ais) and remote defect indicator (rdi). these bytes are defined only for the first sts-1 of the sts-3c signal. bit default name description 7 0 txk1[1] transmit value for k1 overhead octet?bit 1 (msb) 6 0 txk1[2] transmit value for k1 overhead octet?bit 2 5 0 txk1[3] transmit value for k1 overhead octet?bit 3 4 0 txk1[4] transmit value for k1 overhead octet?bit 4 3 0 txk1[5] transmit value for k1 overhead octet?bit 5 2 0 txk1[6] transmit value for k1 overhead octet?bit 6 1 0 txk1[7] transmit value for k1 overhead octet?bit 7 0 0 txk1[8] transmit value for k1 overhead octet?bit 8 (lsb) bit default name description 7 0 txk2[1] transmit value for k2 overhead octet?bit 1 (msb) 6 0 txk2[2] transmit value for k2 overhead octet?bit 2 5 0 txk2[3] transmit value for k2 overhead octet?bit 3 4 0 txk2[4] transmit value for k2 overhead octet?bit 4 3 0 txk2[5] transmit value for k2 overhead octet?bit 5 2 0 txk2[6] transmit value for k2 overhead octet?bit 6 1 0 txk2[7] transmit value for k2 overhead octet?bit 7 0 0 txk2[8] transmit value for k2 overhead octet?bit 8 (lsb)
cx28250 4.0 registers atm physical interface (phy) devices 4.1 registers 28250-dsh-002-c mindspeed technologies ? 4-61 0x0d?txlin (transmit line overhead control register) the txlin register controls the tran smission of various octets in the line overhead of the sonet frame. bit default name description 7 0 stmmode when written to a logic 1, this bi t enables the sdh stm-1 mode pointer. when enabled, the h1/h2 bytes are 6a/0a. when written to 0, the h1/h2 bytes are set to 62/0a for sonet applications. for oc-3c, bit 6 (dispntr) overri des this function. 6 0 dispntr when this bit is written to a logic 1, the h1/h2 overhead bytes are forced to 33, when written to 0, the h1/h2 value is determined by bit 7. 5 0 disb2 when written to a logic 1, this bit disabl es the bip calculations for the line overhead. when disabled, the b2 bytes are set to 00. wh en written to 0, the bip calculations are enabled, and the results are placed in the b2 bytes. 4 0 entxlindl when written to a logic 1, this bit enables the transmit d4-d12 bytes of the data link. when written to 0, these bytes are forced to all 00. 3 0 inslnais when written to a logic 1, this bit insert s line ais. all bits exce pt the section overhead octets are written to a logic 1 prior to scra mbling. when written to 0, line ais is not inserted. 2 0 inslnrdi when written to a logic 1, this bit insert s line rdi. k2 bits 6, 7, and 8 are set to 110. when written to 0, k2 bits 6, 7, and 8 are set to the values of the bits 6, 7, and 8 in the txk2 register. 1 1 autolnrdi when written to a logic 1, this bit en ables automatic line rdi. when enabled, line rdi is automatically generated (f or 5 frames for the cx28250-23 device or 20 frames for the CX28250-26 device) upon rece ption of los, lof, or ais-l. when written to 0, automatic line rd i is disabled. 0 1 autolnrei when written to a logic 1, this bit enab les automatic line rei. when written to 1, line rei codes are automatically inserted upon re ception of line bip e rrors. when written to 0, automatic line rei is disabled.
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-62 mindspeed technologies ? 28250-dsh-002-c 0x0e?txpth (transmit path ov erhead control register) the txpth register controls the tran smission of various octets in the path overhead of the sonet frame. 0x69?txpthbuf (transmit path trace circular buffer) the txpthbuf buffer, the j1 byte, is used to transmit repeatedly a 64-byt e, fixed-length string so that a receiving terminal in a path can verify its con tinued connection to the intended transmitter. bit default name description 7 0 enpthtr when written to a logic 1, this bit en ables the path trace message (j1). when written to 0, the j1 byte contains 00. 6 0 disb3 when written to a logic 1, this bit disa bles the bip calculation for the path overhead. when disabled, the b3 byte is set to 00. when written to 0, the bip calculation is enabled, and the result is placed in the b3 byte. 5 1 autopthrei when written to a logic 1, this bit enables automatic path rei. when enabled, path rei codes are automatically inserted upon rece ption of path bip errors. when written to 0, automatic path rei is not enabled. 4 0 inspthais when written to a logic 1, this bit inserts path ais. when written to 0, path ais is not inserted. 3 0 txrdi[7] this value is mapped to transmit rdi bit 7 in the g1 path overhead octet. (1) 2 0 txrdi[6] this value is mappe d to transmit rdi bit 6 in the g1 path overhead octet. 1 1 txrdi[5] this value is mapped to transmit rdi bit 5 in the g1 path overhead octet. (1) 0 1 autopthrdi when written to a logic 1, this bit enables automatic path rdi. when enabled, path rdi is automatically gene rated (for 10 frames for the cx28250-23 device or 20 frames for the CX28250-26 devi ce) upon reception of los, lof, lop, ais-l, ais-p, uneq-p, or plm-p. when none of the above alarms are present path rdi (g1, bits 5-7) is inserted from bits [3:1] of this register. when written to 0, path rdi (g1, bits 5-7) is inse rted from bits [1:3] of this register. note(s): (1) transmit rdi bits 5 and 7 are reversed as compared to rece ive g1 overhead status regist er (0x 19?rx g1). see 0x19?rxg1 (receive g1 overhead stat us register) on page 4-35. bit default name description 7 x txpthbuf[7] transmit path tr ace circular buffer bit 7. 6 x txpthbuf[6] transmit path tr ace circular buffer bit 6. 5 x txpthbuf[5] transmit path tr ace circular buffer bit 5. 4 x txpthbuf[4] transmit path tr ace circular buffer bit 4. 3 x txpthbuf[3] transmit path tr ace circular buffer bit 3. 2 x txpthbuf[2] transmit path tr ace circular buffer bit 2. 1 x txpthbuf[1] transmit path tr ace circular buffer bit 1. 0 x txpthbuf[0] transmit path tr ace circular buffer bit 0.
cx28250 4.0 registers atm physical interface (phy) devices 4.1 registers 28250-dsh-002-c mindspeed technologies ? 4-63 0x12?txs1 (transmit s1 ov erhead control register) the txs1 register controls the s1 by te in the transport overhead. this byte is allocated for transporting synchronization status messages and is defined only for the first sts-1 of the sts-3c signal. these messages provide an indication of the quality level of the synchronization sour ce of the sonet signal. 0x0c?txsec (transmit section overhead control register) the txsec register controls transmission of various octets in the section over head of the sonet frame. bit default name description 7 0 txs1[1] transmit value for s1 overhead octet?bit 1 (msb) 6 0 txs1[2] transmit value for s1 overhead octet?bit 2 5 0 txs1[3] transmit value for s1 overhead octet?bit 3 4 0 txs1[4] transmit value for s1 overhead octet?bit 4 3 0 txs1[5] transmit value for s1 overhead octet?bit 5 2 0 txs1[6] transmit value for s1 overhead octet?bit 6 1 0 txs1[7] transmit value for s1 overhead octet?bit 7 0 0 txs1[8] transmit value for s1 overhead octet?bit 8 (lsb) bit default name description 7 0 distxscr when written to a logic 1, this bit disables the transmit frame scrambler. when written to 0, scrambling is enabled. 6 0 entxsecdl when written to a logic 1, this bit enables the transmit d1/d2/d3 bytes of the data link. when written to 0, these bytes are forced to all 00. 5 0 ensectr when written to a logic 1, this bit enables the section trace message (j0). when written to 0, the j0 byte co ntains 01. the z0/z0 bytes c ontain 02/03 regardless of the bit 5 setting. 4 0 disa1a2 when this bit is written to a logic 1, the a1/a2 overhead bytes are forced to 00, when written to 0, the a1/a2 overhead byte s contain their default values (f6/28). 3 0 disb1 when written to a logic 1, this bit disables the bip calculation for the section overhead. when disabled, the b1 byte is set to 00. when written to 0, the bip calculation is enabled, and the re sult is placed in the b1 byte. 2 0 insallzer when written to a logic 1, this bit inserts 0s after the transmit frame scrambler output. when written to 0, cell/ overhead data is transmitted. 1 0 txfrmpulout this bit selects the type of output sent to the txframeref pin. when written to a logic 1, the transmit octet clock (19.44 mhz) is present. when written to a logic 0, a transmit frame pulse (8 khz) is present. 0 0 txfrmpulpol this bit select s the polarity of the txframeref pin. when written to a logic 1, the frame pulse output is an acti ve high. when written to 0, the frame pulse output is an active low.
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-64 mindspeed technologies ? 28250-dsh-002-c 0x68?txsecbuf (transmit sectio n trace circular buffer, j0) the txsecbuf buffer, the j0 byte, is used to transmit repeatedly a 64-byte, fixed- length string so that a receiving terminal in a section can veri fy its continued connection to the intended transmitte r. this buffer is also used as a section trace for sdh. 0x6c?txz01 (tr ansmit section z0 1 overhead control register) the contents of this regist er are transmitted in the z0 1 overhead octet. bit default name description 7 x txsecbuf[7] transmit section trace circular buffer bit 7. 6 x txsecbuf[6] transmit section trace circular buffer bit 6. 5 x txsecbuf[5] transmit section trace circular buffer bit 5. 4 x txsecbuf[4] transmit section trace circular buffer bit 4. 3 x txsecbuf[3] transmit section trace circular buffer bit 3. 2 x txsecbuf[2] transmit section trace circular buffer bit 2. 1 x txsecbuf[1] transmit section trace circular buffer bit 1. 0 x txsecbuf[0] transmit section trace circular buffer bit 0. bit default name description 7 0 txz01[7] transmit z0 1 bit 7 6 0 txz01[6] transmit z0 1 bit 6 5 0 txz01[5] transmit z0 1 bit 5 4 0 txz01[4] transmit z0 1 bit 4 3 0 txz01[3] transmit z0 1 bit 3 2 0 txz01[2] transmit z0 1 bit 2 1 0 txz01[1] transmit z0 1 bit 1 0 0 txz01[0] transmit z0 1 bit 0
cx28250 4.0 registers atm physical interface (phy) devices 4.1 registers 28250-dsh-002-c mindspeed technologies ? 4-65 0x6d?txz02 (transmit section z0 2 overhead control register) the contents of this regist er are transmitted in the z0 2 overhead octet. 0x74?udf2 (user define d field 2; overwrite control register) the contents of this register are wr itten into the received cell udf2 octet when in utopia 2, 16 bit mode. it is ignored in utopia 8 bit mode. bit default name description 7 0 txz02[7] transmit z0 2 bit 7 6 0 txz02[6] transmit z0 2 bit 6 5 0 txz02[5] transmit z0 2 bit 5 4 0 txz02[4] transmit z0 2 bit 4 3 0 txz02[3] transmit z0 2 bit 3 2 0 txz02[2] transmit z0 2 bit 2 1 0 txz02[1] transmit z0 2 bit 1 0 0 txz02[0] transmit z0 2 bit 0 bit default name description 7 0 udf2[7] value to write to the udf2 octet. 60 udf2[6] 50 udf2[5] 40 udf2[4] 30 udf2[3] 20 udf2[2] 10 udf2[1] 00 udf2[0]
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-66 mindspeed technologies ? 28250-dsh-002-c 0x4e?unccnt (uncorrect ed hec error counter) the unccnt counter tracks the numb er of uncorrected hec errors. 0x0a?utop1 (utopia control register 1) the utop1 register controls the mode of operation for the utopia interface. bit default name description 7 x unccnt[7] uncorrected hec error counter bit 7 (msb). 6 x unccnt[6] uncorrected hec error counter bit 6. 5 x unccnt[5] uncorrected hec error counter bit 5. 4 x unccnt[4] uncorrected hec error counter bit 4. 3 x unccnt[3] uncorrected hec error counter bit 3. 2 x unccnt[2] uncorrected hec error counter bit 2. 1 x unccnt[1] uncorrected hec error counter bit 1. 0 x unccnt[0] uncorrected hec error counter bit 0 (lsb). bit default name description 7 0 txreset when written to a logic 1, this bit resets the transmit fifo pointers. this reset must be used as a test function since it can create short cells. 6 0 rxreset when written to a logic 1, this bit resets the receive fifo point ers. this reset must be used as a test function since it can create short cells. 5 1 (1) utopmode when written to a logic 1, this bit enables utopia level 2 mode. when written to a logic 0, utopia level 1 operation is enabled. 4 1 handshake when written to a logic 1, this bit enables cell handshaking. when written to a logic 0, octet hands haking is enabled. 3 0 (1) buswidth when written to a logic 1, this bit en ables the 8-bit bus. when written to a logic 0, the 16-bit bus is enabled. 2 0 odd/even this bit determines o dd/even parity. when written to a logic 1, even parity is generated and checked. when written to a logic 0, odd parity is ge nerated and checked. 1 0 txfill[1] these bits set the transmit fifo fill level thresh old for utxclav pin. 00?the txclav line will be asserted if the utopia fifo can accept at least 1 more complete cell. 01?the txclav line will be asserted only if the utopia fifo has room for least 2 more cells. 10?the txclav line will be asserted only if the utopia fifo has room for at least 3 more cells. 11?the txclav line will be asserted only if the utopia fifo can accept at least 3 more cells. 0 0 txfill[0] note(s): (1) pins utopmode and buswidth can ov erride the defaults. refer to table 1-1 for a description of these pins.
cx28250 4.0 registers atm physical interface (phy) devices 4.1 registers 28250-dsh-002-c mindspeed technologies ? 4-67 0x0b?utop2 (utopia control register 2) the utop2 register contains the multi-phy address value for the device. 0x03?version (part number/v ersion status register) the version register is used to identify the mindspeed device and its revision level. bit default name description 7 0 test 1 this is a test function; set to a logic 0. 6 0 test 2 this is a test function; set to a logic 0. 5 0 utopdis when written to a logic 1, this bit disables the utopia re ceiver outputs. (this must not be confused with the discellrcvr bit, which completely stops cell processing). the utopdis bit puts the rece ive side of the utopia outputs (i.e., urxdata[15:0], urxprty, urxsoc, urxclav, and utxclav) in a high impedance state. 4 0 mphyaddr[4]?msb these bits hol d the multi-phy device address. must be a unique address for each de vice on the bus unless it?s using the utopdis bit. 3 0 mphyaddr[3] 2 0 mphyaddr[2] 1 0~ mphyaddr[1] 0 0~ mphyaddr[0]?lsb bit default name description 7 0 part[3]?msb this is the part number that identifies the cx28250 device (0111). 61 part[2] 51 part[1] 4 1 part[0]?lsb 3 0 ver[3]?msb this is the version number that identifies the specific version of the cx28250 device. version numbers start at 1 for the first ve rsion and are incremented for each revision thereafter. cx28250-23 = 4 CX28250-26 = 7 2 1 ver[2] 1 1 ver[1] 0 1 ver[0]?lsb
4.0 registers cx28250 4.1 registers atm physical interface (phy) devices 4-68 mindspeed technologies ? 28250-dsh-002-c
28250-dsh-002-c mindspeed technologies ? 5-1 5 5.0 electrical and mechanical specifications \ this chapter describes the electrical an d mechanical aspects of the cx28250. included are timing diagrams, absolute maximum ratings, dc characteristics, and mechanical drawings. 5.1 timing specifications this section provides timing diagrams and descriptions for the various interfaces of the cx28250. table 5-1 describes the different types of timing relationships that appear in the timing diagrams. the timing relationship labels are numbered when they occur more than once in a diag ram so that each label is unique. this numbering aids in identifyin g the appropriate label in table 5-1 . signals are measured at the 50% point of the changing edge except for those involving high impedance transitions which ar e measured at 10% and 90%. note: all characteristics assume a 3.3 v 5% power supply and ?40 c to 85 c ambient temperature.
5.0 electrical and mechanical specifications cx28250 5.1 timing specifications atm physical interface (phy) devices 5-2 mindspeed technologies ? 28250-dsh-002-c table 5-1. timing diagram nomenclature (1 of 3) symbol timing relationship waveform t pw pulse width t pwh pulse width high t pwl pulse width low t s setup time t sh setup high time t sl setup low time t h hold time t hh hold high time input input input data clock data clock data clock data clock data clock
cx28250 5.0 electrical and mechanical specifications atm physical interface (phy) devices 5.1 timing specifications 28250-dsh-002-c mindspeed technologies ? 5-3 t hl hold low time t pd propagation delay t pdhl propagation delay - high-to-low t pdlh propagation delay - low-to-high t en enable time t enzl enable time - high-impedance to low enable t enzh enable time - high-impedance to high enable t dis disable time table 5-1. timing diagram nomenclature (2 of 3) symbol timing relationship waveform data clock input output input output input output input output input output input output input output
5.0 electrical and mechanical specifications cx28250 5.1 timing specifications atm physical interface (phy) devices 5-4 mindspeed technologies ? 28250-dsh-002-c figure 5-1 illustrates how input waveforms are defined, and figure 5-2 illustrates how output waveforms are defined. t dishz disable time - high disable t dislz disable time - low disable t rec recovery time t per period t cyc cycle time ? f max maximum frequency ? f min minimum frequency ? table 5-1. timing diagram nomenclature (3 of 3) symbol timing relationship waveform input output input output async. input clock input figure 5-1. input waveform 2.0 v 500035_026 t rise t fall 1.5 v 0.8 v t per
cx28250 5.0 electrical and mechanical specifications atm physical interface (phy) devices 5.1 timing specifications 28250-dsh-002-c mindspeed technologies ? 5-5 the following diagram shows how output waveforms are defined. figure 5-2. output waveform t rise t fall 2.4v 1.5v 0.4v t pwh t per t pwl 500035_027
5.0 electrical and mechanical specifications cx28250 5.1 timing specifications atm physical interface (phy) devices 5-6 mindspeed technologies ? 28250-dsh-002-c 5.1.1 microprocessor interface timing figures 5-3 through 5-6 and tables 5-2 through 5-5 define the timing requirements and characteristics of the microprocessor interface. figure 5-3. synchronous mode, read timing diagram note(s): mcs* and mw/r* must not change state while mas* is asserted. t sl1 t hl1 t sh1 t hh1 t sl2 t hl2 t sh2 t hh2 t sl3 t hl3 t sh3 t hh3 t s t h t pwh t pwl t per t en t pd t dis t enzl t dislz (high) mcs* mw/r* mas* maddr[6:0] mclk mdata[7:0] mint* msyncmode valid 500035_028
cx28250 5.0 electrical and mechanical specifications atm physical interface (phy) devices 5.1 timing specifications 28250-dsh-002-c mindspeed technologies ? 5-7 note: for table 5-2 loading: databus = 60 pf, mint* = 20 pf table 5-2. synchronous mode, read timing table label description min max unit t pwh pulse width high, mclk 9 50 ns t pwl pulse width low, mclk 9 50 ns t per period, mclk 20 125 ns t sl1 setup low, mcs* to the rising edge of mclk 1 ? ns t hl1 hold low, mcs* from the rising edge of mclk 2.5 ? ns t sh1 setup high, mcs* to the rising edge of mclk 1 ? ns t hh1 hold high, mcs* from the rising edge of mclk 2.5 ? ns t sl2 setup low, mw/r* to the rising edge of mclk 1 ? ns t hl2 hold low, mw/r* from the rising edge of mclk 2.5 ? ns t sh2 setup high, mw/r* to the ri sing edge of mclk 1 ? ns t hh2 hold high, mw/r* from the rising edge of mclk 2.5 ? ns t sl3 setup low, mas* to the rising edge of mclk 1 ? ns t hl3 hold low, mas* from the rising edge of mclk 2.5 ? ns t sh3 setup high, mas* to the rising edge of mclk 1 ? ns t hh3 hold high, mas* from the rising edge of mclk 2.5 ? ns t s setup, maddr[6:0] to the rising edge of mclk 1 ? ns t h hold, maddr[6:0] from the rising edge of mclk 7.5 ? ns t en enable, mdata[7:0] from th e rising edge of mclk 2 13 ns t pd propagation delay, mdata[7:0] fr om the rising edge of mclk 2 15 (1) ns t dis disable, mdata[7:0] from th e rising edge of mclk 2 13 ns t enzl enable, mint* from the ri sing edge of mclk 2 10 ns t dislz disable, mint* from the rising edge of mclk 2 10 ns note(s): 1. when reading from sonet j0/j1 trace buffers, t pd = 19.7 ns.
5.0 electrical and mechanical specifications cx28250 5.1 timing specifications atm physical interface (phy) devices 5-8 mindspeed technologies ? 28250-dsh-002-c figure 5-4. synchronous mode, write timing diagram note(s): mcs* and mw/r* must not change state while mas* is asserted. t sl1 t hl1 t sh1 t hh1 t sh2 t sl2 t hh2 t hl2 t sl3 t hl3 t sh3 t hh3 t s1 t h1 t s2 t h2 t pwh t pwl t per (high) mcs* mw/r* mas* maddr[6:0] mdata[7:0] mclk msyncmode 500035_029
cx28250 5.0 electrical and mechanical specifications atm physical interface (phy) devices 5.1 timing specifications 28250-dsh-002-c mindspeed technologies ? 5-9 table 5-3. synchronous mode, write timing table label description min max unit t pwh pulse width high, mclk 9 50 ns t pwl pulse width low, mclk 9 50 ns t per period, mclk 20 125 ns t sl1 setup low, mcs* to the rising edge of mclk 1 ? ns t hl1 hold low, mcs* from the rising edge of mclk 2.5 ? ns t sh1 setup high, mcs* to the rising edge of mclk 1 ? ns t hh1 hold high, mcs* from the rising edge of mclk 2.5 ? ns t sl2 setup low, mw/r* to the rising edge of mclk 1 ? ns t hl2 hold low, mw/r* from the rising edge of mclk 2.5 ? ns t sh2 setup high, mw/r* to the ri sing edge of mclk 1 ? ns t hh2 hold high, mw/r* from the rising edge of mclk 2.5 ? ns t sl3 setup low, mas* to the rising edge of mclk 1 ? ns t hl3 hold low, mas* from the rising edge of mclk 2.5 ? ns t sh3 setup high, mas* to the rising edge of mclk 1 ? ns t hh3 hold high, mas* from the rising edge of mclk 2.5 ? ns t s1 setup, maddr[6:0] to the rising edge of mclk 1 ? ns t h1 hold, maddr[6:0] from the rising edge of mclk 7.5 ? ns t s2 setup, mdata[7:0] to the rising edge of mclk 1 ? ns t h2 hold, mdata[7:0] from the rising edge of mclk 7.5 ? ns output load = 60 pf on the data bus
5.0 electrical and mechanical specifications cx28250 5.1 timing specifications atm physical interface (phy) devices 5-10 mindspeed technologies ? 28250-dsh-002-c figure 5-5. asynchronous mode, read t iming (high-performance access time) t dislz t enzl t dis t pd t en t pwh t pwl t h t s (high) maddr[6:0] mcs* + mrd* mdata[7:0] mrdy mint* mwr* msyncmode (low) valid 500035_030 (high) macssel
cx28250 5.0 electrical and mechanical specifications atm physical interface (phy) devices 5.1 timing specifications 28250-dsh-002-c mindspeed technologies ? 5-11 table 5-4. asynchronous mode, read timing table (high-performance access time) label description min max unit t pwl pulse width low, (mcs* + mrd*) (2) 2 x clk + 15 ns (1) ?ns t pwh pulse width high, (mcs* +mrd*) clk + 15 ns (1) ?ns t s setup, maddr[6:0] to the falli ng edge of (mcs* + mrd*) 2 ? ns t h hold, maddr[6:0] from the rising edge of (mcs* + mrd*) 7 ? ns t en enable, mdata[7:0] from the falli ng edge of (mcs* + mrd*) 2 13 ns t pd propagation delay, mdata[7:0] fr om the falling edge of (mcs* + mrd*) ? 2* clk + 10 (1)(3) ns t dis disable, mdata[7:0] from the ri sing edge of (mcs* + mrd*) 2 13 ns t enzl enable, mrdy from the falling edge of (mcs* + mrd*) 1 10 ns t dislz disable, mrdy from the rising edge of (mcs* + mrd*) 2 x clk +1 3 x clk +10 ns note(s): (1) due to internal sampling mechanisms used, these times are specif ied in clock cycles rather than absolute values. for these calculations clk equals the peri od of clock selected via the clk pin (either 26 ns or 52 ns; see section 2.6 ). (2) timing starts with either mcs* or mrd*, whichever occurs last. (3) when reading from internal trace buffers, t pd = 19.7 ns.
5.0 electrical and mechanical specifications cx28250 5.1 timing specifications atm physical interface (phy) devices 5-12 mindspeed technologies ? 28250-dsh-002-c figure 5-6. asynchronous mode, write timing t dislz t enzl t pwh t pwl t h1 t h2 t s1 t s2 (high) (low) 500035 _03 1 maddr[6:0] mcs* + mwr* mdata[7:0] mrdy mrd* msyncmode table 5-5. asynchronous mode, write timing table (high-performance access time) label description min max unit t pwl pulse width low, (mcs* + mwr*) (2) 2 x clk + 15 ns (1) ?ns t pwh pulse width high, (mcs* + mwr*) clk + 15 ns (1) ?ns t s1 setup, maddr[6:0] to the falling edge of (mcs* + mwr*) 2 ? ns t h1 hold, maddr[6:0] from the rising edge of (mcs* + mwr*) 7 ? ns t s2 setup, mdata[7:0] from the fa lling edge of (mcs* + mwr*) ? 1 clk (1) ns t h2 hold, mdata[7:0] from the risi ng edge of (mcs* + mwr*) 7 ? ns t enzl enable, mrdy from the falli ng edge of (mcs* + mrd*) 1 10 ns t dislz disable, mrdy from the rising edge of (mcs* + mrd*) 41 70 ns note(s): (1) due to internal sampling mechanisms used, these times are specif ied in clock cycles rather than absolute values. for these calculations clk equals the peri od of clock selected via the clk pin (either 26 ns or 52 ns; see section 2.6 ). (2) timing starts with either mcs* or mrd*, whichever occurs last.
cx28250 5.0 electrical and mechanical specifications atm physical interface (phy) devices 5.1 timing specifications 28250-dsh-002-c mindspeed technologies ? 5-13 5.1.2 transmit utopia interface timing figure 5-7 and table 5-6 define the timing requirements and characteristics of the transmit utopia interface. all times prov ided are in nanos econds. the output load for this interface is 50 pf. note: figure 5-7 shows timing only, it does not imply function. figure 5-7. transmit utopia interface timing diagram t s1 t h1 t s2 t h2 t s3 t h3 t s4 t h4 t s5 t h5 t per t pwh t pwl t en t pd t dis valid valid utxsoc utxenb* utxaddr[4:0] utxdata[15:0] utxprty utxclav utxclk valid 500035_034
5.0 electrical and mechanical specifications cx28250 5.1 timing specifications atm physical interface (phy) devices 5-14 mindspeed technologies ? 28250-dsh-002-c table 5-6. transmit utopia interface timing table label description min max unit t s1 setup, utxsoc to the ri sing edge of utxclk 4 ? ns t s2 setup, utxenb* to the rising edge of utxclk 4 ? ns t s3 setup, utxaddr[4:0] to the rising edge of utxclk 4 ? ns t s4 setup, utxdata[15:0] to th e rising edge of utxclk 4 ? ns t s5 setup, utxprty to the rising edge of utxclk 4 ? ns t h1 hold, utxsoc from the ri sing edge of utxclk 1 ? ns t h2 hold, utxenb* from the rising edge of utxclk 1 ? ns t h3 hold, utxaddr[4:0] from the rising edge of utxclk 1 ? ns t h4 hold, utxdata[15:0] from th e rising edge of utxclk 1 ? ns t h5 hold, prty from the rising edge of utxclk 1 ? ns t en enable, utxclav from the rising edge of utxclk 1 4 ns t pd propagation delay, utxclav from the rising edge of utxclk 1 9 ns t dis disable, utxclav from the rising edge of utxclk 1 4 ns t per period, utxclk 20 ? ns t pwh pulse width high, utxclk 8 ? ns t pwl pulse width low, utxclk 8 ? ns
cx28250 5.0 electrical and mechanical specifications atm physical interface (phy) devices 5.1 timing specifications 28250-dsh-002-c mindspeed technologies ? 5-15 5.1.3 receive utopia interface timing figure 5-8 and table 5-7 define the timing requirements and characteristics of the receive utopia interface. all times prov ided are in nanoseconds. the output load for this interface is 50 pf. note: figure 5-8 shows timing only, it does not imply function. figure 5-8. receive utopia interface timing diagram t s1 t h1 t s2 t h2 t per t pwh t pwl t en1 t pd1 t dis1 t en2 t pd2 t dis2 t en3 t pd3 t dis3 t en4 t pd4 t dis4 valid urxenb* urxaddr[4:0] urxsoc urxdata[15:0] urxprty urxclav urxclk 500035_035
5.0 electrical and mechanical specifications cx28250 5.1 timing specifications atm physical interface (phy) devices 5-16 mindspeed technologies ? 28250-dsh-002-c table 5-7. receive utopia interface timing table label description min max unit t s1 setup, urxenb* to the rising edge of urxclk 4 ? ns t s2 setup, urxaddr[4:0] to the rising edge of urxclk 4 ? ns t h1 hold, urxenb* from the ri sing edge of urxclk 1 ? ns t h2 hold, urxaddr[4:0] from the rising edge of urxclk 1 ? ns t en1 enable, urxsoc from the ri sing edge of urxclk 2 10 ns t pd1 propagation delay, urxsoc from the rising edge of urxclk 1 10 ns t dis1 disable, urxsoc from the ri sing edge of urxclk 2 10 ns t en2 enable, urxdata[15:0] from th e rising edge of urxclk 2 10 ns t pd2 propagation delay, urxd ata[15:0] from the risi ng edge of urxclk 1 12 ns t dis2 disable, urxdata[15:0] from th e rising edge of urxclk 2 10 ns t en3 enable, urxprty from the ri sing edge of urxclk 2 10 ns t pd3 propagation delay, urxprty from the rising edge of urxclk 1 12 ns t dis3 disable, urxprty from the rising edge of urxclk 2 10 ns t en4 enable, urxclav from the rising edge of urxclk 1 8 ns t pd4 propagation delay, urxclav from the rising edge of urxclk 1 10 ns t dis4 disable, urxclav from the rising edge of urxclk 1 8 ns t per period, urxclk 20 ? ns t pwh pulse width high, urxclk 8 ? ns t pwl pulse width low, urxclk 8 ? ns
cx28250 5.0 electrical and mechanical specifications atm physical interface (phy) devices 5.1 timing specifications 28250-dsh-002-c mindspeed technologies ? 5-17 5.1.4 jtag interface timing figure 5-9 and table 5-8 define the timing requirements and characteristics of the jtag interface. figure 5-9. jtag timing diagram t s1 t h1 t s2 t h2 t rec t pwh t pwl t en t pd t dis valid valid valid tdo tdi tms tck trst* t per valid 500035_036 table 5-8. jtag timing table symbol description min max unit t en enable, tdo from the falling edge of tck 0.6 5 ns t pd propagation delay, tdo from th e falling edge of tck 0.6 5 ns t s1 setup, tdi to the rising edge of tck 2 ? ns t s2 setup, tms to the ri sing edge of tck 2 ? ns t h1 hold, tdi from the risi ng edge of tck 6 ? ns t h2 hold, tms from the rising edge of tck 6 ? ns t pwh pulse width high, tck 16 ? ns t pwl pulse width low, tck 16 ? ns t dis disable, tdo from the fa lling edge of tck 0.8 5 ns t rec recovery time, tck from the rising edge of trst* 2.5 ? ns t per period, tck 40 ? ns
5.0 electrical and mechanical specifications cx28250 5.1 timing specifications atm physical interface (phy) devices 5-18 mindspeed technologies ? 28250-dsh-002-c 5.1.5 one-second interface timing figure 5-10 and table 5-9 show the timing requirements and characteristics of the one-second interface. these output valu es are measured into a 20 pf load. figure 5-10. one-second timing diagram t pdlh t pdhl 8khzin onesecout onesecin t per t pwh1 t pwl t pwh2 500035_037 table 5-9. one-second timing table symbol description min max unit t per period, 8khzin 125 125 s t pwh1 pulse width high, 8khzin 10 ? ns t pwl pulse width low, 8khzin 10 ? ns t pdlh propagation delay low-to-high, onesecout from the rising edge of 8khzin 29 ns t pdhl propagation delay high-to-low, onesecout from the rising edge of 8khzin 26 ns t pwh2 pulse width high, onesecin 22 ? ns
cx28250 5.0 electrical and mechanical specifications atm physical interface (phy) devices 5.1 timing specifications 28250-dsh-002-c mindspeed technologies ? 5-19 5.1.6 data link timing figure 5-11 and table 5-10 show the receive timing requirements and characteristics for the data link. figure 5-12 and table 5-11 show the transmit timing requirements and characteristics for the data link. figure 5-11. data link receive timing diagram 500035 _037a data link indicator (b4) data link rx clock (a4) data link rx data (c4) t setup t pd1 t pwl t pwh t per t pd2 d1,b7 d3,b2 d3,b0 d1,b6 d1,b5 d3,b1 d4,b7 d4,b6 d4,b5 d12,b2 d12,b1 d12,b0 d1,b7 table 5-10. data link receive timing table symbol description min typical max unit t pwh time for clock output high (average) ? 1030 ? ns t pwl time for clock output low ? 50 ? ns t pd1 propagation delay: ri sing edge of sync to next falling edge of clock ? 825 ? ns t pd2 propagation delay: falling edge of sync to next falling edge of clock ? 852 ? ns t setup setup time: clock to data valid ? 50 ? ns t per period ? 125,000 ? ns
5.0 electrical and mechanical specifications cx28250 5.1 timing specifications atm physical interface (phy) devices 5-20 mindspeed technologies ? 28250-dsh-002-c figure 5-12. data link transmit timing diagram d1,b7 d3,b2 d3,b0 d1,b6 d1,b5 d3,b1 d4,b7 d4,b6 d4,b5 d12,b2 d12,b1 d12,b0 d1,b7 500035 _037b data link indicator (c3) data link tx clock (a3) data link tx data (txdl, p3) t setup t pd t pd t pwh t pwl t hold table 5-11. data link transmit timing table symbol description min typical max unit t pwh time for clock output high ? 50 ? ns t pwl time for clock output low ? 1030 ? ns t pd propagation delay: edge of i ndicator to rising edge of clock ? 780 ? ns t setup setup time: data valid to rising edge of clock ? 15 ? ns t hold hold time: clock edge to data invalid ? 15 ? ns
cx28250 5.0 electrical and mechanical specifications atm physical interface (phy) devices 5.2 absolute maximum ratings 28250-dsh-002-c mindspeed technologies ? 5-21 5.2 absolute maximum ratings the absolute maximum ratings listed in table 5-10 are the maximum stresses that the device can tolerate without risking permanent damage. these ratings are not typical of normal operation of the device . exposure to absolute maximum rating conditions for extended periods of time may affect the device?s reliability. this device should be handled as an esd-sensitive device. voltage on any signal pin that exceeds the power supply voltage by more than +0.5 v ca n induce destructive latchup. table 5-12. absolute maximum ratings parameter value supply voltage ?0.5 to +4.6 v v gg pin +6.0 v storage temperature ?40 c to 125 c lead temperature +240 c for 10 sec. junction temperature +125 c static discharge volt age?human body model 1500 v @ 25 c static discharge voltage?charged device model 400 v @ 25 c latch-up current 400 ma @ 25 c fit rate value tbd ja 40 c/w with no airflow, 36 c/w at 1.5 m/s airflow jc 6.5 c/w
5.0 electrical and mechanical specifications cx28250 5.3 dc characteristics atm physical interface (phy) devices 5-22 mindspeed technologies ? 28250-dsh-002-c 5.3 dc characteristics this section describes the dc characteristics of the cx28250. table 5-13 lists general dc characteristics. table 5-13. dc characteristics parameter min typical max unit conditions input low voltage (vil) ? ? ? ? ? 5 v-tolerant ttl 0 ? 0.8 vdc ? ? ???? ? input high voltage (vih) ? ? ? ? ? 5 v-tolerant ttl 2.0 ? 5.25 vdc ? ? ???? ? ttl output low voltage (vol) ? ? 0.4 vdc i oh = 4.0 ma ttl output high voltage (voh) 2.4 ? ? vdc i oh = 1500 a pullup resistance (rpu) (all pins except lpllclk) 35 ? 140 k ? input leakage current (all pins except lpllclk) -10 ? 10 a vin = pwr or gnd lpllclk pull-down resistance 85 ? 370 k ? vdd + 5% three-state output leakage current -10 ? 10 a vout = pwr or gnd input capacitance ? ? 7 pf ? output capacitance ? ? 7 pf ? bidirectional capacitance ? ? 7 pf ? operating power consumption processing cells ? 530 ? mw transmitter driving 50 ? pecl load utopia tx/rx clock at 22 mhz operating current ? 160 ? ma ? note(s): all outputs are ttl drive levels and can be used with 3 v cmos or 5 v ttl logic.
cx28250 5.0 electrical and mechanical specifications atm physical interface (phy) devices 5.3 dc characteristics 28250-dsh-002-c mindspeed technologies ? 5-23 5.3.1 pecl?input the pecl input dc characteristics are shown in table 5-14 . 5.3.2 pecl?output the pecl output dc char acteristics are shown in table 5-15 . 5.3.3 single-ended pecl input (sigdet) the single-ended pecl input dc characteristics are shown in table 5-16 . table 5-14. pecl-input dc characteristics symbol parameter min. typical max. conditions v ref mid-point of v ih and v il ? vdd ? 1.4 ? ? v ih input voltage (high level) vdd ? 1.2 vdd ? 1.0 vdd ? 0.9 ? v il input voltage (low level) vdd ? 2.0 vdd ? 1.75 vdd ? 1.6 ? v diff differential voltage 200 400 800 mv note(s): all pecl voltages are referenced to ground. table 5-15. pecl-output dc characteristics symbol parameter min. typical max. conditions v diff differential voltage 700 750 1000 mv v ol static dc low level vdd ? 2.1 vdd ? 1.75 vdd ? 1.7 (1) v oh static dc high level vdd ? 1.2 vdd ? 1.0 vdd ? 0.80 (1) note(s): (1) 100 ? resistor between outputs. table 5-16. single-ended pecl table symbol parameter minimum typical maximum v ih ? 2.13 v ? ? v il ? ? ? 1.95 v i ih ?? ? 10 a i il ? -10 ??
5.0 electrical and mechanical specifications cx28250 5.4 cx28250 electrical and mechanical description atm physical interface (phy) devices 5-24 mindspeed technologies ? 28250-dsh-002-c 5.4 cx28250 electrical and mechanical description this section describes the mechanical characteristics of the cx28250.
cx28250 5.0 electrical and mechanical specifications atm physical interface (phy) devices 5.4 cx28250 electrical and mechanical description 28250-dsh-002-c mindspeed technologies ? 5-25 5.4.1 cx28250 mechanical drawing the various views of the cx28250 mechanical drawing are shown in figure 5-13 , figure 5-14 , and figure 5-15 . figure 5-13. 156-pin ball gate array (bga) package?top and side views 500035_037c a1 ball pad corner a1 ball pad indicator, 1.0 dia. optional 45? chamfer 4 places 30? typ seating plane 15.00 13.00 0.80 0.05 dim "a" dim "b" 0.40 0.10 +0.70 0.00 0.500 0.10 13.00 +0.70 0.00 15.00 0.35 0.25 0.15 0.30 0.10 zx z x z y 7 5 6 s s y s s top view side view dim "a" dim "b" no. layers pbga thickness schedule 4 1.76 0.21 0.56 0.06 note: all units are mm.
5.0 electrical and mechanical specifications cx28250 5.4 cx28250 electrical and mechanical description atm physical interface (phy) devices 5-26 mindspeed technologies ? 28250-dsh-002-c figure 5-14. 156-pin ball gate array (bga) package?bottom view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a b c d e f g h j k l m n p 1.00 1.00 1.00 ref. 1.00 ref. 500035_044 a1 ball pad corner 0.50 r, 3 places bottom view (dimentions in millimeters) figure 5-15. land patterns for the cx28250 p p d p (mm) d (mm) rs8228 1.27 0.60 cx28250 1.00 0.50 cx28236 1.27 0.60 cx28237 1.27 0.60 land pattern layout dimensions conexant systems bga packages 500035_046
28250-dsh-002-c mindspeed technologies ? a-1 a appendix a pecl applications this section provides application examples for the pecl interface. a.1 cx28250 to 3.3 v pmd if using a pmd that does not output a low level voltage (sink current during a logic 0) the network shown in figure a-1 should be used. resistors r 1 and r 2 must satisfy two equations. first, since the vcc supply and ground both provide a path for the high frequency current, resistors r 1 and r 2 are treated as if they were in parallel, ignoring the extremely high impedance of the pecl input. where: z 0 is the characteristic impedance of th e circuit board trace. this matching network should be as close to the destina tion as possible. an overview of circuit board trace impedance is given in section 3.2.2 . second, r 1 and r 2 form a voltage divider network that establishes the low-level voltage. for example: if z 0 = 50 ?, v il = 1.65 v, and v cc = 3.3 v then r 1 = 100 ? and r 2 = 100 ?. z 0 r 1 r 2 r 1 r 2 + () ----------------------- = v il v cc r 2 r 1 r 2 + () ----------------------- =
appendix a pecl applications cx28250 a.1 cx28250 to 3.3 v pmd atm physical interface (phy) devices a-2 mindspeed technologies ? 28250-dsh-002-c figure a-1. cx28250 to 3.3 v pmd diagram note(s): c 1 = 220 pf rf grade capacitor 3.3 v pecl outputs +3.3 v c 1 3.3 v pecl inputs + + ? ? r 1 r 2 pmd cx28250 500035_022 r 1 r 2
cx28250 appendix a pecl applications atm physical interface (phy) devices a.2 cx28250 to 5 v pmd inputs 28250-dsh-002-c mindspeed technologies ? a-3 a.2 cx28250 to 5 v pmd inputs when connecting the cx28250 3.3 v pecl outputs to 5 v pecl inputs, ensure that the lines are properly terminated. in addition, the input voltage levels must be shifted. both can be accomplished by the circuits in figure a-3 . the termination impedance is given by: the outputs of the cx28250 need to be biased near v ref (2.0 v). therefore: furthermore, v ih and v il going to the pmd are given by: where: v oh is the high level output from the cx28250 and: using the values: r 3 = 75 ? r 4 = 52 ? r 5 = 82.5 ? v oh = 2.5 v results in: v ref = 1.968 v v ih = 3.52 v v il = 3.03 v these values are well with in the desired ranges and provide adequate voltage differential for the pmd. z 0 r 3 r 4 + () r 5 r 3 r 4 r 5 ++ () ------------------------------------ = v ref v cc r 5 r 3 r 4 r 5 ++ () ------------------------------------ = v ih v cc v oh ? () r 4 r 3 r 4 + () ---------------------------------------- - v oh + = v il r 3 r 4 + () v cc r 3 r 4 r 5 ++ () -------------------------------------- =
appendix a pecl applications cx28250 a.2 cx28250 to 5 v pmd inputs atm physical interface (phy) devices a-4 mindspeed technologies ? 28250-dsh-002-c figure a-2. cx28250 pecl to 5 v pecl (capacitive coupled) interface 500035_055 note: 1. the 100 ohm resistor is built in the cx28250 for the lrxdata+ and lrxdata- termination. 2. the ltxdata+ and ltxdata- outputs are internally biased and therefore do not require external bias resistors. 3. the termination resistors on the lsigdet input are necessary only for transceivers with a pecl level signal detect (sd) output. the resistors should have a tolerance of 1%. optical transceiver rd- rd+ z=50 z=50 270 270 z=50 z=50 cx28250 td+ td- sd lrxdata- lrxdata+ ltxdata+ ltxdata- lsigdet place near transceiver 5.0 v 3.3 v 130 place near cx28250 130 82 82 3.3v 3.3v 0.1uf 0.1uf 130 82 5.0v 130 82 5.0v 51.1 78.7 5.0v 82.5 place near transceiver 0.1uf 0.1uf 100 place near cx28250
cx28250 appendix a pecl applications atm physical interface (phy) devices a.2 cx28250 to 5 v pmd inputs 28250-dsh-002-c mindspeed technologies ? a-5 figure a-3. cx28250 to 5 v pmd inputs diagram c 1 r 4 r 3 r 3 r 5 r 5 r 4 500035_023 3.3 v pecl outputs +5 v 5 v pecl inputs + + ? ? cx28250 pmd
appendix a pecl applications cx28250 a.3 cx28250 to 5 v pmd outputs atm physical interface (phy) devices a-6 mindspeed technologies ? 28250-dsh-002-c a.3 cx28250 to 5 v pmd outputs the recommended termination and level shifting circuit for connecting 5.0 v pecl outputs to the cx28250 3.3 v pecl inputs is illustrated in figure a-4 . the line termination impedance is demonstrated in the following equation: the outputs of the 5 v pecl should be biased at around v ref , which is generally v cc -2.0. therefore: if you select: r 6 = 82.5 ? r 7 = 56 ? r 8 = 75 ? z 0 = 50 ? then the low level input voltage, v il , going to the cx28250 is: this is well below the maximum of v ref -0.06 v. given that the v oh for 5 v pecl is around v cc -1.3 v, then v ih for the cx28250 is: not only is this above the minimum (v ref +0.06), but it provides a differential of 340 mv. z 0 r 7 r 8 + () r 6 r 6 r 7 r 8 ++ () ------------------------------------ = 3.0 v r 7 r 8 + () v cc r 6 r 7 r 8 ++ () -------------------------------------- = v il 5.0 r 8 r 6 r 7 r 8 ++ () ------------------------------------ 1 . 7 6 v == v ih 3.7 r 8 r 7 r 8 + () ----------------------- 2 . 1 v ==
cx28250 appendix a pecl applications atm physical interface (phy) devices a.3 cx28250 to 5 v pmd outputs 28250-dsh-002-c mindspeed technologies ? a-7 the ideal pecl layout is illustrated in figure a-5 . figure a-4. cx28250 to 5 v pmd outputs diagram figure a-5. pecl layout diagram (3.3 v inputs) c 1 r 7 r 6 r 8 r 6 r 8 r 7 500035_024 3.3 v pecl inputs +5 v 5 v pecl outputs ? ? cx28250 pmd + + pecl inputs ? + +5 v 3.3 v gnd 500035_025
appendix a pecl applications cx28250 a.3 cx28250 to 5 v pmd outputs atm physical interface (phy) devices a-8 mindspeed technologies ? 28250-dsh-002-c
28250-dsh-002-c mindspeed technologies ? b-1 b appendix b related standards the following is a list of standards relevant to the cx28250. atm forum uni specification 94/0317: atm forum?atm user network interface spec. v3.1, sept. 1994 atm forum utopia leve l 1 specification, ver. 2.01, af-phy-0017.000 atm forum utopia level 2 specification, ver. 1.0, af-phy-0039.000 atm forum?atm-phy/95-0766r2: wire specification bellcore specification t1s1/92-185 bellcore spec. gr-253-core: synchronous optical network (sonet) transport systems: common generi c criteria, issue 1, dec. 1994 itu recommendation i.432, ?b-isd n user network interface?physical interface specification,? june 1990 itu recommendation g.707, ?network node interface for the synchronous digital hierarchy (sdh),? 1996 itu recommendation g.709, ?synchronous multiplexing structure,? 1990 itu recommendation g.804, ?atm cell mapping into pleisiochronous digital hierarchy (pdh)? itu recommendation q.921: isdn user-network interface data link layer specification, 03/93 ansi t1.105: synchronous optical network (sonet)?basic description including multiplex structure, rates and formats, 1995 ansi t1.627-1993: broadband isdn?atm layer functionality and specification i.610: b-isdn operation and main tenance principles and functions gr-1248: generic requirements for operation of atm network elements all of these documents can be obtained from the following companies: bellcore customer service 8 corporate place - room 3c-183 piscataway, nj 08854-4156 1-800-521-core pci special in terest group p.o. box 14070 portland, or 97214 1-800-433-5177 1-503-797-4207 for itu documents: omnicom phillips business information 1201 seven locks road, suite 300 potomac, md 20854 1-800 omnicom (666-4266) atm forum the atm forum 303 vintage park drive foster city, ca 94404-1138 ansi 11 west 42nd street new york, ny 10036 1-212-642-4900
appendix b related standards cx28250 atm physical interface (phy) devices b-2 mindspeed technologies ? 28250-dsh-002-c
28250-dsh-002-c mindspeed technologies ? c-1 c appendix c register summary this appendix is a quick reference to the most commonly used cx28250 registers. it lists the bits that are contained in each register.
appendix c register summary cx28250 atm physical interface (phy) devices c-2 mindspeed technologies ? 28250-dsh-002-c table c-1. cx28250 register summary (1 of 9) 76543210 signal degrade interrupt signal fail interrupt reserved reserved reserved reserved reserved psbf interrupt apsint (0x42) aps interrupt indication status register page 12 76543210 signal degrade threshold(0) signal degrade threshold(1) signal degrade threshold(2) signal degrade threshold(3) signal fail threshold(3) signal fail threshold(2) signal fail threshold(1) signal fail threshold(0) apsthresh (0x09) aps threshold control register page 13 76543210 section bip error counter(8) section bip error counter(9) section bip error counter(10) section bip error counter(11) section bip error counter(15) section bip error counter(14) section bip error counter(13) section bip error counter(12) b1cnth (0x55) section bip error counter (high byte) page 13 76543210 section bip error counter(0) section bip error counter(1) section bip error counter(2) section bip error counter(3) section bip error counter(7) section bip error counter(6) section bip error counter(5) section bip error counter(4) b1cntl (0x54) section bip error counter (low byte) page 14 76543210 line bip error counter(16) line bip error counter(17) reserved reserved reserved reserved reserved reserved b2cnth (0x52) line bip error counter (high byte) page 14 76543210 line bip counter(0) line bip counter(1) line bip counter(2) line bip counter(3) line bip counter(7) line bip counter(6) line bip counter(5) line bip counter(4) b2cntl (0x50) line bip error counter (low byte) page 15 76543210 line bip counter(8) line bip counter(9) line bip counter(10) line bip counter(11) line bip counter(15) line bip counter(14) line bip counter(13) line bip counter(12) b2cntm (0x51) line bip error counter (mid byte) page 15 76543210 path bip error counter(8) path bip error counter(9) path bip error counter(10) path bip error counter(11) path bip error counter(15) path bip error counter(14) path bip error counter(13) path bip error counter(12) b3cnth (0x57) path bip error counter (high byte) page 16 76543210 path bip error counter(0) path bip error counter(1) path bip error counter(2) path bip error counter(3) path bip error counter(7) path bip error counter(6) path bip error counter(5) path bip error counter(4) b3cntl (0x56) path bip error counter (low byte) page 16 76543210 reserved reserved reserved reserved reserved reserved reserved reserved cdrtest (0x70?0x73) page 27
cx28250 appendix c register summary atm physical interface (phy) devices 28250-dsh-002-c mindspeed technologies ? c-3 table c-1. cx28250 register summary (2 of 9) 76543210 cell loss priority payload type virtual channel identifier virtual path identifier dishec transmit hec coset transmit cell scrambler (x 43 +1) generic flow control cgen (0x04) cell generation control register page 18 76543210 utopia loopback line loopback source loopback transmit clock select (0) transmit clock receive clock external clock recovery transmit clock select (1) clkrec (0x01) clock recovery control register page 19 76543210 hec error counter(0) hec error counter(1) hec error counter(2) hec error counter(3) hec error counter(7) hec error counter(6) hec error counter(5) hec error counter(4) corrcnt (0x4d) corrected hec error counter page 20 76543210 loss of cell delineation cell receiver hec checking hec correction reject header deletion of idle cells enable receive cell scrambler enable receive hec coset cval (0x08) cell validation control register page 20 76543210 signal degrade interrupt signal failure interrupt reserved reserved reserved reserved reserved psbf interrupt enaps (0x3a) aps interrupt mask control register page 21 76543210 non-zero gfc received interrupt non-matching cell received interrupt idle cell received interrupt cell received interrupt loss of cell delineation interrupt hec error detected interrupt hec error corrected interrupt reserved encellr (0x39) receive cell interrupt mask control register page 21 76543210 reserved reserved reserved cell sent interrupt parity error interrupt start of cell alignment error interrupt transmit fifo overflow interrupt receive fifo overflow interrupt encellt (0x38) transmit cell interrupt mask control register page 22 76543210 loss of cell delineation path loss of pointer path alarm indication signal line alarm indication signal loss of signal loss of lock out of frame loss of frame enlfout (0x6e) enable line fail output control register page 22 76543210 s1 byte change interrupt z0 1 , z0 2 , or z2 change interrupt line rei error interrupt b2 error interrupt lop interrupt k1/k2 ais-l interrupt rdi-l interrupt enlin (0x36) receive line interrupt mask control register page 23 76543210 loss of cell delineation path loss of pointer path alarm indication signal line alarm indication signal loss of signal loss of lock out of frame loss of frame enpfout (0x6f) enable path output control register page 23
appendix c register summary cx28250 atm physical interface (phy) devices c-4 mindspeed technologies ? 28250-dsh-002-c table c-1. cx28250 register summary (3 of 9) 76543210 enhanced rdi path trace interrupt uneq-p interrupt plm-p interrupt ais-p interrupt rdi-p interrupt b3 error interrupt path rei interrupt enpth (0x37) receive path interrupt mask control register page 24 76543210 receive frame scrambler section trace interrupt section bip error interrupt loss of frame interrupt signal detect interrupt loss of lock interrupt loss of signal interrupt out of frame interrupt ensec (0x35) receive section interrupt mask control register page 24 76543210 transmit cell interrupt receive cell interrupt aps interrupt sonet overhead interrupt sonet section interrupt sonet line interrupt sonet path interrupt one-second interrupt ensumint (0x34) summary interrupt mask control register page 25 76543210 reserved hec byte b3 bip byte b2-3 bip byte a1 byte inverter b1 bip byte b2-1 bip byte b2-2 bip byte errins (0x06) error insertion control register page 25 76543210 error pattern(0) error pattern(1) error pattern(2) error pattern(3) error pattern(7) error pattern(6) error pattern(5) error pattern(4) errpat (0x07) error pattern control register page 26 76543210 master reset logic reset status output pin mode block error mode reserved enable interrupt status latching counter latching gen (0x00) general control register page 27 76543210 receive idle cell mask(0) receive idle cell mask(1) receive idle cell mask(2) receive idle cell mask(3) receive idle cell mask(7) receive idle cell mask(6) receive idle cell mask(5) receive idle cell mask(4) idlmsk1-4 (0x30-33) receive idle cell mask control register 1-4 page 28 76543210 transmit idle cell payload(0) transmit idle cell payload(1) transmit idle cell payload(2) transmit idle cell payload(3) transmit idle cell payload(7) transmit idle cell payload(6) transmit idle cell payload(5) transmit idle cell payload(4) idlpay (0x05) transmit idle cell payload control register page 30 76543210 line rei error counter(16) line rei error counter(17) reserved reserved reserved reserved reserved reserved lfcnth (0x5a) line rei error counter (high byte) page 30 76543210 line rei error counter(0) line rei error counter(1) line rei error counter(2) line rei error counter(3) line rei error counter(7) line rei error counter(6) line rei error counter(5) line rei error counter(4) lfcntl (0x58) line rei error counter (low byte) page 31
cx28250 appendix c register summary atm physical interface (phy) devices 28250-dsh-002-c mindspeed technologies ? c-5 table c-1. cx28250 register summary (4 of 9) 76543210 line rei error counter(8) line rei error counter(9) line rei error counter(10) line rei error counter(11) line rei error counter(15) line rei error counter(14) line rei error counter(13) line rei error counter(12) lfcntm (0x59) line rei error counter (mid byte) page 31 76543210 s1 byte change interrupt z0 1 , z0 2 , or z2 change interrupt line bip error interrupt b2 error interrupt lop interrupt k1/k2 interrupt ais-l interrupt rdi-l interrupt linint (0x3e) receive line interrupt indication status register page 32 76543210 locd event counter(0) locd event counter(1) locd event counter(2) locd event counter(3) locd event counter(7) locd event counter(6) locd event counter(5) locd event counter(4) locdcnt (0x4c) locd event counter page 32 76543210 non-matching cell counter(8) non-matching cell counter(9) non-matching cell counter(10) non-matching cell counter(11) non-matching cell counter(15) non-matching cell counter(14) non-matching cell counter(13) non-matching cell counter(12) noncnth (0x5f) non-matching cell counter (high byte) page 33 76543210 non-matching cell counter(0) non-matching cell counter(1) non-matching cell counter(2) non-matching cell counter(3) non-matching cell counter(7) non-matching cell counter(6) non-matching cell counter(5) non-matching cell counter(4) noncntl (0x5e) non-matching cell counter (low byte) page 33 76543210 oof event counter(0) oof event counter(1) oof event counter(2) oof event counter(3) oof event counter(7) oof event counter(6) oof event counter(5) oof event counter(4) oofcnt (0x4f) oof event counter page 15 76543210 status output on statout(0) status output on statout(1) status output on statout(2) status output on statout(3) status output on statout(7) status output on statout(6) status output on statout(5) status output on statout(4) outstat (0x02) output pin control register page 34 76543210 path rei error counter(8) path rei error counter(9) path rei error counter(10) path rei error counter(11) path rei error counter(15) path rei error counter(14) path rei error counter(13) path rei error counter(12) pfcnth (0x5d) path rei error counter (high byte) page 35 76543210 path rei error counter(0) path rei error counter(1) path rei error counter(2) path rei error counter(3) path rei error counter(7) path rei error counter(6) path rei error counter(5) path rei error counter(4) pfcntl (0x5c) path rei error counter (low byte) page 35 76543210 reserved path trace interrupt uneq-p interrupt plm-p interrupt ais-p interrupt rdi-p interrupt b3 error interrupt path rei interrupt pthint (0x3f) receive path interrupt indication status register page 36
appendix c register summary cx28250 atm physical interface (phy) devices c-6 mindspeed technologies ? 28250-dsh-002-c table c-1. cx28250 register summary (5 of 9) 76543210 signal degrade received signal fail received reserved reserved reserved reserved reserved psbf received rxaps (0x4a) receive aps status register page 36 76543210 receive c2 (bit 8) receive c2 (bit 7) receive c2 (bit 6) receive c2 (bit 5) receive c2 (bit 1) receive c2 (bit 2) receive c2 (bit 3) receive c2 (bit 4) rxc2 (0x18) receive c2 overhead status register page 37 76543210 non-zero gfc received interrupt non-matching cell received interrupt idle cell received interrupt cell received interrupt loss of cell delineation hec error detect hec error correct reserved rxcellint (0x41) receive cell interrupt indication status register page 38 76543210 non-zero gfc received non-matching cell received idle cell received cell received loss of cell delineation uncorrected hec error hec error reserved rxcell (0x49) receive cell status register page 37 76543210 received cell counter(16) received cell counter(17) received cell counter(18) reserved reserved reserved reserved reserved rxcnth (0x66) received cell counter (high byte) page 38 76543210 received cell counter(0) received cell counter(1) received cell counter(2) received cell counter(3) received cell counter(7) received cell counter(6) received cell counter(5) received cell counter(4) rxcntl (0x64) received cell counter (low byte) page 39 76543210 received cell counter(8) received cell counter(9) received cell counter(10) received cell counter(11) received cell counter(15) received cell counter(14) received cell counter(13) received cell counter(12) rxcntm (0x65) received cell counter (mid byte) page 39 76543210 reserved receive g1 (bit 7) receive g1 (bit 6) receive g1 (bit 5) reserved reserved reserved reserved rxg1 (0x19) receive g1 overhead status register page 40 76543210 receive header(0) receive header(1) receive header(2) receive header(3) receive header(7) receive header(6) receive header(5) receive header(4) rxhdr1-4 (0x24-27) receive cell header control register 1-4 page 40 76543210 receive idle cell header(0) receive idle cell header(1) receive idle cell header(2) receive idle cell header(3) receive idle cell header(7) receive idle cell header(6) receive idle cell header(5) receive idle cell header(4) rxidl1-4 (0x2c-2f) receive idle cell header control register 1-4 page 42
cx28250 appendix c register summary atm physical interface (phy) devices 28250-dsh-002-c mindspeed technologies ? c-7 table c-1. cx28250 register summary (6 of 9) 76543210 receive k1 (bit 8) receive k1 (bit 7) receive k1 (bit 6) receive k1 (bit 5) receive k1 (bit 1) receive k1 (bit 2) receive k1 (bit 3) receive k1 (bit 4) rxk1 (0x14) receive k1 overhead status register page 44 76543210 receive k2 (bit 8) receive k2 (bit 7) receive k2 (bit 6) receive k2 (bit 5) receive k2 (bit 1) receive k2 (bit 2) receive k2 (bit 3) receive k2 (bit 4) rxk2 (0x15) receive k2 overhead status register page 45 76543210 receive enable d1-d3 receive enable d4-d12 line rei error line bip error loss of pointer k1/k2 change ais-l rdi-l rxlin (0x46) receive line overhead status register page 45 76543210 receive header mask(0) receive header mask(1) receive header mask(2) receive header mask(3) receive header mask(7) receive header mask(6) receive header mask(5) receive header mask(4) rxmsk1-4 (0x28-2b) receive cell mask control register 1-4 page 46 76543210 reserved reserved uneq-p plm-p ais-p rdi-p b3 error path rei error rxpth (0x47) receive path overhead status register page 48 76543210 receive path trace buffer(0) receive path trace buffer(1) receive path trace buffer(2) receive path trace buffer(3) receive path trace buffer(7) receive path trace buffer(6) receive path trace buffer(5) receive path trace buffer(4) rxpthbuf (0x6b) receive path trace circular buffer page 48 76543210 receive s1 (bit 8) receive s1 (bit 7) receive s1 (bit 6) receive s1 (bit 5) receive s1 (bit 1) receive s1 (bit 2) receive s1 (bit 3) receive s1 (bit 4) rxs1 (0x16) receive s1 overhead status register page 49 76543210 receive frame pulse polarity receive octet clock/receive frame pulse section bip error loss of frame signal detect loss of lock loss of signal out of frame rxsec (0x45) receive section overead status register page 49 76543210 receive section trace buffer(0) receive section trace buffer(1) receive section trace buffer(2) receive section trace buffer(3) receive section trace buffer(7) receive section trace buffer(6) receive section trace buffer(5) receive section trace buffer(4) rxsecbuf (0x6a) receive section trace circular buffer page 50 76543210 receive z0 1 (0) receive z0 1 (1) receive z0 1 (2) receive z0 1 (3) receive z0 1 (7) receive z0 1 (6) receive z0 1 (5) receive z0 1 (4) rxz01 (0x1a) receive section z0 1 overhead register page 50
appendix c register summary cx28250 atm physical interface (phy) devices c-8 mindspeed technologies ? 28250-dsh-002-c table c-1. cx28250 register summary (7 of 9) 76543210 receive z0 2 (0) receive z0 2 (1) receive z0 2 (2) receive z0 2 (3) receive z0 2 (7) receive z0 2 (6) receive z0 2 (5) receive z0 2 (4) rxz02 (0x1b) receive section z0 2 overhead register page 51 76543210 reserved section trace interrupt section bip error interrupt loss of frame interrupt signal detect interrupt loss of lock interrupt loss of signal interrupt out of frame interrupt secint (0x3d) receive section interrupt indication status register page 51 76543210 transmit cell/utopia interrupt receive cell interrupt aps interrupt reserved section interrupt line interrupt path interrupt one-second interrupt sumint (0x3c) summary interrupt indication status register page 52 76543210 transmit c2 (bit 8) transmit c2 (bit 7) transmit c2 (bit 6) transmit c2 (bit 5) transmit c2 (bit 1) transmit c2 (bit 2) transmit c2 (bit 3) transmit c2 (bit 4) txc2 (0x13) transmit c2 overhead control register page 53 76543210 disable idle cell reserved reserved non-idle cell parity error start of cell alignment error transmit fifo overflow receive fifo overflow txcell (0x48) transmit cell status register page 53 76543210 reserved reserved reserved cell sent interrupt parity error start of cell alignment error transmit fifo overflow receive fifo overflow txcellint (0x40) transmit cell interrupt i ndication status register page 54 76543210 transmitted cell counter(16) transmitted cell counter(17) transmitted cell counter(18) reserved reserved reserved reserved reserved txcnth (0x62) transmit cell counter (high byte) page 54 76543210 transmitted cell counter(0) transmitted cell counter(1) transmitted cell counter(2) transmitted cell counter(3) transmitted cell counter(7) transmitted cell counter(6) transmitted cell counter(5) transmitted cell counter(4) txcntl (0x60) transmit cell counter (low byte) page 55 76543210 transmitted cell counter(8) transmitted cell counter(9) transmitted cell counter(10) transmitted cell counter(11) transmitted cell counter(15) transmitted cell counter(14) transmitted cell counter(13) transmitted cell counter(12) txcntm (0x61) transmit cell counter (mid byte) page 55 76543210 transmit header(0) transmit header(1) transmit header(2) transmit header(3) transmit header(7) transmit header(6) transmit header(5) transmit header(4) txhdr1-4 (0x1c-1f) transmit cell header control register 1-4 page 56
cx28250 appendix c register summary atm physical interface (phy) devices 28250-dsh-002-c mindspeed technologies ? c-9 table c-1. cx28250 register summary (8 of 9) 76543210 transmit idle cell header(0) transmit idle cell header(1) transmit idle cell header(2) transmit idle cell header(3) transmit idle cell header(7) transmit idle cell header(6) transmit idle cell header(5) transmit idle cell header(4) txidl1-4 (0x20-23) transmit idle cell header control register 1-4 page 58 76543210 transmit k1 (bit 8) transmit k1 (bit 7) transmit k1 (bit 6) transmit k1 (bit 5) transmit k1 (bit 1) transmit k1 (bit 2) transmit k1 (bit 3) transmit k1 (bit 4) txk1 (0x10) transmit k1 overhead control register page 60 76543210 transmit k2 (bit 8) transmit k2 (bit 7) transmit k2 (bit 6) transmit k2 (bit 5) transmit k2 (bit 1) transmit k2 (bit 2) transmit k2 (bit 3) transmit k2 (bit 4) txk2 (0x11) transmit k2 overhead control register page 60 76543210 automatic line rei automatic line rdi line rdi (k2 byte) line ais stm-1 mode pointer h1/h2 overhead bytes line overhead bip (b2) transmit d4-d12 txlin (0x0d) transmit line overhead control register page 61 76543210 automatic path rdi transmit rdi (bit 7, g1 byte) transmit rdi (bit 6, g1 byte) transmit rdi (bit 5, g1 byte) path trace message (j1) path overhead bip (b3) automatic path rei path ais txpth (0x0e) transmit path overhead control register page 62 76543210 transmit path trace buffer(0) transmit path trace buffer(1) transmit path trace buffer(2) transmit path trace buffer(3) transmit path trace buffer(7) transmit path trace buffer(6) transmit path trace buffer(5) transmit path trace buffer(4) txpthbuf (0x69) transmit path trace circular buffer page 62 76543210 transmit s1 (bit 8) transmit s1 (bit 7) transmit s1 (bit 6) transmit s1 (bit 5) transmit s1 (bit 1) transmit s1 (bit 2) transmit s1 (bit 3) transmit s1 (bit 4) txs1 (0x12) transmit s1 overhead control register page 63 76543210 transmit frame reference polarity transmit clock option transmit overhead data section overhead bip (b1) transmit frame scrambler transmit d1/d2/d3 section trace message (j0) a1/a2 overhead bytes txsec (0x0c) transmit section overhead control register page 63 76543210 transmit section trace buffer(0) transmit section trace buffer(1) transmit section trace buffer(2) transmit section trace buffer(3) transmit section trace buffer(7) transmit section trace buffer(6) transmit section trace buffer(5) transmit section trace buffer(4) txsecbuf (0x68) transmit section trace circular buffer page 64 76543210 transmit z0 1 (0) transmit z0 1 (1) transmit z0 1 (2) transmit z0 1 (3) transmit z0 1 (7) transmit z0 1 (6) transmit z0 1 (5) transmit z0 1 (4) txz01 (0x26c) transmit section z0 1 overhead control register page 64
appendix c register summary cx28250 atm physical interface (phy) devices c-10 mindspeed technologies ? 28250-dsh-002-c table c-1. cx28250 register summary (9 of 9) 76543210 transmit z0 2 (0) transmit z0 2 (1) transmit z0 2 (2) transmit z0 2 (3) transmit z0 2 (7) transmit z0 2 (6) transmit z0 2 (5) transmit z0 2 (4) txz02 (0x6d) transmit section z0 2 overhead control register page 65 76543210 udf2(0) udf2(1) udf2(2) udf2(3) udf2(7) udf2(6) udf2(5) udf2(4) udf2 (0x74) page 65 76543210 hec error counter(0) hec error counter(1) hec error counter(2) hec error counter(3) hec error counter(7) hec error counter(6) hec error counter(5) hec error counter(4) unccnt (0x4e) uncorrected hec error counter page 66 76543210 transmit fifo fill level(0) transmit fifo fill level(1) parity bus width transmit reset receive reset utopia level 2 mode cell handshaking utop1 (0x0a) 76543210 multi-phy address(0) multi-phy address(1) multi-phy address(2) multi-phy address(3) reserved reserved disable rx outputs multi-phy address(4) utop2 (0x0b) utopia control register 2 utopia control register 1 page 66 page 67 76543210 version number(0) version number(1) version number(2) version number(3) part number(3) part number(2) part number(1) part number(0) version (0x03) part number/version status register page 67
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