pin names a0-a12 row address: a0 - a12 column address: a0 - a9 ba0,ba1 bank select address a10/ap auto precharge dq0-dq15 data in/data out cas column address strobe cs0, cs1 chip selects ras row address strobe we data write enable ck, ck differential clock inputs cke0, cke1 clock enables udqs, ldqs data strobe udm, ldm data mask qfc dq fet switch control v dd power supply (+2.5v) vss ground v ddq dq power supply (+2.5v) vss q dq ground v ref reference voltage for inputs n.c. no connect nu not used, electrical connect is present description: the memory stack? series is a family of interchangeable memory modules. the 512 megabit double data rate synchronous dram module is a member of this family which utilizes the space saving lp-stack? tsop stacking technology. the devices are constructed with two 16 meg x 16 ddr sdrams. this 256 megabit based lp-stack? module dpdd32mx16wscy5, has been designed to fit in the same footprint as the 16 meg x 16 ddr sdram tsop monolithic. this allows system upgrade without electrical or mechanical redesign, providing an immediate and low cost memory upgrade solution. features: ? configuration: 32m x 16 (2 banks of 4 meg x 16 bits x 4 banks) ? jedec approved footprint and pinout ? ipc-a-610 manufacturing standards ? package: 66-pin leaded tsop stack the following features are not affected by lp-stack and are provided as reference only. refer to memory oem device specification for details. ? clock frequency is determined by oem memory device used. ? 2.5 volt dq supply ? jedec standard sstl_2 interface for all inputs/outputs ? four bank operation ? programmable burst type: burst length and read latency ? refresh: refer to memory oem specifications ? auto and self refresh this document contains information on a product that is currently released to production at dpac technologies corp. dpac reserves the right to change products or specifications herein without prior notice. 512 megabit cmos ddr sdram dpdd32mx16wscy5 udm/ldm cas we dq0-dq15 cs0 ras ck udqs/ldqs cs1 ck a0-a12 vref cke1 cke0 ba0-ba1 (4 meg x 16 bits x 4 banks) 256 mb ddr sdram (4 meg x 16 bits x 4 banks) qfc 1 functional block diagram advanced components packaging 1 (top view) 60 dq12 vdd 1 2 54 dq8 vddq 3 53 dq1 4 52 vssq dq2 5 51 udqs vssq 6 50 n.c. dq3 7 49 vref 8 48 vss vddq 9 47 dq5 10 46 ck dq6 11 45 ck vssq 12 44 cke0 dq7 13 43 cke1 n.c. 14 42 a12 vddq 15 41 a11 ldqs 16 40 a9 n.c. 17 39 a8 vdd 18 38 a7 *nu/qfc 19 37 a6 ldm 20 36 a5 we 21 35 a4 cas 22 34 vss ras 23 59 dq11 cs0 24 58 vssq cs1 25 57 dq10 ba0 26 56 dq9 ba1 27 55 vddq dq4 dq0 udm n.c. 33 vdd 32 a3 31 a2 30 a1 29 a0 28 a10/ap vddq 61 dq13 62 dq14 63 vssq 64 dq15 65 vss 66 pin-out diagram 30a246-00 rev. d 6/02 * this pin is a no connect for some manufacturers.
* contact your sales representative for supplier and manufacturer codes. note: 1. ac parameters of base memory are unchanged from device manufacturer?s specifications. 2. dc parameters may be affected by stacking. please refer to application note 53a004-00 for further information. 30a246-00 rev. d 6/02 2 dpac technologies products & services for the integration age 7321 lincoln way, garden grove, ca 92841 te l 714 898 0007 fax 714 897 1772 www.dpactech.com nasdaq: dpac ?2002 dpac technologies, all rights reserved. dpac technologies?, memory stack?, system stack?, cs stack? are trademarks of dpa c technologies corp. dpdd32mx16wscy5 512 megabit cmos ddr sdram mechanical drawing 1 .015 [.18] .0256 [.65] .102 max pin 1 index top view side view bottom view end view .502.008 .885.010 .427 [10.85] .417 [10.59] .527 [13.39] .517 [13.13] .0256 [.65] bsc .016 [.41] standard tsop pad layout is acceptable, however, when possible, the following pad layout is recommended for optimal manufacture and inspection. see application note 53a001-00 for further information. [12.75.20] [22.48.25] [2.59 max] .819 [20.80] bsc .020 [.51] typ typ mechanical drawing 20 15 dp xx - cas double data rate synchronous dram prefix cas latency 1.5 cas latency 2.0 dd 32m x 16 y5 package memory desig memory type memory module without support logic depth width desig w 256 megabit based stackable tsop manufacturer code * xx - mfr id supplier dp supplier code * i/o type s sstl inputs/outputs width device c x16 memory based cas latency 2.5 25 cycle xx time latency 60 6ns (166mhz) 7ns (143mhz) 7.5ns (133mhz) 8ns (125mhz) 10ns (100mhz) 10 75 08 70
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