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1 features ? 20ns maximum (3.3 volt su pply) address access time ? asynchronous operation for compatibility with industry- standard 512k x 8 srams ? ttl compatible inputs and output levels, three-state bidirectional data bus ? operational environment: - total dose: 50 krads(si) - sel immune 110 mev-cm 2 /mg - seu let th (0.25) = 52 cm 2 mev - saturated cross section 2.8e-8 cm 2 /bit -< 1.1e-9 errors/bit-day, adams 90% worst case environment geosynchronous orbit ? packaging: - 36-lead ceramic fl atpack (3.831 grams) ? standard microcircuit drawing 5962-99607 - qml q and v compliant part introduction the ut8q512e radtol product is a high-performance cmos static ram organized as 524,288 words by 8 bits. easy memory expansion is provided by an active low chip enable (e ), an active low output enable (g ), and three-state drivers. writing to the device is accompli shed by taking chip enable (e ) and write enable (w ) inputs low. data on the eight i/o pins (dq 0 through dq 7 ) is then written into the location specified on the address pins (a 0 through a 18 ). reading from the device is accomplished by taki ng chip enable (e ) and output enable (g ) low while forcing write enable (w ) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. the eight input/output pins (dq 0 through dq 7 ) are placed in a high impedance state when th e device is deselected (e high), the outputs are disabled (g high), or during a write operation (e low and w low). standard products ut8q512e 512k x 8 radtol sram data sheet november 11, 2008 memory array 1024 rows 512x8 columns pre-charge circuit clk. gen. row select a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 i/o circuit column select data control clk gen. a10 a11 a12 a13 a14 a15 a16 a17 a18 dq 0 - dq 7 w g e figure 1. ut8q512e sram block diagram
2 pin names device operation the ut8q512e has three control inputs called chip enable (e ), write enable (w ), and output enable (g ); 19 address inputs, a(18:0); and eight bidirectional data lines, dq(7:0). e controls device selection, active, and standby modes. asserting e enables the device, causes i dd to rise to its active value, and decodes the 19 address inputs to select one of 524,288 words in the memory. w controls read and write oper ations. during a read cycle, g must be asserted to enable the outputs. table 1. device operation truth table notes: 1. ?x? is defined as a ?don?t care? condition. 2. device active; outputs disabled. read cycle a combination of w greater than v ih (min) and e less than v il (max) defines a read cycle. r ead access time is measured from the latter of chip enable, output enable, or valid address to valid data output. sram read cycle 1, the address access in figure 4a, is initiated by a change in address inputs while the chip is enabled with g asserted and w deasserted. valid data appears on data outputs dq(7:0) after the specified t av q v is satisfied. outputs remain active throughout the entire cycle. as long as chip enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time (t avav ). sram read cycle 2, the chip enable - controlled access in figure 4b, is initiated by e going active while g remains asserted, w remains deasserted, and the addresses remain stable for the entire cycle. after the specified t etqv is satisfied, the eight-bit word addressed by a(18:0) is accessed and appears at the data outputs dq(7:0). sram read cycle 3, the output enable - controlled access in figure 4c, is initiated by g going active while e is asserted, w is deasserted, and the addresse s are stable. read access time is t glqv unless t avqv or t etqv have not been satisfied. a(18:0) address dq(7:0) data input/output e chip enable w write enable g output enable v dd power v ss ground 136 235 334 433 532 631 730 829 928 10 27 11 26 12 25 13 24 14 23 15 22 16 21 17 20 18 19 figure 2. ut8q512e 20ns sram pinout (36) nc a18 a17 a16 a15 g dq7 dq6 v ss v dd dq5 dq4 a14 a13 a12 a11 a10 nc a0 a1 a2 a3 a4 e dq0 dq1 v dd v ss dq2 dq3 w a5 a6 a7 a8 a9 g w e i/o mode mode x 1 x 1 3-state standby x 0 0 data in write 1 1 0 3-state read 2 0 1 0 data out read
3 write cycle a combination of w less than v il (max) and e less than v il (max) defines a write cycle. the state of g is a ?don?t care? for a write cycle. the outputs are placed in the high-impedance state when either g is greater than v ih (min), or when w is less than v il (max). write cycle 1, the write enable - controlled access in figure 5a, is defined by a write terminated by w going high, with e still active. the write pulse width is defined by t wlwh when the write is initiated by w , and by t etwh when the write is initiated by e . unless the outputs have been previously placed in the high- impedance state by g , the user must wait t wlqz before applying data to the nine bidirectional pins dq(7:0) to avoid bus contention. write cycle 2, the chip enable - controlled access in figure 5b, is defined by a write terminated by e going inactive. the write pulse width is defined by t wlef when the write is initiated by w , and by t etef when the write is initiated by the e going active. for the w initiated write, unless the outputs have been previously placed in the high-impedance state by g , the user must wait t wlqz before applying data to the eight bidirectional pins dq(7:0) to avoid bus contention. operational environment table 2.operational environment design specifications 1 notes: 1. the sram will not latchup during radiation exposure under recommended operating conditions. 2. adam?s 0% worst case environment, geosynchronous orbit, 100 mils of aluminum. to tal d ose 50 krad(si) heavy ion error rate 2 < 1.1e-9 errors/bit-day
4 absolute maximum ratings 1 (referenced to v ss ) notes: 1. stresses outside the listed absolute maximum ratings may caus e permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. exposure to absolute maximum rating conditions for extended periods may aff ect device reliability and performance. 2. maximum junction temperat ure may be increased to +175 c during burn-in an d steady-static life. recommended operating conditions symbol parameter limits v dd dc supply voltage -0.5 to 7.0v v i/o voltage on any pin -0.5 to 7.0v t stg storage temperature -65 to +150 c p d maximum power dissipation 1.0w t j maximum junction temperature 2 +150 c jc thermal resistance, junction-to-case 10 c/w i i dc input current 10 ma symbol parameter limits v dd positive supply voltage 3.0 to 3.6v t c case temperature range (c) screening: -55 c to +125 c (w) screening: -40 c to +125 c v in dc input voltage 0v to v dd
5 dc electrical characteristics (pre/post-radiation)* -55 c to +125 c for (c) screening and -40 o c to +125 o c for (w) screening (v dd = 3.3v + 0.3v) notes: * post-radiation perform ance guaranteed at 25 c per mil-std-883 method 1019. 1. measured only for in itial qualification and after process or design ch anges that could affect input/output capacitance. 2. supplied as a design limit bu t not guaranteed or tested. 3. not more than one output may be shorted at a time for maximum duration of one second. 4. g = v 1h 5. post-radiation limits are the 125 o c temperature limits when specified. symbol parameter condition min max unit v ih high-level input voltage (ttl) 2 v v il low-level input voltage (ttl) 0.8 v v ol1 low-level output voltage i ol = 6ma, v dd = 3.0v (ttl) 0.4 v v ol2 low-level output voltage i ol = 200 a,v dd = 3.0v (cmos) 0.08 v v oh1 high-level output voltage i oh = -3ma,v dd = 3.0v (ttl) 2.4 v v oh2 high-level output voltage i oh = -200 a,v dd = 3.0v (cmos) v dd - 0.10 v c in 1 input capacitance ? = 1mhz @ 0v 10 pf c io 1 bidirectional i/o capacitance ? = 1mhz @ 0v 12 pf i in input leakage current v in = v dd and v ss, v dd = v dd (max) -2 2 a i oz three-state output leakage current v o = v dd and v ss v dd = v dd (max) g = v dd (max) -2 2 a i os 2, 3 short-circuit output current v dd = v dd (max), v o = v dd v dd = v dd (max), v o = 0v -90 90 ma i dd (op) 4 supply current operating @ 1mhz inputs: v il = 0.8v, v ih = 2.0v i out = 0ma v dd = v dd (max) 50 ma i dd (op) 4 supply current operating @50mhz inputs: v il = 0.8v, v ih = 2.0v i out = 0ma v dd = v dd (max) 76 ma i dd (sb) 5 supply current standby @0mhz inputs: v il = v ss i out = 0ma e = v dd - 0.5 v dd = v dd (max) v ih = v dd - 0.5v -55 c, -40 c, 25 c 10 ma 125 c45ma
6 { { } } v load + 300mv v load - 300mv v load v h - 300mv v l + 300mv active to high z levels high z to active levels figure 3. 3.3-volt sram loading ac characteristics read cycle (pre/post-radiation)* -55 c to +125 c for (c) screening and -40 o c to +125 o c for (w) screening (v dd = 3.3v + 0.3v) notes: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019. 1. functional test. 2. three-state is defined as a 300mv change fr om steady-state output voltage (see figure 3). 3. the et (chip enable true) notatio n refers to the falling edge of e . seu immunity does not af fect the read parameters. 4. the ef (chip enable false) notation refers to the rising edge of e . seu immunity does not aff ect the read parameters. symbol parameter min max unit t avav 1 read cycle time 20 ns t av q v read access time 20 ns t axqx output hold time 3 ns t glqx g -controlled output enable time 3 ns t glqv g -controlled output enable time (read cycle 3) 10 ns t ghqz 2 g -controlled output three-state time 10 ns t etqx 3 e -controlled output enable time 3 ns t etqv 3 e -controlled access time 20 ns t efqz 1,2,4 e -controlled output three-state time 10 ns
7 assumptions: 1. e and g < v il (max) and w > v ih (min) a(18:0) dq(7:0) figure 4a. sram read cycle 1: address access t avav t avqv t axqx previous valid data valid data assumptions: 1. g < v il (max) and w > v ih (min) a(18:0) e data valid t efqz t etqv t etqx dq(7:0) figure 4b. sram read cycle 2: chip enable-controlled access figure 4c. sram read cycle 3: output enable-controlled access a(18:0) dq(7:0) g t ghqz assumptions: 1. e < v il (max) and w > v ih (min) t glqv t glqx t avqv data valid
8 ac characteristics write cycle (pre/post-radiation)* -55 c to +125 c for (c) screening and -40 o c to +125 o c for (e) screening (v dd = 3.3v + 0.3v) notes : * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019. 1. functional test performe d with outputs disabled (g high). 2. three-state is defined as 300 mv change from steady-state output voltage (see figure 3). symbol parameter min max unit t avav 1 write cycle time 20 ns t etwh chip enable to end of write 20 ns t av e t address setup time for write (e - controlled) 0 ns t av w l address setup time for write (w - controlled) 0 ns t wlwh write pulse width 20 ns t whax address hold time for write (w - controlled) 0 ns t efax address hold time for chip enable (e - controlled) 0 ns t wlqz 2 w - controlled three-state time 10 ns t whqx w - controlled output enable time 4 ns t etef chip enable pulse width (e - controlled) 20 ns t dvwh data setup time 15 ns t whdx data hold time 2 ns t wlef chip enable controlled write pulse width 20 ns t dvef data setup time 15 ns t efdx data hold time 2 ns t av w h address valid to end of write 20 ns t whwl 1 write disable time 5 ns
9 assumptions: 1. g < v il (max). if g > v ih (min) then q(7:0) will be in three-state for the entire cycle. 2. g high for t avav cycle. w t avwl figure 5a. sram write cycle 1: write enable - controlled access a(18:0) q(7:0) e t avav 2 d(7:0) applied data t dvwh t whdx t etwh t wlwh t whax t whqx t wlqz t avwh t whwl
10 t efdx assumptions & notes: 1. g < v il (max). if g > v ih (min) then q(7:0) will be in three-state for the entire cycle. 2. either e scenario above can occur. 3. g high for t avav cycle. a(18:0) figure 5b. sram write cycle 2: chip enable - controlled access w e d(7:0) applied data e q(7:0) t wlqz t etef t wlef t dvef t avav 3 t avet t avet t etef t efax t efax or
11 v dd dut zo = 50-ohm s v dd c l = 40pf r term 100-ohm s test point r term 100-ohm s notes: 1. measurement of data output occurs at the low to high or high to low transition mid-point (i.e., cmos input = v dd /2). 90% input pulses 10% < 5ns < 5ns cmos 0.5v v dd -0.05v 10% figure 6. ac test loads and input waveforms
12 data retention characteris tics (pre-radiation)* (v dd = v dd (min), 1 sec dr pulse) notes: * post-radiation perform ance guaranteed at 25 o c per mil-std-883 method 1019. 1. e = v dr all other inputs = v dr or v ss . symbol parameter temp minimum maximum unit v dr v dd for data retention -- 2.0 -- v i ddr 1 data retention current -40 o c -55 o c 25 o c 125 o c -- -- -- -- 10 10 10 45 ma ma ma ma t efr 1 chip enable to data retention time -- 0 -- ns t r 1 operation recovery time -- t avav -- ns v dd data retention mode t r 3.0v 3.0v v dr > 2.0v figure 7. low v dd data retention waveform t efr e v dd = v dr
13 packaging 1. all exposed metalized areas are gold plated over electroplated nickel per mil-prf-38535. 2. the lid is electri cally connected to v ss . 3. lead finishes are in accordance to mil-prf-38535. 4. dimension are in acco rdance with mil-prf-38535. 5. lead position and copl anarity are not measured. 6. id mark symbol is vendor option: no alphanumerics. one or both id methods ma y be used for pin 1 id. 7. letter designators are in accordance with mil-std-1835. 8. dimensions shown are in inches. figure 8. 36-pin ceramic flatpack
14 ordering information 512k x 8 sram: access time: (20) = 20ns access ti me, 3.3v operation package type: (y) = 36-lead flatpack package (bottom brazed) screening: (notes 3, 4, & 5) (c) = hirel temperature range flow (p) = prototype flow (w) = extended industrial temperature range flow (-40 o c to +125 o c) lead finish: (notes 1 & 2) (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, th en the part marking will match the lead fini sh and will be either ?a? (solder) or ?c? (gold). 3. prototype flow per aeroflex manufact uring flows document. tested at 25 c only. lead finish is gold only. radiation neither tested nor guaranteed. 4. hirel temperature range flow per aeroflex manuf acturing flows document. devices are tested at -55 c, room temp, and +125 c. radiation neither tested nor guaranteed. 5. extended industrial temperature range flow per aeroflex manufacturing flows document. devices are tested at -40 c, room temp, and +125 c. radiation neither tested nor guaranteed. ut8q512e- * * * * -aeroflex core part number
15 512k x 8 sram: smd 5962 - 99607 lead finish: (notes 1 & 2) (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) case outline: (y) = 36-lead ceramic flatpack (bottom-brazed) class designator: (q) = qml class q (v) = qml class v device type 05 = 20ns access time, 3.3v operation, mil-temp 06 = 20ns access time, 3.3v operation, exte nded industrial temp (-40c to +125c) drawing number: 99607 total dose: ( note 3) (d) = 1e4 (10 krad)(si)) (p) = 3e4 (30 krad)(si)) (l) = 5e4 (50krad(si)) federal stock class designator: no options ** * ** notes: 1.lead finish (a,c, or x) must be specified. 2.if an ?x? is specified when ordering, part marking will match the lead finish and will be eith er ?a? (solder) or ?c? (gold). 3.total dose radiation must be specified when ordering.
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