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the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. not all devices/types available in every country. please check with local nec representative for availability and additional information. mos integrated circuit pd703100a-33, 703100a-40, 703101a-33, 703102a-33 v850e/ms1 tm 32-bit single-chip microcontrollers document no. u14168ej3v0ds00 (3rd edition) date published december 2000 n cp(k) printed in japan data sheet 1999 ? the pd703101a-33 and pd703102a-33 are members of the v850 family tm of 32-bit single-chip microcontrollers designed for real-time control operations. these microcontrollers provide on-chip features, including a 32-bit cpu core, rom, ram, an interrupt controller, real-time pulse unit, serial interface, a/d converter, and dma controller. the pd703100a-33 and pd703100a-40 are rom less versions of the pd703101a-33 and pd703102a-33. the pd703100-33, pd703100-40, pd703101-33, and pd703102-33 are also available as products having a 5.0 v power supply for external pins. detailed function descriptions are provided in the following user?s manuals. be sure to read them before designing. v850e/ms1 user?s manual hardware: u12688e v850e/ms1 user?s manual architecture: u12197e features number of instructions: 81 minimum instruction execution time: 25 ns (@ 40 mhz operation) pd703100a-40 30 ns (@ 33 mhz operation) pd703100a-33, 703101a-33, 703102a-33 general-purpose registers: 32 bits 32 instruction set optimized for control applications internal memory rom: none ( pd703100a-33, 703100a-40), 96 kb ( pd703101a-33), 128 kb ( pd703102a-33) ram: 4 kb advanced on-chip interrupt controller real-time pulse unit suitable for control operations powerful serial interface (on-chip dedicated baud rate generator) on-chip clock generator 10-bit resolution a/d converter: 8 channels dma controller: 4 channels power saving functions applications office automation equipment: printers, facsimile machines, ppcs, etc. multimedia equipment: digital still cameras, video printers, etc. consumer equipment: single-lens reflex cameras, etc. industrial equipment: motor controllers, nc machine tools, etc. the mark shows major revised points.
data sheet u14168ej3v0ds 2 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 ordering information part number package maximum operating frequency internal rom pd703100af1-33-fa1 157-pin plastic fbga (14 14) 33 mhz none pd703100agj-33-uen 144-pin plastic lqfp (fine pitch) (20 20) 33 mhz none pd703100agj-40- uen 144-pin plastic lqfp (fine pitch) (20 20) 40 mhz none pd703101af1-33- -fa1 157-pin plastic fbga (14 14) 33 mhz 96 kb pd703101agj-33- - uen 144-pin plastic lqfp (fine pitch) (20 20) 33 mhz 96 kb pd703102af1-33- -fa1 157-pin plastic fbga (14 14) 33 mhz 128 kb pd703102agj-33- - uen 144-pin plastic lqfp (fine pitch) (20 20) 33 mhz 128 kb remark indicates rom code suffix.
data sheet u14168ej3v0ds 3 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 pin configuration (top view) 157-pin plastic fgba (14 14) pd703100af1-33-fa1 pd703101af1-33- -fa1 pd703102af1-33- -fa1 trpnmlkjhgfedcba 1 2 3 4 5 6 7 8 9 10 16 15 14 13 12 11 bottom view abcdefghjklmnprt top view index mark index mark (1/2) pin no. pin name pin no. pin name pin no. pin name a1 ? b1 intp103/dmarq3/p07 c1 intp101/dmarq1/p05 a2 d0/p40 b2 d1/p41 c2 intp102/dmarq2/p06 a3 d2/p42 b3 d3/p43 c3 v ss a4 d4/p44 b4 d5/p45 c4 v ss a5 d6/p46 b5 d7/p47 c5 hv dd a6 d8/p50 b6 d9/p51 c6 v ss a7 d10/p52 b7 d11/p53 c7 d12/p54 a8 d13/p55 b8 d14/p56 c8 d15/p57 a9 a0/pa0 b9 a1/pa1 c9 hv dd a10 a2/pa2 b10 a3/pa3 c10 a4/pa4 a11 a5/pa5 b11 a6/pa6 c11 a7/pa7 a12 a8/pb0 b12 a9/pb1 c12 v ss a13 a10/pb2 b13 a11/pb3 c13 a12/pb4 a14 a13/pb5 b14 a14/pb6 c14 a18/p62 a15 a15/pb7 b15 a17/p61 c15 a19/p63 a16 ? b16 a16/p60 c16 ?
data sheet u14168ej3v0ds 4 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (2/2) pin no. pin name pin no. pin name pin no. pin name d1 ti10/p03 k1 ti12/p103 p14 reset d2 intp100/dmarq0/p04 k2 intp120/tc0/p104 p15 intp151/p125 d3 hv dd k3 intp121/tc1/p105 p16 intp150/p124 d4 ? k14 hldak/p96 r1 av ss d14 v ss k15 oe/p95 r2 ani0/p70 d15 a21/p65 k16 bcyst/p94 r3 p21 d16 a20/p64 l1 to120/p100 r4 sck0/p24 e1 to101/p01 l2 to121/p101 r5 sck1/p27 e2 tclr10/p02 l3 tclr12/p102 r6 intp132/si2/p36 e3 v ss l14 v ss r7 ti13/p33 e14 hv dd l15 refrq/px5 r8 to130/p30 e15 a23/p67 l16 hldrq/p97 r9 intp141/so3/p115 e16 a22/p66 m1 ani5/p75 r10 tclr14/p112 f1 intp113/dmaak3/p17 m2 ani6/p76 r11 to140/p110 f2 to100/p00 m3 ani7/p77 r12 mode0 f3 v dd m14 to150/p120 r13 mode1 f14 cs2/ras2/p82 m15 wait/px6 r14 mode2 f15 cs1/ras1/p81 m16 clkout/px7 r15 intp153/adtrg/p127 f16 cs0/ras0/p80 n1 ani2/p72 r16 intp152/p126 g1 intp110/dmaak0/p14 n2 ani3/p73 t1 ? g2 intp111/dmaak1/p15 n3 ani4/p74 t2 av ref g3 intp112/dmaak2/p16 n14 ti15/p123 t3 nmi/p20 g14 cs5/ras5/iord/p85 n15 tclr15/p122 t4 rxd0/si0/p23 g15 cs4/ras4/iowr/p84 n16 to151/p121 t5 rxd1/si1/p26 g16 cs3/ras3/p83 p1 av dd t6 intp131/so2/p35 h1 to111/p11 p2 ani1/p71 t7 tclr13/p32 h2 tclr11/p12 p3 txd0/so0/p22 t8 intp143/sck3/p117 h3 ti11/p13 p4 txd1/so1/p25 t9 intp140/p114 h14 lcas/lwr/p90 p5 v dd t10 cv dd h15 cs7/ras7/p87 p6 intp133/sck2/p37 t11 x2 h16 cs6/ras6/p86 p7 intp130/p34 t12 x1 j1 intp122/tc2/p106 p8 to131/p31 t13 cv ss j2 intp123/tc3/p107 p9 intp142/si3/p116 t14 mode3 j3 to110/p10 p10 ti14/p113 t15 ? j14 we/p93 p11 to141/p111 t16 ? j15 rd/p92 p12 cksel ? ? j16 ucas/uwr/p91 p13 hv dd ?? remark leave the pins numbered a1, a16, c16, d4, t1, t15, and t16 open.
data sheet u14168ej3v0ds 5 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 144-pin plastic lqfp (fine pitch) (20 20) pd703100agj-33-uen pd703100agj-40-uen pd703101agj-33- -uen pd703102agj-33- -uen intp103/dmarq3/p07 intp102/dmarq2/p06 intp101/dmarq1/p05 intp100/dmarq0/p04 ti10/p03 tclr10/p02 to101/p01 to100/p00 v ss intp113/dmaak3/p17 intp112/dmaak2/p16 intp111/dmaak1/p15 intp110/dmaak0/p14 ti11/p13 tclr11/p12 to111/p11 to110/p10 intp123/tc3/p107 intp122/tc2/p106 intp121/tc1/p105 intp120/tc0/p104 ti12/p103 tclr12/p102 to121/p101 to120/p100 ani7/p77 ani6/p76 ani5/p75 ani4/p74 ani3/p73 ani2/p72 ani1/p71 ani0/p70 av dd av ss av ref 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 a16/p60 a17/p61 a18/p62 a19/p63 a20/p64 a21/p65 a22/p66 a23/p67 hv dd cs0/ras0/p80 cs1/ras1/p81 cs2/ras2/p82 cs3/ras3/p83 cs4/ras4/iowr/p84 cs5/ras5/iord/p85 cs6/ras6/p86 cs7/ras7/p87 lcas/lwr/p90 ucas/uwr/p91 rd/p92 we/p93 bcyst/p94 oe/p95 hldak/p96 hldrq/p97 v ss refrq/px5 wait/px6 clkout/px7 to150/p120 to151/p121 tclr15/p122 ti15/p123 intp150/p124 intp151/p125 intp152/p126 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 nmi/p20 p21 txd0/so0/p22 rxd0/si0/p23 sck0/p24 txd1/so1/p25 rxd1/si1/p26 sck1/p27 v dd intp133/sck2/p37 intp132/si2/p36 intp131/so2/p35 intp130/p34 ti13/p33 tclr13/p32 to131/p31 to130/p30 intp143/sck3/p117 intp142/si3/p116 intp141/so3/p115 intp140/p114 ti14/p113 tclr14/p112 to141/p111 to140/p110 cv dd x2 x1 cv ss cksel mode0 mode1 mode2 mode3 reset intp153/adtrg/p127 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 v dd d0/p40 d1/p41 d2/p42 d3/p43 d4/p44 d5/p45 d6/p46 d7/p47 v ss d8/p50 d9/p51 d10/p52 d11/p53 d12/p54 d13/p55 d14/p56 d15/p57 hv dd a0/pa0 a1/pa1 a2/pa2 a3/pa3 a4/pa4 a5/pa5 a6/pa6 a7/pa7 v ss a8/pb0 a9/pb1 a10/pb2 a11/pb3 a12/pb4 a13/pb5 a14/pb6 a15/pb7 144 142 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
data sheet u14168ej3v0ds 6 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 pin identification a0 to a23: address bus p50 to p57: port 5 adtrg: ad trigger input p60 to p67: port 6 ani0 to ani7: analog input p70 to p77: port 7 av dd : analog power supply p80 to p87: port 8 av ref : analog reference voltage p90 to p97: port 9 av ss : analog ground p100 to p107: port 10 bcyst: bus cycle start timing p110 to p117: port 11 cksel: clock generator operating mode select p120 to p127: port 12 clkout: clock output pa0 to pa7: port a cs0 to cs7: chip select pb0 to pb7: port b cv dd : clock generator power supply px5 to px7: port x cv ss : clock generator ground ras0 to ras7: row address strobe d0 to d15: data bus rd: read dmaak0 to dmaak3 : dma acknowledge refrq: refresh request dmarq0 to dmarq3 : dma request reset: reset hldak: hold acknowledge rxd0, rxd1: receive data hldrq: hold request sck0 to sck3: serial clock hv dd : power supply for external pins si0 to si3: serial input intp100 to intp103, so0 to so3: serial output intp110 to intp113, tc0 to tc3: terminal count signal intp120 to intp123, tclr10 to tclr15 : timer clear intp130 to intp133, ti10 to ti15: timer input intp140 to intp143, to100, to101, intp150 to intp153 : interrupt request from peripherals to110, to111, iord: i/o read strobe to120, to121, iowr: i/o write strobe to130, to131, lcas: lower column address strobe to140, to141, lwr: lower write strobe to150, to151: timer output mode0 to mode3: mode txd0, txd1: transmit data nmi: non-maskable interrupt request ucas: upper column address strobe oe: output enable uwr: upper write strobe p00 to p07: port 0 v dd : power supply for internal unit p10 to p17: port 1 v ss : ground p20 to p27: port 2 wait: wait p30 to p37: port 3 we: write enable p40 to p47: port 4 x1, x2: crystal
data sheet u14168ej3v0ds 7 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 internal block diagram note pd703100a-33, 703100a-40: none pd703101a-33: 96 kb (mask rom) pd703102a-33: 128 kb (mask rom) tclr10 to tclr15 ti10 to ti15 to100, to101, to110, to111, to120, to121, to130, to131, to140, to141, to150, to151 intp100 to intp103, intp110 to intp113, intp120 to intp123, intp130 to intp133, intp140 to intp143, intp150 to intp153 nmi intc rpu uart0/csi0 sio sck0 si0/rxd0 so0/txd0 brg0 uart1/csi1 sck1 si1/rxd1 so1/txd1 brg1 csi2 sck2 si2 so2 brg2 csi3 sck3 si3 so3 av ref adc av ss av dd adtrg ani0 to ani7 ports px5 to px7 pb0 to pb7 pa0 to pa7 p120 to p127 p110 to p117 p100 to p107 p90 to p97 p80 to p87 p70 to p77 p60 to p67 p50 to p57 p40 to p47 p30 to p37 p21 to p27 p20 p10 to p17 p00 to p07 hv dd note rom 4 kbytes ram instruction queue pc system registers general-purpose registers (32 bits
data sheet u14168ej3v0ds 8 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 contents 1. differences among products.............................................................................................9 2. pin functions ............................................................................................................. ...............10 2.1 port pins................................................................................................................ ...............10 2.2 non-port pins............................................................................................................ ...........13 2.3 pin i/o circuits and recommended connection of unused pins ..................................17 3. electrical specifications ................................................................................................. .20 4. package drawings.......................................................................................................... ........76 5. recommended soldering conditions.............................................................................78
data sheet u14168ej3v0ds 9 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 1. differences among products part number pd703100 pd703101 pd703102 pd70f3102 item -33 -40 a-33 a-40 -33 a-33 -33 a-33 -33 a-33 internal rom none 96 kb (mask rom) 128 kb (mask rom) 128 kb (flash memory) maximum operating frequency 33 mhz 40 mhz 33 mhz 40 mhz 33 mhz hv dd 4.5 to 5.5 v 3.0 to 3.6 v 4.5 to 5.5 v 3.0 to 3.6 v 4.5 to 5.5 v 3.0 to 3.6 v 4.5 to 5.5 v 3.0 to 3.6 v operation mode single-chip mode 0, 1 none provided flash memory programming mode none provided flash memory programming pin none provided (v pp ) electrical specifications current consumption differs (refer to the data sheet of each product). package 144lqfp 144lqfp 157fbga 144lqfp 144lqfp 144lqfp 157fbga 144lqfp 144lqfp 157fbga 144lqfp 144lqfp 157fbga others noise tolerance and noise radiation will differ due to the differences in circuit scale and mask layout. remark 144lqfp: 144-pin plastic lqfp (fine pitch) (20 20) 157fbga: 157-pin plastic fbga (14 14)
data sheet u14168ej3v0ds 10 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 2. pin functions 2.1 port pins (1/3) pin name i/o function alternate function p00 to100 p01 to101 p02 tclr10 p03 ti10 p04 intp100/dmarq0 p05 intp101/dmarq1 p06 intp102/dmarq2 p07 i/o port 0 8-bit i/o port input/output can be specified in 1-bit units intp103/dmarq3 p10 to110 p11 to111 p12 tclr11 p13 ti11 p14 intp110/dmaak0 p15 intp111/dmaak1 p16 intp112/dmaak2 p17 i/o port 1 8-bit i/o port input/output can be specified in 1-bit units intp113/dmaak3 p20 input nmi p21 ? p22 txd0/so0 p23 rxd0/si0 p24 sck0 p25 txd1/so1 p26 rxd1/si1 p27 i/o port 2 p20 is an input only port. when a valid edge is input, this pin operates as an nmi input. also, bit 0 of the p2 register indicates the nmi input status. p21 to p27 are a 7-bit i/o port. input/output can be specified in 1-bit units sck1 p30 to130 p31 to131 p32 tclr13 p33 ti13 p34 intp130 p35 intp131/so2 p36 intp132/si2 p37 i/o port 3 8-bit i/o port. input/output can be specified in 1-bit units intp133/sck2 p40 to p47 i/o port 4 8-bit i/o port input/output can be specified in 1-bit units d0 to d7
data sheet u14168ej3v0ds 11 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (2/3) pin name i/o function alternate function p50 to p57 i/o port 5 8-bit i/o port input/output can be specified in 1-bit units d8 to d15 p60 to p67 i/o port 6 8-bit i/o port input/output can be specified in 1-bit units a16 to a23 p70 to p77 input port 7 8-bit input-only port ani0 to ani7 p80 cs0/ras0 p81 cs1/ras1 p82 cs2/ras2 p83 cs3/ras3 p84 cs4/ras4/iowr p85 cs5/ras5/iord p86 cs6/ras6 p87 i/o port 8 8-bit i/o port input/output can be specified in 1-bit units cs7/ras7 p90 lcas/lwr p91 ucas/uwr p92 rd p93 we p94 bcyst p95 oe p96 hldak p97 i/o port 9 8-bit i/o port input/output can be specified in 1-bit units hldrq p100 to120 p101 to121 p102 tclr12 p103 ti12 p104 intp120/tc0 p105 intp121/tc1 p106 intp122/tc2 p107 i/o port 10 8-bit i/o port input/output can be specified in 1-bit units intp123/tc3 p110 to140 p111 to141 p112 tclr14 p113 ti14 p114 intp140 p115 intp141/so3 p116 intp142/si3 p117 i/o port 11 8-bit i/o port input/output can be specified in 1-bit units intp143/sck3
data sheet u14168ej3v0ds 12 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (3/3) pin name i/o function alternate function p120 to150 p121 to151 p122 tclr15 p123 ti15 p124 intp150 p125 intp151 p126 intp152 p127 i/o port 12 8-bit i/o port input/output can be specified in 1-bit units intp153/adtrg pa0 a0 pa1 a1 pa2 a2 pa3 a3 pa4 a4 pa5 a5 pa6 a6 pa7 i/o port a 8-bit i/o port input/output can be specified in 1-bit units a7 pb0 a8 pb1 a9 pb2 a10 pb3 a11 pb4 a12 pb5 a13 pb6 a14 pb7 i/o port b 8-bit i/o port input/output can be specified in 1-bit units a15 px5 refrq px6 wait px7 i/o port x 3-bit i/o port input/output can be specified in 1-bit units clkout
data sheet u14168ej3v0ds 13 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 2.2 non-port pins (1/4) pin name i/o function alternate function to100 p00 to101 p01 to110 p10 to111 p11 to120 p100 to121 p101 to130 p30 to131 p31 to140 p110 to141 p111 to150 p120 to151 output pulse signal output for timers 10 to 15 p121 tclr10 p02 tclr11 p12 tclr12 p102 tclr13 p32 tclr14 p112 tclr15 input external clear signal input for timers 10 to 15 p122 ti10 p03 ti11 p13 ti12 p103 ti13 p33 ti14 p113 ti15 input external count clock input for timers 10 to 15 p123 intp100 p04/dmarq0 intp101 p05/dmarq1 intp102 p06/dmarq2 intp103 input external maskable interrupt request input, also used as external capture trigger input for timer 10 p07/dmarq3 intp110 p14/dmaak0 intp111 p15/dmaak1 intp112 p16/dmaak2 intp113 input external maskable interrupt request input, also used as external capture trigger input for timer 11 p17/dmaak3 intp120 p104/tc0 intp121 p105/tc1 intp122 p106/tc2 intp123 input external maskable interrupt request input, also used as external capture trigger input for timer 12 p107/tc3
data sheet u14168ej3v0ds 14 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (2/4) pin name i/o function alternate function intp130 p34 intp131 p35/so2 intp132 p36/si2 intp133 input external maskable interrupt request input, also used as external capture trigger input for timer 13 p37/sck2 intp140 p114 intp141 p115/so3 intp142 p116/si3 intp143 input external maskable interrupt request input, also used as external capture trigger input for timer 14 p117/sck3 intp150 p124 intp151 p125 intp152 p126 intp153 input external maskable interrupt request input, also used as external capture trigger input for timer 15 p127/adtrg so0 p22/txd0 so1 p25/txd1 so2 p35/intp131 so3 output serial transmit data output (3-wire) for csi0 to csi3 p115/intp141 si0 p23/rxd0 si1 p26/rxd1 si2 p36/intp132 si3 input serial receive data input (3-wire) for csi0 to csi3 p116/intp142 sck0 p24 sck1 p27 sck2 p37/intp133 sck3 i/o serial clock i/o (3-wire) for csi0 to csi3 p117/intp143 txd0 p22/so0 txd1 output serial transmit data output for uart0 and uart1 p25/so1 rxd0 p23/si0 rxd1 input serial receive data input for uart0 and uart1 p26/si1 d0 to d7 p40 to p47 d8 to d15 i/o 16-bit data bus for external memory p50 to p57 a0 to a7 pa0 to pa7 a8 to a15 pb0 to pb7 a16 to a23 output 24-bit address bus for external memory p60 to p67 lwr output lower byte write-enable signal output for external data bus p90/lcas uwr output higher byte write-enable signal output for external data bus p91/ucas rd output read strobe signal output for external data bus p92 we output write enable signal output for dram p93 oe output output enable signal output for dram p95
data sheet u14168ej3v0ds 15 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (3/4) pin name i/o function alternate function lcas output column address strobe signal output for dram?s lower data p90/lwr ucas output column address strobe signal output for dram?s higher data p91/uwr ras0 to ras3 p80/cs0 to p83/cs3 ras4 p84/cs4/iowr ras5 p85/cs5/iord ras6 p86/cs6 ras7 output low address strobe signal output for dram p87/cs7 bcyst output strobe signal output indicating start of bus cycle p94 cs0 to cs3 p80/ras0 to p83/ras3 cs4 p84/ras4/iowr cs5 p85/ras5/iord cs6 p86/ras6 cs7 output chip select signal output p87/ras7 wait input control signal input for inserting waits in bus cycle px6 refrq output refresh request signal output for dram px5 iowr output dma write strobe signal output p84/ras4/cs4 iord output dma read strobe signal output p85/ras5/cs5 dmarq0 to dmarq3 input dma request signal input p04/intp100 to p07/intp103 dmaak0 to dmaak3 output dma acknowledge signal output p14/intp110 to p17/intp113 tc0 to tc3 output dma end (terminal count) signal output p104/intp120 to p107/intp123 hldak output bus hold acknowledge output p96 hldrq input bus hold request input p97 ani0 to ani7 input analog input to a/d converter p70 to p77 nmi input non-maskable interrupt request input p20 clkout output system clock output px7 cksel input input for specifying clock generator?s operation mode ? mode0 to mode3 input specify operation modes ? reset input system reset input ? x1 input ? x2 ? oscillator connection for system clock. input is via x1 when using an external clock. ? adtrg input a/d converter external trigger input p127/intp153 av ref input reference voltage input for a/d converter ? av dd ? positive power supply for a/d converter ? av ss ? ground potential for a/d converter ?
data sheet u14168ej3v0ds 16 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (4/4) pin name i/o function alternate function cv dd ? positive power supply for dedicated clock generator ? cv ss ? ground potential for dedicated clock generator ? v dd ? positive power supply (power supply for internal units) ? hv dd ? positive power supply (power supply for external pins) ? v ss ? ground potential ?
data sheet u14168ej3v0ds 17 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 2.3 pin i/o circuits and recommended connection of unused pins table 2-1 shows the i/o circuit type of each pin and recommended connection of unused pins. figure 2-1 shows the various circuit types using partially abridged diagrams. when connecting to v dd or v ss via a resistor, a resistance value in the range of 1 to 10 k ? is recommended. table 2-1. i/o circuit type of each pin and recommended connection of unused pins (1/2) pin i/o circuit type recommended connection of unused pins p00/to100, p01/to101 5 p02/tclr10, p03/ti10 p04/intp100/dmarq0 to p07/intp103/dmarq3 5-k p10/to110, p11/to111 5 p12/tclr11, p13/ti11 p14/intp110/dmaak0 to p17/intp113/dmaak3 5-k input: independently connect to hv dd or v ss via a resistor output: leave open p20/nmi 2 connect directly to v ss p21 p22/txd0/so0 5 p23/rxd0/si0 p24/sck0 5-k p25/txd1/so1 5 p26/rxd1/si1 p27/sck1 5-k p30/to130, p31/to131 5 p32/tclr13, p33/ti13 p34/intp130 p35/intp131/so2 p36/intp132/si2 p37/intp133/sck2 5-k p40/d0 to p47/d7 p50/d8 to p57/d15 p60/a16 to p67/a23 5 input: independently connect to hv dd or v ss via a resistor output: leave open p70/ani0 to p77/ani7 9 connect directly to v ss p80/cs0/ras0 to p83/cs3/ras3 p84/cs4/ras4/iowr, p85/cs5/ras5/iord p86/cs6/ras6, p87/cs7/ras7 p90/lcas/lwr p91/ucas/uwr 5 input: independently connect to hv dd or v ss via a resistor output: leave open
data sheet u14168ej3v0ds 18 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 table 2-1. i/o circuit type of each pin and recommended connection of unused pins (2/2) pin i/o circuit type recommended connection of unused pins p92/rd p93/we p94/bcyst p95/oe p96/hldak p97/hldrq p100/to120, p101/to121 5 p102/tclr12, p103/ti12 p104/intp120/tc0 to p107/intp123/tc3 5-k p110/to140, p111/toi41 5 p112/tclr14, p113/ti14 p114/intp140 p115/intp141/so3 p116/intp142/si3 p117/intp143/sck3 5-k p120/to150, p121/to151 5 p122/tclr15, p123/ti15 p124/intp150 to p126/intp152 p127/intp153/adtrg 5-k pa0/a0 to pa7/a7 pb0/a8 to pb7/a15 px5/refrq px6/wait px7/clkout 5 input: independently connect to hv dd or v ss via a resistor output: leave open cksel 1 ? reset mode0 to mode2 ? mode3 2 connect to v ss via a resistor (r vpp ) av ref , av ss ? connect directly to v ss av dd ? connect directly to hv dd
data sheet u14168ej3v0ds 19 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 figure 2-1. pin i/o circuits caution replace v dd with hv dd when referencing the circuit diagrams shown above. in p-ch v dd n-ch in data p-ch v dd n-ch in/out output disable input enable data p-ch v dd n-ch in/out output disable input enable in + ? input enable p-ch n-ch v ref (threshold voltage) type 1 type 2 type 5 type 5-k type 9 comparator schmitt-triggered input with hysteresis characteristics
data sheet u14168ej3v0ds 20 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 3. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit v dd v dd pin ? 0.5 to +4.6 v hv dd hv dd pin, hv dd v dd ? 0.5 to +4.6 v cv dd cv dd pin ? 0.5 to +4.6 v cv ss cv ss pin ? 0.5 to +0.5 v av dd av dd pin ? 0.5 to hv dd + 0.5 v power supply voltage av ss av ss pin ? 0.5 to +0.5 v x1 pin, except mode3 pin ? 0.5 to hv dd + 0.5 v input voltage v i mode3 pin ? 0.5 to v dd + 0.5 v clock input voltage v k x1, v dd = 3.0 to 3.6 v ? 0.5 to v dd + 1.0 v 1 pin 4.0 ma output current, low i ol total of all pins 100 ma 1 pin ? 4.0 ma output current, high i oh total of all pins ? 100 ma output voltage v o hv dd = 3.0 v to 3.6 v ? 0.5 to hv dd + 0.5 v av dd > hv dd ? 0.5 to hv dd + 0.5 v analog input voltage v ian p70/ani0 to p77/ani7 pins hv dd av dd ? 0.5 to av dd + 0.5 v av dd > hv dd ? 0.5 to hv dd + 0.5 v a/d converter reference input voltage av ref hv dd av dd ? 0.5 to av dd + 0.5 v operating ambient temperature t a pd703100a-40 ? 40 to +70 c pd703100a-33, 703101a-33, 703102a-33 ? 40 to +85 c storage temperature t stg ? 65 to +150 c caution 1. do not directly connect the output (or i/o) pins to each other, or to v dd , v cc , and gnd. open- drain or open-collector pins, however, can be directly connected to each other. direct connection of the output pins between an ic product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. the ratings and conditions shown below for dc characteristics and ac characteristics are within the range for normal operation and quality assurance.
data sheet u14168ej3v0ds 21 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 capacitance (t a = 25 c, v dd = hv dd = cv dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i 15 pf input/output capacitance c io 15 pf output capacitance c o fc = 1 mhz unmeasured pins returned to 0 v. 15 pf operating conditions operation mode internal operating clock frequency ( ) operating ambient temperature (t a ) power supply voltage (v dd , hv dd ) pd703100a-40 2 to 40 mhz ? 40 to +70 c direct mode pd703100a-33, 703101a-33, 703102a-33 2 to 33 mhz ? 40 to +85 c pd703100a-40 20 to 40 mhz note 2 ? 40 to +70 c pll mode note 1 pd703100a-33, 703101a-33, 703102a-33 20 to 33 mhz note 3 ? 40 to +85 c 3.0 to 3.6 v notes 1. the internal operating clock frequency in the pll mode is the value when operating at 5 multiplication. operation is also possible at a frequency of 20 mh z or lower when used at 1 or 1/2 multiplication by setting the ckdivn bit (n = 0, 1) of the ckc register. 2. the input clock frequency used in pll mode should be 4.0 to 8.0 mhz. 3. the input clock frequency used in pll mode should be used by 4.0 to 6.6 mhz.
data sheet u14168ej3v0ds 22 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 recommended oscillators (a) ceramic resonator (t a = ?40 to +70 c ... pd703100a-40, t a = ?40 to +85 c ... pd703100a-33, 703101a-33, 703102a-33) (i) murata mfg. co., ltd. recommended circuit constant oscillation voltage range type product name oscillation frequency f xx (mhz) c1 (pf) c2 (pf) r d (k ? ) min. (v) max. (v) oscillation stabilization time (max.) t ost (ms) csac4.00mgc040 4.0 100 100 0 3.0 3.6 0.5 cstcc4.00mg0h6 4.0 on-chip on-chip 0 3.0 3.6 0.3 csac5.00mgc040 5.0 100 100 0 3.0 3.6 0.4 cstcc5.00mg0h6 5.0 on-chip on-chip 0 3.0 3.6 0.2 csac6.60mt 6.6 30 30 0 3.0 3.6 0.2 cstcc6.60mg0h6 6.6 on-chip on-chip 0 3.0 3.6 0.1 csac8.00mt 8.0 30 30 0 3.0 3.6 0.2 surface mount cstcc8.00mg0h6 8.0 on-chip on-chip 0 3.0 3.6 0.3 csa4.00mg040 4.0 100 100 0 3.0 3.6 0.5 cst4.00mgw040 4.0 on-chip on-chip 0 3.0 3.6 0.5 csa5.00mg040 5.0 100 100 0 3.0 3.6 0.5 cst5.00mgw040 5.0 on-chip on-chip 0 3.0 3.6 0.5 csa6.60mtz 6.6 30 30 0 3.0 3.6 0.1 cst6.60mtw 6.6 on-chip on-chip 0 3.0 3.6 0.1 csa8.00mtz 8.0 30 30 0 3.0 3.6 0.1 lead cst8.00mtw 8.0 on-chip on-chip 0 3.0 3.6 0.1 cautions 1. connect the oscillator as close to the x1 and x2 pins as possible. 2. do not wire any other signal lines in the area indicated by the broken lines. 3. thoroughly evaluate the matching between the pd703100a-33, 703100a-40, 703101-a33, 703102a-33 and the resonators. x1 x2 c1 c2 r d
data sheet u14168ej3v0ds 23 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (ii) tdk corporation (t a = ?40 to +85 c) (iii) kyocera corporation (t a = ?20 to +80 c) recommended circuit constant oscillation voltage range type product name oscillation frequency f xx (mhz) c1 (pf) c2 (pf) r d (k ? ) min. (v) max. (v) oscillation stabilization time (max.) t ost (ms) ccr4.0mc3 4.0 on-chip on-chip 0 3.0 3.6 0.17 ccr5.0mc3 5.0 on-chip on-chip 0 3.0 3.6 0.15 tdk ccr8.0mc5 8.0 on-chip on-chip 0 3.0 3.6 0.11 cautions 1. connect the oscillator as close to the x1 and x2 pins as possible. 2. do not wire any other signal lines in the area indicated by the broken lines. 3. thoroughly evaluate the matching between the pd703100a-33, 703100a-40, 703101a-33, 703102a-33 and the resonators. recommended circuit constant oscillation voltage range type product name oscillation frequency f xx (mhz) c1 (pf) c2 (pf) r d (k ? ) min. (v) max. (v) oscillation stabilization time (max.) t ost (ms) pbrc5.00br-a 5.0 on-chip on-chip 0 3.0 3.6 0.06 pbrc6.00br-a 6.0 on-chip on-chip 0 3.0 3.6 0.06 kyocera pbrc6.60br-a 6.6 on-chip on-chip 0 3.0 3.6 0.06 cautions 1. connect the oscillator as close to the x1 and x2 pins as possible. 2. do not wire any other signal lines in the area indicated by the broken lines. 3. thoroughly evaluate the matching between the pd703100a-33, 703100a-40, 703101a-33, 703102a-33 and the resonators. x1 x2 c1 c2 r d x1 x2 c1 c2 r d
data sheet u14168ej3v0ds 24 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (b) external clock input (t a = ?40 to +70 c ... pd703100a-40, t a = ?40 to +85 c ... pd703100a-33, 703101a-33, 703102a-33) cautions when turning on/off the power the pd703100a-33, 703100a-40, 703101a-33, and 703102a-33 are configured with power supply pins for the internal unit (v dd ) and for an external pin (hv dd ). the operation guaranteed range is v dd = hv dd = 3.0 to 3.6 v. the input and output state of ports may be undefined when the voltage exceeds this range. open x1 x2 external clock caution input cmos-level voltage to the x1 pin.
data sheet u14168ej3v0ds 25 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 dc characteristics (t a = ?40 to +70 c ... pd703100a-40, t a = ?40 to +85 c ... pd703100a-33, pd703101a-33, pd703102a-33, v dd = hv dd = cv dd = 3.0 to 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit except note 1 0.65hv dd hv dd + 0.3 v input voltage, high v ih note 1 0.8hv dd hv dd + 0.3 v except note 1 and note 2 ? 0.5 0.2hv dd v input voltage, low v il note 1 ? 0.5 0.15hv dd v x1 pin direct mode 0.8v dd v dd + 0.3 v clock input voltage, high v xh pll mode 0.8v dd v dd + 0.3 v x1 pin direct mode ? 0.3 0.15v dd v clock input voltage, low v xl pll mode ? 0.3 0.15v dd v hv t + note 1 , rising edge 2.0 v schmitt-triggered input threshold voltage hv t ? note 1 , falling edge 1.0 v schmitt-triggered input hysteresis width hv t + ?hv t ? note 1 0.3 v output voltage, high v oh i oh = ? 1.0 ma 0.8hv dd v output voltage, low v ol i ol = 2.5 ma 0.15hv dd v input leakage current, high i lih v i = hv dd and except note 2 10 a input leakage current, low i lil v i = 0 v and except note 2 ? 10 a output leakage current, high i loh v o = hv dd 10 a output leakage current, low i lol v o = 0 v ? 10 a notes 1. p04/intp100/dmarq0 to p07/intp103/dmarq3, p14/intp110/dmaak0 to p17/intp113/dmaak3, p34/intp130, p35/intp131/so2, p36/intp132/si2, p37/intp133/sck2, p104/intp120/tc0 to p107/intp123/tc3, p114/intp140, p115/intp141/so3, p116/intp142/si3, p117/intp143/sck3, p124/intp150 to p126/intp152, p127/intp153/adtrg, p02/tclr10, p12/tclr11, p32/tclr13, p102/tclr12, p112/tclr14, p122/tclr15, p03/ti10, p13/ti11, p33/ti13, p103/ti12, p113/ti14, p123/ti15, p20/nmi, p23/rxd0/si0, p24/sck0, p26/rxd1/si1, p27/sck1, mode0 to mode2, reset 2. when the p70/ani0 to p77/ani7 pins are used as analog input. remarks 1. typ. values are reference values for when t a = 25 c, v dd = cv dd = h v dd = 3.3 v. 2. direct mode: f x = 2 to 40 mhz ( pd703100a-40) f x = 2 to 33 mhz ( pd703100a-33, 703101a-33, 703102a-33) pll mode: f x = 20 to 40 mhz ( pd703100a-40) f x = 20 to 33 mhz ( pd703100a-33, 703101a-33, 703102a-33)
data sheet u14168ej3v0ds 26 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 dc characteristics (t a = ?40 to +70 c ... pd703100a-40, t a = ?40 to +85 c ... pd703100a-33, pd703101a-33, pd703102a-33, v dd = cv dd = hv dd = 3.0 to 3.6 v, v ss = 0 v) parameter symbol condition min. typ. max. unit during normal operation i dd1 2.5 f x 4.0 f x + 5.0 ma halt mode i dd2 1.2 f x 2.7 f x ma idle mode i dd3 2.0 5.0 ma pd703100a-40 1.5 5.0 ma power supply current stop mode i dd4 pll mode pd703100a-33, 703101a-33, 703102a-33 5.0 150 a remarks 1. typ. values are reference values for when t a = 25c, v dd = cv dd = hv dd = 3.3 v. 2. direct mode: f x = 2 to 40 mhz ( pd703100a-40) f x = 2 to 33 mhz ( pd703100a-33, 703101a-33, 703102a-33) pll mode: f x = 20 to 40 mhz ( pd703100a-40) f x = 20 to 33 mhz ( pd703100a-33, 703101a-33, 703102a-33)
data sheet u14168ej3v0ds 27 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 data retention characteristics (t a = ?40 to +70 c ... pd703100a-40, t a = ?40 to +85 c ... pd703100a-33, pd703101a-33, pd703102a-33) parameter symbol conditions min. typ. max. unit data retention voltage v dddr stop mode, v dd = v dddr 1.5 3.6 v pd703100a-40 5.0 ma data retention current i dddr v dd = v dddr pd703100a-33, 703101a-33, 703102a-33 150 a power supply voltage rise time t rvd 200 s power supply voltage fall time t fvd 200 s power supply voltage hold time (from stop mode setting) t hvd 0ms stop mode release signal input time t drel 0ns data retention high-level input voltage v ihdr note 0.8hv dddr v dddr v data retention low-level input voltage v ildr note 00.2v dddr v note p04/intp100/dmarq0 to p07/intp103/dmarq3, p14/intp110/dmaak0 to p17/intp113/dmaak3, p34/intp130, p35/intp131/so2, p36/intp132/si2, p37/intp133/sck2, p104/intp120/tc0 to p107/intp123/tc3, p114/intp140, p115/intp141/so3, p116/intp142/si3, p117/intp143/sck3, p124/intp150 to p126/intp152, p127/intp153/adtrg, p02/tclr10, p12/tclr11, p32/tclr13, p102/tclr12, p112/tclr14, p122/tclr15, p03/ti10, p13/ti11, p33/ti13, p103/ti12, p113/ti14, p123/ti15, p20/nmi, p23/rxd0/si0, p24/sck0, p26/rxd1/si1, p27/sck1, mode0 to mode2, reset remark typ. values are reference values for when t a = 25 c. hv dd reset (input) v ihdr v ihdr v ildr v dd t hvd t fvd v dddr t rvd t drel stop mode setting nmi (input) (released at falling edge) nmi (input) (released at rising edge)
data sheet u14168ej3v0ds 28 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 ac characteristics (t a = ?40 to +70 c ... pd703100a-40, t a = ?40 to +85 c ... pd703100a-33, pd703101a-33, pd703102a-33, v dd = hv dd = cv dd = 3.0 to 3.6 v, v ss = 0 v, output pin load capacitance: c l = 50 pf) ac test input measurement points (a) p04/intp100/dmarq0 to p07/intp103/dmarq3, p14/intp110/dmaak0 to p17/intp113/dmaak3, p34/ intp130, p35/intp131/so2, p36/intp132/si2, p37/intp133/sck2, p104/intp120/tc0 to p107/intp123/ tc3, p114/intp140, p115/intp141/so3, p116/intp142/si3, p117/intp143/sck3, p124/intp150 to p126/ intp152, p127/intp153/adtrg, p02/tclr10, p12/tclr11, p32/tclr13, p102/tclr12, p112/tclr14, p122/tclr15, p03/ti10, p13/ti11, p33/ti13, p103/ti12, p113/ti14, p123/ti15, p20/nmi, p23/rxd0/si0, p24/ sck0, p26/rxd1/si1, p27/sck1, mode0 to mode2, reset (b) pins other than those listed in (a) above ac test output measurement points hv dd 0 v 0.8hv dd 0.15hv dd 0.8hv dd 0.15hv dd point of measurement input signal v dd 0v 0.65hv dd 0.2hv dd 0.65hv dd 0.2hv dd point of measurement input signal 2.4 v 0.4 v 2.0 v 0.8 v 2.0 v 0.8 v point of measurement input signal
data sheet u14168ej3v0ds 29 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 load condition caution in cases where the load capacitance is greater than 50 pf due to the circuit configuration, insert a buffer or other element to reduce the device ? s load capacitance to below 50 pf. (1) clock timing parameter symbol conditions min. max. unit pd703100a-40 12.5 250 ns direct mode pd703100a-33, 703101a-33, 703102a-33, 15 250 ns pd703100a-40 125 250 ns x1 input cycle <1> t cyx pll mode pd703100a-33, 703101a-33, 703102-a33 150 250 ns direct mode 5 ns x1 input high-level width <2> t wxh pll mode 50 ns direct mode 5 ns x1 input low-level width <3> t wxl pll mode 50 ns direct mode 4 ns x1 input rise time <4> t xr pll mode 10 ns x1 input fall time <5> t xf direct mode 4 ns pll mode 10 ns pd703100a-40 25 500 ns clkout output cycle <6> t cyk pd703100a-33, 703101a-33, 703102a-33 30 500 ns clkout input high-level width <7> t wkh 0.5t ? 7 ns clkout input low-level width <8> t wkl 0.5t ? 4 ns clkout input rise time <9> t kr 5ns clkout input fall time <10> t kf 5ns remark t = t cyk c l = 50 pf dut (measured device)
data sheet u14168ej3v0ds 30 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 <4> <5> <2> <3> <1> x1 (pll mode) <1> <2> <3> <4> <5> <9> <10> <7> <8> <6> x1 (direct mode) clkout (output)
data sheet u14168ej3v0ds 31 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (2) output waveform (other than x1, clkout) parameter symbol conditions min. max. unit output rise time <12> t or 5ns output fall time <13> t of 5ns <13> signals other than x1, clkout <12> (3) reset timing parameter symbol conditions min. max. unit reset high-level width <14> t wrsh 500 ns when power supply is on, and stop mode has been released 500 + t os ns reset low-level width <15> t wrsl other than when power supply is on, and stop mode has been released 500 ns remark t os : oscillation stabilization time <14> <15> reset (input)
data sheet u14168ej3v0ds 32 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (4) sram, external rom, external i/o access timing (a) access timing (sram, external rom, external i/o) (1/2) parameter symbol conditions min. max. unit address, csn output delay time (from clkout ) <16> t dka 210ns address, csn output hold time (from clkout ) <17> t hka 210ns rd, iord delay time (from clkout ) <18> t dkrdl 214ns rd, iord delay time (from clkout ) <19> t hkrdh 214ns uwr, lwr, iowr delay time (from clkout ) <20> t dkwrl 210ns uwr, lwr, iowr delay time (from clkout ) <21> t hkwrh 210ns bcyst delay time (from clkout ) <22> t dkbsl 210ns bcyst delay time (from clkout ) <23> t hkbsh 210ns wait setup time (to clkout ) <24> t swk 10 ns wait hold time (from clkout ) <25> t hkw 2ns data input setup time (to clkout ) <26> t skid 10 ns data input hold time (from clkout ) <27> t hkid 2ns data output delay time (from clkout ) <28> t dkod 210ns data output hold time (from clkout ) <29> t hkod 210ns remarks 1. maintain at least one of the data input hold times, either t hkid or t hrdid . 2. n = 0 to 7
data sheet u14168ej3v0ds 33 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (a) access timing (sram, external rom, external i/o) (2/2) remarks 1. this is the timing when the number of waits due to the dwc1 and dwc2 registers is zero. 2. the broken lines indicate high impedance. 3. n = 0 to 7 clkout (output) a0 to a23 (output) csn (output) bcyst (output) rd, iord (output) [read] uwr, lwr, iowr (output) [write] d0 to d15 (i/o) [read] d0 to d15 (i/o) [write] wait (input) <16> <17> <22> <23> <18> <19> <20> <21> <26> <27> <28> <29> <24> <25> <24> <25> t1 tw t2
data sheet u14168ej3v0ds 34 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (b) read timing (sram, external rom, external i/o) (1/2) parameter symbol conditions min. max. unit data input setup time (to address) <30> t said (1.5 + w d + w) t ? 20 ns data input setup time (to rd) <31> t srdid (1 + w d + w) t ? 24 ns rd, iord low-level width <32> t wrdl (1 + w d + w) t ? 10 ns rd, iord high-level width <33> t wrdh t ? 10 ns delay time from address, csn to rd, iord <34> t dard 0.5t ? 10 ns delay time from rd, iord to address <35> t drda (0.5 + i) t ? 5 ns data input hold time (from rd, iord ) <36> t hrdid 0ns delay time from rd, iord to data output <37> t drdod (0.5 + i) t ? 10 ns wait setup time (to address) <38> t saw note t ? 20 ns wait setup time (to bcyst ) <39> t sbsw note t ? 20 ns wait hold time (to bcyst ) <40> t hbsw note 0ns note for the first wait sampling when the number of waits due to the dwc1 and dwc2 registers is zero. remarks 1. t = t cyk 2. w: number of waits due to wait 3. w d : number of waits due to the dwc1 and dwc2 registers 4. i: number of idle states that are inserted when a write cycle follows a read cycle 5. maintain at least one of the data input hold times, either t hkid or t hrdid . 6. n = 0 to 7
data sheet u14168ej3v0ds 35 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (b) read timing (sram, external rom, external i/o) (2/2) remarks 1. this is the timing when the number of waits due to the dwc1 and dwc2 registers is zero. 2. the broken lines indicate high impedance. 3. n = 0 to 7 uwr, lwr, iowr (output) rd, iord (output) d0 to d15 (i/o) t1 tw t2 clkout (output) <33> <32> <35> <38> <34> <31> <30> <36> <37> <39> <40> a0 to a23 (output) csn (output) wait (input) bcyst (output)
data sheet u14168ej3v0ds 36 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (c) write timing (sram, external rom, external i/o) (1/2) parameter symbol conditions min. max. unit wait setup time (to address) <38> t saw note t ? 20 ns wait setup time (to bcyst ) <39> t sbsw note t ? 20 ns wait hold time (from bcyst ) <40> t hbsw note 0ns delay time from address, csn to uwr, lwr, iowr <41> t dawr 0.5t ? 5 ns address setup time (to uwr, lwr, iowr ) <42> t sawr (1.5 + w d + w) t ? 10 ns delay time from uwr, lwr, iowr to address <43> t dwra 0.5t ? 5 ns uwr, lwr, iowr high-level width <44> t wwrh t ? 10 ns uwr, lwr, iowr low-level width <45> t wwrl (1 + w d + w) t ? 10 ns data output setup time (to uwr, lwr, iowr ) <46> t sodwr (1.5 + w d + w) t ? 10 ns data output hold time (from uwr, lwr, iowr ) <47> t hwrod 0.5t ? 5 ns note for the first wait sampling when the number of waits due to the dwc1 and dwc2 registers is zero. remarks 1. t = t cyk 2. w: number of waits due to wait 3. w d : number of waits due to the dwc1 and dwc2 registers 4. n = 0 to 7
data sheet u14168ej3v0ds 37 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (c) write timing (sram, external rom, external i/o) (2/2) remarks 1. this is the timing when the number of waits due to the dwc1 and dwc2 registers is zero. 2. the broken lines indicate high impedance. 3. n = 0 to 7 t1 tw t2 clkout (output) <44> <45> <43> <38> <46> <47> <39> <40> <41> <42> a0 to a23 (output) csn (output) rd, iord (output) uwr, lwr, iowr (output) d0 to d15 (i/o) wait (input) bcyst (output)
data sheet u14168ej3v0ds 38 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (d) dma flyby transfer timing (sram external i/o transfer) (1/2) parameter symbol conditions min. max. unit wait setup time (to clkout ) <24> t swk 10 ns wait hold time (from clkout ) <25> t hkw 2ns rd low-level width <32> t wrdl (1 + w d + w f + w) t ? 10 ns rd high-level width <33> t wrdh t ? 10 ns delay time from address, csn to rd <34> t dard 0.5t ? 5 ns delay time from rd to address <35> t drda (0.5 + i) t ? 5 ns delay time from rd to data output <37> t drdod (0.5 + i) t ? 10 ns wait setup time (to address) <38> t saw note t ? 20 ns wait setup time (to bcyst ) <39> t sbsw note t ? 20 ns wait hold time (from bcyst ) <40> t hbsw note 0ns delay time from address to iowr <41> t dawr 0.5t ? 5 ns address setup time (to iowr ) <42> t sawr (1.5 + w d + w) t ? 10 ns delay time from iowr to address <43> t dwra 0.5t ? 5 ns iowr high-level width <44> t wwrh t ? 10 ns iowr low-level width <45> t wwrl (1 + w d + w) t ? 10 ns w f = 0 0 ns delay time from iowr to rd <48> t dwrrd w f = 1 t ? 10 ns delay time from dmaakm to iowr <49> t ddawr 0.5t ? 10 ns delay time from iowr to dmaakm <50> t dwrda (0.5 + w f ) t ? 10 ns note for the first wait sampling when the number of waits due to the dwc1 and dwc2 registers is zero. remarks 1. t = t cyk 2. w: number of waits due to wait 3. w d : number of waits due to the dwc1 and dwc2 registers 4. w f : number of waits that are inserted for a source-side access during a dma flyby transfer 5. i: number of idle states that are inserted when a write cycle follows a read cycle 6. n = 0 to 7, m = 0 to 3
data sheet u14168ej3v0ds 39 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (d) dma flyby transfer timing (sram external i/o transfer) (2/2) remarks 1. this is the timing when the number of waits due to the dwc1 and dwc2 registers is zero and w f = 0. 2. the broken lines indicate high impedance. 3. n = 0 to 7, m = 0 to 3 clkout (output) t1 tw t2 <33> <32> <35> <34> <48> <50> <49> <43> <42> <41> <44> <45> <37> <38> <24> <24> <25> <25> <40> <39> a0 to a23 (output) csn (output) rd (output) dmaakm (output) iord (output) iowr (output) uwr, lwr (output) d0 to d15 (i/o) wait (input) bcyst (output)
data sheet u14168ej3v0ds 40 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (e) dma flyby transfer timing (external i/o sram transfer) (1/2) parameter symbol conditions min. max. unit wait setup time (to clkout ) <24> t swk 10 ns wait hold time (from clkout ) <25> t hkw 2ns iord low-level width <32> t wrdl (1 + w d + w f + w) t ? 10 ns iord high-level width <33> t wrdh t ? 10 ns delay time from address, csn to iord <34> t dard 0.5t ? 5 ns delay time from iord to address <35> t drda (0.5 + i) t ? 5 ns delay time from iord to data output <37> t drdod (0.5 + i) t ? 10 ns wait setup time (to address) <38> t saw note t ? 20 ns wait setup time (to bcyst ) <39> t sbsw note t ? 20 ns wait hold time (from bcyst ) <40> t hbsw note 0ns delay time from address to uwr, lwr <41> t dawr 0.5t ? 5 ns address setup time (to uwr, lwr ) <42> t sawr (1.5 + w d + w) t ? 10 ns delay time from uwr, lwr to address <43> t dwra 0.5t ? 5 ns uwr, lwr high-level width <44> t wwrh t ? 10 ns uwr, lwr low-level width <45> t wwrl (1 + w d + w) t ? 10 ns w f = 0 0 ns delay time from uwr, lwr to iord <48> t dwrrd w f = 1 t ? 10 ns delay time from dmaakm to iord <51> t ddard 0.5t ? 10 ns delay time from iord to dmaakm <52> t drdda 0.5t ? 10 ns note for the first wait sampling when the number of waits due to the dwc1 and dwc2 registers is zero. remarks 1. t = t cyk 2. w: number of waits due to wait 3. w d : number of waits due to the dwc1 and dwc2 registers 4. w f : number of waits that are inserted for a source-side access during a dma flyby transfer 5. i: number of idle states that are inserted when a write cycle follows a read cycle 6. n = 0 to 7, m = 0 to 3
data sheet u14168ej3v0ds 41 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (e) dma flyby transfer timing (external i/o sram transfer) (2/2) remarks 1. this is the timing when the number of waits due to the dwc1 and dwc2 registers is zero and w f = 0. 2. the broken lines indicate high impedance. 3. n = 0 to 7, m = 0 to 3 clkout (output) t1 tw t2 <44> <45> <48> <52> <33> <37> <38> <24> <24> <25> <25> <40> <39> <42> <41> <43> <51> <32> <35> <34> a0 to a23 (output) csn (output) uwr, lwr (output) rd (output) dmaakm (output) iowr (output) iord (output) d0 to d15 (i/o) wait (input) bcyst (output)
data sheet u14168ej3v0ds 42 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (5) page rom access timing (1/2) parameter symbol conditions min. max. unit wait setup time (to clkout ) <24> t swk 10 ns wait hold time (from clkout ) <25> t hkw 2ns data input setup time (to clkout ) <26> t skid 10 ns data input hold time (from clkout ) <27> t hkid 2ns off-page data input setup time (to address) <30> t said (1.5 + w d + w) t ? 20 ns off-page data input setup time (to rd) <31> t srdid (1 + w d + w) t ? 24 ns off-page rd low-level width <32> t wrdl (1 + w d + w) t ? 10 ns rd high-level width <33> t wrdh 0.5t ? 10 ns data input hold time (from rd) <36> t hrdid 0ns delay time from rd to data output <37> t drdod (0.5 + i) t ? 10 ns on-page rd low-level width <53> t wordl (1.5 + w pr + w) t ? 10 ns on-page data input setup time (to address) <54> t soaid (1.5 + w pr + w) t ? 20 ns on-page data input setup time (to rd) <55> t sordid (1.5 + w pr + w) t ? 24 ns remarks 1. t = t cyk 2. w: number of waits due to wait 3. w d : number of waits due to the dwc1 and dwc2 registers 4. w pr : number of waits due to the prc register 5. i: number of idle states that are inserted when a write cycle follows a read cycle 6. maintain at least one of the data input hold times t hkid and t hrdid.
data sheet u14168ej3v0ds 43 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (5) page rom access timing (2/2) note the on-page and off-page addresses are as follows. prc register ma5 ma4 ma3 on-page addresses off-page addresses 0 0 0 a0, a1 a2 to a23 0 0 1 a0 to a2 a3 to a23 0 1 1 a0 to a3 a4 to a23 1 1 1 a0 to a4 a5 to a23 remarks 1. this is the timing for the following case. number of waits due to the dwc1 and dwc2 registers (tdw): 1 number of waits due to the prc register (tprw): 1 2. the broken lines indicate high impedance. 3. n = 0 to 7 clkout (output) on-page address note t1 tdw tw t2 to1 tprw tw to2 <24> <25> <24> <25> <24> <25> <24> <25> <26> <27> <36> <32> <31> <53> <55> <27> <26> <36> <37> <33> <30> <54> off-page address note csn (output) uwr, lwr (output) rd (output) d0 to d15 (i/o) wait (input) bcyst (output)
data sheet u14168ej3v0ds 44 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (6) dram access timing (a) read timing (high-speed page dram access, normal access: off-page) (1/3) parameter symbol conditions min. max. unit wait setup time (to clkout ) <24> t swk 10 ns wait hold time (from clkout ) <25> t hkw 2ns data input setup time (to clkout ) <26> t skid 10 ns data input hold time (from clkout ) <27> t hkid 2ns delay time from oe to data output <37> t drdod (0.5 + i) t ? 10 ns row address setup time <56> t asr (0.5 + w rp ) t ? 10 ns row address hold time <57> t rah (0.5 + w rh ) t ? 10 ns column address setup time <58> t asc 0.5t ? 10 ns column address hold time <59> t cah (1.5 + w da + w) t ? 10 ns read/write cycle time <60> t rc (3 + w rp + w rh + w da + w) t ? 10 ns ras precharge time <61> t rp (0.5 + w rp ) t ? 5 ns ras pulse time <62> t ras (2.5 + w rh + w da + w) t ? 10 ns ras hold time <63> t rsh (1.5 + w da + w) t ? 10 ns column address read time for ras <64> t ral (2 + w da + w) t ? 10 ns cas pulse width <65> t cas (1 + w da + w) t ? 10 ns cas-ras precharge time <66> t crp (1 + w rp ) t ? 10 ns cas hold time <67> t csh (2 + w rh + w da + w) t ? 10 ns we setup time <68> t rcs (2 + w rp + w rh ) t ? 10 ns we hold time (from ras ) <69> t rrh 0.5t ? 10 ns we hold time (from cas ) <70> t rch t ? 10 ns cas precharge time <71> t cpn (2 + w rp + w rh ) t ? 5 ns output enable access time <72> t oea (2 + w rp + w rh + w da + w) t ? 20 ns ras access time <73> t rac (2 + w rh + w da + w) t ? 20 ns access time from column address <74> t aa (1.5 + w da + w) t ? 20 ns cas access time <75> t cac (1 + w da + w) t ? 20 ns remarks 1. t = t cyk 2. w: number of waits due to wait 3. w rp : number of waits due to the rpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. w rh : number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 5. w da : number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 6. i: number of idle states that are inserted when a write cycle follows a read cycle
data sheet u14168ej3v0ds 45 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (a) read timing (high-speed page dram access, normal access: off-page) (2/3) parameter symbol conditions min. max. unit ras column address delay time <76> t rad (0.5 + w rh ) t ? 10 ns ras-cas delay time <77> t rcd (1 + w rh ) t ? 10 ns output buffer turn-off delay time (from oe ) <78> t oez 0ns output buffer turn-off delay time (from cas ) <79> t off 0 remarks 1. t = t cyk 2. w rh : number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13)
data sheet u14168ej3v0ds 46 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (a) read timing (high-speed page dram access, normal access: off-page) (3/3) remarks 1. this is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). number of waits due to the rpcxx bit of the drcn register (trpw): 1 number of waits due to the rhcxx bit of the drcn register (trhw): 1 number of waits due to the dacxx bit of the drcn register (tdaw): 1 2. the broken lines indicate high impedance. 3. n = 0 to 7 trpw trhw t2 t1 tdaw tw t3 <56> <61> <57> <58> <59> <62> <76> <63> <64> <60> <77> <65> <67> <66> <71> <73> <68> <75> <74> <72> <70> <69> <79> <37> <27> <25> <26> <25> <24> <78> <24> clkout (output) a0 to a23 (output) rasn (output) we (output) oe (output) wait (input) d0 to d15 (i/o) ucas (output) lcas (output) row address column address
data sheet u14168ej3v0ds 47 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 [memo]
data sheet u14168ej3v0ds 48 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (b) read timing (high-speed page dram access: on-page) (1/2) parameter symbol conditions min. max. unit data input setup time (to clkout ) <26> t skid 10 ns data input hold time (from clkout ) <27> t hkid 2ns delay time from oe to data output <37> t drdod (0.5 + i) t ? 10 ns column address setup time <58> t asc (0.5 + w cp ) t ? 10 ns column address hold time <59> t cah (1.5 + w da ) t ? 10 ns ras hold time <63> t rsh (1.5 + w da ) t ? 10 ns column address read time for ras <64> t ral (2 + w cp + w da ) t ? 10 ns cas pulse width <65> t cas (1 + w da ) t ? 10 ns we setup time (to cas ) <68> t rcs (1 + w cp ) t ? 10 ns we hold time (from ras ) <69> t rrh 0.5t ? 10 ns we hold time (from cas ) <70> t rch t ? 10 ns output enable access time <72> t oea (1 + w cp + w da ) t ? 20 ns access time from column address <74> t aa (1.5 + w cp + w da ) t ? 20 ns cas access time <75> t cac (1 + w da ) t ? 20 ns output buffer turn-off delay time (from oe ) <78> t oez 0ns output buffer turn-off delay time (from cas ) <79> t off 0ns access time from cas precharge <80> t acp (2 + w cp + w da ) t ? 20 ns cas precharge time <81> t cp (1 + w cp ) t ? 5 ns high-speed page mode cycle time <82> t pc (2 + w cp + w da ) t ? 10 ns ras hold time for cas precharge <83> t rhcp (2.5 + w cp + w da ) t ? 10 ns remarks 1. t = t cyk 2. w cp : number of waits due to the cpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 3. w da : number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. i: number of idle states that are inserted when a write cycle follows a read cycle
data sheet u14168ej3v0ds 49 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (b) read timing (high-speed page dram access: on-page) (2/2) remarks 1. this is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). number of waits due to the cpcxx bit of the drcn register (tcpw): 1 number of waits due to the dacxx bit of the drcn register (tdaw): 1 2. the broken lines indicate high impedance. 3. n = 0 to 7 tcpw to1 tdaw to2 <58> <59> <63> <64> <83> <65> <81> <82> <68> <75> <72> <26> <79> <37> <74> <80> <27> <78> <70> <69> clkout (output) a0 to a23 (output) rasn (output) ucas (output) lcas (output) we (output) oe (output) d0 to d15 (i/o) wait (input) column address
data sheet u14168ej3v0ds 50 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (c) write timing (high-speed page dram access, normal access: off-page) (1/2) parameter symbol conditions min. max. unit wait setup time (to clkout ) <24> t swk 10 ns wait hold time (from clkout ) <25> t hkw 2ns row address setup time <56> t asr (0.5 + w rp ) t ? 10 ns row address hold time <57> t rah (0.5 + w rh ) t ? 10 ns column address setup time <58> t asc 0.5t ? 10 ns column address hold time <59> t cah (1.5 + w da + w) t ? 10 ns read/write cycle time <60> t rc (3 + w rp + w rh + w da + w) t ? 10 ns ras precharge time <61> t rp (0.5 + w rp ) t ? 5 ns ras pulse time <62> t ras (2.5 + w rh + w da + w) t ? 10 ns ras hold time <63> t rsh (1.5 + w da + w) t ? 10 ns column address read time (from ras ) <64> t ral (2 + w da + w) t ? 10 ns cas pulse width <65> t cas (1 + w da + w) t ? 10 ns cas-ras precharge time <66> t crp (1 + w rh ) t ? 10 ns cas hold time <67> t csh (2 + w rh + w da + w) t ? 10 ns cas precharge time <71> t cpn (2 + w rp + w rh ) t ? 5 ns ras column address delay time <76> t rad (0.5 + w rh ) t ? 10 ns ras-cas delay time <77> t rcd (1 + w rh ) t ? 10 ns we setup time (to cas ) <84> t wcs (1 + w rp + w rh ) t ? 10 ns we hold time (from cas ) <85> t wch (1 + w da + w) t ? 10 ns data setup time (to cas ) <86> t ds (1.5 + w rp + w rh ) t ? 10 ns data hold time (from cas ) <87> t dh (1.5 + w da + w) t ? 10 ns remarks 1. t = t cyk 2. w: number of waits due to wait 3. w rp : number of waits due to the rpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. w rh : number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 5. w da : number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13)
data sheet u14168ej3v0ds 51 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (c) write timing (high-speed page dram access, normal access: off-page) (2/2) remarks 1. this is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). number of waits due to the rpcxx bit of the drcn register (trpw): 1 number of waits due to the rhcxx bit of the drcn register (trhw): 1 number of waits due to the dacxx bit of the drcn register (tdaw): 1 2. the broken lines indicate high impedance. 3. n = 0 to 7 trpw trhw t2 t1 tdaw tw t3 <56> <61> <57> <58> <59> <62> <76> <63> <64> <60> <77> <65> <67> <66> <71> <84> <25> <25> <24> <24> <85> <86> <87> clkout (output) a0 to a23 (output) rasn (output) ucas (output) lcas (output) we (output) oe (output) d0 to d15 (i/o) wait (input) row address column address
data sheet u14168ej3v0ds 52 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (d) write timing (high-speed page dram access: on-page) (1/2) parameter symbol conditions min. max. unit column address setup time <58> t asc (0.5 + w cp ) t ? 10 ns column address hold time <59> t cah (1.5 + w da ) t ? 10 ns ras hold time <63> t rsh (1.5 + w da ) t ? 10 ns column address read time (from ras ) <64> t ral (2 + w cp + w da ) t ? 10 ns cas pulse width <65> t cas (1 + w da ) t ? 10 ns cas precharge time <81> t cp (1 + w cp ) t ? 5 ns ras hold time for cas precharge <83> t rhcp (2.5 + w cp + w da ) t ? 10 ns we setup time (to cas ) <84> t wcs w cp 1w cp t ? 10 ns we hold time (from cas ) <85> t wch (1 + w da ) t ? 10 ns data setup time (to cas ) <86> t ds (0.5 + w cp ) t ? 10 ns data hold time (from cas ) <87> t dh (1.5 + w da ) t ? 10 ns we read time (from ras ) <88> t rwl w cp = 0 (1.5 + w da ) t ? 10 ns we read time (from cas ) <89> t cwl w cp = 0 (1 + w da ) t ? 10 ns data setup time (to we ) <90> t dswe w cp = 0 0.5t ? 10 ns data hold time (from we ) <91> t dhwe w cp = 0 (1.5 + w da ) t ? 10 ns we pulse width <92> t wp w cp = 0 (1 + w da ) t ? 10 ns remarks 1. t = t cyk 2. w cp : number of waits due to the cpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 3. w da : number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13)
data sheet u14168ej3v0ds 53 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (d) write timing (high-speed page dram access: on-page) (2/2) remarks 1. this is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). number of waits due to the cpcxx bit of the drcn register (tcpw ): 1 number of waits due to the dacxx bit of the drcn register (tdaw): 1 2. the broken lines indicate high impedance. 3. n = 0 to 7 tcpw to1 tdaw to2 <58> <59> <63> <64> <83> <81> <65> <89> <88> <84> <85> <92> <91> <86> <87> <90> clkout (output) a0 to a23 (output) rasn (output) ucas (output) lcas (output) oe (output) we (output) d0 to d15 (i/o) wait (input) column address
data sheet u14168ej3v0ds 54 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (e) read timing (edo dram) (1/3) parameter symbol conditions min. max. unit data input setup time (to clkout ) <26> t skid 10 ns data input hold time (from clkout ) <27> t hkid 2ns data output delay time from oe <37> t drdod (0.5 + i) t ? 10 ns row address setup time <56> t asr (0.5 + w rp ) t ? 10 ns row address hold time <57> t rah (0.5 + w rh ) t ? 10 ns column address setup time <58> t asc 0.5t ? 10 ns column address hold time <59> t cah (0.5 + w da ) t ? 10 ns ras precharge time <61> t rp (0.5 + w rp ) t ? 5 ns column address read time (from ras ) <64> t ral (2 + w cp + w da ) t ? 10 ns cas-ras precharge time <66> t crp (1 + w rp ) t ? 10 ns cas hold time <67> t csh (1.5 + w rh + w da ) t ? 10 ns we setup time (to cas ) <68> t rcs (2 + w rp + w rh ) t ? 10 ns we hold time (from ras ) <69> t rrh 0.5t ? 10 ns we hold time (from cas ) <70> t rch 1.5t ? 10 ns ras access time <73> t rac (2 + w rh + w da ) t ? 20 ns access time from column address <74> t aa (1.5 + w da ) t ? 20 ns cas access time <75> t cac (1 + w da ) t ? 20 ns column address delay time from ras <76> t rad (0.5 + w rh ) t ? 10 ns ras-cas delay time <77> t rcd (1 + w rh ) t ? 10 ns output buffer turn-off delay time (from oe) <78> t oez 0ns access time from cas precharge <80> t acp (1.5 + w cp + w da ) t ? 20 ns cas precharge time <81> t cp (0.5 + w cp ) t ? 5 ns ras hold time for cas precharge <83> t rhcp (2 + w cp + w da ) t ? 10 ns read cycle time <93> t hpc (1 + w da + w cp ) t ? 10 ns ras pulse width <94> t rasp (2.5 + w rh + w da ) t ? 10 ns cas pulse width <95> t hcas (0.5 + w da ) t ? 10 ns off-page <96> t och1 (2 + w rh + w da ) t ? 10 ns cas hold time from oe on-page <97> t och2 (0.5 + w da ) t ? 10 ns data input hold time (from cas ) <98> t dhc 0ns remarks 1. t = t cyk 2. w rp : number of waits due to the rpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 3. w rh : number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. w da : number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 5. w cp : number of waits due to the cpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 6. i: number of idle states that are inserted when a write cycle follows a read cycle
data sheet u14168ej3v0ds 55 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (e) read timing (edo dram) (2/3) parameter symbol conditions min. max. unit off-page <99> t oea1 (2 + w pr + w rh + w da ) t ? 20 ns output enable access time on-page <100> t oea2 (1 + w cp + w da ) t ? 20 ns remarks 1. t = t cyk 2. w rp : number of waits due to the rpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 3. w rh : number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. w da : number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 5. w cp : number of waits due to the cpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13)
data sheet u14168ej3v0ds 56 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (e) read timing (edo dram) (3/3) note for on-page access from another cycle during the rasn low level signal. remarks 1. this is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). number of waits due to the rpcxx bit of the drcn register (trpw): 1 number of waits due to the rhcxx bit of the drcn register (trhw): 1 number of waits due to the dacxx bit of the drcn register (tdaw): 1 number of waits due to the cpcxx bit of the drcn register (tcpw): 1 2. the broken lines indicate high impedance. 3. n = 0 to 7 trpw t1 trhw t2 tdaw tcpw tb tdaw te <56> <57> <59> <58> <76> <64> <94> <61> <67> <83> <77> <95> <81> <75> <66> <93> <95> <80> <97> <74> <27> <78> data <74> data <70> <69> <68> <96> note <100> <26> <37> <27> <98> <26> <75> <73> <99> clkout (output) a0 to a23 (output) rasn (output) ucas (output) lcas (output) we (output) oe (output) d0 to d15 (i/o) bcyst (output) wait (input) row address column address column address
data sheet u14168ej3v0ds 57 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 [memo]
data sheet u14168ej3v0ds 58 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (f) write timing (edo dram) (1/2) parameter symbol conditions min. max. unit row address setup time <56> t asr (0.5 + w rp ) t ? 10 ns row address hold time <57> t rah (0.5 + w rh ) t ? 10 ns column address setup time <58> t asc 0.5t ? 10 ns column address hold time <59> t cah (0.5 + w da ) t ? 10 ns ras precharge time <61> t rp (0.5 + w rp ) t ? 5 ns ras hold time <63> t rsh (1.5 + w da ) t ? 10 ns column address read time (from ras ) <64> t ral (2 + w cp + w da ) t ? 10 ns cas-ras precharge time <66> t crp (1 + w rp ) t ? 10 ns cas hold time <67> t csh (1.5 + w rh + w da ) t ? 10 ns column address delay time from ras <76> t rad (0.5 + w rh ) t ? 10 ns ras-cas delay time <77> t rcd (1 + w rh ) t ? 10 ns cas precharge time <81> t cp (0.5 + w cp ) t ? 5 ns ras hold time for cas precharge <83> t rhcp (2 + w cp + w da ) t ? 10 ns we hold time (from cas ) <85> t wch (1 + w da ) t ? 10 ns data hold time (from cas ) <87> t dh (0.5 + w da ) t ? 10 ns we read time (from ras ) on-page <88> t rwl w cp = 0 (1.5 + w da ) t ? 10 ns we read time (from cas ) on-page <89> t cwl w cp = 0 (0.5 + w da ) t ? 10 ns we pulse width on-page <92> t wp w cp = 0 (1 + w da ) t ? 10 ns write cycle time <93> t hpc (1 + w da + w cp ) t ? 10 ns ras pulse width <94> t rasp (2.5 + w rh + w da ) t ? 10 ns cas pulse width <95> t hcas (0.5 + w da ) t ? 10 ns off-page <101> t wcs1 (1 + w rp + w rh ) t ? 10 ns we setup time (to cas ) on-page <102> t wcs2 w cp 1w cp t ? 10 ns off-page <103> t ds1 (1.5 + w rp + w rh ) t ? 10 ns data setup time (to cas ) on-page <104> t ds2 (0.5 + w cp ) t ? 10 ns remarks 1. t = t cyk 2. w rp : number of waits due to the rpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 3. w rh : number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. w da : number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 5. w cp : number of waits due to the cpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13)
data sheet u14168ej3v0ds 59 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (f) write timing (edo dram) (2/2) remarks 1. this is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). number of waits due to the rpcxx bit of the drcn register (trpw): 1 number of waits due to the rhcxx bit of the drcn register (trhw): 1 number of waits due to the dacxx bit of the drcn register (tdaw): 1 number of waits due to the cpcxx bit of the drcn register (tcpw): 1 2. the broken lines indicate high impedance. 3. n = 0 to 7 trpw t1 trhw t2 tdaw tcpw tb tdaw te <56> <57> <59> <58> <58> <59> <76> <64> <94> <61> <67> <83> <77> <95> <81> <63> <66> <93> <95> <89> <88> <102> <101> <92> <85> <85> <103> <87> <104> <87> data data clkout (output) a0 to a23 (output) rasn (output) ucas (output) lcas (output) rd (output) oe (output) we (output) d0 to d15 (i/o) bcyst (output) wait (input) row address column address column address
data sheet u14168ej3v0ds 60 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (g) dma flyby transfer timing (dram (edo, high-speed page) external i/o transfer) (1/3) parameter symbol conditions min. max. unit wait setup time (to clkout ) <24> t swk 10 ns wait hold time (from clkout ) <25> t hkw 2ns delay time from oe to data output <37> t drdod (0.5 + i) t ? 10 ns delay time from address to iowr <41> t dawr (0.5 + w rp ) t ? 5 ns address setup time (to iowr ) <42> t sawr (2 + w rp + w rh + w da ) t ? 10 ns delay time from iowr to address <43> t dwra 0.5t ? 5 ns w f = 0 0 ns delay time from iowr to rd <48> t dwrrd w f = 1 t ? 10 ns iowr low-level width <50> t wwrl (2 + w rh + w da + w) t ? 10 ns row address setup time <56> t asr (0.5 + w rp ) t ? 10 ns row address hold time <57> t rah (0.5 + w rh ) t ? 10 ns column address setup time <58> t asc 0.5t ? 10 ns column address hold time <59> t cah (1.5 + w da + w f + w) t ? 10 ns read/write cycle time <60> t rc (3 + w rp + w rh + w da + w f +w) t ? 10 ns ras precharge time <61> t rp (0.5 + w rp ) t ? 5 ns ras hold time <63> t rsh (1.5 + w da + w f + w) t ? 10 ns column address read time for ras <64> t ral (2 + w cp + w da + w f + w) t ? 10 ns cas pulse width <65> t cas (1 + w da + w f + w) t ? 10 ns cas-ras precharge time <66> t crp (1 + w rp ) t ? 10 ns cas hold time <67> t csh (2 + w rh + w da + w f +w) t ? 10 ns we setup time (to cas ) <68> t rcs (2 + w rp + w rh ) t ? 10 ns we hold time (from ras ) <69> t rrh 0.5t ? 10 ns we hold time (from cas ) <70> t rch 1.5t ? 10 ns cas precharge time <71> t cpn (2 + w rp + w rh ) t ? 5 ns remarks 1. t = t cyk 2. w: number of waits due to wait 3. w rp : number of waits due to the rpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. w rh : number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 5 .w da : number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 6. w cp : number of waits due to the cpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 7. w f : number of waits that are inserted for a source-side access during a dma flyby transfer 8. i: number of idle states that are inserted when a write cycle follows a read cycle
data sheet u14168ej3v0ds 61 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (g) dma flyby transfer timing (dram (edo, high-speed page) external i/o transfer) (2/3) parameter symbol conditions min. max. unit delay time from ras to column address <76> t rad (0.5 + w rh ) t ? 10 ns ras-cas delay time <77> t rcd (1 + w rh ) t ? 10 ns output buffer turn-off delay time (from oe ) <78> t oez 0ns output buffer turn-off delay time (from cas ) <79> t off 0ns cas precharge time <81> t cp (0.5 + w cp ) t ? 5 ns high-speed page mode cycle time <82> t pc (2 + w cp + w da + w f + w) t ? 10 ns ras hold time for cas precharge <83> t rhcp (2.5 + w cp + w da + w f + w) t ? 10 ns ras pulse width <94> t rasp (2.5 + w rh + w da + w f + w) t ? 10 ns off-page <96> t och1 (2.5 + w rp + w rh + w da + w f + w) t ? 10 ns oe cas hold time (from cas ) on-page <97> t och2 (1.5 + w cp + w da + w f + w) t ? 10 ns delay time from dmaakm to cas <105> t ddacs (1.5 + w rh ) t ? 10 ns delay time from iowr to cas <106> t drdcs (1 + w rh ) t ? 10 ns remarks 1. t=t cyk 2. w: number of waits due to wait 3. w cp : number of waits due to the cpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. w da : number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 5. w rh : number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 6. w rp : number of waits due to the rpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 7. w f : number of waits that are inserted for a source-side access during a dma flyby transfer 8. m = 0 to 3
data sheet u14168ej3v0ds 62 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (g) dma flyby transfer timing (dram (edo, high-speed page) external i/o transfer) (3/3) remarks 1. this is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). number of waits due to the rpcxx bit of the drcn register (trpw): 1 number of waits due to the rhcxx bit of the drcn register (trhw): 1 number of waits due to the dacxx bit of the drcn register (tdaw): 1 number of waits due to the cpcxx bit of the drcn register (tcpw): 1 number of waits that are inserted for a source-side access during a dma flyby transfer: 0 2. the broken lines indicate high impedance. 3. n = 0 to 7, m = 0 to 3 clkout (output) trpw t1 trhw t2 tdaw tw t3 tcpw to1 tdaw tw to2 <57> <56> <59> a0 to a23 (output) <61> <94> d0 to d15 (i/o) <58> <76> <64> <60> <66> <67> <77> <65> <81> <83> <63> <69> <71> <96> <82> <97> <79> <48> <105> <68> <41> <50> <42> <24> <24> <24> <25> <25> <78> <37> <25> <106> <70> ________ rasn (output) ________ ???? lcas (output) ________ ucas (output) ____ ???? oe (output) ____ ???? rd (output) _____________ ???? dmaakm (output) _____ ???? we (output) _______ ???? iord (output) ________ ???? iowr (output) __________ ???? bcyst (output) ________ ???? wait (input) <43> row address column address column address data data
data sheet u14168ej3v0ds 63 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (h) dma flyby transfer timing (external i/o dram (edo, high-speed page) transfer) (1/3) parameter symbol conditions min. max. unit wait setup time (to clkout ) <24> t swk 10 ns wait hold time (from clkout ) <25> t hkw 2ns iord low-level width <32> t wrdl (2 + w rh + w da + w f + w) t ? 10 ns iord high-level width <33> t wrdh t ? 5 ns delay time from address to iord <34> t dard 0.5t ? 5 ns delay time from iord to address <35> t drda (0.5 + i) t ? 5 ns row address setup time <56> t asr (0.5 + w rp ) t ? 10 ns row address hold time <57> t rah (0.5 + w rh ) t ? 10 ns column address setup time <58> t asc 0.5t ? 10 ns column address hold time <59> t cah (1.5 + w da + w f ) t ? 10 ns read/write cycle time <60> t rc (3 + w rp + w rh + w da + w f + w) t ? 10 ns ras precharge time <61> t rp (0.5 + w rp ) t ? 5 ns ras hold time <63> t rsh (1.5 + w da + w f ) t ? 10 ns column address read time for ras <64> t ral (2 + w cp + w da + w f + w) t ? 10 ns cas pulse width <65> t cas (1 + w da + w f ) t ? 10 ns cas-ras precharge time <66> t crp (1 + w rp ) t ? 10 ns cas hold time <67> t csh (2 + w rh + w da + w f + w) t ? 10 ns cas precharge time <71> t cpn (2 + w rp + w rh + w) t ? 5 ns delay time from ras to column address <76> t rad (0.5 + w rh ) t ? 10 ns ras-cas delay time <77> t rcd (1 + w rh + w) t ? 10 ns cas precharge time <81> t cp (0.5 + w cp + w) t ? 5 ns high-speed page mode cycle time <82> t pc (2 + w cp + w da + w f + w) t ? 10 ns ras hold time for cas precharge <83> t rhcp (2.5 + w cp + w da + w) t ? 10 ns we hold time (from cas ) <85> t wch (1 + w da ) t ? 10 ns we read time (from ras ) <88> t rwl w cp = 0 (1.5 + w da + w) t ? 10 ns we read time (from cas ) <89> t cwl w cp = 0 (1 + w da + w) t ? 10 ns we pulse width <92> t wp w cp = 0 (1 + w da + w) t ? 10 ns ras pulse width <94> t rasp (2.5 + w rh + w da + w f + w) t ? 10 ns remarks 1. t = t cyk 2. w: number of waits due to wait 3. w rh : number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. w da : number of waits due to the dacxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 5. w rp : number of waits due to the rpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 6. w cp : number of waits due to the cpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 7. w f : number of waits that are inserted for a source-side access during a dma flyby transfer 8. i: number of idle states that are inserted when a write cycle follows a read cycle 9. n = 0 to 7
data sheet u14168ej3v0ds 64 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (h) dma flyby transfer timing (external i/o dram (edo, high-speed page) transfer) (2/3) parameter symbol conditions min. max. unit off-page <101> t wcs1 w cp = 0 (1 + w rh + w rp + w) t ? 10 ns we setup time (to cas ) on-page <102> t wcs2 w cp 1w cp t ? 10 ns delay time from dmaakm to cas <105> t ddacs (1.5 + w rh + w) t ? 10 ns delay time from iord to cas <106> t drdcs (1 + w rh + w) t ? 10 ns delay time from we to iord <107> t dwerd w f = 0 0 ns w f = 1 t ? 10 ns remarks 1. t = t cyk 2. w: number of waits due to wait 3. w rh : number of waits due to the rhcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. w rp : number of waits due to the rpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 5. w cp : number of waits due to the cpcxx bit of the drcn register (n = 0 to 3, xx = 00 to 03, 10 to 13) 6. w f : number of waits that are inserted for a source-side access during a dma flyby transfer 7. m = 0 to 3
data sheet u14168ej3v0ds 65 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (h) dma flyby transfer timing (external i/o dram (edo, high-speed page) transfer) (3/3) remarks 1. this is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). number of waits due to the rpcxx bit of the drcn register (trpw): 1 number of waits due to the rhcxx bit of the drcn register (trhw): 1 number of waits due to the dacxx bit of the drcn register (tdaw): 1 number of waits due to the cpcxx bit of the drcn register (tcpw): 1 number of waits that are inserted for a source-side access during a dma flyby transfer: 0 2. the broken lines indicate high impedance. 3. n = 0 to 7, m = 0 to 3 trpw t1 trhw tw t2 tdaw t3 tcpw tw to2 tdaw to1 <56> <57> <58> <76> <61> <60> <94> <64> <77> <65> <63> <81> <67> <66> <71> <82> <101> <105> <83> <85> <89> <106> <34> <107> <33> <24> <25> <24> <25> <24> data data <59> <88> <102> <92> <35> <32> <25> clkout (output) a0 to a23 (output) rasn (output) ucas (output) lcas (output) rd (output) oe (output) dmaakm (output) we (output) iowr (output) iord (output) d0 to d15 (i/o) wait (input) bcyst (output) row address column address column address
data sheet u14168ej3v0ds 66 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (i) cbr refresh timing parameter symbol conditions min. max. unit ras precharge time <61> t rp (1.5 + w rrw ) t ? 5 ns ras pulse width <62> t ras (1.5 + w rcw note ) t ? 10 ns cas hold time <108> t chr (1.5 + w rcw note ) t ? 10 ns refrq pulse width <109> t wrfl (3 + w rrw + w rcw note ) t ? 10 ns ras precharge cas hold time <110> t rpc (0.5 + w rrw ) t ? 10 ns refrq active delay time (from clkout ) <111> t dkrf 210ns refrq inactive delay time (from clkout ) <112> t hkrf 210ns cas setup time <113> t csr t ? 10 ns note at least one clock cycle is inserted by default for w rcw regardless of the settings of bits rcw0 to rcw2 of the rwc register. remarks 1. t = t cyk 2. w rrw : number of waits due to the rrw0 and rrw1 bits of the rwc register 3. w rcw : number of waits due to the rcw0 to rcw2 bits of the rwc register note this trcw is always inserted regardless of the settings of bits rcw0 to rcw2 of the rwc register. remarks 1. this is the timing for the following case. number of waits due to the rrw0 and rrw1 bits of the rwc register (trrw): 1 number of waits due to the rcw0 to rcw2 bits of the rwc register (trcw): 2 2. n = 0 to 7 ti refrq (output) t3 trcw trcw note t2 t1 trrw <109> <111> <112> rasn (output) <62> ucas (output) <108> <110> <61> <113> <110> lcas (output) clkout (output)
data sheet u14168ej3v0ds 67 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (j) cbr self-refresh timing parameter symbol conditions min. max. unit refrq active delay time (from clkout ) <111> t dkrf 210ns refrq inactive delay time (from clkout ) <112> t hkrf 210ns cas hold time <114> t chs ? 5ns ras precharge time <115> t rps (1 + 2w srw ) t ? 10 ns remarks 1. t = t cyk 2. w srw : number of waits due to the srw0 to srw2 bits of the rwc register remarks 1. this is the timing for the following case. number of waits due to the rrw0 and rrw1 bits of the rwc register (trrw): 1 number of waits due to the rcw0 to rcw2 bits of the rwc register (trcw): 1 number of waits due to the srw0 to srw2 bits of the rwc register (tsrw): 2 2. the broken lines indicate high impedance. 3. n = 0 to 7 <111> th th th trrw tsrw ti th trcw tsrw output signals other than above <115> <112> <114> clkout (output) refrq (output) rasn (output) ucas (output) lcas (output)
data sheet u14168ej3v0ds 68 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (7) dmac timing parameter symbol conditions min. max. unit dmarqn setup time (to clkout ) <116> t sdrk 10 ns <117> t hkdr1 2ns dmarqn hold time (from clkout ) <118> t hkdr2 until dmaakn ns dmaakn output delay time (from clkout ) <119> t dkda 210ns dmaakn output hold time (from clkout ) <120> t hkda 210ns tcn output delay time (from clkout ) <121> t dktc 210ns tcn output hold time (from clkout ) <122> t hktc 210ns remark n = 0 to 3 remark n = 0 to 3 <121> dmarqn (input) dmaakn (output) tcn (output) <122> <120> <119> <118> <117> <116> <116> clkout (output)
data sheet u14168ej3v0ds 69 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 [memo]
data sheet u14168ej3v0ds 70 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (8) bus hold timing (1/2) parameter symbol conditions min. max. unit hldrq setup time (to clkout ) <123> t shrk 10 ns hldrq hold time (from clkout ) <124> t hkhr 5ns delay time from clkout to hldak <125> t dkha 210ns hldrq high-level width <126> t whqh t + 17 ns hldak low-level width <127> t whal t ? 8 ns delay time from clkout to bus float <128> t dkcf 10 ns delay time from hldak to bus output <129> t dhac 0ns delay time from hldrq to hldak <130> t dhqha1 2.5t ns delay time from hldrq to hldak <131> t dhqha2 0.5t 1.5t ns remark t = t cyk
data sheet u14168ej3v0ds 71 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (8) bus hold timing (2/2) remarks 1. the broken lines indicate high impedance. 2. n = 0 to 7 t1 t2 t3 ti th th th ti t1 a0 to a23 (output) d0 to d15 (i/o) <123> <124> <124> <123> <123> <123> <126> <130> <125> <127> <125> <128> <129> <131> address undefined data clkout (output) hldrq (intput) hldak (output) csn/rasn (output) bcyst (output) rd (output) we (output) wait (input) ucas (output) lcas (output)
data sheet u14168ej3v0ds 72 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (9) interrupt timing parameter symbol conditions min. max. unit nmi high-level width <132> t wnih 500 ns nmi low-level width <133> t wnil 500 ns intpn high-level width <134> t with 4t + 10 ns intpn low-level width <135> t witl 4t + 10 ns remarks 1. n = 100 to 103, 110 to 113, 120 to 123, 130 to 133, 140 to 143, or 150 to 153 2. t = t cyk remark n = 100 to 103, 110 to 113, 120 to 123, 130 to 133, 140 to 143, or 150 to 153 (10) rpu timing parameter symbol conditions min. max. unit ti1n high-level width <136> t wtih 3t + 18 ns ti1n low-level width <137> t wtil 3t + 18 ns tclr1n high-level width <138> t wtch 3t + 18 ns tclr1n low-level width <139> t wtcl 3t + 18 ns remarks 1. n = 0 to 5 2. t = t cyk remark n = 0 to 5 nmi (input) <132> <133> intpn (input) <134> <135> ti1n (input) <136> <137> tclr1n (input) <138> <139>
data sheet u14168ej3v0ds 73 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (11) uart0, uart1 timing (clocked or master mode only) parameter symbol conditions min. max. unit sckn cycle <140> t cysk0 output 250 ns sckn high-level width <141> t wsk0h output 0.5t cysk0 ? 20 ns sckn low-level width <142> t wsk0l output 0.5t cysk0 ? 20 ns rxdn setup time (to sckn ) <143> t srxsk 30 ns rxdn hold time (from sckn ) <144> t hskrx 0ns txdn output delay time (from sckn ) <145> t dsktx 20 ns txdn output hold time (from sckn ) <146> t hsktx 0.5t cysk0 ? 5 ns remark n = 0, 1 remarks 1. the broken lines indicate high impedance. 2. n = 0, 1 sckn (i/o) <142> <140> <141> rxdn (input) <143> <144> input data txdn (output) <145> output data <146>
data sheet u14168ej3v0ds 74 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 (12) csi0 to csi3 timing (a) master mode parameter symbol conditions min. max. unit sckn cycle <147> t cysk1 output 100 ns sckn high-level width <148> t wsk1h output 0.5t cysk1 ? 20 ns sckn low-level width <149> t wsk1l output 0.5t cysk1 ? 20 ns sin setup time (to sckn ) <150> t ssisk 30 ns sin hold time (from sckn ) <151> t hsksi 0ns son output delay time (from sckn ) <152> t dskso 20 ns son output hold time (from sckn ) <153> t hskso 0.5t cysk1 ? 5 ns remark n = 0 to 3 (b) slave mode parameter symbol conditions min. max. unit sckn cycle <147> t cysk1 input 100 ns sckn high-level width <148> t wsk1h input 30 ns sckn low-level width <149> t wsk1l input 30 ns sin setup time (to sckn ) <150> t ssisk 10 ns sin hold time (from sckn ) <151> t hsksi 10 ns son output delay time (from sckn ) <152> t dskso 30 ns son output hold time (from sckn ) <153> t hskso t wsk1h ns remark n = 0 to 3 remarks 1. the broken lines indicate high impedance. 2. n = 0 to 3 sckn (i/o) <149> <147> <148> sln (input) <150> <151> input data son (output) <152> output data <153>
data sheet u14168ej3v0ds 75 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 a/d converter characteristics (t a = ?40 to +70 c ... pd703100a-40, t a = ?40 to +85 c ... pd703100a-33, pd703101a-33, pd703102a-33, v dd = hv dd = cv dd = 3.0 to 3.6 v, v ss = 0 v, v dd ? 0.5 v av dd v dd , output pin load capacitance: c l = 50 pf) parameter symbol conditions min. typ. max. unit resolution ? 10 bit overall error ? 5lsb quantization error ? 1/2 lsb conversion time t conv 510 s sampling time t samp conversion clock note /6 ns zero-scale error ? 5lsb full-scale error ? 5lsb nonlinearity error ? 3lsb analog input voltage v ian ? 0.3 av ref + 0.3 v analog input resistance r an 1.0 m ? av ref input voltage av ref av ref = av dd 3.0 av dd v av ref input current ai ref 2.0 ma av dd current ai dd 5.0 ma note the conversion clock is the number of clocks set by the adm1 register.
data sheet u14168ej3v0ds 76 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 4. package drawings a b c d e f g h j k l m n p r t 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 157-pin plastic fbga (14x14) item millimeters d d1 13.4 14.0 + ? b
data sheet u14168ej3v0ds 77 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 108 73 136 109 144 72 37 144-pin plastic lqfp (fine pitch) (20x20) item millimeters note a 22.0 + ? + ?
data sheet u14168ej3v0ds 78 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 5. recommended soldering conditions this product should be soldered and mounted under the following recommended conditions. for details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact an nec sales representative. table 5-1. surface mounting type soldering conditions (1) pd703100af1-33-fa1: 157-pin plastic fbga (14 14) pd703101af1-33- -fa1: 157- pin plastic fbga (14 14) pd703102af1-33- -fa1: 157- pin plastic fbga (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 230 c, time: 30 seconds. max. (at 210 c or higher), count: two times or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) ir35-103-2 vps package peak temperature:215 c, time:25 to 40 seconds max. (at 200 c or higher), count: two times or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) vp15-103-2 partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. (2) pd703100agj-33-uen: 144-pin plastic lqfp (fine pitch) (20 20) pd703100agj-40- uen: 144-pin plastic lqfp (fine pitch) (20 20) pd703101agj-33- -uen: 144-pin plastic lqfp (fine pitch) (20 20) pd703102agj-33- -uen: 144-pin plastic lqfp (fine pitch) (20 20) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: two times or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) ir35-103-2 vps package peak temperature:215 c, time:25 to 40 seconds max. (at 200 c or higher), count: two times or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) vp15-103-2 partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period.
data sheet u14168ej3v0ds 79 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 [memo]
data sheet u14168ej3v0ds 80 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. related documents pd70f3102-33 data sheet (u13844e) pd703100-33, 703100-40, 703101-33, 703102-33 data sheet (u13995e) pd70f3102a-33 data sheet (u13845e) reference materials electrical characteristics for microcomputer (u15170j note ) note this document number is that of japanese version. the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. v850e/ms1 and v850 family are trademarks of nec corporation.
data sheet u14168ej3v0ds 81 pd703100a-33, 703100a-40, 703101a-33, 703102a-33 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? ? ? ? ? ?
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