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1997 microchip technology inc. preliminary ds30264a-page 1 devices included in this data sheet: pic17c752 pic17c756 microcontroller core features: only 58 single word instructions to learn all single cycle instructions (121 ns) except for program branches and table reads/writes which are two-cycle operating speed: - dc - 33 mhz clock input - dc - 121 ns instruction cycle hardware multiplier interrupt capability 16 level deep hardware stack direct, indirect, and relative addressing modes internal/external program memory execution capable of addressing 64k x 16 program memory space peripheral features: 50 i/o pins with individual direction control high current sink/source for direct led drive - ra2 and ra3 are open drain, high voltage (12v), high current (60 ma), i/o pins four capture input pins - captures are 16-bit, max resolution 121 ns three pwm outputs - pwm resolution is 1- to 10-bits tmr0: 16-bit timer/counter with 8-bit programmable prescaler tmr1: 8-bit timer/counter tmr2: 8-bit timer/counter tmr3: 16-bit timer/counter two universal synchronous asynchronous receiver transmitters (usart/sci) - independant baud rate generators 10-bit, 12 channel analog-to-digital converter synchronous serial port (ssp) with spi and i 2 c modes (including i 2 c master mode) device memory program (x16) data (x8) pic17c752 8k 454 pic17c756 16k 902 o o pin diagrams special microcontroller features: power-on reset (por), power-up timer (pwrt) and oscillator start-up timer (ost) watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation brown-out reset code-protection power saving sleep mode selectable oscillator options cmos technology: low-power, high-speed cmos eprom technology fully static design wide operating voltage range (2.5v to 6.0v) commercial and industrial temperature ranges low-power consumption - < 5 ma @ 5v, 4 mhz - 100 m a typical @ 4.5v, 32 khz - < 1 m a typical standby current @ 5v 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 rd2/ad10 rd3/ad11 rd4/ad12 rd5/ad13 rd6/ad14 rd7/ad15 rc0/ad0 v dd nc v ss rc1/ad1 rc2/ad2 rc3/ad3 rc4/ad4 rc5/ad5 rc6/ad6 rc7/ad7 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 pic17c75x ra0/int rb0/cap1 rb1/cap2 rb3/pwm2 rb4/tclk12 rb5/tclk3 rb2/pwm1 v ss nc osc2/clkout osc1/clkin v dd rb7/sdo ra3/sdi/sda ra2/ss /scl ra1/t0cki rd1/ad9 rd0/ad8 re0/ale re1/oe re2/wr re3/cap4 mclr /v pp test v ss v dd rf7/an11 rf6/an10 rf5/an9 rf4/an8 rf3/an7 rf2/an6 rf1/an5 rf0/an4 av dd av ss rg3/an0/v ref + rg2/an1/v ref - rg1/an2 rg0/an3 nc v ss v dd rg4/cap3 rg5/pwm3 rg7/tx2/ck2 rg6/rx2/dt2 ra4/rx1/dt1 ra5/tx1/ck1 nc rb6/sck lcc top view pic17c75x high-performance 8-bit cmos eprom microcontrollers
pic17c75x ds30264a-page 2 preliminary 1997 microchip technology inc. pin diagrams cont.? pic17c75x in 68-pin lcc 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 top view ra0/int rb0/cap1 rb1/cap2 rb3/pwm2 rb4/tclk12 rb5/tclk3 rb2/pwm1 v ss nc osc2/clkout osc1/clkin v dd rb7/sdo ra3/sdi/sda ra2/ss /scl ra1/t0cki rd1/ad9 rd0/ad8 re0/ale re1/oe re2/wr re3/cap4 mclr /v pp test v ss v dd rf7/an11 rf6/an10 rf5/an9 rf4/an8 rf3/an7 rf2/an6 rd2/ad10 rd3/ad11 rd4/ad12 rd5/ad13 rd6/ad14 rd7/ad15 rc0/ad0 v dd nc v ss rc1/ad1 rc2/ad2 rc3/ad3 rc4/ad4 rc5/ad5 rc6/ad6 rc7/ad7 rf1/an5 rf0/an4 av dd av ss rg3/an0/v ref + rg2/an1/v ref - rg1/an2 rg0/an3 nc v ss v dd rg4/cap3 rg5/pwm3 rg7/tx2/ck2 rg6/rx2/dt2 ra4/rx1/dt1 ra5/tx1/ck1 nc rb6/sck pic17c75x
1997 microchip technology inc. preliminary ds30264a-page 3 pic17c75x pin diagrams cont.? pic17c75x in 64-pin tqfp pin diagrams cont.? pic17c75x in 64-pin y-shrink dip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 top view applicable to 14 x 14 mm tqfp rd2/ad10 rd3/ad11 rd4/ad12 rd5/ad13 rd6/ad14 rd7/ad15 rc0/ad0 v dd v ss rc1/ad1 rc2/ad2 rc3/ad3 rc4/ad4 rc5/ad5 rc6/ad6 rc7/ad7 rd1/ad9 rd0/ad8 re0/ale re1/oe re2/wr re3/cap4 mclr /v pp test v ss v dd rf7/an11 rf6/an10 rf5/an9 rf4/an8 rf3/an7 rf2/an6 ra0/int rb0/cap1 rb1/cap2 rb3/pwm2 rb4/tclk12 rb5/tclk3 rb2/pwm1 v ss osc2/clkout osc1/clkin v dd rb7/sdo ra3/sdi/sda ra2/ss /scl ra1/t0cki rf1/an5 rf0/an4 av dd av ss rg3/an0/v ref + rg2/an1/v ref - rg1/an2 rg0/an3 v ss v dd rg4/cap3 rg5/pwm3 rg7/tx2/ck2 rg6/rx2/dt2 ra4/rx1/dt1 ra5/tx1/ck1 rb6/sck pic17c75x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 pic17c75x 44 43 42 41 40 39 21 22 23 24 25 26 27 28 29 30 31 32 38 37 36 35 34 33 v dd rc0/ad0 rd7/ad15 rd6/ad14 rd5/ad13 rd4/ad12 rd3/ad11 rd2/ad10 rd1/ad9 rd0/ad8 re0/ale re1/oe re2/wr re3/cap4 mclr /v pp test v dd rf7/an11 rf6/an10 rf5/an9 rf4/an8 rf3/an7 rf2/an6 rf1/an5 rf0/an4 av ss av dd rg3/an0/v ref + rg2/an1/v ref - rg1/an2 v ss v ss rc1/ad1 rc2/ad2 rc3/ad3 rc4/ad4 rc5/ad5 rc6/ad6 rc7/ad7 ra0/int rb0/cap1 rb1/cap2 rb3/pwm2 rb4/tclk12 rb5/tclk3 rb2/pwm1 v ss osc2/clkout osc1/clkin v dd rb7/sdo rb6/sck ra2/ss /scl ra1/t0cki ra4/rx1/dt1 ra5/tx1/ck1 rg6/rx2/dt2 rg7/tx2/ck2 rg5/pwm3 rg4/cap3 v dd v ss rg0/an3 ra3/sdi/sda
pic17c75x ds30264a-page 4 preliminary 1997 microchip technology inc. table of contents 1.0 overview ........................................................................................................................................................................................ 5 2.0 device varieties ............................................................................................................................................................................. 7 3.0 architectural overview ................................................................................................................................................................... 9 4.0 on-chip oscillator circuit ............................................................................................................................................................. 15 5.0 reset............................................................................................................................................................................................ 21 6.0 interrupts ...................................................................................................................................................................................... 29 7.0 memory organization................................................................................................................................................................... 39 8.0 table reads and table writes .................................................................................................................................................... 55 9.0 hardware multiplier ...................................................................................................................................................................... 61 10.0 i/o ports ....................................................................................................................................................................................... 65 11.0 overview of timer resources ....................................................................................................................................................... 85 12.0 timer0 .......................................................................................................................................................................................... 87 13.0 timer1, timer2, timer3, pwms and captures ............................................................................................................................ 91 14.0 universal synchronous asynchronous receiver transmitter (usart) modules...................................................................... 107 15.0 synchronous serial port (ssp) module ..................................................................................................................................... 123 16.0 analog-to-digital converter (a/d) module ................................................................................................................................. 167 17.0 special features of the cpu ..................................................................................................................................................... 177 18.0 instruction set summary............................................................................................................................................................ 183 19.0 development support ................................................................................................................................................................ 219 20.0 pic17c752/756 electrical characteristics ................................................................................................................................. 223 21.0 pic17c752/756 dc and ac characteristics ............................................................................................................................. 249 22.0 packaging information ............................................................................................................................................................... 261 appendix a: modifications .............................................................................................................................................................. 265 appendix b: compatibility .............................................................................................................................................................. 265 appendix c: what? new................................................................................................................................................................ 266 appendix d: what? changed ........................................................................................................................................................ 266 appendix e: i 2 c ? overview........................................................................................................................................................... 267 appendix f: status and control registers ..................................................................................................................................... 273 appendix g: pic16/17 microcontrollers ......................................................................................................................................... 293 pin compatibility ................................................................................................................................................................................ 302 index .................................................................................................................................................................................................. 303 on-line support................................................................................................................................................................................. 317 reader response .............................................................................................................................................................................. 318 pic17c75x product identification system......................................................................................................................................... 319 to our valued customers we constantly strive to improve the quality of all our products and documentation. we have spent an excep- tional amount of time to ensure that these documents are correct. however, we realize that we may have missed a few things. if you ?d any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. we appreciate your assistance in making this a bet- ter document.
1997 microchip technology inc. preliminary ds30264a-page 5 pic17c75x 1.0 overview this data sheet covers the pic17c75x group of the pic17cxxx family of microcontrollers. the following devices are discussed in this data sheet: pic17c752 pic17c756 the pic17c75x devices are 68-pin, eprom-based members of the versatile pic17cxxx family of low-cost, high-performance, cmos, fully-static, 8-bit microcontrollers. all pic16/17 microcontrollers employ an advanced risc architecture. the pic17cxxx has enhanced core features, 16-level deep stack, and multiple internal and external interrupt sources. the separate instruc- tion and data buses of the harvard architecture allow a 16-bit wide instruction word with a separate 8-bit wide data path. the two stage instruction pipeline allows all instructions to execute in a single cycle, except for pro- gram branches (which require two cycles). a total of 58 instructions (reduced instruction set) are available. additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. for mathematical intensive applications all devices have a single cycle 8 x 8 hardware multi- plier. pic17cxxx microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. pic17c75x devices have up to 902 bytes of ram and 50 i/o pins. in addition, the pic17c75x adds several peripheral features useful in many high performance applications including: four timer/counters four capture inputs three pwm outputs two independant universal synchronous asyn- chronous receiver transmitters (usarts) an a/d converter (12 channel, 10-bit resolution) a synchronous serial port (spi and i 2 c w/ master mode) these special features reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. there are four oscillator options, of which the single pin rc oscillator provides a low-cost solution, the lf oscil- lator is for low frequency crystals and minimizes power consumption, xt is a standard crystal, and the ec is for external clock input. the sleep (power-down) mode offers additional power saving. wake-up from sleep can occur through several external and internal interrupts and device resets. a highly reliable watchdog timer with its own on-chip rc oscillator provides protection against software mal- function. there are four con?uration options for the device operational mode: microprocessor microcontroller extended microcontroller protected microcontroller the microprocessor and extended microcontroller modes allow up to 64k-words of external program memory. brown-out reset circuitry has also been added to the device. this allows a device reset to occur if the device v dd falls below the brown-out voltage trip point (bv dd ). the chip will remain in brown-out reset until v dd rises above bv dd . table 1-1 lists the features of the pic17cxxx devices. a uv-erasable cerquad-packaged version (compat- ible with plcc) is ideal for code development while the cost-effective one-time programmable (otp) version is suitable for production in any volume. the pic17c75x ?s perfectly in applications that require extremely fast execution of complex software programs. these include applications ranging from precise motor control and industrial process control to automotive, instrumentation, and telecom applications. the eprom technology makes customization of appli- cation programs (with unique security codes, combina- tions, model numbers, parameter storage, etc.) fast and convenient. small footprint package options (including die sales) make the pic17c75x ideal for applications with space limitations that require high performance. an in-circuit serial programming (isp) feature allows: flexibility of programming the software code as one of the last steps of the manufacturing process high speed execution, powerful peripheral features, ?xible i/o, and low power consumption all at low cost make the pic17c75x ideal for a wide range of embed- ded control applications. 1.1 family and upward compatibility the pic17cxxx family of microcontrollers have archi- tectural enhancements over the pic16c5x and pic16cxx families. these enhancements allow the device to be more ef?ient in software and hardware requirements. refer to appendix a for a detailed list of enhancements and modi?ations. code written for pic16c5x or pic16cxx can be easily ported to pic17cxxx devices (appendix b). 1.2 development support the pic17cxxx family is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a universal programmer, a ? compiler, and fuzzy logic support tools. for additional information see section 19.0.
pic17c75x ds30264a-page 6 preliminary 1997 microchip technology inc. table 1-1: pic17cxxx family of devices features pic17cr42 pic17c42a pic17c43 pic17cr43 pic17c44 pic17c752 pic17c756 maximum frequency of operation 33 mhz 33 mhz 33 mhz 33 mhz 33 mhz 33 mhz 33 mhz operating voltage range 2.5 - 6.0v 2.5 - 6.0v 2.5 - 6.0v 2.5 - 6.0v 2.5 - 6.0v 3.0 - 6.0v 3.0 - 6.0v program memory ( x16) (eprom) - 16 k 4k - 8k 8k 16k (rom) 2k - - 4k --- data memory (bytes) 232 232 454 454 454 454 902 hardware multiplier (8 x 8) ye s ye s ye s ye s ye s ye s ye s timer0 (16-bit + 8-bit postscaler) ye s ye s ye s ye s ye s ye s ye s timer1 (8-bit) ye s ye s ye s ye s ye s ye s ye s timer2 (8-bit) ye s ye s ye s ye s ye s ye s ye s timer3 (16-bit) ye s ye s ye s ye s ye s ye s ye s capture inputs (16-bit) 2 2 2 2 244 pwm outputs (up to 10-bit) 2 2 2 2 233 usart/sci 1 1 1 1 122 a/d channels (10-bit) - - - - -1212 ssp (spi/i 2 c w/master mode) - - - - - yes yes power-on reset ye s ye s ye s ye s ye s ye s ye s watchdog timer ye s ye s ye s ye s ye s ye s ye s external interrupts ye s ye s ye s ye s ye s ye s ye s interrupt sources 11 11 11 11 11 18 18 code protect ye s ye s yes yes yes yes yes brown-out reset - - - - - yes yes in-circuit serial programming - - - - - yes yes i/o pins 33 33 33 33 33 50 50 i/o high current capability source 25 ma 25 ma 25 ma 25 ma 25 ma 25 ma 25 ma sink 25 ma (1) 25 ma (1) 25 ma (1) 25 ma (1) 25 ma (1) 25 ma (1) 25 ma (1) package types 40-pin dip 44-pin plcc 44-pin mqfp 44-pin tqfp 40-pin dip 44-pin plcc 44-pin mqfp 44-pin tqfp 40-pin dip 44-pin plcc 44-pin mqfp 44-pin tqfp 40-pin dip 44-pin plcc 44-pin mqfp 44-pin tqfp 40-pin dip 44-pin plcc 44-pin mqfp 44-pin tqfp 64-pin dip 68-pin lcc 68-pin tqfp 64-pin dip 68-pin lcc 68-pin tqfp note 1: pins ra2 and ra3 can sink up to 60 ma.
1997 microchip technology inc. preliminary ds30264a-page 7 pic17c75x 2.0 device varieties each device has a variety of frequency ranges and packaging options. depending on application and pro- duction requirements, the proper device option can be selected using the information in the pic17c75x prod- uct selection system section at the end of this data sheet. when placing orders, please use the ?ic17c75x product identi?ation system at the back of this data sheet to specify the correct part number. when discussing the functionality of the device, mem- ory technology and voltage range does not matter. there are three memory type options. these are spec- i?d in the middle characters of the part number. 1. c , as in pic17 c 756. these devices have eprom type memory. 2. cr , as in pic17 cr 756. these devices have rom type memory. 3. f , as in pic17 f 756. these devices have flash type memory. all these devices operate over the standard voltage range. devices are also offered which operate over an extended voltage range (and reduced frequency range). table 2-1 shows all possible memory types and voltage range designators for a particular device. these designators are in bold typeface. table 2-1: device memory varieties memory type voltage range standard extended eprom pic17 c xxx pic17 lc xxx rom pic17 cr xxx pic17 lcr xxx flash pic17 f xxx pic17 lf xxx note: not all memory technologies are available for a particular device. 2.1 uv erasable devices the uv erasable version, offered in cerquad pack- age, is optimal for prototype development and pilot pro- grams. the uv erasable version can be erased and repro- grammed to any of the con?uration modes. microchip's programming of the pic17c75x. third party programmers also are available; refer to the third party guide for a list of sources. 2.2 one-t ime-programmable (otp) devices the availability of otp devices is especially useful for customers expecting frequent code changes and updates. the otp devices, packaged in plastic packages, per- mit the user to program them once. in addition to the program memory, the con?uration bits must be pro- grammed. 2.3 quick-t urnaround-production (qtp) devices microchip offers a qtp programming service for fac- tory production orders. this service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabi- lized. the devices are identical to the otp devices but with all eprom locations and con?uration options already programmed by the factory. certain code and prototype veri?ation procedures apply before produc- tion shipments are available. please contact your local microchip technology sales of?e for more details. 2.4 serialized quick-t urnaround production (sqtp sm ) devices microchip offers a unique programming service where a few user-de?ed locations in each device are pro- grammed with different serial numbers. the serial num- bers may be random, pseudo-random or sequential. serial programming allows each device to have a unique number which can serve as an entry-code, password or id number.
pic17c75x ds30264a-page 8 preliminary 1997 microchip technology inc. 2.5 read only memory (rom) devices microchip offers masked rom versions of several of the highest volume parts, thus giving customers a low cost option for high volume, mature products. rom devices do not allow serialization information in the program memory space. for information on submitting rom code, please con- tact your regional sales of?e. 2.6 flash memory devices these devices are electrically erasable and, therefore, can be offered in the low cost plastic package. being electrically erasable, these devices can be erased and reprogrammed in-circuit. these devices are the same for prototype development, pilot programs, as well as production. note: presently, no rom versions of the pic17c75x devices are available. note: presently, no flash versions of the pic17c75x devices are available.
1997 microchip technology inc. preliminary ds30264a-page 9 pic17c75x 3.0 architectural overview the high performance of the pic17cxxx can be attrib- uted to a number of architectural features commonly found in risc microprocessors. to begin with, the pic17cxxx uses a modi?d harvard architecture. this architecture has the program and data accessed from separate memories. so, the device has a program memory bus and a data memory bus. this improves bandwidth over traditional von neumann architecture, where program and data are fetched from the same memory (accesses over the same bus). separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. pic17cxxx opcodes are 16-bits wide, enabling single word instructions. the full 16-bit wide program memory bus fetches a 16-bit instruction in a single cycle. a two-stage pipeline overlaps fetch and execution of instructions. consequently, all instructions execute in a single cycle (121 ns @ 33 mhz), except for program branches and two special instructions that transfer data between program and data memory. the pic17cxxx can address up to 64k x 16 of pro- gram memory space. the pic17c752 integrates 8k x 16 of eprom pro- gram memory on-chip. the pic17c756 integrates 16k x 16 eprom program memory. program execution can be internal only (microcontrol- ler or protected microcontroller mode), external only (microprocessor mode) or both (extended microcon- troller mode). extended microcontroller mode does not allow code protection. the pic17cxxx can directly or indirectly address its register ?es or data memory. all special function regis- ters, including the program counter (pc) and working register (wreg), are mapped in the data memory. the pic17cxxx has an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. this symmetrical nature and lack of ?pecial optimal sit- uations make programming with the pic17cxxx sim- ple yet ef?ient. in addition, the learning curve is reduced signi?antly. one of the pic17cxxx family architectural enhance- ments from the pic16cxx family allows two ?e regis- ters to be used in some two operand instructions. this allows data to be moved directly between two registers without going through the wreg register. thus increasing performance and decreasing program memory usage. the pic17cxxx devices contain an 8-bit alu and working register. the alu is a general purpose arith- metic unit. it performs arithmetic and boolean functions between data in the working register and any register ?e. the alu is 8-bits wide and capable of addition, sub- traction, shift, and logical operations. unless otherwise mentioned, arithmetic operations are two's comple- ment in nature. the wreg register is an 8-bit working register used for alu operations. all pic17c75x devices have an 8 x 8 hardware multi- plier. this multiplier generates a 16-bit result in a single cycle. depending on the instruction executed, the alu may affect the values of the carry (c), digit carry (dc), and zero (z) bits in the alusta register. the c and dc bits operate as a borro w and digit borro w out bit, respec- tively, in subtraction. see the sublw and subwf instructions for examples. although the alu does not perform signed arithmetic, the over?w bit (ov) can be used to implement signed math. signed arithmetic is comprised of a magnitude and a sign bit. the over?w bit indicates if the magni- tude over?ws and causes the sign bit to change state. that is if the result of the signed operation is greater then 128 (7fh) or less then -127 (ffh). signed math can have greater than 7-bit values (magnitude), if more than one byte is used. the use of the over?w bit only operates on bit6 (msb of magnitude) and bit7 (sign bit) of the value in the alu. that is, the over?w bit is not useful if trying to implement signed math where the magnitude, for example, is 11-bits. if the signed math values are greater than 7-bits (15-, 24- or 31-bit), the algorithm must ensure that the low order bytes ignore the over?w status bit. care should be taken when adding and subtracting signed numbers to ensure that the correct operation is executed. example 3-1 shows an item that must be taken into account when doing signed arithmetic on an alu which operates as an unsigned machine. example 3-1: signed math signed math requires the result to be feh (-126). this would be accomplished by subtracting one as opposed to adding one. a simpli?d block diagram is shown in figure 3-1. the descriptions of the device pins are listed in table 3-1. hex value signed value math unsigned value math ffh + 01h = ? -127 + 1 = -126 (feh) 255 + 1 = 0 (00h); carry bit = 1
pic17c75x ds30264a-page 10 preliminary 1997 microchip technology inc. figure 3-1: pic17c75x block diagram rb0/cap1 rb1/cap2 rb2/pwm1 rb3/pwm2 rb4/tclk12 rb5/tclk3 rb6/sck rb7/sdo ra0/int ra1/t0cki ra2/ss /scl ra3/sdi/sda ra4/rx1/dt1 ra5/tx1/ck1 porta rc0/ad0 rc1/ad1 rc2/ad2 rc3/ad3 rc4/ad4 rc5/ad5 rc6/ad6 rc7/ad7 rd0/ad8 rd1/ad9 rd2/ad10 rd3/ad11 rd4/ad12 rd5/ad13 rd6/ad14 rd7/ad15 re0/ale re1/oe re2/wr re3/cap4 rf0/an4 rf1/an5 rf2/an6 rf3/an7 rf4/an8 rf5/an9 rf6/an10 rf7/an11 rg0/an3 rg1/an2 rg2/an1/v ref - rg3/an0/v ref + rg4/cap3 rg5/pwm3 rg6/rx2/dt2 rg7/tx2/ck2 timer0 clock generator power-on reset watchdog timer test mode select v dd , v ss osc1, mclr , v ss test q1, q2, chip_reset & other control system bus interface decode data latch address program memory (eprom) table pointer<16> stack 16 x 16 ta bl e rom latch <16> instruction decode control outputs ir latch <16> f1 f9 16k x 16 pch pclath<8> literal ram data latch bsr data ram 902 x 8 latch pcl read/write decode for mapped in data space wreg<8> bitop alu shifter 8 x 8 mult prodh prodl registers latch <16> address buffer usart1 timer1 timer3 timer2 pwm1 pwm2 pwm3 capture1 capture3 capture2 interrupt module 10-bit a/d portb portc portd porte portf portg ad<15:0> signals q3, q4 osc2 data bus<8> ir<7> 16 16 16 16 8 8 8 8 ir<7> 12 16 ir<16> ssp portc, portd ale, wr , oe , porte ir <7:0> bsr <7:4> usart2 capture4 brown-out reset 17c756 17c752 8k x 16 17c756 17c752 454 x 8
1997 microchip technology inc. preliminary ds30264a-page 11 pic17c75x table 3-1: pinout descriptions name dip no. plcc no. tqfp no. i/o/p type buffer type description osc1/clkin 47 50 39 i st oscillator input in crystal/resonator or rc oscillator mode. external clock input in external clock mode. osc2/clkout 48 51 40 o oscillator output. connects to crystal or resonator in crystal oscillator mode. in rc oscillator or external clock modes osc2 pin outputs clkout which has one fourth the fre- quency (f osc /4) of osc1 and denotes the instruction cycle rate. mclr /v pp 15 16 7 i/p st master clear (reset) input or programming voltage (v pp ) input. this is the active low reset input to the chip. porta is a bi-directional i/o port except for ra0 and ra1 which are input only. ra0/int 56 60 48 i st ra0 can also be selected as an external interrupt input. interrupt can be con?ured to be on positive or negative edge. ra1/t0cki 41 44 33 i st ra1 can also be selected as an external interrupt input, and the interrupt can be con?ured to be on pos- itive or negative edge. ra1 can also be selected to be the clock input to the timer0 timer/counter. ra2/ss /scl 42 45 34 i/o st ra2 can also be used as the slave select input for the spi or the clock input for the i 2 c bus. high voltage, high current, open drain input/output port pin. ra3/sdi/sda 43 46 35 i/o st ra3 can also be used as the data input for the spi or the data for the i 2 c bus. high voltage, high current, open drain input/output port pin. ra4/rx1/dt1 40 43 32 i/o ? st ra4 can also be selected as the usart1 (sci) asyn- chronous receive or usart1 (sci) synchronous data. ra5/tx1/ck1 39 42 31 i/o ? st ra5 can also be selected as the usart1 (sci) asyn- chronous transmit or usart1 (sci) synchronous clock. portb is a bi-directional i/o port with software con?- urable weak pull-ups. rb0/cap1 55 59 47 i/o st rb0 can also be the capture1 input pin. rb1/cap2 54 58 46 i/o st rb1 can also be the capture2 input pin. rb2/pwm1 50 54 42 i/o st rb2 can also be the pwm1 output pin. rb3/pwm2 53 57 45 i/o st rb3 can also be the pwm2 output pin. rb4/tclk12 52 56 44 i/o st rb4 can also be the external clock input to timer1 and timer2. rb5/tclk3 51 55 43 i/o st rb5 can also be the external clock input to timer3. rb6/sck 44 47 36 i/o st rb6 can also be used as the master/slave clock for the spi. rb7/sdo 45 48 37 i/o st rb7 can also be used as the data output for the spi. legend: i = input only; o = output only; i/o = input/output; p = power; ?= not used; ttl = ttl input; st = schmitt trigger input. ? the output is only available by the peripheral operation.
pic17c75x ds30264a-page 12 preliminary 1997 microchip technology inc. portc is a bi-directional i/o port. rc0/ad0 2 3 58 i/o ttl this is also the least signi?ant byte (lsb) of the 16-bit wide system bus in microprocessor mode or extended microcontroller mode. in multiplexed system bus con- ?uration, these pins are address output as well as data input or output. rc1/ad1 63 67 55 i/o ttl rc2/ad2 62 66 54 i/o ttl rc3/ad3 61 65 53 i/o ttl rc4/ad4 60 64 52 i/o ttl rc5/ad5 58 63 51 i/o ttl rc6/ad6 58 62 50 i/o ttl rc7/ad7 57 61 49 i/o ttl portd is a bi-directional i/o port. rd0/ad8 10 11 2 i/o ttl this is also the most signi?ant byte (msb) of the 16-bit system bus in microprocessor mode or extended microprocessor mode or extended microcontroller mode. in multiplexed system bus con?uration these pins are address output as well as data input or output. rd1/ad9 9 10 1 i/o ttl rd2/ad10 8 9 64 i/o ttl rd3/ad11 7 8 63 i/o ttl rd4/ad12 6 7 62 i/o ttl rd5/ad13 5 6 61 i/o ttl rd6/ad14 4 5 60 i/o ttl rd7/ad15 3 4 59 i/o ttl porte is a bi-directional i/o port. re0/ale 11 12 3 i/o ttl in microprocessor mode or extended microcontroller mode, re0 is the address latch enable (ale) output. address should be latched on the falling edge of ale output. re1/oe 12 13 4 i/o ttl in microprocessor or extended microcontroller mode, re1 is the output enable (oe ) control output (active low). re2/wr 13 14 5 i/o ttl in microprocessor or extended microcontroller mode, re2 is the write enable (wr ) control output (active low). re3/cap4 14 15 6 i/o st re3 can also be the capture4 input pin. portf is a bi-directional i/o port. rf0/an4 26 28 18 i/o st rf0 can also be analog input 4. rf1/an5 25 27 17 i/o st rf1 can also be analog input 5. rf2/an6 24 26 16 i/o st rf2 can also be analog input 6. rf3/an7 23 25 15 i/o st rf3 can also be analog input 7. rf4/an8 22 24 14 i/o st rf4 can also be analog input 8. rf5/an9 21 23 13 i/o st rf5 can also be analog input 9. rf6/an10 20 22 12 i/o st rf6 can also be analog input 10. rf7/an11 19 21 11 i/o st rf7 can slso be analog input 11. table 3-1: pinout descriptions name dip no. plcc no. tqfp no. i/o/p type buffer type description legend: i = input only; o = output only; i/o = input/output; p = power; ?= not used; ttl = ttl input; st = schmitt trigger input. ? the output is only available by the peripheral operation.
1997 microchip technology inc. preliminary ds30264a-page 13 pic17c75x portg is a bi-directional i/o port. rg0/an3 32 34 24 i/o st rg0 can also be analog input 3. rg1/an2 31 33 23 i/o st rg1 can also be analog input 2. rg2/an1/v ref - 30 32 22 i/o st rg2 can also be analog input 1, or the ground reference voltage rg3/an0/v ref + 29 31 21 i/o st rg3 can also be analog input 0, or the positive reference voltage rg4/cap3 35 38 27 i/o st rg4 can also be the capture3 input pin. rg5/pwm3 36 39 28 i/o st rg5 can also be the pwm3 output pin. rg6/rx2/dt2 38 41 30 i/o st rg6 can also be selected as the usart2 (sci) asyn- chronous receive or usart2 (sci) synchronous data. rg7/tx2/ck2 37 40 29 i/o st rg7 can also be selected as the usart2 (sci) asyn- chronous transmit or usart2 (sci) synchronous clock. test 16 17 8 i st test mode selection control input. always tie to v ss for nor- mal operation. v ss 17, 33, 49, 64 19, 36,53, 68 9, 25, 41, 56 p ground reference for logic and i/o pins. v dd 1, 18, 34, 46 2, 20, 37, 49, 10, 26, 38, 57 p positive supply for logic and i/o pins. av ss 28 30 20 p ground reference for a/d converter. this pin must be at the same potential as v ss . av dd 27 29 19 p positive supply for a/d converter. this pin must be at the same potential as v dd . nc - 1, 18, 35, 52 - no connect. leave these pins unconnected. table 3-1: pinout descriptions name dip no. plcc no. tqfp no. i/o/p type buffer type description legend: i = input only; o = output only; i/o = input/output; p = power; ?= not used; ttl = ttl input; st = schmitt trigger input. ? the output is only available by the peripheral operation.
pic17c75x ds30264a-page 14 preliminary 1997 microchip technology inc. notes:
1997 microchip technology inc. preliminary ds30264a-page 15 pic17c75x 4.0 on-chip oscillator circuit the internal oscillator circuit is used to generate the device clock. four device clock periods generate an internal instruction clock (t cy ). there are four modes that the oscillator can operate in. these are selected by the device con?uration bits during device program- ming. these modes are: lf low frequency (f osc <= 2 mhz) xt standard crystal/resonator frequency (2 mhz <= f osc <= 33 mhz) ec external clock input (default oscillator con?uration) rc external resistor/capacitor (f osc <= 4 mhz) there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power-up timer (pwrt), which provides a ?ed delay of 96 ms (nomi- nal) on power-up only, designed to keep the part in reset while the power supply stabilizes. with these two timers on-chip, most applications need no external reset circuitry. sleep mode is designed to offer a very low current power-down mode. the user can wake from sleep through external reset, watchdog timer reset or through an interrupt. several oscillator options are made available to allow the part to ? the application. the rc oscillator option saves system cost while the lf crystal option saves power. con?uration bits are used to select various options. 4.1 oscillator con gurations 4.1.1 oscillator types the pic17cxxx can be operated in four different oscil- lator modes. the user can program two con?uration bits (fosc1:fosc0) to select one of these four modes: lf low power crystal xt crystal/resonator ec external clock input rc resistor/capacitor the main difference between the lf and xt modes is the gain of the internal inverter of the oscillator circuit which allows the different frequency ranges. for more details on the device con?uration bits, see section 17.0. 4.1.2 crystal oscillator / ceramic resonators in xt or lf modes, a crystal or ceramic resonator is connected to the osc1/clkin and osc2/clkout pins to establish oscillation (figure 4-2). the pic17cxxx oscillator design requires the use of a par- allel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers speci?a- tions. for frequencies above 20 mhz, it is common for the crystal to be an overtone mode crystal. use of overtone mode crystals require a tank circuit to attenuate the gain at the fundamental frequency. figure 4-3 shows an example circuit. 4.1.2.1 oscillator / resonator start-up as the device voltage increases from vss, the oscillator will start its oscillations. the time required for the oscil- lator to start oscillating depends on many factors. these include: crystal / resonator frequency capacitor values used (c1 and c2) device v dd rise time. system temperature series resistor value (and type) if used oscillator mode selection of device (which selects the gain of the internal oscillator inverter) figure 4-1 shows an example of a typical oscillator / resonator start-up. the peak-to-peak voltage of the oscillator waveform can be quite low (less than 50% of device v dd ) when the waveform is centered at v dd /2 (refer to parameter number d033 and d043 in the elec- trical speci?ation section). figure 4-1: oscillator / resonator start-up characteristics v dd crystal start-up time time
pic17c75x ds30264a-page 16 preliminary 1997 microchip technology inc. figure 4-2: crystal or ceramic resonator operation (xt or lf osc configuration) table 4-1: capacitor selection for ceramic resonators oscillator type resonator frequency capacitor range c1 = c2 (1) lf 455 khz 2.0 mhz 15 - 68 pf 10 - 33 pf xt 4.0 mhz 8.0 mhz 16.0 mhz 22 - 68 pf 33 - 100 pf 33 - 100 pf higher capacitance increases the stability of the oscillator but also increases the start-up time. these values are for design guidance only. since each resonator has its own characteristics, the user should consult the resonator manu- facturer for appropriate values of external components. note 1: these values include all board capaci- tances on this pin. actual capacitor value depends on board capacitance resonators used: 455 khz panasonic efo-a455k04b 0.3% 2.0 mhz murata erie csa2.00mg 0.5% 4.0 mhz murata erie csa4.00mg 0.5% 8.0 mhz murata erie csa8.00mt 0.5% 16.0 mhz murata erie csa16.00mx 0.5% resonators used did not have built-in capacitors. see table 4-1 and table 4-2 for recommended values of c1 and c2. note 1: a series resistor (rs) may be required for at strip cut crystals. c1 c2 xtal osc2 note1 osc1 rf sleep pic17cxxx to internal logic figure 4-3: crystal operation, overtone crystals (xt osc configuration) table 4-2: capacitor selection for crystal oscillator osc type freq c1 (3) c2 (3) lf 32 khz (1) 1 mhz 2 mhz 100-150 pf 10-33 pf 10-33 pf 100-150 pf 10-33 pf 10-33 pf xt 2 mhz 4 mhz 8 mhz (2) 16 mhz 25 mhz 32 mhz (3) 47-100 pf 15-68 pf 15-47 pf tbd 15-47 pf 10 47-100 pf 15-68 pf 15-47 pf tbd 15-47 pf 10 higher capacitance increases the stability of the oscillator but also increases the start-up time and the oscillator cur- rent. these values are for design guidance only. r s may be required in xt mode to avoid overdriving the crystals with low drive level speci?ation. since each crystal has its own characteristics, the user should consult the crystal manufac- turer for appropriate values for external components. note 1: for v dd > 4.5v, c1 = c2 ? 30 pf is recom- mended. 2: r s of 330 w is required for a capacitor com- bination of 15/15 pf. 3: these values include all board capaci- tances on this pin. actual capacitor value depends on board capacitance crystals used: 32.768 khz epson c-001r32.768k-a 20 ppm 1.0 mhz ecs-10-13-1 50 ppm 2.0 mhz ecs-20-20-1 50 ppm 4.0 mhz ecs-40-20-1 50 ppm 8.0 mhz ecs ecs-80-s-4 ecs-80-18-1 50 ppm 16.0 mhz ecs-160-20-1 tbd 25 mhz cts cts25m 50 ppm 32 mhz crystek hf-2 50 ppm c1 c2 0.1 m f sleep osc2 osc1 pic17cxxx to ?ter the fundamental frequency 1 lc2 = (2 p f) 2 where f = tank circuit resonant frequency. this should be midway between the fundamental and the 3rd overtone frequencies of the crystal.
1997 microchip technology inc. preliminary ds30264a-page 17 pic17c75x 4.1.3 external clock oscillator in the ec oscillator mode, the osc1 input can be driven by cmos drivers. in this mode, the osc1/clkin pin is hi-impedance and the osc2/clk- out pin is the clkout output (4 t osc ). figure 4-4: external clock input operation (ec osc configuration) clock from ext. system osc1 osc2 pic17cxxx clkout (f osc /4) 4.1.4 external crystal oscillator circuit either a prepackaged oscillator can be used or a simple oscillator circuit with ttl gates can be built. prepack- aged oscillators provide a wide operating range and better stability. a well-designed crystal oscillator will provide good performance with ttl gates. two types of crystal oscillator circuits can be used: one with series resonance, or one with parallel resonance. figure 4-5 shows implementation of a parallel resonant oscillator circuit. the circuit is designed to use the fun- damental frequency of the crystal. the 74as04 inverter performs the 180-degree phase shift that a parallel oscillator requires. the 4.7 k w resistor provides the negative feedback for stability. the 10 k w potentiome- ter biases the 74as04 in the linear region. this could be used for external oscillator designs. figure 4-5: external parallel resonant crystal oscillator circuit figure 4-6 shows a series resonant oscillator circuit. this circuit is also designed to use the fundamental fre- quency of the crystal. the inverter performs a 180-degree phase shift in a series resonant oscillator circuit. the 330 k w resistors provide the negative feed- back to bias the inverters in their linear region. figure 4-6: external series resonant crystal oscillator circuit 20 pf +5v 20 pf 10k 4.7k 10k 74as04 xtal 10k 74as04 pic17cxxx osc1 to other devices 330 k w 74as04 74as04 pic17cxxx osc1 to other devices xtal 330 k w 74as04 0.1 m f
pic17c75x ds30264a-page 18 preliminary 1997 microchip technology inc. 4.1.5 rc oscillator for timing insensitive applications, the rc device option offers additional cost savings. rc oscillator fre- quency is a function of the supply voltage, the resistor (rext) and capacitor (cext) values, and the operating temperature. in addition to this, oscillator frequency will vary from unit to unit due to normal process parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect oscillation frequency, especially for low cext values. the user also needs to take into account variation due to tolerance of external r and c components used. figure 4-7 shows how the r/c combination is con- nected to the pic17cxxx. for rext values below 2.2 k w , the oscillator operation may become unstable, or stop completely. for very high rext values (e.g. 1 m w ), the oscillator becomes sensitive to noise, humidity and leakage. thus, we recommend to keep rext between 3 k w and 100 k w . although the oscillator will operate with no external capacitor (cext = 0 pf), we recommend using values above 20 pf for noise and stability reasons. with little or no external capacitance, oscillation frequency can vary dramatically due to changes in external capaci- tances, such as pcb trace capacitance or package lead frame capacitance. see section 21.0 for rc frequency variation from part to part due to normal process variation. the variation is larger for larger r (since leakage current variation will affect rc frequency more for large r) and for smaller c (since variation of input capacitance will affect rc frequency more). see section 21.0 for variation of oscillator frequency due to v dd for given rext/cext values as well as fre- quency variation due to operating temperature for given r, c, and v dd values. the oscillator frequency, divided by 4, is available on the osc2/clkout pin, and can be used for test pur- poses or to synchronize other logic (see figure 4-8 for waveform). figure 4-7: rc oscillator mode v dd rext cext v ss osc1 internal clock osc2/clkout fosc/4 pic17cxxx 4.1.5.1 rc start-up as the device voltage increases, the rc will immedi- ately start its oscillations once the pin voltage levels meet the input threshold speci?ations (parameter number d032 and d042 in the electrical speci?ation section). the time required for the rc to start oscillat- ing depends on many factors. these include: resistor value used capacitor value used device v dd rise time system temperature
1997 microchip technology inc. preliminary ds30264a-page 19 pic17c75x 4.2 clocking scheme/instruction cycle the clock input (from osc1) is internally divided by four to generate four non-overlapping quadrature clocks, namely q1, q2, q3, and q4. internally, the pro- gram counter (pc) is incremented every q1, and the instruction is fetched from the program memory and latched into the instruction register in q4. the instruc- tion is decoded and executed during the following q1 through q4. the clocks and instruction execution ?w are shown in figure 4-8. 4.3 instruction flow/pipelining an ?nstruction cycle consists of four q cycles (q1, q2, q3, and q4). the instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g. goto ) then two cycles are required to complete the instruction (example 4-1). a fetch cycle begins with the program counter incre- menting in q1. in the execution cycle, the fetched instruction is latched into the ?nstruction register (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3, and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). figure 4-8: clock/instruction cycle example 4-1: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clkout (rc mode) pc pc+1 pc+2 fetch inst (pc) execute inst (pc-1) fetch inst (pc+1) execute inst (pc) fetch inst (pc+2) execute inst (pc+1) internal phase clock all instructions are single cycle, except for any program branches. these take two cycles since the fetch instruction is ushed from the pipeline while the new instruction is being fetched and then executed. tcy0 tcy1 tcy2 tcy3 tcy4 tcy5 1. movlw 55h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. call sub_1 fetch 3 execute 3 4. bsf porta, bit3 (forced nop) fetch 4 flush 5. instruction @ address sub_1 fetch sub_1 execute sub_1
pic17c75x ds30264a-page 20 preliminary 1997 microchip technology inc. notes:
1997 microchip technology inc. preliminary ds30264a-page 21 pic17c75x 5.0 reset the pic17cxxx differentiates between various kinds of reset: power-on reset (por) mclr reset during normal operation brown-out reset wdt reset (normal operation) some registers are not affected in any reset condition, their status is unknown on por and unchanged in any other reset. most other registers are forced to a ?eset state on power-on reset (por), brown-out reset (bor), on mclr or wdt reset and on mclr reset during sleep. a wdt reset during sleep, is viewed as the resumption of normal operation. the t o and pd bits are set or cleared differently in different reset situ- ations as indicated in table 5-3. these bits are used in software to determine the nature of the reset. see table 5-4 for a full description of reset states of all reg- isters. a simpli?d block diagram of the on-chip reset circuit is shown in figure 5-1. note: while the device is in a reset state, the internal phase clock is held in the q1 state. any processor mode that allows external execution will force the re0/ale pin as a low output and the re1/oe and re2/wr pins as high outputs. figure 5-1: simplified block diagram of on-chip reset circuit s r q external reset mclr v dd osc1 wdt module v dd rise detect ost/pwrt on-chip rc osc? wdt time_out power_on_reset ost 10-bit ripple counter pwrt chip_reset 10-bit ripple counter power_up (enable the pwrt timer only during power_up) (power_up) + (wake_up) (xt + lf) (enable the ost if it is power_up or wake_up from sleep and osc type is xt or lf) reset enable ost enable pwrt ? this rc oscillator is shared with the wdt when not in a power-up sequence. bor module brown-out reset
pic17c75x ds30264a-page 22 preliminary 1997 microchip technology inc. 5.1 power-on reset (por), power-up t imer (pwrt), oscillator start-up t imer (ost), and brown-out reset (bor) 5.1.1 power-on reset (por) the power-on reset circuit holds the device in reset until v dd is above the trip point (in the range of 1.4v - 2.3v). the devices produce an internal reset for both rising and falling v dd . to take advantage of the por, just tie the mclr/ v pp pin directly (or through a resistor) to v dd . this will eliminate external rc components usually needed to create power-on reset. a minimum rise time for v dd is required. see electrical speci?a- tions for details. figure 5-2 and figure 5-3 show two possible por cir- cuits. figure 5-2: using on-chip por figure 5-3: external power-on reset circuit (for slow v dd power-up) v dd mclr pic17cxxx v dd note 1: an external power-on reset circuit is required only if v dd power-up time is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r < 40 k w is recommended to ensure that the voltage drop across r does not exceed 0.2v (max. leakage current spec. on the mclr/ v pp pin is 5 m a). a larger voltage drop will degrade v ih level on the mclr/ v pp pin. 3: r1 = 100 w to 1 k w will limit any current ?wing into mclr from external capaci- tor c in the event of mclr/ v pp pin breakdown due to electrostatic dis- charge (esd) or electrical overstress (eos). c r1 r d v dd mclr pic17cxxx v dd 5.1.2 power-up timer (pwrt) the power-up timer provides a ?ed 96 ms time-out (nominal) on power-up. this occurs from the rising edge of the por signal and after the ?st rising edge of mclr (detected high). the power-up timer operates on an internal rc oscillator. the chip is kept in reset as long as the pwrt is active. in most cases the pwrt delay allows v dd to rise to an acceptable level. the power-up time delay will vary from chip to chip and with v dd and temperature. see dc parameters for details. 5.1.3 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides a 1024 oscillator cycle (1024t osc ) delay after mclr is detected high or a wake-up from sleep event occurs. the ost time-out is invoked only for xt and lf oscil- lator modes on a power-on reset or a wake-up from sleep. the ost counts the oscillator pulses on the osc1/clkin pin. the counter only starts incrementing after the amplitude of the signal reaches the oscillator input thresholds. this delay allows the crystal oscillator or resonator to stabilize before the device exits reset. the length of the time-out is a function of the crys- tal/resonator frequency. figure 5-4 shows the operation of the ost circuit. in this ?ure the oscillator is of such a low frequency that ost time out occurs after the power-up timer time-out. figure 5-4: oscillator start-up time v dd mclr osc2 ost time_out pwrt time_out internal reset t osc 1 t ost t pwrt por or bor trip point this ?ure shows in greater detail the timings involved with the oscillator start-up timer. in this example the low frequency crystal start-up time is larger than power-up time (t pwrt ). tosc1 = time for the crystal oscillator to react to an oscil- lation level detectable by the oscillator start-up timer (ost). t ost = 1024t osc .
1997 microchip technology inc. preliminary ds30264a-page 23 pic17c75x 5.1.4 time-out sequence on power-up the time-out sequence is as follows: first the internal por signal goes high when the por trip point is reached. if mclr is high, then both the ost and pwrt timers start. in general the pwrt time-out is longer, except with low frequency crystals/resona- tors. the total time-out also varies based on oscillator con?uration. table 5-1 shows the times that are asso- ciated with the oscillator con?uration. figure 5-5 and figure 5-6 display these time-out sequences. if the device voltage is not within electrical speci?ation at the end of a time-out, the mclr/ v pp pin must be held low until the voltage is within the device speci?a- tion. the use of an external rc delay is suf?ient for many of these applications. the time-out sequence begins from the ?st rising edge of mclr . table 5-3 shows the reset conditions for some special registers, while table 5-4 shows the initialization condi- tions for all the registers. table 5-1: time-out in various situations table 5-2: status bits and their significance table 5-3: reset condition for the program counter and the cpusta register oscillator con?uration power-up wake up from sleep mclr reset bor xt, lf greater of: 96 ms or 1024t osc 1024t osc ec, rc greater of: 96 ms or 1024t osc por bor (1) t o pd event 0011 power-on reset 1110 mclr reset during sleep or interrupt wake-up from sleep 1101 wdt reset during normal operation 1100 wdt wake-up during sleep 1111 mclr reset during normal operation 10xx brown-out reset 000x illegal, t o is set on por 00x0 illegal, pd is set on por xx11 clrwdt instruction executed note 1: when bor is enabled, else the bor status bit is unknown event pch:pcl cpusta (4) ost active power-on reset 0000h --11 1100 ye s brown-out reset 0000h --11 1101 no mclr reset during normal operation 0000h --11 1111 no mclr reset during sleep 0000h --11 1011 yes (2) wdt reset during normal operation 0000h --11 0111 no wdt wake-up during sleep (3) 0000h --11 0011 yes (2) interrupt wake-up from sleep glintd is set pc + 1 --11 1011 yes (2) glintd is clear pc + 1 (1) --10 1011 yes (2) legend: u = unchanged, x = unknown, - = unimplemented read as '0'. note 1: on wake-up, this instruction is executed. the instruction at the appropriate interrupt vector is fetched and then executed. 2: the ost is only active when the oscillator is con?ured for xt or lf modes. 3: the program counter = 0, that is, the device branches to the reset vector. this is different from the mid-range devices. 4: when bor is enabled, else the bor status bit is unknown.
pic17c75x ds30264a-page 24 preliminary 1997 microchip technology inc. in figure 5-5, figure 5-6 and figure 5-7, t pwrt > t ost , as would be the case in higher frequency crys- tals. for lower frequency crystals, (i.e., 32 khz) t ost would be greater. figure 5-5: time-out sequence on power-up (mclr tied to v dd ) figure 5-6: time-out sequence on power-up (mclr not tied to v dd ) figure 5-7: slow rise time (mclr tied to v dd ) t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset v dd mclr internal por pwr t time-out ost time-out internal reset 0v 1v 5v t pwrt t ost minimum v dd operating voltage
1997 microchip technology inc. preliminary ds30264a-page 25 pic17c75x table 5-4: initialization conditions for special function registers register address power-on reset brown-out reset mclr reset wdt reset wake-up from sleep through interrupt unbanked indf0 00h n.a. n.a. n.a. fsr0 01h xxxx xxxx uuuu uuuu uuuu uuuu pcl 02h 0000h 0000h pc + 1 (2) pclath 03h 0000 0000 0000 0000 uuuu uuuu alusta 04h 1111 xxxx 1111 uuuu 1111 uuuu t0sta 05h 0000 000- 0000 000- 0000 000- cpusta (3) 06h --11 1100 (4) --11 qquu (4) --uu qquu (4) intsta 07h 0000 0000 0000 0000 uuuu uuuu (1) indf1 08h n.a. n.a. n.a. fsr1 09h xxxx xxxx uuuu uuuu uuuu uuuu wreg 0ah xxxx xxxx uuuu uuuu uuuu uuuu tmr0l 0bh xxxx xxxx uuuu uuuu uuuu uuuu tmr0h 0ch xxxx xxxx uuuu uuuu uuuu uuuu tblptrl 0dh 0000 0000 0000 0000 uuuu uuuu tblptrh 0eh 0000 0000 0000 0000 uuuu uuuu bsr 0fh 0000 0000 0000 0000 uuuu uuuu bank 0 porta 10h 0-xx xxxx 0-uu uuuu u-uu uuuu ddrb 11h 1111 1111 1111 1111 uuuu uuuu portb 12h xxxx xxxx uuuu uuuu uuuu uuuu rcsta1 13h 0000 -00x 0000 -00u uuuu -uuu rcreg1 14h xxxx xxxx uuuu uuuu uuuu uuuu txsta1 15h 0000 --1x 0000 --1u uuuu --uu txreg1 16h xxxx xxxx uuuu uuuu uuuu uuuu spbrg1 17h xxxx xxxx uuuu uuuu uuuu uuuu bank 1 ddrc 10h 1111 1111 1111 1111 uuuu uuuu portc 11h xxxx xxxx uuuu uuuu uuuu uuuu ddrd 12h 1111 1111 1111 1111 uuuu uuuu portd 13h xxxx xxxx uuuu uuuu uuuu uuuu ddre 14h ---- 1111 ---- 1111 ---- uuuu porte 15h ---- xxxx ---- uuuu ---- uuuu pir1 16h x000 0010 u000 0010 uuuu uuuu (1) pie1 17h 0000 0000 0000 0000 uuuu uuuu legend: u = unchanged, x = unknown, - = unimplemented read as '0', q = value depends on condition. note 1: one or more bits in intsta, pir1, pir2 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the glintd bit is cleared, the pc is loaded with the interrupt vector. 3: see table 5-3 for reset value of speci? condition. 4: if brown-out is enabled, else the bor bit is unknown.
pic17c75x ds30264a-page 26 preliminary 1997 microchip technology inc. bank 2 tmr1 10h xxxx xxxx uuuu uuuu uuuu uuuu tmr2 11h xxxx xxxx uuuu uuuu uuuu uuuu tmr3l 12h xxxx xxxx uuuu uuuu uuuu uuuu tmr3h 13h xxxx xxxx uuuu uuuu uuuu uuuu pr1 14h xxxx xxxx uuuu uuuu uuuu uuuu pr2 15h xxxx xxxx uuuu uuuu uuuu uuuu pr3/ca1l 16h xxxx xxxx uuuu uuuu uuuu uuuu pr3/ca1h 17h xxxx xxxx uuuu uuuu uuuu uuuu bank 3 pw1dcl 10h xx-- ---- uu-- ---- uu-- ---- pw2dcl 11h xx0- ---- uu0- ---- uuu- ---- pw1dch 12h xxxx xxxx uuuu uuuu uuuu uuuu pw2dch 13h xxxx xxxx uuuu uuuu uuuu uuuu ca2l 14h xxxx xxxx uuuu uuuu uuuu uuuu ca2h 15h xxxx xxxx uuuu uuuu uuuu uuuu tcon1 16h 0000 0000 0000 0000 uuuu uuuu tcon2 17h 0000 0000 0000 0000 uuuu uuuu bank 4 pir2 10h 000- 0010 000- 0010 uuu- uuuu (1) pie2 11h 000- 0000 000- 0000 uuu- uuuu unimplemented 12h ---- ---- ---- ---- ---- ---- rcsta2 13h 0000 -00x 0000 -00u uuuu -uuu rcreg2 14h xxxx xxxx uuuu uuuu uuuu uuuu txsta2 15h 0000 --1x 0000 --1u uuuu --uu txreg2 16h xxxx xxxx uuuu uuuu uuuu uuuu spbrg2 17h xxxx xxxx uuuu uuuu uuuu uuuu bank 5 ddrf 10h 1111 1111 1111 1111 uuuu uuuu portf 11h xxxx xxxx uuuu uuuu uuuu uuuu ddrg 12h 1111 1111 1111 1111 uuuu uuuu portg 13h xxxx xxxx uuuu uuuu uuuu uuuu adcon0 14h 0000 -0-0 0000 -0-0 uuuu uuuu adcon1 15h 000- 0000 000- 0000 uuuu uuuu adresl 16h xxxx xxxx xxxx xxxx uuuu uuuu adresh 17h xxxx xxxx xxxx xxxx uuuu uuuu table 5-4: initialization conditions for special function registers (cont.?) register address power-on reset brown-out reset mclr reset wdt reset wake-up from sleep through interrupt legend: u = unchanged, x = unknown, - = unimplemented read as '0', q = value depends on condition. note 1: one or more bits in intsta, pir1, pir2 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the glintd bit is cleared, the pc is loaded with the interrupt vector. 3: see table 5-3 for reset value of speci? condition. 4: if brown-out is enabled, else the bor bit is unknown.
1997 microchip technology inc. preliminary ds30264a-page 27 pic17c75x bank 6 sspadd 10h 0000 0000 0000 0000 uuuu uuuu sspcon1 11h 0000 0000 0000 0000 uuuu uuuu sspcon2 12h 0000 0000 0000 0000 uuuu uuuu sspstat 13h 0000 0000 0000 0000 uuuu uuuu sspbuf 14h xxxx xxxx uuuu uuuu uuuu uuuu unimplemented 15h ---- ---- ---- ---- ---- ---- unimplemented 16h ---- ---- ---- ---- ---- ---- unimplemented 17h ---- ---- ---- ---- ---- ---- bank 7 pw3dcl 10h xxx- ---- uuu- ---- uuu- ---- pw3dch 11h xxxx xxxx uuuu uuuu uuuu uuuu ca3l 12h xxxx xxxx uuuu uuuu uuuu uuuu ca3h 13h xxxx xxxx uuuu uuuu uuuu uuuu ca4l 14h xxxx xxxx uuuu uuuu uuuu uuuu ca4h 15h xxxx xxxx uuuu uuuu uuuu uuuu tcon3 16h -000 0000 -000 0000 -uuu uuuu unimplemented 17h ---- ---- ---- ---- ---- ---- unbanked prodl 18h xxxx xxxx uuuu uuuu uuuu uuuu prodh 19h xxxx xxxx uuuu uuuu uuuu uuuu table 5-4: initialization conditions for special function registers (cont.?) register address power-on reset brown-out reset mclr reset wdt reset wake-up from sleep through interrupt legend: u = unchanged, x = unknown, - = unimplemented read as '0', q = value depends on condition. note 1: one or more bits in intsta, pir1, pir2 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the glintd bit is cleared, the pc is loaded with the interrupt vector. 3: see table 5-3 for reset value of speci? condition. 4: if brown-out is enabled, else the bor bit is unknown.
pic17c75x ds30264a-page 28 preliminary 1997 microchip technology inc. 5.1.5 brown-out reset (bor) pic17c75x devices have an on-chip brown-out reset circuitry. this circuitry places the device into a reset when the device voltage falls below a trip point (bv dd ). this ensures that the device does not continue pro- gram execution outside the valid operation range of the device. brown-out resets are typically used in ac line applications or large battery applications where large loads may be switched in (such as automotive). a con?uration bit, boden, can disable (if clear/pro- grammed) or enable (if set) the brown-out reset cir- cuitry. if v dd falls below bv dd (typically 4.0v, parameter d005 in electrical speci?ation section), for greater than parameter d035, the brown-out situation will reset the chip. a reset is not guaranteed to occur if v dd falls below bv dd for less than parameter d035. the chip will remain in brown-out reset until v dd rises above bv dd . the power-up timer will now be invoked and will keep the chip in reset an additional 96 ms. if v dd drops below bv dd while the power-up timer is running, the chip will go back into a brown-out reset and the power-up timer will be initialized. once v dd rises above bv dd , the power-up timer will execute a 96 ms time delay. figure 5-10 shows typical brown-out situations. in some applications the brown-out reset trip point of the device may not be at the desired level. figure 5-8 and figure 5-9 are two examples of external circuitry that may be implemented. each needs to be evaluated to determine if they match the requirements of the application. note: before using the on-chip brown-out for a voltage supervisory function, please review the electrical speci?ations to ensure that they meet your requirements. figure 5-8: external brown-out protection circuit 1 figure 5-9: external brown-out protection circuit 2 v dd 33k 10k 40 k w v dd mclr pic17cxxx this circuit will activate reset when v dd goes below (vz + 0.7v) where vz = zener voltage. this brown-out circuit is less expensive, albeit less accurate. transistor q1 turns off when v dd is below a certain level such that: v dd r1 r1 + r2 = 0.7v r2 40 k w v dd mclr pic17cxxx r1 q1 v dd figure 5-10: brown-out situations 96 ms bv dd max. bv dd min. v dd internal reset bv dd max. bv dd min. v dd internal reset 96 ms < 96 ms 96 ms bv dd max. bv dd min. v dd internal reset
1997 microchip technology inc. preliminary ds30264a-page 29 pic17c75x 6.0 interrupts the pic17c75x devices have 18 sources of interrupt: external interrupt from the ra0/int pin change on rb7:rb0 pins tmr0 over?w tmr1 over?w tmr2 over?w tmr3 over?w usart1 transmit buffer empty usart1 receive buffer full usart2 transmit buffer empty usart2 receive buffer full ssp interrupt ssp i 2 c bus collision interrupt a/d conversion complete capture1 capture2 capture3 capture4 t0cki edge occurred there are six registers used in the control and status of interrupts. these are: cpusta intsta pie1 pir1 pie2 pir2 the cpusta register contains the glintd bit. this is the global interrupt disable bit. when this bit is set, all interrupts are disabled. this bit is part of the controller core functionality and is described in the memory orga- nization section. when an interrupt is responded to, the glintd bit is automatically set to disable any further interrupts, the return address is pushed onto the stack and the pc is loaded with the interrupt vector address. there are four interrupt vectors. each vector address is for a speci? interrupt source (except the peripheral interrupts which all vector to the same address). these sources are: external interrupt from the ra0/int pin tmr0 over?w t0cki edge occurred any peripheral interrupt when program execution vectors to one of these inter- rupt vector addresses (except for the peripheral inter- rupts), the interrupt ?g bit is automatically cleared. vectoring to the peripheral interrupt vector address does not automatically clear the source of the interrupt. in the peripheral interrupt service routine, the source(s) of the interrupt can be determined by testing the inter- rupt ?g bits. the interrupt ?g bit(s) must be cleared in software before re-enabling interrupts to avoid in?ite interrupt requests. when an interrupt condition is met, that individual inter- rupt ?g bit will be set regardless of the status of its cor- responding mask bit or the glintd bit. for external interrupt events, there will be an interrupt latency. for two cycle instructions, the latency could be one instruction cycle longer. the ?eturn from interrupt instruction, retfie , can be used to mark the end of the interrupt service routine. when this instruction is executed, the stack is ?oped? and the glintd bit is cleared (to re-enable interrupts). figure 6-1: interrupt logic rbif rbie tmr3if tmr3ie tmr2if tmr2ie tmr1if tmr1ie ca2if ca2ie ca1if ca1ie tx1if tx1ie rc1if rc1ie t0if t0ie intf inte t0ckif t0ckie glintd (cpusta<4>) peie wake-up (if in sleep mode) or terminate long write interrupt to cpu peif sspif sspie bclif bclie adif adie ca4if ca4ie ca3if ca3ie tx2if tx2ie rc2if rc2ie pir1 / pie1 pir2 / pie2 intsta
pic17c75x ds30264a-page 30 preliminary 1997 microchip technology inc. 6.1 interrupt status register (intst a) the interrupt status/control register (intsta) records the individual interrupt requests in ?g bits, and con- tains the individual interrupt enable bits (not for the peripherals). the peif bit is a read only, bit wise or of all the periph- eral ?g bits in the pir registers (figure 6-5 and figure 6-6). care should be taken when clearing any of the intsta register enable bits when interrupts are enabled (glintd is clear). if any of the intsta ?g bits (t0if, intf, t0ckif, or peif) are set in the same instruction cycle as the corresponding interrupt enable bit is cleared, the device will vector to the reset address (0x00). when disabling any of the intsta enable bits, the glintd bit should be set (disabled). note: t0if, intf, t0ckif, and peif get set by their speci?d condition, even if the corre- sponding interrupt enable bit is clear (inter- rupt disabled) or the glintd bit is set (all interrupts disabled). figure 6-2: intsta register (address: 07h, unbanked) r - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 peif t0ckif t0if intf peie t0ckie t0ie inte r = readable bit w = writable bit - n = value at por reset bit7 bit0 bit 7: peif : peripheral interrupt flag bit this bit is the or of all peripheral interrupt ?g bits and?d with their corresponding enable bits. 1 = a peripheral interrupt is pending 0 = no peripheral interrupt is pending bit 6: t0ckif : external interrupt on t0cki pin flag bit this bit is cleared by hardware, when the interrupt logic forces program execution to vector (18h). 1 = the software speci?d edge occurred on the ra1/t0cki pin 0 = the software speci?d edge did not occur on the ra1/t0cki pin bit 5: t0if : tmr0 over?w interrupt flag bit this bit is cleared by hardware, when the interrupt logic forces program execution to vector (10h). 1 = tmr0 over?wed 0 = tmr0 did not over?w bit 4: intf : external interrupt on int pin flag bit this bit is cleared by hardware, when the interrupt logic forces program execution to vector (08h). 1 = the software speci?d edge occurred on the ra0/int pin 0 = the software speci?d edge did not occur on the ra0/int pin bit 3: peie : peripheral interrupt enable bit this bit enables all peripheral interrupts that have their corresponding enable bits set. 1 = enable peripheral interrupts 0 = disable peripheral interrupts bit 2: t0ckie : external interrupt on t0cki pin enable bit 1 = enable software speci?d edge interrupt on the ra1/t0cki pin 0 = disable interrupt on the ra1/t0cki pin bit 1: t0ie : tmr0 over?w interrupt enable bit 1 = enable tmr0 over?w interrupt 0 = disable tmr0 over?w interrupt bit 0: inte : external interrupt on ra0/int pin enable bit 1 = enable software speci?d edge interrupt on the ra0/int pin 0 = disable software speci?d edge interrupt on the ra0/int pin
1997 microchip technology inc. preliminary ds30264a-page 31 pic17c75x 6.2 peripheral interrupt enable register1 (pie1) and register2 (pie2) these registers contains the individual enable bits for the peripheral interrupts. figure 6-3: pie1 register (address: 17h, bank 1) r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 rbie tmr3ie tmr2ie tmr1ie ca2ie ca1ie tx1ie rc1ie r = readable bit w = writable bit -n = value at por reset bit7 bit0 bit 7: rbie : portb interrupt on change enable bit 1 = enable portb interrupt on change 0 = disable portb interrupt on change bit 6: tmr3ie : tmr3 interrupt enable bit 1 = enable tmr3 interrupt 0 = disable tmr3 interrupt bit 5: tmr2ie : tmr2 interrupt enable bit 1 = enable tmr2 interrupt 0 = disable tmr2 interrupt bit 4: tmr1ie : tmr1 interrupt enable bit 1 = enable tmr1 interrupt 0 = disable tmr1 interrupt bit 3: ca2ie : capture2 interrupt enable bit 1 = enable capture2 interrupt 0 = disable capture2 interrupt bit 2: ca1ie : capture1 interrupt enable bit 1 = enable capture1 interrupt 0 = disable capture1 interrupt bit 1: tx1ie : usart1 transmit interrupt enable bit 1 = enable usart1 transmit buffer empty interrupt 0 = disable usart1 transmit buffer empty interrupt bit 0: rc1ie : usart1 receive interrupt enable bit 1 = enable usart1 receive buffer full interrupt 0 = disable usart1 receive buffer full interrupt
pic17c75x ds30264a-page 32 preliminary 1997 microchip technology inc. figure 6-4: pie2 register (address: 11h, bank 4) r/w - 0 r/w - 0 r/w - 0 u - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 sspie bclie adie ca4ie ca3ie tx2ie rc2ie r = readable bit w = writable bit -n = value at por reset bit7 bit0 bit 7: sspie : synchronous serial port interrupt enable 1 = enable ssp interrupt 0 = disable ssp interrupt bit 6: bclie : bus collision interrupt enable 1 = enable bus collision interrupt 0 = disable bus collision interrupt bit 5: adie : a/d module interrupt enable 1 = enable a/d module interrupt 0 = disable a/d module interrupt bit 4: unimplemented: read as ? bit 3: ca4ie : capture4 interrupt enable 1 = enable capture4 interrupt 0 = disable capture4 interrupt bit 2: ca3ie : capture3 interrupt enable 1 = enable capture3 interrupt 0 = disable capture3 interrupt bit 1: tx2ie : usart2 transmit interrupt enable 1 = enable usart2 transmit interrupt 0 = disable usart2 transmit interrupt bit 0: rc2ie : usart2 receive interrupt enable 1 = enable usart2 receive interrupt 0 = disable usart2 receive interrupt
1997 microchip technology inc. preliminary ds30264a-page 33 pic17c75x 6.3 peripheral interr upt request register1 (pir1) and register2 (pir2) these registers contains the individual ?g bits for the peripheral interrupts. note: these bits will be set by the speci?d con- dition, even if the corresponding interrupt enable bit is cleared (interrupt disabled), or the glintd bit is set (all interrupts dis- abled). before enabling an interrupt, the user may wish to clear the interrupt ?g to ensure that the program does not immedi- ately branch to the peripheral interrupt ser- vice routine. figure 6-5: pir1 register (address: 16h, bank 1) r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r - 1 r - 0 rbif tmr3if tmr2if tmr1if ca2if ca1if tx1if rc1if r = readable bit w = writable bit -n = value at por reset bit7 bit0 bit 7: rbif : portb interrupt on change flag bit 1 = one of the portb inputs changed (software must end the mismatch condition) 0 = none of the portb inputs have changed bit 6: tmr3if : tmr3 interrupt flag bit if capture1 is enab led (ca1/ pr 3 = 1) 1 = tmr3 over?wed 0 = tmr3 did not over?w if capture1 is disab led (ca1/ pr 3 = 0) 1 = tmr3 value has rolled over to 0000h from equalling the period register (pr3h:pr3l) value 0 = tmr3 value has not rolled over to 0000h from equalling the period register (pr3h:pr3l) value bit 5: tmr2if : tmr2 interrupt flag bit 1 = tmr2 value has rolled over to 0000h from equalling the period register (pr2) value 0 = tmr2 value has not rolled over to 0000h from equalling the period register (pr2) value bit 4: tmr1if : tmr1 interrupt flag bit if tmr1 i s in 8-bit mode (t16 = 0) 1 = tmr1 value has rolled over to 0000h from equalling the period register (pr1) value 0 = tmr1 value has not rolled over to 0000h from equalling the period register (pr1) value if timer1 is in 16-bit mode (t16 = 1) 1 = tmr2:tmr1 value has rolled over to 0000h from equalling the period register (pr2:pr1) value 0 = tmr2:tmr1 value has not rolled over to 0000h from equalling the period register (pr2:pr1) value bit 3: ca2if : capture2 interrupt flag bit 1 = capture event occurred on rb1/cap2 pin 0 = capture event did not occur on rb1/cap2 pin bit 2: ca1if : capture1 interrupt flag bit 1 = capture event occurred on rb0/cap1 pin 0 = capture event did not occur on rb0/cap1 pin bit 1: tx1if : usart1 transmit interrupt flag bit (state controlled by hardware) 1 = usart1 transmit buffer is empty 0 = usart1 transmit buffer is full bit 0: rc1if : usart1 receive interrupt flag bit (state controlled by hardware) 1 = usart1 receive buffer is full 0 = usart1 receive buffer is empty
pic17c75x ds30264a-page 34 preliminary 1997 microchip technology inc. figure 6-6: pir2 register (address: 10h, bank 4) r/w - 0 r/w - 0 r/w - 0 u - 0 r/w - 0 r/w - 0 r - 1 r - 0 sspif bclif adif ca4if ca3if tx2if rc2if r = readable bit w = writable bit -n = value at por reset bit7 bit0 bit 7: sspif : synchronous serial port (ssp) interrupt flag 1 = the ssp interrupt condition has occured, and must be cleared in software before returning from the interrupt service routine. the conditions that will set this bit are: spi a transmission/reception has taken place. i 2 c sla v e / master a transmission/reception has taken place. i 2 c master the initiated start condition was completed by the ssp module. the initiated stop condition was completed by the ssp module. the initiated restart condition was completed by the ssp module. the initiated acknowledge condition was completed by the ssp module. a start condition occurred while the ssp module was idle (multimaster system). a stop condition occurred while the ssp module was idle (multimaster system). 0 = an ssp interrupt condition has occurred. bit 6: bclif : bus collision interrupt flag 1 = a bus collision has occurred in the ssp, when con?ured for i 2 c master mode 0 = no bus collision has occurred bit 5: adif : a/d module interrupt flag 1 = an a/d conversion is complete 0 = an a/d conversion is not complete bit 4: unimplemented : read as '0' bit 3: ca4if : capture4 interrupt flag 1 = capture event occurred on re3/cap4 pin 0 = capture event did not occur on re3/cap4 pin bit 2: ca3if : capture3 interrupt flag 1 = capture event occurred on rg4/cap3 pin 0 = capture event did not occur on rg4/cap3 pin bit 1: tx2if :usart2 transmit interrupt flag (state controlled by hardware) 1 = usart2 transmit buffer is empty 0 = usart2 transmit buffer is full bit 0: rc2if : usart2 receive interrupt flag (state controlled by hardware) 1 = usart2 receive buffer is full 0 = usart2 receive buffer is empty
1997 microchip technology inc. preliminary ds30264a-page 35 pic17c75x 6.4 interrupt operation global interrupt disable bit, glintd (cpusta<4>), enables all unmasked interrupts (if clear) or disables all interrupts (if set). individual interrupts can be disabled through their corresponding enable bits in the intsta register. peripheral interrupts need either the global peripheral enable peie bit disabled, or the speci? peripheral enable bit disabled. disabling the peripher- als via the global peripheral enable bit, disables all peripheral interrupts. glintd is set on reset (interrupts disabled). the retfie instruction allows returning from interrupt and re-enables interrupts at the same time. when an interrupt is responded to, the glintd bit is automatically set to disable any further interrupt, the return address is pushed onto the stack and the pc is loaded with the interrupt vector. there are four interrupt vectors which help reduce interrupt latency. the peripheral interrupt vector has multiple interrupt sources. once in the peripheral interrupt service rou- tine, the source(s) of the interrupt can be determined by polling the interrupt ?g bits. the peripheral interrupt ?g bit(s) must be cleared in software before re-enabling interrupts to avoid continuous interrupts. the pic17c75x devices have four interrupt vectors. these vectors and their hardware priority are shown in table 6-1. if two enabled interrupts occur ?t the same time? the interrupt of the highest priority will be ser- viced ?st. this means that the vector address of that interrupt will be loaded into the program counter (pc). table 6-1: interrupt vectors/priorities address vector priority 0008h external interrupt on ra0/int pin (intf) 1 (highest) 0010h tmr0 over?w interrupt (t0if) 2 0018h external interrupt on t0cki (t0ckif) 3 0020h peripherals (peif) 4 (lowest) note 1: individual interrupt ?g bits are set regard- less of the status of their corresponding mask bit or the glintd bit. note 2: before disabling any of the intsta enable bits, the glintd bit should be set (disabled). 6.5 ra0 /int interrupt the external interrupt on the ra0/int pin is edge trig- gered. either the rising edge, if intedg bit (t0sta<7>) is set, or the falling edge, if intedg bit is clear. when a valid edge appears on the ra0/int pin, the intf bit (intsta<4>) is set. this interrupt can be disabled by clearing the inte control bit (intsta<0>). the int interrupt can wake the processor from sleep. see section 17.4 for details on sleep operation. 6.6 t 0c k i interrupt the external interrupt on the ra1/t0cki pin is edge triggered. either the rising edge, if the t0se bit (t0sta<6>) is set, or the falling edge, if the t0se bit is clear. when a valid edge appears on the ra1/t0cki pin, the t0ckif bit (intsta<6>) is set. this interrupt can be disabled by clearing the t0ckie control bit (intsta<2>). the t0cki interrupt can wake up the processor from sleep. see section 17.4 for details on sleep operation. 6.7 per ipheral interrupt the peripheral interrupt ?g indicates that at least one of the peripheral interrupts occurred (peif is set). the peif bit is a read only bit, and is a bit wise or of all the ?g bits in the pir registers and?d with the corre- sponding enable bits in the pie registers. some of the peripheral interrupts can wake the processor from sleep. see section 17.4 for details on sleep opera- tion. 6.8 context saving during interrupts during an interrupt, only the returned pc value is saved on the stack. typically, users may wish to save key reg- isters during an interrupt; e.g. wreg, alusta and the bsr registers. this requires implementation in soft- ware. example 6-2 shows the saving and restoring of infor- mation for an interrupt service routine. this is for a sim- ple interrupt scheme, where only one interrupt may occur at a time (no interrupt nesting). the sfrs are stored in the non-banked gpr area. example 6-2 shows the saving and restoring of infor- mation for a more complex interrupt service routine. this is useful where nesting of interrupts is required. a maximum of 6 levels can be done by this example. the bsr is stored in the non-banked gpr area, while the other registers would be stored in a particular bank. therefore 6 saves may be done with this routine (since there are 6 non-banked gpr registers). these routines require a dedicated indirect addressing register, fsr0 has been selected for this. the push and pop code segments could either be in each interrupt service routine or could be subroutines that were called. depending on the application, other registers may also need to be saved.
pic17c75x ds30264a-page 36 preliminary 1997 microchip technology inc. figure 6-7: int pin / t0cki pin interrupt timing q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 osc1 osc2 ra0/int or ra1/t0cki intf or t0ckif glintd pc instruction executed system bus instruction fetched pc pc + 1 addr (vector) pc inst (pc) inst (pc+1) inst (pc) dummy dummy yy yy + 1 retfie retfie inst (pc+1) inst (vector) addr addr addr addr addr inst (yy + 1) dummy pc + 1
1997 microchip technology inc. preliminary ds30264a-page 37 pic17c75x example 6-1: saving status and wreg in ram (simple) ; the addresses that are used to store the cpusta and wreg values must be in the data memory ; address range of 1ah - 1fh. up to 6 locations can be saved and restored using the movfp ; instruction. this instruction neither affects the status bits, nor corrupts the wreg register. ; unbank1 equ 0x01a ; address for 1st location to save unbank2 equ 0x01b ; address for 2nd location to save unbank3 equ 0x01c ; address for 3rd location to save unbank4 equ 0x01d ; address for 4th location to save unbank5 equ 0x01e ; address for 5th location to save ; (label not used in program) unbank6 equ 0x01f ; address for 6th location to save ; (label not used in program) ; : ; at interrupt vector address push movfp alusta, unbank1 ; push alusta value movfp bsr, unbank2 ; push bsr value movfp wreg, unbank3 ; push wreg value movfp pclath, unbank4 ; push pclath value ; : ; interrupt service routine (isr) code ; pop movfp unbank4, pclath ; restore pclath value movfp unbank3, wreg ; restore wreg value movfp unbank2, bsr ; restore bsr value movfp unbank1, alusta ; restore alusta value ; retfie ; return from interrupt (enable interrupts)
pic17c75x ds30264a-page 38 preliminary 1997 microchip technology inc. example 6-2: saving status and wreg in ram (nested) ; the addresses that are used to store the cpusta and wreg values must be in the data memory ; address range of 1ah - 1fh. up to 6 locations can be saved and restored using the movfp ; instruction. this instruction neither affects the status bits, nor corrupts the wreg register. ; this routine uses the frs0, so it controls the fs1 and fs0 bits in the alusta register. ; nobank_fsr equ 0x40 bank_fsr equ 0x41 alu_temp equ 0x42 wreg_temp equ 0x43 bsr_s1 equ 0x01a ; 1st location to save bsr bsr_s2 equ 0x01b ; 2nd location to save bsr (label not used in program) bsr_s3 equ 0x01c ; 3rd location to save bsr (label not used in program) bsr_s4 equ 0x01d ; 4th location to save bsr (label not used in program) bsr_s5 equ 0x01e ; 5th location to save bsr (label not used in program) bsr_s6 equ 0x01f ; 6th location to save bsr (label not used in program) ; initialization ; call clear_ram ; must clear all data ram ; init_pointers ; must initialize the pointers for pop and push clrf bsr, f ; set all banks to 0 clrf alusta, f ; fsr0 post increment bsf alusta, fs1 clrf wreg, f ; clear wreg movlw bsr_s1 ; load fsr0 with 1st address to save bsr movwf fsr0 movwf nobank_fsr movlw 0x20 movwf bank_fsr : : ; your code : : ; at interrupt vector address push bsf alusta, fs0 ; fsr0 has auto-increment, does not affect status bits bcf alusta, fs1 ; does not affect status bits movfp bsr, indf0 ; no status bits are affected clrf bsr, f ; periperal and data ram bank 0 no status bits are affected movpf alusta, alu_temp ; movpf fsr0, nobank_fsr ; save the fsr for bsr values movpf wreg, wreg_temp ; movfp bank_fsr, fsr0 ; restore fsr value for other values movfp alu_temp, indf0 ; push alusta value movfp wreg_temp, indf0 ; push wreg value movfp pclath, indf0 ; push pclath value movpf fsr0, bank_fsr ; restore fsr value for other values movfp nobank_fsr, fsr0 ; ; : ; interrupt service routine (isr) code ; pop clrf alusta, f ; fsr0 has auto-decrement, does not affect status bits movfp bank_fsr, fsr0 ; restore fsr value for other values decf fsr0, f ; movfp indf0, pclath ; pop pclath value movfp indf0, wreg ; pop wreg value bsf alusta, fs1 ; fsr0 does not change movpf indf0, alu_temp ; pop alusta value movpf fsr0, bank_fsr ; restore fsr value for other values decf nobank_fsr, f ; movfp nobank_fsr, fsr0 ; save the fsr for bsr values movfp alu_temp, alusta ; movfp indf0, bsr ; no status bits are affected ; retfie ; return from interrupt (enable interrupts)
1997 microchip technology inc. preliminary ds30264a-page 39 pic17c75x 7.0 memory organization there are two memory blocks in the pic17c75x; pro- gram memory and data memory. each block has its own bus, so that access to each block can occur during the same oscillator cycle. the data memory can further be broken down into general purpose ram and the special function reg- isters (sfrs). the operation of the sfrs that control the ?ore are described here. the sfrs used to con- trol the peripheral modules are described in the section discussing each individual peripheral module. 7.1 program memory organization pic17c75x devices have a 16-bit program counter capable of addressing a 64k x 16 program memory space. the reset vector is at 0000h and the interrupt vectors are at 0008h, 0010h, 0018h, and 0020h (figure 7-1). 7.1.1 program memory operation the pic17c75x can operate in one of four possible program memory con?urations. the con?uration is selected by con?uration bits. the possible modes are: microprocessor microcontroller extended microcontroller protected microcontroller the microcontroller and protected microcontroller modes only allow internal execution. any access beyond the program memory reads unknown data. the protected microcontroller mode also enables the code protection feature. the extended microcontroller mode accesses both the internal program memory as well as external program memory. execution automatically switches between internal and external memory. the 16-bits of address allow a program memory range of 64k-words. the microprocessor mode only accesses the external program memory. the on-chip program memory is ignored. the 16-bits of address allow a program mem- ory range of 64k-words. microprocessor mode is the default mode of an unprogrammed device. the different modes allow different access to the con- ?uration bits, test memory, and boot rom. table 7-1 lists which modes can access which areas in memory. test memory and boot memory are not required for normal operation of the device. care should be taken to ensure that no unintended branches occur to these areas. figure 7-1: program memory map and stack pc<15:0> stack level 1 stack level 16 reset vector int pin interrupt vector timer0 interrupt vector t0cki pin interrupt vector peripheral interrupt vector fosc0 fosc1 wdtps0 wdtps1 pm0 reserved pm1 reserved con?uration memory space user memory space (1) call, return retfie, retlw 16 0000h 0008h 0010h 0020h 0021h 0018h fdffh fe00h fe01h fe02h fe03h fe04h fe05h fe06h fe07h fe0fh test eprom boot rom fe10h ff5fh ff60h ffffh 1fffh 3fffh (pic17c752) (pic17c756) reserved pm2 fe08h note 1: user memory space may be internal, external, or both. the memory con?uration depends on the processor mode. fe0eh boden fe0dh
pic17c75x ds30264a-page 40 preliminary 1997 microchip technology inc. table 7-1: mode memory access operating mode internal program memory con?uration bits, test memory, boot rom microprocessor no access no access microcontroller access access extended microcontroller access no access protected microcontroller access access the pic17c75x can operate in modes where the pro- gram memory is off-chip. they are the microprocessor and extended microcontroller modes. the micropro- cessor mode is the default for an unprogrammed device. regardless of the processor mode, data memory is always on-chip. figure 7-2: memory map in different modes microprocessor mode 0000h ffffh external program memory external program memory 2000h ffffh 0000h 01fffh on-chip program memory extended microcontroller mode microcontroller modes 0000h 01fffh 2000h fe00h ffffh on-chip on-chip on-chip off-chip on-chip off-chip on-chip off-chip on-chip program space data space con?. bits test memory boot rom pic17c752 0000h ffffh external program memory external program memory ffffh 0000h 0000h 3fffh 4000h fe00h ffffh off-chip on-chip off-chip on-chip off-chip on-chip con?. bits test memory boot rom program space data space on-chip on-chip 00h ffh 1ffh 120h on-chip 3fffh 4000h pic17c756 on-chip program memory on-chip program memory on-chip program memory 2ffh 220h 3ffh 320h 00h ffh 1ffh 120h 2ffh 220h 3ffh 320h 00h ffh 1ffh 120h 2ffh 220h 3ffh 320h 00h ffh 1ffh 120h 00h ffh 1ffh 120h 00h ffh 1ffh 120h
1997 microchip technology inc. preliminary ds30264a-page 41 pic17c75x 7.1.2 external memory interface when either microprocessor or extended microcontrol- ler mode is selected, portc, portd and porte are con?ured as the system bus. portc and portd are the multiplexed address/data bus and porte<2:0> is for the control signals. external components are needed to demultiplex the address and data. this can be done as shown in figure 7-4. the waveforms of address and data are shown in figure 7-3. for com- plete timings, please refer to the electrical speci?ation section. figure 7-3: external program memory access waveforms the system bus requires that there is no bus con?ct (minimal leakage), so the output value (address) will be capacitively held at the desired value. as the speed of the processor increases, external eprom memory with faster access time must be used. table 7-2 lists external memory speed requirements for a given pic17c75x device frequency. q3 q1 q2 q4 q3 q1 q2 q4 ad <15:0> ale oe wr '1' read cycle write cycle address out data in address out data out q1 in extended microcontroller mode, when the device is executing out of internal memory, the control signals will continue to be active. that is, they indicate the action that is occurring in the internal memory. the external memory access is ignored. this following selection is for use with microchip eproms. for interfacing to other manufacturers mem- ory, please refer to the electrical speci?ations of the desired pic17c75x device, as well as the desired memory device to ensure compatibility. table 7-2: eprom memory access time ordering suffix pic17c75x oscillator frequency instruction cycle time (t cy ) eprom suf? pic17c752 pic17c756 8 mhz 500 ns -25 16 mhz 250 ns -15 20 mhz 200 ns -10 25 mhz 160 ns -70 33 mhz 121 ns (1) note 1: the access times for this requires the use of fast srams. figure 7-4: typical external program memory connection diagram ad7-ad0 pic17cxxx ad15-ad8 ale i/o (1) ad15-ad0 373 memory (msb) ax-a0 d7-d0 a15-a0 memory (lsb) ax-a0 d7-d0 373 138 (1) oe wr oe oe wr wr ce ce (2) (2) note 1: use of i/o pins is only required for paged memory. 2: this signal is unused for rom and eprom devices.
pic17c75x ds30264a-page 42 preliminary 1997 microchip technology inc. 7.2 data memory organization data memory is partitioned into two areas. the ?st is the general purpose registers (gpr) area, while the second is the special function registers (sfr) area. the sfrs control and give the status for the operation of the device. portions of data memory are banked, this occurs in both areas. the gpr area is banked to allow greater than 232 bytes of general purpose ram. banking requires the use of control bits for bank selec- tion. these control bits are located in the bank select register (bsr). if an access is made to the unbanked region, the bsr bits are ignored. figure 7-5 shows the data memory map organization. instructions movpf and movfp provide the means to move values from the peripheral area (?? to any loca- tion in the register file (??, and vice-versa. the de?i- tion of the ? range is from 0h to 1fh, while the ? range is 0h to ffh. the ? range has six more loca- tions than peripheral registers which can be used as general purpose registers. this can be useful in some applications where variables need to be copied to other locations in the general purpose ram (such as saving status information during an interrupt). the entire data memory can be accessed either directly or indirectly through ?e select registers fsr0 and fsr1 (section 7.4). indirect addressing uses the appropriate control bits of the bsr for accesses into the banked areas of data memory. the bsr is explained in greater detail in section 7.8. 7.2.1 general purpose register (gpr) all devices have some amount of gpr area. the gprs are 8-bits wide. when the gpr area is greater than 232, it must be banked to allow access to the additional memory space. all the pic17c75x devices have banked memory in the gpr area. to facilitate switching between these banks, the movlr bank instruction has been added to the instruction set. gprs are not initialized by a power-on reset and are unchanged on all other resets. 7.2.2 special function registers (sfr) the sfrs are used by the cpu and peripheral func- tions to control the operation of the device (figure 7-5). these registers are static ram. the sfrs can be classi?d into two sets, those asso- ciated with the ?ore function and those related to the peripheral functions. those registers related to the ?ore are described here, while those related to a peripheral feature are described in the section for each peripheral feature. the peripheral registers are in the banked portion of memory, while the core registers are in the unbanked region. to facilitate switching between the peripheral banks, the movlb bank instruction has been provided.
1997 microchip technology inc. preliminary ds30264a-page 43 pic17c75x figure 7-5: pic17c75x register file map addr unbanked 00h indf0 01h fsr0 02h pcl 03h pclath 04h alusta 05h t0sta 06h cpusta 07h intsta 08h indf1 09h fsr1 0ah wreg 0bh tmr0l 0ch tmr0h 0dh tblptrl 0eh tblptrh 0fh bsr bank 0 bank 1 (1) bank 2 (1) bank 3 (1) bank 4 (1) bank 5 (1) bank 6 (1) bank 7 (1) 10h porta ddrc tmr1 pw1dcl pir2 ddrf sspadd pw3dcl 11h ddrb portc tmr2 pw2dcl pie2 portf sspcon1 pw3dch 12h portb ddrd tmr3l pw1dch ddrg sspcon2 ca3l 13h rcsta1 portd tmr3h pw2dch rcsta2 portg sspstat ca3h 14h rcreg1 ddre pr1 ca2l rcreg2 adcon0 sspbuf ca4l 15h txsta1 porte pr2 ca2h txsta2 adcon1 ca4h 16h txreg1 pir1 pr3l/ca1l tcon1 txreg2 adresl tcon3 17h spbrg1 pie1 pr3h/ca1h tcon2 spbrg2 adresh unbanked 18h prodl 19h prodh 1ah 1fh general purpose ram bank 0 (2) bank 1 (2) bank 2 (2, 3) bank 3 (2, 3) 20h ffh general purpose ram general purpose ram general purpose ram general purpose ram note 1: sfr ?e locations 10h - 17h are banked. the lower nibble of the bsr speci?s the bank. all unbanked sfrs ignore the bank select register (bsr) bits. 2: general purpose registers (gpr) locations 20h - ffh, 120h - 1ffh, 220h - 2ffh, and 320h - 3ffh are banked. the upper nibble of the bsr speci?s this bank. all other gprs ignore the bank select register (bsr) bits. 3: these ram banks are not implemented on the pic17c752. reading any register in this bank reads ?s
pic17c75x ds30264a-page 44 preliminary 1997 microchip technology inc. table 7-3: special function registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (3) unbanked 00h indf0 uses contents of fsr0 to address data memory (not a physical register) ---- ---- ---- ---- 01h fsr0 indirect data memory address pointer 0 xxxx xxxx uuuu uuuu 02h pcl low order 8-bits of pc 0000 0000 0000 0000 03h (1) pclath holding register for upper 8-bits of pc 0000 0000 uuuu uuuu 04h alusta fs3 fs2 fs1 fs0 ov z dc c 1111 xxxx 1111 uuuu 05h t0sta intedg t0se t0cs t0ps3 t0ps2 t0ps1 t0ps0 0000 000- 0000 000- 06h (2) cpusta stkav glintd t o pd po r bo r --11 1100 --11 qquu 07h intsta peif t0ckif t0if intf peie t0ckie t0ie inte 0000 0000 0000 0000 08h indf1 uses contents of fsr1 to address data memory (not a physical register) ---- ---- ---- ---- 09h fsr1 indirect data memory address pointer 1 xxxx xxxx uuuu uuuu 0ah wreg working register xxxx xxxx uuuu uuuu 0bh tmr0l tmr0 register; low byte xxxx xxxx uuuu uuuu 0ch tmr0h tmr0 register; high byte xxxx xxxx uuuu uuuu 0dh tblptrl low byte of program memory table pointer 0000 0000 0000 0000 0eh tblptrh high byte of program memory table pointer 0000 0000 0000 0000 0fh bsr bank select register 0000 0000 0000 0000 bank 0 10h porta rbpu ra5/tx1/ ck1 ra4/rx1/ dt1 ra3/sdi/ sda ra2/ss / scl ra1/t0cki ra0/int 0-xx xxxx 0-uu uuuu 11h ddrb data direction register for portb 1111 1111 1111 1111 12h portb rb7/ sdo rb6/ sck rb5/ tclk3 rb4/ tclk12 rb3/ pwm2 rb2/ pwm1 rb1/ cap2 rb0/ cap1 xxxx xxxx uuuu uuuu 13h rcsta1 spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00u 14h rcreg1 serial port receive register xxxx xxxx uuuu uuuu 15h txsta1 csrc tx9 txen sync trmt tx9d 0000 --1x 0000 --1u 16h txreg1 serial port transmit register (for usart1) xxxx xxxx uuuu uuuu 17h spbrg1 baud rate generator register (for usart1) xxxx xxxx uuuu uuuu bank 1 10h ddrc data direction register for portc 1111 1111 1111 1111 11h portc rc7/ ad7 rc6/ ad6 rc5/ ad5 rc4/ ad4 rc3/ ad3 rc2/ ad2 rc1/ ad1 rc0/ ad0 xxxx xxxx uuuu uuuu 12h ddrd data direction register for portd 1111 1111 1111 1111 13h portd rd7/ ad15 rd6/ ad14 rd5/ ad13 rd4/ ad12 rd3/ ad11 rd2/ ad10 rd1/ ad9 rd0/ ad8 xxxx xxxx uuuu uuuu 14h ddre data direction register for porte ---- 1111 ---- 1111 15h porte re3/ cap4 re2/wr re1/oe re0/ale ---- xxxx ---- uuuu 16h pir1 rbif tmr3if tmr2if tmr1if ca2if ca1if tx1if rc1if x000 0010 u000 0010 17h pie1 rbie tmr3ie tmr2ie tmr1ie ca2ie ca1ie tx1ie rc1ie 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition. shaded cells are unimplemented, read as '0'. note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for pc<15:8> whose contents are updated from or transferred to the upper byte of the program counter. 2: the t o and pd status bits in cpusta are not affected by a mclr reset. 3: other (non power-up) resets include: external reset through mclr and watchdog timer reset.
1997 microchip technology inc. preliminary ds30264a-page 45 pic17c75x bank 2 10h tmr1 timer1s register xxxx xxxx uuuu uuuu 11h tmr2 timer2s register xxxx xxxx uuuu uuuu 12h tmr3l timer3s register; low byte xxxx xxxx uuuu uuuu 13h tmr3h timer3s register; high byte xxxx xxxx uuuu uuuu 14h pr1 timer1s period register xxxx xxxx uuuu uuuu 15h pr2 timer2s period register xxxx xxxx uuuu uuuu 16h pr3l/ca1l timer3s period register - low byte/capture1 register; low byte xxxx xxxx uuuu uuuu 17h pr3h/ca1h timer3s period register - high byte/capture1 register; high byte xxxx xxxx uuuu uuuu bank 3 10h pw1dcl dc1 dc0 xx-- ---- uu-- ---- 11h pw2dcl dc1 dc0 tm2pw2 xx0- ---- uu0- ---- 12h pw1dch dc9 dc8 dc7 dc6 dc5 dc4 dc3 dc2 xxxx xxxx uuuu uuuu 13h pw2dch dc9 dc8 dc7 dc6 dc5 dc4 dc3 dc2 xxxx xxxx uuuu uuuu 14h ca2l capture2 low byte xxxx xxxx uuuu uuuu 15h ca2h capture2 high byte xxxx xxxx uuuu uuuu 16h tcon1 ca2ed1 ca2ed0 ca1ed1 ca1ed0 t16 tmr3cs tmr2cs tmr1cs 0000 0000 0000 0000 17h tcon2 ca2ovf ca1ovf pwm2on pwm1on ca1/pr3 tmr3on tmr2on tmr1on 0000 0000 0000 0000 bank 4 : 10h pir2 sspif bclif adif ca4if ca3if tx2if rc2if 000- 0010 000- 0010 11h pie2 sspie bclie adie ca4ie ca3ie tx2ie rc2ie 000- 0000 000- 0000 12h unimplemented ---- ---- ---- ---- 13h rcsta2 spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00u 14h rcreg2 serial port receive register for usart2 xxxx xxxx uuuu uuuu 15h txsta2 csrc tx9 txen sync trmt tx9d 0000 --1x 0000 --1u 16h txreg2 serial port transmit register for usart2 xxxx xxxx uuuu uuuu 17h spbrg2 baud rate generator for usart2 xxxx xxxx uuuu uuuu bank 5 : 10h ddrf data direction register for portf 1111 1111 1111 1111 11h portf rf7/ an11 rf6/ an10 rf5/ an9 rf4/ an8 rf3/ an7 rf2/ an6 rf1/ an5 rf0/ an4 0000 0000 0000 0000 12h ddrg data direction register for portg 1111 1111 1111 1111 13h portg rg7/ tx2/ck2 rg6/ rx2/dt2 rg5/ pwm3 rg4/ cap3 rg3/ an0 rg2/ an1 rg1/ an2 rg0/ an3 xxxx 0000 uuuu 0000 14h adcon0 chs3 chs2 chs1 chs0 go/done adon 0000 -0-0 0000 -0-0 15h adcon1 adcs1 adcs0 adfm pcfg3 pcfg2 pcfg1 pcfg0 000- 0000 000- 0000 16h adresl a/d result register low byte xxxx xxxx uuuu uuuu 17h adresh a/d result register high byte xxxx xxxx uuuu uuuu table 7-3: special function registers (cont.?) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (3) legend: x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition. shaded cells are unimplemented, read as '0'. note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for pc<15:8> whose contents are updated from or transferred to the upper byte of the program counter. 2: the t o and pd status bits in cpusta are not affected by a mclr reset. 3: other (non power-up) resets include: external reset through mclr and watchdog timer reset.
pic17c75x ds30264a-page 46 preliminary 1997 microchip technology inc. bank 6 : 10h sspadd ssp address register in i 2 c slave mode. ssp baud rate reload register in i 2 c master mode. 0000 0000 0000 0000 11h sspcon1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 12h sspcon2 gcen akstat akdt aken rcen pen rsen sen 0000 0000 0000 0000 13h sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 14h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 15h unimplemented ---- ---- ---- ---- 16h unimplemented ---- ---- ---- ---- 17h unimplemented ---- ---- ---- ---- bank 7 : 10h pw3dcl dc1 dc0 tm2pw3 - - - - - xx0- ---- uu0- ---- 11h pw3dch dc9 dc8 dc7 dc6 dc5 dc4 dc3 dc2 xxxx xxxx uuuu uuuu 12h ca3l capture3 low byte xxxx xxxx uuuu uuuu 13h ca3h capture3 high byte xxxx xxxx uuuu uuuu 14h ca4l capture4 low byte xxxx xxxx uuuu uuuu 15h ca4h capture4 high byte xxxx xxxx uuuu uuuu 16h tcon3 ca4ovf ca3ovf ca4ed1 ca4ed0 ca3ed1 ca3ed0 pwm3on -000 0000 -000 0000 17h unimplemented ---- ---- ---- ---- unbanked 18h (5) prodl low byte of 16-bit product (8 x 8 hardware multiply) xxxx xxxx uuuu uuuu 19h (5) prodh high byte of 16-bit product (8 x 8 hardware multiply) xxxx xxxx uuuu uuuu table 7-3: special function registers (cont.?) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (3) legend: x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition. shaded cells are unimplemented, read as '0'. note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for pc<15:8> whose contents are updated from or transferred to the upper byte of the program counter. 2: the t o and pd status bits in cpusta are not affected by a mclr reset. 3: other (non power-up) resets include: external reset through mclr and watchdog timer reset.
1997 microchip technology inc. preliminary ds30264a-page 47 pic17c75x 7.2.2.1 alu status register (alusta) the alusta register contains the status bits of the arithmetic and logic unit and the mode control bits for the indirect addressing register. as with all the other registers, the alusta register can be the destination for any instruction. if the alusta register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. therefore, the result of an instruction with the alusta register as destination may be different than intended. for example, clrf alusta will clear the upper four bits and set the z bit. this leaves the alusta register as 0000u1uu (where u = unchanged). it is recommended, therefore, that only bcf , bsf , swapf and movwf instructions be used to alter the alusta register because these instructions do not affect any status bit. to see how other instructions affect the status bits, see the ?nstruction set sum- mary. the arithmetic and logic unit (alu) is capable of car- rying out arithmetic or logical operations on two oper- ands or a single operand. all single operand instructions operate either on the wreg register or the given file register. for two operand instructions, one of the operands is the wreg register and the other one is either a ?e register or an 8-bit immediate constant. note 3: the c and dc bits operate as a borro w and digit borro w bit, respectively, in sub- traction. see the sublw and subwf instructions for examples. note 4: the over?w bit will be set if the 2s com- plement result exceeds +127 or is less than -128. figure 7-6: alusta register (address: 04h, unbanked) r/w - 1 r/w - 1 r/w - 1 r/w - 1 r/w - x r/w - x r/w - x r/w - x fs3 fs2 fs1 fs0 ov z dc c r = readable bit w = writable bit -n = value at por reset (x = unknown) bit7 bit0 bit 7-6: fs3:fs2 : fsr1 mode select bits 00 = post auto-decrement fsr1 value 01 = post auto-increment fsr1 value 1x = fsr1 value does not change bit 5-4: fs1:fs0 : fsr0 mode select bits 00 = post auto-decrement fsr0 value 01 = post auto-increment fsr0 value 1x = fsr0 value does not change bit 3: ov : over?w bit this bit is used for signed arithmetic (2s complement). it indicates an over?w of the 7-bit magnitude, which causes the sign bit (bit7) to change state. 1 = over?w occurred for signed arithmetic, (in this arithmetic operation) 0 = no over?w occurred bit 2: z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the results of an arithmetic or logic operation is not zero bit 1: dc : digit carry/borro w bit for addwf and addlw instructions. 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result note: for borrow the polarity is reversed. bit 0: c : carry/borro w bit for addwf and addlw instructions. 1 = a carry-out from the most signi?ant bit of the result occurred note that a subtraction is executed by adding the twos complement of the second operand. for rotate ( rrcf , rlcf ) instructions, this bit is loaded with either the high or low order bit of the source register. 0 = no carry-out from the most signi?ant bit of the result note: for borrow the polarity is reversed.
pic17c75x ds30264a-page 48 preliminary 1997 microchip technology inc. 7.2.2.2 cpu status register (cpusta) the cpusta register contains the status and control bits for the cpu. this register has a bit that is used to globally enable/disable interrupts. if only a speci? interrupt is desired to be enabled/disabled, please refer to the interrupt status (intsta) register and the peripheral interrupt enable (pie) registers. the cpusta register also indicates if the stack is available and contains the power-down (pd ) and time-out (t o ) bits. the t o , pd , and stkav bits are not writable. these bits are set and cleared according to device logic. therefore, the result of an instruction with the cpusta register as destination may be different than intended. the por bit allows the differentiation between a power-on reset, external mclr reset, or a wdt reset. the bor bit indicates if a brown-out reset occured. note 1: the bor status bit is a don? care and is not necessarily predictable if the brown-out circuit is disabled (when the boden bit in the con?uration word is programmed). figure 7-7: cpusta register (address: 06h, unbanked) u - 0 u - 0 r - 1 r/w - 1 r - 1 r - 1 r/w - 0 r/w - 0 stkav glintd t o pd por bor r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7-6: unimplemented : read as '0' bit 5: stkav : stack available bit this bit indicates that the 4-bit stack pointer value is fh, or has rolled over from fh ? 0h (stack over?w). 1 = stack is available 0 = stack is full, or a stack over?w may have occurred (once this bit has been cleared by a stack over?w, only a device reset will set this bit) bit 4: glintd : global interrupt disable bit this bit disables all interrupts. when enabling interrupts, only the sources with their enable bits set can cause an interrupt. 1 = disable all interrupts 0 = enables all un-masked interrupts bit 3: t o : wdt time-out status bit 1 = after power-up or by a clrwdt instruction 0 = a watchdog timer time-out occurred bit 2: pd : power-down status bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 1: por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set by software after a power-on reset occurs) bit 0: bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set by software after a brown-out reset occurs)
1997 microchip technology inc. preliminary ds30264a-page 49 pic17c75x 7.2.2.3 tmr0 status/control register (t0sta) this register contains various control bits. bit7 (intedg) is used to control the edge upon which a sig- nal on the ra0/int pin will set the ra0/int interrupt ?g. the other bits con?ure the timer0 prescaler and clock source. figure 7-8: t0sta register (address: 05h, unbanked) r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 u - 0 intedg t0se t0cs t0ps3 t0ps2 t0ps1 t0ps0 r = readable bit w = writable bit u = unimplemented, reads as ? -n = value at por reset bit7 bit0 bit 7: intedg : ra0/int pin interrupt edge select bit this bit selects the edge upon which the interrupt is detected. 1 = rising edge of ra0/int pin generates interrupt 0 = falling edge of ra0/int pin generates interrupt bit 6: t0se : timer0 clock input edge select bit this bit selects the edge upon which tmr0 will increment. when t0cs = 0 (exter nal cloc k) 1 = rising edge of ra1/t0cki pin increments tmr0 and/or generates a t0ckif interrupt 0 = falling edge of ra1/t0cki pin increments tmr0 and/or generates a t0ckif interrupt when t0cs = 1 (inter nal cloc k) don? care bit 5: t0cs : timer0 clock source select bit this bit selects the clock source for timer0. 1 = internal instruction clock cycle (t cy ) 0 = external clock input on the t0cki pin bit 4-1: t0ps3:t0ps0 : timer0 prescale selection bits these bits select the prescale value for timer0. bit 0: unimplemented : read as '0' t0ps3:t0ps0 prescale value 0000 0001 0010 0011 0100 0101 0110 0111 1xxx 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
pic17c75x ds30264a-page 50 preliminary 1997 microchip technology inc. 7.3 stack operation pic17c75x devices have a 16 x 16-bit hardware stack (figure 7-1). the stack is not part of either the program or data memory space, and the stack pointer is neither readable nor writable. the pc (program counter) is ?ushed onto the stack when a call or lcall instruction is executed or an interrupt is acknowledged. the stack is ?oped in the event of a return , retlw , or a retfie instruction execution. pclath is not affected by a ?ush or a ?op operation. the stack operates as a circular buffer, with the stack pointer initialized to '0' after all resets. there is a stack available bit (stkav) to allow software to ensure that the stack has not over?wed. the stkav bit is set after a device reset. when the stack pointer equals fh, stkav is cleared. when the stack pointer rolls over from fh to 0h, the stkav bit will be held clear until a device reset. after the device is ?ushed sixteen times (without a ?op?, the seventeenth push overwrites the value from the ?st push. the eighteenth push overwrites the second push (and so on). note 1: there is not a status bit for stack under- ?w. the stkav bit can be used to detect the under?w which results in the stack pointer being at the top of stack. note 2: there are no instruction mnemonics called push or pop. these are actions that occur from the execution of the call , return , retlw , and retfie instruc- tions, or the vectoring to an interrupt vec- tor. note 3: after a reset, if a ?op operation occurs before a ?ush operation, the stkav bit will be cleared. this will appear as if the stack is full (under?w has occurred). if a ?ush operation occurs next (before another ?op?, the stkav bit will be locked clear. only a device reset will cause this bit to set. 7.4 indirect addressing indirect addressing is a mode of addressing data memory where the data memory address in the instruction is not ?ed. that is, the register that is to be read or written can be modi?d by the program. this can be useful for data tables in the data memory. figure 7-9 shows the operation of indirect addressing. this shows the moving of the value to the data mem- ory address speci?d by the value of the fsr register. example 7-1 shows the use of indirect addressing to clear ram in a minimum number of instructions. a similar concept could be used to move a de?ed num- ber of bytes (block) of data to the usart transmit reg- ister (txreg). the starting address of the block of data to be transmitted could easily be modi?d by the program. figure 7-9: indirect addressing opcode address file = indfx fsr instruction executed instruction fetched ram opcode file
1997 microchip technology inc. preliminary ds30264a-page 51 pic17c75x 7.4.1 indirect addressing registers the pic17c75x has four registers for indirect addressing. these registers are: indf0 and fsr0 indf1 and fsr1 registers indf0 and indf1 are not physically imple- mented. reading or writing to these registers activates indirect addressing, with the value in the correspond- ing fsr register being the address of the data. the fsr is an 8-bit register and allows addressing any- where in the 256-byte data memory address range. for banked memory, the bank of memory accessed is speci?d by the value in the bsr. if ?e indf0 (or indf1) itself is read indirectly via an fsr, all '0's are read (zero bit is set). similarly, if indf0 (or indf1) is written to indirectly, the operation will be equivalent to a nop, and the status bits are not affected. 7.4.2 indirect addressing operation the indirect addressing capability has been enhanced over that of the pic16cxx family. there are two con- trol bits associated with each fsr register. these two bits con?ure the fsr register to: auto-decrement the value (address) in the fsr after an indirect access auto-increment the value (address) in the fsr after an indirect access no change to the value (address) in the fsr after an indirect access these control bits are located in the alusta register. the fsr1 register is controlled by the fs3:fs2 bits and fsr0 is controlled by the fs1:fs0 bits. when using the auto-increment or auto-decrement features, the effect on the fsr is not re?cted in the alusta register. for example, if the indirect address causes the fsr to equal '0', the z bit will not be set. if the fsr register contains a value of 0h, an indirect read will read 0h (zero bit is set) while an indirect write will be equivalent to a nop (status bits are not affected). indirect addressing allows single cycle data transfers within the entire data space. this is possible with the use of the movpf and movfp instructions, where either 'p' or 'f' is speci?d as indf0 (or indf1). if the source or destination of the indirect address is in banked memory, the location accessed will be deter- mined by the value in the bsr. a simple program to clear ram from 20h - ffh is shown in example 7-1. example 7-1: indirect addressing 7.5 t able pointer (tblptrl and tblptrh) file registers tblptrl and tblptrh form a 16-bit pointer to address the 64k program memory space. the table pointer is used by instructions tablwt and tablrd . the tablrd and the tablwt instructions allow trans- fer of data between program and data space. the table pointer serves as the 16-bit address of the data word within the program memory. for a more complete description of these registers and the operation of table reads and table writes, see section 8.0. 7.6 t able latch (tbla th, tbla tl) the table latch (tblat) is a 16-bit register, with tblath and tblatl referring to the high and low bytes of the register. it is not mapped into data or pro- gram memory. the table latch is used as a temporary holding latch during data transfer between program and data memory (see tablrd , tablwt , tlrd and tlwt instruction descriptions). for a more complete description of these registers and the operation of table reads and table writes, see section 8.0. movlw 0x20 ; movwf fsr0 ; fsr0 = 20h bcf alusta, fs1 ; increment fsr bsf alusta, fs0 ; after access bcf alusta, c ; c = 0 movlw end_ram + 1 ; lp clrf indf0 ; addr(fsr) = 0 cpfseq fsr0 ; fsr0 = end_ram+1? goto lp ; no, clear next : ; yes, all ram is : ; cleared
pic17c75x ds30264a-page 52 preliminary 1997 microchip technology inc. 7.7 program counter module the program counter (pc) is a 16-bit register. pcl, the low byte of the pc, is mapped in the data memory. pcl is readable and writable just as is any other regis- ter. pch is the high byte of the pc and is not directly addressable. since pch is not mapped in data or pro- gram memory, an 8-bit register pclath (pc high latch) is used as a holding latch for the high byte of the pc. pclath is mapped into data memory. the user can read or write pch through pclath. the 16-bit wide pc is incremented after each instruc- tion fetch during q1 unless: modi?d by a goto , call , lcall , return , retlw , or retfie instruction modi?d by an interrupt response due to destination write to pcl by an instruction ?kips are equivalent to a forced nop cycle at the skipped address. figure 7-10 and figure 7-11 show the operation of the program counter for various situations. figure 7-10: program counter operation figure 7-11: program counter using the call and goto instructions internal data bus <8> pclath 8 8 8 pch pcl 8 15 0 7 5 4 0 12 8 7 0 87 pc<15:13> pclath opcode 5 3 8 pch pcl 13 15 using figure 7-10, the operations of the pc and pclath for different instructions are as follows: a) lcall instr uctions : an 8-bit destination address is provided in the instruction (opcode). pclath is unchanged. pclath ? pch opcode<7:0> ? pcl b) read instr uctions on pcl : any instruction that reads pcl. pcl ? data bus ? alu or destination pch ? pclath c) wr ite instr uctions on pcl : any instruction that writes to pcl. 8-bit data ? data bus ? pcl pclath ? pch d) read-modify-wr ite instr uctions on pcl: any instruction that does a read-write-modify operation on pcl, such as addwf pcl . read: pcl ? data bus ? alu write: 8-bit result ? data bus ? pcl pclath ? pch e) return instr uction: stack ? pc<15:0> using figure 7-11, the operation of the pc and pclath for goto and call instructions is as follows: call , goto instr uctions : a 13-bit destination address is provided in the instruction (opcode). opcode<12:0> ? pc<12:0> pc<15:13> ? pclath<7:5> opcode<12:8> ? pclath<4:0> the read-modify-write only affects the pcl with the result. pch is loaded with the value in the pclath. for example, addwf pcl will result in a jump within the current page. if pc = 03f0h, wreg = 30h and pclath = 03h before instruction, pc = 0320h after the instruction. to accomplish a true 16-bit computed jump, the user needs to compute the 16-bit destination address, write the high byte to pclath and then write the low value to pcl. the following pc related operations do not change pclath: a) lcall , retlw , and retfie instructions. b) interrupt vector is forced onto the pc. c) read-modify-write instructions on pcl (e.g. bsf pcl ).
1997 microchip technology inc. preliminary ds30264a-page 53 pic17c75x 7.8 bank select register (bsr) the bsr is used to switch between banks in the data memory area (figure 7-12). in the pic17c752, and pic17c756 devices, the entire byte is implemented. the lower nibble is used to select the peripheral regis- ter bank. the upper nibble is used to select the general purpose memory bank. all the special function registers (sfrs) are mapped into the data memory space. in order to accommodate the large number of registers, a banking scheme has been used. a segment of the sfrs, from address 10h to address 17h, is banked. the lower nibble of the bank select register (bsr) selects the currently active ?eripheral bank. effort has been made to group the peripheral registers of related functionality in one bank. however, it will still be necessary to switch from bank to bank in order to address all peripherals related to a single task. to assist this, a movlb bank instruction has been included in the instruction set. the need for a large general purpose memory space dictated a general purpose ram banking scheme. the upper nibble of the bsr selects the currently active general purpose ram bank. to assist this, a movlr bank instruction has been provided in the instruction set. if the currently selected bank is not implemented (such as bank 13), any read will read all '0's. any write is completed to the bit bucket and the alu status bits will be set/cleared as appropriate. note: registers in bank 15 in the special func- tion register area, are reserved for microchip use. reading of registers in this bank may cause random values to be read. figure 7-12: bsr operation 7430 10h 17h bsr 0 123 8 15 20h ffh (1) (2) bank 15 bank 8 bank 3 bank 2 bank 1 bank 0 01 2 bank 2 bank 1 bank 0 15 bank 15 sfr banks gpr banks address range note 1: only banks 0 through 7 are implemented. selection of an unimplemented bank is not recommended . bank 15 is reserved for microchip use, reading of registers in this bank may cause random values to be read. 2: bank 0 and bank 1 are implemented for the pic17c752, and banks 0 through 3 are implemented for the pic17c756. selection of an unimplemented bank is not recommended. 3 bank 3 4 bank 4 4 5 6 7 bank 7 bank 6 bank 5 bank 4 (peripheral) (ram)
pic17c75x ds30264a-page 54 preliminary 1997 microchip technology inc. notes:
1997 microchip technology inc. preliminary ds30264a-page 55 pic17c75x 8.0 table reads and table writes the pic17c75x has four instructions that allow the processor to move data from the data memory space to the program memory space, and vice versa. since the program memory space is 16-bits wide and the data memory space is 8-bits wide, two operations are required to move 16-bit values to/from the data mem- ory. the tlwt t,f and tablwt t,i,f instructions are used to write data from the data memory space to the program memory space. the tlrd t,f and tablrd t,i,f instructions are used to write data from the pro- gram memory space to the data memory space. the program memory can be internal or external. for the program memory access to be external, the device needs to be operating in extended microcontroller or microprocessor mode. figure 8-1 through figure 8-4 show the operation of these four instructions. figure 8-1: tlwt instruction operation table pointer table latch (16-bit) program memory data memory tblptrh tblptrl tablath tablatl f tlwt 1,f tlwt 0,f 1 note 1: 8-bit value, from register 'f', loaded into the high or low byte in tablat (16-bit). figure 8-2: tablwt instruction operation table pointer table latch (16-bit) program memory data memory tblptrh tblptrl tablath tablatl f tablwt 1,i,f tablwt 0,i,f 1 prog-mem (tblptr) 2 note 1: 8-bit value, from register 'f', loaded into the high or low byte in tablat (16-bit). 2: 16-bit tablat value written to address program memory (tblptr). 3: if ? = 1, then tblptr = tblptr + 1, if ? = 0, then tblptr is unchanged. 3 3
pic17c75x ds30264a-page 56 preliminary 1997 microchip technology inc. figure 8-3: tlrd instruction operation table pointer table latch (16-bit) program memory data memory tblptrh tblptrl tablath tablatl f tlrd 1,f tlrd 0,f 1 note 1: 8-bit value, from tablat (16-bit) high or low byte, loaded into register 'f'. figure 8-4: tablrd instruction operation table pointer table latch (16-bit) program memory data memory tblptrh tblptrl tablath tablatl f tablrd 1,i,f tablrd 0,i,f 1 prog-mem (tblptr) 2 note 1: 8-bit value, from tablat (16-bit) high or low byte, loaded into register 'f'. 2: 16-bit value at program memory (tblptr) loaded into tablat register. 3: if ? = 1, then tblptr = tblptr + 1, if ? = 0, then tblptr is unchanged. 3 3
1997 microchip technology inc. preliminary ds30264a-page 57 pic17c75x 8.1 t able w rites to internal memory a table write operation to internal memory causes a long write operation. the long write is necessary for programming the internal eprom. instruction execu- tion is halted while in a long write cycle. the long write will be terminated by any enabled interrupt. to ensure that the eprom location has been well programmed, a minimum programming time is required (see speci? cation #d114). having only one interrupt enabled to terminate the long write ensures that no unintentional interrupts will prematurely terminate the long write. the sequence of events for programming an internal program memory location should be: 1. disable all interrupt sources, except the source to terminate eprom program write. 2. raise mclr /v pp pin to the programming volt- age. 3. clear the wdt. 4. do the table write. the interrupt will terminate the long write. 5. verify the memory location (table read). note 1: programming requirements must be met. see timing speci?ation in electrical speci?ations for the desired device. violating these speci?ations (including temperature) may result in eprom locations that are not fully programmed and may lose their state over time. note 2: if the v pp requirement is not met, the table write is a 2 cycle write and the pro- gram memory is unchanged. 8.1.1 terminating long writes an interrupt source or reset are the only events that terminate a long write operation. terminating the long write from an interrupt source requires that the inter- rupt enable and ?g bits are set. the glintd bit only enables the vectoring to the interrupt address. if the t0cki, ra0/int, or tmr0 interrupt source is used to terminate the long write; the interrupt ?g, of the highest priority enabled interrupt, will terminate the long write and automatically be cleared. if a peripheral interrupt source is used to terminate the long write, the interrupt enable and ?g bits must be set. the interrupt ?g will not be automatically cleared upon the vectoring to the interrupt vector address. the glintd bit determines whether the program will branch to the interrupt vector when the long write is terminated. if glintd is clear, the program will vector, if glintd is set, the program will not vector to the interrupt address. note 1: if an interrupt is pending, the tablwt is aborted (an nop is executed). the highest priority pending interrupt, from the t0cki, ra0/int, or tmr0 sources that is enabled, has its ?g cleared. note 2: if the interrupt is not being used for the program write timing, the interrupt should be disabled. this will ensure that the interrupt is not lost, nor will it termi- nate the long write prematurely. table 8-1: interrupt - table write interaction interrupt source glintd enable bit flag bit action ra0/int, tmr0, t0cki 0 0 1 1 1 1 0 1 1 0 x 1 terminate long table write (to internal program memory), branch to interrupt vector (branch clears ?g bit). none none terminate table write, do not branch to interrupt vector (?g is automatically cleared). peripheral 0 0 1 1 1 1 0 1 1 0 x 1 terminate table write, branch to interrupt vector. none none terminate table write, do not branch to interrupt vector (?g remains set).
pic17c75x ds30264a-page 58 preliminary 1997 microchip technology inc. 8.2 t able w rites to e xternal memory table writes to external memory are always two-cycle instructions. the second cycle writes the data to the external memory location. the sequence of events for an external memory write are the same for an internal write. note: if an interrupt is pending or occurs during the tablwt , the two cycle table write completes. the ra0/int, tmr0, or t0cki interrupt ?g is automatically cleared or the pending peripheral inter- rupt is acknowledged. 8.2.2 table write code the i operand of the tablwt instruction can specify that the value in the 16-bit tblptr register is auto- matically incremented (for the next write). in example 8-1, the tblptr register is not automatically incremented. example 8-1: table write clrwdt ; clear wdt movlw high (tbl_addr) ; load the table movwf tblptrh ; address movlw low (tbl_addr) ; movwf tblptrl ; movlw high (data) ; load hi byte tlwt 1, wreg ; in tablath movlw low (data) ; load lo byte tablwt 0,0,wreg ; in tablath ; and write to ; program memory ; (ext. sram) figure 8-5: tablwt write timing (external memory) q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 ad15:ad0 instruction fetched instruction executed ale oe wr tablwt inst (pc+1) inst (pc-1) tablwt cycle1 tablwt cycle2 inst (pc+2) data write cycle '1' pc pc+1 tbl pc+2 data out inst (pc+1) note: if external write, and glintd = '1', and enable bit = '1', then when '1' ? flag bit, do table write. the highest pending interrupt is cleared.
1997 microchip technology inc. preliminary ds30264a-page 59 pic17c75x figure 8-6: consecutive tablwt write timing (external memory) q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 ad15:ad0 instruction fetched instruction executed ale oe wr pc tablwt1 tablwt2 inst (pc+2) inst (pc-1) tablwt1 cycle1 tablwt1 cycle2 tablwt2 cycle1 tablwt2 cycle2 data write cycle data write cycle inst (pc+3) pc+1 tbl1 pc+2 tbl2 pc+3 data out 1 data out 2 inst (pc+2)
pic17c75x ds30264a-page 60 preliminary 1997 microchip technology inc. 8.3 t able reads the table read allows the program memory to be read. this allows constants to be stored in the program memory space, and retrieved into data memory when needed. example 8-2 reads the 16-bit value at pro- gram memory address tblptr. after the dummy byte has been read from the tablath, the tablath is loaded with the 16-bit data from program memory address tblptr + 1. the ?st read loads the data into the latch, and can be considered a dummy read (unknown data loaded into 'f'). indf0 should be con- ?ured for either auto-increment or auto-decrement. example 8-2: table read movlw high (tbl_addr) ; load the table movwf tblptrh ; address movlw low (tbl_addr) ; movwf tblptrl ; tablrd 0,0,dummy ; dummy read, ; updates tablath tlrd 1, indf0 ; read hi byte ; of tablath tablrd 0,1,indf0 ; read lo byte ; of tablath and ; update tablath figure 8-7: tablrd timing figure 8-8: tablrd timing (consecutive tablrd instructions) q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 ad15:ad0 instruction fetched instruction executed ale oe wr tablrd inst (pc+1) inst (pc+2) inst (pc-1) tablrd cycle1 tablrd cycle2 inst (pc+1) data read cycle pc pc+1 tbl data in pc+2 '1' q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 ad15:ad0 instruction fetched instruction executed tablrd1 tablrd2 inst (pc+2) inst (pc+3) inst (pc+2) ale oe wr inst (pc-1) tablrd1 cycle1 tablrd1 cycle2 tablrd2 cycle1 tablrd2 cycle2 data read cycle data read cycle '1' pc pc+1 pc+2 pc+3 tbl1 data in 1 tbl2 data in 2
1997 microchip technology inc. preliminary ds30264a-page 61 pic17c75x 9.0 hardware multiplier all pic17c75x devices have an 8 x 8 hardware multi- plier included in the alu of the device. by making the multiply a hardware operation, it completes in a single instruction cycle. this is an unsigned multiply that gives a 16-bit result. the result is stored into the 16-bit product register (prodh:prodl). the multiplier does not affect any ?gs in the alusta register. making the 8 x 8 multiplier execute in a single cycle gives the following advantages: higher computational throughput reduces code size requirements for multiply algo- rithms the performance increase allows the device to be used in applications previously reserved for digital signal processors. table 9-1 shows a performance comparison between pic17cxxx devices using the single cycle hardware multiply, and performing the same function without the hardware multiply. example 9-1 shows the sequence to do an 8 x 8 unsigned multiply. only one instruction is required when one argument of the multiply is already loaded in the wreg register. example 9-2 shows the sequence to do an 8 x 8 signed multiply. to account for the sign bits of the arguments, each arguments most signi?ant bit (msb) is tested and the appropriate subtractions are done. example 9-1: 8 x 8 unsigned multiply routine example 9-2: 8 x 8 signed multiply routine movfp arg1, wreg ; mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl movfp arg1, wreg mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl btfsc arg2, sb ; test sign bit subwf prodh, f ; prodh = prodh ; - arg1 movfp arg2, wreg btfsc arg1, sb ; test sign bit subwf prodh, f ; prodh = prodh ; - arg2 table 9-1: performance comparison routine multiply method program memory (words) cycles (max) time @ 33 mhz 8 x 8 unsigned without hardware multiply 13 69 8.364 m s hardware multiply 1 1 0.121 m s 8 x 8 signed without hardware multiply hardware multiply 6 6 0.727 m s 16 x 16 unsigned without hardware multiply 21 242 29.333 m s hardware multiply 24 24 2.91 m s 16 x 16 signed without hardware multiply 52 254 30.788 m s hardware multiply 36 36 4.36 m s
pic17c75x ds30264a-page 62 preliminary 1997 microchip technology inc. example 9-3 shows the sequence to do a 16 x 16 unsigned multiply. equation 9-1 shows the algorithm that is used. the 32-bit result is stored in 4 registers res3:res0. equation 9-1: 16 x 16 unsigned multiplication algorithm res3:res0 = arg1h:arg1l arg2h:arg2l = (arg1h arg2h 2 16 )+ (arg1h arg2l 2 8 )+ (arg1l arg2h 2 8 )+ (arg1l arg2l) example 9-3: 16 x 16 unsigned multiply routine movfp arg1l, wreg mulwf arg2l ; arg1l * arg2l -> ; prodh:prodl movpf prodh, res1 ; movpf prodl, res0 ; ; movfp arg1h, wreg mulwf arg2h ; arg1h * arg2h -> ; prodh:prodl movpf prodh, res3 ; movpf prodl, res2 ; ; movfp arg1l, wreg mulwf arg2h ; arg1l * arg2h -> ; prodh:prodl movfp prodl, wreg ; addwf res1, f ; add cross movfp prodh, wreg ; products addwfc res2, f ; clrf wreg, f ; addwfc res3, f ; ; movfp arg1h, wreg ; mulwf arg2l ; arg1h * arg2l -> ; prodh:prodl movfp prodl, wreg ; addwf res1, f ; add cross movfp prodh, wreg ; products addwfc res2, f ; clrf wreg, f ; addwfc res3, f ;
1997 microchip technology inc. preliminary ds30264a-page 63 pic17c75x example 9-4 shows the sequence to do an 16 x 16 signed multiply. equation 9-2 shows the algorithm used. the 32-bit result is stored in four registers res3:res0. to account for the sign bits of the argu- ments, each argument pairs most signi?ant bit (msb) is tested and the appropriate subtractions are done. equation 9-2: 16 x 16 signed multiplication algorithm res3:res0 = arg1h:arg1l arg2h:arg2l = (arg1h arg2h 2 16 )+ (arg1h arg2l 2 8 )+ (arg1l arg2h 2 8 )+ (arg1l arg2l) + (-1 arg2h<7> arg1h:arg1l 2 16 )+ (-1 arg1h<7> arg2h:arg2l 2 16 ) example 9-4: 16 x 16 signed multiply routine movfp arg1l, wreg mulwf arg2l ; arg1l * arg2l -> ; prodh:prodl movpf prodh, res1 ; movpf prodl, res0 ; ; movfp arg1h, wreg mulwf arg2h ; arg1h * arg2h -> ; prodh:prodl movpf prodh, res3 ; movpf prodl, res2 ; ; movfp arg1l, wreg mulwf arg2h ; arg1l * arg2h -> ; prodh:prodl movfp prodl, wreg ; addwf res1, f ; add cross movfp prodh, wreg ; products addwfc res2, f ; clrf wreg, f ; addwfc res3, f ; ; movfp arg1h, wreg ; mulwf arg2l ; arg1h * arg2l -> ; prodh:prodl movfp prodl, wreg ; addwf res1, f ; add cross movfp prodh, wreg ; products addwfc res2, f ; clrf wreg, f ; addwfc res3, f ; ; btfss arg2h, 7 ; arg2h:arg2l neg? goto sign_arg1 ; no, check arg1 movfp arg1l, wreg ; subwf res2 ; movfp arg1h, wreg ; subwfb res3 ; sign_arg1 btfss arg1h, 7 ; arg1h:arg1l neg? goto cont_code ; no, done movfp arg2l, wreg ; subwf res2 ; movfp arg2h, wreg ; subwfb res3 ; cont_code :
pic17c75x ds30264a-page 64 preliminary 1997 microchip technology inc. notes:
1997 microchip technology inc. preliminary ds30264a-page 65 pic17c75x 10.0 i/o ports pic17c75x devices have seven i/o ports, porta through portg. portb through portg have a cor- responding data direction register (ddr), which is used to con?ure the port pins as inputs or outputs. these seven ports are made up of 50 i/o pins. some of these ports pins are multiplexed with alternate func- tions. portc, portd, and porte are multiplexed with the system bus. these pins are con?ured as the system bus when the devices con?uration bits are selected to microprocessor or extended microcontroller modes. in the two other microcontroller modes, these pins are general purpose i/o. porta, portb, porte<3>, portf and portg are multiplexed with the peripheral features of the device. these peripheral features are: timer modules capture modules pwm modules usart/sci modules ssp module a/d module external interrupt pin when some of these peripheral modules are turned on, the port pin will automatically con?ure to the alternate function. the modules that do this are: pwm module ssp module usart/sci module when a pin is automatically con?ured as an output by a peripheral module, the pins data direction (ddr) bit is unknown. after disabling the peripheral module, the user should re-initialize the ddr bit to the desired con- ?uration. the other peripheral modules (which require an input) must have their data direction bit con?ured appropri- ately. note: a pin that is a peripheral input, can be con- ?ured as an output (ddrx is cleared). the peripheral events will be determined by the action output on the port pin. 10.1 port a register porta is a 6-bit wide latch. porta does not have a corresponding data direction register (ddr). reading porta reads the status of the pins. the ra1 pin is multiplexed with tmr0 clock input, ra2 and ra3 are multiplexed with the ssp functions, and ra4 and ra5 are multiplexed with the usart1 func- tions. the control of ra2, ra3, ra4 and ra5 as out- puts are automatically con?ured by the their multiplexed peripheral module. 10.1.1 using ra2, ra3 as outputs the ra2 and ra3 pins are open drain outputs. to use the ra2 and/or the ra3 pin(s) as output(s), simply write to the porta register the desired value. a '0' will cause the pin to drive low, while a '1' will cause the pin to ?at (hi-impedance). an external pull-up resistor should be used to pull the pin high. writes to the ra2 and ra3 pins will not affect the other porta pins. figure 10-1: ra0 and ra1 block diagram note: when using the ra2 or ra3 pin(s) as out- put(s), read-modify-write instructions (such as bcf , bsf , btg ) on porta are not rec- ommended. such operations read the port pins, do the desired operation, and then write this value to the data latch. this may inadvertently cause the ra2 or ra3 pins to switch from input to output (or vice-versa). to avoid this possibility use a shadow reg- ister for porta. do the bit operations on this shadow register and then move it to porta. note: i/o pins have protection diodes to v dd and v ss . data b u s rd_porta (q2)
pic17c75x ds30264a-page 66 preliminary 1997 microchip technology inc. example 10-1 shows an instruction sequence to initial- ize porta. the bank select register (bsr) must be selected to bank 0 for the port to be initialized. the fol- lowing example uses the movlb instruction to load the bsr register for bank selection. example 10-1: initializing porta figure 10-2: ra2 block diagram movlb 0 ; select bank 0 movlw 0xf3 ; movpf porta ; initialize porta ; ra<3:2> are output low ; ra<5:4> and ra<1:0> ; are inputs ; (outputs floating) note: i/o pin has protection diodes to v ss . data bus wr_porta (q4) qd q ck rd_porta (q2) q d en peripheral data in 1 0 i 2 c mode enable s cl out figure 10-3: ra3 block diagram figure 10-4: ra4 and ra5 block diagram note: i/o pin has protection diodes to v ss . data bus wr_porta (q4) qd q ck rd_porta (q2) q d en peripheral data in sd a out ssp mode ? note: i/o pins have protection diodes to v dd and v ss . data bus rd_porta (q2) serial port output signals serial port input signal oe = spen,sync,txen, cren , sren for ra4 oe = spen (sync +sync,csrc ) for ra5
1997 microchip technology inc. preliminary ds30264a-page 67 pic17c75x table 10-1: porta functions table 10-2: registers/bits associated with porta name bit0 buffer type function ra0/int bit0 st input or external interrupt input. ra1/t0cki bit1 st input or clock input to the tmr0 timer/counter, and/or an external interrupt input. ra2/ss /scl bit2 st input/output or slave select input for the spi or clock input for the i 2 c bus. output is open drain type. ra3/sdi/sda bit3 st input/output or data input for the spi or data for the i 2 c bus. output is open drain type. ra4/rx1/dt1 bit4 st input/output or usart1 asynchronous receive or usart1 synchronous data. ra5/tx1/ck1 bit5 st input/output or usart1 asynchronous transmit or usart1 synchronous clock. rbpu bit7 control bit for portb weak pull-ups. legend: st = schmitt trigger input. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (note1) 10h, bank 0 porta rbpu ra5/ tx1/ck1 ra4/ rx1/dt1 ra3/ sdi/sda ra2/ ss /scl ra1/t0cki ra0/int 0-xx xxxx 0-uu uuuu 05h, unbanked t0sta intedg t0se t0cs ps3 ps2 ps1 ps0 0000 000- 0000 000- 13h, bank 0 rcsta1 spen rc9 sren cren ferr oerr rc9d 0000 -00x 0000 -00u 15h, bank 0 txsta1 csrc tx9 txen sync trmt tx9d 0000 --1x 0000 --1u legend: x = unknown, u = unchanged, - = unimplemented reads as '0'. shaded cells are not used by porta. note 1: other (non power-up) resets include: external reset through mclr and the watchdog timer reset.
pic17c75x ds30264a-page 68 preliminary 1997 microchip technology inc. 10.2 portb and ddrb registers portb is an 8-bit wide bi-directional port. the corre- sponding data direction register is ddrb. a '1' in ddrb con?ures the corresponding port pin as an input. a '0' in the ddrb register con?ures the corre- sponding port pin as an output. reading portb reads the status of the pins, whereas writing to it will write to the port latch. each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is done by clearing the rbpu (porta<7>) bit. the weak pull-up is automatically turned off when the port pin is con?ured as an output. the pull-ups are enabled on any reset. portb also has an interrupt on change feature. only pins con?ured as inputs can cause this interrupt to occur (i.e. any rb7:rb0 pin con?ured as an output is excluded from the interrupt on change comparison). the input pins (of rb7:rb0) are compared with the value in the portb data latch. the ?ismatch outputs of rb7:rb0 are or?d together to set the portb interrupt flag bit, rbif (pir1<7>). this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the inter- rupt by: a) read-write portb (such as; movpf portb, portb ). this will end mismatch condition. b) then, clear the rbif bit. a mismatch condition will continue to set the rbif bit. reading then writing portb will end the mismatch condition, and allow the rbif bit to be cleared. this interrupt on mismatch feature, together with soft- ware con?urable pull-ups on this port, allows easy interface to a keypad and make it possible for wake-up on key-depression. for an example, refer to applica- tion note an552, ?mplementing wake-up on key- stroke. the interrupt on change feature is recommended for wake-up on operations where portb is only used for the interrupt on change feature and key depression operations. figure 10-5: block diagram of rb5:rb4 and rb1:rb0 port pins note: i/o pins have protection diodes to v dd and v ss . data bus q d ck q d ck weak pull-up port input latch port data oe wr_portb (q4) wr_ddrb (q4) rd_portb (q2) rd_ddrb (q2) rbif rbpu match signal from other port pins (porta<7>) peripheral data in
1997 microchip technology inc. preliminary ds30264a-page 69 pic17c75x example 10-2 shows an instruction sequence to initial- ize portb. the bank select register (bsr) must be selected to bank 0 for the port to be initialized. the fol- lowing example uses the movlb instruction to load the bsr register for bank selection. example 10-2: initializing portb movlb 0 ; select bank 0 clrf portb ; initialize portb by clearing ; output data latches movlw 0xcf ; value used to initialize ; data direction movwf ddrb ; set rb<3:0> as inputs ; rb<5:4> as outputs ; rb<7:6> as inputs figure 10-6: block diagram of rb3:rb2 port pins note: i/o pins have protection diodes to v dd and vss. data bus q d ck q d ck r weak pull-up port input latch port data oe peripheral_enable peripheral_output wr_portb (q4) wr_ddrb (q4) rd_portb (q2) rd_ddrb (q2) rbif rbpu match signal from other port pins (porta<7>) peripheral data in
pic17c75x ds30264a-page 70 preliminary 1997 microchip technology inc. figure 10-7: block diagram of rb6 port pin figure 10-8: block diagram of rb7 port pin note: i/o pins have protection diodes to v dd and vss. data bus q d ck q d ck weak pull-up port data oe spi output enable spi output wr_portb (q4) wr_ddrb (q4) rd_portb (q2) rd_ddrb (q2) rbif rbpu match signal from other port pins (porta<7>) peripheral data in q d en p n q 0 1 note: i/o pins have protection diodes to v dd and vss. data bus q d ck q d ck weak pull-up port data oe spi output enable spi output wr_portb (q4) wr_ddrb (q4) rd_portb (q2) rd_ddrb (q2) rbif rbpu match signal from other port pins (porta<7>) peripheral data in en q d en p n q 0 1 ss output disable
1997 microchip technology inc. preliminary ds30264a-page 71 pic17c75x table 10-3: portb functions table 10-4: registers/bits associated with portb name bit buffer type function rb0/cap1 bit0 st input/output or the capture1 input pin. software programmable weak pull-up and interrupt on change features. rb1/cap2 bit1 st input/output or the capture2 input pin. software programmable weak pull-up and interrupt on change features. rb2/pwm1 bit2 st input/output or the pwm1 output pin. software programmable weak pull-up and interrupt on change features. rb3/pwm2 bit3 st input/output or the pwm2 output pin. software programmable weak pull-up and interrupt on change features. rb4/tclk12 bit4 st input/output or the external clock input to timer1 and timer2. software programmable weak pull-up and interrupt on change features. rb5/tclk3 bit5 st input/output or the external clock input to timer3. software programmable weak pull-up and interrupt on change features. rb6/sck bit6 st input/output or the master/slave clock for the spi. software programmable weak pull-up and interrupt on change features. rb7/sdo bit7 st input/output or data output for the spi. software programmable weak pull-up and interrupt on change features. legend: st = schmitt trigger input. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (note1) 12h portb rb7/ sdo rb6/ sck rb5/ tclk3 rb4/ tclk12 rb3/ pwm2 rb2/ pwm1 rb1/ cap2 rb0/ cap1 xxxx xxxx uuuu uuuu 11h, bank 0 ddrb data direction register for portb 1111 1111 1111 1111 10h, bank 0 porta rbpu ra5/ tx1/ck1 ra4/ rx1/dt1 ra3/ sdi/sda ra2/ ss /scl ra1/t0cki ra0/int 0-xx xxxx 0-uu uuuu 06h, unbanked cpusta stkav glintd t o pd por bor --11 1100 --11 qq11 07h, unbanked intsta peif t0ckif t0if intf peie t0ckie t0ie inte 0000 0000 0000 0000 16h, bank 1 pir1 rbif tmr3if tmr2if tmr1if ca2if ca1if tx1if rc1if 0000 0010 0000 0010 17h, bank 1 pie1 rbie tmr3ie tmr2ie tmr1ie ca2ie ca1ie tx1ie rc1ie 0000 0000 0000 0000 16h, bank 3 tcon1 ca2ed1 ca2ed0 ca1ed1 ca1ed0 t16 tmr3cs tmr2cs tmr1cs 0000 0000 0000 0000 17h, bank 3 tcon2 ca2ovf ca1ovf pwm2on pwm1on ca1/pr3 tmr3on tmr2on tmr1on 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends on condition. shaded cells are not used by portb. note 1: other (non power-up) resets include: external reset through mclr and the watchdog timer reset.
pic17c75x ds30264a-page 72 preliminary 1997 microchip technology inc. 10.3 portc and ddrc registers portc is an 8-bit bi-directional port. the correspond- ing data direction register is ddrc. a '1' in ddrc con- ?ures the corresponding port pin as an input. a '0' in the ddrc register con?ures the corresponding port pin as an output. reading portc reads the status of the pins, whereas writing to it will write to the port latch. portc is multiplexed with the system bus. when operating as the system bus, portc is the low order byte of the address/data bus (ad7:ad0). the timing for the system bus is shown in the electrical characteris- tics section. note: this port is con?ured as the system bus when the devices con?uration bits are selected to microprocessor or extended microcontroller modes. in the two other microcontroller modes, this port is a gen- eral purpose i/o. example 10-3 shows an instruction sequence to initial- ize portc. the bank select register (bsr) must be selected to bank 1 for the port to be initialized. the fol- lowing example uses the movlb instruction to load the bsr register for bank selection. example 10-3: initializing portc movlb 1 ; select bank 1 clrf portc ; initialize portc data ; latches before setting ; the data direction register movlw 0xcf ; value used to initialize ; data direction movwf ddrc ; set rc<3:0> as inputs ; rc<5:4> as outputs ; rc<7:6> as inputs figure 10-9: block diagram of rc7:rc0 port pins note: i/o pins have protection diodes to v dd and vss. q d ck ttl 0 1 q d ck r s input buffer port data to d_bus ? ir instruction read data bus rd_portc wr_portc rd_ddrc wr_ddrc ex_en data/addr_out drv_sys sys bus control
1997 microchip technology inc. preliminary ds30264a-page 73 pic17c75x table 10-5: portc functions table 10-6: registers/bits associated with portc name bit buffer type function rc0/ad0 bit0 ttl input/output or system bus address/data pin. rc1/ad1 bit1 ttl input/output or system bus address/data pin. rc2/ad2 bit2 ttl input/output or system bus address/data pin. rc3/ad3 bit3 ttl input/output or system bus address/data pin. rc4/ad4 bit4 ttl input/output or system bus address/data pin. rc5/ad5 bit5 ttl input/output or system bus address/data pin. rc6/ad6 bit6 ttl input/output or system bus address/data pin. rc7/ad7 bit7 ttl input/output or system bus address/data pin. legend: ttl = ttl input. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (note1) 11h, bank 1 portc rc7/ ad7 rc6/ ad6 rc5/ ad5 rc4/ ad4 rc3/ ad3 rc2/ ad2 rc1/ ad1 rc0/ ad0 xxxx xxxx uuuu uuuu 10h, bank 1 ddrc data direction register for portc 1111 1111 1111 1111 legend: x = unknown, u = unchanged. note 1: other (non power-up) resets include: external reset through mclr and the watchdog timer reset.
pic17c75x ds30264a-page 74 preliminary 1997 microchip technology inc. 10.4 portd and ddrd registers portd is an 8-bit bi-directional port. the correspond- ing data direction register is ddrd. a '1' in ddrd con- ?ures the corresponding port pin as an input. a '0' in the ddrd register con?ures the corresponding port pin as an output. reading portd reads the status of the pins, whereas writing to it will write to the port latch. portd is multiplexed with the system bus. when operating as the system bus, portd is the high order byte of the address/data bus (ad15:ad8). the timing for the system bus is shown in the electrical character- istics section. note: this port is con?ured as the system bus when the devices con?uration bits are selected to microprocessor or extended microcontroller modes. in the two other microcontroller modes, this port is a gen- eral purpose i/o. example 10-4 shows an instruction sequence to initial- ize portd. the bank select register (bsr) must be selected to bank 1 for the port to be initialized. the fol- lowing example uses the movlb instruction to load the bsr register for bank selection. example 10-4: initializing portd movlb 1 ; select bank 1 clrf portd ; initialize portd data ; latches before setting ; the data direction register movlw 0xcf ; value used to initialize ; data direction movwf ddrd ; set rd<3:0> as inputs ; rd<5:4> as outputs ; rd<7:6> as inputs figure 10-10: block diagram of rd7:rd0 port pins (in i/o port mode) note: i/o pins have protection diodes to v dd and vss. q d ck ttl 0 1 q d ck r s input buffer port data to d_bus ? ir instruction read data bus rd_portd wr_portd rd_ddrd wr_ddrd ex_en data/addr_out drv_sys sys bus control
1997 microchip technology inc. preliminary ds30264a-page 75 pic17c75x table 10-7: portd functions table 10-8: registers/bits associated with portd name bit buffer type function rd0/ad8 bit0 ttl input/output or system bus address/data pin. rd1/ad9 bit1 ttl input/output or system bus address/data pin. rd2/ad10 bit2 ttl input/output or system bus address/data pin. rd3/ad11 bit3 ttl input/output or system bus address/data pin. rd4/ad12 bit4 ttl input/output or system bus address/data pin. rd5/ad13 bit5 ttl input/output or system bus address/data pin. rd6/ad14 bit6 ttl input/output or system bus address/data pin. rd7/ad15 bit7 ttl input/output or system bus address/data pin. legend: ttl = ttl input. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (note1) 13h, bank 1 portd rd7/ ad15 rd6/ ad14 rd5/ ad13 rd4/ ad12 rd3/ ad11 rd2/ ad10 rd1/ ad9 rd0/ ad8 xxxx xxxx uuuu uuuu 12h, bank 1 ddrd data direction register for portd 1111 1111 1111 1111 legend: x = unknown, u = unchanged. note 1: other (non power-up) resets include: external reset through mclr and the watchdog timer reset.
pic17c75x ds30264a-page 76 preliminary 1997 microchip technology inc. 10.5 porte and ddre register porte is a 4-bit bi-directional port. the corresponding data direction register is ddre. a '1' in ddre con?- ures the corresponding port pin as an input. a '0' in the ddre register con?ures the corresponding port pin as an output. reading porte reads the status of the pins, whereas writing to it will write to the port latch. porte is multiplexed with the system bus. when operating as the system bus, porte contains the con- trol signals for the address/data bus (ad15:ad0). these control signals are address latch enable (ale), output enable (oe ), and write (wr ). the control sig- nals oe and wr are active low signals. the timing for the system bus is shown in the electrical characteris- tics section. note: three pins of this port are con?ured as the system bus when the devices con?u- ration bits are selected to microprocessor or extended microcontroller modes. the other pin is a general purpose i/o or capture4 pin. in the two other microcon- troller modes, re2:re0 are general pur- pose i/o pins. example 10-5 shows an instruction sequence to initial- ize porte. the bank select register (bsr) must be selected to bank 1 for the port to be initialized. the fol- lowing example uses the movlb instruction to load the bsr register for bank selection. example 10-5: initializing porte movlb 1 ; select bank 1 clrf porte ; initialize porte data ; latches before setting ; the data direction ; register movlw 0x03 ; value used to initialize ; data direction movwf ddre ; set re<1:0> as inputs ; re<3:2> as outputs ; re<7:4> are always ; read as '0' figure 10-11: block diagram of re2:re0 (in i/o port mode) note: i/o pins have protection diodes to v dd and vss. q d ck ttl 0 1 q d ck r s input buffer port data data bus rd_porte wr_porte rd_ddre wr_ddre ex_en cntl drv_sys sys bus control
1997 microchip technology inc. preliminary ds30264a-page 77 pic17c75x figure 10-12: block diagram of re3/cap4 port pin table 10-9: porte functions table 10-10: registers/bits associated with porte name bit buffer type function re0/ale bit0 ttl input/output or system bus address latch enable (ale) control pin. re1/oe bit1 ttl input/output or system bus output enable (oe ) control pin. re2/wr bit2 ttl input/output or system bus write (wr ) control pin. re3/cap4 bit3 st input/output or capture4 input pin legend: ttl = ttl input. st = schmitt trigger input address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on, por, bor value on all other resets (note1) 15h, bank 1 porte re3/cap4 re2/wr re1/oe re0/ale ---- xxxx ---- uuuu 14h, bank 1 ddre data direction register for porte ---- 1111 ---- 1111 14h, bank 7 ca4l capture4 low byte xxxx xxxx uuuu uuuu 15h, bank 7 ca4h capture4 high byte xxxx xxxx uuuu uuuu 16h, bank 7 tcon3 ca4ovf ca3ovf ca4ed1 ca4ed0 ca3ed1 ca3ed0 pwm3on -000 0000 -000 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by porte. note 1: other (non power-up) resets include: external reset through mcl r and the watchdog timer reset. note: i/o pin has protection diodes to v dd and vss. d ck q d ck q s port data data bus rd_porte wr_porte rd_ddre wr_ddre en q d en p n q q peripheral in v dd
pic17c75x ds30264a-page 78 preliminary 1997 microchip technology inc. 10.6 portf and ddrf registers portf is an 8-bit wide bi-directional port. the corre- sponding data direction register is ddrf. a '1' in ddrf con?ures the corresponding port pin as an input. a '0' in the ddrf register con?ures the corresponding port pin as an output. reading portf reads the status of the pins, whereas writing to them will write to the respective port latch. all eight bits of portf are multiplexed with 8 of the 12 channels of the 10-bit a/d converter. upon reset the entire port is automatically con?ured as analog inputs, and must be con?ured in software to be a digital i/o. example 10-6 shows an instruction sequence to initial- ize portf. the bank select register (bsr) must be selected to bank 5 for the port to be initialized. the fol- lowing example uses the movlb instruction to load the bsr register for bank selection. example 10-6: initializing portf movlb 5 ; select bank 5 movlw 0x0e ; configure portf as movpf adcon1 ; digital clrf portf ; initialize portf data ; latches before setting ; the data direction ; register movlw 0x03 ; value used to initialize ; data direction movwf ddrf ; set rf<1:0> as inputs ; rf<7:2> as outputs figure 10-13: block diagram of rf7:rf0 data bus wr portf wr ddrf rd port data latch ddrf latch p v ss i/o pin pcfg3:pcfg0 q d q ck q d q ck en qd en n st input buffer v dd rd ddrf to other pads v an chs3:chs0 to other pads
1997 microchip technology inc. preliminary ds30264a-page 79 pic17c75x table 10-11: portf functions table 10-12: registers/bits associated with portf name bit buffer type function rf0/an4 bit0 st input/output or analog input 4 rf1/an5 bit1 st input/output or analog input 5 rf2/an6 bit2 st input/output or analog input 6 rf3/an7 bit3 st input/output or analog input 7 rf4/an8 bit4 st input/output or analog input 8 rf5/an9 bit5 st input/output or analog input 9 rf6/an10 bit6 st input/output or analog input 10 rf7/an11 bit7 st input/output or analog input 11 legend: st = schmitt trigger input. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on, por, bor value on all other resets (note1) 10h, bank 5 ddrf data direction register for portf 1111 1111 1111 1111 11h, bank 5 portf rf7/ an11 rf6/ an10 rf5/ an9 rf4/ an8 rf3/ an7 rf2/ an6 rf1/ an5 rf0/ an4 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by portf. note 1: other (non power-up) resets include: external reset through mclr and the watchdog timer reset.
pic17c75x ds30264a-page 80 preliminary 1997 microchip technology inc. 10.7 portg and ddrg registers portg is an 8-bit wide bi-directional port. the corre- sponding data direction register is ddrg. a '1' in ddrg con?ures the corresponding port pin as an input. a '0' in the ddrg register con?ures the corre- sponding port pin as an output. reading portg reads the status of the pins, whereas writing to them will write to the respective port latch. the lower four bits of portg are multiplexed with four of the 12 channels of the 10-bit a/d converter. the remaining bits of portg are multiplexed with peripheral output and inputs. rg4 is multiplexed with the cap3 input, rg5 is multiplexed with the pwm3 output, rg6 and rg7 are multiplexed with the usart2 functions. upon reset the entire port is automatically con?ured as analog inputs, and must be con?ured in software to be a digital i/o. example 10-7 shows the instruction sequence to initial- ize portg. the bank select register (bsr) must be selected to bank 5 for the port to be initialized. the fol- lowing example uses the movlb instruction to load the bsr register for bank selection. example 10-7: initializing portg movlb 5 ; select bank 5 movlw 0x0e ; configure portg as movpf adcon1 ; digital clrf portg ; initialize portg data ; latches before setting ; the data direction ; register movlw 0x03 ; value used to initialize ; data direction movwf ddrg ; set rg<1:0> as inputs ; rg<7:2> as outputs figure 10-14: block diagram of rg3:rg0 data bus wr portg wr ddrg rd port data latch ddrg latch p v ss i/o pin pcfg3:pcfg0 q d q ck q d q ck en qd en n st input buffer v dd rd ddrg to other pads v an chs3:chs0 to other pads
1997 microchip technology inc. preliminary ds30264a-page 81 pic17c75x figure 10-15: rg4 block diagram figure 10-16: rg7:rg5 block diagram note: i/o pin has protection diodes to v dd and vss. d ck q d ck q data bus rd_portg wr_portg rd_ddrg wr_ddrg en q d en p n q peripheral data in v dd note: i/o pins have protection diodes to v dd and vss. q d ck 1 0 q d ck r port data data bus rd_portg wr_portg rd_ddrg wr_ddrg n q d en p n q q output output enable peripheral data in v dd
pic17c75x ds30264a-page 82 preliminary 1997 microchip technology inc. table 10-13: portg functions table 10-14: registers/bits associated with portg name bit buffer type function rg0/an3 bit0 st input/output or analog input 3. rg1/an2 bit1 st input/output or analog input 2. rg2/an1/v ref - bit2 st input/output or analog input 1 or the ground reference voltage rg3/an0/v ref + bit3 st input/output or analog input 0 or the positive reference voltage rg4/cap3 bit4 st rg4 can also be the capture3 input pin. rg5/pwm3 bit5 st rg5 can also be the pwm3 output pin. rg6/rx2/dt2 bit6 st rg6 can also be selected as the usart2 (sci) asynchronous receive or usart2 (sci) synchronous data. rg7/tx2/ck2 bit7 st rg7 can also be selected as the usart2 (sci) asynchronous trans- mit or usart2 (sci) synchronous clock. legend: st = schmitt trigger input. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on, por, bor value on all other resets (note1) 12h, bank 5 ddrg data direction register for portg 1111 1111 1111 1111 13h, bank 5 portg rg7/ tx2/ck2 rg6/ rx2/dt2 rg5/ pwm3 rg4/ cap3 rg3/ an0 rg2/ an1 rg1/ an2 rg0/ an3 xxxx 0000 uuuu 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by portg. note 1: other (non power-up) resets include: external reset through mclr and the watchdog timer reset.
1997 microchip technology inc. preliminary ds30264a-page 83 pic17c75x 10.8 i/o programming considerations 10.8.1 bi-directional i/o ports any instruction which writes, operates internally as a read followed by a write operation. for example, the bcf and bsf instructions read the register into the cpu, execute the bit operation, and write the result back to the register. caution must be used when these instructions are applied to a port with both inputs and outputs de?ed. for example, a bsf operation on bit5 of portb will cause all eight bits of portb to be read into the cpu. then the bsf operation takes place on bit5 and portb is written to the output latches. if another bit of portb is used as a bi-directional i/o pin (e.g. bit0) and it is de?ed as an input at this time, the input signal present on the pin itself would be read into the cpu and re-written to the data latch of this particu- lar pin, overwriting the previous content. as long as the pin stays in the input mode, no problem occurs. how- ever, if bit0 is switched into output mode later on, the content of the data latch may now be unknown. reading a port reads the values of the port pins. writing to the port register writes the value to the port latch. when using read-modify-write instructions ( bcf, bsf , btg , etc.) on a port, the value of the port pins is read, the desired operation is performed with this value, and the value is then written to the port latch. example 10-8 shows the effect of two sequential read-modify-write instructions on an i/o port. example 10-8: read modify write instructions on an i/o port 10.8.2 successive operations on i/o ports the actual write to an i/o port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (figure 10-17). therefore, care must be exercised if a write followed by a read operation is carried out on the same i/o port. the sequence of instructions should be such to allow the pin voltage to stabilize (load depen- dent) before executing the instruction that reads the values on that i/o port. otherwise, the previous state of that pin may be read into the cpu rather than the ?ew state. when in doubt, it is better to separate these instructions with a nop or another instruction not accessing this i/o port. ; initial port settings: portb<7:4> inputs ; portb<3:0> outputs ; portb<7:6> have pull-ups and are ; not connected to other circuitry ; ; port latch port pins ; ---------- --------- ; bcf portb, 7 ; 01pp pppp 11pp pppp bcf portb, 6 ; 10pp pppp 11pp pppp bcf ddrb, 7 ; 10pp pppp 11pp pppp bcf ddrb, 6 ; 10pp pppp 10pp pppp ; ; note that the user may have expected the ; pin values to be 00pp pppp. the 2nd bcf ; caused rb7 to be latched as the pin value ; (high). note: a pin actively outputting a low or high should not be driven from external devices in order to change the level on this pin (i.e. ?ired-or? ?ired-and?. the resulting high output currents may damage the device. figure 10-17: successive i/o operation pc pc + 1 pc + 2 pc + 3 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetched rb7:rb0 movwf portb write to portb nop port pin sampled here nop movf portb,w instruction executed movwf portb write to portb nop movf portb,w note: this example shows a write to portb followed by a read from portb. note that: data setup time = (0.25t cy - t pd ) where t cy = instruction cycle t pd = propagation delay therefore, at higher clock frequencies, a write followed by a read may be problematic.
pic17c75x ds30264a-page 84 preliminary 1997 microchip technology inc. notes:
1997 microchip technology inc. preliminary ds30264a-page 85 pic17c75x 11.0 overview of timer resources the pic17c75x has four timer modules. each module can generate an interrupt to indicate that an event has occurred. these timers are called: timer0 - 16-bit timer with programmable 8-bit prescaler timer1 - 8-bit timer timer2 - 8-bit timer timer3 - 16-bit timer for enhanced time-base functionality, four input cap- tures and three pulse width modulation (pwm) out- puts are possible. the pwms use the timer1 and timer2 resources and the input captures use the timer3 resource. 11.1 t imer0 overview the timer0 module is a simple 16-bit over?w counter. the clock source can be either the internal system clock (fosc/4) or an external clock. when timer0 uses an external clock source, it has the ?xibility to allow user selection of the incrementing edge, rising or falling. the timer0 module also has a programmable pres- caler. the ps3:ps0 bits (t0sta<4:1>) determine the prescale value. tmr0 can increment at the following rates: 1:1, 1:2, 1:4, 1:8, 1:16, 1:32, 1:64, 1:128, 1:256. synchronization of the external clock occurs after the prescaler. when the prescaler is used, the external clock frequency may be higher then the devices fre- quency. the maximum external frequency, on the t0cki pin, is 50 mhz, given the high and low time requirements of the clock. 11.2 t imer1 overview the timer1 module is an 8-bit timer/counter with an 8-bit period register (pr1). when the tmr1 value rolls over from the period match value to 0h, the tmr1if ?g is set, and an interrupt will be generated if enabled. in counter mode, the clock comes from the rb4/tclk12 pin, which can also be selected to be the clock for the timer2 module. tmr1 can be concatenated with tmr2 to form a 16-bit timer. the tmr1 register is the lsb and tmr2 is the msb. when in the 16-bit timer mode, there is a corresponding 16-bit period register (pr2:pr1). when the tmr2:tmr1 value rolls over from the period match value to 0h, the tmr1if ?g is set, and an interrupt will be generated if enabled. 11.3 t imer2 overview the timer2 module is an 8-bit timer/counter with an 8-bit period register (pr2). when the tmr2 value rolls over from the period match value to 0h, the tmr2if ?g is set, and an interrupt will be generated if enabled. in counter mode, the clock comes from the rb4/tclk12 pin, which can also provide the clock for the timer1 module. tmr2 can be concatenated with tmr1 to form a 16-bit timer. the tmr2 register is the msb and tmr1 is the lsb. when in the 16-bit timer mode, there is a corresponding 16-bit period register (pr2:pr1). when the tmr2:tmr1 value rolls over from the period match value to 0h, the tmr1if ?g is set, and an interrupt will be generated if enabled. 11.4 t imer3 o verview the timer3 module is a 16-bit timer/counter with a 16-bit period register. when the tmr3h:tmr3l value rolls over to 0h, the tmr3if bit is set and an interrupt will be generated if enabled. in counter mode, the clock comes from the rb5/tclk3 pin. when operating in the four capture mode, the period registers become the second (of four) 16-bit capture registers. 11.5 role of the t imer/counters the timer modules are general purpose, but have ded- icated resources associated with them. timer1 and timer2 are the time-bases for the three pulse width modulation (pwm) outputs, while timer3 is the time-base for the four input captures.
pic17c75x ds30264a-page 86 preliminary 1997 microchip technology inc. notes:
1997 microchip technology inc. preliminary ds30264a-page 87 pic17c75x 12.0 timer0 the timer0 module consists of a 16-bit timer/counter, tmr0. the high byte is register tmr0h and the low byte is register tmr0l. a software programmable 8-bit prescaler makes timer0 an effective 24-bit over?w timer. the clock source is software programmable as either the internal instruction clock or an external clock on the ra1/t0cki pin. the control bits for this module are in register t0sta (figure 12-1). figure 12-1: t0sta register (address: 05h, unbanked) r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 u - 0 intedg t0se t0cs t0ps3 t0ps2 t0ps1 t0ps0 r = readable bit w = writable bit u = unimplemented, read as '0' -n = value at por reset bit7 bit0 bit 7: intedg : ra0/int pin interrupt edge select bit this bit selects the edge upon which the interrupt is detected 1 = rising edge of ra0/int pin generates interrupt 0 = falling edge of ra0/int pin generates interrupt bit 6: t0se : timer0 clock input edge select bit this bit selects the edge upon which tmr0 will increment when t0cs = 0 (external clock) 1 = rising edge of ra1/t0cki pin increments tmr0 and/or generates a t0ckif interrupt 0 = falling edge of ra1/t0cki pin increments tmr0 and/or generates a t0ckif interrupt when t0cs = 1 (internal clock) don? care bit 5: t0cs : timer0 clock source select bit this bit selects the clock source for tmr0. 1 = internal instruction clock cycle (t cy ) 0 = external clock input on the t0cki pin bit 4-1: t0ps3:t0ps0 : timer0 prescale selection bits these bits select the prescale value for tmr0. bit 0: unimplemented : read as '0' t0ps3:t0ps0 prescale value 0000 0001 0010 0011 0100 0101 0110 0111 1xxx 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
pic17c75x ds30264a-page 88 preliminary 1997 microchip technology inc. 12.1 t imer0 operation when the t0cs (t0sta<5>) bit is set, tmr0 incre- ments on the internal clock. when t0cs is clear, tmr0 increments on the external clock (ra1/t0cki pin). the external clock edge can be selected in software. when the t0se (t0sta<6>) bit is set, the timer will increment on the rising edge of the ra1/t0cki pin. when t0se is clear, the timer will increment on the falling edge of the ra1/t0cki pin. the prescaler can be programmed to introduce a prescale of 1:1 to 1:256. the timer incre- ments from 0000h to ffffh and rolls over to 0000h. on over?w, the tmr0 interrupt flag bit (t0if) is set. the tmr0 interrupt can be masked by clearing the cor- responding tmr0 interrupt enable bit (t0ie). the tmr0 interrupt flag bit (t0if) is automatically cleared when vectoring to the tmr0 interrupt vector. 12.2 using t imer0 with external clock when an external clock input is used for timer0, it is synchronized with the internal phase clocks. figure 12-3 shows the synchronization of the external clock. this synchronization is done after the prescaler. the output of the prescaler (psout) is sampled twice in every instruction cycle to detect a rising or a falling edge. the timing requirements for the external clock are detailed in the electrical speci?ation section. 12.2.1 delay from external clock edge since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time tmr0 is actually incremented. figure 12-3 shows that this delay is between 3t osc and 7t osc . thus, for example, mea- suring the interval between two edges (e.g. period) will be accurate within 4t osc ( 121 ns @ 33 mhz). figure 12-2: timer0 module block diagram figure 12-3: tmr0 timing with external clock (increment on falling edge) ra1/t0cki synchronization prescaler (8 stage async ripple counter) t0se (t0sta<6>) fosc/4 t0cs (t0sta<5>) t0ps3:t0ps0 (t0sta<4:1>) q2 q4 0 1 tmr0h<8> tmr0l<8> interrupt on over?w sets t0if (intsta<5>) 4 psout q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 prescaler output (psout) sampled prescaler output increment tmr0 tmr0 t0 t0 + 1 t0 + 2 (note 3) (note 2) note 1: the delay from the t0cki edge to the tmr0 increment is 3tosc to 7tosc. 2: - = psout is sampled here. 3: the psout high time is too short and is missed by the sampling circuit. (note 1)
1997 microchip technology inc. preliminary ds30264a-page 89 pic17c75x 12.3 read/w rite consideration for tmr0 although tmr0 is a 16-bit timer/counter, only 8-bits at a time can be read or written during a single instruction cycle. care must be taken during any read or write. 12.3.1 reading 16-bit value the problem in reading the entire 16-bit value is that after reading the low (or high) byte, its value may change from ffh to 00h. example 12-1 shows a 16-bit read. to ensure a proper read, interrupts must be disabled during this routine. example 12-1: 16-bit read movpf tmr0l, tmplo ;read low tmr0 movpf tmr0h, tmphi ;read high tmr0 movfp tmplo, wreg ;tmplo -> wreg cpfslt tmr0l ;tmr0l < wreg? return ;no then return movpf tmr0l, tmplo ;read low tmr0 movpf tmr0h, tmphi ;read high tmr0 return ;return 12.3.2 writing a 16-bit value to tmr0 since writing to either tmr0l or tmr0h will effectively inhibit increment of that half of the tmr0 in the next cycle (following write), but not inhibit increment of the other half, the user must write to tmr0l ?st and tmr0h second in two consecutive instructions, as shown in example 12-2. the interrupt must be dis- abled. any write to either tmr0l or tmr0h clears the prescaler. example 12-2: 16-bit write 12.4 prescaler assignments timer0 has an 8-bit prescaler. the prescaler assign- ment is fully under software control; i.e., it can be changed ?n the ? during program execution. when changing the prescaler assignment, clearing the pres- caler is recommended before changing assignment. the value of the prescaler is ?nknown, and assigning a value that is less then the present value makes it dif- ?ult to take this unknown time into account. bsf cpusta, glintd ; disable interrupts movfp ram_l, tmr0l ; movfp ram_h, tmr0h ; bcf cpusta, glintd ; done, enable ; interrupts figure 12-4: tmr0 timing: write high or low byte q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 ad15:ad0 ale tmr0l tmr0h movfp w,tmr0l write to tmr0l movfp tmr0l,w read tmr0l (value = nt0) movfp tmr0l,w read tmr0l (value = nt0) movfp tmr0l,w read tmr0l (value = nt0 +1) t0 t0+1 new t0 (nt0) new t0+1 pc pc+1 pc+2 pc+3 pc+4 fetch instruction executed
pic17c75x ds30264a-page 90 preliminary 1997 microchip technology inc. figure 12-5: tmr0 read/write in timer mode table 12-1: registers/bits associated with timer0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (note1) 05h, unbanked t0sta intedg t0se t0cs t0ps3 t0ps2 t0ps1 t0ps0 0000 000- 0000 000- 06h, unbanked cpusta stkav glintd t o pd por bor --11 1100 --11 qq11 07h, unbanked intsta peif t0ckif t0if intf peie t0ckie t0ie inte 0000 0000 0000 0000 0bh, unbanked tmr0l tmr0 register; low byte xxxx xxxx uuuu uuuu 0ch, unbanked tmr0h tmr0 register; high byte xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as a '0', q - value depends on condition, shaded cells are not used by timer0. note 1: other (non power-up) resets include: external reset through mclr and the watchdog timer reset. instruction executed movfp datal,tmr0l write tmr0l movfp datah,tmr0h write tmr0h movpf tmr0l,w read tmr0l movpf tmr0l,w read tmr0l movpf tmr0l,w read tmr0l q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 ad15:ad0 ale wr_trm0l wr_tmr0h rd_tmr0l tmr0h tmr0l 12 12 13 ab fe ff 56 57 58 in this example, old tmr0 value is 12feh, new value of ab56h is written. instruction fetched movfp datal,tmr0l write tmr0l movfp datah,tmr0h write tmr0h movpf tmr0l,w read tmr0l movpf tmr0l,w read tmr0l movpf tmr0l,w read tmr0l movpf tmr0l,w read tmr0l previously fetched instruction
1997 microchip technology inc. preliminary ds30264a-page 91 pic17c75x 13.0 timer1, timer2, timer3, pwms and captures the pic17c75x has a wealth of timers and time-based functions to ease the implementation of control applica- tions. these time-base functions include three pwm outputs and four capture inputs. timer1 and timer2 are two 8-bit incrementing timers, each with an 8-bit period register (pr1 and pr2 respectively) and separate over?w interrupt ?gs. timer1 and timer2 can operate either as timers (incre- ment on internal fosc/4 clock) or as counters (incre- ment on falling edge of external clock on pin rb4/tclk12). they are also software con?urable to operate as a single 16-bit timer/counter. these timers are also used as the time-base for the pwm (pulse width modulation) modules. timer3 is a 16-bit timer/counter which uses the tmr3h and tmr3l registers. timer3 also has two additional registers (pr3h/ca1h: pr3l/ca1l) that are con?- urable as a 16-bit period register or a 16-bit capture register. tmr3 can be software con?ured to incre- ment from the internal system clock (f osc /4) or from an external signal on the rb5/tclk3 pin. timer3 is the time-base for all of the 16-bit captures. six other registers comprise the capture2, capture3, and capture4 registers (ca2h:ca2l, ca3h:ca3l, and ca4h:ca4l). figure 13-1, figure 13-2, and figure 13-3 are the con- trol registers for the operation of timer1, timer2, and timer3, as well as pwm1, pwm2, pwm3, capture1, capture2, capture3, and capture4. table 13-1 shows the timer resource requirements for these time-base functions. each timer is an open resource so that multiple functions may operate with it. table 13-1: time-base function / resource requirements time-base function timer resource pwm1 timer1 pwm2 timer1 or timer2 pwm3 timer1 or timer2 capture1 timer3 capture2 timer3 capture3 timer3 capture4 timer3 figure 13-1: tcon1 register (address: 16h, bank 3) r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 ca2ed1 ca2ed0 ca1ed1 ca1ed0 t16 tmr3cs tmr2cs tmr1cs r = readable bit w = writable bit -n = value at por reset bit7 bit0 bit 7-6: ca2ed1:ca2ed0 : capture2 mode select bits 00 = capture on every falling edge 01 = capture on every rising edge 10 = capture on every 4th rising edge 11 = capture on every 16th rising edge bit 5-4: ca1ed1:ca1ed0 : capture1 mode select bits 00 = capture on every falling edge 01 = capture on every rising edge 10 = capture on every 4th rising edge 11 = capture on every 16th rising edge bit 3: t16 : timer2:timer1 mode select bit 1 = timer2 and timer1 form a 16-bit timer 0 = timer2 and timer1 are two 8-bit timers bit 2: tmr3cs : timer3 clock source select bit 1 = tmr3 increments off the falling edge of the rb5/tclk3 pin 0 = tmr3 increments off the internal clock bit 1: tmr2cs : timer2 clock source select bit 1 = tmr2 increments off the falling edge of the rb4/tclk12 pin 0 = tmr2 increments off the internal clock bit 0: tmr1cs : timer1 clock source select bit 1 = tmr1 increments off the falling edge of the rb4/tclk12 pin 0 = tmr1 increments off the internal clock
pic17c75x ds30264a-page 92 preliminary 1997 microchip technology inc. figure 13-2: tcon2 register (address: 17h, bank 3) r - 0 r - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 ca2ovf ca1ovf pwm2on pwm1on ca1/pr3 tmr3on tmr2on tmr1on r = readable bit w = writable bit -n = value at por reset bit7 bit0 bit 7: ca2ovf : capture2 over?w status bit this bit indicates that the capture value had not been read from the capture register pair (ca2h:ca2l) before the next capture event occurred. the capture register retains the oldest unread capture value (last capture before over?w). subsequent capture events will not update the capture register with the tmr3 value until the capture register has been read (both bytes). 1 = over?w occurred on capture2 register 0 = no over?w occurred on capture2 register bit 6: ca1ovf : capture1 over?w status bit this bit indicates that the capture value had not been read from the capture register pair (pr3h/ca1h:pr3l/ca1l) before the next capture event occurred. the capture register retains the old- est unread capture value (last capture before over?w). subsequent capture events will not update the capture register with the tmr3 value until the capture register has been read (both bytes). 1 = over?w occurred on capture1 register 0 = no over?w occurred on capture1 register bit 5: pwm2on : pwm2 on bit 1 = pwm2 is enabled (the rb3/pwm2 pin ignores the state of the ddrb<3> bit) 0 = pwm2 is disabled (the rb3/pwm2 pin uses the state of the ddrb<3> bit for data direction) bit 4: pwm1on : pwm1 on bit 1 = pwm1 is enabled (the rb2/pwm1 pin ignores the state of the ddrb<2> bit) 0 = pwm1 is disabled (the rb2/pwm1 pin uses the state of the ddrb<2> bit for data direction) bit 3: ca1/pr3 : ca1/pr3 register mode select bit 1 = enables capture1 (pr3h/ca1h:pr3l/ca1l is the capture1 register. timer3 runs without a period register) 0 = enables the period register (pr3h/ca1h:pr3l/ca1l is the period register for timer3) bit 2: tmr3on : timer3 on bit 1 = starts timer3 0 = stops timer3 bit 1: tmr2on : timer2 on bit this bit controls the incrementing of the tmr2 register. when tmr2:tmr1 form the 16-bit timer (t16 is set), tmr2on must be set. this allows the msb of the timer to increment. 1 = starts timer2 (must be enabled if the t16 bit (tcon1<3>) is set) 0 = stops timer2 bit 0: tmr1on : timer1 on bit when t16 is set (in 16-bit timer mode) 1 = starts 16-bit tmr2:tmr1 0 = stops 16-bit tmr2:tmr1 when t16 is clear (in 8-bit timer mode) 1 = starts 8-bit timer1 0 = stops 8-bit timer1
1997 microchip technology inc. preliminary ds30264a-page 93 pic17c75x figure 13-3: tcon3 register (address: 16h, bank 7) u-0 r - 0 r - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 - ca4ovf ca3ovf ca4ed1 ca4ed0 ca3ed1 ca3ed0 pwm3on r = readable bit w = writable bit u = unimplemented bit, reads as ? -n = value at por reset bit7 bit0 bit 7: unimplemented: read as ? bit 6: ca4ovf : capture4 over?w status bit this bit indicates that the capture value had not been read from the capture register pair (ca4h:ca4l) before the next capture event occurred. the capture register retains the oldest unread capture value (last capture before over?w). subsequent capture events will not update the capture register with the tmr3 value until the capture register has been read (both bytes). 1 = over?w occurred on capture4 registers 0 = no over?w occurred on capture4 registers bit 5: ca3ovf : capture3 over?w status bit this bit indicates that the capture value had not been read from the capture register pair (ca3h:ca3l) before the next capture event occurred. the capture register retains the oldest unread capture value (last capture before over?w). subsequent capture events will not update the capture register with the tmr3 value until the capture register has been read (both bytes). 1 = over?w occurred on capture3 registers 0 = no over?w occurred on capture3 registers bit 4-3: ca4ed1:ca4ed0 : capture4 mode select bits 00 = capture on every falling edge 01 = capture on every rising edge 10 = capture on every 4th rising edge 11 = capture on every 16th rising edge bit 2-1: ca3ed1:ca3ed0 : capture3 mode select bits 00 = capture on every falling edge 01 = capture on every rising edge 10 = capture on every 4th rising edge 11 = capture on every 16th rising edge bit 0: pwm3on : pwm3 on bit 1 = pwm3 is enabled (the rg5/pwm3 pin ignores the state of the ddrg<5> bit) 0 = pwm3 is disabled (the rg5/pwm3 pin uses the state of the ddrg<5> bit for data direction)
pic17c75x ds30264a-page 94 preliminary 1997 microchip technology inc. 13.1 t imer1 an d t imer2 13.1.1 timer1, timer2 in 8-bit mode both timer1 and timer2 will operate in 8-bit mode when the t16 bit is clear. these two timers can be inde- pendently con?ured to increment from the internal instruction cycle clock (t cy ) or from an external clock source on the rb4/tclk12 pin. the timer clock source is con?ured by the tmrxcs bit (x = 1 for timer1 or = 2 for timer2). when tmrxcs is clear, the clock source is internal and increments once every instruction cycle (fosc/4). when tmrxcs is set, the clock source is the rb4/tclk12 pin, and the counters will increment on every falling edge of the rb4/tclk12 pin. the timer increments from 00h until it equals the period register (prx). it then resets to 00h at the next incre- ment cycle. the timer interrupt ?g is set when the timer is reset. tmr1 and tmr2 have individual inter- rupt ?g bits. the tmr1 interrupt ?g bit is latched into tmr1if, and the tmr2 interrupt ?g bit is latched into tmr2if. each timer also has a corresponding interrupt enable bit (tmrxie). the timer interrupt can be enabled/dis- abled by setting/clearing this bit. for peripheral inter- rupts to be enabled, the peripheral interrupt enable bit must be set (peie = '1') and global interrupt must be enabled (glintd = '0'). the timers can be turned on and off under software control. when the timer on control bit (tmrxon) is set, the timer increments from the clock source. when tmrxon is cleared, the timer is turned off and cannot cause the timer interrupt ?g to be set. 13.1.1.1 external clock input for timer1 and timer2 when tmrxcs is set, the clock source is the rb4/tclk12 pin, and the counter will increment on every falling edge on the rb4/tclk12 pin. the tclk12 input is synchronized with internal phase clocks. this causes a delay from the time a falling edge appears on tclk12 to the time tmr1 or tmr2 is actu- ally incremented. for the external clock input timing requirements, see the electrical speci?ation section. figure 13-4: timer1 and timer2 in two 8-bit timer/counter mode fosc/4 rb4/tclk12 tmr1on (tcon2<0>) tmr1cs (tcon1<0>) tmr1 pr1 reset equal set tmr1if (pir1<4>) 0 1 comparator<8> comparator x8 fosc/4 tmr2on (tcon2<1>) tmr2cs (tcon1<1>) tmr2 pr2 reset equal set tmr2if (pir1<5>) 1 0 comparator<8> comparator x8
1997 microchip technology inc. preliminary ds30264a-page 95 pic17c75x 13.1.2 timer1 and timer2 in 16-bit mode to select 16-bit mode, set the t16 bit. in this mode tmr2 and tmr1 are concatenated to form a 16-bit timer (tmr2:tmr1). the 16-bit timer increments until it matches the 16-bit period register (pr2:pr1). on the following timer clock, the timer value is reset to 0h, and the tmr1if bit is set. when selecting the clock source for the16-bit timer, the tmr1cs bit controls the entire 16-bit timer and tmr2cs is a ?on? care? however ensure that tmr2on is set (allows tmr2 to increment). when tmr1cs is clear, the timer increments once every instruction cycle (fosc/4). when tmr1cs is set, the timer increments on every falling edge of the rb4/tclk12 pin. for the 16-bit timer to increment, both tmr1on and tmr2on bits must be set (table 13-2). table 13-2: turning on 16-bit timer t16 tmr2on tmr1on result 11 1 16-bit timer (tmr2:tmr1) on 10 1 only tmr1 increments 1x 0 16-bit timer off 01 1 timers in 8-bit mode 13.1.2.1 external clock input for tmr2:tmr1 when tmr1cs is set, the 16-bit tmr2:tmr1 incre- ments on the falling edge of clock input tclk12. the input on the rb4/tclk12 pin is sampled and synchro- nized by the internal phase clocks twice every instruc- tion cycle. this causes a delay from the time a falling edge appears on rb4/tclk12 to the time tmr2:tmr1 is actually incremented. for the external clock input timing requirements, see the electrical speci?ation section. figure 13-5: tmr2 and tmr1 in 16-bit timer/counter mode rb4/tclk12 fosc/4 tmr1on (tcon2<0>) tmr1cs (tcon1<0>) tmr1 x 8 pr1 x 8 reset equal set interrupt tmr1if (pir1<4>) 1 0 comparator<8> comparator x16 tmr2 x 8 pr2 x 8 msb lsb
pic17c75x ds30264a-page 96 preliminary 1997 microchip technology inc. table 13-3: summary of timer1 and timer2 registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (note1) 16h, bank 3 tcon1 ca2ed1 ca2ed0 ca1ed1 ca1ed0 t16 tmr3cs tmr2cs tmr1cs 0000 0000 0000 0000 17h, bank 3 tcon2 ca2ovf ca1ovf pwm2on pwm1on ca1/pr3 tmr3on tmr2on tmr1on 0000 0000 0000 0000 16h, bank 7 tcon3 ca4ovf ca3ovf ca4ed1 ca4ed0 ca3ed1 ca3ed0 pwm3on -000 0000 -000 0000 10h, bank 2 tmr1 timer1s register xxxx xxxx uuuu uuuu 11h, bank 2 tmr2 timer2s register xxxx xxxx uuuu uuuu 16h, bank 1 pir1 rbif tmr3if tmr2if tmr1if ca2if ca1if tx1if rc1if 0000 0010 0000 0010 17h, bank 1 pie1 rbie tmr3ie tmr2ie tmr1ie ca2ie ca1ie tx1ie rc1ie 0000 0000 0000 0000 07h, unbanked intsta peif t0ckif t0if intf peie t0ckie t0ie inte 0000 0000 0000 0000 06h, unbanked cpusta stkav glintd t o pd por bor --11 1100 --11 qq11 14h, bank 2 pr1 timer1 period register xxxx xxxx uuuu uuuu 15h, bank 2 pr2 timer2 period register xxxx xxxx uuuu uuuu 10h, bank 3 pw1dcl dc1 dc0 xx-- ---- uu-- ---- 11h, bank 3 pw2dcl dc1 dc0 tm2pw2 xx0- ---- uu0- ---- 10h, bank 7 pw3dcl dc1 dc0 tm2pw3 xx0- ---- uu0- ---- 12h, bank 3 pw1dch dc9 dc8 dc7 dc6 dc5 dc4 dc3 dc2 xxxx xxxx uuuu uuuu 13h, bank 3 pw2dch dc9 dc8 dc7 dc6 dc5 dc4 dc3 dc2 xxxx xxxx uuuu uuuu 11h, bank 7 pw3dch dc9 dc8 dc7 dc6 dc5 dc4 dc3 dc2 xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as a '0', q - value depends on condition, shaded cells are not used by timer1 or timer2. note 1: other (non power-up) resets include: external reset through mclr and wdt timer reset.
1997 microchip technology inc. preliminary ds30264a-page 97 pic17c75x 13.1.3 using pulse width modulation (pwm) outputs with timer1 and timer2 three high speed pulse width modulation (pwm) out- puts are provided. the pwm1 output uses timer1 as its time-base, while pwm2 and pwm3 may indepen- dently be software con?ured to use either timer1 or timer2 as the time-base. the pwm outputs are on the rb2/pwm1, rb3/pwm2, and rg5/pwm3 pins. each pwm output has a maximum resolution of 10-bits. at 10-bit resolution, the pwm output frequency is 32.2 khz (@ 32 mhz clock) and at 8-bit resolution the pwm output frequency is 128.9 khz. the duty cycle of the output can vary from 0% to 100%. figure 13-6 shows a simpli?d block diagram of a pwm module. the duty cycle registers are double buffered for glitch free operation. figure 13-7 shows how a glitch could occur if the duty cycle registers were not double buff- ered. the user needs to set the pwm1on bit (tcon2<4>) to enable the pwm1 output. when the pwm1on bit is set, the rb2/pwm1 pin is con?ured as pwm1 output and forced as an output irrespective of the data direc- tion bit (ddrb<2>). when the pwm1on bit is clear, the pin behaves as a port pin and its direction is con- trolled by its data direction bit (ddrb<2>). similarly, the pwm2on (tcon2<5>) bit controls the con?ura- tion of the rb3/pwm2 pin and the pwm3on (tcon3<0>) bit controls the con?uration of the rg5/pwm3 pin. figure 13-6: simplified pwm block diagram pwxdch duty cycle registers pwxdcl<7:6> clear timer, pwmx pin and latch d.c. (slave) comparator tmrx comparator pry (note 1) r s q pwmxon pwmx note 1: 8-bit timer is concatenated with 2-bit internal q clock or 2 bits of the prescaler to create 10-bit time-base. read write figure 13-7: pwm output 0 10203040 0 pwm output timer interrupt write new pwm value timer interrupt new pwm value transferred to slave note the dotted line shows pwm output if duty cycle registers were not double buffered. if the new duty cycle is written after the timer has passed that value, then the pwm does not reset at all during the current cycle causing a ?litch? in this example, pwm period = 50. old duty cycle is 30. new duty cycle value is 10.
pic17c75x ds30264a-page 98 preliminary 1997 microchip technology inc. 13.1.3.1 pwm periods the period of the pwm1 output is determined by timer1 and its period register (pr1). the period of the pwm2 and pwm3 outputs can be individually software con?ured to use either timer1 or timer2 as the time-base. for pwm2, when tm2pw2 bit (pw2dcl<5>) is clear, the time-base is determined by tmr1 and pr1, and when tm2pw2 is set, the time-base is determined by timer2 and pr2. for pwm3, when tm2pw3 bit (pw3dcl<5>) is clear, the time-base is determined by tmr1 and pr1, and when tm2pw3 is set, the time-base is determined by timer2 and pr2. running two different pwm outputs on two different timers allows different pwm periods. running all pwms from timer1 allows the best use of resources by freeing timer2 to operate as an 8-bit timer. timer1 and timer2 can not be used as a 16-bit timer if any pwm is being used. the pwm periods can be calculated as follows: period of pwm1 = [(pr1) + 1] x 4t osc period of pwm2 = [(pr1) + 1] x 4t osc or [(pr2) + 1] x 4t osc period of pwm3 = [(pr1) + 1] x 4t osc or [(pr2) + 1] x 4t osc the duty cycle of pwmx is determined by the 10-bit value dcx<9:0>. the upper 8-bits are from register pwxdch and the lower 2-bits are from pwxdcl<7:6> (pwxdch:pwxdcl<7:6>). table 13-4 shows the maximum pwm frequency (f pwm ) given the value in the period register. the number of bits of resolution that the pwm can achieve depends on the operation frequency of the device as well as the pwm frequency (f pwm ). maximum pwm resolution (bits) for a given pwm fre- quency: where: f pwm = 1 / period of pwm the pwmx duty cycle is as follows: pwmx duty cycle =(dcx) x t osc where dcx represents the 10-bit value from pwxdch:pwxdcl. log ( f pwm log (2) f osc ) bits = if dcx = 0, then the duty cycle is zero. if prx = pwxdch, then the pwm output will be low for one to four q-clock (depending on the state of the pwxdcl<7:6> bits). for a duty cycle to be 100%, the pwxdch value must be greater then the prx value. the duty cycle registers for both pwm outputs are dou- ble buffered. when the user writes to these registers, they are stored in master latches. when tmr1 (or tmr2) over?ws and a new pwm period begins, the master latch values are transferred to the slave latches and the pwmx pin is forced high. the user should also avoid any "read-modify-write" operations on the duty cycle registers, such as: addwf pw1dch . this may cause duty cycle outputs that are unpredictable. table 13-4: pwm frequency vs. resolution at 33 mhz 13.1.3.2 pwm interrupts the pwm modules makes use of the tmr1 and/or tmr2 interrupts. a timer interrupt is generated when tmr1 or tmr2 equals its period register and on the following increment is cleared to zero. this interrupt also marks the beginning of a pwm cycle. the user can write new duty cycle values before the timer roll-over. the tmr1 interrupt is latched into the tmr1if bit and the tmr2 interrupt is latched into the tmr2if bit. these ?gs must be cleared in software. note: for pw1dch, pw1dcl, pw2dch, pw2dcl, pw3dch and pw3dcl regis- ters, a write operation writes to the "master latches" while a read operation reads the "slave latches". as a result, the user may not read back what was just written to the duty cycle registers. pwm frequency frequency (khz) 32.2 64.5 90.66 128.9 515.6 prx value 0xff 0x7f 0x5a 0x3f 0x0f high resolution 10-bit 9-bit 8.5-bit 8-bit 6-bit standard resolution 8-bit 7-bit 6.5-bit 6-bit 4-bit
1997 microchip technology inc. preliminary ds30264a-page 99 pic17c75x 13.1.3.3 external clock source the pwms will operate regardless of the clock source of the timer. the use of an external clock has rami?a- tions that must be understood. because the external tclk12 input is synchronized internally (sampled once per instruction cycle), the time tclk12 changes to the time the timer increments will vary by as much as 1t cy (one instruction cycle). this will cause jitter in the duty cycle as well as the period of the pwm output. this jitter will be 1t cy , unless the external clock is synchronized with the processor clock. use of one of the pwm outputs as the clock source to the tclk12 input, will supply a synchronized clock. in general, when using an external clock source for pwm, its frequency should be much less than the device frequency (fosc). 13.1.3.3.1 max resolution/frequency for external clock input the use of an external clock for the pwm time-base (timer1 or timer2) limits the pwm output to a maxi- mum resolution of 8-bits. the pwxdcl<7:6> bits must be kept cleared. use of any other value will distort the pwm output. all resolutions are supported when inter- nal clock mode is selected. the maximum attainable frequency is also lower. this is a result of the timing requirements of an external clock input for a timer (see the electrical speci?ation section). the maximum pwm frequency, when the timers clock source is the rb4/tclk12 pin, as shown in table 13-4 (standard resolution mode). table 13-5: registers/bits associated with pwm address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (note1) 16h, bank 3 tcon1 ca2ed1 ca2ed0 ca1ed1 ca1ed0 t16 tmr3cs tmr2cs tmr1cs 0000 0000 0000 0000 17h, bank 3 tcon2 ca2ovf ca1ovf pwm2on pwm1on ca1/pr3 tmr3on tmr2on tmr1on 0000 0000 0000 0000 16h, bank 7 tcon3 ca4ovf ca3ovf ca4ed1 ca4ed0 ca3ed1 ca3ed0 pwm3on -000 0000 -000 0000 10h, bank 2 tmr1 timer1s register xxxx xxxx uuuu uuuu 11h, bank 2 tmr2 timer2s register xxxx xxxx uuuu uuuu 16h, bank 1 pir1 rbif tmr3if tmr2if tmr1if ca2if ca1if tx1if rc1if 0000 0010 0000 0010 17h, bank 1 pie1 rbie tmr3ie tmr2ie tmr1ie ca2ie ca1ie tx1ie rc1ie 0000 0000 0000 0000 07h, unbanked intsta peif t0ckif t0if intf peie t0ckie t0ie inte 0000 0000 0000 0000 06h, unbanked cpusta stkav glintd t o pd por bor --11 1100 --11 qq11 14h, bank 2 pr1 timer1 period register xxxx xxxx uuuu uuuu 15h, bank 2 pr2 timer2 period register xxxx xxxx uuuu uuuu 10h, bank 3 pw1dcl dc1 dc0 xx-- ---- uu-- ---- 11h, bank 3 pw2dcl dc1 dc0 tm2pw2 xx0- ---- uu0- ---- 10h, bank 7 pw3dcl dc1 dc0 tm2pw3 xx0- ---- uu0- ---- 12h, bank 3 pw1dch dc9 dc8 dc7 dc6 dc5 dc4 dc3 dc2 xxxx xxxx uuuu uuuu 13h, bank 3 pw2dch dc9 dc8 dc7 dc6 dc5 dc4 dc3 dc2 xxxx xxxx uuuu uuuu 11h, bank 7 pw3dch dc9 dc8 dc7 dc6 dc5 dc4 dc3 dc2 xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends on conditions, shaded cells are not used by pwm module. note 1: other (non power-up) resets include: external reset through mclr and wdt timer reset.
pic17c75x ds30264a-page 100 preliminary 1997 microchip technology inc. 13.2 t im er3 timer3 is a 16-bit timer consisting of the tmr3h and tmr3l registers. tmr3h is the high byte of the timer and tmr3l is the low byte. this timer has an associ- ated 16-bit period register (pr3h/ca1h:pr3l/ca1l). this period register can be software con?ured to be a another 16-bit capture register. when the tmr3cs bit (tcon1<2>) is clear, the timer increments every instruction cycle (fosc/4). when tmr3cs is set, the counter increments on every falling edge of the rb5/tclk3 pin. in either mode, the tmr3on bit must be set for the timer/counter to incre- ment. when tmr3on is clear, the timer will not incre- ment or set ?g bit tmr3if. timer3 has two modes of operation, depending on the ca1/pr3 bit (tcon2<3>). these modes are: three capture and one period register mode four capture register mode the pic17c75x has up to four 16-bit capture registers that capture the 16-bit value of tmr3 when events are detected on capture pins. there are four capture pins (rb0/cap1, rb1/cap2, rg4/cap3, and re3/cap4), one for each capture register pair. the capture pins are multiplexed with the i/o pins. an event can be: a rising edge a falling edge every 4th rising edge every 16th rising edge each 16-bit capture register has an interrupt ?g asso- ciated with it. the ?g is set when a capture is made. the capture modules are truly part of the timer3 block. figure 13-8 and figure 13-9 show the block diagrams for the two modes of operation. 13.2.1 three capture and one period register mode in this mode registers pr3h/ca1h and pr3l/ca1l constitute a 16-bit period register. a block diagram is shown in figure 13-8. the timer increments until it equals the period register and then resets to 0000h on the next timer clock. tmr3 interrupt flag bit (tmr3if) is set at this point. this interrupt can be disabled by clearing the tmr3 interrupt enable bit (tmr3ie). tmr3if must be cleared in software. figure 13-8: timer3 with three capture and one period register block diagram pr3h/ca1h tmr3h comparator<8> fosc/4 tmr3on reset equal 0 1 comparator x16 rb5/tclk3 set tmr3if tmr3cs pr3l/ca1l tmr3l ca2h ca2l rb1/cap2 edge select, prescaler select 2 set ca2if capture2 ca2ed1: ca2ed0 (tcon1<7:6>) (tcon2<2>) (tcon1<2>) (pir1<3>) (pir1<6>) enable ca3h ca3l rg4/cap3 edge select, prescaler select 2 set ca3if capture3 ca3ed1: ca3ed0 (tcon3<2:1>) (pir2<2>) enable ca4h ca4l re3/cap4 edge select, prescaler select 2 set ca4if capture4 ca4ed1: ca4ed0 (tcon3<4:3>) (pir2<3>) enable
1997 microchip technology inc. preliminary ds30264a-page 101 pic17c75x this mode (3 capture, 1 period) is selected if control bit ca1/pr3 is clear. in this mode, the capture1 register, consisting of high byte (pr3h/ca1h) and low byte (pr3l/ca1l), is con?ured as the period control regis- ter for tmr3. capture1 is disabled in this mode, and the corresponding interrupt bit ca1if is never set. tmr3 increments until it equals the value in the period register and then resets to 0000h on the next timer clock. all other captures are active in this mode. 13.2.1.1 capture operation the caxed1 and caxed0 bits determine the event on which capture will occur. the possible events are: capture on every falling edge capture on every rising edge capture every 4th rising edge capture every 16th rising edge when a capture takes place, an interrupt ?g is latched into the caxif bit. this interrupt can be enabled by set- ting the corresponding mask bit caxie. the peripheral interrupt enable bit (peie) must be set and the global interrupt disable bit (glintd) must be cleared for the interrupt to be acknowledged. the caxif interrupt ?g bit is cleared in software. when the capture prescale select is changed, the pres- caler is not reset and an event may be generated. therefore, the ?st capture after such a change will be ambiguous. however, it sets the time-base for the next capture. the prescaler is reset upon chip reset. the capture pin, capx, is a multiplexed pin. when used as a port pin, the capture is not disabled. how- ever, the user can simply disable the capture interrupt by clearing caxie. if the capx pin is used as an output pin, the user can activate a capture by writing to the port pin. this may be useful during development phase to emulate a capture interrupt. the input on the capture pin capx is synchronized internally to internal phase clocks. this imposes certain restrictions on the input waveform (see the electrical speci?ation section for timing). the capture over?w status ?g bit is double buffered. the master bit is set if one captured word is already residing in the capture register (caxh:caxl) and another ?vent has occurred on the capx pin. the new event will not transfer the tmr3 value to the capture register, protecting the previous unread capture value. when the user reads both the high and the low bytes (in any order) of the capture register, the master over?w bit is transferred to the slave over?w bit (caxovf) and then the master bit is reset. the user can then read tconx to determine the value of caxovf. the recommended sequence to read capture registers and capture over?w ?g bits is shown in example 13-1.
pic17c75x ds30264a-page 102 preliminary 1997 microchip technology inc. 13.2.2 four capture mode this mode is selected by setting bit ca1/pr3 . a block diagram is shown in figure 13-9. in this mode, tmr3 runs without a period register and increments from 0000h to ffffh and rolls over to 0000h. the tmr3 interrupt flag (tmr3if) is set on this rollover. the tmr3if bit must be cleared in software. registers pr3h/ca1h and pr3l/ca1l make a 16-bit capture register (capture1). it captures events on pin rb0/cap1. capture mode is con?ured by the ca1ed1 and ca1ed0 bits. capture1 interrupt flag bit (ca1if) is set upon detection of the capture event. the corresponding interrupt mask bit is ca1ie. the capture1 over?w status bit is ca1ovf. all the captures operate in the same manner. refer to section 13.2.1 for the operation of capture. figure 13-9: timer3 with four captures block diagram rb0/cap1 edge select, prescaler select pr3h/ca1h pr3l/ca1l rb1/cap2 rg4/cap3 edge select, prescaler select 2 set ca1if (pir1<2>) capture1 enable tmr3on tmr3cs (tcon1<2>) 0 1 set tmr3if (pir1<6>) edge select, prescaler select ca2h ca2l set ca2if (pir1<3>) ca3h ca3l set ca3if (pir2<2>) ca1ed1, ca1ed0 (tcon1<5:4>) (tcon2<2>) fosc/4 rb5/tclk3 capture2 enable capture3 enable ca2ed1, ca2ed0 (tcon1<7:6>) 2 ca3ed1: ca3ed0 (tcon3<2:1>) tmr3h tmr3l 2 re3/cap4 edge select, prescaler select 2 ca4h ca4l set ca4if (pir2<3>) capture4 enable ca4ed1: ca4ed0 (tcon3<4:3>)
1997 microchip technology inc. preliminary ds30264a-page 103 pic17c75x 13.2.3 reading the capture registers the capture over?w status ?g bits are double buffered. the master bit is set if one captured word is already residing in the capture register and another ?vent has occurred on the capx pin. the new event will not transfer the tmr3 value to the capture register, protecting the previous unread capture value. when the user reads both the high and the low bytes (in any order) of the capture register, the master over?w bit is transferred to the slave over?w bit (caxovf) and then the master bit is reset. the user can then read tconx to determine the value of caxovf. an example of an instruction sequence to read capture registers and capture over?w ?g bits is shown in example 13-1. depending on the capture source, dif- ferent registers will need to be read. example 13-1: sequence to read capture registers table 13-6: registers associated with capture movlb 3 ; select bank 3 movpf ca2l, lo_byte ; read capture2 low byte, store in lo_byte movpf ca2h, hi_byte ; read capture2 high byte, store in hi_byte movpf tcon2, stat_val ; read tcon2 into file stat_val address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (note1) 16h, bank 3 tcon1 ca2ed1 ca2ed0 ca1ed1 ca1ed0 t16 tmr3cs tmr2cs tmr1cs 0000 0000 0000 0000 17h, bank 3 tcon2 ca2ovf ca1ovf pwm2on pwm1on ca1/pr3 tmr3on tmr2on tmr1on 0000 0000 0000 0000 16h, bank 7 tcon3 ca4ovf ca3ovf ca4ed1 ca4ed0 ca3ed1 ca3ed0 pwm3on -000 0000 -000 0000 12h, bank 2 tmr3l holding register for the low byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu 13h, bank 2 tmr3h holding register for the high byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu 16h, bank 1 pir1 rbif tmr3if tmr2if tmr1if ca2if ca1if tx1if rc1if 0000 0010 0000 0010 17h, bank 1 pie1 rbie tmr3ie tmr2ie tmr1ie ca2ie ca1ie tx1ie rc1ie 0000 0000 0000 0000 10h, bank 4 pir2 sspif bclif adif ca4if ca3if tx2if rc2if 000- 0010 000- 0010 11h, bank 4 pie2 sspie bclie adie ca4ie ca3ie tx2ie rc2ie 000- 0000 000- 0000 07h, unbanked intsta peif t0ckif t0if intf peie t0ckie t0ie inte 0000 0000 0000 0000 06h, unbanked cpusta stkav glintd t o pd por bor --11 1100 --11 qq11 16h, bank 2 pr3l/ca1l timer3 period register, low byte/capture1 register, low byte xxxx xxxx uuuu uuuu 17h, bank 2 pr3h/ca1h timer3 period register, high byte/capture1 register, high byte xxxx xxxx uuuu uuuu 14h, bank 3 ca2l capture2 low byte xxxx xxxx uuuu uuuu 15h, bank 3 ca2h capture2 high byte xxxx xxxx uuuu uuuu 12h, bank 7 ca3l capture3 low byte xxxx xxxx uuuu uuuu 13h, bank 7 ca3h capture3 high byte xxxx xxxx uuuu uuuu 14h, bank 7 ca4l capture4 low byte xxxx xxxx uuuu uuuu 15h, bank 7 ca4h capture4 high byte xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition, shaded cells are not used by capture. note 1: other (non power-up) resets include: external reset through mclr and wdt timer reset.
pic17c75x ds30264a-page 104 preliminary 1997 microchip technology inc. 13.2.4 external clock input for timer3 when tmr3cs is set, the 16-bit tmr3 increments on the falling edge of clock input tclk3. the input on the rb5/tclk3 pin is sampled and synchronized by the internal phase clocks twice every instruction cycle. this causes a delay from the time a falling edge appears on tclk3 to the time tmr3 is actually incremented. for the external clock input timing requirements, see the electrical speci?ation section. figure 13-10 shows the timing diagram when operating from an external clock. 13.2.5 reading/writing timer3 since timer3 is a 16-bit timer and only 8-bits at a time can be read or written, care should be taken when reading or writing while the timer is running. the best method is to stop the timer, perform any read or write operation, and then restart timer3 (using the tmr3on bit). however, if it is necessary to keep timer3 free-run- ning, care must be taken. for writing to the 16-bit tmr3, example 13-2 may be used. for reading the 16-bit tmr3, example 13-3 may be used. interrupts must be disabled during this routine. example 13-2: writing to tmr3 example 13-3: reading from tmr3 figure 13-10: timer1, timer2, and timer3 operation (in counter mode) bsf cpusta, glintd ; disable interrupts movfp ram_l, tmr3l ; movfp ram_h, tmr3h ; bcf cpusta, glintd ; done, enable interrupts movpf tmr3l, tmplo ; read low tmr3 movpf tmr3h, tmphi ; read high tmr3 movfp tmplo, wreg ; tmplo -> wreg cpfslt tmr3l, wreg ; tmr3l < wreg? return ; no then return movpf tmr3l, tmplo ; read low tmr3 movpf tmr3h, tmphi ; read high tmr3 return ; return q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction executed movwf movfp tmrx,w tmrx movfp tmrx,w write to tmrx read tmrx read tmrx 34h 35h a8h a9h 00h 'a9h' 'a9h' tclk12 tmr1, tmr2, or tmr3 pr1, pr2, or pr3h:pr3l wr_tmr rd_tmr tmrxif note 1: tclk12 is sampled in q2 and q4. 2: indicates a sampling point. 3: the latency from tclk12 to timer increment is between 2tosc and 6tosc. or tclk3
1997 microchip technology inc. preliminary ds30264a-page 105 pic17c75x figure 13-11: timer1, timer2, and timer3 operation (in timer mode) q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 ad15:ad0 ale instruction fetched tmr1 pr1 tmr1on wr_tmr1 wr_tcon2 tmr1if rd_tmr1 tmr1 reads 03h tmr1 reads 04h movwf tmr1 write tmr1 movf tmr1, w read tmr1 movf tmr1, w read tmr1 bsf tcon2, 0 stop tmr1 bcf tcon2, 0 start tmr1 movlb 3 nop nop nop nop nop 04h 05h 03h 04h 05h 06h 07h 08h 00h
pic17c75x ds30264a-page 106 preliminary 1997 microchip technology inc. notes:
1997 microchip technology inc. preliminary ds30264a-page 107 pic17c75x 14.0 universal synchronous asynchronous receiver transmitter (usart) modules each usart module is a serial i/o module. there are two usart modules that are available on the pic17c75x. they are speci?d as usart1 and usart2. the description of the operation of these modules is generic in regard to the register names and pin names used. table 14-1 shows the generic names that are used in the description of operation and the actual names for both usart1 and usart2. since the control bits in each register have the same function, their names are the same (there is no need to differen- tiate). the transmit status and control register (txsta) is shown in figure 14-1, while the receive status and control register (rcsta) is shown in figure 14-2. table 14-1: usart module generic names generic name usart1 name usart2 name registers rcsta rcsta1 rcsta2 txsta txsta1 txsta2 spbrg spbrg1 spbrg2 rcreg rcreg1 rcreg2 txreg txreg1 txreg2 interrupt control bits rcie rc1ie rc2ie rcif rc1if rc2if txie tx1ie tx2ie txif tx1if tx2if pins rx/dt ra4/rx1/dt1 rg6/rx2/dt2 tx/ck ra5/tx1/ck1 rg7/tx2/ck2 figure 14-1: txsta1 register (address: 15h, bank 0) txsta2 register (address: 15h, bank 4) r/w - 0 r/w - 0 r/w - 0 r/w - 0 u - 0 u - 0 r - 1 r/w - x csrc tx9 txen sync trmt tx9d r = readable bit w = writable bit -n = value at por reset (x = unknown) bit7 bit0 bit 7: csrc : clock source select bit synchronous mode: 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) asynchronous mode : don? care bit 6: tx9 : 9-bit transmit select bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5: txen : transmit enable bit 1 = transmit enabled 0 = transmit disabled sren/cren overrides txen in sync mode bit 4: sync : usart mode select bit (synchronous/asynchronous) 1 = synchronous mode 0 = asynchronous mode bit 3-2: unimplemented : read as '0' bit 1: trmt : transmit shift register (tsr) empty bit 1 = tsr empty 0 = tsr full bit 0: tx9d : 9th bit of transmit data (can be used to calculated the parity in software)
pic17c75x ds30264a-page 108 preliminary 1997 microchip technology inc. the usart can be con?ured as a full duplex asyn- chronous system that can communicate with peripheral devices such as crt terminals and personal comput- ers, or it can be con?ured as a half duplex synchro- nous system that can communicate with peripheral devices such as a/d or d/a integrated circuits, serial eeproms etc. the usart can be con?ured in the following modes: asynchronous (full duplex) synchronous - master (half duplex) synchronous - slave (half duplex) the spen (rcsta<7>) bit has to be set in order to con?ure the i/o pins as the serial communication interface. the usart module will control the direction of the rx/dt and tx/ck pins, depending on the states of the usart con?uration bits in the rcsta and txsta registers. the bits that control i/o direction are: spen txen sren cren csrc figure 14-2: rcsta1 register (address: 13h, bank 0) rcsta2 register (address: 13h, bank 4) r/w - 0 r/w - 0 r/w - 0 r/w - 0 u - 0 r - 0 r - 0 r - x spen rx9 sren cren ferr oerr rx9d r = readable bit w = writable bit -n = value at por reset (x = unknown) bit7 bit 0 bit 7: spen : serial port enable bit 1 = con?ures tx/ck and rx/dt pins as serial port pins 0 = serial port disabled bit 6: rx9 : 9-bit receive select bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5: sren : single receive enable bit this bit enables the reception of a single byte. after receiving the byte, this bit is automatically cleared. synchronous mode: 1 = enable reception 0 = disable reception note: this bit is ignored in synchronous slave reception. asynchronous mode: don? care bit 4: cren : continuous receive enable bit this bit enables the continuous reception of serial data. asynchronous mode: 1 = enable continuous reception 0 = disables continuous reception synchronous mode: 1 = enables continuous reception until cren is cleared (cren overrides sren) 0 = disables continuous reception bit 3: unimplemented : read as '0' bit 2: ferr : framing error bit 1 = framing error (updated by reading rcreg) 0 = no framing error bit 1: oerr : overrun error bit 1 = overrun (cleared by clearing cren) 0 = no overrun error bit 0: rx9d : 9th bit of receive data (can be the software calculated parity bit)
1997 microchip technology inc. preliminary ds30264a-page 109 pic17c75x figure 14-3: usart transmit figure 14-4: usart receive ck/tx dt sync/async tsr start 0 1 7 8 stop ? 16 ? 4 brg 01 7 8 bit count txie interrupt txen/ write to txreg clock sync/async sync/async txsta<0> sync master/slave data bus load txreg ck rx 0 1 7 8 stop ? 16 ? 4 brg bit count clock buffer logic buffer logic spen osc start 0 1 7 rx9d 0 1 7 rx9d ferr ferr majority detect data msb lsb rsr rcreg async/sync sync/async master/slave sync enable fifo logic clk fifo rcie interrupt rx9 data bus sren/ cren/ start_bit async/sync detect
pic17c75x ds30264a-page 110 preliminary 1997 microchip technology inc. 14.1 usart b aud rate generator (brg) the brg supports both the asynchronous and syn- chronous modes of the usart. it is a dedicated 8-bit baud rate generator. the spbrg register controls the period of a free running 8-bit timer. table 14-2 shows the formula for computation of the baud rate for differ- ent usart modes. these only apply when the usart is in synchronous master mode (internal clock) and asynchronous mode. given the desired baud rate and fosc, the nearest inte- ger value between 0 and 255 can be calculated using the formula below. the error in baud rate can then be determined. table 14-2: baud rate formula sync mode baud rate 0 1 asynchronous synchronous f osc /(64(x+1)) f osc /(4(x+1)) x = value in spbrg (0 to 255) example 14-1 shows the calculation of the baud rate error for the following conditions: f osc = 16 mhz desired baud rate = 9600 sync = 0 example 14-1: calculating baud rate error writing a new value to the spbrg, causes the brg timer to be reset (or cleared), this ensures that the brg does not wait for a timer over?w before outputting the new baud rate. desired baud rate=fosc / (64 (x + 1)) 9600 = 16000000 /(64 (x + 1)) x = 25.042 = 25 calculated baud rate=16000000 / (64 (25 + 1)) = 9615 error = (calculated baud rate - desired baud rate) desired baud rate = (9615 - 9600) / 9600 = 0.16% table 14-3: registers associated with baud rate generator address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (note1) usart1 13h, bank 0 rcsta1 spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00u 15h, bank 0 txsta1 csrc tx9 txen sync trmt tx9d 0000 --1x 0000 --1u 17h, bank 0 spbrg1 baud rate generator register xxxx xxxx uuuu uuuu usart2 13h, bank 4 rcsta2 spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00u 15h, bank 4 txsta2 csrc tx9 txen sync trmt tx9d 0000 --1x 0000 --1u 17h, bank 4 spbrg2 baud rate generator register xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used by the baud rate generator. note 1: other (non power-up) resets include: external reset through mclr and watchdog timer reset.
1997 microchip technology inc. preliminary ds30264a-page 111 pic17c75x table 14-4: baud rates for synchronous mode baud rate (k) f osc = 33 mhz spbrg value (decimal) f osc = 25 mhz spbrg value (decimal) f osc = 20 mhz spbrg value (decimal) f osc = 16 mhz spbrg value (decimal) kbaud %error kbaud %error kbaud %error kbaud %error 0.3 na na na na 1.2 na na na na 2.4 na na na na 9.6 na na na na 19.2 na na 19.53 +1.73 255 19.23 +0.16 207 76.8 77.10 +0.39 106 77.16 +0.47 80 76.92 +0.16 64 76.92 +0.16 51 96 95.93 -0.07 85 96.15 +0.16 64 96.15 +0.16 51 95.24 -0.79 41 300 294.64 -1.79 27 297.62 -0.79 20 294.1 -1.96 16 307.69 +2.56 12 500 485.29 -2.94 16 480.77 -3.85 12 500 0 9 500 0 7 high 8250 0 6250 0 5000 0 4000 0 low 32.22 255 24.41 255 19.53 255 15.625 255 baud rate (k) f osc = 10 mhz spbrg value (decimal) f osc = 7.159 mhz spbrg value (decimal) f osc = 5.068 mhz spbrg value (decimal) kbaud %error kbaud %error kbaud %error 0.3 na na na 1.2 na na na 2.4 na na na 9.6 9.766 +1.73 255 9.622 +0.23 185 9.6 0 131 19.2 19.23 +0.16 129 19.24 +0.23 92 19.2 0 65 76.8 75.76 -1.36 32 77.82 +1.32 22 79.2 +3.13 15 96 96.15 +0.16 25 94.20 -1.88 18 97.48 +1.54 12 300 312.5 +4.17 7 298.3 -0.57 5 316.8 +5.60 3 500 500 0 4 na ?a high 2500 0 1789.8 0 1267 0 low 9.766 255 6.991 255 4.950 255 baud rate (k) f osc = 3.579 mhz spbrg value (decimal) f osc = 1 mhz spbrg value (decimal) f osc = 32.768 khz spbrg value (decimal) kbaud %error kbaud %error kbaud %error 0.3 na na 0.303 +1.14 26 1.2 na 1.202 +0.16 207 1.170 -2.48 6 2.4 na 2.404 +0.16 103 na 9.6 9.622 +0.23 92 9.615 +0.16 25 na 19.2 19.04 -0.83 46 19.24 +0.16 12 na 76.8 74.57 -2.90 11 83.34 +8.51 2 na 96 99.43 _3.57 8 na na 300 298.3 -0.57 2 na na 500 na na na high 894.9 0 250 0 8.192 0 low 3.496 255 0.976 255 0.032 255
pic17c75x ds30264a-page 112 preliminary 1997 microchip technology inc. table 14-5: baud rates for asynchronous mode baud rate (k) f osc = 33 mhz spbrg value (decimal) f osc = 25 mhz spbrg value (decimal) f osc = 20 mhz spbrg value (decimal) f osc = 16 mhz spbrg value (decimal) kbaud %error kbaud %error kbaud %error kbaud %error 0.3 na na na na 1.2 na na 1.221 +1.73 255 1.202 +0.16 207 2.4 2.398 -0.07 214 2.396 0.14 162 2.404 +0.16 129 2.404 +0.16 103 9.6 9.548 -0.54 53 9.53 -0.76 40 9.469 -1.36 32 9.615 +0.16 25 19.2 19.09 -0.54 26 19.53 +1.73 19 19.53 +1.73 15 19.23 +0.16 12 76.8 73.66 -4.09 6 78.13 +1.73 4 78.13 +1.73 3 83.33 +8.51 2 96 103.12 +7.42 4 97.65 +1.73 3 104.2 +8.51 2 na 300 257.81 -14.06 1 390.63 +30.21 0 312.5 +4.17 0 na 500 515.62 +3.13 0 na na na high 515.62 0 0 312.5 0 250 0 low 2.014 255 1.53 255 1.221 255 0.977 255 baud rate (k) f osc = 10 mhz spbrg value (decimal) f osc = 7.159 mhz spbrg value (decimal) f osc = 5.068 mhz spbrg value (decimal) kbaud %error kbaud %error kbaud %error 0.3 na na 0.31 +3.13 255 1.2 1.202 +0.16 129 1.203 _0.23 92 1.2 0 65 2.4 2.404 +0.16 64 2.380 -0.83 46 2.4 0 32 9.6 9.766 +1.73 15 9.322 -2.90 11 9.9 -3.13 7 19.2 19.53 +1.73 7 18.64 -2.90 5 19.8 +3.13 3 76.8 78.13 +1.73 1 na 79.2 +3.13 0 96 na na na 300 na na na 500 na na na high 156.3 0 111.9 0 79.2 0 low 0.610 255 0.437 255 0.309 2 55 baud rate (k) f osc = 3.579 mhz spbrg value (decimal) f osc = 1 mhz spbrg value (decimal) f osc = 32.768 khz spbrg value (decimal) kbaud %error kbaud %error kbaud %error 0.3 0.301 +0.23 185 0.300 +0.16 51 0.256 -14.67 1 1.2 1.190 -0.83 46 1.202 +0.16 12 na 2.4 2.432 +1.32 22 2.232 -6.99 6 na 9.6 9.322 -2.90 5 na na 19.2 18.64 -2.90 2 na na 76.8 na na na 96 na na na 300 na na na 500 na na na high 55.93 0 15.63 0 0.512 0 low 0.218 255 0.061 255 0.002 255
1997 microchip technology inc. preliminary ds30264a-page 113 pic17c75x 14.2 usart a synchronous mode in this mode, the usart uses standard nonre- turn-to-zero (nrz) format (one start bit, eight or nine data bits, and one stop bit). the most common data for- mat is 8-bits. an on-chip dedicated 8-bit baud rate gen- erator can be used to derive standard baud rate frequencies from the oscillator. the usarts transmit- ter and receiver are functionally independent but use the same data format and baud rate. the baud rate generator produces a clock x64 of the bit shift rate. par- ity is not supported by the hardware, but can be imple- mented in software (and stored as the ninth data bit). asynchronous mode is stopped during sleep. the asynchronous mode is selected by clearing the sync bit (txsta<4>). the usart asynchronous module consists of the fol- lowing important elements: baud rate generator sampling circuit asynchronous transmitter asynchronous receiver 14.2.1 usart asynchronous transmitter the usart transmitter block diagram is shown in figure 14-3. the heart of the transmitter is the transmit shift register (tsr). the shift register obtains its data from the read/write transmit buffer (txreg). txreg is loaded with data in software. the tsr is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsr is loaded with new data from the txreg (if available). once txreg transfers the data to the tsr (occurs in one t cy at the end of the current brg cycle), the txreg is empty and an interrupt bit, txif, is set. this interrupt can be enabled/disabled by setting/clearing the txie bit. txif will be set regardless of txie and cannot be reset in software. it will reset only when new data is loaded into txreg. while txif indicates the status of the txreg, the trmt (txsta<1>) bit shows the status of the tsr. trmt is a read only bit which is set when the tsr is empty. no interrupt logic is tied to this bit, so the user has to poll this bit in order to deter- mine if the tsr is empty. note: the tsr is not mapped in data memory, so it is not available to the user. transmission is enabled by setting the txen (txsta<5>) bit. the actual transmission will not occur until txreg has been loaded with data and the baud rate generator (brg) has produced a shift clock (figure 14-5). the transmission can also be started by ?st loading txreg and then setting txen. normally when transmission is ?st started, the tsr is empty, so a transfer to txreg will result in an immediate transfer to tsr resulting in an empty txreg. a back-to-back transfer is thus possible (figure 14-6). clearing txen during a transmission will cause the transmission to be aborted. this will reset the transmitter and the tx/ck pin will revert to hi-impedance. in order to select 9-bit transmission, the tx9 (txsta<6>) bit should be set and the ninth bit value should be written to tx9d (txsta<0>). the ninth bit value must be written before writing the 8-bit data to the txreg. this is because a data write to txreg can result in an immediate transfer of the data to the tsr (if the tsr is empty). steps to follow when setting up an asynchronous transmission: 1. initialize the spbrg register for the appropriate baud rate. 2. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 3. if interrupts are desired, then set the txie bit. 4. if 9-bit transmission is desired, then set the tx9 bit. 5. load data to the txreg register. 6. if 9-bit transmission is selected, the ninth bit should be loaded in tx9d. 7. enable the transmission by setting txen (starts transmission). writing the transmit data to the txreg, then enabling the transmit (setting txen) allows transmission to start sooner than doing these two events in the opposite order. note: to terminate a transmission, either clear the spen bit, or the txen bit. this will reset the transmit logic, so that it will be in the proper state when transmit is re-enabled.
pic17c75x ds30264a-page 114 preliminary 1997 microchip technology inc. figure 14-5: asynchronous master transmission figure 14-6: asynchronous master transmission (back to back) table 14-6: registers associated with asynchronous transmission address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (note1) 16h, bank 1 pir1 rbif tmr3if tmr2if tmr1if ca2if ca1if tx1if rc1if 0000 0010 0000 0010 17h, bank 1 pie1 rbie tmr3ie tmr2ie tmr1ie ca2ie ca1ie tx1ie rc1ie 0000 0000 0000 0000 13h, bank 0 rcsta1 spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00u 16h, bank 0 txreg1 serial port transmit register (usart1) xxxx xxxx uuuu uuuu 15h, bank 0 txsta1 csrc tx9 txen sync trmt tx9d 0000 --1x 0000 --1u 17h, bank 0 spbrg1 baud rate generator register (usart1) xxxx xxxx uuuu uuuu 10h, bank 4 pir2 sspif bclif adif ca4if ca3if tx2if rc2if 000- 0010 000- 0010 11h, bank 4 pie2 sspie bclie adie ca4ie ca3ie tx2ie rc2ie 000- 0000 000- 0000 13h, bank 4 rcsta2 spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00u 16h, bank 4 txreg2 serial port transmit register (usart2) xxxx xxxx uuuu uuuu 15h, bank 4 txsta2 csrc tx9 txen sync trmt tx9d 0000 --1x 0000 --1u 17h, bank 4 spbrg2 baud rate generator register (usart2) xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for asynchronous transmission. note 1: other (non power-up) resets include: external reset through mclr and watchdog timer reset. word 1 stop bit word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txreg word 1 brg output (shift clock) tx txif bit trmt bit (tx/ck pin) transmit shift reg. write to txreg brg output (shift clock) tx txif bit trmt bit word 1 word 2 word 1 word 2 start bit stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions. (tx/ck pin)
1997 microchip technology inc. preliminary ds30264a-page 115 pic17c75x 14.2.2 usart asynchronous receiver the receiver block diagram is shown in figure 14-4. the data comes in the rx/dt pin and drives the data recovery block. the data recovery block is actually a high speed shifter operating at 16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at f osc . once asynchronous mode is selected, reception is enabled by setting bit cren (rcsta<4>). the heart of the receiver is the receive (serial) shift reg- ister (rsr). after sampling the stop bit, the received data in the rsr is transferred to the rcreg (if it is empty). if the transfer is complete, the interrupt bit, rcif, is set. the actual interrupt can be enabled/dis- abled by setting/clearing the rcie bit. rcif is a read only bit which is cleared by the hardware. it is cleared when rcreg has been read and is empty. rcreg is a double buffered register; (i.e. it is a two deep fifo). it is possible for two bytes of data to be received and transferred to the rcreg fifo and a third byte begin shifting to the rsr. on detection of the stop bit of the third byte, if the rcreg is still full, then the overrun error bit, oerr (rcsta<1>) will be set. the word in the rsr will be lost. rcreg can be read twice to retrieve the two bytes in the fifo. the oerr bit has to be cleared in software which is done by resetting the receive logic (cren is set). if the oerr bit is set, transfers from the rsr to rcreg are inhibited, so it is essential to clear the oerr bit if it is set. the framing error bit ferr (rcsta<2>) is set if a stop bit is not detected. 14.2.3 sampling the data on the rx/dt pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the rx/dt pin. the sampling is done on the seventh, eighth and ninth falling edges of a x16 clock (figure 14-7). the x16 clock is a free running clock, and the three sample points occur at a frequency of every 16 falling edges. note: the ferr and the 9th receive bit are buff- ered the same way as the receive data. reading the rcreg register will allow the rx9d and ferr bits to be loaded with val- ues for the next received received data. therefore, it is essential for the user to read the rcsta register before reading rcreg in order not to lose the old ferr and rx9d information. figure 14-7: rx pin sampling scheme rx baud clk x16 clk start bit bit0 samples 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 baud clk for all but start bit (rx/dt pin)
pic17c75x ds30264a-page 116 preliminary 1997 microchip technology inc. steps to follow when setting up an asynchronous reception: 1. initialize the spbrg register for the appropriate baud rate. 2. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 3. if interrupts are desired, then set the rcie bit. 4. if 9-bit reception is desired, then set the rx9 bit. 5. enable the reception by setting the cren bit. 6. the rcif bit will be set when reception com- pletes and an interrupt will be generated if the rcie bit was set. 7. read rcsta to get the ninth bit (if enabled) and ferr bit to determine if any error occurred dur- ing reception. 8. read rcreg for the 8-bit received data. 9. if an overrun error occurred, clear the error by clearing the oerr bit. note: to terminate a reception, either clear the sren and cren bits, or the spen bit. this will reset the receive logic, so that it will be in the proper state when receive is re-enabled. figure 14-8: asynchronous reception table 14-7: registers associated with asynchronous reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (note1) 16h, bank 1 pir1 rbif tmr3if tmr2if tmr1if ca2if ca1if tx1if rc1if 0000 0010 0000 0010 17h, bank 1 pie1 rbie tmr3ie tmr2ie tmr1ie ca2ie ca1ie tx1ie rc1ie 0000 0000 0000 0000 13h, bank 0 rcsta1 spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00u 14h, bank 0 rcreg1 rx7 rx6 rx5 rx4 rx3 rx2 rx1 rx0 xxxx xxxx uuuu uuuu 15h, bank 0 txsta1 csrc tx9 txen sync trmt tx9d 0000 --1x 0000 --1u 17h, bank 0 spbrg1 baud rate generator register xxxx xxxx uuuu uuuu 10h, bank 4 pir2 sspif bclif adif ca4if ca3if tx2if rc2if 000- 0010 000- 0010 11h, bank 4 pie2 sspie bclie adie ca4ie ca3ie tx2ie rc2ie 000- 0000 000- 0000 13h, bank 4 rcsta2 spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00u 14h, bank 4 rcreg2 rx7 rx6 rx5 rx4 rx3 rx2 rx1 rx0 xxxx xxxx uuuu uuuu 15h, bank 4 txsta2 csrc tx9 txen sync trmt tx9d 0000 --1x 0000 --1u 17h, bank 4 spbrg2 baud rate generator register xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for asynchronous reception. note 1: other (non power-up) resets include: external reset through mclr and watchdog timer reset. start bit bit7/8 bit1 bit0 bit7/8 bit0 stop bit start bit start bit bit7/8 stop bit rx reg rcv buffer reg rcv shift read rcv buffer reg rcreg rcif (interrupt ?g) oerr bit cren word 1 rcreg word 2 rcreg stop bit note: this timing diagram shows three words appearing on the rx input. the rcreg (receive buffer) is read after the third word, causing the oerr (overrun) bit to be set. (rx/dt pin) word 3
1997 microchip technology inc. preliminary ds30264a-page 117 pic17c75x 14.3 usart s ynchronous master mode in master synchronous mode, the data is transmitted in a half-duplex manner; i.e. transmission and reception do not occur at the same time: when transmitting data, the reception is inhibited and vice versa. the synchro- nous mode is entered by setting the sync (txsta<4>) bit. in addition, the spen (rcsta<7>) bit is set in order to con?ure the i/o pins to ck (clock) and dt (data) lines respectively. the master mode indicates that the processor transmits the master clock on the ck line. the master mode is entered by setting the csrc (txsta<7>) bit. 14.3.1 usart synchronous master transmission the usart transmitter block diagram is shown in figure 14-3. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer txreg. txreg is loaded with data in software. the tsr is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsr is loaded with new data from txreg (if available). once txreg transfers the data to the tsr (occurs in one t cy at the end of the current brg cycle), txreg is empty and the txif bit is set. this interrupt can be enabled/disabled by setting/clearing the txie bit. txif will be set regardless of the state of bit txie and cannot be cleared in software. it will reset only when new data is loaded into txreg. while txif indicates the status of txreg, trmt (txsta<1>) shows the status of the tsr. trmt is a read only bit which is set when the tsr is empty. no interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr is empty. the tsr is not mapped in data memory, so it is not available to the user. transmission is enabled by setting the txen (txsta<5>) bit. the actual transmission will not occur until txreg has been loaded with data. the ?st data bit will be shifted out on the next available rising edge of the clock on the tx/ck pin. data out is stable around the falling edge of the synchronous clock (figure 14-10). the transmission can also be started by ?st loading txreg and then setting txen. this is advantageous when slow baud rates are selected, since brg is kept in reset when the txen, cren, and sren bits are clear. setting the txen bit will start the brg, creating a shift clock immediately. normally when transmission is ?st started, the tsr is empty, so a transfer to txreg will result in an immediate transfer to the tsr, resulting in an empty txreg. back-to-back transfers are possible. clearing txen during a transmission will cause the transmission to be aborted and will reset the transmit- ter. the rx/dt and tx/ck pins will revert to hi-imped- ance. if either cren or sren are set during a transmission, the transmission is aborted and the rx/dt pin reverts to a hi-impedance state (for a recep- tion). the tx/ck pin will remain an output if the csrc bit is set (internal clock). the transmitter logic is not reset, although it is disconnected from the pins. in order to reset the transmitter, the user has to clear the txen bit. if the sren bit is set (to interrupt an ongoing trans- mission and receive a single word), then after the sin- gle word is received, sren will be cleared and the serial port will revert back to transmitting, since the txen bit is still set. the dt line will immediately switch from hi-impedance receive mode to transmit and start driving. to avoid this, txen should be cleared. in order to select 9-bit transmission, the tx9 (txsta<6>) bit should be set and the ninth bit should be written to tx9d (txsta<0>). the ninth bit must be written before writing the 8-bit data to txreg. this is because a data write to txreg can result in an immediate transfer of the data to the tsr (if the tsr is empty). if the tsr was empty and txreg was written before writing the ?ew tx9d, the ?resent value of tx9d is loaded. steps to follow when setting up a synchronous master transmission: 1. initialize the spbrg register for the appropriate baud rate (see baud rate generator section for details). 2. enable the synchronous master serial port by setting the sync, spen, and csrc bits. 3. ensure that the cren and sren bits are clear (these bits override transmission when set). 4. if interrupts are desired, then set the txie bit (the glintd bit must be clear and the peie bit must be set). 5. if 9-bit transmission is desired, then set the tx9 bit. 6. start transmission by loading data to the txreg register. 7. if 9-bit transmission is selected, the ninth bit should be loaded in tx9d. 8. enable the transmission by setting txen. writing the transmit data to the txreg, then enabling the transmit (setting txen) allows transmission to start sooner than doing these two events in the reverse order. note: to terminate a transmission, either clear the spen bit, or the txen bit. this will reset the transmit logic, so that it will be in the proper state when transmit is re-enabled.
pic17c75x ds30264a-page 118 preliminary 1997 microchip technology inc. table 14-8: registers associated with synchronous master transmission figure 14-9: synchronous transmission figure 14-10: synchronous transmission (through txen) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (note1) 16h, bank 1 pir1 rbif tmr3if tmr2if tmr1if ca2if ca1if tx1if rc1if 0000 0010 0000 0010 17h, bank 1 pie1 rbie tmr3ie tmr2ie tmr1ie ca2ie ca1ie tx1ie rc1ie 0000 0000 0000 0000 13h, bank 0 rcsta1 spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00u 16h, bank 0 txreg1 tx7 tx6 tx5 tx4 tx3 tx2 tx1 tx0 xxxx xxxx uuuu uuuu 15h, bank 0 txsta1 csrc tx9 txen sync trmt tx9d 0000 --1x 0000 --1u 17h, bank 0 spbrg1 baud rate generator register xxxx xxxx uuuu uuuu 10h, bank 4 pir2 sspif bclif adif ca4if ca3if tx2if rc2if 000- 0010 000- 0010 11h, bank 4 pie2 sspie bclie adie ca4ie ca3ie tx2ie rc2ie 000- 0000 000- 0000 13h, bank 4 rcsta2 spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00u 16h, bank 4 txreg2 tx7 tx6 tx5 tx4 tx3 tx2 tx1 tx0 xxxx xxxx uuuu uuuu 15h, bank 4 txsta2 csrc tx9 txen sync trmt tx9d 0000 --1x 0000 --1u 17h, bank 4 spbrg2 baud rate generator register xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for synchronous master transmission. note 1: other (non power-up) resets include: external reset through mclr and watchdog timer reset. q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 q3 q4 dt ck write to txreg txif interrupt ?g trmt txen '1' write word 1 write word 2 bit0 bit1 bit2 bit7 bit0 word 1 word 2 (rx/dt pin) (tx/ck pin) dt ck write to txreg txif bit trmt bit bit0 bit1 bit2 bit6 bit7 (rx/dt pin) (tx/ck pin)
1997 microchip technology inc. preliminary ds30264a-page 119 pic17c75x 14.3.2 usart synchronous master reception once synchronous mode is selected, reception is enabled by setting either the sren (rcsta<5>) bit or the cren (rcsta<4>) bit. data is sampled on the rx/dt pin on the falling edge of the clock. if sren is set, then only a single word is received. if cren is set, the reception is continuous until cren is reset. if both bits are set, then cren takes precedence. after clock- ing the last bit, the received data in the receive shift register (rsr) is transferred to rcreg (if it is empty). if the transfer is complete, the interrupt bit rcif is set. the actual interrupt can be enabled/disabled by set- ting/clearing the rcie bit. rcif is a read only bit which is reset by the hardware. in this case it is reset when rcreg has been read and is empty. rcreg is a dou- ble buffered register; i.e., it is a two deep fifo. it is possible for two bytes of data to be received and trans- ferred to the rcreg fifo and a third byte to begin shifting into the rsr. on the clocking of the last bit of the third byte, if rcreg is still full, then the overrun error bit oerr (rcsta<1>) is set. the word in the rsr will be lost. rcreg can be read twice to retrieve the two bytes in the fifo. the oerr bit has to be cleared in software. this is done by clearing the cren bit. if oerr is set, transfers from rsr to rcreg are inhibited, so it is essential to clear the oerr bit if it is set. the 9th receive bit is buffered the same way as the receive data. reading the rcreg register will allow the rx9d and ferr bits to be loaded with values for the next received data; therefore, it is essential for the user to read the rcsta register before reading rcreg in order not to lose the old ferr and rx9d information. steps to follow when setting up a synchronous master reception: 1. initialize the spbrg register for the appropriate baud rate. see section 14.1 for details. 2. enable the synchronous master serial port by setting bits sync, spen, and csrc. 3. if interrupts are desired, then set the rcie bit. 4. if 9-bit reception is desired, then set the rx9 bit. 5. if a single reception is required, set bit sren. for continuous reception set bit cren. 6. the rcif bit will be set when reception is com- plete and an interrupt will be generated if the rcie bit was set. 7. read rcsta to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. read the 8-bit received data by reading rcreg. 9. if any error occurred, clear the error by clearing cren. note: to terminate a reception, either clear the sren and cren bits, or the spen bit. this will reset the receive logic, so that it will be in the proper state when receive is re-enabled. figure 14-11: synchronous reception (master mode, sren) cren bit dt ck write to the sren bit sren bit rcif bit read rcreg note: timing diagram demonstrates sync master mode with sren = 1. q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4 '0' bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 '0' q1 q2 q3 q4 (rx/dt pin) (tx/ck pin)
pic17c75x ds30264a-page 120 preliminary 1997 microchip technology inc. table 14-9: registers associated with synchronous master reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (note1) 16h, bank 1 pir1 rbif tmr3if tmr2if tmr1if ca2if ca1if tx1if rc1if 0000 0010 0000 0010 17h, bank 1 pie1 rbie tmr3ie tmr2ie tmr1ie ca2ie ca1ie tx1ie rc1ie 0000 0000 0000 0000 13h, bank 0 rcsta1 spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00u 14h, bank 0 rcreg1 rx7 rx6 rx5 rx4 rx3 rx2 rx1 rx0 xxxx xxxx uuuu uuuu 15h, bank 0 txsta1 csrc tx9 txen sync trmt tx9d 0000 --1x 0000 --1u 17h, bank 0 spbrg1 baud rate generator register xxxx xxxx uuuu uuuu 10h, bank 4 pir2 sspif bclif adif ca4if ca3if tx2if rc2if 000- 0010 000- 0010 11h, bank 4 pie2 sspie bclie adie ca4ie ca3ie tx2ie rc2ie 000- 0000 000- 0000 13h, bank 4 rcsta2 spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00u 14h, bank 4 rcreg2 rx7 rx6 rx5 rx4 rx3 rx2 rx1 rx0 xxxx xxxx uuuu uuuu 15h, bank 4 txsta2 csrc tx9 txen sync trmt tx9d 0000 --1x 0000 --1u 17h, bank 4 spbrg2 baud rate generator register xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for synchronous master reception. note 1: other (non power-up) resets include: external reset through mclr and watchdog timer reset.
1997 microchip technology inc. preliminary ds30264a-page 121 pic17c75x 14.4 usart s ync hronous slave mode the synchronous slave mode differs from the master mode in the fact that the shift clock is supplied exter- nally at the tx/ck pin (instead of being supplied inter- nally in the master mode). this allows the device to transfer or receive data in the sleep mode. the slave mode is entered by clearing the csrc (txsta<7>) bit. 14.4.1 usart synchronous slave transmit the operation of the sync master and slave modes are identical except in the case of the sleep mode. if two words are written to txreg and then the sleep instruction executes, the following will occur. the ?st word will immediately transfer to the tsr and will trans- mit as the shift clock is supplied. the second word will remain in txreg. txif will not be set. when the ?st word has been shifted out of tsr, txreg will transfer the second word to the tsr and the txif ?g will now be set. if txie is enabled, the interrupt will wake the chip from sleep and if the global interrupt is enabled, then the program will branch to interrupt vector (0020h). steps to follow when setting up a synchronous slave transmission: 1. enable the synchronous slave serial port by set- ting the sync and spen bits and clearing the csrc bit. 2. clear the cren bit. 3. if interrupts are desired, then set the txie bit. 4. if 9-bit transmission is desired, then set the tx9 bit. 5. start transmission by loading data to txreg. 6. if 9-bit transmission is selected, the ninth bit should be loaded in tx9d. 7. enable the transmission by setting txen. writing the transmit data to the txreg, then enabling the transmit (setting txen) allows transmission to start sooner than doing these two events in the reverse order. note: to terminate a transmission, either clear the spen bit, or the txen bit. this will reset the transmit logic, so that it will be in the proper state when transmit is re-enabled. 14.4.2 usart synchronous slave reception operation of the synchronous master and slave modes are identical except in the case of the sleep mode. also, sren is a don't care in slave mode. if receive is enabled (cren) prior to the sleep instruc- tion, then a word may be received during sleep. on completely receiving the word, the rsr will transfer the data to rcreg (setting rcif) and if the rcie bit is set, the interrupt generated will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector (0020h). steps to follow when setting up a synchronous slave reception: 1. enable the synchronous master serial port by setting the sync and spen bits and clearing the csrc bit. 2. if interrupts are desired, then set the rcie bit. 3. if 9-bit reception is desired, then set the rx9 bit. 4. to enable reception, set the cren bit. 5. the rcif bit will be set when reception is com- plete and an interrupt will be generated if the rcie bit was set. 6. read rcsta to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. read the 8-bit received data by reading rcreg. 8. if any error occurred, clear the error by clearing the cren bit. note: to abort reception, either clear the spen bit, the sren bit (when in single receive mode), or the cren bit (when in continu- ous receive mode). this will reset the receive logic, so that it will be in the proper state when receive is re-enabled.
pic17c75x ds30264a-page 122 preliminary 1997 microchip technology inc. table 14-10: registers associated with synchronous slave transmission table 14-11: registers associated with synchronous slave reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (note1) 16h, bank 1 pir1 rbif tmr3if tmr2if tmr1if ca2if ca1if tx1if rc1if 0000 0010 0000 0010 17h, bank 1 pie1 rbie tmr3ie tmr2ie tmr1ie ca2ie ca1ie tx1ie rc1ie 0000 0000 0000 0000 13h, bank 0 rcsta1 spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00u 15h, bank 0 txsta1 csrc tx9 txen sync trmt tx9d 0000 --1x 0000 --1u 16h, bank 0 txreg1 tx7 tx6 tx5 tx4 tx3 tx2 tx1 tx0 xxxx xxxx uuuu uuuu 17h, bank 0 spbrg1 baud rate generator register xxxx xxxx uuuu uuuu 10h, bank 4 pir2 sspif bclif adif ca4if ca3if tx2if rc2if 000- 0010 000- 0010 11h, bank 4 pie2 sspie bclie adie ca4ie ca3ie tx2ie rc2ie 000- 0000 000- 0000 13h, bank 4 rcsta2 spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00u 16h, bank 4 txreg2 tx7 tx6 tx5 tx4 tx3 tx2 tx1 tx0 xxxx xxxx uuuu uuuu 15h, bank 4 txsta2 csrc tx9 txen sync trmt tx9d 0000 --1x 0000 --1u 17h, bank 4 spbrg2 baud rate generator register xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for synchronous slave transmission. note 1: other (non power-up) resets include: external reset through mclr and watchdog timer reset. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (note1) 16h, bank1 pir1 rbif tmr3if tmr2if tmr1if ca2if ca1if tx1if rc1if 0000 0010 0000 0010 17h, bank1 pie1 rbie tmr3ie tmr2ie tmr1ie ca2ie ca1ie tx1ie rc1ie 0000 0000 0000 0000 13h, bank0 rcsta1 spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00u 14h, bank0 rcreg1 rx7 rx6 rx5 rx4 rx3 rx2 rx1 rx0 xxxx xxxx uuuu uuuu 15h, bank 0 txsta1 csrc tx9 txen sync trmt tx9d 0000 --1x 0000 --1u 17h, bank 0 spbrg1 baud rate generator register xxxx xxxx uuuu uuuu 10h, bank 4 pir2 sspif bclif adif ca4if ca3if tx2if rc2if 000- 0010 000- 0010 11h, bank 4 pie2 sspie bclie adie ca4ie ca3ie tx2ie rc2ie 000- 0000 000- 0000 13h, bank 4 rcsta2 spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00u 14h, bank 4 rcreg2 rx7 rx6 rx5 rx4 rx3 rx2 rx1 rx0 xxxx xxxx uuuu uuuu 15h, bank 4 txsta2 csrc tx9 txen sync trmt tx9d 0000 --1x 0000 --1u 17h, bank 4 spbrg2 baud rate generator register xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for synchronous slave reception. note 1: other (non power-up) resets include: external reset through mclr and watchdog timer reset.
1997 microchip technology inc. preliminary ds30264a-page 123 pic17c75x 15.0 synchronous serial port (ssp) module the synchronous serial port (ssp) module is a serial interface useful for communicating with other periph- eral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, dis- play drivers, a/d converters, etc. the ssp module can operate in one of two modes: serial peripheral interface (spi) inter-integrated circuit (i 2 c) refer to application note an578, "use of the ssp module in the i 2 c multi-master environment." figure 15-1, figure 15-2, and figure 15-3 show the block diagrams for the three different modes of opera- tion. figure 15-1: spi mode block diagram read write internal data bus sspsr reg sspbuf reg sspm3:sspm0 bit0 shift clock ss control enable edge select clock select tmr2 output t osc prescaler 4, 16, 64 2 edge select 2 4 data to tx/rx in sspsr data direction bit 2 smp:cke sdi sdo ss sck figure 15-2: i 2 c slave mode block diagram figure 15-3: i 2 c master mode block diagram read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg) scl shift clock msb lsb sda read write sspsr reg match detect sspadd reg start and stop bit detect / generate sspbuf reg internal data bus addr match set/clear s bit clear/set p, bits (sspstat reg) scl shift clock msb lsb sda baud rate generator 7 sspadd<6:0> and and set sspif
pic17c75x ds30264a-page 124 preliminary 1997 microchip technology inc. figure 15-4: sspstat: sync serial port status register (address: 13h, bank 6) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a p s r/w ua bf r = readable bit w = writable bit u = unimplemented bit, read as ? - n =value at por reset bit7 bit0 bit 7: smp: spi data input sample phase spi master mode 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi sla v e mode smp must be cleared when spi is used in slave mode in i 2 c master or sla v e mode: 1= slew rate control disabled for standard speed mode (100 khz and 1 mhz) 0= slew rate control enabled for high speed mode (400 khz) bit 6: cke : spi clock edge select (figure 15-8, figure 15-11, and figure 15-12) ckp = 0 1 = data transmitted on rising edge of sck 0 = data transmitted on falling edge of sck ckp = 1 1 = data transmitted on falling edge of sck 0 = data transmitted on rising edge of sck bit 5: d/a : data/address bit (i 2 c slave mode only) 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4: p : stop bit (i 2 c mode only. this bit is cleared when the ssp module is disabled, sspen is cleared) 1 = indicates that a stop bit has been detected last (this bit is '0' on reset) 0 = stop bit was not detected last bit 3: s : start bit (i 2 c mode only. this bit is cleared when the ssp module is disabled, sspen is cleared) 1 = indicates that a start bit has been detected last (this bit is '0' on reset) 0 = start bit was not detected last bit 2: r/w : read/write bit information (i 2 c mode only) this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit, or a ck bit. in i 2 c sla v e mode: 1 = read 0 = write in i 2 c master mode: 1 = transmit is in progress 0 = transmit is not in progress. or?ng this bit with sae, rce, spe, or ake will indicate if the ssp is in idle mode. bit 1: ua : update address (10-bit i 2 c slave mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0: bf : buffer full status bit receiv e (spi and i 2 c modes) 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty t r ansmit (i 2 c mode only) 1 = data transmit in progress (does not include a ck and stop bits), sspbuf is full 0 = data transmit complete (does not include a ck and stop bits), sspbuf is empty
1997 microchip technology inc. preliminary ds30264a-page 125 pic17c75x figure 15-5: sspcon1: sync serial port control register1 (address 11h, bank 6) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 r = readable bit w = writable bit u = unimplemented bit, read as ? - n =value at por reset bit7 bit0 bit 7: wcol : write collision detect bit master mode: 1 = a write to the sspbuf register was attempted while the i 2 c conditions were not valid for a transmission to be started 0 = no collision sla v e mode: 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6: sspov : receive over?w indicator bit in spi mode 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of over- ?w, the data in sspsr is lost. over?w can only occur in slave mode. the user must read the sspbuf, even if only transmitting data, to avoid setting over?w. in master mode the over?w bit is not set since each new reception (and transmission) is initiated by writing to the sspbuf register. 0 = no over?w in i 2 c mode 1 = a byte is received while the sspbuf register is still holding the previous byte. sspov is a "don? care" in transmit mode. sspov must be cleared in software in either mode. 0 = no over?w bit 5: sspen : synchronous serial port enable bit in spi mode 1 = enables serial port and con?ures sck, sdo, and sdi as serial port pins 0 = disables serial port and con?ures these pins as i/o port pins in i 2 c mode 1 = enables the serial port and con?ures the sda and scl pins as serial port pins 0 = disables serial port and con?ures these pins as i/o port pins note: in both modes, when enabled, these pins must be properly con?ured as input or output. bit 4: ckp : clock polarity select bit in spi mode 1 = idle state for clock is a high level 0 = idle state for clock is a low level in i 2 c sla v e mode sck release control 1 = enable clock 0 = holds clock low (clock stretch) (used to ensure data setup time) in i 2 c master mode unused in this mode bit 3-0: sspm3:sspm0 : synchronous serial port mode select bits 0000 = spi master mode, clock = f osc /4 0001 = spi master mode, clock = f osc /16 0010 = spi master mode, clock = f osc /64 0011 = spi master mode, clock = tmr2 output/2 0100 = spi slave mode, clock = sck pin. ss pin control enabled. 0101 = spi slave mode, clock = sck pin. ss pin control disabled. ss can be used as i/o pin 0110 = i 2 c slave mode, 7-bit address 0111 = i 2 c slave mode, 10-bit address 1000 = i 2 c master mode, clock = f osc / (4 * (sspadd+1) ) 1xx1 = reserved 1x1x = reserved
pic17c75x ds30264a-page 126 preliminary 1997 microchip technology inc. figure 15-6: sspcon2: sync serial port control register2 (address 12h, bank 6) r/w-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gcen ackstat ackdt acken rcen pen rsen sen r = readable bit w = writable bit u = unimplemented bit, read as ? - n =value at por reset bit7 bit0 bit 7: gcen : general call enable bit (in i 2 c slave mode only) 1 = enable interrupt when a general call address is received in the sspsr. 0 = general call address disabled. bit 6: ackstat : acknowledge status bit (in i 2 c master mode only) in master transmit mode: 1 = acknowledge was not received from slave 0 = acknowledge was received from slave bit 5: ackdt : acknowledge data bit (in i 2 c master mode only) in master receive mode: value that will be transmitted when the user initiates an acknowledge sequence at the end of a receive. 1 = not acknowledge 0 = acknowledge bit 4: acken : acknowledge sequence enable bit (in i 2 c master mode only). in master receive mode: 1 = initiate acknowledge sequence on sda and scl pins, and transmit akd data bit. automatically cleared by hardware. 0 = acknowledge sequence idle note: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling), and the sspbuf may not be written (or writes to the sspbuf are disabled). bit 3: rcen : receive enable bit (in i 2 c master mode only). 1 = enables receive mode for i 2 c 0 = receive idle note: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling), and the sspbuf may not be written (or writes to the sspbuf are disabled). bit 2: pen : stop condition enable bit (in i 2 c master mode only). sck release control 1 = initiate stop condition on sda and scl pins. automatically cleared by hardware. 0 = stop condition idle note: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling), and the sspbuf may not be written (or writes to the sspbuf are disabled). bit 1: rsen : restart condition enabled bit (in i 2 c master mode only) 1 = initiate restart condition on sda and scl pins. automatically cleared by hardware. 0 = restart condition idle. note: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling), and the sspbuf may not be written (or writes to the sspbuf are disabled) bit 0: sen : start condition enabled bit (in i 2 c master mode only) 1 = initiate start condition on sda and scl pins. automatically cleared by hardware. 0 = start condition idle. note: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling), and the sspbuf may not be written (or writes to the sspbuf are disabled).
1997 microchip technology inc. preliminary ds30264a-page 127 pic17c75x 15.1 s pi mode the spi mode allows 8-bits of data to be synchro- nously transmitted and received simultaneously. all four modes of spi are supported. to accomplish com- munication, typically three pins are used: serial data out (sdo) serial data in (sdi) serial clock (sck) additionally a fourth pin may be used when in a slave mode of operation: slave select (ss ) when initializing the spi, several options need to be speci?d. this is done by programming the appropriate control bits in the sspcon1 register (sspcon1<5:0>) and sspstat<7:6>. these control bits allow the following to be speci?d: master mode (sck is the clock output) slave mode (sck is the clock input) clock polarity (idle state of sck) data input sample phase (middle or end of data output time) clock edge (output data on rising/falling edge of sck) clock rate (master mode only) slave select mode (slave mode only) the ssp consists of a transmit/receive shift register (sspsr) and a buffer register (sspbuf). the sspsr shifts the data in and out of the device, msb first. the sspbuf holds the data that was written to the sspsr, until the received data is ready. once the 8-bits of data have been received, that byte is moved to the sspbuf register. then the buffer full detect bit bf (sspstat<0>) and the interrupt ?g bit sspif (pir2<7>) are set. this double buffering of the received data (sspbuf) allows the next byte to start reception before reading the data that was just received. any write to the sspbuf register during transmission/reception of data will be ignored, and the write collision detect bit wcol (sspcon1<7>) will be set. user software must clear the wcol bit so that it can be determined if the following write(s) to the ssp- buf register completed successfully. when the application software is expecting to receive valid data, the sspbuf should be read before the next byte of data to transfer is written to the sspbuf. buffer full bit bf (sspstat<0>) indicates when sspbuf has been loaded with the received data (transmission is complete). when the sspbuf is read, bit bf is cleared. this data may be irrelevant if the spi is only a transmitter. generally the ssp interrupt is used to determine when the transmission/reception has com- pleted. the sspbuf must be read and/or written. if the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. example 15-1 shows the loading of the sspbuf (sspsr) for data transmission. the shaded instruction is only required if the received data is mean- ingful. example 15-1: loading the sspbuf (sspsr) register movlb 6 ; bank 6 loop btfss sspstat, bf ; has data been ; received ; (transmit ; complete)? goto loop ; no movpf sspbuf, rxdata ; save in user ram movfp txdata, sspbuf ; new data to xmit
pic17c75x ds30264a-page 128 preliminary 1997 microchip technology inc. the block diagram of the ssp module, when in spi mode (figure 15-7), shows that the sspsr is not directly readable or writable, and can only be accessed by addressing the sspbuf register. additionally, the ssp status register (sspstat) indicates the various status conditions. figure 15-7: ssp block diagram (spi mode) read write internal data bus sspsr reg sspbuf reg sspm3:sspm0 bit0 shift clock ss control enable edge select clock select tmr2 output t osc prescaler 4, 16, 64 2 edge select 2 4 data to tx/rx in sspsr data direction bit 2 smp:cke sdi sdo ss sck to enable the serial port, ssp enable bit, sspen (sspcon1<5>) must be set. to reset or recon?ure spi mode, clear bit sspen, re-initialize the sspcon registers, and then set bit sspen. this con?ures the sdi, sdo, sck, and ss pins as serial port pins. for the pins to behave as the serial port function, some must have their data direction bits (in the ddr register) appropriately programmed. that is: sdi is automatically controlled by the spi module sdo must have ddrb<7> cleared sck (master mode) must have ddrb<6> cleared sck (slave mode) must have ddrb<6> set ?s must have porta<2> set any serial port function that is not desired may be over- ridden by programming the corresponding data direc- tion (ddr) register to the opposite value. an example would be in master mode where you are only sending data (to a display driver), then both sdi and ss could be used as general purpose open drain outputs by writ- ing a ?? figure 15-9 shows a typical connection between two microcontrollers. the master controller (processor 1) initiates the data transfer by sending the sck signal. data is shifted out of both shift registers on their pro- grammed clock edge, and latched on the opposite edge of the clock. both processors should be pro- grammed to same clock polarity (ckp), then both con- trollers would send and receive data at the same time. whether the data is meaningful (or dummy data) depends on the application software. this leads to three scenarios for data transmission: master sends data slave sends dummy data master sends data slave sends data master sends dummy data slave sends data note: the ss pin must be con?ured as an input for the slave select to operate. this is done by writing a ? to porta<2>.
1997 microchip technology inc. preliminary ds30264a-page 129 pic17c75x 15.1.1 master mode the master can initiate the data transfer at any time because it controls the sck. the master determines when the slave (processor 2, figure 15-9) is to broad- cast data by the software protocol. in master mode the data is transmitted/received as soon as the sspbuf register is written to. if the spi is only going to receive, the sck output could be disabled (programmed as an input). the sspsr register will continue to shift in the signal present on the sdi pin at the programmed clock rate. as each byte is received, it will be loaded into the sspbuf register as if a normal received byte (interrupts and status bits appropriately set). this could be useful in receiver applications as a ?ine activity monitor mode. the clock polarity is selected by appropriately program- ming bit ckp (sspcon1<4>). this then would give waveforms for spi communication as shown in figure 15-8, figure 15-11, and figure 15-12 where the msb is transmitted ?st. in master mode, the spi clock rate (bit rate) is user programmable to be one of the fol- lowing: ? osc /4 (or t cy ) ? osc /16 (or 4 ?t cy ) ? osc /64 (or 16 ?t cy ) timer2 output/2 this allows a maximum bit clock frequency (at 33 mhz) of 8.25 mhz. figure 15-8 shows the waveforms for master mode. when cke = 1, the sdo data is valid before there is a clock edge on sck. the change of the input sample is shown based on the state of the smp bit. the time when the sspbuf is loaded with the received data is shown. figure 15-8: spi mode timing (master mode) sck (ckp = 0 sck (ckp = 1 sck (ckp = 0 sck (ckp = 1 4 clock modes input sample input sample sdi bit7 bit0 sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit0 sdi sspif (smp = 1) (smp = 0) (smp = 1) cke = 1) cke = 0) cke = 1) cke = 0) (smp = 0) write to sspbuf sspsr to sspbuf sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 (cke = 0) (cke = 1)
pic17c75x ds30264a-page 130 preliminary 1997 microchip technology inc. 15.1.2 slave mode in slave mode, the data is transmitted and received as the external clock pulses appear on sck. when the last bit is latched the interrupt ?g bit sspif (pir2<7>) is set. while in slave mode the external clock is supplied by the external clock source on the sck pin. this external clock must meet the minimum high and low times as speci?d in the electrical speci?ations. while in sleep mode, the slave can transmit/receive data and wake the device from sleep. 15.1.3 slave select synchronization the ss pin allows a synchronous slave mode. the spi must be in slave mode with ss pin control enabled (sspcon1<3:0> = 04h). the pin must not be driven low for the ss pin to function as an input. the ra2 data latch must be high. when the ss pin is low, transmission and reception are enabled and the sdo pin is driven. when the ss pin goes high, the sdo pin is no longer driven, even if in the middle of a transmitted byte, and becomes a ?ating output. external pull-up/ pull-down resistors may be desirable, depending on the application. to emulate two-wire communication, the sdo pin can be connected to the sdi pin. when the spi needs to operate as a receiver the sdo pin can be con?ured as an input. this disables transmissions from the sdo. the sdi can always be left as an input (sdi function) since it cannot create a bus con?ct. in figure 15-11 the ss pin terminates the transmis- sion/reception. the sspif bit is set after the last edge of the sck. in figure 15-12 the ss pin causes the ?st bit of the data to be output. the sspif bit in set after the last sck edge. note: when the spi is in slave mode with ss pin control enabled, (sspcon<3:0> = 0100 ) the spi module will reset if the ss pin is set to v dd . note: if the spi is used in slave mode with cke = '1', then the ss pin control must be enabled. figure 15-9: spi master/slave connection serial input buffer (sspbuf) shift register (sspsr) msb lsb sdo sdi processor 1 sck spi master sspm3:sspm0 = 00xx b serial input buffer (sspbuf) shift register (sspsr) lsb msb sdi sdo processor 2 sck spi slave sspm3:sspm0 = 010x b serial clock
1997 microchip technology inc. preliminary ds30264a-page 131 pic17c75x figure 15-10: slave synchronization timing sck (ckp = 1 sck (ckp = 0 input sample sdi bit7 sdo bit7 bit6 bit7 sspif interrupt (smp = 0) cke = 0) cke = 0) (smp = 0) write to sspbuf sspsr to sspbuf ss flag optional bit0 bit7 bit0
pic17c75x ds30264a-page 132 preliminary 1997 microchip technology inc. figure 15-11: spi mode timing (slave mode with cke = 0) sck (ckp = 1 sck (ckp = 0 input sample sdi bit7 bit0 sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sspif interrupt (smp = 0) cke = 0) cke = 0) (smp = 0) write to sspbuf sspsr to sspbuf ss flag optional
1997 microchip technology inc. preliminary ds30264a-page 133 pic17c75x figure 15-12: spi mode timing (slave mode with cke = 1) table 15-1: registers associated with spi operation address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (note1) 07h, unbanked intsta peif t0ckif t0if intf peie t0ckie t0ie inte 0000 0000 0000 0000 10h, bank 4 pir2 sspif bclif adif ca4if ca3if tx2if rc2if 000- 0010 000- 0010 11h, bank 4 pie2 sspie bclie adie ca4ie ca3ie tx2ie rc2ie 000- 0000 000- 0000 14h, bank 6 sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 11h, bank 6 sspcon1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 13h, bank 6 sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the ssp in spi mode. note 1: other (non power-up) resets include: external reset through mclr and watchdog timer reset. sck (ckp = 1 sck (ckp = 0 input sample sdi bit7 bit0 sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sspif interrupt (smp = 0) cke = 1) cke = 1) (smp = 0) write to sspbuf sspsr to sspbuf ss flag not optional
pic17c75x ds30264a-page 134 preliminary 1997 microchip technology inc. 15.2 ssp i 2 c operation the ssp module in i 2 c mode fully implements all mas- ter and slave functions (including general call support) and provides interrupts on start and stop bits in hard- ware to determine a free bus (multi-master function). the ssp module implements the standard mode spec- i?ations as well as 7-bit and 10-bit addressing. appendix e gives an overview of the i 2 c bus speci?a- tion. figure 15-13: ssp block diagram (i 2 c mode) figure 15-14: i 2 c master mode block diagram read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg) scl shift clock msb lsb sda read write sspsr reg match detect sspadd reg start and stop bit detect / generate sspbuf reg internal data bus addr match set/clear s bit clear/set p, bits (sspstat reg) scl shift clock msb lsb sda baud rate generator 7 sspadd<6:0> and and set sspif two pins are used for data transfer. these are the scl pin, which is the clock, and the sda pin, which is the data. pins that are on porta are automatically con?- ured when the i 2 c mode is enabled. the ssp module functions are enabled by setting ssp enable bit sspen (sspcon1<5>). the ssp module has six registers for i 2 c operation. these are the: ssp control register1 (sspcon1) ssp control register2 (sspcon2) ssp status register (sspstat) serial receive/transmit buffer (sspbuf) ssp shift register (sspsr) - not directly acces- sible ssp address register (sspadd) the sspcon1 register allows control of the i 2 c oper- ation. four mode selection bits (sspcon1<3:0>) allow one of the following i 2 c modes to be selected: ? 2 c slave mode (7-bit address) ? 2 c slave mode (10-bit address) ? 2 c master mode, clock = osc/4 (sspadd +1) selection of any i 2 c mode, with the sspen bit set, forces the scl and sda pins to be open drain. these pins are on porta and therefore there is no need to program to be inputs. the sspstat register gives the status of the data transfer. this information includes detection of a start or stop bit, speci?s if the received byte was data or address if the next byte is the completion of 10-bit address, and if this will be a read or write data transfer. the sspbuf is the register to which transfer data is written to or read from. the sspsr register shifts the data in or out of the device. in receive operations, the sspbuf and sspsr create a doubled buffered receiver. this allows reception of the next byte to begin before reading the last byte of received data. when the complete byte is received, it is transferred to the sspbuf register and ?g bit sspif is set. if another complete byte is received before the sspbuf register is read, a receiver over?w has occurred and bit sspov (sspcon1<6>) is set and the byte in the sspsr is lost. the sspadd register holds the slave address. in 10-bit mode, the user needs to write the high byte of the address ( 1111 0 a9 a8 0 ). following the high byte address match, the low byte of the address needs to be loaded (a7:a0).
1997 microchip technology inc. preliminary ds30264a-page 135 pic17c75x 15.2.1 slave mode in slave mode, the scl and sda pins must be con?- ured as inputs. the ssp module will override the input state with the output data when required (slave-trans- mitter). when an address is matched or the data transfer after an address match is received, the hardware automati- cally will generate the acknowledge (a ck ) pulse, and then load the sspbuf register with the received value currently in the sspsr register. there are certain conditions that will cause the ssp module not to give this a ck pulse. these are if either (or both): a) the buffer full bit bf (sspstat<0>) was set before the transfer was received. b) the over?w bit sspov (sspcon1<6>) was set before the transfer was received. in this case, the sspsr register value is not loaded into the sspbuf, but bit sspif (pir2<7>) is set. table 15-2 shows what happens when a data transfer byte is received, given the status of bits bf and sspov. the shaded cells show the condition where user software did not properly clear the over?w condi- tion. flag bit bf is cleared by reading the sspbuf reg- ister while bit sspov is cleared through software. the scl clock input must have a minimum high and low time for proper operation. the high and low times of the i 2 c speci?ation as well as the requirement of the ssp module is shown in timing parameter #100 and parameter #101. 15.2.1.1 addressing once the ssp module has been enabled, it waits for a start condition to occur. following the start condi- tion, the 8-bits are shifted into the sspsr register. all incoming bits are sampled with the rising edge of the clock (scl) line. the value of register sspsr<7:1> is compared to the value of the sspadd register. the address is compared on the falling edge of the eighth clock (scl) pulse. if the addresses match, and the bf and sspov bits are clear, the following events occur: a) the sspsr register value is loaded into the sspbuf register. b) the buffer full bit, bf is set. c) an a ck pulse is generated. d) ssp interrupt ?g bit, sspif (pir2<7>) is set (interrupt is generated if enabled) - on the falling edge of the ninth scl pulse. in 10-bit address mode, two address bytes need to be received by the slave. the ?e most signi?ant bits (msbs) of the ?st address byte specify if this is a 10-bit address. bit r/w (sspstat<2>) must specify a write so the slave device will receive the second address byte. for a 10-bit address the ?st byte would equal 1111 0 a9 a8 0 ? where a9 and a8 are the two msbs of the address. the sequence of events for a 10-bit address is as follows, with steps 7- 9 for slave-transmit- ter: 1. receive ?st (high) byte of address (bits sspif, bf, and bit ua (sspstat<1>) are set). 2. update the sspadd register with second (low) byte of address (clears bit ua and releases the scl line). 3. read the sspbuf register (clears bit bf) and clear ?g bit sspif. 4. receive second (low) byte of address (bits sspif, bf, and ua are set). 5. update the sspadd register with the ?st (high) byte of address, if match occurs releases the scl line, this will clear bit ua. 6. read the sspbuf register (clears bit bf) and clear ?g bit sspif. 7. receive repeated start condition. 8. receive ?st (high) byte of address (bits sspif and bf are set). 9. read the sspbuf register (clears bit bf) and clear ?g bit sspif. note: following the restart condition (step 7) in 10-bit mode, the user only needs to match the ?st 7-bit address. the user does not update the sspadd for the sec- ond half of the address. table 15-2: data transfer received byte actions status bits as data transfer is received sspsr ? sspbuf generate ack pulse set bit sspif (ssp interrupt occurs if enabled) bf sspov 00 ye s ye s ye s 10 no no yes 11 no no yes 0 1 no no ye s
pic17c75x ds30264a-page 136 preliminary 1997 microchip technology inc. 15.2.1.2 slave reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspstat register is cleared. the received address is loaded into the sspbuf register. when the address byte over?w condition exists, then no acknowledge (a ck ) pulse is given. an over?w con- dition is de?ed as either bit bf (sspstat<0>) is set or bit sspov (sspcon1<6>) is set. an ssp interrupt is generated for each data transfer byte. flag bit sspif (pir2<7>) must be cleared in soft- ware. the sspstat register is used to determine the status of the byte. note: the sspbuf will be loaded if the sspov bit = 1 and the bf ?g = 0. if a read of the sspbuf was performed, but the user did not clear the state of the sspov bit before the next receive occured. the a ck is not sent and the sspbuf is updated. 15.2.1.3 slave transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register. the a ck pulse will be sent on the ninth bit, and the sclpin is held low. the transmit data must be loaded into the sspbuf register, which also loads the sspsr register. then scl pin should be enabled by setting bit ckp (sspcon1<4>). the master must monitor the scl pin prior to asserting another clock pulse. the slave devices may be holding off the master by stretching the clock. the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time (figure 15-16). figure 15-15: i 2 c waveforms for reception (7-bit address) figure 15-16: i 2 c waveforms for transmission (7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 56 7 89 123 4 bus master terminates transfer bit sspov is set because the sspbuf register is still full. cleared in software sspbuf register is read a ck receiving data receiving data d0 d1 d2 d3 d4 d5 d6 d7 a ck r/w =0 receiving address sspif (pir2<7>) bf (sspstat<0>) sspov (sspcon1<6>) a ck a ck is not sent. sda scl sspif (pir1<3>) bf (sspstat<0>) ckp (sspcon1<4>) a7 a6 a5 a4 a3 a2 a1 a ck d7 d6 d5 d4 d3 d2 d1 d0 a ck transmitting data r/w = 1 receiving address 123456789 123456789 p cleared in software sspbuf is written in software from ssp interrupt service routine set bit after writing to sspbuf s data in sampled scl held low while cpu responds to sspif (the sspbuf must be written-to before the ckp bit can be set)
1997 microchip technology inc. preliminary ds30264a-page 137 pic17c75x figure 15-17: i 2 c slave-transmitter (10-bit address) 12345 789 p d7 d6 d5 d4 d3 d1 d0 a ck transmitting data bus master terminates transfer d2 6 cleared in software master sends nack transmit is complete write of sspbuf initiates transmit sda scl sspif bf (sspstat<0>) s 1 234 56 7 89 1 2345 67 89 1 2345 7 89 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1 a0 1 1 1 1 0 a8 r/w =1 a ck a ck r/w = 0 a ck receive first byte of address cleared in software a9 6 (pir1<3>) receive second byte of address cleared by hardware when sspadd is updated with low byte of address. ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address. sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf ag receive first byte of address dummy read of sspbuf to clear bf ag sr cleared in software ckp has to be set for clock to be released
pic17c75x ds30264a-page 138 preliminary 1997 microchip technology inc. figure 15-18: i 2 c slave-receiver (10-bit address) sda scl sspif bf (sspstat<0>) s 1 234 56 7 89 1 2345 67 89 1 1 1 1 0 a9a8 a7 a6 a5 a4a3a2a1 a0 a ck r/w = 0 a ck receive first byte of address cleared in software (pir1<3>) receive second byte of address cleared by hardware when sspadd is updated with low byte of address. ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf ag p bus master terminates transfer 12345 789 d7 d6 d5 d4 d3 d1 r/w=1 a ck d2 6 receive data byte d0 dummy read of sspbuf to clear bf ag cleared in software read of sspbuf clears bf ag
1997 microchip technology inc. preliminary ds30264a-page 139 pic17c75x an ssp interrupt is generated for each data transfer byte. flag bit sspif must be cleared in software, and the sspstat register is used to determine the status of the byte. flag bit sspif is set on the falling edge of the ninth clock pulse. as a slave-transmitter, the a ck pulse from the mas- ter-receiver is latched on the rising edge of the ninth scl input pulse. if the sda line was high (not a ck ), then the data transfer is complete. when the a ck is latched by the slave, the slave logic is reset and the slave then monitors for another occurrence of the start bit. if the sda line was low (a ck ), the transmit data must be loaded into the sspbuf register, which also loads the sspsr register. then the scl pin should be enabled by setting bit ckp. 15.2.2 general call address support the addressing procedure for the i 2 c bus is such that the ?st byte after the start condition usually deter- mines which device will be the slave addressed by the master. the exception is the general call address which can address all devices. when this address is used, all devices should, in theory, respond with an acknowledge. the general call address is one of eight addresses reserved for speci? purposes by the i 2 c protocol. it consists of all 0s with r/w = 0 the general call address is recognized when the gen- eral call enable bit (gcen) is enabled (sspcon2<7> = 1). following a start-bit detect, 8-bits are shifted into sspsr and the address is compared against sspadd, and is also compared to the general call address, ?ed in hardware. if the general call address matches, the sspsr is transfered to the sspbuf, the bf ?g is set (eigth bit), and on the falling edge of the ninth bit (a ck bit) the sspif interrupt is set. when the interrupt is serviced. the source for the interrupt can be checked by reading the contents of the sspbuf to determine if the address was device speci? or a general call address. in 10-bit mode, the sspadd is required to be updated for the second half of the address to match, and the ua bit is set (sspstat<1>). if the general call address is sampled when gcen = 1 while the slave is con?ured in 10-bit address mode, then the second half of the address is not necessary, the ua bit will not be set, and the slave will begin receiving data after the acknowledge (figure 15-19). figure 15-19: general call address sequence (7 or 10-bit mode) sda scl s sspif (pir2<7>) bf (sspstat<0>) sspov (sspcon1<6>) cleared in software sspbuf is read r/w = 0 ack general call address address is compared to general call address gcen (sspcon2<7>) receiving data ack 123456789123456789 d7 d6 d5 d4 d3 d2 d1 d0 after ack, set interrupt
pic17c75x ds30264a-page 140 preliminary 1997 microchip technology inc. table 15-3: registers associated with i 2 c operation address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (note 1) 07h, unbanked intsta peif t0ckif t0if intf peie t0ckie t0ie inte 0000 0000 0000 0000 10h, bank 4 pir2 sspif bclif adif ca4if ca3if tx2if rc2if 00-- 0000 00-- 0000 11h, bank 4 pie2 sspie bclie adie ca4ie ca3ie tx2ie rc2ie 00-- 0000 00-- 0000 10h. bank 6 sspadd synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 14h, bank 6 sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 11h, bank 6 sspcon1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 12h, bank 6 sspcon2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 0000 0000 13h, bank 6 sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the ssp in i 2 c mode. note 1: other (non power-up) resets include: external reset through mclr and watchdog timer reset.
1997 microchip technology inc. preliminary ds30264a-page 141 pic17c75x 15.2.3 master mode master mode of operation is supported by interrupt generation on the detection of the start and stop conditions. the stop (p) and start (s) bits are cleared from a reset or when the ssp module is dis- abled. control of the i 2 c bus may be taken when the p bit is set, or the bus is idle with both the s and p bits clear. in master mode, the scl and sda lines are manipu- lated by the ssp hardware. the following events will cause ssp interrupt flag bit, sspif, to be set (ssp interrupt if enabled): start condition stop condition data transfer byte transmitted/received figure 15-20: ssp block diagram (i 2 c master mode) read write sspsr start bit, stop bit, start bit detect, sspbuf internal data bus set/reset, s, p, wcol (sspstat) shift clock msb lsb sda acknowledge generate stop bit detect write collision detect clock arbitration state counter for end of xmit/rcv scl scl in bus collision sda in receive enable clock cntl clock arbitrate/wcol detect (hold off clock source) sspadd<6:0> baud set sspif, bclif reset acks tat, pen (sspcon2) rate generator sspm3:sspm0
pic17c75x ds30264a-page 142 preliminary 1997 microchip technology inc. 15.2.4 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the ssp module is disabled. control of the i 2 c bus may be taken when bit p (sspstat<4>) is set, or the bus is idle with both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will gener- ate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be moni- tored to see if the signal level is the expected output level. this check is performed in hardware, with the result placed in the bclif bit. the states where arbitration can be lost are: address transfer data transfer a start condition a restart condition an acknowledge condition 15.2.5 i 2 c master mode support master mode is enabled by setting and clearing the appropriate sspm bits in sspcon1 and by setting the sspen bit. once master mode is enabled, the user has six options. - assert a start condition on sda and scl. - assert a restart condition on sda and scl. - write to the sspbuf register initiating trans- mission of data/address. - generate a stop condition on sda and scl. - con?ure the i 2 c port to receive data. - generate an acknowledge condition at the end of a received byte of data. note: the ssp module when con?ured in i 2 c master mode does not allow queueing of events. for instance: the user is not allowed to intitiate a start condition, and immediately write the sspbuf register to initate transmission before the start con- dition is complete. in this case the ssp- buf will not be written to, and the wcol bit will be set, indicating that a write to the sspbuf did not occur. 15.2.5.1 i 2 c master mode operation the master device generates all of the serial clock pulses and the start and stop conditions. a trans- fer is ended with a stop condition or with a repeated start condition. since the repeated start condi- tion is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mode serial data is output through sda, while scl outputs the serial clock. the ?st byte transmitted contains the slave address of the receiving device, (7 bits) and the data direction bit. in this case the data direction bit (r/w ) will be logic '0'. serial data is transmitted 8 bits at a time. after each byte is transmitted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. in master receive mode the ?st byte transmitted con- tains the slave address of the transmitting device (7 bits) and the data direction bit. in this case the data direction bit (r/w ) will be logic '1'. thus the ?st byte transmitted is a 7-bit slave address followed by a '1' to indicate receive bit. serial data is received via sda while scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an acknowledge bit is transmitted. start and stop conditions indicate the beginning and end of transmis- sion. the baud rate generator used for spi mode operation is now used to set the scl clock frequency for either 100 khz, 400 khz, or 1 mhz i 2 c operation. the baud rate generator reload value is contained in the lower 7 bits of the sspadd register. the baud rate generator will automatically begin counting on a write to the sspbuf. once the given operation is complete (i.e. transmission of the last data bit is followed by ack) the internal clock will automatically stop counting and the scl pin will remain in its last state a typical transmit sequence would go as follows: 1. the user generates a start condition by setting the start enable bit (sen) in sspcon2. 2. sspif is set. the module will wait the required start time before any other operation takes place. 3. the user loads the sspbuf with address to transmit. 4. address is shifted out the sda pin until all 8 bits are transmitted. 5. the ssp module shifts in the ack bit from the slave device, and writes its value into the sspcon2 register ( sspcon2<6>). 6. the module generates an interrupt at the end of the ninth clock cycle by setting sspif. 7. the user loads the sspbuf with eight bits of data. 8. data is shifted out the sda pin until all 8 bits are transmitted.
1997 microchip technology inc. preliminary ds30264a-page 143 pic17c75x 9. the ssp module shifts in the ack bit from the slave device, and writes its value into the sspcon2 register ( sspcon2<6>). 10. the module generates an interrupt at the end of the ninth clock cycle by setting sspif. 11. the user generates a stop condition by setting the stop enable bit pen in sspcon2. 15.2.6 baud rate generator in i 2 c master mode, the reload value for the brg is located in the lower 7 bits of the sspadd register (figure 15-21). when the brg is loaded with this value, the brg counts down to 0 and stops until another reload has taken place. in i 2 c master mode, the brg is not reloaded automatically. if clock arbi- tration is taking place for instance, the brg will be reloaded when the scl pin is sampled high (figure 15-22). figure 15-21: baud rate generator block diagram figure 15-22: baud rate generator timing with clock arbitration sspm3:sspm0 brg down counter clkout fosc/4 sspadd<6:0> sspm3:sspm0 scl reload control reload sda scl scl deasserted but slave holds dx-1 dx brg scl is sampled high, reload takes place, and brg starts its count. 03h 02h 01h 00h 03h 02h reload brg value scl low (clock arbitration) scl allowed to transition high brg counts down brg counts down brg counts down 01h 00h note: there are two baud rate over?ws per clock period. clock period may be of variable time due to clock arbitration. xx 00h
pic17c75x ds30264a-page 144 preliminary 1997 microchip technology inc. 15.2.7 i 2 c master mode start condition timing to initiate a start condition the user sets the start condition enable bit or sen bit (sspcon2<0>). if the sda and scl pins are sampled high, the baud rate generator is re-loaded with the contents of sspadd<6:0>, and starts its count. if scl and sda are both sampled high when the baud rate generator times out (t brg ), the sda pin is driven low. the action of the sda being driven low while scl is high is the start condition, and causes the s bit (sspstat<3>) to be set. since the i 2 c module is con?ured in master mode, a '1' in the s bit causes the sspif ?g to be set. following this, the baud rate generator is reloaded with the contents of sspadd<6:0> and resumes its count. when the baud rate generator times out (t brg ) the sen bit in the sspcon2 register will be automati- cally cleared, the baud rate generator is suspended leaving the sda line held low, and the start condi- tion is complete. 15.2.7.1 wcol status flag if the user writes the sspbuf when an start sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesn? occur). note: if at the beginning of start condition the sda and scl pins are already sampled low, or if during the start condition the scl line is sampled low before the sda line is driven low, a bus collision occurs, the bus collision interrupt flag (bclif) is set, the start condition is aborted, and the i 2 c module is reset into its idle state. note: because queueing of events is not allowed, writing to the lower 5 bits of sspcon2 is disabled until the start condition is complete. figure 15-23: first start bit timing sda scl s t brg 1st bit 2nd bit t brg sda = 1, at completion of start bit, scl = 1 write to sspbuf occurs here t brg automatic clear sspcon2<0> t brg write to sspcon2<0> occurs here. set s bit (sspstat<3>)
1997 microchip technology inc. preliminary ds30264a-page 145 pic17c75x figure 15-24: start condition flowchart idle mode sen (sspcon2<0> = 1) bus collision detected, set bclif, sda = 1? load brg with ye s brg rollover? force sda = 0, load brg with sspadd<6:0>, no ye s force scl = 0, clear sen. set s bit and sspif. sspadd<6:0> scl = 1? sda = 0? no ye s brg rollover? no clear sen start condition done, no ye s reset brg scl= 0? no ye s scl = 0? no ye s reset brg release scl, sspen = 1, sspcon1<3:0> = 1000
pic17c75x ds30264a-page 146 preliminary 1997 microchip technology inc. 15.2.8 i 2 c master mode restart condition timing a restart condition occurs when the rsen bit (sspcon2<1>) is programmed high and the ssp module is in the idle state. when the rsen bit is set, the scl pin is asserted low. when the scl pin is sampled low, the baud rate generator is loaded with the contents of sspadd<5:0>, and begins counting. the sda pin is released (brought high) for one baud rate generator count (t brg ). when the baud rate gen- erator times out, if sda is sampled high, the scl pin will be de-asserted (brought high). when scl is sam- pled high the baud rate generator is re-loaded with the contents of sspadd<6:0> and begins counting. sda and scl must be sampled high for one t brg . this action is then followed by assertion of the sda pin (sda = 0) for one t brg while scl = 1. following this, the rsen bit in the sspcon2 register will be automatically cleared, and the baud rate generator is not reloaded, leaving the sda pin held low. as soon as a start condition is detected on the sda and scl pins, the s bit (sspstat<3>) will be set. the sspif bit will not be set until the baud rate generator has timed-out. note 1: if the rsen is programmed while a trans- mit is in progress, it will not take effect. note 2: a bus collision during the restart con- dition occurs if: ?da is sampled low when scl goes from low to high. ?cl goes low before sda is asserted low. this may indicate that another master is attempting to transmit a data "1". immediately following the sspif bit getting set, the user may write the sspbuf with the 7-bit address in 7-bit mode, or the default ?st address in 10-bit mode. after the ?st eight bits are transmitted and an ack is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode). after the write to the sspbuf, each bit of address will be shifted out on the falling edge of scl until all seven address bits and the r/w bit are completed. on the falling edge of the eighth clock the master will de-assert the sda pin allowing the slave to respond with an acknowledge. on the falling edge of the ninth clock the master will sample the sda pin to see if the address was recognized by a slave. the status of the ack bit is programmed into the akstat status bit sspcon2<6>. following the falling edge of the ninth clock transmission of the address, the sspif is set, the bf ?g is cleared, and the baud rate generator is turned off until another write to the sspbuf takes place, holding scl low and allowing sda to ?at. 15.2.8.1 wcol status flag if the user writes the sspbuf when a restart sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesn? occur). note: because queueing of events is not allowed, writing of the lower 5 bits of sspcon2 is disabled until the restart condition is complete. figure 15-25: repeat start condition timing sda scl sr = restart write to sspcon2 write to sspbuf occurs here. falling edge of ninth clock end of xmit at completion of start bit, automatic clear sspcon2<1> 1st bit set s (sspstat<3>) t brg t brg sda = 1, sda = 1, scl(no change) scl = 1 occurs here. t brg t brg t brg
1997 microchip technology inc. preliminary ds30264a-page 147 pic17c75x figure 15-26: restart condition flowchart (page 1) idle mode, sspen = 1, force scl = 0 scl = 0? release sda, load brg with scl = 1? no ye s no ye s brg no ye s release scl sspcon1<3:0> = 1000 rollover? sspadd<6:0> load brg with sspadd<6:0> (clock arbitration) a b c sda = 1? no ye s start rsen = 1(sspcon2<1>) bus collision, set bclif, release sda, clear rsen
pic17c75x ds30264a-page 148 preliminary 1997 microchip technology inc. figure 15-27: restart condition flowchart (page 2) force sda = 0, load brg with sspadd<6:0> ye s restart condition done, clear rsen ye s brg rollover? brg rollover? ye s sda = 0? no scl = 1? no b set s, set sspif c a no no ye s force scl = 0, reset brg
1997 microchip technology inc. preliminary ds30264a-page 149 pic17c75x 15.2.9 i 2 c master mode transmission transmission of a data byte, a 7-bit address, or the either half of a 10-bit address is accomplished by sim- ply writing a value to sspbuf register. this action will set the buffer full ?g (bf) and allow the baud rate generator to begin counting and start the next trans- mission. each bit of address/data will be shifted out onto the sda pin after the falling edge of scl is asserted (see data hold time spec). scl is held low for one baud rate generator roll over count (t brg ). data should be valid before scl is released high (see data setup time spec). when the scl pin is released high, it is held that way for t brg , the data on the sda pin must remain stable for that duration and some hold time after the next falling edge of scl. after the eighth bit is shifted out (the falling edge of the eighth clock), the bf ?g is cleared and the master releases sda allowing the slave device being addressed to respond with an a ck bit during the ninth bit time, if an address match occurs or if data was received properly. the status of a ck is read into the sspcon2 register bit6 on the falling edge of the ninth clock. if the master receives an acknowledge, the acknowledge status bit (akstat) is cleared. if not, the bit is set. after the ninth clock the sspif is set, and the master clock (baud rate generator) is suspended until the next data byte is loaded into the sspbuf leaving scl low and sda unchanged. (figure 15-29) 15.2.9.1 bf status flag in transmit mode, the bf bit (sspstat<0>) is set when the cpu writes to sspbuf and is cleared when all 8 bits are shifted out. 15.2.9.2 wcol status flag if the user writes the sspbuf when a transmit is already in progress (i.e. sspsr is still shifting out a data byte), then wcol is set and the contents of the buffer are unchanged (the write doesn? occur). wcol must be cleared in software. 15.2.9.3 akstat status flag in transmit mode, the akstat bit (sspcon2<6>) is cleared when the slave has sent an acknowledge (a ck = 0), and is set when the slave does not acknowledge (a ck = 1). a slave sends an acknowl- edge when it has recognized its address (including a general call), or when the slave has properly received its data.
pic17c75x ds30264a-page 150 preliminary 1997 microchip technology inc. figure 15-28: master transmit flowchart idle mode num_clocks = 0, release sda so slave can drive ack num_clocks load brg with sda = current data bit ye s brg rollover? no brg no ye s force scl = 0 = 8? ye s no ye s brg rollover? no force scl = 1, stop brg scl = 1? load brg with count high time rollover? no read sda and place into akstat bit (sspcon2<6>) force scl = 0, scl = 1? sda = data bit? no ye s ye s rollover? no ye s stop brg, force scl = 1 (clock arbitration) (clock arbitration) num_clocks = num_clocks + 1 bus collision detected set bclif, hold prescale off ye s no bf = 1 bf = 0, sspadd<6:0>, start brg count, load brg with sspadd<6:0>, start brg count sspadd<6:0>, load brg with count scl high time sspadd<6:0>, sda = data bit? ye s no clear xmit enable scl = 0? no ye s reset brg write sspbuf set sspif
1997 microchip technology inc. preliminary ds30264a-page 151 pic17c75x figure 15-29: i 2 c master mode timing (transmission, 7 or 10-bit address) sda scl sspif bf (sspstat<0>) sen a7 a6 a5 a4 a3 a2 a1 a ck = 0 d7 d6 d5 d4 d3 d2 d1 d0 a ck transmitting data or second half r/w = 0 transmit address to slave 123456789 123456789 p cleared in software service routine sspbuf is written in software from ssp interrupt after start condition sen cleared by hardware. s sspbuf written with 7 bit address and r/w start transmit scl held low while cpu responds to sspif sen = 0 of 10-bit address write sspcon2<0> sen = 1 start condition begins from slave clear akstat bit sspcon2<6> akstat in sspcon2 = 1 cleared in software sspbuf written pen cleared in software
pic17c75x ds30264a-page 152 preliminary 1997 microchip technology inc. 15.2.10 i 2 c master mode reception master mode reception is enabled by programming the receive enable bit, rcen (sspcon2<3>). the baud rate generator begins counting, and on each rollover, the state of the scl pin changes (high to low/low to high), and data is shifted into the sspsr. after the falling edge of the eighth clock, the receive enable ?g is automatically cleared, the contents of the sspsr are loaded into the sspbuf, the bf ?g is set, the sspif is set, and the baud rate generator is suspended from counting, holding scl low. the ssp is now in idle state, awaiting the next command. when the buffer is read by the cpu, the bf ?g is automatically cleared. the user can then send an acknowledge bit at the end of reception, by setting the acknowledge sequence enable bit, acken (sspcon2<4>). note: the ssp module must be in idle mode before the rce bit is set, or the rcen bit will be disreguarded. 15.2.10.1 bf status flag in receive operation, bf is set when an address or data byte is loaded into sspbuf from sspsr. it is cleared when sspbuf is read. 15.2.10.2 sspov status flag in receive operation, sspov is set when 8 bits are received into the sspsr, and the bf ?g is already set from a previous reception. 15.2.10.3 wcol status flag if the user writes the sspbuf when a receive is already in progress (i.e. sspsr is still shifting in a data byte), then wcol is set and the contents of the buffer are unchanged (the write doesn? occur).
1997 microchip technology inc. preliminary ds30264a-page 153 pic17c75x figure 15-30: master receiver flowchart idle mode num_clocks = 0, release sda force scl=0, ye s no brg rollover? release scl ye s no scl = 1? load brg with ye s no brg rollover? (clock arbitration) load brg w/ start count sspadd<6:0>, start count. sample sda, shift data into sspsr num_clocks = num_clocks + 1 ye s num_clocks = 8? no force scl = 0, set sspif, set bf. move contents of sspsr into sspbuf, clear rcen. rcen = 1 sspadd<6:0>,
pic17c75x ds30264a-page 154 preliminary 1997 microchip technology inc. figure 15-31: i 2 c master mode timing (reception 7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 5 678 9 1234 bus master terminates transfer a ck receiving data from slave receiving data from slave d0 d1 d2 d3 d4 d5 d6 d7 a ck r/w = 1 transmit address to slave sspif bf a ck is not sent write to sspcon2<0> (sen = 1) write to sspbuf occurs here ack from slave master congured as a receiver by programming sspcon2<3>, (rcen = 1) pen bit = 1 written here cleared in software start xmit sen = 0 (pir2<7>) sspov sda = 0, scl = 1 while cpu (sspstat<0>) a ck last bit is shifted into sspsr and contents are unloaded into sspbuf cleared in software cleared in software set sspif interrupt at end of recieve set p bit (sspstat<4>) and sspif cleared in software ack from master set sspif at end set sspif interrupt at end of acknowledge sequence set sspif interrupt at end of acknow- ledge sequence of recieve set acken start acknowledge sequence sspov is set because sspbuf is still full sda = ackdt (sspcon2<5>) = 1 rcen cleared automatically rcen = 1 start next receive write to sspcon2<4> to start acknowledge sequence sda = ackdt (sspcon2<5>) = 0 rcen cleared automatically responds to sspif acken begin start condition
1997 microchip technology inc. preliminary ds30264a-page 155 pic17c75x 15.2.11 acknowledge sequence timing an acknowledge sequence is enabled by setting the acknowledge sequence enable bit, acken (sspcon2<4>). when this bit is set, the scl pin is pulled low and the contents of the acknowledge data bit is presented on the sda pin. if the user wishes to generate an acknowledge, then the ackdt bit should be cleared. if not, the user should set the ackdt bit before starting an acknowledge sequence. the baud rate generator then counts for one rollover period (t brg ), and the scl pin is de-asserted (pulled high). when the scl pin is sampled high (clock arbitration), the baud rate generator counts for t brg . the scl pin is then pulled low for one t brg . following this, the acken bit is automatically cleared, the baud rate generator is turned off, and the ssp module then goes into idle mode. (figure 15-32) 15.2.11.1 wcol status flag if the user writes the sspbuf when an acknowledege sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesn? occur). figure 15-32: acknowledge sequence timing note: t brg = one baud rate generator period. sda scl set sspif at the end acknowledge sequence starts here write to sspcon2 acken automatically cleared cleared in t brg t brg of receive a ck 8 acken = 1, ackdt = 0 d0 9 sspif software set sspif at the end of acknowledge sequence cleared in software
pic17c75x ds30264a-page 156 preliminary 1997 microchip technology inc. figure 15-33: acknowledge flowchart idle mode force scl = 0 ye s no scl = 0? drive ackdt bit ye s no brg rollover? (sspcon2<5>) onto sda pin, load brg with sspadd<6:0>, start count. force scl = 1 ye s no scl = 1? no ackdt = 0? load brg with no brg rollover? sspadd <6:0>, start count. no sda = 1? bus collision detected, set bclif, ye s force scl = 0, (clock arbitration) clear acken no scl = 0? reset brg clear acken set acken release scl, ye s ye s ye s
1997 microchip technology inc. preliminary ds30264a-page 157 pic17c75x 15.2.12 stop condition timing a stop bit is asserted on the sda pin at the end of a receive/transmit by setting the stop sequence enable bit pen (sspcon2<2>). at the end of a receive/trans- mit the scl line is held low after the falling edge of the ninth clock. when the pen bit is set, the master will assert the sda line low . when the sda line is sam- pled low, the baud rate generator is reloaded and counts down to 0. when the baud rate generator times out, the scl pin will be brought high, and one t brg (baud rate generator rollover count) later, the sda pin will be de-asserted. when the sda pin is sampled high while scl is high, the pen bit will be automatically cleared, and the p bit (sspstat<4>) is set which in turn will set the sspif ?g. (figure 15-34) whenever the cpu decides to take control of the bus, it will ?st determine if the bus is busy by checking the s and p bits in the sspstat register. if the bus is busy, then the cpu can be interrupted (noti?d) when a stop bit is detected (i.e. bus is free). 15.2.12.1 wcol status flag if the user writes the sspbuf when a stop sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesn? occur). figure 15-34: stop condition receive or transmit mode scl sda sda asserted low before rising edge of clock write to sspcon2 set pen falling edge of scl = 1 for t brg , followed by sda = 1 for t brg 9th clock scl brought high after t brg note: t brg = one baud rate generator period. t brg t brg after sda sampled high, pen bit (sspcon2<2>) is t brg to setup stop condition. automatically cleared. p bit (sspstat<4>) is set a ck p t brg
pic17c75x ds30264a-page 158 preliminary 1997 microchip technology inc. figure 15-35: stop condition flowchart idle mode, sspen = 1, force sda = 0 scl doesn? change sda = 0? de-assert scl, scl = 1 scl = 1? no ye s start brg no ye s brg sda going from 0 to 1 while scl = 1 no ye s sets p bit sspstat<4>, set sspif, release sda, start brg stop condition done sspcon1<3:0> = 1000 rollover? no brg rollover? ye s p bit set? no ye s bus collision detected, set bclif, clear spen start brg no ye s brg rollover? (clock arbitration) pen = 1
1997 microchip technology inc. preliminary ds30264a-page 159 pic17c75x 15.2.13 clock arbitration clock arbitration occurs when the master during any receive, transmit, or restart/stop condition de-asserts the scl pin (scl allowed to ?at high). when the scl pin is allowed to ?at high, the baud rate genera- tor (brg) is suspended from counting until the scl pin is actually sampled high. when the scl pin is sampled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and begins counting. this ensures that the scl high time will always be at least one brg rollover count in the event that the clock is held low by an external device. (figure 15-36) figure 15-36: clock arbitration timing in master transmit mode scl sda brg over?w, release scl, if scl = 1 load brg with sspadd<6:0>, and start count brg over?w occurs, release scl, slave device holds scl low. scl = 1 brg starts counting clock high interval. scl line sampled once every machine cycle (t osc 4). hold off brg until scl is sampled high. t brg t brg t brg to measure high time interval
pic17c75x ds30264a-page 160 preliminary 1997 microchip technology inc. 15.2.14 multi -master communication, bus collision, and bus arbitration multi-master mode support is achieved by bus arbitra- tion. when the master outputs address/data bits onto the sda pin, arbitration takes place when the master outputs a '1' on sda by letting sda ?at high and another master asserts a '0'. when the scl pin ?ats high, data should be stable. if the expected data on sda is a '1' and the data sampled on the sda pin = '0', then a bus collision has taken place. the master will set the bus collision interrupt flag, bclif and reset the i 2 c port to its idle state. (figure 15-37). if a transmit was in progress when the bus collision occurred, the transmission is halted, the bf ?g is cleared, the sda and scl lines are de-asserted, and the sspbuf can be written to. when the user ser- vices the bus collision interrupt service routine, and if the i 2 c bus is free, the user can resume communica- tion by asserting a start condition. if a start, restart, stop, or acknowledge condi- tion was in progress when the bus collision occurred, the condition is aborted, the sda and scl lines are de-asserted, and the respective control bits in the sspcon2 register are cleared. when the user ser- vices the bus collision interrupt service routine, and if the i 2 c bus is free, the user can resume communica- tion by asserting a start condition. the master will continue to monitor the sda and scl pins, and if a stop condition occurs, the sspif bit will be set. a write to the sspbuf will start the transmission of data at the ?st data bit, regardless of where the trans- mitter left off when bus collision occurred. in multi-master mode, the interrupt generation on the detection of start and stop conditions allows the deter- mination of when the bus is free. control of the i 2 c bus can be taken when the p bit is set in the sspstat register, or the bus is idle and the s and p bits are cleared. figure 15-37: bus collision timing for transmit and acknowledge sda scl bclif sda released sda line pulled low by another source sample sda. while scl is high data doesn? match what is driven bus collision has occurred. set bus collision interrupt. by the master. by master data changes while scl = 0
1997 microchip technology inc. preliminary ds30264a-page 161 pic17c75x 15.2.14.1 bus collision during a start condition during a start condition, a bus collision occurs if: a) sda or scl are sampled low at the beginning of the start condition (figure 15-38) b) scl is sampled low before sda is asserted low. (figure 15-39) during a start condition both the sda and the scl pins are monitored. i f : the sda pin is already low or the scl pin is already low, then: the start condition is aborted, and the bclif ?g is set, and the ssp module is reset to its idle state (figure 15-38). the start condition begins with the sda and scl pins de-asserted. when the sda pin is sampled high, the baud rate generator is loaded from sspadd<6:0> and counts down to 0. if the scl pin is sampled low while sda is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data '1' during the start condition. if the sda pin is sampled low during this count, the brg is reset and the sda line is asserted early (figure 15-40). if however a '1' is sampled on the sda pin, the sda pin is asserted low at the end of the brg count. the baud rate generator is then reloaded and counts down to 0, and during this time, if the scl pins is sampled as '0', a bus collision does not occur. at the end of the brg count the scl pin is asserted low. note: the reason that bus collision is not a factor during a start condition is that no two bus masters can assert a start condition at the exact same time. therefore, one master will always assert sda before the other. this condition does not cause a bus collision because the two masters must be allowed to arbitrate the ?st address follow- ing the start condition, and if the address is the same, arbitration must be allowed to continue into the data portion, restart, or stop conditions. figure 15-38: bus collision during start condition (sda only) sda scl sen sda sampled low before sda goes low before the sen bit is set. s bit and sspif set because ssp module reset into idle state. sen cleared automatically because of bus collision. s bit and sspif set because set sen, enable start condition if sda = 1, scl=1 sda = 0, scl = 1 bclif s sspif sda = 0, scl = 1 sspif and bclif are cleared in software. sspif and bclif are cleared in software. . set bclif, set bclif. start condition.
pic17c75x ds30264a-page 162 preliminary 1997 microchip technology inc. figure 15-39: bus collision during start condition (scl = 0) figure 15-40: brg reset due to sda collision during start condition sda scl sen bus collision occurs, set bclif. scl = 0 before sda = 0, set sen, enable start sequence if sda = 1, scl = 1 t brg t brg sda = 0, scl = 1 bclif s sspif interrupts cleared in software. bus collision occurs, set bclif. scl = 0 before brg time out, sda scl sen set s, sspif set sen, enable start sequence if sda = 1, scl = 1 less than t brg t brg sda = 0, scl = 1 bclif s sspif s interrupts cleared in software. set s, sspif sda = 0, scl = 1 sda goes low early. reset brg and assert sda
1997 microchip technology inc. preliminary ds30264a-page 163 pic17c75x 15.2.14.2 bus collision during a restart condition during a restart condition, a bus collision occurs if: a) a ? is sampled on sda when scl goes from ? to ? b) scl goes low before sda is asserted low, indi- cating that another master is attempting to trans- mit a data ?? when the user de-asserts sda and the pin is allowed to ?at high, the brg is loaded with sspadd<6:0>, and counts down to 0. the scl pin is then de-asserted, and when sampled high, the sda pin is sampled. if sda is low, a bus collision has occurred (i.e. another master is attempting to transmit a data ??. if however sda is sampled high then the brg is reloaded and begins counting. if sda goes from high to low before the brg times out, no bus collision occurs, because no two masters can assert sda at exactly the same time. if, however, scl goes from high to low before the brg times out and sda has not already been asserted, then a bus collision occurs. in this case, another master is attempting to transmit a data ? dur- ing the restart condition. if at the end of the brg time out both scl and sda are still high, the sda pin is driven low, the brg is reloaded, and begins counting. at the end of the count, regardless of the status of the scl pin, the scl pin is driven low and the restart condition is com- plete. (figure 15-41) figure 15-41: bus collision during a restart condition (case 1) figure 15-42: bus collision during restart condition (case 2) sda scl rsen bclif s sspif sample sda when scl goes high. if sda = 0, set bclif and release sda and scl cleared in software sda scl bclif rsen s sspif interrupt cleared in software scl goes low before sda, set bclif. release sda and scl t brg t brg
pic17c75x ds30264a-page 164 preliminary 1997 microchip technology inc. 15.2.14.3 bus collision during a stop condition bus collision occurs during a stop condition if: a) after the sda pin has been de-asserted and allowed to ?at high, sda is sampled low after the brg has timed out. b) after the scl pin is de-asserted, scl is sam- pled low before sda goes high. the stop condition begins with sda asserted low. when sda is sampled low, the scl pin is allow to ?at. when the pin is sampled high (clock arbitration), the baud rate generator is loaded with sspadd<6:0> and counts down to 0. after the brg times out sda is sampled. if sda is sampled low, a bus collision has occurred. this is due to another master attempting to drive a data '0'. if the scl pin is sampled low before sda is allowed to ?at high, a bus collision occurs. this is another case of another master attempting to drive a data '0'. (figure 15-43) figure 15-43: bus collision during a stop condition (case 1) figure 15-44: bus collision during a stop condition (case 2) sda scl bclif pen p sspif t brg t brg t brg sda asserted low sda sampled low after t brg , set bclif sda scl bclif pen p sspif t brg t brg t brg assert sda scl goes low before sda goes high set bclif
1997 microchip technology inc. preliminary ds30264a-page 165 pic17c75x 15.3 con n ection considerations for i 2 c bus for standard-mode i 2 c bus devices, the values of resistors r p r s in figure 15-45 depends on the follow- ing parameters supply voltage bus capacitance number of connected devices (input current + leakage current). the supply voltage limits the minimum value of resistor r p due to the speci?d minimum sink current of 3 ma at v ol max = 0.4v for the speci?d output stages. for example, with a supply voltage of v dd = 5v+ 10% and v ol max = 0.4v at 3 ma, r p min = (5.5-0.4)/0.003 = 1.7 k w. v dd as a function of r p is shown in figure 15-45. the desired noise margin of 0.1v dd for the low level, limits the maximum value of r s . series resistors are optional. the bus capacitance is the total capacitance of wire, connections, and pins. this capacitance limits the max- imum value of r p due to the speci?d rise time (figure 15-45). the smp bit is the slew rate control enabled bit. this bit is in the sspstat register, and controls the slew rate of the i/o pins when in i 2 c mode (master or slave). this control ensures that the rise and fall times of the scl and sda pins will meet the minimum require- ments as speci?d in the i 2 c speci?ation for 400 khz operation. figure 15-45: sample device configuration for i 2 c bus r p r p v dd + 10% sda scl note: i 2 c devices with input levels related to v dd must have one common supply line to which the pull up resistor is also connected. device c b =10 - 400 pf r s r s
pic17c75x ds30264a-page 166 preliminary 1997 microchip technology inc. notes:
1997 microchip technology inc. preliminary ds30264a-page 167 pic17c75x 16.0 analog-to-digital converter (a/d) module the analog-to-digital (a/d) converter module has twelve analog inputs for the pic17c75x devices. the a/d allows conversion of an analog input signal to a corresponding 10-bit digital number. the output of the sample and hold is the input into the converter, which generates the result via successive approximation. the analog reference voltages (positive and negative supply) are software selectable to either the devices supply voltages (av dd , avss) or the voltage level on the rg3/an0/v ref + and rg2/an1/v ref - pins. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to oper- ate in sleep, the a/d clock must be derived from the a/ds internal rc oscillator. the a/d module has four registers. these registers are: a/d result high register (adresh) a/d result low register (adresl) a/d control register0 (adcon0) a/d control register1 (adcon1) the adcon0 register, shown in figure 16-1, controls the operation of the a/d module. the adcon1 regis- ter, shown in figure 16-2, con?ures the functions of the port pins. the port pins can be con?ured as ana- log inputs (rg3 and rg2 can also be the voltage refer- ences) or as digital i/o. figure 16-1: adcon0 register (address: 14h, bank 5) r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 r/w-0 chs3 chs2 chs1 chs0 go/done adon r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7-4: chs2:chs0 : analog channel select bits 0000 = channel 0, (an0) 0001 = channel 1, (an1) 0010 = channel 2, (an2) 0011 = channel 3, (an3) 0100 = channel 4, (an4) 0101 = channel 5, (an5) 0110 = channel 6, (an6) 0111 = channel 7, (an7) 1000 = channel 8, (an8) 1001 = channel 9, (an9) 1010 = channel 10, (an10) 1011 = channel 11, (an11) 11xx = reserved , do not select bit 3: unimplemented : read as '0' bit 2: go/done : a/d conversion status bit if adon = 1 1 = a/d conversion in progress (setting this bit starts the a/d conversion which is automatically cleared by hardware when the a/d conversion is complete) 0 = a/d conversion not in progress bit 1: unimplemented : read as '0' bit 0: adon : a/d on bit 1 = a/d converter module is operating 0 = a/d converter module is shutoff and consumes no operating current
pic17c75x ds30264a-page 168 preliminary 1997 microchip technology inc. figure 16-2: adcon1 register (address 15h, bank 5) r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 adcs1 adcs0 adfm pcfg3 pcfg2 pcfg1 pcfg0 r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7-6: adcs1:adcs0 : a/d conversion clock select bits 00 = f osc /8 01 = f osc /32 10 = f osc /64 11 = f rc (clock derived from an internal rc oscillator) bit 5: adfm : a/d result format select 1 = right justi?d. 6 most signi?ant bits of adresh are read as ?? 0 = left justi?d. 6 least signi?ant bits of adresl are read as ?? bit 4: unimplemented: read as '0' bit 3-0: pcfg3:pcfg1 : a/d port con?uration control bits bit 0: pcfg0 : a/d voltage reference select bit 1 = a/d reference is the v ref + and v ref - pins 0 = a/d reference is av dd and av ss note: when this bit is set, ensure that the a/d voltage reference speci?ations are met. a = analog input d = digital i/o pcfg3:pcfg1 an11 an10 an9 an8 an7 an6 an5 an4 an3 an2 an1 an0 000 a a aa aaaaaaaa 001 a a aa daaaaaaa 010 a a aa ddaaaaaa 011 aaaadddaaaaa 100 aaaaddddaaaa 101 d a aa dddddaaa 110 d d aa ddddddaa 111 d d dd dddddddd
1997 microchip technology inc. preliminary ds30264a-page 169 pic17c75x the adresh:adresl registers contains the 10-bit result of the a/d conversion. when the a/d conversion is complete, the result is loaded into this a/d result reg- ister pair, the go/done bit (adcon0<2>) is cleared, and a/d interrupt ?g bit adif is set. the block dia- grams of the a/d module are shown in figure 16-3. after the a/d module has been con?ured as desired, the selected channel must be acquired before the con- version is started. the analog input channels must have their corresponding ddr bits selected as inputs. to determine acquisition time, see section 16.1. after this acquisition time has elapsed the a/d conversion can be started. the following steps should be followed for doing an a/d conversion: 1. con?ure the a/d module: con?ure analog pins / voltage reference / and digital i/o (adcon1) select a/d input channel (adcon0) select a/d conversion clock (adcon0) turn on a/d module (adcon0) 2. con?ure a/d interrupt (if desired): clear adif bit set adie bit clear glintd bit 3. wait the required acquisition time. 4. start conversion: set go/done bit (adcon0) 5. wait for a/d conversion to complete, by either: polling for the go/done bit to be cleared or waiting for the a/d interrupt 6. read a/d result register pair (adresh:adresl), clear bit adif if required. 7. for next conversion, go to step 1 or step 2 as required. the a/d conversion time per bit is de?ed as t ad . a minimum wait of 2t ad is required before next acquisition starts. figure 16-3: a/d block diagram (input voltage) v in v ref - (reference voltage) av dd pcfg0 chs3:chs0 an7 an6 an5 an4 an3 an2 an1 an0 0111 0110 0101 0100 0011 0010 0001 0000 a/d converter an11 an10 an9 an8 1011 1010 1001 1000 v ref + av ss
pic17c75x ds30264a-page 170 preliminary 1997 microchip technology inc. 16.1 a/d acquisition requirements for the a/d converter to meet its speci?d accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 16-4. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ), figure 16-4. the source impedance affects the offset voltage at the analog input (due to pin leakage current). the maximum recommended impedance for ana- log sources is 10 k w . after the analog input channel is selected (changed) this acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, equation 16-1 may be used. this equation calculates the acquisition time to within 1/2 lsb error (1024 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its speci?d accuracy. equation 16-1: a/d minimum charging time (for c hold ) v hold = (v ref - (v ref /2048)) ? (1 - e (-tcap/c hold (r ic + r ss + r s )) ) given v hold = (v ref /2048), for 1/2 lsb resolution v ref = v ref + - v ref - or tcap = -(200 pf)(1 k w + r ss + r s ) ln(1/2047) example 16-1 shows the calculation of the minimum required acquisition time t acq . this calculation is based on the following application system assump- tions. c hold = 200 pf rs = 10 k w 1/2 lsb error v dd = 5v ? rss = 7 k w temp (application system max.) = 50 c v hold = 0 @ t = 0 note 1: the reference voltage (v ref ) has no effect on the equation, since it cancels itself out. note 2: the charge holding capacitor (c hold ) is not discharged after each conversion. note 3: the maximum recommended impedance for analog sources is 10 k w . this is required to meet the pin leakage speci? cation. note 4: after a conversion has completed, a 2.0t ad delay must complete before acqui- sition can begin again. during this time the holding capacitor is not connected to the selected a/d input channel. figure 16-4: analog input model c pin va rs anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = dac capacitance v ss 6v sampling switch 5v 4v 3v 2v 5 6 7 8 9 10 11 ( k w ) v dd = 200 pf 500 na legend c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions
1997 microchip technology inc. preliminary ds30264a-page 171 pic17c75x example 16-1: calculating the minimum required acquisition time t acq = ampli?r settling time + holding capacitor charging time + temperature coef?ient ? ? only required for temperatures 1 25 c t acq =10 m s + tcap + [(temp - 25 c)(0.05 m s/ c)] t cap =-c hold (r ic + r ss + r s ) ln(1/2047) -200 pf (1 k w + 7 k w + 10 k w ) ln(0.0004885) -200 pf (18 k w ) ln(0.0004885) -3.6 m s (-7.6241) 27.447 m s t acq =10 m s + 27.447 m s + [(50 c - 25 c)(0.05 m s/ c)] 37.447 m s + 1.25 m s 38.697 m s 16.2 selecting the a /d conversion clock the a/d conversion time per bit is de?ed as t ad . the a/d conversion requires a minimum 12t ad per 10-bit conversion. the source of the a/d conversion clock is software selected. the four possible options for t ad are: ?t osc 32t osc 64t osc internal rc oscillator for correct a/d conversions, the a/d conversion clock (t ad ) must be selected to ensure a minimum t ad time of 1.6 m s. table 16-1 and table 16-2 show the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. these times are for standard voltage range devices. table 16-1: t ad vs. device operating frequencies (standard devices (c)) table 16-2: t ad vs. device operating frequencies (extended voltage devices (lc)) ad clock source (t ad ) device frequency operation adcs1:adcs0 33 mhz 20 mhz 5 mhz 1.25 mhz 333.33 khz 8t osc 00 242 ns (2) 400 ns (2) 1.6 m s 6.4 m s 24 m s 32t osc 01 970 ns (2) 1.6 m s 6.4 m s 25.6 m s (3) 96 m s (3) 64t osc 10 1.94 m s 3.2 m s 12.8 m s (3) 51.2 m s (3) 192 m s (3) rc 11 2 - 6 m s (1, 4) 2 - 6 m s (1, 4) 2 - 6 m s (1, 4) 2 - 6 m s (1, 4) 2 - 6 m s (1) legend: shaded cells are are outside of recommended ranges. note 1: the rc source has a typical t ad time of 4 m s. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: when the device frequencies is greater than 1 mhz, the rc a/d conversion clock source is only recom- mended for sleep operation. ad clock source (t ad ) device frequency operation adcs1:adcs0 8 mhz 4 mhz 2 mhz 1 mhz 333.33 khz 8t osc 00 1.0 m s (2) 2.0 m s (2) 4 m s8 m s 24 m s 32t osc 01 4.0 m s8 m s 16 m s 32 m s (3) 96 m s (3) 64t osc 10 8.0 m s 16 m s 32 m s (3) 64 m s (3) 192 m s (3) rc 11 3 - 9 m s (1, 4) 3 - 9 m s (1, 4) 3 - 9 m s (1, 4) 3 - 9 m s (1) 3 - 9 m s (1) legend: shaded cells are are outside of recommended ranges. note 1: the rc source has a typical t ad time of 4 m s. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: when the device frequencies is greater than 1 mhz, the rc a/d conversion clock source is only recom- mended for sleep operation.
pic17c75x ds30264a-page 172 preliminary 1997 microchip technology inc. 16.3 conf iguring analog port pins the adcon1, and ddr registers control the operation of the a/d port pins. the port pins that are desired as analog inputs must have their corresponding ddr bits set (input). if the ddr bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs2:chs0 bits and the ddr bits. note 1: when reading the port register, any pin con?ured as an analog input channel will read as cleared (a low level). pins con?- ured as digital inputs, will convert an ana- log input. analog levels on a digitally con?ured input will not affect the conver- sion accuracy. note 2: analog levels on any pin that is de?ed as a digital input (including the an11:an0 pins), may cause the input buffer to con- sume current that is out of the devices speci?ation. 16.4 a/d conversions example 16-2 shows how to perform an a/d conver- sion. the portf and lower four portg pins are con- ?ured as analog inputs. the analog references (v ref + and v ref -) are the device av dd and av ss . the a/d interrupt is enabled, and the a/d conversion clock is f rc . the conversion is performed on the rg3/an0 pin (channel 0). clearing the go/done bit during a conversion will abort the current conversion. the a/d result register pair will not be updated with the partially completed a/d conversion sample. that is, the adresh:adresl registers will continue to contain the value of the last completed conversion (or the last value written to the adresh:adresl registers). after the a/d conversion is aborted, a 2t ad wait is required before the next acquisition is started. after this 2t ad wait, acquisition on the selected channel is automati- cally started. note: the go/done bit should not be set in the same instruction that turns on the a/d. example 16-2: a/d conversion movlb 5 ; bank 5 clrf adcon1, f ; configure a/d inputs movlw 0xc1 ; rc clock, a/d is on, channel 0 is selected movwf adcon0 ; movlb 4 ; bank 4 bcf pir2, adif ; clear a/d interrupt flag bit bsf pie2, adie ; enable a/d interrupts bsf intsta, peie ; enable peripheral interrupts bcf cpusta, glintd ; enable all interrupts ; ; ensure that the required sampling time for the selected input channel has elapsed. ; then the conversion may be started. ; movlb 5 ; bank 5 bsf adcon0, go ; start a/d conversion : ; the adif bit will be set and the go/done bit : ; is cleared upon completion of the a/d conversion
1997 microchip technology inc. preliminary ds30264a-page 173 pic17c75x 16.4.1 a/d result registers the adresh:adresl register pair is the location where the 10-bit a/d result is loaded at the completion of the a/d conversion. this register pair is 16-bits wide. the a/d module gives the ?xibility to left or right justify the 10-bit result in the 16-bit result register. the a/d format select bit (adfm) controls this justi?ation. figure 16-5 shows the operation of the a/d result justi- ?ation. the extra bits are loaded with ?s? when an a/d result will not overwrite these locations (a/d dis- able), these registers may be used as two general pur- pose 8-bit registers. 16.5 a/d operation during sleep the a/d module can operate during sleep mode. this requires that the a/d clock source be set to rc (adcs1:adcs0 = 11 ). when the rc clock source is selected, the a/d module waits one instruction cycle before starting the conversion. this allows the sleep instruction to be executed, which eliminates all digital switching noise from the conversion. when the conver- sion is completed the go/done bit will be cleared, and the result loaded into the adres register. if the a/d interrupt is enabled, the device will wake-up from sleep. if the a/d interrupt is not enabled, the a/d mod- ule will then be turned off, although the adon bit will remain set. when the a/d clock source is another clock option (not rc), a sleep instruction will cause the present conver- sion to be aborted and the a/d module to be turned off, though the adon bit will remain set. turning off the a/d places the a/d module in its lowest current consumption state. note: for the a/d module to operate in sleep, the a/d clock source must be set to rc (adcs1:adcs0 = 11 ). to allow the con- version to occur during sleep, ensure the sleep instruction immediately follows the instruction that sets the go/done bit. figure 16-5: a/d result justification 10-bit result adresh adresl 0000 00 adfm = 0 0 2 1 0 7 7 10-bits result adresh adresl 10-bits 0000 00 7 0 7 6 5 0 result adfm = 1 right justi?d left justi?d
pic17c75x ds30264a-page 174 preliminary 1997 microchip technology inc. 16.6 a /d accuracy/error the absolute accuracy speci?d for the a/d converter includes the sum of all contributions for quantization error, integral error, differential error, full scale error, off- set error, and monotonicity. it is de?ed as the maxi- mum deviation from of an actual transition versus an ideal transition for any code. the absolute error of the a/d converter is speci?d at < + 1 lsb for v dd = v ref (over the devices speci?d operating range). how- ever, the accuracy of the a/d converter will degrade as v dd diverges from v ref . for a given range of analog inputs, the output digital code will be the same. this is due to the quantization of the analog input to a digital code. quantization error is typically + 1/2 lsb and is inherent in the analog to digital conversion process. the only way to reduce quantization error is to increase the resolution of the a/d converter. offset error measures the ?st actual transition of a code versus the ?st ideal transition of a code. offset error shifts the entire transfer function. offset error can be calibrated out of a system or introduced into a sys- tem through the interaction of the total leakage current and source impedance at the analog input. gain error measures the maximum deviation of the last actual transition and the last ideal transition adjusted for offset error. this error appears as a change in slope of the transfer function. the difference is gain error to full scale error is that full scale doe not take offset error into account. gain error can be calibrated out in soft- ware. linearity error refers to the uniformity of the code changes. linearity errors cannot be calibrated out of the system. integral non-linearity error measures the actual code transition versus the ideal code transition adjusted by the gain error for each code. differential non-linearity measures the maximum actual code width versus the ideal code width. this measure is unadjusted. the maximum pin leakage current is 1 m a. in systems where the device frequency is low, use of the a/d rc clock is preferred. at moderate to high fre- quencies, t ad should be derived from the device oscil- lator. t ad must not violate the minimum and should be 8 m s for preferred operation. this is because t ad , when derived from t osc , is kept away from on-chip phase clock transitions. this reduces, to a large extent, the effects of digital switching noise. this is not possi- ble with the rc derived clock. the loss of accuracy due to digital switching noise can be signi?ant if many i/o pins are active. in systems where the device will enter sleep mode after the start of the a/d conversion, the rc clock source selection is required. in this mode, the digital noise from the modules in sleep are stopped. this method gives high accuracy. 16.7 effect s of a reset a device reset forces all registers to their reset state. this forces the a/d module to be turned off, and any conversion is aborted. the value that is in the adresh:adresl registers is not modi?d for a power-on reset. the adresh:adresl registers will contain unknown data after a power-on reset. 16.8 connection considerations if the input voltage exceeds the rail values (v ss or v dd ) by greater than 0.3v, then the accuracy of the conver- sion is out of speci?ation. an external rc ?ter is sometimes added for anti-alias- ing of the input signal. the r component should be selected to ensure that the total source impedance is kept under the 10 k w recommended speci?ation. any external components connected (via hi-impedance) to an analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin. 16.9 t ransfer function the transfer function of the a/d converter is as follows: the ?st transition occurs when the analog input voltage (v ain ) equals analog v ref / 1024 (figure 16-6). figure 16-6: a/d transfer function 16.10 references a good reference for the undestanding a/d converter is the "analog-digital conversion handbook" third edi- tion, published by prentice hall (isbn 0-13-03-2848-0). digital code output 3feh 003h 002h 001h 000h 0.5 lsb 1 lsb 1.5 lsb 2 lsb 2.5 lsb 1022 lsb 1022.5 lsb 3 lsb analog input voltage 3ffh 1023 lsb 1021.5 lsb
1997 microchip technology inc. preliminary ds30264a-page 175 pic17c75x figure 16-7: flowchart of a/d operation table 16-3: registers/bits associated with a/d address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (note 1) 06h, unbanked cpusta stakav glintd t o pd por bor --11 1100 --11 qq11 07h, unbanked intsta peif t0ckif t0if intf peie t0ckie t0ie inte 0000 0000 0000 0000 10h, bank 4 pir2 sspif bclif adif ca4if ca3if tx2if rc2if 000- 0010 000- 0010 11h, bank 4 pie2 sspie bclie adie ca4ie ca3ie tx2ie rc2ie 000- 0000 000- 0000 10h, bank 5 ddrf data direction register for portf 1111 1111 1111 1111 11h, bank 5 portf rf7/ an11 rf6/ an10 rf5/ an9 rf4/ an8 rf3/ an7 rf2/ an6 rf1/ an5 rf0/ an4 0000 0000 0000 0000 12h, bank 5 ddrg data direction register for portg 1111 1111 1111 1111 13h, bank 5 portg rg7/ tx2/ck2 rg6/ rx2/dt2 rg5/ pwm3 rg4/ cap3 rg3/ an0/v ref + rg2/ an1/v ref - rg1/ an2 rg0/ an3 xxxx 0000 uuuu 0000 14h, bank 5 adcon0 chs3 chs2 chs1 chs0 go/done adon 0000 -0-0 0000 -0-0 15h, bank 5 adcon1 adcs1 adcs0 adfm pcfg3 pcfg2 pcfg1 pcfg0 000- 0000 000- 0000 16h, bank 5 adresl a/d result low register xxxx xxxx uuuu uuuu 17h, bank 5 adresh a/d result high register xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used for a/d conversion. note 1: other (non power-up) resets include: external reset through mclr and watchdog timer reset. acquire adon = 0 adon = 0? go = 0? a/d clock go = 0, adif = 0 abort conversion sleep power-down a/d wait 2t ad wake-up ye s no ye s no no ye s finish conversion go = 0, adif = 1 device in no ye s finish conversion go = 0, adif = 1 wait 2t ad stay in sleep selected channel = rc? sleep no ye s instruction? start of a/d conversion delayed 1 instruction cycle from sleep? power-down a/d ye s no wait 2t ad finish conversion go = 0, adif = 1 sleep?
pic17c75x ds30264a-page 176 preliminary 1997 microchip technology inc. notes:
1997 microchip technology inc. preliminary ds30264a-page 177 pic17c75x 17.0 special features of the cpu what sets a microcontroller apart from other proces- sors are special circuits to deal with the needs of real-time applications. the pic17cxxx family has a host of such features intended to maximize system reli- ability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. these are: oscillator selection (section 4.0) reset (section 5.0) - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) interrupts (section 6.0) watchdog timer (wdt) sleep mode code protection the pic17cxxx has a watchdog timer which can be shutoff only through eprom bits. it runs off its own rc oscillator for added reliability. there are two timers that offer necessary delays on power-up. one is the oscil- lator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power-up timer (pwrt), which provides a ?ed delay of 96 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabi- lizes. with these two timers on-chip, most applications need no external reset circuitry. the sleep mode is designed to offer a very low cur- rent power-down mode. the user can wake from sleep through external reset, watchdog timer reset or through an interrupt. several oscillator options are also made available to allow the part to ? the applica- tion. the rc oscillator option saves system cost while the lf crystal option saves power. con?uration bits are used to select various options. this con?uration word has the format shown in figure 17-1. figure 17-1: configuration words u - x r/p - 1 r/p - 1 u - x u - x u - x u - x u - x u - x high (h) table read addr. pm2 boden fe0fh - fe08h bit15 bit 8 bit 7 bit 0 u - x u - x r/p - 1 u - x r/p - 1 r/p - 1 r/p - 1 r/p - 1 r/p - 1 low (l) table read addr. pm1 pm0 wdtps1 wdtps0 fosc1 fosc0 fe07h - fe00h bit15 bit 8 bit 7 bit 0 bit 6h boden : brown-out detect enable 1 = brown-out detect circuitry is enabled 0 = brown-out detect circuitry is disabled bits 7h:6l:4l pm2, pm1, pm0 , processor mode select bits 111 = microprocessor mode 110 = microcontroller mode 101 = extended microcontroller mode 000 = code protected microcontroller mode bits 2l:3l wdtps1:wdtps0 , wdt postscaler select bits 11 = wdt enabled, postscaler = 1 10 = wdt enabled, postscaler = 256 01 = wdt enabled, postscaler = 64 00 = wdt disabled, 16-bit over?w timer bits 1l:0l fosc1:fosc0 , oscillator select bits 11 = ec oscillator 10 = xt oscillator 01 = rc oscillator 00 = lf oscillator reserved
pic17c75x ds30264a-page 178 preliminary 1997 microchip technology inc. 17.1 con guratio n bits the pic17cxxx has eight con?uration locations (table 17-1). these locations can be programmed (read as '0') or left unprogrammed (read as '1') to select various device con?urations. any write to a con?ura- tion location, regardless of the data, will program that con?uration bit. a tablwt instruction is required to write to program memory locations. the con?uration bits can be read by using the tablrd instructions. reading any con?uration location between fe00h and fe07h will read the low byte of the con?uration word (figure 17-1) into the tablatl register. the tab- lath register will be ffh. reading a con?uration location between fe08h and fe0fh will read the high byte of the con?uration word into the tablatl regis- ter. the tablath register will be ffh. addresses fe00h thorough fe0fh are only in the pro- gram memory space for microcontroller and code pro- tected microcontroller modes. a device programmer will be able to read the con?uration word in any pro- cessor mode. see programming speci?ations for more detail. table 17-1: configuration locations bit address fosc0 fe00h fosc1 fe01h wdtps0 fe02h wdtps1 fe03h pm0 fe04h pm1 fe06h boden fe0eh pm2 fe0fh note: when programming the desired con?ura- tion locations, they must be programmed in ascending order. starting with address fe00h. 17.2 oscillator con gurations 17.2.1 oscillator types the pic17cxxx can be operated in four different oscil- lator modes. the user can program two con?uration bits (fosc1:fosc0) to select one of these four modes: lf low power crystal xt crystal/resonator ec external clock input rc resistor/capacitor for information on the different oscillator types and how to use them, please refer to section 4.0.
1997 microchip technology inc. preliminary ds30264a-page 179 pic17c75x 17.3 w atchdog t imer (wdt) the watchdog timers function is to recover from software malfunction. the wdt uses an internal free running on-chip rc oscillator for its clock source. this does not require any external components. this rc oscillator is separate from the rc oscillator of the osc1/clkin pin. that means that the wdt will run, even if the clock on the osc1/clkin and osc2/clkout pins have been stopped, for example, by execution of a sleep instruction. during normal operation and sleep mode, a wdt time-out generates a device reset. the wdt can be permanently disabled by programming the con?ura- tion bits wdtps1:wdtps0 as ' 00 ' (section 17.1). under normal operation, the wdt must be cleared on a regular interval. this time is less the minimum wdt over?w time. not clearing the wdt in this time frame will cause the wdt to over?w and reset the device. 17.3.1 wdt period the wdt has a nominal time-out period of 12 ms, (with postscaler = 1). the time-out periods vary with temper- ature, v dd and process variations from part to part (see dc specs). if longer time-out periods are desired, a postscaler with a division ratio of up to 1:256 can be assigned to the wdt. thus, typical time-out periods up to 3.0 seconds can be realized. the clrwdt and sleep instructions clear the wdt and the postscaler (if assigned to the wdt) and pre- vent it from timing out thus generating a device reset condition. the t o bit in the cpusta register will be cleared upon a wdt time-out. 17.3.2 clearing the wdt and postscaler the wdt and postscaler are cleared when: the device is in the reset state ? sleep instruction is executed ? clrwdt instruction is executed wake-up from sleep by an interrupt the wdt counter/postscaler will start counting on the ?st edge after the device exits the reset state. 17.3.3 wdt programming considerations it should also be taken in account that under worst case conditions (v dd = min., temperature = max., max. wdt postscaler) it may take several seconds before a wdt time-out occurs. the wdt and postscaler is the power-up timer during the power-on reset sequence. 17.3.4 wdt as normal timer when the wdt is selected as a normal timer, the clock source is the device clock. neither the wdt nor the postscaler are directly readable or writable. the over- ?w time is 65536 t osc cycles. on over?w, the t o bit is cleared (device is not reset). the clrwdt instruction can be used to set the t o bit. this allows the wdt to be a simple over?w timer. the simple timer does not increment when in sleep. figure 17-2: watchdog timer block diagram table 17-2: registers/bits associated with the watchdog timer address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (note1) con? see figure 17-1 for location of wdtpsx bits in con?uration word. (note 2) (note 2) 06h, unbanked cpusta stkav glintd t o pd por bor --11 1100 --11 qq11 legend: - = unimplemented read as '0', q - value depends on condition, shaded cells are not used by the wdt. note 1: other (non power-up) resets include: external reset through mclr and watchdog timer reset. 2: this value will be as the device was programmed, or if unprogrammed, will read as all '1's. wdt wdt enable postscaler 4 - to - 1 mux wdtps1:wdtps0 on-chip rc wdt over?w oscillator (1) note 1: this oscillator is separate from the external rc oscillator on the osc1 pin.
pic17c75x ds30264a-page 180 preliminary 1997 microchip technology inc. 17.4 power- do wn mode (sleep) the power-down mode is entered by executing a sleep instruction. this clears the watchdog timer and postscaler (if enabled). the pd bit is cleared and the t o bit is set (in the cpusta register). in sleep mode, the oscillator driver is turned off. the i/o ports maintain their status (driving high, low, or hi-impedance). the mclr/ v pp pin must be at a logic high level (v ihmc ). a wdt time-out reset does not drive the mclr/ v pp pin low. 17.4.1 wake-up from sleep the device can wake-up from sleep through one of the following events: por external reset input on mclr/ v pp pin wdt reset (if wdt was enabled) bor interrupt from ra0/int pin, rb port change, t0cki interrupt, or some peripheral interrupts the following peripheral interrupts can wake the device from sleep: capture interrupts usart synchronous slave transmit interrupts usart synchronous slave receive interrupts a/d conversion complete spi slave transmit / receive complete ? 2 c slave receive other peripherals cannot generate interrupts since dur- ing sleep, no on-chip q clocks are present. any reset event will cause a device reset. any interrupt event is considered a continuation of program execu- tion. the t o and pd bits in the cpusta register can be used to determine the cause of device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. the t o bit is cleared if wdt time-out occurred (and caused wake-up). when the sleep instruction is being executed, the next instruction (pc + 1) is pre-fetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up is regardless of the state of the glintd bit. if the glintd bit is set (disabled), the device continues execution at the instruction after the sleep instruction. if the glintd bit is clear (enabled), the device executes the instruction after the sleep instruction and then branches to the interrupt vector address. in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. the wdt is cleared when the device wakes from sleep, regardless of the source of wake-up. 17.4.1.1 wake-up delay when the oscillator type is con?ured in xt or lf mode, the oscillator start-up timer (ost) is activated on wake-up. the ost will keep the device in reset for 1024t osc . this needs to be taken into account when considering the interrupt response time when coming out of sleep. note: if the global interrupt is disabled (glintd is set), but any interrupt source has both its interrupt enable bit and the corresponding interrupt ?g bit set, the device will imme- diately wake-up from sleep. the t o bit is set, and the pd bit is cleared. figure 17-3: wake-up from sleep through interrupt q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 osc1 clkout(4) int intf ?g glintd bit instr uction flo w pc instruction fetched instruction executed interrupt latency (2) pc pc+1 pc+2 0004h 0005h dummy cycle inst (pc) = sleep inst (pc+1) inst (pc-1) sleep tost(2) processor in sleep inst (pc+2) inst (pc+1) note 1: xt or lf oscillator mode assumed. 2: tost = 1024tosc (drawing not to scale). this delay will not be there for rc osc mode. 3: when glintd = 0 processor jumps to interrupt routine after wake-up. if glintd = 1, execution will continue in line. 4: clkout is not available in these osc modes, but shown here for timing reference. (ra0/int pin)
1997 microchip technology inc. preliminary ds30264a-page 181 pic17c75x 17.4.2 minimizing current consumption to minimize current consumption, all i/o pins should be either at v dd , or v ss , with no external circuitry drawing current from the i/o pin. i/o pins that are hi-impedance inputs should be pulled high or low externally to avoid switching currents caused by ?ating inputs. the t0cki input should be at v dd or v ss . the contributions from on-chip pull-ups on portb should also be con- sidered, and disabled when possible. 17.5 code protection the code in the program memory can be protected by selecting the microcontroller in code protected mode (pm2:pm0 = ' 000 '). in this mode, instructions that are in the on-chip pro- gram memory space, can continue to read or write the program memory. an instruction that is executed out- side of the internal program memory range will be inhibited from writing to or reading from program mem- ory. if the code protection bit(s) have not been pro- grammed, the on-chip program memory can be read out for veri?ation purposes. note: microchip does not recommend code pro- tecting windowed devices.
pic17c75x ds30264a-page 182 preliminary 1997 microchip technology inc. 17.6 in-circuit serial programming the pic17c75x group of the high end family (pic17cxxx) has an added feature that allows serial programming while in the end application circuit. this is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. this allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. this also allows the most recent ?mware or a custom ?m- ware to be programmed. devices may be serialized to make the product unique, ?pecial variants of the product may be offered, and code updates are possible. this allows for increased design ?xibility. to place the device into the serial programming test mode, two pins will need to be placed at v ihh . these are the test pin and the mclr /v pp pin. also a sequence of events must occur as follows: 1. the test pin is placed at v ihh . 2. the mclr /v pp pin is placed at v ihh . there is a setup time between step 1 and step 2 that must be met. after this sequence the program counter is pointing to program memory address 0xff60. this location is in the boot rom. the code initializes the usart/sci so that it can receive commands. for this, the device must be clocked. the device clock source in this mode is the ra1/t0cki pin. after delaying to allow the usart/sci to initialize, commands can be received. the ?w is shown in these 3 steps: 1. the device clock source starts. 2. wait 80 device clocks for boot rom code to con?ure the usart/sci. 3. commands may now be sent. for complete details of serial programming, please refer to the pic17c75x programming speci?ation. (contact your local microchip technology sales of?e for availability.) figure 17-4: typical in-circuit serial programming connection external connector signals to normal connections to normal connections pic17c75x v dd v ss mclr /v pp ra1/t0cki ra4/rx1/dt1 +5v 0v v pp dev. clk data i/o v dd ra5/tx1/ck1 data clk test test cntl table 17-3: isp interface pins during programming name function type description ra4/rx1/dt1 dt i/o serial data ra5/tx1/ck1 ck i serial clock ra1/t0cki osci i device clock source test test i test mode selection control input. force to v ihh , mclr /v pp mclr /v pp p master clear reset and device programming voltage v dd v dd p positive supply for logic and i/o pins v ss v ss p ground reference for logic and i/o pins
1997 microchip technology inc. ds30264a-page 183 pic17c75x 18.0 instruction set summary the pic17cxxx instruction set consists of 58 instruc- tions. each instruction is a 16-bit word divided into an opcode and one or more operands. the opcode speci?s the instruction type, while the operand(s) fur- ther specify the operation of the instruction. the pic17cxxx instruction set can be grouped into three types: byte-oriented bit-oriented literal and control operations. these formats are shown in figure 18-1. table 18-1 shows the ?ld descriptions for the opcodes. these descriptions are useful for under- standing the opcodes in table 18-2 and in each speci? instruction descriptions. byte-oriented instructions , 'f' represents a ?e regis- ter designator and 'd' represents a destination designa- tor. the ?e register designator speci?s which ?e register is to be used by the instruction. the destination designator speci?s where the result of the operation is to be placed. if 'd' = '0', the result is placed in the wreg register. if 'd' = '1', the result is placed in the ?e register speci?d by the instruction. bit-oriented instructions , 'b' represents a bit ?ld des- ignator which selects the number of the bit affected by the operation, while 'f' represents the number of the ?e in which the bit is located. literal and control operations , 'k' represents an 8- or 13-bit constant or literal value. the instruction set is highly orthogonal and is grouped into: byte-oriented operations bit-oriented operations literal and control operations all instructions are executed within one single instruc- tion cycle, unless: a conditional test is true the program counter is changed as a result of an instruction a table read or a table write instruction is exe- cuted (in this case, the execution takes two instruction cycles with the second cycle executed as a nop ) one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 25 mhz, the normal instruction execution time is 160 ns. if a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 320 ns. table 18-1: opcode field descriptions field description f register ?e address (00h to ffh) p peripheral register ?e address (00h to 1fh) i table pointer control i = '0' (do not change) i = '1' (increment after instruction execution) t table byte select t = '0' (perform operation on lower byte) t = '1' (perform operation on upper byte literal ?ld, constant data) wreg working register (accumulator) b bit address within an 8-bit ?e register k literal ?ld, constant data or label x don't care location (= '0' or '1') the assembler will generate code with x = '0'. it is the recommended form of use for compatibility with all microchip software tools. d destination select 0 = store result in wreg 1 = store result in ?e register f default is d = '1' u unused, encoded as '0' s destination select 0 = store result in ?e register f and in the wreg 1 = store result in ?e register f default is s = '1' label label name c,dc, z,ov alu status bits carry, digit carry, zero, over?w glintd global interrupt disable bit (cpusta<4>) tblptr table pointer (16-bit) tblat table latch (16-bit) consists of high byte (tblath) and low byte (tblatl) tblatl table latch low byte tblath table latch high byte tos top of stack pc program counter bsr bank select register wdt watchdog timer counter to time-out bit pd power-down bit dest destination either the wreg register or the speci- ?d register ?e location [ ] options ( ) contents ? assigned to < > register bit ?ld ? in the set of i talics user de?ed term (font is courier)
pic17c75x ds30264a-page 184 1997 microchip technology inc. table 18-2 lists the instructions recognized by the mpasm assembler. all instruction examples use the following format to rep- resent a hexadecimal number: 0xhh where h signi?s a hexadecimal digit. to represent a binary number: 0000 0100b where b signi?s a binary string. figure 18-1: general format for instructions note 1: any unused opcode is reserved. use of any reserved opcode may cause unex- pected operation. byte-oriented ?e register operations 15 9 8 7 0 d = 0 for destination wreg opcode d f (file #) d = 1 for destination f f = 8-bit ?e register address bit-oriented ?e register operations 15 11 10 8 7 0 opcode b (bit #) f (file #) b = 3-bit address f = 8-bit ?e register address literal and control operations 15 8 7 0 opcode k (literal) k = 8-bit immediate value byte to byte move operations 15 13 12 8 7 0 opcode p (file #) f (file #) call and goto operations 15 13 12 0 opcode k (literal) k = 13-bit immediate value p = peripheral register ?e address f = 8-bit ?e register address 18.1 special functi on registers as source/destination the pic17c75xs orthogonal instruction set allows read and write of all ?e registers, including special function registers. there are some special situations the user should be aware of: 18.1.1 alusta as destination if an instruction writes to alusta, the z, c, dc and ov bits may be set or cleared as a result of the instruction and overwrite the original data bits written. for exam- ple, executing clrf alusta will clear register alusta, and then set the z bit leaving 0000 0100b in the register. 18.1.2 pcl as source or destination read, write or read-modify-write on pcl may have the following results: read pc: pch ? pclath; pcl ? dest write pcl: pclath ? pch; 8-bit destination value ? pcl read-modify-write: pcl ? alu operand pclath ? pch; 8-bit result ? pcl where pch = program counter high byte (not an addressable register), pclath = program counter high holding latch, dest = destination, wreg or f. 18.1.3 bit manipulation all bit manipulation instructions are done by ?st read- ing the entire register, operating on the selected bit and writing the result back (read-modify-write (r-m-w)). the user should keep this in mind when operating on some special function registers, such as ports. note: status bits that are manipulated by the device (including the interrupt ?g bits) are set or cleared in the q1 cycle. so there is no issue on doing r-m-w instructions on registers which contain these bits
1997 microchip technology inc. ds30264a-page 185 pic17c75x 18.2 q cycle activity each instruction cycle (tcy) is comprised of four q cycles (q1-q4). the q cycle is the same as the device oscillator cycle (t osc ). the q cycles provide the tim- ing/designation for the decode, read, process data, write etc., of each instruction cycle. the following dia- gram shows the relationship of the q cycles to the instruction cycle. the four q cycles that make up an instruction cycle (tcy) can be generalized as: q1: instruction decode cycle or forced no operation q2: instruction read cycle or no operation q3: process the data q4: instruction write cycle or no operation each instruction will show the detailed q cycle opera- tion for the instruction. figure 18-2: q cycle activity q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 tcy1 tcy2 tcy3 tosc
pic17c75x ds30264a-page 186 1997 microchip technology inc. table 18-2: pic17cxxx instruction set mnemonic, operands description cycles 16-bit opcode status affected notes msb lsb byte-oriented file register operations addwf f,d add wreg to f 1 0000 111d ffff ffff ov,c,dc,z addwfc f,d add wreg and carry bit to f 1 0001 000d ffff ffff ov,c,dc,z andwf f,d and wreg with f 1 0000 101d ffff ffff z clrf f,s clear f, or clear f and clear wreg 1 0010 100s ffff ffff none 3 comf f,d complement f 1 0001 001d ffff ffff z cpfseq f compare f with wreg, skip if f = wreg 1 (2) 0011 0001 ffff ffff none 6,8 cpfsgt f compare f with wreg, skip if f > wreg 1 (2) 0011 0010 ffff ffff none 2,6,8 cpfslt f compare f with wreg, skip if f < wreg 1 (2) 0011 0000 ffff ffff none 2,6,8 daw f,s decimal adjust wreg register 1 0010 111s ffff ffff c3 decf f,d decrement f 1 0000 011d ffff ffff ov,c,dc,z decfsz f,d decrement f, skip if 0 1 (2) 0001 011d ffff ffff none 6,8 dcfsnz f,d decrement f, skip if not 0 1 (2) 0010 011d ffff ffff none 6,8 incf f,d increment f 1 0001 010d ffff ffff ov,c,dc,z incfsz f,d increment f, skip if 0 1 (2) 0001 111d ffff ffff none 6,8 infsnz f,d increment f, skip if not 0 1 (2) 0010 010d ffff ffff none 6,8 iorwf f,d inclusive or wreg with f 1 0000 100d ffff ffff z movfp f,p move f to p 1 011p pppp ffff ffff none movpf p,f move p to f 1 010p pppp ffff ffff z movwf f move wreg to f 1 0000 0001 ffff ffff none mulwf f multiply wreg with f 1 0011 0100 ffff ffff none negw f,s negate wreg 1 0010 110s ffff ffff ov,c,dc,z 1,3 nop no operation 1 0000 0000 0000 0000 none rlcf f,d rotate left f through carry 1 0001 101d ffff ffff c rlncf f,d rotate left f (no carry) 1 0010 001d ffff ffff none rrcf f,d rotate right f through carry 1 0001 100d ffff ffff c rrncf f,d rotate right f (no carry) 1 0010 000d ffff ffff none setf f,s set f 1 0010 101s ffff ffff none 3 subwf f,d subtract wreg from f 1 0000 010d ffff ffff ov,c,dc,z 1 subwfb f,d subtract wreg from f with borrow 1 0000 001d ffff ffff ov,c,dc,z 1 swapf f,d swap f 1 0001 110d ffff ffff none tablrd t,i,f table read 2 (3) 1010 10ti ffff ffff none 7 tablwt t,i,f table write 2 1010 11ti ffff ffff none 5 legend: refer to table 18-1 for opcode ?ld descriptions. note 1: 2s complement method. 2: unsigned arithmetic. 3: if s = '1', only the ?e is affected: if s = '0', both the wreg register and the ?e are affected; if only the work- ing register (wreg) is required to be affected, then f = wreg must be speci?d. 4: during an lcall , the contents of pclath are loaded into the msb of the pc and kkkk kkkk is loaded into the lsb of the pc (pcl) 5: multiple cycle instruction for eprom programming when table pointer selects internal eprom. the instruc- tion is terminated by an interrupt event. when writing to external program memory, it is a two-cycle instruc- tion. 6: two-cycle instruction when condition is true, else single cycle instruction. 7: two-cycle instruction except for tablrd to pcl (program counter low byte) in which case it takes 3 cycles. 8: a ?kip means that instruction fetched during execution of current instruction is not executed, instead an nop is executed.
1997 microchip technology inc. ds30264a-page 187 pic17c75x tlrd t,f table latch read 1 1010 00tx ffff ffff none tlwt t,f table latch write 1 1010 01tx ffff ffff none tstfsz f test f, skip if 0 1 (2) 0011 0011 ffff ffff none 6,8 xorwf f,d exclusive or wreg with f 1 0000 110d ffff ffff z bit-oriented file register operations bcf f,b bit clear f 1 1000 1bbb ffff ffff none bsf f,b bit set f 1 1000 0bbb ffff ffff none btfsc f,b bit test, skip if clear 1 (2) 1001 1bbb ffff ffff none 6,8 btfss f,b bit test, skip if set 1 (2) 1001 0bbb ffff ffff none 6,8 btg f,b bit toggle f 1 0011 1bbb ffff ffff none literal and control operations addlw k add literal to wreg 1 1011 0001 kkkk kkkk ov,c,dc,z andlw k and literal with wreg 1 1011 0101 kkkk kkkk z call k subroutine call 2 111k kkkk kkkk kkkk none 7 clrwdt clear watchdog timer 1 0000 0000 0000 0100 t o ,pd goto k unconditional branch 2 110k kkkk kkkk kkkk none 7 iorlw k inclusive or literal with wreg 1 1011 0011 kkkk kkkk z lcall k long call 2 1011 0111 kkkk kkkk none 4,7 movlb k move literal to low nibble in bsr 1 1011 1000 uuuu kkkk none movlr k move literal to high nibble in bsr 1 1011 101x kkkk uuuu none movlw k move literal to wreg 1 1011 0000 kkkk kkkk none mullw k multiply literal with wreg 1 1011 1100 kkkk kkkk none retfie return from interrupt (and enable interrupts) 2 0000 0000 0000 0101 glintd 7 retlw k return literal to wreg 2 1011 0110 kkkk kkkk none 7 return return from subroutine 2 0000 0000 0000 0010 none 7 sleep enter sleep mode 1 0000 0000 0000 0011 t o , pd sublw k subtract wreg from literal 1 1011 0010 kkkk kkkk ov,c,dc,z xorlw k exclusive or literal with wreg 1 1011 0100 kkkk kkkk z table 18-2: pic17cxxx instruction set (cont.?) mnemonic, operands description cycles 16-bit opcode status affected notes msb lsb legend: refer to table 18-1 for opcode ?ld descriptions. note 1: 2s complement method. 2: unsigned arithmetic. 3: if s = '1', only the ?e is affected: if s = '0', both the wreg register and the ?e are affected; if only the work- ing register (wreg) is required to be affected, then f = wreg must be speci?d. 4: during an lcall , the contents of pclath are loaded into the msb of the pc and kkkk kkkk is loaded into the lsb of the pc (pcl) 5: multiple cycle instruction for eprom programming when table pointer selects internal eprom. the instruc- tion is terminated by an interrupt event. when writing to external program memory, it is a two-cycle instruc- tion. 6: two-cycle instruction when condition is true, else single cycle instruction. 7: two-cycle instruction except for tablrd to pcl (program counter low byte) in which case it takes 3 cycles. 8: a ?kip means that instruction fetched during execution of current instruction is not executed, instead an nop is executed.
pic17c75x ds30264a-page 188 1997 microchip technology inc. addlw add literal to wreg syntax: [ label ] addlw k operands: 0 k 255 operation: (wreg) + k ? (wreg) status affected: ov, c, dc, z encoding: 1011 0001 kkkk kkkk description: the contents of wreg are added to the 8-bit literal 'k' and the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to wreg example : addlw 0x15 before instruction wreg = 0x10 after instruction wreg = 0x25 addwf add wreg to f syntax: [ label ] addwf f,d operands: 0 f 255 d ? [0,1] operation: (wreg) + (f) ? (dest) status affected: ov, c, dc, z encoding: 0000 111d ffff ffff description: add wreg to register 'f'. if 'd' is 0 the result is stored in wreg. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example : addwf reg, 0 before instruction wreg = 0x17 reg = 0xc2 after instruction wreg = 0xd9 reg = 0xc2
1997 microchip technology inc. ds30264a-page 189 pic17c75x addwfc add wreg and carry bit to f syntax: [ label ] addwfc f,d operands: 0 f 255 d ? [0,1] operation: (wreg) + (f) + c ? (dest) status affected: ov, c, dc, z encoding: 0001 000d ffff ffff description: add wreg, the carry flag and data memory location 'f'. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed in data memory location 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example : addwfc reg 0 before instruction carry bit = 1 reg = 0x02 wreg = 0x4d after instruction carry bit = 0 reg = 0x02 wreg = 0x50 andlw and literal with wreg syntax: [ label ] andlw k operands: 0 k 255 operation: (wreg) .and. (k) ? (wreg) status affected: z encoding: 1011 0101 kkkk kkkk description: the contents of wreg are and?d with the 8-bit literal 'k'. the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to wreg example : andlw 0x5f before instruction wreg = 0xa3 after instruction wreg = 0x03
pic17c75x ds30264a-page 190 1997 microchip technology inc. andwf and wreg with f syntax: [ label ] andwf f,d operands: 0 f 255 d ? [0,1] operation: (wreg) .and. (f) ? (dest) status affected: z encoding: 0000 101d ffff ffff description: the contents of wreg are and?d with register 'f'. if 'd' is 0 the result is stored in wreg. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example : andwf reg, 1 before instruction wreg = 0x17 reg = 0xc2 after instruction wreg = 0x17 reg = 0x02 bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 255 0 b 7 operation: 0 ? (f) status affected: none encoding: 1000 1bbb ffff ffff description: bit 'b' in register 'f' is cleared. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'f' example : bcf flag_reg, 7 before instruction flag_reg = 0xc7 after instruction flag_reg = 0x47
1997 microchip technology inc. ds30264a-page 191 pic17c75x bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 255 0 b 7 operation: 1 ? (f) status affected: none encoding: 1000 0bbb ffff ffff description: bit 'b' in register 'f' is set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'f' example : bsf flag_reg, 7 before instruction flag_reg= 0x0a after instruction flag_reg= 0x8a btfsc bit test, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 255 0 b 7 operation: skip if (f) = 0 status affected: none encoding: 1001 1bbb ffff ffff description: if bit 'b' in register ?' is 0 then the next instruction is skipped. if bit 'b' is 0 then the next instruction fetched during the current instruction exe- cution is discarded, and a nop is exe- cuted instead, making this a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: q1 q2 q3 q4 decode read register 'f' process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation example : here false true btfsc : : flag,1 before instruction pc = address (here) after instruction if flag<1> = 0; pc = address (true) if flag<1> = 1; pc = address (false)
pic17c75x ds30264a-page 192 1997 microchip technology inc. btfss bit test, skip if set syntax: [ label ] btfss f,b operands: 0 f 127 0 b < 7 operation: skip if (f) = 1 status affected: none encoding: 1001 0bbb ffff ffff description: if bit 'b' in register 'f' is 1 then the next instruction is skipped. if bit 'b' is 1, then the next instruction fetched during the current instruction exe- cution, is discarded and an nop is exe- cuted instead, making this a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: q1 q2 q3 q4 decode read register 'f' process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation example : here false true btfss : : flag,1 before instruction pc = address (here) after instruction if flag<1> = 0; pc = address (false) if flag<1> = 1; pc = address (true) btg bit toggle f syntax: [ label ] btg f,b operands: 0 f 255 0 b < 7 operation: (f ) ? (f) status affected: none encoding: 0011 1bbb ffff ffff description: bit 'b' in data memory location 'f' is inverted. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'f' example : btg portc, 4 before instruction: portc = 0111 0101 [0x75] after instruction: portc = 0110 0101 [0x65]
1997 microchip technology inc. ds30264a-page 193 pic17c75x call subroutine call syntax: [ label ] call k operands: 0 k 4095 operation: pc+ 1 ? tos, k ? pc<12:0>, k<12:8> ? pclath<4:0>; pc<15:13> ? pclath<7:5> status affected: none encoding: 111k kkkk kkkk kkkk description: subroutine call within 8k page. first, return address (pc+1) is pushed onto the stack. the 13-bit value is loaded into pc bits<12:0>. then the upper-eight bits of the pc are copied into pclath. call is a two-cycle instruction. see lcall for calls outside 8k memory space. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal 'k'<7:0>, push pc to stack process data write to pc no operation no operation no operation no operation example : here call there before instruction pc = address (here) after instruction pc = address (there) tos = address (here + 1) clrf clear f syntax: [ label ] clrf f,s operands: 0 f 255 operation: 00h ? f, s ? [0,1] 00h ? dest status affected: none encoding: 0010 100s ffff ffff description: clears the contents of the speci?d reg- ister(s). s = 0: data memory location 'f' and wreg are cleared. s = 1: data memory location 'f' is cleared. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'f' and if speci?d wreg example : clrf flag_reg before instruction flag_reg = 0x5a after instruction flag_reg = 0x00
pic17c75x ds30264a-page 194 1997 microchip technology inc. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h ? wdt 0 ? wdt postscaler, 1 ? t o 1 ? pd status affected: t o , pd encoding: 0000 0000 0000 0100 description: clrwdt instruction resets the watch- dog timer. it also resets the prescaler of the wdt. status bits t o and pd are set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data no operation example : clrwdt before instruction wdt counter = ? after instruction wdt counter = 0x00 wdt postscaler = 0 t o =1 pd =1 comf complement f syntax: [ label ] comf f,d operands: 0 f 255 d ? [0,1] operation: ? (dest) status affected: z encoding: 0001 001d ffff ffff description: the contents of register 'f' are comple- mented. if 'd' is 0 the result is stored in wreg. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example : comf reg1,0 before instruction reg1 = 0x13 after instruction reg1 = 0x13 wreg = 0xec (f)
1997 microchip technology inc. ds30264a-page 195 pic17c75x cpfseq compare f with wreg, skip if f = wreg syntax: [ label ] cpfseq f operands: 0 f 255 operation: (f) ?(wreg), skip if (f) = (wreg) (unsigned comparison) status affected: none encoding: 0011 0001 ffff ffff description: compares the contents of data memory location 'f' to the contents of wreg by performing an unsigned subtraction. if 'f' = wreg then the fetched instruc- tion is discarded and an nop is exe- cuted instead making this a two-cycle instruction. words: 1 cycles: 1 (2) q cycle activity: q1 q2 q3 q4 decode read register 'f' process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation example : here cpfseq reg nequal : equal : before instruction pc address = here wreg = ? reg = ? after instruction if reg = wreg; pc = address (equal) if reg 1 wreg; pc = address (nequal) cpfsgt compare f with wreg, skip if f > wreg syntax: [ label ] cpfsgt f operands: 0 f 255 operation: (f) - ( wreg), skip if (f) > (wreg) (unsigned comparison) status affected: none encoding: 0011 0010 ffff ffff description: compares the contents of data memory location 'f' to the contents of the wreg by performing an unsigned subtraction. if the contents of 'f' are greater than the contents of wreg then the fetched instruction is discarded and an nop is executed instead making this a two-cycle instruction. words: 1 cycles: 1 (2) q cycle activity: q1 q2 q3 q4 decode read register 'f' process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation example : here cpfsgt reg ngreater : greater : before instruction pc = address (here) wreg = ? after instruction if reg > wreg; pc = address (greater) if reg wreg; pc = address (ngreater)
pic17c75x ds30264a-page 196 1997 microchip technology inc. cpfslt compare f with wreg, skip if f < wreg syntax: [ label ] cpfslt f operands: 0 f 255 operation: (f) ( wreg), skip if (f) < (wreg) (unsigned comparison) status affected: none encoding: 0011 0000 ffff ffff description: compares the contents of data memory location 'f' to the contents of wreg by performing an unsigned subtraction. if the contents of 'f' are less than the contents of wreg, then the fetched instruction is discarded and an nop is executed instead making this a two-cycle instruction. words: 1 cycles: 1 (2) q cycle activity: q1 q2 q3 q4 decode read register 'f' process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation example : here cpfslt reg nless : less : before instruction pc = address (here) w= ? after instruction if reg < wreg; pc = address (less) if reg 3 wreg; pc = address (nless) daw decimal adjust wreg register syntax: [ label ] daw f,s operands: 0 f 255 s ? [0,1] operation: if [wreg<3:0> >9] .or. [dc = 1] then wreg<3:0> + 6 ? f<3:0>, s<3:0>; else wreg<3:0> ? f<3:0>, s<3:0>; if [wreg<7:4> >9] .or. [c = 1] then wreg<7:4> + 6 ? f<7:4>, s<7:4> else wreg<7:4> ? f<7:4>, s<7:4> status affected: c encoding: 0010 111s ffff ffff description: daw adjusts the eight bit value in wreg resulting from the earlier addi- tion of two variables (each in packed bcd format) and produces a correct packed bcd result. s = 0: result is placed in data memory location 'f' and wreg. s = 1: result is placed in data memory location 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'f' and other speci?d register example1 : daw reg1, 0 before instruction wreg = 0xa5 reg1 = ?? c=0 dc = 0 after instruction wreg = 0x05 reg1 = 0x05 c=1 dc = 0 example 2 : before instruction wreg = 0xce reg1 = ?? c=0 dc = 0 after instruction wreg = 0x24 reg1 = 0x24 c=1 dc = 0
1997 microchip technology inc. ds30264a-page 197 pic17c75x decf decrement f syntax: [ label ] decf f,d operands: 0 f 255 d ? [0,1] operation: (f) ?1 ? (dest) status affected: ov, c, dc, z encoding: 0000 011d ffff ffff description: decrement register 'f'. if 'd' is 0 the result is stored in wreg. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example : decf cnt, 1 before instruction cnt = 0x01 z=0 after instruction cnt = 0x00 z=1 decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 255 d ? [0,1] operation: (f) ?1 ? (dest); skip if result = 0 status affected: none encoding: 0001 011d ffff ffff description: the contents of register 'f' are decre- mented. if 'd' is 0 the result is placed in wreg. if 'd' is 1 the result is placed back in register 'f'. if the result is 0, the next instruction, which is already fetched, is discarded, and an nop is executed instead mak- ing it a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation example : here decfsz cnt, 1 goto loop continue before instruction pc = address (here) after instruction cnt = cnt - 1 if cnt = 0; pc = address (continue) if cnt 1 0; pc = address (here+1)
pic17c75x ds30264a-page 198 1997 microchip technology inc. dcfsnz decrement f, skip if not 0 syntax: [ label ] dcfsnz f,d operands: 0 f 255 d ? [0,1] operation: (f) ?1 ? (dest); skip if not 0 status affected: none encoding: 0010 011d ffff ffff description: the contents of register 'f' are decre- mented. if 'd' is 0 the result is placed in wreg. if 'd' is 1 the result is placed back in register 'f'. if the result is not 0, the next instruc- tion, which is already fetched, is dis- carded, and an nop is executed instead making it a two-cycle instruc- tion. words: 1 cycles: 1(2) q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation example : here dcfsnz temp, 1 zero : nzero : before instruction temp_value = ? after instruction temp_value = temp_value - 1, if temp_value = 0; pc = address (zero ) if temp_value 1 0; pc = address (nzero) goto unconditional branch syntax: [ label ] goto k operands: 0 k 8191 operation: k ? pc<12:0>; k<12:8> ? pclath<4:0>, pc <15 :13> ? pclath<7:5> status affected: none encoding: 110k kkkk kkkk kkkk description: goto allows an unconditional branch anywhere within an 8k page bound- ary. the thirteen bit immediate value is loaded into pc bits <12:0>. then the upper eight bits of pc are loaded into pclath. goto is always a two-cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to pc no operation no operation no operation no operation example : goto there after instruction pc = address (there)
1997 microchip technology inc. ds30264a-page 199 pic17c75x incf increment f syntax: [ label ] incf f,d operands: 0 f 255 d ? [0,1] operation: (f) + 1 ? (dest) status affected: ov, c, dc, z encoding: 0001 010d ffff ffff description: the contents of register 'f' are incre- mented. if 'd' is 0 the result is placed in wreg. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example : incf cnt, 1 before instruction cnt = 0xff z=0 c=? after instruction cnt = 0x00 z=1 c=1 incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 255 d ? [0,1] operation: (f) + 1 ? (dest) skip if result = 0 status affected: none encoding: 0001 111d ffff ffff description: the contents of register 'f' are incre- mented. if 'd' is 0 the result is placed in wreg. if 'd' is 1 the result is placed back in register 'f'. if the result is 0, the next instruction, which is already fetched, is discarded, and an nop is executed instead mak- ing it a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation example : here incfsz cnt, 1 nzero : zero : before instruction pc = address (here) after instruction cnt = cnt + 1 if cnt = 0; pc = address (zero) if cnt 1 0; pc = address (nzero)
pic17c75x ds30264a-page 200 1997 microchip technology inc. infsnz increment f, skip if not 0 syntax: [ label ] infsnz f,d operands: 0 f 255 d ? [0,1] operation: (f) + 1 ? (dest), skip if not 0 status affected: none encoding: 0010 010d ffff ffff description: the contents of register 'f' are incre- mented. if 'd' is 0 the result is placed in wreg. if 'd' is 1 the result is placed back in register 'f'. if the result is not 0, the next instruction, which is already fetched, is discarded, and an nop is executed instead mak- ing it a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation example : here infsnz reg, 1 zero nzero before instruction reg = reg after instruction reg = reg + 1 if reg = 1; pc = address (zero) if reg = 0; pc = address (nzero) iorlw inclusive or literal with wreg syntax: [ label ] iorlw k operands: 0 k 255 operation: (wreg) .or. (k) ? (wreg) status affected: z encoding: 1011 0011 kkkk kkkk description: the contents of wreg are or?d with the eight bit literal 'k'. the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to wreg example : iorlw 0x35 before instruction wreg = 0x9a after instruction wreg = 0xbf
1997 microchip technology inc. ds30264a-page 201 pic17c75x iorwf inclusive or wreg with f syntax: [ label ] iorwf f,d operands: 0 f 255 d ? [0,1] operation: (wreg) .or. (f) ? (dest) status affected: z encoding: 0000 100d ffff ffff description: inclusive or wreg with register 'f'. if 'd' is 0 the result is placed in wreg. if 'd' is 1 the result is placed back in regis- ter 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example : iorwf result, 0 before instruction result = 0x13 wreg = 0x91 after instruction result = 0x13 wreg = 0x93 lcall long call syntax: [ label ] lcall k operands: 0 k 255 operation: pc + 1 ? tos; k ? pcl, (pclath) ? pch status affected: none encoding: 1011 0111 kkkk kkkk description: lcall allows an unconditional subrou- tine call to anywhere within the 64k pro- gram memory space. first, the return address (pc + 1) is pushed onto the stack. a 16-bit desti- nation address is then loaded into the program counter. the lower 8-bits of the destination address is embedded in the instruction. the upper 8-bits of pc is loaded from pc high holding latch, pclath. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write register pcl no operation no operation no operation no operation example : movlw high(subroutine) movpf wreg, pclath lcall low(subroutine) before instruction subroutine = 16-bit address pc = ? after instruction pc = address (subroutine)
pic17c75x ds30264a-page 202 1997 microchip technology inc. movfp move f to p syntax: [ label ] movfp f,p operands: 0 f 255 0 p 31 operation: (f) ? (p) status affected: none encoding: 011p pppp ffff ffff description: move data from data memory location 'f' to data memory location 'p'. location 'f' can be anywhere in the 256 word data space (00h to ffh) while 'p' can be 00h to 1fh. either ?' or 'f' can be wreg (a useful special situation). movfp is particularly useful for transfer- ring a data memory location to a periph- eral register (such as the transmit buffer or an i/o port). both 'f' and 'p' can be indirectly addressed. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'p' example : movfp reg1, reg2 before instruction reg1 = 0x33, reg2 = 0x11 after instruction reg1 = 0x33, reg2 = 0x33 movlb move literal to low nibble in bsr syntax: [ label ] movlb k operands: 0 k 15 operation: k ? (bsr<3:0>) status affected: none encoding: 1011 1000 uuuu kkkk description: the four bit literal 'k' is loaded in the bank select register (bsr). only the low 4-bits of the bank select register are affected. the upper half of the bsr is unchanged. the assembler will encode the ? ?lds as '0'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write literal 'k' to bsr<3:0> example : movlb 5 before instruction bsr register = 0x22 after instruction bsr register = 0x25 (bank 5)
1997 microchip technology inc. ds30264a-page 203 pic17c75x movlr move literal to high nibble in bsr syntax: [ label ] movlr k operands: 0 k 15 operation: k ? (bsr<7:4>) status affected: none encoding: 1011 101x kkkk uuuu description: the 4-bit literal 'k' is loaded into the most signi?ant 4-bits of the bank select register (bsr). only the high 4-bits of the bank select register are affected. the lower half of the bsr is unchanged. the assembler will encode the ? ?lds as 0. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write literal 'k' to bsr<7:4> example : movlr 5 before instruction bsr register = 0x22 after instruction bsr register = 0x52 movlw move literal to wreg syntax: [ label ] movlw k operands: 0 k 255 operation: k ? (wreg) status affected: none encoding: 1011 0000 kkkk kkkk description: the eight bit literal 'k' is loaded into wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to wreg example : movlw 0x5a after instruction wreg = 0x5a
pic17c75x ds30264a-page 204 1997 microchip technology inc. movpf move p to f syntax: [ label ] movpf p,f operands: 0 f 255 0 p 31 operation: (p) ? (f) status affected: z encoding: 010p pppp ffff ffff description: move data from data memory location 'p' to data memory location 'f'. location 'f' can be anywhere in the 256 byte data space (00h to ffh) while 'p' can be 00h to 1fh. either 'p' or 'f' can be wreg (a useful special situation). movpf is particularly useful for transfer- ring a peripheral register (e.g. the timer or an i/o port) to a data memory loca- tion. both 'f' and 'p' can be indirectly addressed. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'p' process data write register 'f' example : movpf reg1, reg2 before instruction reg1 = 0x11 reg2 = 0x33 after instruction reg1 = 0x11 reg2 = 0x11 movwf move wreg to f syntax: [ label ] movwf f operands: 0 f 255 operation: (wreg) ? (f) status affected: none encoding: 0000 0001 ffff ffff description: move data from wreg to register 'f'. location 'f' can be anywhere in the 256 word data space. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'f' example : movwf reg before instruction wreg = 0x4f reg = 0xff after instruction wreg = 0x4f reg = 0x4f
1997 microchip technology inc. ds30264a-page 205 pic17c75x mullw multiply literal with wreg syntax: [ label ] mullw k operands: 0 k 255 operation: (k x wreg) ? prodh:prodl status affected: none encoding: 1011 1100 kkkk kkkk description: an unsigned multiplication is carried out between the contents of wreg and the 8-bit literal 'k'. the 16-bit result is placed in prodh:prodl register pair. prodh contains the high byte. wreg is unchanged. none of the status ?gs are affected. note that neither over?w nor carry is possible in this operation. a zero result is possible but not detected. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write registers prodh: prodl example : mullw 0xc4 before instruction wreg = 0xe2 prodh = ? prodl = ? after instruction wreg = 0xc4 prodh = 0xad prodl = 0x08 mulwf multiply wreg with f syntax: [ label ] mulwf f operands: 0 f 255 operation: (wreg x f) ? prodh:prodl status affected: none encoding: 0011 0100 ffff ffff description: an unsigned multiplication is carried out between the contents of wreg and the register ?e location 'f'. the 16-bit result is stored in the prodh:prodl register pair. prodh contains the high byte. both wreg and 'f' are unchanged. none of the status ?gs are affected. note that neither over?w nor carry is possible in this operation. a zero result is possible but not detected. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write registers prodh: prodl example : mulwf reg before instruction wreg = 0xc4 reg = 0xb5 prodh = ? prodl = ? after instruction wreg = 0xc4 reg = 0xb5 prodh = 0x8a prodl = 0x94
pic17c75x ds30264a-page 206 1997 microchip technology inc. negw negate w syntax: [ label ] negw f,s operands: 0 f 255 s ? [0,1] operation: wreg + 1 ? (f); wreg + 1 ? s status affected: ov, c, dc, z encoding: 0010 110s ffff ffff description: wreg is negated using twos comple- ment. if 's' is 0 the result is placed in wreg and data memory location 'f'. if 's' is 1 the result is placed only in data memory location 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'f' and other speci?d register example : negw reg,0 before instruction wreg = 0011 1010 [0x3a], reg = 1010 1011 [0xab] after instruction wreg = 1100 0111 [0xc6] reg = 1100 0111 [0xc6] nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none encoding: 0000 0000 0000 0000 description: no operation. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation example : none.
1997 microchip technology inc. ds30264a-page 207 pic17c75x retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos ? (pc); 0 ? glintd; pclath is unchanged. status affected: glintd encoding: 0000 0000 0000 0101 description: return from interrupt. stack is pop?d and top of stack (tos) is loaded in the pc. interrupts are enabled by clearing the glintd bit. glintd is the global interrupt disable bit (cpusta<4>). words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation clear glintd pop pc from stack no operation no operation no operation no operation example : retfie after interrupt pc = tos glintd = 0 retlw return literal to wreg syntax: [ label ] retlw k operands: 0 k 255 operation: k ? (wreg); tos ? (pc); pclath is unchanged status affected: none encoding: 1011 0110 kkkk kkkk description: wreg is loaded with the eight bit literal 'k'. the program counter is loaded from the top of the stack (the return address). the high address latch (pclath) remains unchanged. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data pop pc from stack, write to wreg no operation no operation no operation no operation example : call table ; wreg contains table ; offset value ; wreg now has ; table value : table addwf pc ; wreg = offset retlw k0 ; begin table retlw k1 ; : : retlw kn ; end of table before instruction wreg = 0x07 after instruction wreg = value of k7
pic17c75x ds30264a-page 208 1997 microchip technology inc. return return from subroutine syntax: [ label ] return operands: none operation: tos ? pc; status affected: none encoding: 0000 0000 0000 0010 description: return from subroutine. the stack is popped and the top of the stack (tos) is loaded into the program counter. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation process data pop pc from stack no operation no operation no operation no operation example : return after interrupt pc = tos rlcf rotate left f through carry syntax: [ label ] rlcf f,d operands: 0 f 255 d ? [0,1] operation: f ? d; f<7> ? c; c ? d<0> status affected: c encoding: 0001 101d ffff ffff description: the contents of register 'f' are rotated one bit to the left through the carry flag. if 'd' is 0 the result is placed in wreg. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example : rlcf reg,0 before instruction reg = 1110 0110 c=0 after instruction reg = 1110 0110 wreg = 1100 1100 c=1 c register f
1997 microchip technology inc. ds30264a-page 209 pic17c75x rlncf rotate left f (no carry) syntax: [ label ] rlncf f,d operands: 0 f 255 d ? [0,1] operation: f ? d; f<7> ? d<0> status affected: none encoding: 0010 001d ffff ffff description: the contents of register 'f' are rotated one bit to the left. if 'd' is 0 the result is placed in wreg. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example : rlncf reg, 1 before instruction c=0 reg = 1110 1011 after instruction c= reg = 1101 0111 register f rrcf rotate right f through carry syntax: [ label ] rrcf f,d operands: 0 f 255 d ? [0,1] operation: f ? d; f<0> ? c; c ? d<7> status affected: c encoding: 0001 100d ffff ffff description: the contents of register 'f' are rotated one bit to the right through the carry flag. if 'd' is 0 the result is placed in wreg. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example : rrcf reg1,0 before instruction reg1 = 1110 0110 c= 0 after instruction reg1 = 1110 0110 wreg = 0111 0011 c= 0 c register f
pic17c75x ds30264a-page 210 1997 microchip technology inc. rrncf rotate right f (no carry) syntax: [ label ] rrncf f,d operands: 0 f 255 d ? [0,1] operation: f ? d; f<0> ? d<7> status affected: none encoding: 0010 000d ffff ffff description: the contents of register 'f' are rotated one bit to the right. if 'd' is 0 the result is placed in wreg. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example 1 : rrncf reg, 1 before instruction wreg = ? reg = 1101 0111 after instruction wreg = 0 reg = 1110 1011 example 2 : rrncf reg, 0 before instruction wreg = ? reg = 1101 0111 after instruction wreg = 1110 1011 reg = 1101 0111 register f setf set f syntax: [ label ] setf f,s operands: 0 f 255 s ? [0,1] operation: ffh ? f; ffh ? d status affected: none encoding: 0010 101s ffff ffff description: if 's' is 0, both the data memory location 'f' and wreg are set to ffh. if 's' is 1 only the data memory location 'f' is set to ffh. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'f' and other speci?d register example1 : setf reg, 0 before instruction reg = 0xda wreg = 0x05 after instruction reg = 0xff wreg = 0xff example2 : setf reg, 1 before instruction reg = 0xda wreg = 0x05 after instruction reg = 0xff wreg = 0x05
1997 microchip technology inc. ds30264a-page 211 pic17c75x sleep enter sleep mode syntax: [ label ] sleep operands: none operation: 00h ? wdt; 0 ? wdt postscaler; 1 ? t o ; 0 ? pd status affected: t o , pd encoding: 0000 0000 0000 0011 description: the power-down status bit (pd ) is cleared. the time-out status bit (t o ) is set. watchdog timer and its pres- caler are cleared. the processor is put into sleep mode with the oscillator stopped. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data go to sleep example : sleep before instruction t o =? pd =? after instruction t o =1 ? pd =0 ? if wdt causes wake-up, this bit is cleared sublw subtract wreg from literal syntax: [ label ] sublw k operands: 0 k 255 operation: k ?(wreg) ? ( wreg) status affected: ov, c, dc, z encoding: 1011 0010 kkkk kkkk description: wreg is subtracted from the eight bit literal 'k'. the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to wreg example 1 : sublw 0x02 before instruction wreg = 1 c=? after instruction wreg = 1 c = 1 ; result is positive z=0 example 2 : before instruction wreg = 2 c=? after instruction wreg = 0 c = 1 ; result is zero z=1 example 3 : before instruction wreg = 3 c=? after instruction wreg = ff ; (2s complement) c = 0 ; result is negative z=1
pic17c75x ds30264a-page 212 1997 microchip technology inc. subwf subtract wreg from f syntax: [ label ] subwf f,d operands: 0 f 255 d ? [0,1] operation: (f) ?(w) ? ( dest) status affected: ov, c, dc, z encoding: 0000 010d ffff ffff description: subtract wreg from register 'f' (2s complement method). if 'd' is 0 the result is stored in wreg. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example 1 : subwf reg1, 1 before instruction reg1 = 3 wreg = 2 c=? after instruction reg1 = 1 wreg = 2 c = 1 ; result is positive z=0 example 2 : before instruction reg1 = 2 wreg = 2 c=? after instruction reg1 = 0 wreg = 2 c = 1 ; result is zero z=1 example 3 : before instruction reg1 = 1 wreg = 2 c=? after instruction reg1 = ff wreg = 2 c = 0 ; result is negative z=0 subwfb subtract wreg from f with borrow syntax: [ label ] subwfb f,d operands: 0 f 255 d ? [0,1] operation: (f) ?(w) ?c ? ( dest) status affected: ov, c, dc, z encoding: 0000 001d ffff ffff description: subtract wreg and the carry ?g (borrow) from register 'f' (2s comple- ment method). if 'd' is 0 the result is stored in wreg. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example 1 : subwfb reg1, 1 before instruction reg1 = 0x19 ( 0001 1001 ) wreg = 0x0d ( 0000 1101 ) c=1 after instruction reg1 = 0x0c ( 0000 1011 ) wreg = 0x0d ( 0000 1101 ) c = 1 ; result is positive z=0 example2 : subwfb reg1,0 before instruction reg1 = 0x1b ( 0001 1011 ) wreg = 0x1a ( 0001 1010 ) c=0 after instruction reg1 = 0x1b ( 0001 1011 ) wreg = 0x00 c = 1 ; result is zero z=1 example3 : subwfb reg1,1 before instruction reg1 = 0x03 ( 0000 0011 ) wreg = 0x0e ( 0000 1101 ) c=1 after instruction reg1 = 0xf5 ( 1111 0100 ) [2s comp] wreg = 0x0e ( 0000 1101 ) c = 0 ; result is negative z=0
1997 microchip technology inc. ds30264a-page 213 pic17c75x swapf swap f syntax: [ label ] swapf f,d operands: 0 f 255 d ? [0,1] operation: f<3:0> ? dest<7:4>; f<7:4> ? dest<3:0> status affected: none encoding: 0001 110d ffff ffff description: the upper and lower nibbles of register 'f' are exchanged. if 'd' is 0 the result is placed in wreg. if 'd' is 1 the result is placed in register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example : swapf reg, 0 before instruction reg = 0x53 after instruction reg = 0x35 tablrd table read syntax: [ label ] tablrd t,i,f operands: 0 f 255 i ? [0,1] t ? [0,1] operation: if t = 1, tblath ? f; if t = 0, tblatl ? f; prog mem (tblptr) ? tblat; if i = 1, tblptr + 1 ? tblptr status affected: none encoding: 1010 10ti ffff ffff description: 1. a byte of the table latch (tblat) is moved to register ?e 'f'. if t = 0: the high byte is moved; if t = 1: the low byte is moved 2. then the contents of the program memory location pointed to by the 16-bit table pointer (tblptr) is loaded into the 16-bit table latch (tblat). 3. if i = 1: tblptr is incremented; if i = 0: tblptr is not incremented words: 1 cycles: 2 (3 cycle if f = pcl) q cycle activity: q1 q2 q3 q4 decode read register tblath or tblatl process data write register 'f' no operation no operation (table pointer on address bus) no operation no operation (oe goes low)
pic17c75x ds30264a-page 214 1997 microchip technology inc. tablrd table read example1 : tablrd 1, 1, reg ; before instruction reg = 0x53 tblath = 0xaa tblatl = 0x55 tblptr = 0xa356 memory(tblptr) = 0x1234 after instruction (table write completion) reg = 0xaa tblath = 0x12 tblatl = 0x34 tblptr = 0xa357 memory(tblptr) = 0x5678 example2 : tablrd 0, 0, reg ; before instruction reg = 0x53 tblath = 0xaa tblatl = 0x55 tblptr = 0xa356 memory(tblptr) = 0x1234 after instruction (table write completion) reg = 0x55 tblath = 0x12 tblatl = 0x34 tblptr = 0xa356 memory(tblptr) = 0x1234 tablwt table write syntax: [ label ] tablwt t,i,f operands: 0 f 255 i ? [0,1] t ? [0,1] operation: if t = 0, f ? tblatl; if t = 1, f ? tblath; tblat ? prog mem (tblptr); if i = 1, tblptr + 1 ? tblptr status affected: none encoding: 1010 11ti ffff ffff description: 1. load value in ? into 16-bit table latch (tblat) if t = 0: load into low byte; if t = 1: load into high byte 2. the contents of tblat is written to the program memory location pointed to by tblptr if tblptr points to external program memory location, then the instruction takes two-cycle if tblptr points to an internal eprom location, then the instruction is terminated when an interrupt is received. note: the mclr /v pp pin must be at the programming voltage for successful programming of internal memory. if mclr /v pp = v dd the programming sequence of internal memory will be interrupted. a short write will occur (2 t cy ). the internal memory location will not be affected. 3. the tblptr can be automati- cally incremented if i = 0; tblptr is not incremented if i = 1; tblptr is incremented words: 1 cycles: 2 (many if write is to on-chip eprom program memory) q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register tblath or tblatl no operation no operation (table pointer on address bus) no operation no operation (table latch on address bus, wr goes low)
1997 microchip technology inc. ds30264a-page 215 pic17c75x tablwt table write example1 : tablwt 1, 1, reg before instruction reg = 0x53 tblath = 0xaa tblatl = 0x55 tblptr = 0xa356 memory(tblptr) = 0xffff after instruction (table write completion) reg = 0x53 tblath = 0x53 tblatl = 0x55 tblptr = 0xa357 memory(tblptr - 1) = 0x5355 example 2 : tablwt 0, 0, reg before instruction reg = 0x53 tblath = 0xaa tblatl = 0x55 tblptr = 0xa356 memory(tblptr) = 0xffff after instruction (table write completion) reg = 0x53 tblath = 0xaa tblatl = 0x53 tblptr = 0xa356 memory(tblptr) = 0xaa53 program memory 16 bits 15 0 tblptr tblat data memory 8 bits 15 8 70 tlrd table latch read syntax: [ label ] tlrd t,f operands: 0 f 255 t ? [0,1] operation: if t = 0, tblatl ? f; if t = 1, tblath ? f status affected: none encoding: 1010 00tx ffff ffff description: read data from 16-bit table latch (tblat) into ?e register 'f'. table latch is unaffected. if t = 1; high byte is read if t = 0; low byte is read this instruction is used in conjunction with tablrd to transfer data from pro- gram memory to data memory. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register tblath or tblatl process data write register 'f' example : tlrd t, ram before instruction t=0 ram = ? tblat = 0x00af (tblath = 0x00) (tblatl = 0xaf) after instruction ram = 0xaf tblat = 0x00af (tblath = 0x00) (tblatl = 0xaf) before instruction t=1 ram = ? tblat = 0x00af (tblath = 0x00) (tblatl = 0xaf) after instruction ram = 0x00 tblat = 0x00af (tblath = 0x00) (tblatl = 0xaf) program memory 16 bits 15 0 tblptr tblat data memory 8 bits 15 8 70
pic17c75x ds30264a-page 216 1997 microchip technology inc. tlwt table latch write syntax: [ label ] tlwt t,f operands: 0 f 255 t ? [0,1] operation: if t = 0, f ? tblatl; if t = 1, f ? tblath status affected: none encoding: 1010 01tx ffff ffff description: data from ?e register 'f' is written into the 16-bit table latch (tblat). if t = 1; high byte is written if t = 0; low byte is written this instruction is used in conjunction with tablwt to transfer data from data memory to program memory. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register tblath or tblatl example : tlwt t, ram before instruction t=0 ram = 0xb7 tblat = 0x0000 (tblath = 0x00) (tblatl = 0x00) after instruction ram = 0xb7 tblat = 0x00b7 (tblath = 0x00) (tblatl = 0xb7) before instruction t=1 ram = 0xb7 tblat = 0x0000 (tblath = 0x00) (tblatl = 0x00) after instruction ram = 0xb7 tblat = 0xb700 (tblath = 0xb7) (tblatl = 0x00) tstfsz test f, skip if 0 syntax: [ label ] tstfsz f operands: 0 f 255 operation: skip if f = 0 status affected: none encoding: 0011 0011 ffff ffff description: if 'f' = 0, the next instruction, fetched during the current instruction execution, is discarded and an nop is executed making this a two-cycle instruction. words: 1 cycles: 1 (2) q cycle activity: q1 q2 q3 q4 decode read register 'f' process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation example : here tstfsz cnt nzero : zero : before instruction pc = address( here ) after instruction if cnt = 0x00, pc = address (zero) if cnt 1 0x00, pc = address (nzero)
1997 microchip technology inc. ds30264a-page 217 pic17c75x xorlw exclusive or literal with wreg syntax: [ label ] xorlw k operands: 0 k 255 operation: (wreg) .xor. k ? ( wreg) status affected: z encoding: 1011 0100 kkkk kkkk description: the contents of wreg are xor?d with the 8-bit literal 'k'. the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to wreg example : xorlw 0xaf before instruction wreg = 0xb5 after instruction wreg = 0x1a xorwf exclusive or wreg with f syntax: [ label ] xorwf f,d operands: 0 f 255 d ? [0,1] operation: (wreg) .xor. (f) ? ( dest) status affected: z encoding: 0000 110d ffff ffff description: exclusive or the contents of wreg with register 'f'. if 'd' is 0 the result is stored in wreg. if 'd' is 1 the result is stored back in the register 'f'. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example : xorwf reg, 1 before instruction reg = 0xaf wreg = 0xb5 after instruction reg = 0x1a wreg = 0xb5
pic17c75x ds30264a-page 218 1997 microchip technology inc. notes:
1997 microchip technology inc. ds30264a-page 219 pic17c75x 19.0 development support 19.1 de velopme nt t ools the pic16/17 microcontrollers are supported with a full range of hardware and software development tools: picmaster/picmaster ce real-time in-circuit emulator icepic low-cost pic16c5x and pic16cxxx in-circuit emulator pro mate a ii universal programmer picstart a plus entry-level prototype programmer picdem-1 low-cost demonstration board picdem-2 low-cost demonstration board picdem-3 low-cost demonstration board mpasm assembler mplab-sim software simulator mplab-c (c compiler) fuzzy logic development system ( fuzzy tech a - mp) 19.2 picmaster: high p erf ormance univer sal in-cir cuit em ulator with mplab ide the picmaster universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the pic12c5xx, pic14c000, pic16c5x, pic16cxxx and pic17cxx families. picmaster is supplied with the mplab ? integrated development environment (ide), which allows editing, ?ake and download, and source debugging from a single environment. interchangeable target probes allow the system to be easily recon?ured for emulation of different proces- sors. the universal architecture of the picmaster allows expansion to support all new microchip micro- controllers. the picmaster emulator system has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. the pc compatible 386 (and higher) machine platform and microsoft windows a 3.x environment were chosen to best make these fea- tures available to you, the end user. a ce compliant version of picmaster is available for european union (eu) countries. 19.3 i cepic: lo w-cost pic16cxxx in-cir cuit em ulator icepic is a low-cost in-circuit emulator solution for the microchip pic16c5x and pic16cxxx families of 8-bit otp microcontrollers. icepic is designed to operate on pc-compatible machines ranging from 286-at a through pentium ? based machines under windows 3.x environment. icepic features real time, non-intrusive emulation. 19.4 pr o ma te ii: univer sal pr ogrammer the pro mate ii universal programmer is a full-fea- tured programmer capable of operating in stand-alone mode as well as pc-hosted mode. the pro mate ii has programmable v dd and v pp supplies which allows it to verify programmed memory at v dd min and v dd max for maximum reliability. it has an lcd display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand- alone mode the pro mate ii can read, verify or pro- gram pic16c5x, pic16cxxx, pic17cxx and pic14000 devices. it can also set con?uration and code-protect bits in this mode. 19.5 p icst ar t plus entr y le vel de velopment system the picstart programmer is an easy-to-use, low- cost prototype programmer. it connects to the pc via one of the com (rs-232) ports. mplab integrated development environment software makes using the programmer simple and ef?ient. picstart plus is not recommended for production programming. picstart plus supports all pic12c5xx, pic14000, pic16c5x, pic16cxxx and pic17cxx devices with up to 40 pins. larger pin count devices such as the pic16c923 and pic16c924 may be supported with an adapter socket.
pic17c75x ds30264a-page 220 1997 microchip technology inc. 19.6 picdem-1 lo w-cost pic16/17 demonstration boar d the picdem-1 is a simple board which demonstrates the capabilities of several of microchips microcontrol- lers. the microcontrollers supported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the users can program the sample micro controllers provided with the picdem-1 board, on a pro mate ii or picstart-16b programmer, and easily test ?m- ware. the user can also connect the picdem-1 board to the picmaster emulator and down load the ?mware to the emulator for testing. additional pro- totype area is available for the user to build some addi- tional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simulated analog input, push-button switches and eight leds connected to portb. 19.7 picdem-2 lo w-cost pic16cxx demonstration boar d the picdem-2 is a simple demonstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcon trollers. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers provided with the picdem-2 board, on a pro mate ii pro- grammer or picstart-16c, and easily test ?mware. the picmaster emulator may also be used with the picdem-2 board to test ?mware. additional prototype area has been provided to the user for adding addi- tional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 inter- face, push-button switches, a potentiometer for simu- lated analog input, a serial eeprom to demonstrate usage of the i 2 c bus and separate headers for connec- tion to an lcd module and a keypad. 19.8 picdem-3 lo w-cost pic16cxxx demonstration boar d the picdem-3 is a simple demonstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with a lcd module. all the neces- sary hardware and software is included to run the basic demonstration programs. the user can pro- gram the sample microcontrollers provided with the picdem-3 board, on a pro mate ii program- mer or picstart plus with an adapter socket, and easily test ?mware. the picmaster emulator may also be used with the picdem-3 board to test ?m- ware. additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include an rs-232 interface, push-button switches, a potenti- ometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem-3 board is an lcd panel, with 4 commons and 12 seg- ments, that is capable of displaying time, temperature and day of the week. the picdem-3 provides an addi- tional rs-232 interface and windows 3.1 software for showing the demultiplexed lcd signals on a pc. a sim- ple serial interface allows the user to construct a hard- ware demultiplexer for the lcd signals. picdem-3 will be available in the 3rd quarter of 1996. 19.9 mplab integrated de velopment en vir onment softwar e the mplab ide software brings an ease of software development previously unseen in the 8-bit microcon- troller market. mplab is a windows based application which contains: a full featured editor three operating modes - editor - emulator - simulator a project manager customizable tool bar and key mapping a status bar with project information extensive on-line help mplab allows you to: edit your source ?es (either assembly or ?? one touch assemble (or compile) and download to pic16/17 tools (automatically updates all project information) debug using: - source ?es - absolute listing ?e transfer data dynamically via dde (soon to be replaced by ole) run up to four emulators on the same pc the ability to use mplab with microchips simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools. 19.10 assemb ler (mp asm) the mpasm universal macro assembler is a pc- hosted symbolic assembler. it supports all microcon- troller series including the pic12c5xx, pic14000, pic16c5x, pic16cxxx, and pic17cxx families. mpasm offers full featured macro capabilities, condi- tional assembly, and several source and listing formats. it generates various object code formats to support microchip's development tools as well as third party programmers.
1997 microchip technology inc. ds30264a-page 221 pic17c75x mpasm allows full symbolic debugging from picmaster, microchips universal emulator system. mpasm has the following features to assist in develop- ing software for speci? use applications. provides translation of assembler source code to object code for all microchip microcontrollers. macro assembly capability. produces all the ?es (object, listing, symbol, and special) required for symbolic debug with microchips emulator systems. supports hex (default), decimal and octal source and listing formats. mpasm provides a rich directive language to support programming of the pic16/17. directives are helpful in making the development of your assemble source code shorter and more maintainable. 19.11 s oftware sim ulator (mplab-sim) the mplab-sim software simulator allows code development in a pc host environment. it allows the user to simulate the pic16/17 series microcontrollers on an instruction level. on any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. the input/ output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. mplab-sim fully supports symbolic debugging using mplab-c and mpasm. the software simulator offers the low cost ?xibility to develop and debug code out- side of the laboratory environment making it an excel- lent multi-project software development tool. 19.12 c compiler ( mplab-c) the mplab-c code development system is a complete ? compiler and integrated development environment for microchips pic16/17 family of micro- controllers. the compiler provides powerful integration capabilities and ease of use not found with other compilers. for easier source level debugging, the compiler pro- vides symbol information that is compatible with the mplab ide memory display (picmaster emulator software versions 1.13 and later). 19.13 fuzzy logic de velopment system ( fuzzy tech-mp) fuzzy tech-mp fuzzy logic development tool is avail- able in two versions - a low cost introductory version, mp explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzy tech-mp, edition for imple- menting more complex systems. both versions include microchips fuzzy lab ? demon- stration board for hands-on experience with fuzzy logic systems implementation. 19.14 mp-drivew a y ? ?application code generator mp-driveway is an easy-to-use windows-based appli- cation code generator. with mp-driveway you can visually con?ure all the peripherals in a pic16/17 device and, with a click of the mouse, generate all the initialization and many functional code modules in c language. the output is fully compatible with micro- chips mplab-c c compiler. the code produced is highly modular and allows easy integration of your own code. mp-driveway is intelligent enough to maintain your code through subsequent code generation. 19.15 seev al a ev aluation and pr ogramming system the seeval seeprom designers kit supports all microchip 2-wire and 3-wire serial eeproms. the kit includes everything necessary to read, write, erase or program special features of any microchip seeprom product including smart serials ? and secure serials. the total endurance ? disk is included to aid in trade- off analysis and reliability calculations. the total kit can signi?antly reduce time-to-market and result in an optimized system. 19.16 t ruegaug e a intellig ent batter y mana g ement the truegauge development tool supports system development with the mta11200b truegauge intelli- gent battery management ic. system design veri?a- tion can be accomplished before hardware prototypes are built. user interface is graphically-oriented and measured data can be saved in a ?e for exporting to microsoft excel. 19.17 k ee l oq a ev aluation and pr ogramming t ools k ee l oq evaluation and programming tools support microchips hcs secure data products. the hcs eval- uation kit includes an lcd display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters.
pic17c75x ds30264a-page 222 1997 microchip technology inc. table 19-1: development tools from microchip pic12c5xx pic14000 pic16c5x pic16cxxx pic16c6x pic16c7xx pic16c8x pic16c9xx pic17c4x pic17c75x 24cxx 25cxx 93cxx hcs200 hcs300 hcs301 emulator products picmaster a / picmaster-ce in-circuit emulator 444 4 44444 available 3q97 icepic low-cost in-circuit emulator 4 44444 software tools mplab ? integrated development environment 444 4 444444 mplab ? c compiler 444 4 444444 fuzzy tech a -mp explorer/edition fuzzy logic dev. tool 444 4 44444 mp-driveway ? applications code generator 44444 4 total endurance ? software model 4 programmers picstart a lite ultra low-cost dev. kit 4444 picstart a plus low-cost universal dev. kit 444 4 444444 pro mate a ii universal programmer 444 4 44444444 keeloq a programmer 4 demo boards seeval a designers kit 4 picdem-1 44 4 4 picdem-2 44 picdem-3 4 keeloq a evaluation kit 4
1997 microchip technology inc. preliminary ds30264a-page 223 pic17c75x 20.0 pic17c752/756 electrical characteristics absolute maximum ratings ? ambient temperature under bias................................................................................................................. -55 to +125?c storage temperature .............................................................................................................................. -65?c to +150?c voltage on v dd with respect to v ss ................................................................................................................ 0 to +7.5v voltage on mclr with respect to v ss (note 2).......................................................................................... -0.3v to +14v voltage on ra2 and ra3 with respect to v ss ............................................................................................. -0.3v to +14v voltage on all other pins with respect to v ss .................................................................................... -0.3v to v dd + 0.3v total power dissipation (note 1)................................................................................................................................1.0w maximum current out of v ss pin(s) - total (@ 70?c) ............................................................................................500 ma maximum current into v dd pin(s) - total (@ 70?c) ...............................................................................................500 ma input clamp current, i ik (v i < 0 or v i > v dd ) ...................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) .............................................................................................................. 20 ma maximum output current sunk by any i/o pin (except ra2 and ra3).....................................................................35 ma maximum output current sunk by ra2 or ra3 pins ................................................................................................60 ma maximum output current sourced by any i/o pin ....................................................................................................20 ma maximum current sunk by porta and portb (combined) .................................................................................150 ma maximum current sourced by porta and portb (combined)............................................................................100 ma maximum current sunk by portc, portd and porte (combined) ..................................................................150 ma maximum current sourced by portc, portd and porte (combined).............................................................100 ma maximum current sunk by portf and portg (combined) ................................................................................150 ma maximum current sourced by portf and portg (combined) ...........................................................................100 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v ol x i ol ) note 2: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 w should be used when applying a "low" level to the mclr pin rather than pulling this pin directly to v ss . ? notice: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speci?ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic17c75x ds30264a-page 224 preliminary 1997 microchip technology inc. table 20-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) osc pic17lc752-08 pic17lc756-08 pic17c752-25 pic17c756-25 pic17c752-33 pic17c756-33 jw devices (ceramic windowed devices) rc v dd : 3.0v to 6.0v i dd ?: 6 ma max. i pd ?: 5 m a max. at 5.5v freq: 4 mhz max. v dd : 4.5v to 6.0v i dd ?: 6 ma max. i pd ?: 5 m a max. at 5.5v freq: 4 mhz max. v dd : 4.5v to 6.0v i dd ?: 6 ma max. i pd ?: 5 m a max. at 5.5v freq: 4 mhz max. v dd : 4.5v to 6.0v i dd ?: 6 ma max. i pd ?: 5 m a max. at 5.5v freq: 4 mhz max. xt v dd : 3.0v to 6.0v i dd ?: 12 ma max. i pd ?: 5 m a max. at 5.5v freq: 8 mhz max. v dd : 4.5v to 6.0v i dd ?: 38 ma max. i pd ?: 5 m a max. at 5.5v freq: 25 mhz max. v dd : 4.5v to 6.0v i dd ?: 50 ma max. i pd ?: 5 m a max. at 5.5v freq: 33 mhz max. v dd : 4.5v to 6.0v i dd ?: 50 ma max. i pd ?: 5 m a max. at 5.5v freq: 33 mhz max. ec v dd : 3.0v to 6.0v i dd ?: 12 ma max. i pd ?: 5 m a max. at 5.5v freq: 8 mhz max. v dd : 4.5v to 6.0v i dd ?: 38 ma max. i pd ?: 5 m a max. at 5.5v freq: 25 mhz max. v dd : 4.5v to 6.0v i dd ?: 50 ma max. i pd ?: 5 m a max. at 5.5v freq: 33 mhz max. v dd : 4.5v to 6.0v i dd ?: 50 ma max. i pd ?: 5 m a max. at 5.5v freq: 33 mhz max. lf v dd : 3.0v to 6.0v i dd ?: 115 m a max. at 32 khz i pd ?: 5 m a max. at 5.5v freq: 2 mhz max. v dd : 4.5v to 6.0v i dd ?: 85 m a typ. at 32 khz i pd ?: < 1 m a typ. at 5.5v freq: 2 mhz max. v dd : 4.5v to 6.0v i dd ?: 85 m a typ. at 32 khz i pd ?: < 1 m a typ. at 5.5v freq: 2 mhz max. v dd : 3.0v to 6.0v i dd ?: 115 m a max. at 32 khz i pd ?: 5 m a max. at 5.5v freq: 2 mhz max. the shaded sections indicate oscillator selections which are tested for functionality, but not for min/max speci?ations. it is recommended that the user select the device type that ensures the speci?ations required. ? the wdt, bor,and a/d circuitry are disabled.
1997 microchip technology inc. preliminary ds30264a-page 225 pic17c75x 20.1 dc characteristics: pic17c752/756-25 (commercial, industrial) pic17c752/756-33 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial param. no. sym characteristic min typ? max units conditions d001 v dd supply voltage 4.5 6.0 v d002 v dr ram data retention voltage (note 1) 1.5 * v device in sleep mode d003 v por v dd start voltage to ensure internal power-on reset signal ? ss v see section on power-on reset for details d004 s vdd v dd rise rate to ensure proper operation 0.085 * v/ms see section on power-on reset for details d005 v bor brown-out reset voltage trip point 3.6 4.3 v d006 v portp power-on reset trip point 1.8 v v dd = v portp d010 d011 d012 d013 d015 i dd supply current (note 2) tbd tbd tbd tbd tbd 6 * 12 24 * 38 50 ma ma ma ma ma f osc = 4 mhz (note 4) f osc = 8 mhz f osc = 16 mhz f osc = 25 mhz f osc = 33 mhz d021 i pd power-down current (note 3) ? 15 m av dd = 5.5v, wdt disabled module differential current d023 d i bor bor circuitry 300 500 m av dd = 4.5v, boden enabled d024 d i wdt watchdog timer 10 35 m av dd = 5.5v d026 d i ad a/d converter 1 m av dd = 5.5v, a/d not converting * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd or v ss , t0cki = v dd , mclr = v dd ; wdt disabled. current consumed from the oscillator and i/os driving external capacitive or resistive loads needs to be con- sidered. for the rc oscillator, the current through the external pull-up resistor (r) can be estimated as: v dd / (2 r). for capacitive loads, the current can be estimated (for an individual i/o pin) as (c l v dd ) f c l = total capacitive load on the i/o pin; f = average frequency the i/o pin switches. the capacitive currents are most signi?ant when the device is con?ured for external execution (includes extended microcontroller mode). 3: the power down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula i r = v dd /2rext (ma) with rext in kohm.
pic17c75x ds30264a-page 226 preliminary 1997 microchip technology inc. 20.2 dc characteristics: pic17lc752/756 (commercial, industrial) pic17lc752/756 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial param. no. sym characteristic min typ? max units conditions d001 v dd supply voltage 3.0 6.0 v d002 v dr ram data retention voltage (note 1) 1.5 * v device in sleep mode d003 v por v dd start voltage to ensure internal power-on reset signal ? ss v see section on power-on reset for details d004 s vdd v dd rise rate to ensure proper operation 0.010 * v/ms see section on power-on reset for details d005 v bor brown-out reset voltage trip point 3.6 4.3 v d006 v portp power-on reset trip point 1.8 v v dd = v portp d010 d011 d014 i dd supply current (note 2) 3 6 85 6 * 12 150 ma ma m a f osc = 4 mhz (note 4) f osc = 8 mhz f osc = 32 khz, (ec osc con?uration) d021 i pd power-down current (note 3) ? 15 m av dd = 5.5v, wdt disabled module differential current d023 d i bor bor circuitry 300 500 m av dd = 4.5v, boden enabled d024 d i wdt watchdog timer 10 35 m av dd = 5.5v d026 d i ad a/d converter 1 m av dd = 5.5v, a/d not converting * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1=external square wave, from rail to rail; all i/o pins tristated, pulled to v dd or v ss , t0cki = v dd , mclr = v dd ; wdt disabled. current consumed from the oscillator and i/os driving external capacitive or resistive loads needs to be con- sidered. for the rc oscillator, the current through the external pull-up resistor (r) can be estimated as: v dd / (2 r). for capacitive loads, the current can be estimated (for an individual i/o pin) as (c l v dd ) f c l = total capacitive load on the i/o pin; f = average frequency the i/o pin switches. the capacitive currents are most signi?ant when the device is con?ured for external execution (includes extended microcontroller mode). 3: the power down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd or v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula i r = v dd /2rext (ma) with rext in kohm.
1997 microchip technology inc. preliminary ds30264a-page 227 pic17c75x 20.3 dc characteristics: pic17c752/756-25 (commercial, industrial) pic17c752/756-33 (commercial, industrial) pic17lc752/756-08 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in section 20.1 param. no. sym characteristic min typ? max units conditions input low voltage v il i/o ports d030 with ttl buffer (note 6) v ss v ss 0.8 0.2v dd v v 4.5v v dd 5.5v 3.0v v dd 4.5v, and 5.5v v dd 6.0v d031 with schmitt trigger buffer v ss 0.2v dd v d032 mclr , osc1 (in ec and rc mode) vss 0.2v dd v note1 d033 osc1 (in xt, and lf mode) 0.5v dd ? input high voltage v ih i/o ports d040 with ttl buffer (note 6) 2.0 1 + 0.2v dd v dd v dd v v 4.5v v dd 5.5v 3.0v v dd 4.5v, and 5.5v v dd 6.0v d041 with schmitt trigger buffer 0.8v dd ? dd v d042 mclr 0.8v dd ? dd v note1 d043 osc1 (xt, and lf mode) 0.5v dd ? d050 v hys hysteresis of schmitt trigger inputs 0.15v dd * v input leakage current (notes 2, 3) d060 i il i/o ports (except ra2, ra3) 1 m a vss v pin v dd , i/o pin (in digital mode) at hi-impedance portb weak pull-ups disabled d061 mclr , test 2 m av pin = vss or v pin = v dd d062 ra2, ra3 2 m a vss v ra 2, v ra 3 12v d063 osc1 (ec, rc modes) 1 m a vss v pin v dd d063b osc1 (xt, lf modes) v pin m ar f 3 1 m w , see figure 4-2 d064 mclr , test 25 m av mclr = v pp = 12v (when not programming) d070 i purb portb weak pull-up current 60 200 400 m a v pin = v ss , rbpu = 0 4.5v v dd 6.0v * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. these parameters are for design guidance only and are not tested, nor characterized. note 1: in rc oscillator conguration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic17cxxx devices be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specied levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is dened as coming out of the pin. 4: these specications are for the programming of the on-chip program memory eprom through the use of the table write instructions. the complete programming specications can be found in: pic17c75x programming specications (literature number ds tbd). 5: the mclr /v pp pin may be kept in this range at times other than programming, but is not recommended. 6: for ttl buffers, the better of the two specications may be used.
pic17c75x ds30264a-page 228 preliminary 1997 microchip technology inc. output low voltage d080 d081 v ol i/o ports with ttl buffer 0.1v dd 0.1v dd * 0.4 v v v i ol = v dd /1.250 ma 4.5v v dd 6.0v v dd = 3.0v i ol = 6 ma, v dd = 4.5v note 6 d082 ra2 and ra3 3.0 0.4 0.6 v v v i ol = 60.0 ma, v dd = 6.0v i ol = 60.0 ma, v dd = 2.5v i ol = 60.0 ma, v dd = 4.5v d083 d084 osc2/clkout (rc and ec osc modes) 0.4 0.1v dd * v v i ol = 1 ma, v dd = 4.5v i ol = v dd /5 ma (pic17lc75x only) output high voltage (note 3) d090 d091 v oh i/o ports (except ra2 and ra3) with ttl buffer 0.9v dd 0.9v dd * 2.4 v v v i oh = -v dd /2.500 ma 4.5v v dd 6.0v v dd = 3.0v i oh = -6.0 ma, v dd = 4.5v note 6 d093 d094 osc2/clkout (rc and ec osc modes) 2.4 0.9v dd * v v i oh = -5 ma, v dd = 4.5v i oh = -v dd /5 ma (pic17lc75x only) d150 v od open drain high voltage 12 v ra2 and ra3 pins only pulled-up to externally applied voltage capacitive loading specs on output pins d100 c osc2 osc2/clkout pin 25 pf in ec or rc osc modes when osc2 pin is outputting clkout. external clock is used to drive osc1. d101 c io all i/o pins and osc2 (in rc mode) 50 pf d102 c ad system interface bus (portc, portd and porte) 50 pf in microprocessor or extended microcontroller mode dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in section 20.1 param. no. sym characteristic min typ? max units conditions * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. these parameters are for design guidance only and are not tested, nor characterized. note 1: in rc oscillator conguration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic17cxxx devices be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specied levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is dened as coming out of the pin. 4: these specications are for the programming of the on-chip program memory eprom through the use of the table write instructions. the complete programming specications can be found in: pic17c75x programming specications (literature number ds tbd). 5: the mclr /v pp pin may be kept in this range at times other than programming, but is not recommended. 6: for ttl buffers, the better of the two specications may be used.
1997 microchip technology inc. preliminary ds30264a-page 229 pic17c75x dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +40?c operating voltage v dd range as described in section 20.1 param. no. sym characteristic min typ? max units conditions internal program memory programming specs (note 4) d110 d111 d112 d113 d114 v pp v ddp i pp i ddp t prog voltage on mclr /v pp pin supply voltage during programming current into mclr /v pp pin supply current during programming programming pulse width 12.75 4.75 100 5.0 25 13.25 5.25 50 30 1000 v v ma ma m s note 5 terminated via inter- nal/external interrupt or a reset * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. these parameters are for design guidance only and are not tested, nor characterized. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic17cxx devices be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is de?ed as coming out of the pin. 4: these speci?ations are for the programming of the on-chip program memory eprom through the use of the table write instructions. the complete programming speci?ations can be found in: pic17cxx programming speci?ations (literature number ds30139). 5: the mclr /v pp pin may be kept in this range at times other than programming, but is not recommended. 6: for ttl buffers, the better of the two speci?ations may be used. note 1: when using the table write for internal programming, the device temperature must be less than 40?c. note 2: for in-circuit serial programming (isp), refer to the device programming speci?ation.
pic17c75x ds30264a-page 230 preliminary 1997 microchip technology inc. 20.4 t iming para meter symbology the timing parameter symbols have been created following one of the following formats: 1. tpps2pps 3. t cc : st (i 2 c speci?ations only) 2. tpps 4. ts (i 2 c speci?ations only) t f frequency t time lowercase symbols (pp) and their meanings: pp ad address/data ost oscillator start-up timer al ale pwrt power-up timer cc capture1 and capture2 rb portb ck clkout or clock rd rd dt data in rw rd or wr in int pin t0 t0cki io i/o port t123 tclk12 and tclk3 mc mclr wdt watchdog timer oe oe wr wr os osc1 uppercase symbols and their meanings: s d driven l low e edge p period f fall r rise h high v valid i invalid (hi-impedance) z hi-impedance
1997 microchip technology inc. preliminary ds30264a-page 231 pic17c75x figure 20-1: parameter measurement information all timings are measure between high and low measurement points as indicated in the ?ures below. 0.9 v dd 0.1 v dd rise time fall time v oh = 0.7v dd v dd /2 v ol = 0.3v dd data out valid data out invalid output hi-impedance output driven 0.25v 0.25v 0.25v 0.25v output level conditions portc, d, e, f, and g pins all other input pins v ih = 2.4v v il = 0.4v data in valid data in invalid v ih = 0.9v dd v il = 0.1v dd data in valid data in invalid input level conditions load conditions load condition 1 pin c l v ss 50 pf c l
pic17c75x ds30264a-page 232 preliminary 1997 microchip technology inc. 20.5 t iming diagrams and speci cations figure 20-2: external clock timing table 20-2: external clock timing requirements param. no. sym characteristic min typ? max units conditions fosc external clkin frequency (note 1) dc dc dc 8 25 33 mhz mhz mhz ec osc mode - 08 devices (8 mhz devices) - 25 devices (25 mhz devices) - 33 devices (33 mhz devices) oscillator frequency (note 1) dc 1 1 1 dc 4 8 25 33 2 mhz mhz mhz mhz mhz rc osc mode xt osc mode - 08 devices (8 mhz devices) - 25 devices (25 mhz devices) - 33 devices (33 mhz devices) lf osc mode 1 tosc external clkin period (note 1) 125 40 30.3 ns ns ns ec osc mode - 08 devices (8 mhz devices) - 25 devices (25 mhz devices) - 33 devices (33 mhz devices) oscillator period (note 1) 250 125 40 30.3 500 1,000 1,000 1,000 ns ns ns ns ns rc osc mode xt osc mode - 08 devices (8 mhz devices) - 25 devices (25 mhz devices) - 33 devices (33 mhz devices) lf osc mode 2t cy instruction cycle time (note 1) 121.2 4/fosc dc ns 3 tosl, tosh clock in (osc1) high or low time 10 ns ec oscillator 4 tosr, tosf clock in (osc1) rise or fall time 5 ns ec oscillator ? data in ?yp column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. these parameters are for design guidance only and are not tested, nor characterized. note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period. all speci?d values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these speci?d limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. all devices are tested to operate at ?in. values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the ?ax. cycle time limit is ?c (no clock) for all devices. osc1 osc2 ? q4 q1 q2 q3 q4 q1 1 3 3 4 4 2 ? in ec and rc modes only.
1997 microchip technology inc. preliminary ds30264a-page 233 pic17c75x figure 20-3: clkout and i/o timing table 20-3: clkout and i/o timing requirements param. no. sym characteristic min typ? max units conditions 10 tosl2ckl osc1 to clkout 15 30 ns note 1 11 tosl2ckh osc1 to clkout - 15 30 ns note 1 12 tckr clkout rise time 5 15 ns note 1 13 tckf clkout fall time 5 15 ns note 1 14 tckh2iov clkout - to port out valid pic17 c xxx 0.5t cy + 20 ns note 1 pic17 lc xxx 0.5t cy + 50 ns note 1 15 tiov2ckh port in valid before clkout - pic17 c xxx 0.25t cy + 25 ns note 1 pic17 lc xxx 0.25t cy + 50 ns note 1 16 tckh2ioi port in hold after clkout - 0 ns note 1 17 tosl2iov osc1 (q1 cycle) to port out valid 100 ns 18 tosl2ioi osc1 (q2 cycle) to port input invalid (i/o in hold time) 0 ns 19 tiov2osl port input valid to osc1 (i/o in setup time) 30 ns 20 tior port output rise time 10 35 ns 21 tiof port output fall time 10 35 ns 22 tinhl int pin high or low time 25 * ns 23 trbhl rb7:rb0 change int high or low time 25 * ns * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. these parameters are for design guidance only and are not tested, nor characterized. note 1: measurements are taken in ec mode where clkout output is 4 x t osc . osc1 osc2 ? i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 22 23 19 18 15 11 12 16 old value new value ? in ec and rc modes only.
pic17c75x ds30264a-page 234 preliminary 1997 microchip technology inc. figure 20-4: reset, watchdog timer, oscillator start-up timer, power-up timer, and brown-out reset timing table 20-4: reset, watchdog timer, oscillator start-up timer, power-up timer, and brown-out reset requirements param. no. sym characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 100 * ns v dd = 5v 31 t wdt watchdog timer time-out period (prescale = 1) 5 * 12 25 * ms v dd = 5v 32 t ost oscillation start-up timer period 1024t osc ms t osc = osc1 period 33 t pwrt power-up timer period 40 * 96 200 * ms v dd = 5v 34 t ioz mclr to i/o hi-impedance 100 ns depends on pin load 35 tmcl2adi mclr to system inter- face bus (ad15:ad0>) invalid pic17 c xxx 100 * ns pic17 lc xxx 120 * ns 36 t bor brown-out reset pulse width (low) 100 * ns 3.8v v dd 4.2v * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. these parameters are for design guidance only and are not tested, nor characterized. this speci?ation ensured by design. v dd mclr internal por / bor pwrt timeout osc timeout internal reset watchdog timer reset 33 32 30 31 address / data 35
1997 microchip technology inc. preliminary ds30264a-page 235 pic17c75x figure 20-5: timer0 external clock timings table 20-5: timer0 external clock requirements figure 20-6: timer1, timer2, and timer3 external clock timings table 20-6: timer1, timer2, and timer3 external clock requirements param. no. sym characteristic min typ? max units conditions 40 tt0h t0cki high pulse width no prescaler 0.5t cy + 20 ns with prescaler 10* ns 41 tt0l t0cki low pulse width no prescaler 0.5t cy + 20 ns with prescaler 10* ns 42 tt0p t0cki period greater of: 20 ns or tcy + 40 n ns n = prescale value (1, 2, 4, ..., 256) * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. this speci?ation ensured by design. param. no. sym characteristic min typ ? max units conditions 45 tt123h tclk12 and tclk3 high time 0.5t cy + 20 ns 46 tt123l tclk12 and tclk3 low time 0.5t cy + 20 ns 47 tt123p tclk12 and tclk3 input period t cy + 40 n ns n = prescale value (1, 2, 4, 8) 48 tcke2tmri delay from selected external clock edge to timer increment 2t osc 6tosc * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. this speci?ation ensured by design. ra1/t0cki 40 41 42 tclk12 45 46 or tclk3 tmrx 48 48 47
pic17c75x ds30264a-page 236 preliminary 1997 microchip technology inc. figure 20-7: capture timings table 20-7: capture requirements figure 20-8: pwm timings table 20-8: pwm requirements param. no. sym characteristic min typ? max units conditions 50 tccl capture pin input low time 10 * ns 51 tcch capture pin input high time 10 * ns 52 tccp capture pin input period 2t cy n ns n = prescale value (4 or 16) * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. this speci?ation ensured by design. param. no. sym characteristic min typ? max units conditions 53 tccr pwm pin output rise time 10 * 35 * ns 54 tccf pwm pin output fall time 10 * 35 * ns * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. this speci?ation ensured by design. cap pin (capture mode) 50 51 52 pwm pin (pwm mode) 53 54
1997 microchip technology inc. preliminary ds30264a-page 237 pic17c75x figure 20-9: spi master mode timing (cke = 0) table 20-9: spi mode requirements (master mode, cke = 0) param. no. sym characteristic min typ? max units conditions 70 tssl2sch, tssl2scl ss to sck or sck - input t cy *ns 71 tsch sck input high time (slave mode) t cy + 20 * ns 72 tscl sck input low time (slave mode) t cy + 20 * ns 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 * ns 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 * ns 75 tdor sdo data output rise time 10 25 * ns 76 tdof sdo data output fall time 10 25 * ns 78 tscr sck output rise time (master mode) 10 25 * ns 79 tscf sck output fall time (master mode) 10 25 * ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge 50 * ns * characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are no tested. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 78 79 80 79 78 msb lsb bit6 - - - - - -1 msb in lsb in bit6 - - - -1 refer to figure 20-1 for load conditions.
pic17c75x ds30264a-page 238 preliminary 1997 microchip technology inc. figure 20-10: spi master mode timing (cke = 1) table 20-10: spi mode requirements (master mode, cke = 1) param. no. sym characteristic min typ? max units conditions 71 tsch sck input high time (slave mode) t cy + 20 * ns 72 tscl sck input low time (slave mode) t cy + 20 * ns 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 * ns 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 * ns 75 tdor sdo data output rise time 10 25 * ns 76 tdof sdo data output fall time 10 25 * ns 78 tscr sck output rise time (master mode) 10 25 * ns 79 tscf sck output fall time (master mode) 10 25 * ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge 50 * ns 81 tdov2sch, tdov2scl sdo data output setup to sck edge t cy *ns * characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 81 71 72 74 75, 76 78 80 msb 79 73 msb in bit6 - - - - - -1 lsb in bit6 - - - -1 lsb refer to figure 20-1 for load conditions.
1997 microchip technology inc. preliminary ds30264a-page 239 pic17c75x figure 20-11: spi slave mode timing (cke = 0) table 20-11: spi mode requirements (slave mode timing (cke = 0) param. no. sym characteristic min typ? max units conditions 70 tssl2sch, tssl2scl ss to sck or sck - input t cy *ns 71 tsch sck input high time (slave mode) t cy + 20 * ns 72 tscl sck input low time (slave mode) t cy + 20 * ns 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 * ns 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 * ns 75 tdor sdo data output rise time 10 25 * ns 76 tdof sdo data output fall time 10 25 * ns 77 tssh2doz ss - to sdo output hi-impedance 10 * 50 * ns 78 tscr sck output rise time (master mode) 10 25 * ns 79 tscf sck output fall time (master mode) 10 25 * ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge 50 * ns 83 tsch2ssh, tscl2ssh ss - after sck edge 1.5t cy + 40 * ns * characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78 sdi msb lsb bit6 - - - - - -1 msb in bit6 - - - -1 lsb in 83 refer to figure 20-1 for load conditions.
pic17c75x ds30264a-page 240 preliminary 1997 microchip technology inc. figure 20-12: spi slave mode timing (cke = 1) table 20-12: spi mode requirements (slave mode, cke = 1) param. no. sym characteristic min typ? max units conditions 70 tssl2sch, tssl2scl ss to sck or sck - input t cy *ns 71 tsch sck input high time (slave mode) t cy + 20 * ns 72 tscl sck input low time (slave mode) t cy + 20 * ns 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 * ns 75 tdor sdo data output rise time 10 25 * ns 76 tdof sdo data output fall time 10 25 * ns 77 tssh2doz ss - to sdo output hi-impedance 10 * 50 * ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge 50 * ns 82 tssl2dov sdo data output valid after ss edge 50 * ns 83 tsch2ssh, tscl2ssh ss - after sck edge 1.5t cy + 40 * ns * characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 82 sdi 74 75, 76 msb bit6 - - - - - -1 lsb 77 msb in bit6 - - - -1 lsb in 80 83 refer to figure 20-1 for load conditions.
1997 microchip technology inc. preliminary ds30264a-page 241 pic17c75x figure 20-13: i 2 c bus start/stop bits timing table 20-13: i 2 c bus start/stop bits requirements param. no. sym characteristic min typ max units conditions 90 t su : sta start condition 100 khz mode 2(t osc )(brg + 1) ns only relevant for repeated start condi- tion setup time 400 khz mode 2(t osc )(brg + 1) 1 mhz mode (1) 2(t osc )(brg + 1) 91 t hd : sta start condition 100 khz mode 2(t osc )(brg + 1) ns after this period the ?st clock pulse is generated hold time 400 khz mode 2(t osc )(brg + 1) 1 mhz mode (1) 2(t osc )(brg + 1) 92 t su : sto stop condition 100 khz mode 2(t osc )(brg + 1) ns setup time 400 khz mode 2(t osc )(brg + 1) 1 mhz mode (1) 2(t osc )(brg + 1) 93 t hd : sto stop condition 100 khz mode 2(t osc )(brg + 1) ns hold time 400 khz mode 2(t osc )(brg + 1) 1 mhz mode (1) 2(t osc )(brg + 1) this speci?ation ensured by design. for the value required by the i 2 c speci?ation, please refer to figure e-11. note 1: maximum pin capacitance = 10 pf for all i 2 c pins. note: refer to figure 20-1 for load conditions 91 93 scl sda start condition stop condition 90 92
pic17c75x ds30264a-page 242 preliminary 1997 microchip technology inc. figure 20-14: i 2 c bus data timing note: refer to figure 20-1 for load conditions 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
1997 microchip technology inc. preliminary ds30264a-page 243 pic17c75x table 20-14: i 2 c bus data requirements param. no. sym characteristic min max units conditions 100 t high clock high time 100 khz mode 2(t osc )(brg + 1) m s 400 khz mode 2(t osc )(brg + 1) m s 1 mhz mode (1) 2(t osc )(brg + 1) m s 101 t low clock low time 100 khz mode 2(t osc )(brg + 1) m s 400 khz mode 2(t osc )(brg + 1) m s 1 mhz mode (1) 2(t osc )(brg + 1) m s 102 t r sda and scl rise time 100 khz mode 1000 * ns cb is speci?d to be from 10 to 400 pf 400 khz mode 20 + 0.1cb * 300 * ns 1 mhz mode (1) 300 * ns 103 t f sda and scl fall time 100 khz mode 300 * ns cb is speci?d to be from 10 to 400 pf 400 khz mode 20 + 0.1cb * 300 * ns 1 mhz mode (1) 100 * ns 90 t su : sta start condition setup time 100 khz mode 2(t osc )(brg + 1) m s only relevant for repeated start condition 400 khz mode 2(t osc )(brg + 1) m s 1 mhz mode (1) 2(t osc )(brg + 1) m s 91 t hd : sta start condition hold time 100 khz mode 2(t osc )(brg + 1) m s after this period the ?st clock pulse is generated 400 khz mode 2(t osc )(brg + 1) m s 1 mhz mode (1) 2(t osc )(brg + 1) m s 106 t hd : dat data input hold time 100 khz mode 0 ns 400 khz mode 0 0.9 * m s 1 mhz mode (1) tbd * ns 107 t su : dat data input setup time 100 khz mode 250 * ns note 2 400 khz mode 100 * ns 1 mhz mode (1) tbd * ns 92 t su : sto stop condition setup time 100 khz mode 2(t osc )(brg + 1) m s 400 khz mode 2(t osc )(brg + 1) m s 1 mhz mode (1) 2(t osc )(brg + 1) m s 109 t aa output valid from clock 100 khz mode 3500 * ns 400 khz mode 1000 * ns 1 mhz mode (1) ns 110 t buf bus free time 100 khz mode 4.7 m s time the bus must be free before a new transmission can start 400 khz mode 1.3 m s 1 mhz mode (1) tbd * m s d102 cb bus capacitive loading 400 * pf * characterized but not tested. this speci?ation ensured by design. for the value required by the i 2 c speci?ation, please refer to figure e-11. these parameters are for design guidance only and are not tested, nor characterized. note 1: maximum pin capacitance = 10 pf for all i 2 c pins. 2: a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the parameter # 107 3 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line. parameter # 102.+ # 107 = 1000 + 250 = 1250 ns (for 100 khz-mode) before the scl line is released.
pic17c75x ds30264a-page 244 preliminary 1997 microchip technology inc. figure 20-15: usart synchronous transmission (master/slave) timing table 20-15: usart synchronous transmission requirements figure 20-16: usart synchronous receive (master/slave) timing table 20-16: usart synchronous receive requirements param. no. sym characteristic min typ? max units conditions 120 tckh2dtv sync xmit (master & sla ve) clock high to data out valid pic17 c xxx 50 ns pic17 lc xxx 75 * ns 121 tckrf clock out rise time and fall time (master mode) pic17 c xxx 25 ns pic17 lc xxx 40 * ns 122 tdtrf data out rise time and fall time pic17 c xxx 25 ns pic17 lc xxx 40 * ns ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. parameter no. sym characteristic min typ? max units conditions 125 tdtv2ckl sync rcv (master & sla ve) data hold before ck (dt hold time) 15 ns 126 tckl2dtl data hold after ck (dt hold time) 15 ns ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. 121 121 120 122 tx/ck rx/dt pin pin 125 126 tx/ck rx/dt pin pin
1997 microchip technology inc. preliminary ds30264a-page 245 pic17c75x table 20-17: a/d converter characteristics: pic17lc752/756-08 (commercial, industrial) pic17c752/756-25 (commercial, industrial) pic17c752/756-33 (commercial, industrial) param. no. sym characteristic min typ? max units conditions a01 n r resolution 10 bit v ref = v dd = 5.12v, v ss v ain v ref a02 e abs absolute error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a03 e il integral linearity error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a04 e dl differential linearity error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a05 e fs full scale error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a06 e off offset error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a10 monotonicity guaranteed v ss v ain v ref a20 v ref reference voltage (v refh - v refl ) 0v v a21 v refh reference voltage high v ss + 3.0v ?v dd + 0.3v v a22 v refl reference voltage low av ss - 0.3v ?v dd - 3.0v v a25 v ain analog input voltage v ss - 0.3v ? ref + 0.3v v a30 z ain recommended impedance of analog voltage source 10.0 k w a40 i ad a/d conversion current (v dd ) 17 c xxx 180 m a average current consumption when a/d is on. (note 1) 17 lc xxx 90 m a a50 i ref v ref input current (note 2) 10 1000 10 m a m a during v ain acquisition. based on differential of v hold to v ain . to charge c hold see section 16.1. during a/d conversion cycle * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. 2: v ref current is from rg0 and rg1 pins or av dd and av ss pins, whichever is selected as reference input.
pic17c75x ds30264a-page 246 preliminary 1997 microchip technology inc. figure 20-17: a/d conversion timing table 20-18: a/d conversion requirements param. no. sym characteristic min typ? max units conditions 130 t ad a/d clock period pic17cxxx 1.6 m s t osc based, v ref 3 3.0v pic17lcxxx 3.0 m st osc based, v ref full range pic17cxxx 2.0 * 4.0 6.0 * m s a/d rc mode pic17lcxxx 3.0 * 6.0 9.0 * m s a/d rc mode 131 t cnv conversion time (not including acquisition time) (note 1) 12 13 t ad 132 t acq acquisition time (note 2) 10 * 40 m s m s the minimum time is the ampli?r settling time. this may be used if the ?ew input voltage has not changed by more than 1lsb (i.e. 5mv @ 5.12v) from the last sampled voltage (as stated on c hold ). 134 t go q4 to adclk start tosc/2 if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be exe- cuted. * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. this speci?ation ensured by design. note 1: adres register may be read on the following t cy cycle. 2: see section 16.1 for minimum conditions when input voltage has changed more then 1 lsb. 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (t osc /2) (1) 987 210 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1 t cy . . . . . .
1997 microchip technology inc. preliminary ds30264a-page 247 pic17c75x figure 20-18: memory interface write timing table 20-19: memory interface write requirements param. no. sym characteristic min typ? max units conditions 150 tadv2all ad<15:0> (address) valid to pic17 c xxx 0.25tcy - 10 ns ale (address setup time) pic17 lc xxx tbd 151 tall2adi ale to address out invalid pic17 c xxx 0 ns (address hold time) pic17 lc xxx tbd 152 tadv2wrl data out valid to wr pic17 c xxx 0.25tcy - 40 ns (data setup time) pic17 lc xxx tbd 153 twrh2adi wr - to data out invalid pic17 c xxx 0.25t cy ns (data hold time) pic17 lc xxx tbd 154 twrl wr pulse width pic17 c xxx 0.25t cy ns pic17 lc xxx tbd * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. this speci?ation ensured by design. osc1 ale oe wr ad<15:0> q1 q2 q3 q4 q1 q2 150 151 152 153 154 addr out data out addr out
pic17c75x ds30264a-page 248 preliminary 1997 microchip technology inc. figure 20-19: memory interface read timing table 20-20: memory interface read requirements param. no. sym characteristic min typ? max units conditions 150 tadv2all ad15:ad0 (address) valid to pic17 c xxx 0.25tcy - 10 ns ale (address setup time) pic17 lc xxx tbd 151 tall2adi ale to address out invalid pic17 c xxx 5* ns (address hold time) pic17 lc xxx tbd 160 tadz2oel ad15:ad0 hi-impedance to pic17 c xxx 0* ns oe pic17 lc xxx tbd 161 toeh2add oe - to ad15:ad0 driven pic17 c xxx 0.25tcy - 15 ns pic17 lc xxx tbd 162 tadv2oeh data in valid before oe - pic17 c xxx 35 ns (data setup time) pic17 lc xxx tbd 163 toeh2adi oe - to data in invalid pic17 c xxx 0 ns (data hold time) pic17 lc xxx tbd 164 talh ale pulse width pic17 c xxx 0.25t cy ns pic17 lc xxx tbd 165 toel oe pulse width pic17 c xxx 0.5tcy - 35 ns pic17 lc xxx tbd 166 talh2alh ale - to ale - (cycle time) pic17 c xxx t cy ns pic17 lc xxx tbd 167 tacc address access time pic17 c xxx 0.75t cy - 30 ns pic17 lc xxx tbd 168 toe output enable access time pic17 c xxx 0.5t cy - 45 ns (oe low to data valid) pic17 lc xxx tbd * these parameters are characterized but not tested. ? data in ?yp column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. this speci?ation ensured by design. osc1 ale oe ad<15:0> wr q1 q2 q3 data in addr out 150 151 160 166 165 162 163 161 '1' '1' q4 q1 q2 addr out 164 168 167
1997 microchip technology inc. preliminary ds30264a-page 249 pic17c75x 21.0 pic17c752/756 dc and ac characteristics the graphs and tables provided in this section are for design guidance and are not tested nor guaranteed. in some graphs or tables the data presented is outside speci?d operating range (e.g. outside speci?d v dd range). this is for information only and devices are ensured to operate properly only within the speci?d range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time. "typical" represents the mean of the distribution while "max" or "min" represents (mean + 3 s ) and (mean - 3 s ) respectively where s is standard deviation. table 21-1: pin capacitance per package type figure 21-1: typical rc oscillator frequency vs. temperature pin name typical capacitance (pf) 64-pin dip 68-pin plcc 64-pin tqfp all pins, except mclr , v dd , and v ss 10 10 10 mclr pin 20 20 20 f osc f osc (25 c) 1.10 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0.90 010 20253040506070 t( c) frequency normalized to +25 c v dd = 5.5v v dd = 3.5v rext 3 10 k w cext = 100 pf
pic17c75x ds30264a-page 250 preliminary 1997 microchip technology inc. figure 21-2: typical rc oscillator frequency vs. v dd figure 21-3: typical rc oscillator frequency vs. v dd 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 4.0 4.5 5.0 5.5 6.0 6.5 f osc (mhz) v dd (volts) r = 10k cext = 22 pf, t = 25 c r = 100k 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 4.0 4.5 5.0 5.5 6.0 6.5 f osc (mhz) v dd (volts) r = 10k cext = 100 pf, t = 25 c r = 100k r = 3.3k r = 5.1k
1997 microchip technology inc. preliminary ds30264a-page 251 pic17c75x figure 21-4: typical rc oscillator frequency vs. v dd table 21-2: rc oscillator frequencies cext rext average fosc @ 5v, 25 c 22 pf 10k 3.33 mhz 12% 100k 353 khz 13% 100 pf 3.3k 3.54 mhz 10% 5.1k 2.43 mhz 14% 10k 1.30 mhz 17% 100k 129 khz 10% 300 pf 3.3k 1.54 mhz 14% 5.1k 980 khz 12% 10k 564 khz 16% 160k 35 khz 18% 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 4.0 4.5 5.0 5.5 6.0 6.5 f osc (mhz) v dd (volts) r = 10k cext = 300 pf, t = 25 c r = 160k r = 3.3k r = 5.1k 0.2 0.0
pic17c75x ds30264a-page 252 preliminary 1997 microchip technology inc. figure 21-5: transconductance (gm) of lf oscillator vs. v dd figure 21-6: transconductance (gm) of xt oscillator vs. v dd 500 450 400 350 300 250 200 150 100 2.5 3.0 3.5 4.0 4.5 5.0 gm( m a/v) v dd (volts) min @ 85 c 50 0 5.5 6.0 max @ -40 c typ @ 25 c 20 18 16 14 12 10 8 6 4 2.5 3.0 3.5 4.0 4.5 5.0 gm(ma/v) v dd (volts) min @ 85 c 2 0 5.5 6.0 max @ -40 c typ @ 25 c
1997 microchip technology inc. preliminary ds30264a-page 253 pic17c75x figure 21-7: typical i dd vs. frequency (external clock 25 c) figure 21-8: maximum i dd vs. frequency (external clock 125 c to -40 c) 10k 100k 1m 10m 100m 100 1000 10000 100000 i dd ( m a) external clock frequency (hz) 7.0v 10 6.5v 6.0v 5.5v 4.5v 5.0v 4.0v 10k 100k 1m 10m 100m 100 1000 10000 100000 i dd ( m a) external clock frequency (hz) 6.5v 6.0v 5.5v 4.0v 4.5v 5.0v 7.0v
pic17c75x ds30264a-page 254 preliminary 1997 microchip technology inc. figure 21-9: typical i pd vs. v dd watchdog disabled 25 c figure 21-10: maximum i pd vs. v dd watchdog disabled 12 10 8 6 4 4.0 4.5 5.0 5.5 6.0 i pd (na) v dd (volts) 2 0 6.5 7.0 600 500 400 300 200 4.0 4.5 5.0 5.5 6.0 i pd (na) v dd (volts) 100 0 6.5 7.0 1300 1200 1100 1000 900 800 700 1900 1800 1700 1600 1500 1400 temp. = 85 c temp. = 70 c temp. = 0 c temp. = -40 c
1997 microchip technology inc. preliminary ds30264a-page 255 pic17c75x figure 21-11: typical i pd vs. v dd watchdog enabled 25 c figure 21-12: maximum i pd vs. v dd watchdog enabled 30 25 20 15 10 4.0 4.5 5.0 5.5 6.0 i pd ( m a) v dd (volts) 5 0 6.5 7.0 60 50 40 30 20 4.0 4.5 5.0 5.5 6.0 i pd ( m a) v dd (volts) 10 0 6.5 7.0 -40 c 0 c 70 c 85 c
pic17c75x ds30264a-page 256 preliminary 1997 microchip technology inc. figure 21-13: wdt timer time-out period vs. v dd figure 21-14: i oh vs. v oh , v dd = 3v 30 25 20 15 10 4.0 4.5 5.0 5.5 6.0 v dd (volts) 5 0 6.5 7.0 wdt period (ms) max. 70 c typ. 25 c min. 0 c min. -40 c max. 85 c 0 -2 -4 -6 -8 -10 -12 -14 0.0 0.5 1.0 1.5 2.0 2.5 i oh (ma) v oh (volts) min @ 85 c -16 -18 3.0 max @ -40 c typ @ 25 c
1997 microchip technology inc. preliminary ds30264a-page 257 pic17c75x figure 21-15: i oh vs. v oh , v dd = 5v figure 21-16: i ol vs. v ol , v dd = 3v 0 -5 -10 -15 -20 -25 0.0 0.5 1.0 1.5 2.0 2.5 i oh (ma) v oh (volts) -30 -35 3.0 max @ -40 c typ @ 25 c 3.5 4.0 4.5 5.0 min @ 85 c 30 25 20 15 10 0.0 0.5 1.0 1.5 2.0 v ol (volts) 5 0 2.5 3.0 i ol (ma) min. +85 c typ. 25 c max. -40 c
pic17c75x ds30264a-page 258 preliminary 1997 microchip technology inc. figure 21-17: i ol vs. v ol , v dd = 5v figure 21-18: v th (input threshold voltage) of i/o pins (ttl) vs . v dd 90 80 70 60 50 40 30 20 0.0 0.5 1.0 1.5 2.0 2.5 i ol (ma) v ol (volts) min @ +85 c 10 0 3.0 max @ -40 c typ @ 25 c 2.5 v th (volts) v dd (volts) 0.6 max (-40 c to +85 c) typ @ 25 c 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.8 1.0 1.2 1.4 1.6 1.8 2.0 min (-40 c to +85 c)
1997 microchip technology inc. preliminary ds30264a-page 259 pic17c75x figure 21-19: v ih , v il of i/o pins (schmitt trigger) vs . v dd figure 21-20: v th (input threshold voltage) of osc1 input (in xt and lf modes) vs. v dd 2.0 v ih , v il (volts) v dd (volts) 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 6.0 4.0 4.5 5.0 v ih , max (-40 c to +85 c) v ih , typ (25 c) v ih , min (-40 c to +85 c) v il , max (-40 c to +85 c) v il , typ (25 c) v il , min (-40 c to +85 c) v th ,(volts) v dd (volts) 1.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.2 1.4 1.6 1.8 2.0 2.2 2.4 6.0 2.6 2.8 3.0 min (-40 c to +85 c) 3.2 3.4 max (-40 c to +85 c) typ (25 c)
pic17c75x ds30264a-page 260 preliminary 1997 microchip technology inc. notes:
1997 microchip technology inc. ds30264a-page 261 pic17c75x 22.0 packaging information 22.1 64-lead plastic surface mount (tqfp 10x10x1 mm bod y 1.0/0.10 mm lead form) package group: plastic tqfp symbol millimeters inches min nominal max min nominal max a 0 -7 0 7 a - - 1.20 a1 0.05 0.10 0.15 a2 0.95 1.00 1.05 b 0.17 0.22 0.27 b1 0.17 0.20 0.23 d - 12.00 - d1 - 10.00 - e - 12.00 - e1 - 10.00 - e - 0.50 - l 0.45 0.60 0.75 n - 64 - 64 d d/2 e e/2 e 8 places 11/13 a see detail b 0.09/0.20 b1 b 0.09/0.16 base metal with lead finish a2 a1 0.08 r min. 0.20 min. 1.00 ref. l 0-7 datum plane gauge plane 0.25 0 min. det ail b a e/2 a see detail a det ail a e1 d1
pic17c75x ds30264a-page 262 1997 microchip technology inc. 22.2 64-lead plastic dual in-line (750 mil) package group: plastic dual in-line (pla) symbol millimeters inches min max notes min max notes a 0 15 0 15 a 5.08 0.200 a1 0.51 0.020 a2 3.38 4.27 0.133 0.168 b 0.38 0.56 0.015 0.022 b1 .076 1.27 typical 0.030 0.050 typical c 0.20 0.30 typical 0.008 0.012 typical d 57.40 57.91 2.260 2.280 d1 55.12 55.12 reference 2.170 2.170 reference e 19.05 19.69 0.750 0.775 e1 16.76 17.27 0.660 0.680 e1 1.73 1.83 typical 0.068 0.072 typical ea 19.05 19.05 reference 0.750 0.750 reference eb 19.05 21.08 0.750 0.830 l 3.05 3.43 0.120 0.135 n 6464 6464 s 1.19 0.047 s1 0.686 0.027 n pin no. 1 e1 e s d b1 b base plane seating plane s1 a1 a2 a l e1 a c e a d1 e b indicator area
1997 microchip technology inc. ds30264a-page 263 pic17c75x 22.3 68-lead plastic leaded chip carrier (square) package group: plastic leaded chip carrier (plcc) symbol millimeters inches min max notes min max notes a 4.191 4.699 0.165 0.185 a1 2.286 2.794 0.090 0.110 d 25.019 25.273 0.985 0.995 d1 24.130 24.334 0.950 0.958 d2 22.860 23.622 0.900 0.930 d3 20.320 - reference 0.800 - reference e 25.019 25.273 0.985 0.995 e1 24.130 24.334 0.950 0.958 e2 22.860 23.622 0.900 0.930 e3 20.320 - reference 0.800 - reference n 68 - 68 - cp - 0.102 - 0.004 lt 0.203 0.254 0.008 0.010 s 0.177 .007 b d-e -a- 0.254 d 1 d 3 3 3 -c- -f- -d- 4 9 8 -b- -e- s 0.177 .007 a f-g s s e e 1 -h- -g- 6 2 3 .010 max 1.524 .060 10 2 11 0.508 .020 1.651 .065 r 1.14/0.64 .045/.025 r 1.14/0.64 .045/.025 1.651 .065 0.508 .020 -h- 11 0.254 .010 max 6 min 0.812/0.661 .032/.026 3 -c- 0.64 .025 min 5 0.533/0.331 .021/.013 0.177 .007 m a f-g s , d-e s 1.27 .050 2 sides a s 0.177 .007 b a s d 3 /e 3 d 2 0.101 .004 0.812/0.661 .032/.026 s 0.38 .015 f-g 4 s 0.38 .015 f-g e 2 d -h- a 1 seating plane 2 sides n pics
pic17c75x ds30264a-page 264 1997 microchip technology inc. 22.4 p ac ka g e marking inf ormation legend: mm...m xx...x aa bb c d 1 e microchip part number information customer speci? information* year code (last 2 digits of calender year) week code (week of january 1 is week '01? facility code of the plant at which wafer is manufactured. c = chandler, arizona, u.s.a. mask revision number for microcontroller assembly code of the plant or country of origin in which part was assembled. in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer speci? information. note : standard otp marking consists of microchip part number, year code, week code, facility code, mask revision number, and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales of?e. for qtp devices, any special marking adders are included in qtp price. * 68-lead plcc mmmmmmmmmm mmmmmmm aabbcde example s = tempe, arizona, u.s.a. 64-lead tqfp mmmmmmm aabbcde mmmmmmmmmm example 9717cae 68-lead cerquad windowed example aabbcde 64-lead sdip (shrink dip) mmmmmmmmmmmmmmmmm example pic17c756 -08/l 9748cae mmmmmmmmmmmmmmmmm aabbcde pic17c756-04/cl 9750cae -08i/pt pic17c752 9736cae pic17c752-04i/sp
1997 microchip technology inc. preliminary ds30264a-page 265 pic17c75x appendix a: modifications the following is the list of modi?ations over the pic16cxx microcontroller family: 1. instruction word length is increased to 16-bit. this allows larger page sizes both in program memory (8 kwords verses 2 kwords) and regis- ter ?e (256 bytes versus 128 bytes). 2. four modes of operation: microcontroller, pro- tected microcontroller, extended microcontroller, and microprocessor. 3. 22 new instructions. the movf , tris and option instructions have been removed. 4. four new instructions ( tlrd , tlwt , tablrd , tablwt ) for transferring data between data memory and program memory. they can be used to ?elf program the eprom program memory. 5. single cycle data memory to data memory trans- fers possible ( movpf and movfp instructions). these instructions do not affect the working register (wreg). 6. w register (wreg) is now directly addressable. 7. a pc high latch register (pclath) is extended to 8-bits. the pclatch register is now both readable and writable. 8. data memory paging is rede?ed slightly. 9. ddr registers replaces function of tris regis- ters. 10. multiple interrupt vectors added. this can decrease the latency for servicing interrupts. 11. stack size is increased to 16 deep. 12. bsr register for data memory paging. 13. wake up from sleep operates slightly differ- ently. 14. the oscillator start-up timer (ost) and power-up timer (pwrt) operate in parallel and not in series. 15. portb interrupt on change feature works on all eight port pins. 16. tmr0 is 16-bit plus 8-bit prescaler. 17. second indirect addressing register added (fsr1 and fsr2). con?uration bits can select the fsr registers to auto-increment, auto-dec- rement, remain unchanged after an indirect address. 18. hardware multiplier added (8 x 8 ? 16-bit) 19. peripheral modules operate slightly differently. 20. a/d has both a v ref + and v ref -. 21. usarts do not implement brgh feature. 22. oscillator modes slightly rede?ed. 23. control/status bits and registers have been placed in different registers and the control bit for globally enabling interrupts has inverse polarity. 24. in-circuit serial programming is implemented dif- ferently. appendix b: compatibility to convert code written for pic16cxxx to pic17cxxx, the user should take the following steps: 1. remove any tris and option instructions, and implement the equivalent code. 2. separate the interrupt service routine into its four vectors. 3. replace: movf reg1, w with: movfp reg1, wreg 4. replace: movf reg1, w movwf reg2 with: movpf reg1, reg2 ; addr(reg1)<20h or movfp reg1, reg2 ; addr(reg2)<20h 5. ensure that all bit names and register names are updated to new data memory map locations. 6. verify data memory banking. 7. verify mode of operation for indirect addressing. 8. verify peripheral routines for compatibility. 9. weak pull-ups are enabled on reset. to convert code from the pic17c42 to all the other pic17cxxx devices, the user should take the following steps. 1. if the hardware multiply is to be used, ensure that any variables at address 18h and 19h are moved to another address. 2. ensure that the upper nibble of the bsr was not written with a non-zero value. this may cause unexpected operation since the ram bank is no longer 0. 3. the disabling of global interrupts has been enhanced so there is no additional testing of the glintd bit after a bsf cpusta, glintd instruction. note: if reg1 and reg2 are both at addresses greater then 20h, two instructions are required. movfp reg1, wreg ; movpf wreg, reg2 ;
pic17c75x ds30264a-page 266 preliminary 1997 microchip technology inc. appendix c: whats new this is the ?st revision of the data sheet . nothing new at this time. appendix d: whats changed this is the ?st revision of the data sheet . nothing new at this time.
1997 microchip technology inc. preliminary ds30264a-page 267 pic17c75x appendix e: i 2 c ? overview this section provides an overview of the inter-inte- grated circuit (i 2 c) bus, with section 15.2 discussing the operation of the ssp module in i 2 c mode. the i 2 c bus is a two-wire serial interface developed by the philips corporation. the original speci?ation, or standard mode, was for data transfers of up to 100 kbps. this device will communicate with fast mode devices if attached to the same bus. the i 2 c interface employs a comprehensive protocol to ensure reliable transmission and reception of data. when transmitting data, one device is the ?aster which initiates transfer on the bus and generates the clock signals to permit that transfer, while the other device(s) acts as the ?lave. all portions of the slave protocol are implemented in the ssp modules hard- ware, including general call support. table e-1 de?es some of the i 2 c bus terminology. for additional infor- mation on the i 2 c interface speci?ation, refer to the philips document the i 2 c bus and how to use it. #939839340011, which can be obtained from the phil- ips corporation. in the i 2 c interface protocol each device has an address. when a master wishes to initiate a data trans- fer, it ?st transmits the address of the device that it wishes to ?alk to. all devices ?isten to see if this is their address. within this address, a bit speci?s if the master wishes to read-from/write-to the slave device. the master and slave are always in opposite modes (transmitter/receiver) of operation during a data trans- fer. that is they can be thought of as operating in either of these two relations: master-transmitter and slave-receiver slave-transmitter and master-receiver in both cases the master generates the clock signal. the output stages of the clock (scl) and data (sda) lines must have an open-drain or open-collector in order to perform the wired-and function of the bus. external pull-up resistors are used to ensure a high level when no device is pulling the line down. the num- ber of devices that may be attached to the i 2 c bus is limited only by the maximum bus loading speci?ation of 400 pf. e.1 initiating and t erminating data t ransfer during times of no data transfer (idle time), both the clock line (scl) and the data line (sda) are pulled high through the external pull-up resistors. the start and stop conditions determine the start and stop of data transmission. the start condition is de?ed as a high to low transition of the sda when the scl is high. the stop condition is de?ed as a low to high transition of the sda when the scl is high. figure e-1 shows the start and stop conditions. the master generates these conditions for starting and terminating data trans- fer. due to the de?ition of the start and stop con- ditions, when data is being transmitted, the sda line can only change state when the scl line is low. figure e-1: start and stop conditions sda scl s p start condition change of data allowed change of data allowed stop condition table e-1: i 2 c bus terminology term description transmitter the device that sends the data to the bus. receiver the device that receives the data from the bus. master the device which initiates the transfer, generates the clock and terminates the transfer. slave the device addressed by a master. multi-master more than one master device in a system. these masters can attempt to control the bus at the same time without corrupting the message. arbitration procedure that ensures that only one of the master devices will control the bus. this ensure that the transfer data does not get corrupted. synchronization procedure where the clock signals of two or more devices are synchronized.
pic17c75x ds30264a-page 268 preliminary 1997 microchip technology inc. e.2 addressing i 2 c devices there are two address formats. the simplest is the 7-bit address format with a r/w bit (figure e-2). the more complex is the 10-bit address with a r/w bit (figure e-3). for 10-bit address format, two bytes must be transmitted with the ?st ?e bits specifying this to be a 10-bit address. figure e-2: 7-bit address format figure e-3: i 2 c 10-bit address format e.3 t ransfer acknowledge all data must be transmitted per byte, with no limit to the number of bytes transmitted per data transfer. after each byte, the slave-receiver generates an acknowl- edge bit (a ck ) (figure e-4). when a slave-receiver doesn? acknowledge the slave address or received data, the master must abort the transfer. the slave must leave sda high so that the master can generate the stop condition (figure e-1). s r/w ack sent by slave slave address s r/w read/write pulse msb lsb start condition ack acknowledge s 1 1 1 1 0 a9 a8 r/w a ck a7 a6 a5 a4 a3 a2 a1 a0 a ck sent by slave = 0 for write s r/w a ck - start condition - read/write pulse - acknowledge figure e-4: slave-receiver acknowledge if the master is receiving the data (master-receiver), it generates an acknowledge signal for each received byte of data, except for the last byte. to signal the end of data to the slave-transmitter, the master does not generate an acknowledge (not acknowledge). the slave then releases the sda line so the master can generate the stop condition. the master can also generate the stop condition during the acknowledge pulse for valid termination of data transfer. if the slave needs to delay the transmission of the next byte, holding the scl line low will force the master into a wait state. data transfer continues when the slave releases the scl line. this allows the slave to move the received data or fetch the data it needs to transfer before allowing the clock to start. this wait state tech- nique can also be implemented at the bit level, figure e-5. the slave will inherently stretch the clock, when it is a transmitter, but will not when it is a receiver. the slave will have to clear the ckp bit to enable clock stretching when it is a receiver. s data output by transmitter data output by receiver scl from master start condition clock pulse for acknowledgment not acknowledge acknowledge 1 2 8 9 figure e-5: data transfer wait state 12 78 9 123 89 p sda scl s start condition address r/w ack wait state data ack msb acknowledgment signal from receiver acknowledgment signal from receiver byte complete interrupt with receiver clock line held low while interrupts are serviced stop condition
1997 microchip technology inc. preliminary ds30264a-page 269 pic17c75x figure e-6 and figure e-7 show master-transmitter and master-receiver data transfer sequences. when a master does not wish to relinquish the bus (by generating a stop condition), a repeated start con- dition (sr) must be generated. this condition is identi- cal to the start condition (sda goes high-to-low while scl is high), but occurs after a data transfer acknowl- edge pulse (not the bus-free state). this allows a mas- ter to send ?ommands to the slave and then receive the requested information or to address a different slave device. this sequence is shown in figure e-8. figure e-6: master-transmitter sequence figure e-7: master-receiver sequence figure e-8: combined format for 7-bit address: s slave address first 7 bits s r/w a1 slave address second byte a2 data a data p a master transmitter addresses a slave receiver with a 10-bit address. a/a slave address r/w a data a data a/a p '0' (write) data transferred (n bytes - acknowledge) a master transmitter addresses a slave receiver with a 7-bit address. the transfer direction is not changed. from master to slave from slave to master a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition (write) for 10-bit address: for 7-bit address: s slave address first 7 bits s r/w a1 slave address second byte a2 a master transmitter addresses a slave receiver with a 10-bit address. slave address r/w a data a data a p '1' (read) data transferred (n bytes - acknowledge) a master reads a slave immediately after the ?st byte. from master to slave from slave to master a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition (write) for 10-bit address: slave address first 7 bits sr r/w a3 a data a p data (read) combined format: s combined format - a master addresses a slave with a 10-bit address, then transmits slave address r/w a data a/a sr p (read) sr = repeated transfer direction of data and acknowledgment bits depends on r/w bits. from master to slave from slave to master a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition slave address first 7 bits sr r/w a (write) data to this slave and reads data from this slave. slave address second byte data sr slave address first 7 bits r/w a data a a p a a data a/a data (read) slave address r/w a data a/a start condition (write) direction of transfer may change at this point (read or write) (n bytes + acknowledge)
pic17c75x ds30264a-page 270 preliminary 1997 microchip technology inc. e.4 multi-master the i 2 c protocol allows a system to have more than one master. this is called multi-master. when two or more masters try to transfer data at the same time, arbitration and synchronization occur. e.4.1 arbitration arbitration takes place on the sda line, while the scl line is high. the master which transmits a high when the other master transmits a low loses arbitration (figure e-9), and turns off its data output stage. a mas- ter which lost arbitration can generate clock pulses until the end of the data byte where it lost arbitration. when the master devices are addressing the same device, arbitration continues into the data. figure e-9: multi-master arbitration (two masters) masters that also incorporate the slave function, and have lost arbitration must immediately switch over to slave-receiver mode. this is because the winning mas- ter-transmitter may be addressing it. arbitration is not allowed between: a repeated start condition a stop condition and a data bit a repeated start condition and a stop condi- tion care needs to be taken to ensure that these conditions do not occur. transmitter 1 loses arbitration data 1 sda data 1 data 2 sda scl e.5 c lock synchronization clock synchronization occurs after the devices have started arbitration. this is performed using a wired-and connection to the scl line. a high to low transition on the scl line causes the concerned devices to start counting off their low period. once a device clock has gone low, it will hold the scl line low until its scl high state is reached. the low to high tran- sition of this clock may not change the state of the scl line, if another device clock is still within its low period. the scl line is held low by the device with the longest low period. devices with shorter low periods enter a high wait-state, until the scl line comes high. when the scl line comes high, all devices start counting off their high periods. the ?st device to complete its high period will pull the scl line low. the scl line high time is determined by the device with the shortest high period, figure e-10. figure e-10: clock synchronization e.6 i 2 c t iming speci cations table e-2 (figure e-11) and table e-3 (figure e-12) show the timing speci?ations as required by the phil- ips speci?ation for i 2 c. for additional information please refer to to section 15.2 and section 20.5. clk 1 clk 2 scl wait state start counting high period counter reset
1997 microchip technology inc. preliminary ds30264a-page 271 pic17c75x figure e-11: i 2 c bus start/stop bits timing specification table e-2: i 2 c bus start/stop bits timing specification microchip parameter no. sym characteristic min typ max units conditions 90 t su : sta start condition 100 khz mode 4700 ns only relevant for repeated start condition setup time 400 khz mode 600 91 t hd : sta start condition 100 khz mode 4000 ns after this period the ?st clock pulse is generated hold time 400 khz mode 600 92 t su : sto stop condition 100 khz mode 4700 ns setup time 400 khz mode 600 93 t hd : sto stop condition 100 khz mode 4000 ns hold time 400 khz mode 600 91 93 scl sda start condition stop condition 90 92
pic17c75x ds30264a-page 272 preliminary 1997 microchip technology inc. figure e-12: i 2 c bus data timing specification table e-3: i 2 c bus data timing specification microchip parameter no. sym characteristic min max units conditions 100 t high clock high time 100 khz mode 4.0 m s 400 khz mode 0.6 m s 101 t low clock low time 100 khz mode 4.7 m s 400 khz mode 1.3 m s 102 t r sda and scl rise time 100 khz mode 1000 ns 400 khz mode 20 + 0.1cb 300 ns cb is speci?d to be from 10 to 400 pf 103 t f sda and scl fall time 100 khz mode 300 ns 400 khz mode 20 + 0.1cb 300 ns cb is speci?d to be from 10 to 400 pf 90 t su : sta start condition setup time 100 khz mode 4.7 m s only relevant for repeated start condition 400 khz mode 0.6 m s 91 t hd : sta start condition hold time 100 khz mode 4.0 m s after this period the ?st clock pulse is generated 400 khz mode 0.6 m s 106 t hd : dat data input hold time 100 khz mode 0 ns 400 khz mode 0 0.9 m s 107 t su : dat data input setup time 100 khz mode 250 ns note 2 400 khz mode 100 ns 92 t su : sto stop condition setup time 100 khz mode 4.7 m s 400 khz mode 0.6 m s 109 t aa output valid from clock 100 khz mode 3500 ns note 1 400 khz mode 1000 ns 110 t buf bus free time 100 khz mode 4.7 m s time the bus must be free before a new transmission can start 400 khz mode 1.3 m s d102 cb bus capacitive loading 400 pf note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the unde?ed region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement tsu;dat 3 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max.+tsu;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus speci?ation) before the scl line is released. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
1997 microchip technology inc. preliminary ds30264a-page 273 pic17c75x appendix f: status and control registers figure f-1: pic17c75x register file map addr unbanked 00h indf0 01h fsr0 02h pcl 03h pclath 04h alusta 05h t0sta 06h cpusta 07h intsta 08h indf1 09h fsr1 0ah wreg 0bh tmr0l 0ch tmr0h 0dh tblptrl 0eh tblptrh 0fh bsr bank 0 bank 1 (1) bank 2 (1) bank 3 (1) bank 4 (1) bank 5 (1) bank 6 (1) bank 7 (1) 10h porta ddrc tmr1 pw1dcl pir2 ddrf sspadd pw3dcl 11h ddrb portc tmr2 pw2dcl pie2 portf sspcon1 pw3dch 12h portb ddrd tmr3l pw1dch ddrg sspcon2 ca3l 13h rcsta1 portd tmr3h pw2dch rcsta2 portg sspstat ca3h 14h rcreg1 ddre pr1 ca2l rcreg2 adcon0 sspbuf ca4l 15h txsta1 porte pr2 ca2h txsta2 adcon1 ca4h 16h txreg1 pir1 pr3l/ca1l tcon1 txreg2 adresl tcon3 17h spbrg1 pie1 pr3h/ca1h tcon2 spbrg2 adresh unbanked 18h prodl 19h prodh 1ah 1fh general purpose ram bank 0 (2) bank 1 (2) bank 2 (2, 3) bank 3 (2, 3) 20h ffh general purpose ram general purpose ram general purpose ram general purpose ram note 1: sfr ?e locations 10h - 17h are banked. the lower nibble of the bsr speci?s the bank. all unbanked sfrs ignore the bank select register (bsr) bits. 2: general purpose registers (gpr) locations 20h - ffh, 120h - 1ffh, 220h - 2ffh, and 320h - 3ffh are banked. the upper nibble of the bsr speci?s this bank. all other gprs ignore the bank select register (bsr) bits. 3: these ram banks are not implemented on the pic17c752. reading any register in this bank reads ?s.
pic17c75x ds30264a-page 274 preliminary 1997 microchip technology inc. figure f-2: alusta register (address: 04h, unbanked) r/w - 1 r/w - 1 r/w - 1 r/w - 1 r/w - x r/w - x r/w - x r/w - x fs3 fs2 fs1 fs0 ov z dc c r = readable bit w = writable bit -n = value at por reset (x = unknown) bit7 bit0 bit 7-6: fs3:fs2 : fsr1 mode select bits 00 = post auto-decrement fsr1 value 01 = post auto-increment fsr1 value 1x = fsr1 value does not change bit 5-4: fs1:fs0 : fsr0 mode select bits 00 = post auto-decrement fsr0 value 01 = post auto-increment fsr0 value 1x = fsr0 value does not change bit 3: ov : over?w bit this bit is used for signed arithmetic (2s complement). it indicates an over?w of the 7-bit magnitude, which causes the sign bit (bit7) to change state. 1 = over?w occurred for signed arithmetic, (in this arithmetic operation) 0 = no over?w occurred bit 2: z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the results of an arithmetic or logic operation is not zero bit 1: dc : digit carry/borro w bit for addwf and addlw instructions. 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result note: for borrow the polarity is reversed. bit 0: c : carry/borro w bit for addwf and addlw instructions. 1 = a carry-out from the most signi?ant bit of the result occurred note that a subtraction is executed by adding the twos complement of the second operand. for rotate ( rrcf , rlcf ) instructions, this bit is loaded with either the high or low order bit of the source register. 0 = no carry-out from the most signi?ant bit of the result note: for borrow the polarity is reversed.
1997 microchip technology inc. preliminary ds30264a-page 275 pic17c75x figure f-3: t0sta register (address: 05h, unbanked) r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 u - 0 intedg t0se t0cs ps3 t0ps2 t0ps1 t0ps0 r = readable bit w = writable bit u = unimplemented, reads as ? -n = value at por reset bit7 bit0 bit 7: intedg : ra0/int pin interrupt edge select bit this bit selects the edge upon which the interrupt is detected. 1 = rising edge of ra0/int pin generates interrupt 0 = falling edge of ra0/int pin generates interrupt bit 6: t0se : timer0 clock input edge select bit this bit selects the edge upon which tmr0 will increment. when t0cs = 0 (exter nal cloc k) 1 = rising edge of ra1/t0cki pin increments tmr0 and/or generates a t0ckif interrupt 0 = falling edge of ra1/t0cki pin increments tmr0 and/or generates a t0ckif interrupt when t0cs = 1 (inter nal cloc k) don? care bit 5: t0cs : timer0 clock source select bit this bit selects the clock source for timer0. 1 = internal instruction clock cycle (t cy ) 0 = external clock input on the t0cki pin bit 4-1: t0ps3:t0ps0 : timer0 prescale selection bits these bits select the prescale value for timer0. bit 0: unimplemented : read as '0' t0ps3:t0ps0 prescale value 0000 0001 0010 0011 0100 0101 0110 0111 1xxx 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
pic17c75x ds30264a-page 276 preliminary 1997 microchip technology inc. figure f-4: cpusta register (address: 06h, unbanked) u - 0 u - 0 r - 1 r/w - 1 r - 1 r - 1 r/w - 0 r/w - 0 stkav glintd t o pd por bor r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7-6: unimplemented : read as '0' bit 5: stkav : stack available bit this bit indicates that the 4-bit stack pointer value is fh, or has rolled over from fh ? 0h (stack over?w). 1 = stack is available 0 = stack is full, or a stack over?w may have occurred (once this bit has been cleared by a stack over?w, only a device reset will set this bit) bit 4: glintd : global interrupt disable bit this bit disables all interrupts. when enabling interrupts, only the sources with their enable bits set can cause an interrupt. 1 = disable all interrupts 0 = enables all un-masked interrupts bit 3: t o : wdt time-out status bit 1 = after power-up or by a clrwdt instruction 0 = a watchdog timer time-out occurred bit 2: pd : power-down status bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 1: por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set by software after a power-on reset occurs) bit 0: bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set by software after a brown-out reset occurs)
1997 microchip technology inc. preliminary ds30264a-page 277 pic17c75x figure f-5: intsta register (address: 07h, unbanked) r - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 peif t0ckif t0if intf peie t0ckie t0ie inte r = readable bit w = writable bit - n = value at por reset bit7 bit0 bit 7: peif : peripheral interrupt flag bit this bit is the or of all peripheral interrupt ?g bits and?d with their corresponding enable bits. 1 = a peripheral interrupt is pending 0 = no peripheral interrupt is pending bit 6: t0ckif : external interrupt on t0cki pin flag bit this bit is cleared by hardware, when the interrupt logic forces program execution to vector (18h). 1 = the software speci?d edge occurred on the ra1/t0cki pin 0 = the software speci?d edge did not occur on the ra1/t0cki pin bit 5: t0if : tmr0 over?w interrupt flag bit this bit is cleared by hardware, when the interrupt logic forces program execution to vector (10h). 1 = tmr0 over?wed 0 = tmr0 did not over?w bit 4: intf : external interrupt on int pin flag bit this bit is cleared by hardware, when the interrupt logic forces program execution to vector (08h). 1 = the software speci?d edge occurred on the ra0/int pin 0 = the software speci?d edge did not occur on the ra0/int pin bit 3: peie : peripheral interrupt enable bit this bit enables all peripheral interrupts that have their corresponding enable bits set. 1 = enable peripheral interrupts 0 = disable peripheral interrupts bit 2: t0ckie : external interrupt on t0cki pin enable bit 1 = enable software speci?d edge interrupt on the ra1/t0cki pin 0 = disable interrupt on the ra1/t0cki pin bit 1: t0ie : tmr0 over?w interrupt enable bit 1 = enable tmr0 over?w interrupt 0 = disable tmr0 over?w interrupt bit 0: inte : external interrupt on ra0/int pin enable bit 1 = enable software speci?d edge interrupt on the ra0/int pin 0 = disable software speci?d edge interrupt on the ra0/int pin
pic17c75x ds30264a-page 278 preliminary 1997 microchip technology inc. figure f-6: pie1 register (address: 17h, bank 1) r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 rbie tmr3ie tmr2ie tmr1ie ca2ie ca1ie tx1ie rc1ie r = readable bit w = writable bit -n = value at por reset bit7 bit0 bit 7: rbie : portb interrupt on change enable bit 1 = enable portb interrupt on change 0 = disable portb interrupt on change bit 6: tmr3ie : tmr3 interrupt enable bit 1 = enable tmr3 interrupt 0 = disable tmr3 interrupt bit 5: tmr2ie : tmr2 interrupt enable bit 1 = enable tmr2 interrupt 0 = disable tmr2 interrupt bit 4: tmr1ie : tmr1 interrupt enable bit 1 = enable tmr1 interrupt 0 = disable tmr1 interrupt bit 3: ca2ie : capture2 interrupt enable bit 1 = enable capture2 interrupt 0 = disable capture2 interrupt bit 2: ca1ie : capture1 interrupt enable bit 1 = enable capture1 interrupt 0 = disable capture1 interrupt bit 1: tx1ie : usart1 transmit interrupt enable bit 1 = enable usart1 transmit buffer empty interrupt 0 = disable usart1 transmit buffer empty interrupt bit 0: rc1ie : usart1 receive interrupt enable bit 1 = enable usart1 receive buffer full interrupt 0 = disable usart1 receive buffer full interrupt
1997 microchip technology inc. preliminary ds30264a-page 279 pic17c75x figure f-7: pie2 register (address: 11h, bank 4) r/w - 0 r/w - 0 r/w - 0 u - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 sspie bclie adie ca4ie ca3ie tx2ie rc2ie r = readable bit w = writable bit -n = value at por reset bit7 bit0 bit 7: sspie : synchronous serial port interrupt enable 1 = enable ssp interrupt 0 = disable ssp interrupt bit 6: bclie : bus collision interrupt enable 1 = enable bus collision interrupt 0 = disable bus collision interrupt bit 5: adie : a/d module interrupt enable 1 = enable a/d module interrupt 0 = disable a/d module interrupt bit 4: unimplemented: read as ? bit 3: ca4ie : capture4 interrupt enable 1 = enable capture4 interrupt 0 = disable capture4 interrupt bit 2: ca3ie : capture3 interrupt enable 1 = enable capture3 interrupt 0 = disable capture3 interrupt bit 1: tx2ie : usart2 transmit interrupt enable 1 = enable usart2 transmit interrupt 0 = disable usart2 transmit interrupt bit 0: rc2ie : usart2 receive interrupt enable 1 = enable usart2 receive interrupt 0 = disable usart2 receive interrupt
pic17c75x ds30264a-page 280 preliminary 1997 microchip technology inc. figure f-8: pir1 register (address: 16h, bank 1) r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r - 1 r - 0 rbif tmr3if tmr2if tmr1if ca2if ca1if tx1if rc1if r = readable bit w = writable bit -n = value at por reset bit7 bit0 bit 7: rbif : portb interrupt on change flag bit 1 = one of the portb inputs changed (software must end the mismatch condition) 0 = none of the portb inputs have changed bit 6: tmr3if : tmr3 interrupt flag bit if capture1 is enab led (ca1/ pr 3 = 1) 1 = tmr3 over?wed 0 = tmr3 did not over?w if capture1 is disab led (ca1/ pr 3 = 0) 1 = tmr3 value has rolled over to 0000h from equalling the period register (pr3h:pr3l) value 0 = tmr3 value has not rolled over to 0000h from equalling the period register (pr3h:pr3l) value bit 5: tmr2if : tmr2 interrupt flag bit 1 = tmr2 value has rolled over to 0000h from equalling the period register (pr2) value 0 = tmr2 value has not rolled over to 0000h from equalling the period register (pr2) value bit 4: tmr1if : tmr1 interrupt flag bit if tmr1 i s in 8-bit mode (t16 = 0) 1 = tmr1 value has rolled over to 0000h from equalling the period register (pr1) value 0 = tmr1 value has not rolled over to 0000h from equalling the period register (pr1) value if timer1 is in 16-bit mode (t16 = 1) 1 = tmr2:tmr1 value has rolled over to 0000h from equalling the period register (pr2:pr1) value 0 = tmr2:tmr1 value has not rolled over to 0000h from equalling the period register (pr2:pr1) value bit 3: ca2if : capture2 interrupt flag bit 1 = capture event occurred on rb1/cap2 pin 0 = capture event did not occur on rb1/cap2 pin bit 2: ca1if : capture1 interrupt flag bit 1 = capture event occurred on rb0/cap1 pin 0 = capture event did not occur on rb0/cap1 pin bit 1: tx1if : usart1 transmit interrupt flag bit (state controlled by hardware) 1 = usart1 transmit buffer is empty 0 = usart1 transmit buffer is full bit 0: rc1if : usart1 receive interrupt flag bit (state controlled by hardware) 1 = usart1 receive buffer is full 0 = usart1 receive buffer is empty
1997 microchip technology inc. preliminary ds30264a-page 281 pic17c75x figure f-9: pir2 register (address: 10h, bank 4) r/w - 0 r/w - 0 r/w - 0 u - 0 r/w - 0 r/w - 0 r/w - 1 r/w - 0 sspif bclif adif ca4if ca3if tx2if rc2if r = readable bit w = writable bit -n = value at por reset bit7 bit0 bit 7: sspif : synchronous serial port (ssp) interrupt flag 1 = the ssp interrupt condition has occured, and must be cleared in software before returning from the interrupt service routine. the conditions that will set this bit are: spi a transmission/reception has taken place. i 2 c sla v e / master a transmission/reception has taken place. i 2 c master the initiated start condition was completed by the ssp module. the initiated stop condition was completed by the ssp module. the initiated restart condition was completed by the ssp module. the initiated acknowledge condition was completed by the ssp module. a start condition occurred while the ssp module was idle (multimaster system). a stop condition occurred while the ssp module was idle (multimaster system). 0 = an ssp interrupt condition has occurred. bit 6: bclif : bus collision interrupt flag 1 = a bus collision has occurred in the ssp, when con?ured for i 2 c master mode 0 = no bus collision has occurred bit 5: adif : a/d module interrupt flag 1 = an a/d conversion is complete 0 = an a/d conversion is not complete bit 4: unimplemented : read as '0' bit 3: ca4if : capture4 interrupt flag 1 = capture event occurred on re3/cap4 pin 0 = capture event did not occur on re3/cap4 pin bit 2: ca3if : capture3 interrupt flag 1 = capture event occurred on rg4/cap3 pin 0 = capture event did not occur on rg4/cap3 pin bit 1: tx2if :usart2 transmit interrupt flag 1 = usart2 transmit buffer is empty 0 = usart2 transmit buffer is full bit 0: rc2if : usart2 receive interrupt flag 1 = usart2 receive buffer is full 0 = usart2 receive buffer is empty
pic17c75x ds30264a-page 282 preliminary 1997 microchip technology inc. figure f-10: txsta1 register (address: 15h, bank 0) txsta2 register (address: 15h, bank 4) r/w - 0 r/w - 0 r/w - 0 r/w - 0 u - 0 u - 0 r - 1 r/w - x csrc tx9 txen sync trmt tx9d r = readable bit w = writable bit -n = value at por reset (x = unknown) bit7 bit0 bit 7: csrc : clock source select bit synchronous mode: 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) asynchronous mode : don? care bit 6: tx9 : 9-bit transmit select bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5: txen : transmit enable bit 1 = transmit enabled 0 = transmit disabled sren/cren overrides txen in sync mode bit 4: sync : usart mode select bit (synchronous/asynchronous) 1 = synchronous mode 0 = asynchronous mode bit 3-2: unimplemented : read as '0' bit 1: trmt : transmit shift register (tsr) empty bit 1 = tsr empty 0 = tsr full bit 0: tx9d : 9th bit of transmit data (can be used to calculated the parity in software)
1997 microchip technology inc. preliminary ds30264a-page 283 pic17c75x figure f-11: rcsta1 register (address: 13h, bank 0) rcsta2 register (address: 13h, bank 4) r/w - 0 r/w - 0 r/w - 0 r/w - 0 u - 0 r - 0 r - 0 r - x spen rx9 sren cren ferr oerr rx9d r = readable bit w = writable bit -n = value at por reset (x = unknown) bit7 bit 0 bit 7: spen : serial port enable bit 1 = con?ures tx/ck and rx/dt pins as serial port pins 0 = serial port disabled bit 6: rx9 : 9-bit receive select bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5: sren : single receive enable bit this bit enables the reception of a single byte. after receiving the byte, this bit is automatically cleared. synchronous mode: 1 = enable reception 0 = disable reception note: this bit is ignored in synchronous slave reception. asynchronous mode: don? care bit 4: cren : continuous receive enable bit this bit enables the continuous reception of serial data. asynchronous mode: 1 = enable continuous reception 0 = disables continuous reception synchronous mode: 1 = enables continuous reception until cren is cleared (cren overrides sren) 0 = disables continuous reception bit 3: unimplemented : read as '0' bit 2: ferr : framing error bit 1 = framing error (updated by reading rcreg) 0 = no framing error bit 1: oerr : overrun error bit 1 = overrun (cleared by clearing cren) 0 = no overrun error bit 0: rx9d : 9th bit of receive data (can be the software calculated parity bit)
pic17c75x ds30264a-page 284 preliminary 1997 microchip technology inc. figure f-12: tcon1 register (address: 16h, bank 3) r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 ca2ed1 ca2ed0 ca1ed1 ca1ed0 t16 tmr3cs tmr2cs tmr1cs r = readable bit w = writable bit -n = value at por reset bit7 bit0 bit 7-6: ca2ed1:ca2ed0 : capture2 mode select bits 00 = capture on every falling edge 01 = capture on every rising edge 10 = capture on every 4th rising edge 11 = capture on every 16th rising edge bit 5-4: ca1ed1:ca1ed0 : capture1 mode select bits 00 = capture on every falling edge 01 = capture on every rising edge 10 = capture on every 4th rising edge 11 = capture on every 16th rising edge bit 3: t16 : timer2:timer1 mode select bit 1 = timer2 and timer1 form a 16-bit timer 0 = timer2 and timer1 are two 8-bit timers bit 2: tmr3cs : timer3 clock source select bit 1 = tmr3 increments off the falling edge of the rb5/tclk3 pin 0 = tmr3 increments off the internal clock bit 1: tmr2cs : timer2 clock source select bit 1 = tmr2 increments off the falling edge of the rb4/tclk12 pin 0 = tmr2 increments off the internal clock bit 0: tmr1cs : timer1 clock source select bit 1 = tmr1 increments off the falling edge of the rb4/tclk12 pin 0 = tmr1 increments off the internal clock
1997 microchip technology inc. preliminary ds30264a-page 285 pic17c75x figure f-13: tcon2 register (address: 17h, bank 3) r - 0 r - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 ca2ovf ca1ovf pwm2on pwm1on ca1/pr3 tmr3on tmr2on tmr1on r = readable bit w = writable bit -n = value at por reset bit7 bit0 bit 7: ca2ovf : capture2 over?w status bit this bit indicates that the capture value had not been read from the capture register pair (ca2h:ca2l) before the next capture event occurred. the capture register retains the oldest unread capture value (last capture before over?w). subsequent capture events will not update the capture register with the tmr3 value until the capture register has been read (both bytes). 1 = over?w occurred on capture2 register 0 = no over?w occurred on capture2 register bit 6: ca1ovf : capture1 over?w status bit this bit indicates that the capture value had not been read from the capture register pair (pr3h/ca1h:pr3l/ca1l) before the next capture event occurred. the capture register retains the old- est unread capture value (last capture before over?w). subsequent capture events will not update the capture register with the tmr3 value until the capture register has been read (both bytes). 1 = over?w occurred on capture1 register 0 = no over?w occurred on capture1 register bit 5: pwm2on : pwm2 on bit 1 = pwm2 is enabled (the rb3/pwm2 pin ignores the state of the ddrb<3> bit) 0 = pwm2 is disabled (the rb3/pwm2 pin uses the state of the ddrb<3> bit for data direction) bit 4: pwm1on : pwm1 on bit 1 = pwm1 is enabled (the rb2/pwm1 pin ignores the state of the ddrb<2> bit) 0 = pwm1 is disabled (the rb2/pwm1 pin uses the state of the ddrb<2> bit for data direction) bit 3: ca1/pr3 : ca1/pr3 register mode select bit 1 = enables capture1 (pr3h/ca1h:pr3l/ca1l is the capture1 register. timer3 runs without a period register) 0 = enables the period register (pr3h/ca1h:pr3l/ca1l is the period register for timer3) bit 2: tmr3on : timer3 on bit 1 = starts timer3 0 = stops timer3 bit 1: tmr2on : timer2 on bit this bit controls the incrementing of the tmr2 register. when tmr2:tmr1 form the 16-bit timer (t16 is set), tmr2on must be set. this allows the msb of the timer to increment. 1 = starts timer2 (must be enabled if the t16 bit (tcon1<3>) is set) 0 = stops timer2 bit 0: tmr1on : timer1 on bit when t16 is set (in 16-bit timer mode) 1 = starts 16-bit tmr2:tmr1 0 = stops 16-bit tmr2:tmr1 when t16 is clear (in 8-bit timer mode) 1 = starts 8-bit timer1 0 = stops 8-bit timer1
pic17c75x ds30264a-page 286 preliminary 1997 microchip technology inc. figure f-14: tcon3 register (address: 16h, bank 7) u-0 r - 0 r - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 0 - ca4ovf ca3ovf ca4ed1 ca4ed0 ca3ed1 ca3ed0 pwm3on r = readable bit w = writable bit u = unimplemented bit, reads as ? -n = value at por reset bit7 bit0 bit 7: unimplemented: read as ? bit 6: ca4ovf : capture4 over?w status bit this bit indicates that the capture value had not been read from the capture register pair (ca4h:ca4l) before the next capture event occurred. the capture register retains the oldest unread capture value (last capture before over?w). subsequent capture events will not update the capture register with the tmr3 value until the capture register has been read (both bytes). 1 = over?w occurred on capture4 registers 0 = no over?w occurred on capture4 registers bit 5: ca3ovf : capture3 over?w status bit this bit indicates that the capture value had not been read from the capture register pair (ca3h:ca3l) before the next capture event occurred. the capture register retains the oldest unread capture value (last capture before over?w). subsequent capture events will not update the capture register with the tmr3 value until the capture register has been read (both bytes). 1 = over?w occurred on capture3 registers 0 = no over?w occurred on capture3 registers bit 4-3: ca4ed1:ca4ed0 : capture4 mode select bits 00 = capture on every falling edge 01 = capture on every rising edge 10 = capture on every 4th rising edge 11 = capture on every 16th rising edge bit 2-1: ca3ed1:ca3ed0 : capture3 mode select bits 00 = capture on every falling edge 01 = capture on every rising edge 10 = capture on every 4th rising edge 11 = capture on every 16th rising edge bit 0: pwm3on : pwm3 on bit 1 = pwm3 is enabled (the rg5/pwm3 pin ignores the state of the ddrg<5> bit) 0 = pwm3 is disabled (the rg5/pwm3 pin uses the state of the ddrg<5> bit for data direction)
1997 microchip technology inc. preliminary ds30264a-page 287 pic17c75x figure f-15: adcon0 register (address: 14h, bank 5) r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 r/w-0 chs3 chs2 chs1 chs0 go/done adon r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7-4: chs2:chs0 : analog channel select bits 0000 = channel 0, (an0) 0001 = channel 1, (an1) 0010 = channel 2, (an2) 0011 = channel 3, (an3) 0100 = channel 4, (an4) 0101 = channel 5, (an5) 0110 = channel 6, (an6) 0111 = channel 7, (an7) 1000 = channel 8, (an8) 1001 = channel 9, (an9) 1010 = channel 10, (an10) 1011 = channel 11, (an11) 11xx = reserved , do not select bit 3: unimplemented : read as '0' bit 2: go/done : a/d conversion status bit if adon = 1 1 = a/d conversion in progress (setting this bit starts the a/d conversion which is automatically cleared by hardware when the a/d conversion is complete) 0 = a/d conversion not in progress bit 1: unimplemented : read as '0' bit 0: adon : a/d on bit 1 = a/d converter module is operating 0 = a/d converter module is shutoff and consumes no operating current
pic17c75x ds30264a-page 288 preliminary 1997 microchip technology inc. figure f-16: adcon1 register (address 15h, bank 5) r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 adcs1 adcs0 adfm pcfg3 pcfg2 pcfg1 pcfg0 r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7-6: adcs1:adcs0 : a/d conversion clock select bits 00 = f osc /8 01 = f osc /32 10 = f osc /64 11 = f rc (clock derived from an internal rc oscillation) bit 5: adfm : a/d result format select 1 = right justi?d. 6 most signi?ant bits of adresh are read as ?? 0 = left justi?d. 6 least signi?ant bits of adresl are read as ?? bit 4: unimplemented: read as '0' bit 3-0: pcfg3:pcfg1 : a/d port con?uration control bits bit 0: pcfg0 : a/d voltage reference select bit 1 = a/d reference is the v ref + and v ref - pins 0 = a/d reference is av dd and av ss note: when this bit is set, ensure that the a/d voltage reference speci?ations are met. a = analog input d = digital i/o pcfg3:pcfg1 an11 an10 an9 an8 an7 an6 an5 an4 an3 an2 an1 an0 000 a a aa aaaaaaaa 001 a a aa daaaaaaa 010 a a aa ddaaaaaa 011 aaaadddaaaaa 100 aaaaddddaaaa 101 d a aa dddddaaa 110 d d aa ddddddaa 111 d d dd dddddddd
1997 microchip technology inc. preliminary ds30264a-page 289 pic17c75x figure f-17: sspstat: sync serial port status register (address: 13h, bank 6) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a p s r/w ua bf r = readable bit w = writable bit u = unimplemented bit, read as ? - n =value at por reset bit7 bit0 bit 7: smp: spi data input sample phase spi master mode 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi sla v e mode smp must be cleared when spi is used in slave mode in i 2 c master or sla v e mode: 1= slew rate control disabled for standard speed mode (100 khz and 1 mhz) 0= slew rate control enabled for high speed mode (400 khz) bit 6: cke : spi clock edge select (figure 15-8, figure 15-11, and figure 15-12) ckp = 0 1 = data transmitted on rising edge of sck 0 = data transmitted on falling edge of sck ckp = 1 1 = data transmitted on falling edge of sck 0 = data transmitted on rising edge of sck bit 5: d/a : data/address bit (i 2 c slave mode only) 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4: p : stop bit (i 2 c mode only. this bit is cleared when the ssp module is disabled, sspen is cleared) 1 = indicates that a stop bit has been detected last (this bit is '0' on reset) 0 = stop bit was not detected last bit 3: s : start bit (i 2 c mode only. this bit is cleared when the ssp module is disabled, sspen is cleared) 1 = indicates that a start bit has been detected last (this bit is '0' on reset) 0 = start bit was not detected last bit 2: r/w : read/write bit information (i 2 c mode only) this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit, or a ck bit. in i 2 c sla v e mode: 1 = read 0 = write in i 2 c master mode: 1 = transmit is in progress 0 = transmit is not in progress. or?ng this bit with sae, rce, spe, or ake will indicate if the ssp is in idle mode. bit 1: ua : update address (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0: bf : buffer full status bit receiv e (spi and i 2 c modes) 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty t r ansmit (i 2 c mode only) 1 = data transmit in progress (does not include a ck and stop bits), sspbuf is full 0 = data transmit complete (does not include a ck and stop bits), sspbuf is empty
pic17c75x ds30264a-page 290 preliminary 1997 microchip technology inc. figure f-18: sspcon1: sync serial port control register (address 11h, bank 6) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 r = readable bit w = writable bit u = unimplemented bit, read as ? - n =value at por reset bit7 bit0 bit 7: wcol : write collision detect bit master mode: 1 = a write to the sspbuf register was attempted while the i 2 c conditions were not valid for a transmission to be started 0 = no collision sla v e mode: 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6: sspov : receive over?w indicator bit in spi mode 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of over- ?w, the data in sspsr is lost. over?w can only occur in slave mode. the user must read the sspbuf, even if only transmitting data, to avoid setting over?w. in master mode the over?w bit is not set since each new reception (and transmission) is initiated by writing to the sspbuf register. 0 = no over?w in i 2 c mode 1 = a byte is received while the sspbuf register is still holding the previous byte. sspov is a "don? care" in transmit mode. sspov must be cleared in software in either mode. 0 = no over?w bit 5: sspen : synchronous serial port enable bit in spi mode 1 = enables serial port and con?ures sck, sdo, and sdi as serial port pins 0 = disables serial port and con?ures these pins as i/o port pins in i 2 c mode 1 = enables the serial port and con?ures the sda and scl pins as serial port pins 0 = disables serial port and con?ures these pins as i/o port pins note: in both modes, when enabled, these pins must be properly con?ured as input or output. bit 4: ckp : clock polarity select bit in spi mode 1 = idle state for clock is a high level 0 = idle state for clock is a low level in i 2 c sla v e mode sck release control 1 = enable clock 0 = holds clock low (clock stretch) (used to ensure data setup time) in i 2 c master mode unused in this mode bit 3-0: sspm3:sspm0 : synchronous serial port mode select bits 0000 = spi master mode, clock = f osc /4 0001 = spi master mode, clock = f osc /16 0010 = spi master mode, clock = f osc /64 0011 = spi master mode, clock = tmr2 output/2 0100 = spi slave mode, clock = sck pin. ss pin control enabled. 0101 = spi slave mode, clock = sck pin. ss pin control disabled. ss can be used as i/o pin 0110 = i 2 c slave mode, 7-bit address 0111 = i 2 c slave mode, 10-bit address 1000 = i 2 c master mode, clock = f osc / (4 * (sspadd+1) ) 1xx1 = reserved 1x1x = reserved
1997 microchip technology inc. preliminary ds30264a-page 291 pic17c75x figure f-19: sspcon2: sync serial port control register2 (address 12h, bank 6) r/w-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gcen ackstat ackdt acken rcen pen rsen sen r = readable bit w = writable bit u = unimplemented bit, read as ? - n =value at por reset bit7 bit0 bit 7: gcen : general call enable bit (in i 2 c slave mode only) 1 = enable interrupt when a general call address is received in the sspsr. 0 = general call address disabled. bit 6: ackstat : acknowledge status bit (in i 2 c master mode only) in master transmit mode: 1 = acknowledge was not received from slave 0 = acknowledge was received from slave bit 5: ackdt : acknowledge data bit (in i 2 c master mode only) in master receive mode: value that will be transmitted when the user initiates an acknowledge sequence at the end of a receive. 1 = not acknowledge 0 = acknowledge bit 4: acken : acknowledge sequence enable bit (in i 2 c master mode only). in master receive mode: 1 = initiate acknowledge sequence on sda and scl pins, and transmit akd data bit. automatically cleared by hardware. 0 = acknowledge sequence idle note: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling), and the sspbuf may not be written (or writes to the sspbuf are disabled). bit 3: rcen : receive enable bit (in i 2 c master mode only). 1 = enables receive mode for i 2 c 0 = receive idle note: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling), and the sspbuf may not be written (or writes to the sspbuf are disabled). bit 2: pen : stop condition enable bit (in i 2 c master mode only). sck release control 1 = initiate stop condition on sda and scl pins. automatically cleared by hardware. 0 = stop condition idle note: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling), and the sspbuf may not be written (or writes to the sspbuf are disabled). bit 1: rsen : restart condition enabled bit (in i 2 c master mode only) 1 = initiate restart condition on sda and scl pins. automatically cleared by hardware. 0 = restart condition idle. note: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling), and the sspbuf may not be written (or writes to the sspbuf are disabled) bit 0: sen : start condition enabled bit (in i 2 c master mode only) 1 = initiate start condition on sda and scl pins. automatically cleared by hardware. 0 = start condition idle. note: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling), and the sspbuf may not be written (or writes to the sspbuf are disabled)
pic17c75x ds30264a-page 292 preliminary 1997 microchip technology inc. notes:
1997 microchip technology inc. preliminary ds30264a-page 293 pic17c75x appendix g: pic16/17 microcontrollers g.1 pic12cxxx f amil y of de vices g.2 pic14c000 f amil y of de vices pic12c508 pic12c509 pic12c671 pic12c672 clock maximum frequency of operation (mhz) 4444 memory eprom program memory 512 x 12 1024 x 12 1024 x 14 2048 x 14 data memory (bytes) 25 41 128 128 peripherals timer module(s) tmr0 tmr0 tmr0 tmr0 a/d converter (8-bit) channels 4 4 features wake-up from sleep on pin change yes yes yes yes i/o pins 5555 input pins 1111 internal pull-ups yes yes yes yes voltage range (volts) 2.5-5.5 2.5-5.5 2.5-5.5 2.5-5.5 in-circuit serial programming yes yes yes yes number of instructions 33 33 35 35 packages 8-pin dip, soic 8-pin dip, soic 8-pin dip, soic 8-pin dip, soic all pic12c5xx devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. all pic12c5xx devices use serial programming with data pin gp1 and clock pin gp0. pic14c000 clock maximum frequency of operation (mhz) 20 memory eprom program memory (x14 words) 4k data memory (bytes) 192 timer module(s) tmr0 adtmr peripherals serial port(s) (spi/i 2 c, usart) i 2 c with smbus support features slope a/d converter channels 8 external; 6 internal interrupt sources 11 i/o pins 22 voltage range (volts) 2.7-6.0 in-circuit serial programming yes additional on-chip features internal 4mhz oscillator, bandgap reference,temperature sensor, calibration factors, low voltage detector, sleep, hibernate, comparators with programmable references (2) packages 28-pin dip (.300 mil), soic, ssop
pic17c75x ds30264a-page 294 preliminary 1997 microchip technology inc. g.3 pic16c15x f amil y of de vices pic16c154 pic16cr154 pic16c156 pic16cr156 pic16c158 pic16cr158 clock maximum frequency of operation (mhz) 20 20 20 20 20 20 memory eprom program memory (x12 words) 512 1k 2k rom program memory (x12 words) 512 1k 2k ram data memory (bytes) 25 25 25 25 73 73 peripherals timer module(s) tmr0 tmr0 tmr0 tmr0 tmr0 tmr0 features i/o pins 12 12 12 12 12 12 voltage range (volts) 3.0-5.5 2.5-5.5 3.0-5.5 2.5-5.5 3.0-5.5 2.5-5.5 number of instructions 33 33 33 33 33 33 packages 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability.
1997 microchip technology inc. preliminary ds30264a-page 295 pic17c75x g.4 pic16c5x f amil y of de vices pic16c52 pic16c54 pic16c54a pic16cr54a pic16c55 pic16c56 clock maximum frequency of operation (mhz) 4202020 2020 memory eprom program memory (x12 words) 384 512 512 512 1k rom program memory (x12 words) 512 ram data memory (bytes) 25 25 25 25 24 25 peripherals timer module(s) tmr0 tmr0 tmr0 tmr0 tmr0 tmr0 features i/o pins 12 12 12 12 20 12 voltage range (volts) 2.5-6.25 2.5-6.25 2.0-6.25 2.0-6.25 2.5-6.25 2.5-6.25 number of instructions 33 33 33 33 33 33 packages 18-pin dip, soic 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 28-pin dip, soic, ssop 18-pin dip, soic; 20-pin ssop pic16c57 pic16cr57b pic16c58a pic16cr58a clock maximum frequency of operation (mhz) 20 20 20 20 memory eprom program memory (x12 words) 2k 2k rom program memory (x12 words) ?k 2k ram data memory (bytes) 72 72 73 73 peripherals timer module(s) tmr0 tmr0 tmr0 tmr0 features i/o pins 20 20 12 12 voltage range (volts) 2.5-6.25 2.5-6.25 2.0-6.25 2.5-6.25 number of instructions 33 33 33 33 packages 28-pin dip, soic, ssop 28-pin dip, soic, ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop all pic16/17 family devices have power-on reset, selectable watchdog timer (except pic16c52), selectable code protect and high i/o current capability.
pic17c75x ds30264a-page 296 preliminary 1997 microchip technology inc. g.5 pic16c55 x f amil y of de vices g.6 pic16c62x and pic16c64x f amil y of de vices pic16c554 pic16c556 (1) pic16c558 clock maximum frequency of operation (mhz) 20 20 20 memory eprom program memory (x14 words) 512 1k 2k data memory (bytes) 80 80 128 peripherals timer module(s) tmr0 tmr0 tmr0 comparators(s) internal reference voltage features interrupt sources 3 3 3 i/o pins 13 13 13 voltage range (volts) 2.5-6.0 2.5-6.0 2.5-6.0 packages 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. all pic16c5xx family devices use serial programming with clock pin rb6 and data pin rb7. note 1: please contact your local microchip sales of?e for availability of these devices. pic16c620 pic16c621 pic16c622 pic16c642 pic16c662 clock maximum frequency of operation (mhz) 20 20 20 20 20 memory eprom program memory (x14 words) 512 1k 2k 4k 4k data memory (bytes) 80 80 128 176 176 peripherals timer module(s) tmr0 tmr0 tmr0 tmr0 tmr0 comparators(s) 22222 internal reference voltage yes yes yes yes yes features interrupt sources 44445 i/o pins 13 13 13 22 33 voltage range (volts) 2.5-6.0 2.5-6.0 2.5-6.0 3.0-6.0 3.0-6.0 brown-out reset yes yes yes yes yes packages 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 28-pin pdip, soic, windowed cdip 40-pin pdip, windowed cdip; 44-pin plcc, mqfp all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. all pic16c62x and pic16c64x family devices use serial programming with clock pin rb6 and data pin rb7.
1997 microchip technology inc. preliminary ds30264a-page 297 pic17c75x g.7 pic16c6x f amil y of de vices pic16c61 pic16c62a pic16cr62 pic16c63 pic16cr63 clock maximum frequency of operation (mhz) 20 20 20 20 20 memory eprom program memory (x14 words) 1k 2k 4k rom program memory (x14 words) 2k 4k data memory (bytes) 36 128 128 192 192 peripherals timer module(s) tmr0 tmr0, tmr1, tmr2 tmr0, tmr1, tmr2 tmr0, tmr1, tmr2 tmr0, tmr1, tmr2 capture/compare/ pwm module(s) 1122 serial port(s) (spi/i 2 c, usart) spi/i 2 c spi/i 2 c spi/i 2 c, usart spi/i 2 c usart parallel slave port features interrupt sources 3 7 7 10 10 i/o pins 13 22 22 22 22 voltage range (volts) 3.0-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 in-circuit serial programming yes yes yes yes yes brown-out reset yes yes yes yes packages 18-pin dip, so 28-pin sdip, soic, ssop 28-pin sdip, soic, ssop 28-pin sdip, soic 28-pin sdip, soic pic16c64a pic16cr64 pic16c65a pic16cr65 clock maximum frequency of operation (mhz) 20 20 20 20 memory eprom program memory (x14 words) 2k 4k rom program memory (x14 words) 2k 4k data memory (bytes) 128 128 192 192 peripherals timer module(s) tmr0, tmr1, tmr2 tmr0, tmr1, tmr2 tmr0, tmr1, tmr2 tmr0, tmr1, tmr2 capture/compare/pwm module(s) 1122 serial port(s) (spi/i 2 c, usart) spi/i 2 c spi/i 2 c spi/i 2 c, usart spi/i 2 c, usart parallel slave port yes yes yes yes features interrupt sources 8 8 11 11 i/o pins 33 33 33 33 voltage range (volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 in-circuit serial programming yes yes yes yes brown-out reset yes yes yes yes packages 40-pin dip; 44-pin plcc, mqfp, tqfp 40-pin dip; 44-pin plcc, mqfp, tqfp 40-pin dip; 44-pin plcc, mqfp, tqfp 40-pin dip; 44-pin plcc, mqfp, tqfp all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. all pic16c6x family devices use serial programming with clock pin rb6 and data pin rb7.
pic17c75x ds30264a-page 298 preliminary 1997 microchip technology inc. g.8 pic16c7xx f amil y of de v ces pic16c710 pic16c71 pic16c711 pic16c715 pic16c72 pic16cr72 (1) clock maximum frequency of operation (mhz) 20 20 20 20 20 20 memory eprom program memory (x14 words) 512 1k 1k 2k 2k rom program memory (14k words) 2k data memory (bytes) 36 36 68 128 128 128 peripherals timer module(s) tmr0 tmr0 tmr0 tmr0 tmr0, tmr1, tmr2 tmr0, tmr1, tmr2 capture/compare/ pwm module(s) 1 1 serial port(s) (spi/i 2 c, usart) spi/i 2 c spi/i 2 c parallel slave port a/d converter (8-bit) channels 4 4 4 4 5 5 features interrupt sources 4 4 4 4 8 8 i/o pins 13 13 13 13 22 22 voltage range (volts) 3.0-6.0 3.0-6.0 3.0-6.0 3.0-5.5 2.5-6.0 3.0-5.5 in-circuit serial programming yes yes yes yes yes yes brown-out reset yes yes yes yes yes packages 18-pin dip, soic; 20-pin ssop 18-pin dip, soic 18-pin dip, soic; 20-pin ssop 18-pin dip, soic; 20-pin ssop 28-pin sdip, soic, ssop 28-pin sdip, soic, ssop pic16c73a pic16c74a clock maximum frequency of operation (mhz) 20 20 memory eprom program memory (x14 words) 4k 4k data memory (bytes) 192 192 peripherals timer module(s) tmr0, tmr1, tmr2 tmr0, tmr1, tmr2 capture/compare/pwm module(s) 2 2 serial port(s) (spi/i 2 c, usart) spi/i 2 c, usart spi/i 2 c, usart parallel slave port yes a/d converter (8-bit) channels 5 8 features interrupt sources 11 12 i/o pins 22 33 voltage range (volts) 2.5-6.0 2.5-6.0 in-circuit serial programming yes yes brown-out reset yes yes packages 28-pin sdip, soic 40-pin dip; 44-pin plcc, mqfp, tqfp all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capabil- ity. all pic16c7xx family devices use serial programming with clock pin rb6 and data pin rb7. note 1: please contact your local microchip sales of?e for availability of these devices.
1997 microchip technology inc. preliminary ds30264a-page 299 pic17c75x g.9 pic16c 8x f amil y of de vices pic16f83 pic16cr83 pic16f84 pic16cr84 clock maximum frequency of operation (mhz) 10 10 10 10 flash program memory 512 1k memory eeprom program memory rom program memory 512 1k data memory (bytes) 36 36 68 68 data eeprom (bytes) 64 64 64 64 peripher- als timer module(s) tmr0 tmr0 tmr0 tmr0 features interrupt sources 4 4 4 4 i/o pins 13 13 13 13 voltage range (volts) 2.0-6.0 2.0-6.0 2.0-6.0 2.0-6.0 packages 18-pin dip, soic 18-pin dip, soic 18-pin dip, soic 18-pin dip, soic all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capabil- ity. all pic16c8x family devices use serial programming with clock pin rb6 and data pin rb7.
pic17c75x ds30264a-page 300 preliminary 1997 microchip technology inc. g.10 pic16c9xx f amil y of de vices pic16c923 pic16c924 clock maximum frequency of operation (mhz) 8 8 memory eprom program memory 4k 4k data memory (bytes) 176 176 peripherals timer module(s) tmr0, tmr1, tmr2 tmr0, tmr1, tmr2 capture/compare/pwm module(s) 1 1 serial port(s) (spi/i 2 c, usart) spi/i 2 c spi/i 2 c parallel slave port a/d converter (8-bit) channels 5 lcd module 4 com, 32 seg 4 com, 32 seg features interrupt sources 8 9 i/o pins 25 25 input pins 27 27 voltage range (volts) 3.0-6.0 3.0-6.0 in-circuit serial programming yes yes brown-out reset packages 64-pin sdip (1) , tqfp; 68-pin plcc, die 64-pin sdip (1) , tqfp; 68-pin plcc, die all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capa- bility. all pic16c9xx family devices use serial programming with clock pin rb6 and data pin rb7.
1997 microchip technology inc. preliminary ds30264a-page 301 pic17c75x g.11 pic17cxx f ami l y of de vices pic17c42a pic17cr42 pic17c43 pic17cr43 pic17c44 clock maximum frequency of operation (mhz) 33 33 33 33 33 memory eprom program memory (words) 2k 4k 8k rom program memory (words) 2k 4k ram data memory (bytes) 232 232 454 454 454 peripherals timer module(s) tmr0, tmr1, tmr2, tmr3 tmr0, tmr1, tmr2, tmr3 tmr0, tmr1, tmr2, tmr3 tmr0, tmr1, tmr2, tmr3 tmr0, tmr1, tmr2, tmr3 captures/pwm module(s) 22222 serial port(s) (usart) yes yes yes yes yes features hardware multiply yes yes yes yes yes external interrupts yes yes yes yes yes interrupt sources 11 11 11 11 11 i/o pins 33 33 33 33 33 voltage range (volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 number of instructions 58 58 58 58 58 packages 40-pin dip; 44-pin plcc, mqfp, tqfp 40-pin dip; 44-pin plcc, mqfp, tqfp 40-pin dip; 44-pin plcc, mqfp, tqfp 40-pin dip; 44-pin plcc, mqfp, tqfp 40-pin dip; 44-pin plcc, mqfp, tqfp all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capa- bility.
pic17c75x ds30264a-page 302 preliminary 1997 microchip technology inc. pin compatibility devices that have the same package type and v dd , v ss and mclr pin locations are said to be pin compatible. this allows these different devices to operate in the same socket. compatible devices may only requires minor software modi?ation to allow proper operation in the application socket (ex., pic16c56 and pic16c61 devices). not all devices in the same package size are pin compatible; for example, the pic16c62 is compatible with the pic16c63, but not the pic16c55. pin compatibility does not mean that the devices offer the same features. as an example, the pic16c54 is pin compatible with the pic16c71, but does not have an a/d converter, weak pull-ups on portb, or interrupts. table g-1: pin compatible devices pin compatible devices package pic12c508, pic12c509, pic12c671, pic12c672 8-pin pic16c154, pic16cr154, pic16c156, pic16cr156, pic16c158, pic16cr158, pic16c52, pic16c54, pic16c54a, pic16cr54a, pic16c56, pic16c58a, pic16cr58a, pic16c61, pic16c554, pic16c556, pic16c558 pic16c620, pic16c621, pic16c622 pic16c641, pic16c642, pic16c661, pic16c662 pic16c710, pic16c71, pic16c711, pic16c715 pic16f83, pic16cr83, pic16f84a, pic16cr84 18-pin, 20-pin pic16c55, pic16c57, pic16cr57b 28-pin pic16cr62, pic16c62a, pic16c63, pic16c72, pic16c73a 28-pin pic16cr64, pic16c64a, pic16c65a, pic16c74a 40-pin pic17cr42, pic17c42a, pic17c43, pic17cr43, pic17c44 40-pin pic16c923, pic16c924 64/68-pin pic17c756, pic17c752 64/68-pin
1997 microchip technology inc. preliminary ds30264a-page 303 pic17c75x index a a/d accuracy/error .......................................................... 174 adcon0 register..................................................... 167 adcon1 register..................................................... 168 adif bit ..................................................................... 169 analog input model block diagram........................... 170 analog-to-digital converter....................................... 167 block diagram........................................................... 169 configuring analog port pins.................................... 172 configuring the interrupt ........................................... 169 configuring the module............................................. 169 connection considerations....................................... 174 conversion clock...................................................... 171 conversions .............................................................. 172 converter characteristics ......................................... 245 delays ....................................................................... 170 effects of a reset...................................................... 174 equations .................................................................. 170 flowchart of a/d operation....................................... 175 go/done bit ............................................................ 169 internal sampling switch (rss) impedence .............. 170 operation during sleep ............................................ 173 sampling requirements............................................ 170 sampling time .......................................................... 170 source impedence.................................................... 170 time delays .............................................................. 170 transfer function...................................................... 174 a/d interrupt........................................................................ 34 a/d interrupt flag bit, adif................................................. 34 a/d module interrupt enable, adie .................................... 32 ack ........................................................................... 135, 268 acknowledge data bitr, akd............................................. 126 acknowledge pulse........................................................... 135 acknowledge sequence enable bit, ake ......................... 126 acknowledge status bit, aks ........................................... 126 adcon0 ............................................................................. 45 adcon1 ............................................................................. 45 addlw ............................................................................. 188 addwf ............................................................................. 188 addwfc .......................................................................... 189 adie.................................................................................... 32 adif .................................................................................... 34 adres register ............................................................... 167 adresh ............................................................................. 45 adresl.............................................................................. 45 akd................................................................................... 126 ake................................................................................... 126 aks........................................................................... 126, 149 alu ....................................................................................... 9 alusta ...................................................................... 44, 184 alusta register................................................................ 47 andlw ............................................................................. 189 andwf ............................................................................. 190 application note an552,"implementing wake-up on keystroke"...................................................................... 68 application note an578, "use of the ssp module in the i 2 c multi-master environment."................................... 123 assembler ......................................................................... 220 asynchronous master transmission ................................. 114 asynchronous transmitter ................................................ 113 b bank select register (bsr)................................................ 53 banking ......................................................................... 42, 53 baud rate formula .......................................................... 110 baud rate generator ....................................................... 143 baud rate generator (brg) ............................................ 110 baud rates asynchronous mode................................................. 112 synchronous mode................................................... 111 bcf .................................................................................. 190 bclie ..................................................................................32 bclif ..................................................................................34 bf ............................................................. 124, 135, 149, 152 bit manipulation ................................................................ 184 block diagrams a/d............................................................................ 169 analog input model................................................... 170 baud rate generator ............................................... 143 bsr operation ............................................................53 external brown-out protection circuit (case1)............28 external power-on reset circuit .................................22 external program memory connection .......................41 i 2 c master mode ...................................................... 141 i 2 c module................................................................ 134 indirect addressing......................................................50 on-chip reset circuit ..................................................21 portd ........................................................................74 porte ........................................................................76 program counter operation ........................................52 pwm............................................................................97 ra0 and ra1...............................................................65 ra2..............................................................................66 ra3..............................................................................66 ra4 and ra5...............................................................66 rb3:rb2 port pins ......................................................69 rb7:rb4 and rb1:rb0 port pins ...............................68 rc7:rc0 port pins......................................................72 ssp (i 2 c mode)........................................................ 134 ssp (spi mode) ....................................................... 128 ssp module (i 2 c master mode) ............................... 123 ssp module (i 2 c slave mode) ................................. 123 ssp module (spi mode) .......................................... 123 timer3 with one capture and one period register. 100 tmr1 and tmr2 in 16-bit timer/counter mode .........95 tmr1 and tmr2 in two 8-bit timer/counter mode ...94 tmr3 with two capture registers........................... 102 using call, goto.....................................................52 wdt ......................................................................... 179 boden ................................................................................28 borrow ...................................................................................9 brg .......................................................................... 110, 143 brown-out protection ...........................................................28 brown-out reset (bor).......................................................28 bsf................................................................................... 191 bsr .............................................................................. 44, 53 bsr operation ....................................................................53 btfsc .............................................................................. 191 btfss .............................................................................. 192 btg .................................................................................. 192 buffer full bit, bf .............................................................. 135 buffer full status bit, bf................................................... 124 bus arbitration .................................................................. 160 bus collision section...................................................................... 160 bus collision during a restart condition .................... 163 bus collision during a start condition ............................. 161 bus collision during a stop condition.............................. 164 bus collision interrupt enable, bclie .................................32 bus collision interrupt flag bit, bclif ................................34
pic17c75x ds30264a-page 304 preliminary 1997 microchip technology inc. c c.............................................................................. 9, 47, 274 c compiler (mp-c)............................................................ 221 ca1/pr3 ............................................................................. 92 ca1ed0 .............................................................................. 91 ca1ed1 .............................................................................. 91 ca1ie.................................................................................. 31 ca1if .......................................................................... 33, 280 ca1ovf.............................................................................. 92 ca2ed0 .............................................................................. 91 ca2ed1 .............................................................................. 91 ca2h............................................................................. 26, 45 ca2ie.......................................................................... 31, 101 ca2if .................................................................. 33, 101, 280 ca2l ............................................................................. 26, 45 ca2ovf.............................................................................. 92 ca3h................................................................................... 46 ca3ie.................................................................................. 32 ca3if .................................................................................. 34 ca3l ................................................................................... 46 ca4h................................................................................... 46 ca4ie.................................................................................. 32 ca4if .................................................................................. 34 calculating baud rate error ............................................. 110 call ........................................................................... 50, 193 capacitor selection ceramic resonators ................................................... 16 crystal oscillator ......................................................... 16 capture ....................................................................... 91, 100 capture sequence to read example................................ 103 capture1 mode ........................................................................... 91 overflow ................................................ 92, 93, 285, 286 capture1 interrupt ....................................................... 33, 280 capture2 mode ........................................................................... 91 overflow ................................................ 92, 93, 285, 286 capture2 interrupt ....................................................... 33, 280 capture3 interrupt enable, ca3ie ...................................... 32 capture3 interrupt flag bit, ca3if ...................................... 34 capture4 interrupt enable, ca4ie ...................................... 32 capture4 interrupt flag bit, ca4if ...................................... 34 carry (c) ............................................................................... 9 ceramic resonators ........................................................... 15 circular buffer ..................................................................... 50 cke................................................................................... 124 ckp........................................................................... 125, 290 clearing the prescaler....................................................... 179 clock polarity select bit, ckp ................................... 125, 290 clock/instruction cycle (figure) .......................................... 19 clocking scheme/instruction cycle..................................... 19 clrf................................................................................. 193 clrwdt........................................................................... 194 code examples indirect addressing ..................................................... 51 loading the sspbuf register................................... 127 saving status and wreg in ram .............................. 38 table read ................................................................. 60 table write.................................................................. 58 code protection ................................................................ 181 comf................................................................................ 194 configuration bits ............................................................................ 178 locations................................................................... 178 oscillator ............................................................. 15, 178 word ......................................................................... 177 cpfseq ........................................................................... 195 cpfsgt ........................................................................... 195 cpfslt ............................................................................ 196 cpusta ............................................................... 44, 48, 180 crystal operation, overtone crystals ................................. 16 crystal or ceramic resonator operation............................ 16 crystal oscillator................................................................. 15 d d/a .................................................................................... 124 data memory gpr ...................................................................... 39, 42 indirect addressing ..................................................... 50 organization ............................................................... 42 sfr ............................................................................ 39 data memory banking ........................................................ 42 data/address bit, d/a ....................................................... 124 daw ................................................................................. 196 dc........................................................................... 9, 47, 274 ddrb...................................................................... 25, 44, 68 ddrc ..................................................................... 25, 44, 72 ddrd ..................................................................... 25, 44, 74 ddre...................................................................... 25, 44, 76 ddrf.................................................................................. 45 ddrg ................................................................................. 45 decf ................................................................................ 197 decfsnz......................................................................... 198 decfsz ........................................................................... 197 delay from external clock edge........................................ 88 development support ....................................................... 219 development tools........................................................... 219 digit borrow .......................................................................... 9 digit carry (dc) .................................................................... 9 duty cycle .......................................................................... 97 e electrical characteristics pic17c752/756 absolute maximum ratings.............................. 223 capture timing ................................................. 236 clkout and i/o timing .................................. 233 dc characteristics............................................ 225 external clock timing....................................... 232 memory interface read timing ........................ 248 memory interface write timing ........................ 247 parameter measurement information............... 231 reset, watchdog timer, oscillator start-up timer and power-up timer timing ................... 234 timer0 clock timing......................................... 235 timer1, timer2 and timer3 clock timing ........ 235 timing parameter symbology .......................... 230 usart module synchronous receive timing.................................................................. 244 usart module synchronous transmission timing............................................................... 244 eprom memory access time order suffix....................... 41 extended microcontroller .................................................... 39 extended microcontroller mode .......................................... 41 external memory interface.................................................. 41 external program memory waveforms............................... 41
1997 microchip technology inc. preliminary ds30264a-page 305 pic17c75x f family of devices pic12cxxx .............................................................. 293 pic14c000 ............................................................... 293 pic16c15x ............................................................... 294 pic16c55x ............................................................... 296 pic16c5x ................................................................. 295 pic16c62x and pic16c64x .................................... 296 pic16c6x ................................................................. 297 pic16c7xx............................................................... 298 pic16c8x ................................................................. 299 pic16c9xx............................................................... 300 pic17c75x ................................................................... 6 pic17cxx................................................................. 301 ferr ................................................................................ 115 flowcharts acknowledge............................................................. 156 master receiver........................................................ 153 master transmit ........................................................ 150 restart condition ...................................................... 147 start condition .......................................................... 145 stop condition .......................................................... 158 fosc0 .............................................................................. 177 fosc1 .............................................................................. 177 fs0 ............................................................................. 47, 274 fs1 ............................................................................. 47, 274 fs2 ............................................................................. 47, 274 fs3 ............................................................................. 47, 274 fsr0 ............................................................................. 44, 51 fsr1 ............................................................................. 44, 51 fuzzy logic dev. system ( fuzzy tech -mp) .......... 219, 221 g gce .................................................................................. 126 general call address sequence....................................... 139 general call address support .......................................... 139 general call enable bit, gce ........................................... 126 general format for instructions ........................................ 184 general purpose ram ........................................................ 39 general purpose ram bank............................................... 53 general purpose register (gpr) ....................................... 42 glintd ......................................................... 35, 48, 101, 180 global interrupt disable bit, glintd .................................. 35 goto ............................................................................... 198 gpr (general purpose register) ....................................... 42 gpr banks ......................................................................... 53 graphs i oh vs. v oh , v dd = 3v .............................................. 256 i oh vs. v oh , v dd = 5v .............................................. 257 i ol vs. v ol , v dd = 3v ............................................... 257 i ol vs. v ol , v dd = 5v ............................................... 258 maximum i dd vs. frequency (external clock 125 c to -40 c) ........................................................ 253 maximum i pd vs. v dd watchdog disabled ............... 254 maximum i pd vs. v dd watchdog enabled................ 255 rc oscillator frequency vs. v dd (cext = 100 pf).... 250 rc oscillator frequency vs. v dd (cext = 22 pf)...... 250 rc oscillator frequency vs. v dd (cext = 300 pf).... 251 transconductance of lf oscillator vs.v dd ............... 252 transconductance of xt oscillator vs. v dd .............. 252 typical i dd vs. frequency (external clock 25 c) ..... 253 typical i pd vs. v dd watchdog disabled 25 c .......... 254 typical i pd vs. v dd watchdog enabled 25 c ........... 255 typical rc oscillator vs. temperature ..................... 249 v ih , v il of mclr , t0cki and osc1 (in rc mode) vs. v dd ...................................................................... 259 v th (input threshold voltage) of i/o pins vs. v dd ... 258 v th (input threshold voltage) of osc1 input (in xt, hs, and lp modes) vs. v dd ................ 259 wdt timer time-out period vs. v dd ....................... 256 h hardware multiplier..............................................................61 i i/o ports bi-directional................................................................83 i/o ports ......................................................................65 programming considerations ......................................83 read-modify-write instructions ...................................83 successive operations................................................83 i 2 c .................................................................................... 134 addressing i 2 c devices............................................ 268 arbitration ................................................................. 270 combined format..................................................... 269 i 2 c overview ............................................................ 267 initiating and terminating data transfer .................. 267 master-receiver sequence ...................................... 269 master-transmitter sequence .................................. 269 multi-master.............................................................. 270 start...................................................................... 267 stop................................................................ 267, 268 transfer acknowledge.............................................. 268 i 2 c master mode receiver flowchart............................... 153 i 2 c master mode reception ............................................. 152 i 2 c master mode restart condition.................................. 146 i 2 c mode selection........................................................... 134 i 2 c module acknowledge flowchart............................................ 156 acknowledge sequence timing ................................ 155 addressing................................................................ 135 baud rate generator ............................................... 143 block diagram .......................................................... 141 brg block diagram ................................................. 143 brg reset due to sda collision ............................. 162 brg timing .............................................................. 143 bus arbitration .......................................................... 160 bus collision............................................................. 160 acknowledge .................................................... 160 restart condition.............................................. 163 restart condition timing (case1) .................... 163 restart condition timing (case2) .................... 163 start condition.................................................. 161 start condition timing .............................. 161, 162 stop condition .................................................. 164 stop condition timing (case1) ........................ 164 stop condition timing (case2) ........................ 164 transmit timing................................................ 160 bus collision timing .................................................. 160 clock arbitration ....................................................... 159 clock arbitration timing (master transmit) .............. 159 conditions to not give ack pulse............................. 135 general call address support.................................. 139 master mode............................................................. 141 master mode 7-bit reception timing......................... 154 master mode operation............................................ 142 master mode start condition.................................... 144 master mode transmission ...................................... 149 master mode transmit sequence ............................ 142 master transmit flowchart ....................................... 150 multi-master communication.................................... 160 multi-master mode.................................................... 142 operation.................................................................. 134 repeat start condition timing................................... 146 restart condition flowchart ..................................... 147 slave mode............................................................... 135
pic17c75x ds30264a-page 306 preliminary 1997 microchip technology inc. slave reception........................................................ 136 slave transmission................................................... 136 sspbuf.................................................................... 134 start condition flowchart.......................................... 145 stop condition flowchart .......................................... 158 stop condition receive or transmit timing............... 157 stop condition timing................................................ 157 waveforms for 7-bit reception ................................. 136 waveforms for 7-bit transmission ............................ 136 i 2 c module address register, sspadd........................... 134 i 2 c slave mode ................................................................. 135 incf.................................................................................. 199 incfsnz........................................................................... 200 incfsz ............................................................................. 199 in-circuit serial programming ........................................... 182 indf0............................................................................ 44, 51 indf1............................................................................ 44, 51 indirect addressing indirect addressing ..................................................... 50 operation .................................................................... 51 registers ..................................................................... 51 initialization conditions for special function registers ...... 25 initializing portb ............................................................... 69 initializing portc............................................................... 72 initializing portd............................................................... 74 initializing porte ................................................... 76, 78, 80 insta.................................................................................. 44 instruction flow/pipelining .................................................. 19 instruction set ................................................................... 186 addlw ..................................................................... 188 addwf ..................................................................... 188 addwfc .................................................................. 189 andlw ..................................................................... 189 andwf ..................................................................... 190 bcf ........................................................................... 190 bsf ........................................................................... 191 btfsc ...................................................................... 191 btfss ...................................................................... 192 btg........................................................................... 192 call ......................................................................... 193 clrf......................................................................... 193 clrwdt................................................................... 194 comf ....................................................................... 194 cpfseq ................................................................... 195 cpfsgt ................................................................... 195 cpfslt .................................................................... 196 daw.......................................................................... 196 decf ........................................................................ 197 decfsnz ................................................................. 198 decfsz.................................................................... 197 goto ....................................................................... 198 incf.......................................................................... 199 incfsnz .................................................................. 200 incfsz ..................................................................... 199 iorlw ...................................................................... 200 iorwf ...................................................................... 201 lcall ....................................................................... 201 movfp ..................................................................... 202 movlb ..................................................................... 202 movlr ..................................................................... 203 movlw .................................................................... 203 movpf ..................................................................... 204 movwf .................................................................... 204 mullw ..................................................................... 205 mulwf ..................................................................... 205 negw ....................................................................... 206 nop .......................................................................... 206 retfie ..................................................................... 207 retlw ..................................................................... 207 return................................................................... 208 rlcf ........................................................................ 208 rlncf...................................................................... 209 rrcf........................................................................ 209 rrncf ..................................................................... 210 setf ........................................................................ 210 sleep ...................................................................... 211 sublw ..................................................................... 211 subwf..................................................................... 212 subwfb .................................................................. 212 swapf ..................................................................... 213 tablrd ........................................................... 213, 214 tablwt ........................................................... 214, 215 tlrd ........................................................................ 215 tlwt ........................................................................ 216 tstfsz .................................................................... 216 xorlw .................................................................... 217 xorwf .................................................................... 217 instruction set summary .................................................. 183 instructions tablrd ..................................................................... 60 tlrd .......................................................................... 60 int pin................................................................................ 36 inte.................................................................................... 30 intedg ........................................................................ 49, 87 inter-integrated circuit (i 2 c) ............................................. 123 internal sampling switch (rss) impedence...................... 170 interrupt on change feature .............................................. 68 interrupt status register (intsta)..................................... 30 interrupts a/d interrupt ............................................................... 34 bus collision interrupt ................................................ 34 capture1 interrupt .............................................. 33, 280 capture2 interrupt .............................................. 33, 280 capture3 interrupt ...................................................... 34 capture4 interrupt ...................................................... 34 context saving ........................................................... 35 flag bits tmr1ie .............................................................. 29 tmr1if............................................................... 29 tmr2ie .............................................................. 29 tmr2if............................................................... 29 tmr3ie .............................................................. 29 tmr3if............................................................... 29 global interrupt disable .............................................. 35 interrupts .................................................................... 29 logic ........................................................................... 29 operation .................................................................... 35 peripheral interrupt enable......................................... 31 peripheral interrupt request ...................................... 33 pie2 register ............................................................. 32 pir1 register ............................................................. 33 pir2 register ............................................................. 34 portb interrupt on change .............................. 33, 280 pwm ........................................................................... 98 ra0/int ...................................................................... 35 status register ........................................................... 30 synchronous serial port interrupt .............................. 34 t0cki interrupt ........................................................... 35 timing ......................................................................... 36 tmr1 overflow interrupt .................................... 33, 280 tmr2 overflow interrupt .................................... 33, 280 tmr3 overflow interrupt .................................... 33, 280 usart1 receive interrupt ................................. 33, 280 usart1 transmit interrupt ................................ 33, 280
1997 microchip technology inc. preliminary ds30264a-page 307 pic17c75x usart2 receive interrupt ......................................... 34 vectors peripheral interrupt ............................................. 35 program memory locations................................ 39 ra0/int interrupt................................................ 35 t0cki interrupt ................................................... 35 vectors/priorities......................................................... 35 wake-up from sleep............................................... 180 intf .................................................................................... 30 intsta ............................................................................... 44 intsta register ................................................................. 30 iorlw .............................................................................. 200 iorwf .............................................................................. 201 l lcall ......................................................................... 50, 201 m maps register file map................................................ 43, 273 memory external interface........................................................ 41 external memory waveforms...................................... 41 memory map (different modes) .................................. 40 mode memory access ................................................ 40 organization................................................................ 39 program memory ........................................................ 39 program memory map ................................................ 39 microcontroller .................................................................... 39 microprocessor ................................................................... 39 minimizing current consumption ...................................... 181 movfp ....................................................................... 42, 202 moving data between data and program memories.......... 42 movlb ....................................................................... 42, 202 movlr ............................................................................. 203 movlw ............................................................................ 203 movpf ....................................................................... 42, 204 movwf ............................................................................ 204 mpasm assembler ................................................... 219, 220 mp-c c compiler .............................................................. 221 mpsim software simulator ....................................... 219, 221 mullw ............................................................................. 205 multi-master communication ............................................ 160 multi-master mode ............................................................ 142 multiply examples 16 x 16 routine........................................................... 62 16 x 16 signed routine............................................... 63 8 x 8 routine............................................................... 61 8 x 8 signed routine................................................... 61 mulwf ............................................................................. 205 n negw ............................................................................... 206 nop .................................................................................. 206 o opcode field descriptions ................................................ 183 opcodes.............................................................................. 52 oscillator configuration....................................................... 15, 178 crystal......................................................................... 15 external clock............................................................. 17 external crystal circuit ............................................... 17 external parallel resonant crystal circuit .................. 17 external series resonant crystal circuit.................... 17 rc............................................................................... 18 rc frequencies........................................................ 251 oscillator start-up time (figure) .........................................22 oscillator start-up timer (ost) ...........................................22 ost .....................................................................................22 ov .......................................................................... 9, 47, 274 overflow (ov) ........................................................................9 p p ....................................................................................... 124 packaging information ...................................................... 261 pc (program counter).........................................................52 pcfg0 bit ................................................................. 168, 288 pcfg1 bit ................................................................. 168, 288 pcfg2 bit ................................................................. 168, 288 pch .....................................................................................52 pcl....................................................................... 44, 52, 184 pclath ....................................................................... 44, 52 pd ............................................................................... 48, 180 peie ........................................................................... 30, 101 peif.....................................................................................30 peripheral bank ...................................................................53 peripheral banks .................................................................53 peripheral interrupt enable..................................................31 peripheral interrupt request (pir1) ....................................33 peripheral register banks ...................................................42 picdem-1 low-cost pic16/17 demo board ........... 219, 220 picdem-2 low-cost pic16cxx demo board......... 219, 220 picdem-3 low-cost pic16c9xxx demo board ............ 220 picmaster in-circuit emulator ...................................... 219 picstart low-cost development system .................... 219 picstart low-cost development system .................... 219 pie .................................................................... 116, 120, 122 pie1 .............................................................................. 25, 44 pie2 ........................................................................ 25, 32, 45 pin compatible devices ................................................... 302 pir.................................................................... 116, 120, 122 pir1.............................................................................. 25, 44 pir2.............................................................................. 25, 45 pm0 .......................................................................... 177, 181 pm1 .......................................................................... 177, 181 pop .............................................................................. 35, 50 por .....................................................................................22 porta ................................................................... 25, 44, 65 portb ................................................................... 25, 44, 68 portb interrupt on change ...................................... 33, 280 portc ................................................................... 25, 44, 72 portd ................................................................... 25, 44, 74 porte ................................................................... 25, 44, 76 portf ................................................................................45 portg ................................................................................45 power-down mode............................................................ 180 power-on reset (por)........................................................22 power-up timer (pwrt) .....................................................22 pr1............................................................................... 26, 45 pr2............................................................................... 26, 45 pr3/ca1h ...........................................................................26 pr3/ca1l............................................................................26 pr3h/ca1h ........................................................................45 pr3l/ca1l..........................................................................45 prescaler assignments ........................................................89 pro mate universal programmer .................................. 219 prodh......................................................................... 27, 46 prodl ......................................................................... 27, 46 program counter (pc).........................................................52 program memory external access waveforms........................................41
pic17c75x ds30264a-page 308 preliminary 1997 microchip technology inc. external connection diagram ..................................... 41 map ............................................................................. 39 modes extended microcontroller .................................... 39 microcontroller .................................................... 39 microprocessor ................................................... 39 protected microcontroller .................................... 39 operation .................................................................... 39 organization................................................................ 39 protected microcontroller .................................................... 39 ps0 ............................................................................... 49, 87 ps1 ............................................................................... 49, 87 ps2 ............................................................................... 49, 87 ps3 ............................................................................... 49, 87 push ............................................................................ 35, 50 pw1dch....................................................................... 26, 45 pw1dcl ....................................................................... 26, 45 pw2dch....................................................................... 26, 45 pw2dcl ....................................................................... 26, 45 pw3dch....................................................................... 27, 46 pw3dcl ....................................................................... 27, 46 pwm ............................................................................. 91, 97 duty cycle................................................................... 98 external clock source ................................................ 99 frequency vs. resolution ........................................... 98 interrupts ..................................................................... 98 max resolution/frequency for external clock input ... 99 output ......................................................................... 97 periods........................................................................ 98 pwm1 ........................................................... 92, 93, 285, 286 pwm1on ...................................................................... 92, 97 pwm2 ........................................................... 92, 93, 285, 286 pwm2on ...................................................................... 92, 97 pwm3on ............................................................................ 93 pwrt.................................................................................. 22 r r/w ................................................................................... 124 r/w bit ...................................................................... 135, 268 r/w bit .............................................................................. 136 ra1/t0cki pin .................................................................... 87 rbie.................................................................................... 31 rbif .................................................................................... 33 rbpu .................................................................................. 68 rc oscillator ....................................................................... 18 rc oscillator frequencies ................................................ 251 rc1ie.................................................................................. 31 rc1if.......................................................................... 33, 280 rc2ie.................................................................................. 32 rc2if.................................................................................. 34 rce,receive enable bit, rce .......................................... 126 rcreg ..................................................... 115, 116, 120, 121 rcreg1 ....................................................................... 25, 44 rcreg2 ....................................................................... 25, 45 rcsta .............................................................. 116, 120, 122 rcsta1 ........................................................................ 25, 44 rcsta2 ........................................................................ 25, 45 read/write bit, r/w .......................................................... 124 reading 16-bit value........................................................... 89 receive overflow indicator bit, sspov .................... 125, 290 receive status and control register ................................ 107 register file map ........................................................ 43, 273 registers adcon0 ..................................................................... 45 adcon1 ..................................................................... 45 adresh ..................................................................... 45 adresl ..................................................................... 45 alusta.......................................................... 35, 44, 47 brg .......................................................................... 110 bsr ...................................................................... 35, 44 ca2h .......................................................................... 45 ca2l........................................................................... 45 ca3h .......................................................................... 46 ca3l........................................................................... 46 ca4h .......................................................................... 46 ca4l........................................................................... 46 cpusta ............................................................... 44, 48 ddrb ......................................................................... 44 ddrc ......................................................................... 44 ddrd ......................................................................... 44 ddre ......................................................................... 44 ddrf.......................................................................... 45 ddrg ......................................................................... 45 fsr0 .................................................................... 44, 51 fsr1 .................................................................... 44, 51 indf0 ................................................................... 44, 51 indf1 ................................................................... 44, 51 insta ......................................................................... 44 intsta ....................................................................... 30 pcl............................................................................. 44 pclath ..................................................................... 44 pie1 ...................................................................... 31, 44 pie2 ...................................................................... 32, 45 pir1...................................................................... 33, 44 pir2...................................................................... 34, 45 porta ....................................................................... 44 portb ....................................................................... 44 portc ....................................................................... 44 portd ....................................................................... 44 porte ....................................................................... 44 portf ....................................................................... 45 portg ....................................................................... 45 pr1............................................................................. 45 pr2............................................................................. 45 pr3h/ca1h ............................................................... 45 pr3l/ca1l................................................................. 45 prodh....................................................................... 46 prodl ....................................................................... 46 pw1dch .................................................................... 45 pw1dcl..................................................................... 45 pw2/dcl.................................................................... 45 pw2dch .................................................................... 45 pw3dch .................................................................... 46 pw3dcl..................................................................... 46 rcreg1..................................................................... 44 rcreg2..................................................................... 45 rcsta1 ..................................................................... 44 rcsta2 ..................................................................... 45 spbrg1 ..................................................................... 44 spbrg2 ..................................................................... 45 special function table ............................................... 44 sspadd ..................................................................... 46 sspbuf ..................................................................... 46 sspcon1 .................................................................. 46 sspcon2 .................................................................. 46 sspstat ........................................................... 46, 124 t0sta ............................................................ 44, 49, 87 tblptrh ................................................................... 44 tblptrl .................................................................... 44 tcon1 ................................................................. 45, 91 tcon2 ................................................................. 45, 92 tcon3 ................................................................. 46, 93 tmr0h ....................................................................... 44
1997 microchip technology inc. preliminary ds30264a-page 309 pic17c75x tmr1 .......................................................................... 45 tmr2 .......................................................................... 45 tmr3h........................................................................ 45 tmr3l ........................................................................ 45 txreg1...................................................................... 44 txreg2...................................................................... 45 txsta1 ...................................................................... 44 txsta2 ...................................................................... 45 wreg................................................................... 35, 44 regsters tmr0l ........................................................................ 44 reset section ........................................................................ 21 status bits and their significance .............................. 23 time-out in various situations ................................... 23 time-out sequence.................................................... 23 restart condition enabled bit, rse.................................. 126 retfie ............................................................................. 207 retlw ............................................................................. 207 return ........................................................................... 208 rlcf................................................................................. 208 rlncf .............................................................................. 209 rrcf ................................................................................ 209 rrncf ............................................................................. 210 rse................................................................................... 126 rx pin sampling scheme................................................. 115 s s........................................................................................ 124 sae................................................................................... 126 sampling ........................................................................... 115 saving status and wreg in ram .................................. 38 sck................................................................................... 127 scl ................................................................................... 135 sda................................................................................... 135 sdi .................................................................................... 127 sdo .................................................................................. 127 serial clock, sck ............................................................. 127 serial clock, scl .............................................................. 135 serial data address, sda................................................. 135 serial data in, sdi ............................................................ 127 serial data out, sdo........................................................ 127 setf ................................................................................. 210 sfr ................................................................................... 184 sfr (special function registers)....................................... 39 sfr as source/destination .............................................. 184 signed math.......................................................................... 9 slave select synchronization ........................................... 130 slave select, ss ............................................................... 127 sleep ...................................................................... 180, 211 smp .................................................................................. 124 software simulator (mpsim) ............................................ 221 spbrg ............................................................. 116, 120, 122 spbrg1 ....................................................................... 25, 44 spbrg2 ....................................................................... 25, 45 spe................................................................................... 126 special features of the cpu ............................................ 177 special function registers ................................... 39, 44, 184 summary..................................................................... 44 special function registers, file map ......................... 43, 273 spi master mode ............................................................. 129 serial clock............................................................... 127 serial data in ............................................................ 127 serial data out ......................................................... 127 serial peripheral interface (spi) ............................... 123 slave select.............................................................. 127 spi clock................................................................... 129 spi mode.................................................................. 127 spi clock edge select, cke ............................................ 124 spi data input sample phase select, smp ..................... 124 spi master/slave connection........................................... 130 spi module master/slave connection ......................................... 130 slave mode............................................................... 130 slave select synchronization ................................... 130 slave synch timnig.................................................. 131 slave timing with cke = 0 ....................................... 132 slave timing with cke = 1 ....................................... 133 ss ..................................................................................... 127 ssp .................................................................................. 123 block diagram (spi mode) ....................................... 128 spi mode.................................................................. 127 sspadd........................................................... 134, 135 sspbuf ........................................................... 129, 134 sspcon1 ................................................................ 125 sspcon2 ................................................................ 126 sspsr ............................................................. 129, 135 sspstat ......................................................... 124, 134 ssp i 2 c ssp i 2 c operation ................................................... 134 ssp module spi master mode...................................................... 129 spi master./slave connection.................................. 130 spi slave mode........................................................ 130 sspcon1 register .................................................. 134 ssp overflow detect bit, sspov..................................... 135 sspadd ..............................................................................46 sspbuf ............................................................. 46, 134, 135 sspcon1 .......................................................... 46, 125, 134 sspcon2 .................................................................. 46, 126 sspen ..................................................................... 125, 290 sspie ..................................................................................32 sspif ......................................................................... 34, 136 sspm3:sspm0 ........................................................ 125, 290 sspov ..................................................... 125, 135, 152, 290 sspstat ........................................................... 46, 124, 134 stack operation.....................................................................50 pointer .........................................................................50 stack............................................................................39 start bit (s) ....................................................................... 124 start condition enabled bit, sae...................................... 126 stkav .......................................................................... 48, 50 stop bit (p)........................................................................ 124 stop condition enable bit ................................................. 126 sublw ............................................................................. 211 subwf............................................................................. 212 subwfb .......................................................................... 212 swapf ............................................................................. 213 synchronous master mode............................................... 117 synchronous master reception ....................................... 119 synchronous master transmission .................................. 117 synchronous serial port ................................................... 123 synchronous serial port enable bit, sspen............ 125, 290 synchronous serial port interrupt .......................................34 synchronous serial port interrupt enable, sspie...............32 synchronous serial port mode select bits, sspm3:sspm0 ........................................................ 125, 290 synchronous slave mode................................................. 121 t t0cki ..................................................................................35
pic17c75x ds30264a-page 310 preliminary 1997 microchip technology inc. t0cki pin............................................................................ 36 t0ckie................................................................................ 30 t0ckif................................................................................ 30 t0cs ............................................................................. 49, 87 t0ie..................................................................................... 30 t0if..................................................................................... 30 t0se ............................................................................. 49, 87 t0sta ........................................................................... 44, 49 t16 ...................................................................................... 91 table latch ......................................................................... 51 table pointer....................................................................... 51 table read example ...................................................................... 60 table reads section................................................... 60 tlrd........................................................................... 60 table write code ........................................................................... 58 timing ......................................................................... 58 to external memory.................................................... 58 tablrd .................................................................... 213, 214 tablwt.................................................................... 214, 215 t ad .................................................................................... 171 tblath .............................................................................. 51 tblatl ............................................................................... 51 tblptrh...................................................................... 44, 51 tblptrl ...................................................................... 44, 51 tclk12 ....................................................................... 91, 284 tclk3 ......................................................................... 91, 284 tcon1 .......................................................................... 26, 45 tcon2 ................................................................................ 45 tcon2,tcon3................................................................... 26 tcon3 .......................................................................... 46, 93 time-out sequence ............................................................ 23 timer resources................................................................. 85 timer0 ................................................................................. 87 timer1 16-bit mode ................................................................. 95 clock source select.................................................... 91 on bit .................................................... 92, 93, 285, 286 section .................................................................. 91, 94 timer2 16-bit mode ................................................................. 95 clock source select.................................................... 91 on bit .................................................... 92, 93, 285, 286 section .................................................................. 91, 94 timer3 clock source select.................................................... 91 on bit .................................................... 92, 93, 285, 286 section ................................................................ 91, 100 timers tcon3 ........................................................................ 93 timing diagrams a/d conversion ......................................................... 246 acknowledge sequence timing................................ 155 asynchronous master transmission ......................... 114 asynchronous reception .......................................... 116 back to back asynchronous master transmission ... 114 baud rate generator with clock arbitration ............. 143 brg reset due to sda collision ............................. 162 bus collision start condition timing ...................................... 161 bus collision during a restart condition (case 1) ... 163 bus collision during a restart condition (case2) .... 163 bus collision during a start condition (scl = 0) ..... 162 bus collision during a stop condition ...................... 164 bus collision for transmit and acknowledge............ 160 external parallel resonant crystal oscillator circuit ......................................................................... 17 external program memory access ............................. 41 i 2 c bus data............................................................. 242 i 2 c bus start/stop bits.............................................. 241 i 2 c master mode first start bit timing ...................... 144 i 2 c master mode reception timing........................... 154 i 2 c master mode transmission timing ..................... 151 interrupt (int, tmr0 pins) ......................................... 36 master mode transmit clock arbitration .................. 159 oscillator start-up time .............................................. 22 pic17c752/756 capture timing .............................. 236 pic17c752/756 clkout and i/o............................ 233 pic17c752/756 external clock ................................ 232 pic17c752/756 memory interface read ................. 248 pic17c752/756 memory interface write.................. 247 pic17c752/756 pwm timing .................................. 236 pic17c752/756 reset, watchdog timer, oscillator start-up timer and power-up timer ......................... 234 pic17c752/756 timer0 clock .................................. 235 pic17c752/756 timer1, timer2 and timer3 clock . 235 pic17c752/756 usart module synchronous receive..................................................................... 244 pic17c752/756 usart module synchronous transmission ............................................................ 244 repeat start condition ............................................. 146 slave synchronization .............................................. 131 spi mode timing (master mode)spi mode master mode timing diagram .......................... 129 spi mode timing (slave mode with cke = 0).......... 132 spi mode timing (slave mode with cke = 1).......... 133 stop condition receive or transmit ......................... 157 synchronous reception ........................................... 119 synchronous transmission ...................................... 118 table write ................................................................. 58 tmr0 .................................................................... 88, 89 tmr0 read/write in timer mode ............................... 90 tmr1, tmr2, and tmr3 in timer mode ................. 105 wake-up from sleep .............................................. 180 tlrd ................................................................................ 215 tlwt ................................................................................ 216 tmr0 16-bit read ................................................................. 89 16-bit write ................................................................. 89 module ........................................................................ 88 operation .................................................................... 88 overview..................................................................... 85 prescaler assignments ............................................... 89 read/write considerations......................................... 89 read/write in timer mode.......................................... 90 timing ................................................................... 88, 89 tmr0 status/control register (t0sta) ............................. 49 tmr0h ............................................................................... 44 tmr0l ................................................................................ 44 tmr1 ............................................................................ 26, 45 8-bit mode................................................................... 94 external clock input ................................................... 94 overview..................................................................... 85 timer mode .............................................................. 105 two 8-bit timer/counter mode ................................... 94 using with pwm ......................................................... 97 tmr1 overflow interrupt ............................................ 33, 280 tmr1cs ............................................................................. 91 tmr1ie............................................................................... 31 tmr1if....................................................................... 33, 280 tmr1on............................................................................. 92 tmr2 ............................................................................ 26, 45
1997 microchip technology inc. preliminary ds30264a-page 311 pic17c75x 8-bit mode ................................................................... 94 external clock input.................................................... 94 in timer mode........................................................... 105 two 8-bit timer/counter mode ................................... 94 using with pwm.......................................................... 97 tmr2 overflow interrupt............................................. 33, 280 tmr2cs ............................................................................. 91 tmr2ie ............................................................................... 31 tmr2if ....................................................................... 33, 280 tmr2on ............................................................................. 92 tmr3 example, reading from ........................................... 104 example, writing to.................................................. 104 external clock input.................................................. 104 in timer mode........................................................... 105 one capture and one period register mode........... 100 overview ..................................................................... 85 reading/writing ........................................................ 104 tmr3 interrupt flag bit, tmr3if ................................ 33, 280 tmr3cs ..................................................................... 91, 100 tmr3h.......................................................................... 26, 45 tmr3ie ............................................................................... 31 tmr3if ....................................................................... 33, 100 tmr3l .......................................................................... 26, 45 tmr3on ..................................................................... 92, 100 to ....................................................................... 48, 179, 180 transmit status and control register ............................... 107 tstfsz ............................................................................ 216 turning on 16-bit timer....................................................... 95 tx1ie .................................................................................. 31 tx1if .......................................................................... 33, 280 tx2ie .................................................................................. 32 tx2if .................................................................................. 34 txreg...................................................... 113, 117, 121, 122 txreg1........................................................................ 25, 44 txreg2........................................................................ 25, 45 txsta .............................................................. 116, 120, 122 txsta1 ........................................................................ 25, 44 txsta2 ........................................................................ 25, 45 u ua ..................................................................................... 124 update address, ua ......................................................... 124 upward compatibility ............................................................ 5 usart asynchronous master transmission......................... 114 asynchronous mode ................................................. 113 asynchronous receive ............................................. 115 asynchronous transmitter ........................................ 113 baud rate generator................................................ 110 synchronous master mode ....................................... 117 synchronous master reception................................ 119 synchronous master transmission........................... 117 synchronous slave mode ......................................... 121 synchronous slave transmit .................................... 121 usart1 receive interrupt ......................................... 33, 280 usart1 transmit interrupt ........................................ 33, 280 usart2 receive interrupt enable, rc2ie......................... 32 usart2 receive interrupt flag bit, rc2if ........................ 34 usart2 receive interrupt flag bit, tx2if ......................... 34 usart2 transmit interrupt enable, tx2ie ........................ 32 v v dd ........................................................................... 225, 226 w wake-up from sleep ....................................................... 180 wake-up from sleep through interrupt.......................... 180 watchdog timer ............................................................... 179 waveform for general call address sequence................ 139 waveforms external program memory access ..............................41 wcol ............................... 125, 144, 149, 152, 155, 157, 290 wcol status flag............................................................ 144 wdt ................................................................................. 179 clearing the wdt ..................................................... 179 normal timer............................................................ 179 period ....................................................................... 179 programming considerations ................................... 179 wdtps0........................................................................... 177 wdtps1........................................................................... 177 wreg .................................................................................44 write collision detect bit, wcol.............................. 125, 290 x xorlw ............................................................................ 217 xorwf ............................................................................ 217 z z ............................................................................. 9, 47, 274 zero (z)..................................................................................9
pic17c75x ds30264a-page 312 preliminary 1997 microchip technology inc. list of equations and examples example 3-1: signed math.................................................. 9 example 4-1: instruction pipeline flow ............................. 19 example 6-1: saving status and wreg in ram (simple) ...................................................... 37 example 6-2: saving status and wreg in ram (nested) ...................................................... 38 example 7-1: indirect addressing ..................................... 51 example 8-1: table write ................................................. 58 example 8-2: table read ................................................. 60 example 9-1: 8 x 8 unsigned multiply routine ................. 61 example 9-2: 8 x 8 signed multiply routine ..................... 61 equation 9-1: 16 x 16 unsigned multiplication algorithm .. 62 example 9-3: 16 x 16 unsigned multiply routine ............. 62 equation 9-2: 16 x 16 signed multiplication algorithm ...... 63 example 9-4: 16 x 16 signed multiply routine ................. 63 example 10-1: initializing porta....................................... 66 example 10-2: initializing portb....................................... 69 example 10-3: initializing portc ...................................... 72 example 10-4: initializing portd ...................................... 74 example 10-5: initializing porte....................................... 76 example 10-6: initializing portf ....................................... 78 example 10-7: initializing portg ...................................... 80 example 10-8: read modify write instructions on an i/o port ....................................................... 83 example 12-1: 16-bit read ................................................. 89 example 12-2: 16-bit write ................................................. 89 example 13-1: sequence to read capture registers ...... 103 example 13-2: writing to tmr3 ........................................ 104 example 13-3: reading from tmr3 ................................. 104 example 14-1: calculating baud rate error ..................... 110 example 15-1: loading the sspbuf (sspsr) register.. 127 equation 16-1: a/d minimum charging time (for c hold ) .............................................. 170 example 16-1: calculating the minimum required acquisition time ....................................... 171 example 16-2: a/d conversion......................................... 172 list of figures figure 3-1: pic17c75x block diagram ........................ 10 figure 4-1: oscillator / resonator start-up characteristics............................................ 15 figure 4-2: crystal or ceramic resonator operation (xt or lf osc configuration) .................... 16 figure 4-3: crystal operation, overtone crystals (xt osc configuration) ............................. 16 figure 4-4: external clock input operation (ec osc configuration) ............................................. 17 figure 4-5: external parallel resonant crystal oscillator circuit ......................................... 17 figure 4-6: external series resonant crystal oscillator circuit ......................................... 17 figure 4-7: rc oscillator mode .................................... 18 figure 4-8: clock/instruction cycle ............................... 19 figure 5-1: simplified block diagram of on-chip reset circuit ............................................... 21 figure 5-2: using on-chip por ................................... 22 figure 5-3: external power-on reset circuit (for slow v dd power-up) .......................... 22 figure 5-4: oscillator start-up time ............................. 22 figure 5-5: time-out sequence on power-up (mclr tied to v dd ) ................................... 24 figure 5-6: time-out sequence on power-up (mclr not tied to v dd )........................... 24 figure 5-7: slow rise time (mclr tied to v dd ) ......... 24 figure 5-8: external brown-out protection circuit 1 ..... 28 figure 5-9: external brown-out protection circuit 2 ..... 28 figure 5-10: brown-out situations .................................. 28 figure 6-1: interrupt logic ............................................ 29 figure 6-2: intsta register (address: 07h, unbanked) .................................................. 30 figure 6-3: pie1 register (address: 17h, bank 1) ....... 31 figure 6-4: pie2 register (address: 11h, bank 4) ....... 32 figure 6-5: pir1 register (address: 16h, bank 1) ....... 33 figure 6-6: pir2 register (address: 10h, bank 4) ....... 34 figure 6-7: int pin / t0cki pin interrupt timing .......... 36 figure 7-1: program memory map and stack............... 39 figure 7-2: memory map in different modes ................ 40 figure 7-3: external program memory access waveforms ................................................. 41 figure 7-4: typical external program memory connection diagram................................... 41 figure 7-5: pic17c75x register file map ................... 43 figure 7-6: alusta register (address: 04h, unbanked) .................................................. 47 figure 7-7: cpusta register (address: 06h, unbanked) .................................................. 48 figure 7-8: t0sta register (address: 05h, unbanked) .................................................. 49 figure 7-9: indirect addressing..................................... 50 figure 7-10: program counter operation ....................... 52 figure 7-11: program counter using the call and goto instructions ....................................... 52 figure 7-12: bsr operation ........................................... 53 figure 8-1: tlwt instruction operation ........................ 55 figure 8-2: tablwt instruction operation .................... 55 figure 8-3: tlrd instruction operation ........................ 56 figure 8-4: tablrd instruction operation .................... 56 figure 8-5: tablwt write timing (external memory)... 58 figure 8-6: consecutive tablwt write timing (external memory) ...................................... 59 figure 8-7: tablrd timing........................................... 60 figure 8-8: tablrd timing (consecutive tablrd instructions) ................................................ 60
1997 microchip technology inc. preliminary ds30264a-page 313 pic17c75x figure 10-1: ra0 and ra1 block diagram ..................... 65 figure 10-2: ra2 block diagram .................................... 66 figure 10-3: ra3 block diagram .................................... 66 figure 10-4: ra4 and ra5 block diagram ..................... 66 figure 10-5: block diagram of rb5:rb4 and rb1:rb0 port pins ..................................................... 68 figure 10-6: block diagram of rb3:rb2 port pins......... 69 figure 10-7: block diagram of rb6 port pin................... 70 figure 10-8: block diagram of rb7 port pin................... 70 figure 10-9: block diagram of rc7:rc0 port pins ........ 72 figure 10-10: block diagram of rd7:rd0 port pins (in i/o port mode) ....................................... 74 figure 10-11: block diagram of re2:re0 (in i/o port mode).......................................................... 76 figure 10-12: block diagram of re3/cap4 port pin ........ 77 figure 10-13: block diagram of rf7:rf0......................... 78 figure 10-14: block diagram of rg3:rg0........................ 80 figure 10-15: rg4 block diagram .................................... 81 figure 10-16: rg7:rg5 block diagram............................ 81 figure 10-17: successive i/o operation ........................... 83 figure 12-1: t0sta register (address: 05h, unbanked) .................................................. 87 figure 12-2: timer0 module block diagram ................... 88 figure 12-3: tmr0 timing with external clock (increment on falling edge) ....................... 88 figure 12-4: tmr0 timing: write high or low byte ....... 89 figure 12-5: tmr0 read/write in timer mode ............... 90 figure 13-1: tcon1 register (address: 16h, bank 3) ... 91 figure 13-2: tcon2 register (address: 17h, bank 3) ... 92 figure 13-3: tcon3 register (address: 16h, bank 7) ... 93 figure 13-4: timer1 and timer2 in two 8-bit timer/ counter mode ............................................. 94 figure 13-5: tmr2 and tmr1 in 16-bit timer/counter mode........................................................... 95 figure 13-6: simplified pwm block diagram .................. 97 figure 13-7: pwm output ............................................... 97 figure 13-8: timer3 with three capture and one period register block diagram................. 100 figure 13-9: timer3 with four captures block diagram .................................................... 102 figure 13-10: timer1, timer2, and timer3 operation (in counter mode)..................................... 104 figure 13-11: timer1, timer2, and timer3 operation (in timer mode) ........................................ 105 figure 14-1: txsta1 register (address: 15h, bank 0) txsta2 register (address: 15h, bank 4) 107 figure 14-2: rcsta1 register (address: 13h, bank 0) rcsta2 register (address: 13h, bank 4) 108 figure 14-3: usart transmit....................................... 109 figure 14-4: usart receive........................................ 109 figure 14-5: asynchronous master transmission......... 114 figure 14-6: asynchronous master transmission (back to back) .......................................... 114 figure 14-7: rx pin sampling scheme ........................ 115 figure 14-8: asynchronous reception.......................... 116 figure 14-9: synchronous transmission ...................... 118 figure 14-10: synchronous transmission (through txen) ....................................... 118 figure 14-11: synchronous reception (master mode, sren)....................................................... 119 figure 15-1: spi mode block diagram.......................... 123 figure 15-2: i 2 c slave mode block diagram ................ 123 figure 15-3: i 2 c master mode block diagram .............. 123 figure 15-4: sspstat: sync serial port status register (address: 13h, bank 6) ............. 124 figure 15-5: sspcon1: sync serial port control register1 (address 11h, bank 6)............ 125 figure 15-6: sspcon2: sync serial port control register2 (address 12h, bank 6)........... 126 figure 15-7: ssp block diagram (spi mode)............... 128 figure 15-8: spi mode timing (master mode) ............. 129 figure 15-9: spi master/slave connection .................. 130 figure 15-10: slave synchronization timing .................. 131 figure 15-11: spi mode timing (slave mode with cke = 0)................................................... 132 figure 15-12: spi mode timing (slave mode with cke = 1)................................................... 133 figure 15-13: ssp block diagram (i 2 c mode)................................................ 134 figure 15-14: i 2 c master mode block diagram.............. 134 figure 15-15: i 2 c waveforms for reception (7-bit address).......................................... 136 figure 15-16: i 2 c waveforms for transmission (7-bit address).......................................... 136 figure 15-17: i2c slave-transmitter (10-bit address).... 137 figure 15-18: i2c slave-receiver (10-bit address)........ 138 figure 15-19: general call address sequence (7 or 10-bit mode)..................................... 139 figure 15-20: ssp block diagram (i 2 c master mode) ... 141 figure 15-21: baud rate generator block diagram....... 143 figure 15-22: baud rate generator timing with clock arbitration ....................................... 143 figure 15-23: first start bit timing................................. 144 figure 15-24: start condition flowchart ........................ 145 figure 15-25: repeat start condition timing ................. 146 figure 15-26: restart condition flowchart (page 1)...... 147 figure 15-27: restart condition flowchart (page 2)...... 148 figure 15-28: master transmit flowchart ...................... 150 figure 15-29: i 2 c master mode timing (transmission, 7 or 10-bit address).................................. 151 figure 15-30: master receiver flowchart...................... 153 figure 15-31: i 2 c master mode timing (reception 7-bit address)........................................... 154 figure 15-32: acknowledge sequence timing ............... 155 figure 15-33: acknowledge flowchart........................... 156 figure 15-34: stop condition receive or transmit mode ........................................................ 157 figure 15-35: stop condition flowchart ........................ 158 figure 15-36: clock arbitration timing in master transmit mode ......................................... 159 figure 15-37: bus collision timing for transmit and acknowledge ............................................ 160 figure 15-38: bus collision during start condition (sda only) ................................................ 161 figure 15-39: bus collision during start condition (scl = 0) .................................................. 162 figure 15-40: brg reset due to sda collision during start condition.......................................... 162 figure 15-41: bus collision during a restart condition (case 1).................................................... 163 figure 15-42: bus collision during restart condition (case 2).................................................... 163 figure 15-43: bus collision during a stop condition (case 1).................................................... 164 figure 15-44: bus collision during a stop condition (case 2).................................................... 164 figure 15-45: sample device configuration for i 2 c bus .. 165 figure 16-1: adcon0 register (address: 14h, bank 5) ..................................................... 167 figure 16-2: adcon1 register (address 15h, bank 5) ..................................................... 168
pic17c75x ds30264a-page 314 preliminary 1997 microchip technology inc. figure 16-3: a/d block diagram ................................... 169 figure 16-4: analog input model................................... 170 figure 16-5: a/d result justification ............................. 173 figure 16-6: a/d transfer function............................... 174 figure 16-7: flowchart of a/d operation ...................... 175 figure 17-1: configuration words ................................. 177 figure 17-2: watchdog timer block diagram ............... 179 figure 17-3: wake-up from sleep through interrupt ... 180 figure 17-4: typical in-circuit serial programming connection................................................ 182 figure 18-1: general format for instructions ................ 184 figure 18-2: q cycle activity......................................... 185 figure 20-1: parameter measurement information ....... 231 figure 20-2: external clock timing ............................... 232 figure 20-3: clkout and i/o timing........................... 233 figure 20-4: reset, watchdog timer, oscillator start-up timer, power-up timer, and brown-out reset timing............................................. 234 figure 20-5: timer0 external clock timings ................. 235 figure 20-6: timer1, timer2, and timer3 external clock timings ........................................... 235 figure 20-7: capture timings ....................................... 236 figure 20-8: pwm timings ........................................... 236 figure 20-9: spi master mode timing (cke = 0) ......... 237 figure 20-10: spi master mode timing (cke = 1) ......... 238 figure 20-11: spi slave mode timing (cke = 0) ........... 239 figure 20-12: spi slave mode timing (cke = 1) ........... 240 figure 20-13: i 2 c bus start/stop bits timing.................. 241 figure 20-14: i 2 c bus data timing ................................. 242 figure 20-15: usart synchronous transmission (master/slave) timing............................... 244 figure 20-16: usart synchronous receive (master/slave) timing............................... 244 figure 20-17: a/d conversion timing ............................. 246 figure 20-18: memory interface write timing................. 247 figure 20-19: memory interface read timing ................ 248 figure 21-1: typical rc oscillator frequency vs. temperature ............................................. 249 figure 21-2: typical rc oscillator frequency vs. v dd . 250 figure 21-3: typical rc oscillator frequency vs. v dd . 250 figure 21-4: typical rc oscillator frequency vs. v dd . 251 figure 21-5: transconductance (gm) of lf oscillator vs. v dd ...................................................... 252 figure 21-6: transconductance (gm) of xt oscillator vs. v dd ...................................................... 252 figure 21-7: typical i dd vs. frequency (external clock 25 c)............................................... 253 figure 21-8: maximum i dd vs. frequency (external clock 125 c to -40 c) ........................................ 253 figure 21-9: typical i pd vs. v dd watchdog disabled 25 c.......................................................... 254 figure 21-10: maximum i pd vs. v dd watchdog disabled .................................................... 254 figure 21-11: typical i pd vs. v dd watchdog enabled 25 c.......................................................... 255 figure 21-12: maximum i pd vs. v dd watchdog enabled..................................................... 255 figure 21-13: wdt timer time-out period vs. v dd ....... 256 figure 21-14: i oh vs. v oh , v dd = 3v .............................. 256 figure 21-15: i oh vs. v oh , v dd = 5v .............................. 257 figure 21-16: i ol vs. v ol , v dd = 3v ............................... 257 figure 21-17: i ol vs. v ol , v dd = 5v ............................... 258 figure 21-18: v th (input threshold voltage) of i/o pins (ttl) vs . v dd ............................................ 258 figure 21-19: v ih , v il of i/o pins (schmitt trigger) vs . v dd ........................................................... 259 figure 21-20: v th (input threshold voltage) of osc1 input (in xt and lf modes) vs. v dd ....... 259 figure e-1: start and stop conditions ........................ 267 figure e-2: 7-bit address format ................................ 268 figure e-3: i 2 c 10-bit address format........................ 268 figure e-4: slave-receiver acknowledge .................... 268 figure e-5: data transfer wait state .......................... 268 figure e-6: master-transmitter sequence ................... 269 figure e-7: master-receiver sequence ....................... 269 figure e-8: combined format..................................... 269 figure e-9: multi-master arbitration (two masters) .......................................... 270 figure e-10: clock synchronization .............................. 270 figure e-11: i 2 c bus start/stop bits timing specification ............................................. 271 figure e-12: i 2 c bus data timing specification .......... 272 figure f-1: pic17c75x register file map ................. 273 figure f-2: alusta register (address: 04h, unbanked) ................................................ 274 figure f-3: t0sta register (address: 05h, unbanked) ................................................ 275 figure f-4: cpusta register (address: 06h, unbanked) ................................................ 276 figure f-5: intsta register (address: 07h, unbanked) ................................................ 277 figure f-6: pie1 register (address: 17h, bank 1) ..... 278 figure f-7: pie2 register (address: 11h, bank 4) ..... 279 figure f-8: pir1 register (address: 16h, bank 1) ..... 280 figure f-9: pir2 register (address: 10h, bank 4) ..... 281 figure f-10: txsta1 register (address: 15h, bank 0) txsta2 register (address: 15h, bank 4) ..................................................... 282 figure f-11: rcsta1 register (address: 13h, bank 0) rcsta2 register (address: 13h, bank 4) ..................................................... 283 figure f-12: tcon1 register (address: 16h, bank 3) ..................................................... 284 figure f-13: tcon2 register (address: 17h, bank 3) ..................................................... 285 figure f-14: tcon3 register (address: 16h, bank 7) ..................................................... 286 figure f-15: adcon0 register (address: 14h, bank 5) ..................................................... 287 figure f-16: adcon1 register (address 15h, bank 5) ..................................................... 288 figure f-17: sspstat: sync serial port status register (address: 13h, bank 6)............. 289 figure f-18: sspcon1: sync serial port control register (address 11h, bank 6).............. 290 figure f-19: sspcon2: sync serial port control register2 (address 12h, bank 6)........... 291
1997 microchip technology inc. preliminary ds30264a-page 315 pic17c75x list of tables table 1-1: pic17cxxx family of devices..................... 6 table 2-1: device memory varieties.............................. 7 table 3-1: pinout descriptions..................................... 11 table 4-1: capacitor selection for ceramic resonators ................................................. 16 table 4-2: capacitor selection for crystal oscillator ... 16 table 5-1: time-out in various situations ................... 23 table 5-2: status bits and their significance .......... 23 table 5-3: reset condition for the program counter and the cpusta register.......................... 23 table 5-4: initialization conditions for special function registers...................................... 25 table 6-1: interrupt vectors/priorities .......................... 35 table 7-1: mode memory access ................................ 40 table 7-2: eprom memory access time ordering suffix........................................................... 41 table 7-3: special function registers ......................... 44 table 8-1: interrupt - table write interaction ............... 57 table 9-1: performance comparison........................... 61 table 10-1: porta functions....................................... 67 table 10-2: registers/bits associated with porta ...... 67 table 10-3: portb functions....................................... 71 table 10-4: registers/bits associated with portb ...... 71 table 10-5: portc functions....................................... 73 table 10-6: registers/bits associated with portc ...... 73 table 10-7: portd functions....................................... 75 table 10-8: registers/bits associated with portd ...... 75 table 10-9: porte functions....................................... 77 table 10-10: registers/bits associated with porte ...... 77 table 10-11: portf functions ....................................... 79 table 10-12: registers/bits associated with portf ...... 79 table 10-13: portg functions ...................................... 82 table 10-14: registers/bits associated with portg ..... 82 table 12-1: registers/bits associated with timer0 ....... 90 table 13-1: time-base function / resource requirements ............................................. 91 table 13-2: turning on 16-bit timer.............................. 95 table 13-3: summary of timer1 and timer2 registers..................................................... 96 table 13-4: pwm frequency vs. resolution at 33 mhz ................................................... 98 table 13-5: registers/bits associated with pwm.......... 99 table 13-6: registers associated with capture........... 103 table 14-1: usart module generic names............... 107 table 14-2: baud rate formula................................... 110 table 14-3: registers associated with baud rate generator.................................................. 110 table 14-4: baud rates for synchronous mode.......... 111 table 14-5: baud rates for asynchronous mode ........ 112 table 14-6: registers associated with asynchronous transmission..................... 114 table 14-7: registers associated with asynchronous reception.......................... 116 table 14-8: registers associated with synchronous master transmission ................................ 118 table 14-9: registers associated with synchronous master reception...................................... 120 table 14-10: registers associated with synchronous slave transmission .................................. 122 table 14-11: registers associated with synchronous slave reception........................................ 122 table 15-1: registers associated with spi operation .................................................. 133 table 15-2: data transfer received byte actions....... 135 table 15-3: registers associated with i 2 c operation.. 140 table 16-1: t ad vs. device operating frequencies (standard devices (c)) ............................. 171 table 16-2: t ad vs. device operating frequencies (extended voltage devices (lc)) ............. 171 table 16-3: registers/bits associated with a/d........... 175 table 17-1: configuration locations............................ 178 table 17-2: registers/bits associated with the watchdog timer ....................................... 179 table 17-3: isp interface pins..................................... 182 table 18-1: opcode field descriptions ....................... 183 table 18-2: pic17cxxx instruction set...................... 186 table 19-1: development tools from microchip............ 222 table 20-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) ......... 224 table 20-2: external clock timing requirements ....... 232 table 20-3: clkout and i/o timing requirements... 233 table 20-4: reset, watchdog timer, oscillator start-up timer, power-up timer, and brown-out reset requirements ............... 234 table 20-5: timer0 external clock requirements....... 235 table 20-6: timer1, timer2, and timer3 external clock requirements ................................. 235 table 20-7: capture requirements ............................. 236 table 20-8: pwm requirements ................................. 236 table 20-9: spi mode requirements (master mode, cke = 0)................................................... 237 table 20-10: spi mode requirements (master mode, cke = 1)................................................... 238 table 20-11: spi mode requirements (slave mode timing (cke = 0)...................................... 239 table 20-12: spi mode requirements (slave mode, cke = 1)................................................... 240 table 20-13: i 2 c bus start/stop bits requirements...... 241 table 20-14: i 2 c bus data requirements ..................... 243 table 20-15: usart synchronous transmission requirements ........................................... 244 table 20-16: usart synchronous receive requirements ........................................... 244 table 20-17: a/d converter characteristics: pic17lc752/756-08 (commercial, industrial) pic17c752/756-25 (commercial, industrial) pic17c752/756-33 (commercial, industrial).................................................. 245 table 20-18: a/d conversion requirements................. 246 table 20-19: memory interface write requirements..... 247 table 20-20: memory interface read requirements...... 248 table 21-1: pin capacitance per package type ......... 249 table 21-2: rc oscillator frequencies ....................... 251 table e-1: i 2 c bus terminology ................................ 267 table e-2: i 2 c bus start/stop bits timing specification... 271 table e-3: i 2 c bus data timing specification .......... 272 table g-1: pin compatible devices ........................... 302
pic17c75x ds30264a-page 316 preliminary 1997 microchip technology inc. notes:
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pic17c75x ds30264a-page 318 1997 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (602) 786-7578. please list the following information, and use this outline to provide us with your comments about this data sheet. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you tnd the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds30264a pic17c75x
1997 microchip technology inc. preliminary ds30264a-page 319 pic17c75x pic17c75x product identit cation system to order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales oftces. sales and support products supported by a preliminary data sheet may possibly have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. the microchip website at www.microchip.com 2. your local microchip sales oftce (see following page) 3. the microchip corporate literature center u.s. fax: (602) 786-7277 4. the microchip?s bulletin board, via your local compuserve number (compuserve membership not required). please specify which device, revision of silicon and data sheet (include literature #) you are using. for latest version information and upgrade kits for microchip development tools, please call 1-800-755-2345 or 1-602-786-7302. pattern: qtp, sqtp, rom code (factory specited) or special requirements. blank for otp and windowed devices package: p = pdip jw = windowed cerdip p = pdip (600 mil) pq = mqfp pt = tqfp l = plcc temperature e = 0?c to +70?c range: i = e40?c to +85?c frequency 08 = 8 mhz range: 25 = 25 mhz 33 = 33 mhz device: pic17c756 : standard v dd range pic17c756t : (tape and reel) pic17lc756 : extended v dd range part no. e xx x /xx xxx examples a) pic17c756 e 25/p commercial temp., pdip package, 25 mhz, normal v dd limits b) pic17lc756e08/pt commercial temp., tqfp package, 8mhz, extended v dd limits c) pic17c756e33i/p industrial temp., pdip package, 33 mhz, normal v dd limits
? 2002 microchip technology inc. information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip?s products as critical com- ponents in life support systems is not authorized except with express written approval by microchip. no licenses are con- veyed, implicitly or otherwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, filterlab, k ee l oq , microid, mplab, pic, picmicro, picmaster, picstart, pro mate, seeval and the embedded control solutions company are registered trademarks of microchip tech- nology incorporated in the u.s.a. and other countries. dspic, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, mxdev, picc, picdem, picdem.net, rfpic, select mode and total endurance are trademarks of microchip technology incorporated in the u.s.a. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2002, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified. note the following details of the code protection feature on picmicro ? mcus. the picmicro family meets the specifications contained in the microchip data sheet. microchip believes that its family of picmicro microcontrollers is one of the most secure products of its kind on the market to day, when used in the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowl - edge, require using the picmicro microcontroller in a manner outside the operating specifications contained in the data sheet. the person doing so may be engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ? unbreakable ? . code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our product. if you have any further questions about this matter, please contact the local sales office nearest to you.
? 2002 microchip technology inc. m americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: http://www.microchip.com rocky mountain 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7966 fax: 480-792-7456 atlanta 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3848 fax: 978-692-3821 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 kokomo 2767 s. albright road kokomo, indiana 46902 tel: 765-864-8360 fax: 765-864-8387 los angeles 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 new york 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia microchip technology australia pty ltd suite 22, 41 rawson street epping 2121, nsw australia tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing microchip technology consulting (shanghai) co., ltd., beijing liaison office unit 915 bei hai wan tai bldg. no. 6 chaoyangmen beidajie beijing, 100027, no. china tel: 86-10-85282100 fax: 86-10-85282104 china - chengdu microchip technology consulting (shanghai) co., ltd., chengdu liaison office rm. 2401, 24th floor, ming xing financial tower no. 88 tidu street chengdu 610016, china tel: 86-28-6766200 fax: 86-28-6766599 china - fuzhou microchip technology consulting (shanghai) co., ltd., fuzhou liaison office unit 28f, world trade plaza no. 71 wusi road fuzhou 350001, china tel: 86-591-7503506 fax: 86-591-7503521 china - shanghai microchip technology consulting (shanghai) co., ltd. room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 china - shenzhen microchip technology consulting (shanghai) co., ltd., shenzhen liaison office rm. 1315, 13/f, shenzhen kerry centre, renminnan lu shenzhen 518001, china tel: 86-755-2350361 fax: 86-755-2366086 hong kong microchip technology hongkong ltd. unit 901-6, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 india microchip technology inc. india liaison office divyasree chambers 1 floor, wing a (a3/a4) no. 11, o?shaugnessey road bangalore, 560 025, india tel: 91-80-2290061 fax: 91-80-2290062 japan microchip technology japan k.k. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea 135-882 tel: 82-2-554-7200 fax: 82-2-558-5934 singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore, 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan microchip technology taiwan 11f-3, no. 207 tung hua north road taipei, 105, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe denmark microchip technology nordic aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france microchip technology sarl parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany microchip technology gmbh gustav-heinemann ring 125 d-81739 munich, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5869 fax: 44-118 921-5820 01/18/02 w orldwide s ales and s ervice

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