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i-cube, inc. [rev. 1.2] 8/8/01 1 ocx481 crosspoint switch advanced mini data sheet features description the ocx481 sram-based device is a non-blocking 24 x 24 digital crosspoint switch capable of data rates of 1.6 gigabits per second per port. the i/o ports are fixed as either input or output ports. the input and output ports operate in flow-through (asynchronous) mode. the patented activearray provides greater density, superior performance, and greater flexibility compared to a traditional n:1 multiplexer architecture. the ocx? devices support various operating modes covering one input to one output at a time as well as one input to many outputs, plus a special broadcast mode to program one input to all outputs while maintaining maximum data rates. in all modes data integrity and connections are maintained on all unchanged data paths. the rapidconfigure parallel interface allows fast configuration of the output buffers and the switch matrix. readback is supported for device test and verification purposes. a functional block diagram of the ocx481 is shown in figure 1. applications figure 1 ocx481 functional block diagram ? 1.6 gb/s port data bandwidth, >38gb/s aggregate bandwidth low power cmos, 2.5v and 3.3v power supply sram-based, in-system programmable 48 configurable i/o ports ? 24 dedicated differential input ports ? 24 dedicated differential output ports ? supports lvpecl and lvds i/o ? lvttl control interface ? output enable control for all outputs non-blocking switch matrix ? patented activearray ? matrix for superior performance ? double-buffered configuration ram cells for simultaneous global updates ? implieddisconnect ? function for single cycle disconnect/ connect full broadcast and multicast capability ? one-to-one and one-to-many connections ? special broadcast mode routes one input to all outputs at maximum data rate low jitter and signal skew low duty cycle distortion rapidconfigure ? parallel interface for configuration and readback serial programming interface for configuration 172 bga package with 1.27mm ball spacing integrated termination resistors sonet/sdh and dwdm digital cross-connects system backplanes and interconnects high speed test equipment atm switch cores video switching input buffers 24 x 24 crosspoint switch matrix oe# hw_rst# update# out[23:0] 48 configuration and programming logic rca[6:0] rcb[6:0] rci[3:0] rc_clk# rc_en# 4 7 7 rapidconfigure signals in[23:0] 48 output buffers rco[2:0] 3
ocx481 crosspoint switch ? advanced mini data sheet 2 [rev. 1.2] 8/8/01 i-cube, inc. (this page intentionally left blank)
i-cube, inc. [rev. 1.2] 8/8/01 3 ocx481 crosspoint switch ? advanced mini data sheet contents 1. introduction ................................................................................................................. .......... 7 1.1 input and output buffers.................................................................................................... .. 8 1.1.1 input and output port function mode ........................................................................... 8 1.1.2 broadcast mode ............................................................................................................ .8 1.2 output control signals...................................................................................................... ... 9 1.3 rapidconfigure interface .................................................................................................... .9 1.3.1 rapidconfigure programming instructions.................................................................... 9 1.4 implieddisconnect ........................................................................................................... ...11 1.5 device reset options ........................................................................................................ .12 2. pin description .............................................................................................................. .......13 3. differential i/o standards ................................................................................................... 14 3.1 lvpecl ...................................................................................................................... ....... 14 3.2 lvds ........................................................................................................................ ......... 14 4. electrical specifications .................................................................................................... ...15 4.1 absolute maximum ratings .............................................................................................. 15 4.2 recommended operating conditions ................................................................................ 15 4.3 pin capacitance ............................................................................................................ ..... 15 4.4 dc electrical specifications .............................................................................................. 16 4.5 lvpecl ac electrical specifications ............................................................................... 17 4.6 timing diagrams............................................................................................................. ... 18 5. power consumption ............................................................................................................ .21 5.1 power for lvpecl i/o ..................................................................................................... 21 6. component availability and ordering information ..........................................................22 7. glossary..................................................................................................................... ............22 8. product status definition .................................................................................................... .24
ocx481 crosspoint switch ? advanced mini data sheet 4 [rev. 1.2] 8/8/01 i-cube, inc.
i-cube, inc. [rev. 1.2] 8/8/01 5 ocx481 crosspoint switch ? advanced mini data sheet figures figure 1 ocx481 functional block diagram ......................................................................................... ........... 1 figure 2 ocx481 switch matrix .................................................................................................... .................... 7 figure 3 input and output buffer configuration ................................................................................... ............. 8 figure 4 ocx481 operating in lvpecl mode ......................................................................................... ..... 14 figure 5 flow-through mode timing ................................................................................................ .............. 18 figure 6 output enable timing .................................................................................................... .................... 18 figure 7 duty cycle distortion................................................................................................... ...................... 18 figure 8 rapidconfigure write cycle .............................................................................................. ................ 19 figure 9 rapidconfigure read cycle ............................................................................................... ................ 19 figure 10 typical performance.................................................................................................... ....................... 20 figure 11 power consumption diagram for the ocx481 using lvpecl........................................................ 21
ocx481 crosspoint switch ? advanced mini data sheet 6 [rev. 1.2] 8/8/01 i-cube, inc. tables table 1 summary for programmable i/o attributes for ocx481................................................................. 8 table 2 rapidconfigure programming instructions .................................................................................. .... 9 table 3 rco[2:0] readback pin assignment......................................................................................... ..... 11 table 4 programming an output buffer using rapidconfigure .................................................................. 11 table 5 device reset options ..................................................................................................... ................. 12 table 6 ocx481 pin description................................................................................................... .............. 13 table 7 absolute maximum ratings................................................................................................. ........... 15 table 8 recommended operating conditions......................................................................................... ..... 15 table 9 pin capacitance .......................................................................................................... ..................... 15 table 10 lvttl dc electrical specifications...................................................................................... ........ 16 table 11 lvpecl dc electrical specifications ..................................................................................... ...... 16 table 12 lvpecl ac electrical specifications ..................................................................................... ...... 17
ocx481 crosspoint switch ? advanced mini data sheet i-cube, inc. [rev. 1.2] 8/8/01 7 1. introduction the ocx481 is a differential crosspoint-switching device. the main functional block of the device is a switch matrix as shown in figure 1. the switch matrix is a x-y structure supporting an input-to-output data flow. figure 2 shows a conceptual view of the switch matrix with inputs connected to the horizontal trace and outputs to the vertical trace. connections between vertical and horizontal lines are implemented with a proprietary high- performance buffering circuit. signal path delays through the switch matrix are very well balanced, resulting in predictable and uniform pin-to-pin delays. note ? for the purpose of clarity, the logic diagrams within this data sheet are conceptual representations only and do not show actual circuit implementation. figure 2 ocx481 switch matrix the active sram cells are responsible for establishing connections in the switch matrix by turning on the interconnect circuit, while the loading sram cell can be used to store a second configuration that can be transferred to the active sram cell at a later time. the two sram cells are arranged so that a double buffered scheme can be employed. through the use of an internal signal (generated automatically during a programming cycle) it is possible to store a second configuration map in the loading sram while the active sram maintains its present connection status. when the update# signal is asserted low, the contents of the loading sram cell are transferred to the active sram cell and the switch matrix connection is either made or broken. the update# signal can be used to control when the switch matrix is reconfigured. for instance, as long as the update# signal is asserted high, the loading sram cells for the entire switch matrix could be changed without affecting the current configuration of the switch. when the update# signal is asserted low, the entire switch matrix would be reconfigured simultaneously. if the update# signal is asserted continuously, all crosspoint programming commands (generated by rapidconfigure or serial programming cycles) will take effect immediately, since the loading sram cell ? s contents will be transferred directly to the active sram cell. update# active sram cell loading sram cell data proprietary high-performance buffering circuit
ocx481 crosspoint switch ? advanced mini data sheet 8 [rev. 1.2] 8/8/01 i-cube, inc. 1.1 input and output buffers all of the i/o buffers are differential with flow-through mode. figure 3 shows the basic block diagram of the input and output blocks with the sources for the output control signals (oe#). the control signals are explained in more details in the following sections. figure 3 input and output buffer configuration 1.1.1 input and output port function mode the following legend describes the various modes of the input and output ports and the specification used by the ocxpro ? software. legend: ax ? switch matrix signal px ? port signal oe# ? output enable (# means ? active low ? ) 1.1.2 broadcast mode the ocx481 has a special broadcast mode which connects any input to all outputs without performance degradation. the input is selected using rapidconfigure or serial interface and disconnects all other inputs. the global update pin (update#) must be held high during broadcast mode. asserting the update# pin returns the array to the previous program condition. table 1 summary for programmable i/o attributes for ocx481 symbol i/o port function mnemonic input ? the external signal is buffered from the input port pin to the corresponding switch matrix line. in output ? the internal signal is buffered from the corresponding switch matrix line to the output port pin. in this mode an optional output enable (oe#) can be selected. the default state is logic high with enable set to on. op no connect ? in this mode, the output port pin is isolated from the switch matrix. nc switch matrix input output oe# px ax oe# px ax ax px
ocx481 crosspoint switch ? advanced mini data sheet i-cube, inc. [rev. 1.2] 8/8/01 9 1.2 output control signals every output port of the ocx481 has a global output enable signal (oe#). all output buffers have output enables that have programmable polarity and are individually configurable. additionally each output can be permanently enabled (always on) or disabled (always off) which is useful for applications which need to tri-state outputs (for example when using multiple chips in expansion mode) or for power saving in designs that do not need to use all the outputs available. two control bits are used to control the function of the output enable. 1.3 rapidconfigure interface rapidconfigure (rc) is a 23 signal parallel interface that is used to program the ocx481 device. the 23 pins are allocated as follows: rca[6:0] = rapidconfigure address a. rca are input pins. rcb[6:0] = rapidconfigure address b. rcb are input pins. rci[3:0] = rapidconfigure instruction bits rco[2:0] = rapidconfigure readback. rco are output pins. rc_clk# = rapidconfigure clock rc_en# = rapidconfigure cycle enable (state is sensed on negative edge of clock) 1.3.1 rapidconfigure programming instructions the rc interface supports both write and read types of operations: 1. write operations (reset crosspoint and input or output buffer (iob), configure an output buffer, connect/disconnect crosspoint) 2. read operations (output buffer and crosspoint configuration read). table 2 rapidconfigure programming instructions rci[3:0] rca[6:0] rcb[6:0] rco[2:0] instruction description 0000 reserved 0001 reserved 0010 x x reset crosspoint array reset, along with an update operation (update# pin or update command) resets the entire crosspoint array to no connect. all output buffers remain unchanged by this operation. 0011 x input port address set array to broadcast mode connects the input selected by rcb[6:0] to all output ports and disconnects all other inputs. the global update (update#) pin must be held high during broadcast mode. activating the global update pin returns the array to the previous program condition. 0100 output port address data configure an output buffer program an output buffer specified by rca[6:0]. see table 4 for rcb[6:0] bit assignment and buffer functionality.
ocx481 crosspoint switch ? advanced mini data sheet 10 [rev. 1.2] 8/8/01 i-cube, inc. note ? x = don ? t care. 0101 readback crosspoint, output buffer status this is a two-cycle instruction. cycle 1 output port address input port address x specify the crosspoint connect status at output location specified by rca[6:0] to the input location specified by rcb[6:0]. cycle 2 x x output data readback (using rco[2:0]) the status of the input buffer specified in cycle 1 by rca[6:0], the output buffer specified in cycle 1 by rco[2:0] and the crosspoint connect status. see table 3 for rco[2:0] readback pin assignment. 0110 x x update program the global update function without the use of the update# pin. 0111 x input port address disconnect input disconnect the crosspoint cells of the input row location specified by rca[6:0]. 1000 output port address input port address disconnect input and output disconnect the crosspoint cell at the output location specified by rca[6:0] to the input location specified by rcb[6:0]. all other connections from the source input address or to the same output address remain the same as before. 1001 output port address input port address connect, with implieddisconnect connect the crosspoint cell at the output location specified by rca[6:0] to the input location specified by rcb[6:0]. all other connections from the same input address or to the same output address are set to no connect (nc). 1010 output port address input port address connect, without implieddisconnect connect the crosspoint cell at the output location specified by rca[6:0] to the input location specified by rcb[6:0]. all other connections to the same output address are set to ? no connect ? while all other connections from the same input address remain the same as before. 1011 reserved 1100 reserved 1101 x x reset all reset the switch matrix to no connects (nc). update is forced internally. sets the output buffer to flow-through mode with output enabled. 1110 reserved 1111 reserved table 2 rapidconfigure programming instructions (continued) rci[3:0] rca[6:0] rcb[6:0] rco[2:0] instruction description
ocx481 crosspoint switch ? advanced mini data sheet i-cube, inc. [rev. 1.2] 8/8/01 11 1.4 implieddisconnect implieddisconnect is a feature that provides the ability to make fast switch connection changes. when using the normal ? connect ? command, all other connection to the specified output are set to ? no connect ? . however, the specified input remains connected to any other outputs to which it was connected before. the ? connect with implieddisconnect ? commands allow the user to disconnect the specified input from all other outputs as well. this enables the user to make a complete connection change in one rapidconfigure cycle. table 3 rco[2:0] readback pin assignment rco[2:0] readback location signal/function o2 crosspoint connection status: 0 = no connection (nc) ? (default state at reset) 1 = connected o1, o0 0,0 0,1 1,0 1,1 output buffer output enable: output enabled (on) ? this is the default state at reset output disabled (off) output controlled by oe (active high) output controlled by oe# (active low) table 4 programming an output buffer using rapidconfigure rcb[6:0] signal/function b6, b5, b4, b3, b2 don ? t care b1, b0 0,0 0,1 1,0 1,1 output enable: output enabled (on) ? this is the default state at reset output disabled (off) output controlled by oe (active high) output controlled by oe# (active low)
ocx481 crosspoint switch ? advanced mini data sheet 12 [rev. 1.2] 8/8/01 i-cube, inc. 1.5 device reset options the power-on reset, rapidconfigure reset, and hardware reset will program the output buffers to flow- through mode (with global clock selected), and output enabled (on). the hardware reset pin can be done accomplished through the hw_rst# pin (active low). rc reset can be accomplished by applying the rc instruction 1101 to the rci[3:0] pins. table 5 device reset options programming interface reset method output ports switch matrix rce mode control tap hardware reset power-on reset op nc 1 (rc enabled) tlr 1 1. tlr = test logic reset state. hw_rst# (low pulse) op nc 1 (rc enabled) tlr rapidconfigure reset 1. device reset (instruction 1101) op nc 1 (rc enabled) unchanged 2. reset crosspoint array (instruction 0010) unchanged nc unchanged unchanged
ocx481 crosspoint switch ? advanced mini data sheet i-cube, inc. [rev. 1.2] 8/8/01 13 2. pin description notes : 1. dedicated differential input buffers can receive both lvpecl and lvds voltage levels using 3.3v supply. 2. v dd .pad is 3.3v for lvpecl outputs. 3. the lvttl control, serial pins, and differential input ports are 3.3v ? they are not 5v tolerant. table 6 ocx481 pin description pin name # of pins type description inp[23:0] 24 input non-inverting differential input signals inn[23:0] 24 input inverting differential input signals outp[23:0] 24 output non-inverting differential input signals outn[23:0] 24 output inverting differential input signals oe# 1 input global output enable hw_rst# 1 input hardware reset update# 1 input global update rc pins rca[6:0] 7 input rapidconfigure address a rcb[6:0] 7 input rapidconfigure address b rco[2:0] 3 output rapidconfigure readback rci[3:0] 4 input rapidconfigure instruction bits rc_clk# 1 input rapidconfigure clock rc_en# 1 input rapidconfigure cycle enable power and ground pins v dd .core 12 2.5v power core voltage v dd .pad (2) 8 3.3v power differential output buffer voltage v dd .in (1, 3) 8 3.3v power lvttl control pins voltage and differential input buffer voltage v ss 38 ground ground nc 3 no connect no connect
ocx481 crosspoint switch ? advanced mini data sheet 14 [rev. 1.2] 8/8/01 i-cube, inc. 3. differential i/o standards the ocx481 support the two most popular differential signaling standards: low voltage positive emitter coupled logic (lvpecl) and low voltage differential signaling (lvds). lvpecl is commonly used in video switching applications or those designs requiring transmission of high- speed clock signals. this is the default i/o supported by the ocx481 device. lvds is typically used in communication systems as high speed, low noise point-to-point links. the ocx481 conforms to the ansi/tia/eia-644 standard covering electrical specifications for output drivers and receiver inputs. 3.1 lvpecl lvpecl is a differential signaling standard that specifies two pins per input or output. the voltage swing between these two signal lines is approximately 850 mv. the use of a reference voltage or a board termination voltage is not required. transmitting and receiving circuits for lvpecl are shown in figure 4 with termination resistors integrated on-chip, thus, removing the need for any external resistors. integrated output attenuation resistors produce the required lvpecl output swing while providing a 100 ohm output impedance to minimize return reflections. figure 4 ocx481 operating in lvpecl mode 3.2 lvds lvds is a differential signaling standard that requires the use of two pins per input or output. it requires that one data bit is carried through two signal lines. as with all differential signaling standards, lvds has an inherent noise immunity over single-ended standards. the voltage swing between two signal lines is approximately 350mv. the use of a reference voltage or a board termination voltage is not required. note ? it is possible to operate the ocx481 device with v dd. pad = 2.5v that will allow the outputs to closely approximate ? true lvds ? levels. refer to the application note ? operating the ocx1601 in lvds applications ? for further details. ocx481 device z 0 =50 ? z 0 =50 ? inp 110 r t inn ? + switch matrix z 0 =50 ? z 0 =50 ? outp outn v dd.pad = 3.3v from lvpecl driver to receiver
ocx481 crosspoint switch ? advanced mini data sheet i-cube, inc. [rev. 1.2] 8/8/01 15 4. electrical specifications 4.1 absolute maximum ratings 4.2 recommended operating conditions 4.3 pin capacitance 1. exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2. a maximum undershoot of 2v for a maximum duration of 20 ns is acceptable. overshoot to 3.6v is acceptable. 3. all inputs are 3.3v tolerant with the v dd pin at 2.5v or 3.3v. 4. note that min and max values for v dd for differential outputs are i/o standard dependent. 5. capacitance measured at 25 c. sample tested only. 6. measured using human body model. table 7 absolute maximum ratings 1 symbol parameter limits units v dd .core supply voltage (core) -0.3 to +3.0 v v dd .in supply voltage (inputs) -0.3 to +3.6 v v dd .pad supply voltage (differential outputs) -0.3 to +3.6 v v in 2 input voltage -0.3 to +3.6 3 v t j junction temperature +150 c t stg storage temperature -65 to +150 c p max maximum power dissipation 6 w esd 6 electrostatic discharge 2000 v table 8 recommended operating conditions symbol parameter limits units v dd .core supply voltage (core) +2.375 to +2.625 v v dd .pad 4 supply voltage (differential output buffers) 3.3v 10% v v dd .in supply voltage (inputs) +3.0 to +3.6 v t a operating temperature: commercial operating temperature: industrial 0 to +70 -40 to +85 c table 9 pin capacitance 5 symbol parameter max units c pin signal pin capacitance 10 pf
ocx481 crosspoint switch ? advanced mini data sheet 16 [rev. 1.2] 8/8/01 i-cube, inc. 4.4 dc electrical specifications (t a = -40 c to 85 c, v dd .in = 3.3v 10%, v dd .core = 2.5v 5%) 1. all lvttl input pins have pull-up resistors. 2. input leakage only valid when both positive and negative inputs/outputs area equal (i.e. both high or both low). 3. see section 5 for dynamic power consumption calculation. 4. maximum capacitive load is 12 pf. the v oh levels are 200mv below standard single-ended lvpecl levels and are compatible with devices tolerant of lower common-mode ranges. the above table summarizes the dc output specifications of lvpecl. table 10 lvttl dc electrical specifications symbol parameter conditions min max units v ih high-level input ports are 3.3v tolerant 2.0 3.6 v v il low-level input ports are 3.3v tolerant -0.3 0.8 v v oh high-level output v dd .pad = min i oh = -4ma 2.4 v dd .pad+ 0.3 v v ol low-level output v dd .pad = min i ol = 8ma 0.4 v il ih , il il (1) input pin leakage current (2) v dd .in= max 0.0 < in < v dd.pad +5 -50 ? il oz tristate leakage output off state (2) v dd .pad = max 0.0 < in < v dd.pad +5 -5 ? power p ddq (3) quiescent power all v dd = max 0.5 w table 11 lvpecl dc electrical specifications symbol dc parameters min max units v in_diff input differential voltage 100 mv v in_com input common mode voltage 0.25 2.25 v v out_diff output differential voltage 650 900 mv v out_com output common mode voltage v dd .pad 2 v dd .pad 2 v z in termination impedance 80 120 ?
ocx481 crosspoint switch ? advanced mini data sheet i-cube, inc. [rev. 1.2] 8/8/01 17 4.5 lvpecl ac electrical specifications (v dd .in = 3.3v 10%, v dd .core = 2.5v 5%, v dd .pad = 3.3v 10%) notes : 1. these parameters are guaranteed but not tested in production. table 12 lvpecl ac electrical specifications 0 c to 70 c -40 c to +85 c symbol parameter min max min max units r data nrz data rate (1) 1.6 1.6 gb/s t phl , t plh one way signal propagation delay, fanout = 1 3.0 3.5 ns t w+ input flow-through positive pulse width 0.6 0.6 ns t w- input flow-through negative pulse width 0.6 0.6 ns t dcd+ , t dcd- duty cycle distortion 0.12 0.12 ns t jitter output jitter tbd tbd tbd tbd ps t sk skew between output ports (1) 0.2 0.25 ns t phz_ot , t plz_ot output enable to valid data 5 5 ns t pzh_ot , t pzl_ot output enable to high z state 5 5 ns t rc rapidconfigure clock period 12 12 ns t w+_rc t w-_rc rapidconfigure clock pulse width 5 5 ns t s_rc rapidconfigure address setup to rc_clk# 3 4 ns t h_rc rapidconfigure address and enable hold time to rc_clk# 3 4 ns t p_ud update of crosspoint to data out 10 10 ns
ocx481 crosspoint switch ? advanced mini data sheet 18 [rev. 1.2] 8/8/01 i-cube, inc. 4.6 timing diagrams note ? for the purpose of clarity, the timing diagrams within this data sheet are conceptual representations only and do not show actual circuit implementation. figure 5 flow-through mode timing figure 6 output enable timing figure 7 duty cycle distortion inport 1 inport 2 outport 1 outport 2 t sk t sk t plh t w+ t phl inport 1 in op outport 1 switch matrix inport 2 outport 2 oe# outport t pzh_ot t pzl_ot t plz_ot t phz_ot inport oe# in op outport inport switch matrix inport t in+ outport t in- t out+ t out- t dcd+ =t in+ - t out+ t dcd- =t in- - t out- in op switch matrix outport inport
ocx481 crosspoint switch ? advanced mini data sheet i-cube, inc. [rev. 1.2] 8/8/01 19 figure 8 rapidconfigure write cycle figure 9 rapidconfigure read cycle rca/rcb address, instruction rc_en# t rc t w+_rc t s_rc t rc t w-_rc t h_rc t s_rc t h_rc rc_clk# rca/rcb address, instruction rc_en# t rc t w+_rc t s_rc t rc t w-_rc t h_rc t s_rc t h_rc rc_clk# high impedance data valid rco
ocx481 crosspoint switch ? advanced mini data sheet 20 [rev. 1.2] 8/8/01 i-cube, inc. figure 10 typical performance typical performance at 1.6 gb/s with prbs data (currently not available for this document)
ocx481 crosspoint switch ? advanced mini data sheet i-cube, inc. [rev. 1.2] 8/8/01 21 5. power consumption chip power, consists of three integral elements (refer to figure 11): 1. input power ? this element has two components: a steady state component that is always on, and a component that is based on the number of inputs being used. 2. core power ? this element is the same for lvpecl or lvds outputs. core power is a function of data rate (mb/s) and the number of connection paths through the switch matrix. 3. output power ? this element is a fixed amount for each differential output. the value is zero if the output enable (oe#) is disabled or set to off. 5.1 power for lvpecl i/o figure 11 power consumption diagram for the ocx481 using lvpecl oe# output buffer switch matrix input power (always on) core power (320mw + 10mw/input) + 0.015mw/mbs/connection + 37mw/output example: worst case = (320mw + 240mw) + (0.015 mw x 1600 x 24) + (37mw x 24) 560mw 576mw 888mw + + = 2.02 watts output power
ocx481 crosspoint switch ? advanced mini data sheet 22 [rev. 1.2] 8/8/01 i-cube, inc. 6. component availability and ordering information 7. glossary crosspoint: a single cell controlled by two ram bits. the ram bits are connected in a master-slave configuration to provide an update for programming and changing program information all at once. crosspoint array: an array of crosspoint cells used to connect any input port to any output port. input or output path: the signal flow from pin to array and array to pin. each path has a register with selectable clocks, drivers for the loaded outputs with selectable enables, and sense circuits to detect changes on either side of the io buffer. port: a name followed by a number to identify a pin on the device. rapidconfigure: a parallel programming method for the ocx devices. the rc mode uses 23 dedicated pins to program the crosspoint array and the io buffers. the 23 pins consist of an enable, a clock, four instruction bits, two seven-bit address fields, and a three-bit data field. ocxxxxs - pp###t family # i/o ports speed grade blank = 667 mb/s 1 = 1.6 gb/s package code pb172 = ball grid array temperature range blank - commercial (0 c to 70 c) i - industrial (-40 c to +85 c)
ocx481 crosspoint switch ? advanced mini data sheet i-cube, inc. [rev. 1.2] 8/8/01 23 revision history date/ version no. description 4/25/2001 revision 1.0 preliminary release of ? advanced ? mini data sheet. 5/21/2001 revision 1.1 changes to lvpecl power consumption diagram and input power. 7/27/01 revision 1.2 changes to lvpecl dc electrical specs table; added termination impedance.
ocx481 crosspoint switch ? advanced mini data sheet 24 [rev. 1.2] 8/8/01 i-cube, inc. 8. product status definition i-cube ? is a registered trademark and rapidconnect, rapidconfigure, activearray, implieddisconnect, iq, iqx, msx, msxpro, ocx, ocxpro, and psx are trademarks of i-cube, inc. all other trademarks or registered trademarks are the property of their respective holders. i-cube, inc., does not assume any liability arising out of the applications or use of the product described herein; nor does it convey any license under its patents, copyright rights or any rights of others. the information contained in this document is believed to be current and accurate as of the publication date. i-cube reserves the right to make changes, at any time, in order to improve reliability, function, performance or design in order to supply the best product possible. i-cube assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. this product is protected under the u.s. patents: 5202593, 5282271, 5426738, 5428750, 5428800, 5465056, 5530814, 5559971, 5625780, 5710550, 5717871, 5734334, 5781717, 5790048. additional patents pending. ocx481 crosspoint switch advanced mini data sheet ? rev 1.2, july 2001 copyright ? 1992-2001 i-cube, inc. all rights reserved. unpublished ? rights reserved under the copyright laws of the united states. use of copyright notices is precautionary and does not imply publication or disclosure. i-cube ? , inc. 2605 s. winchester blvd. campbell, ca 95008 usa phone: +(408) 341-1888 ocx481 crosspoint switch ? advanced mini data sheet fax: +(408) 341-1899 revision 1.2, july 2001 email: marketing@icube.com document#: ocx481_ds_1.2 internet: http://www.icube.com data sheet identification product status definition advanced formative or in design this data sheet contains the design specifications for product development. specification may change in any manner without notice. preliminary preproduction product this data sheet contains the preliminary data, and supplementary data will be published at a later date. i-cube reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. no identification full production this data sheet contains final specifications. i-cube reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. obsolete no longer in production this data sheet contains specifications for a product that has been discontinued by i-cube. the data sheet is provided for reference information only.

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