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is61nw6432 integrated silicon solution, inc. 1 advance information sr050-0b 07/15/98 this document contains advance information data. issi reserves the right to make changes to its products at any time without no tice in order to improve design and supply the best possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 1998, integrated silicon solution, inc. features ? fast access time: C 5 ns-100 mhz; 6 ns-83 mhz; C 7 ns-75 mhz; 8 ns-66 mhz ? no wait cycles between read and write ? internal self-timed write cycle ? individual byte write control ? clock controlled, registered address, data and control ? pentium? or linear burst sequence control using mode input ? three chip enables for simple depth expansion and address pipelining ? common data inputs and data outputs ? jedec 100-pin tqfp and pqfp package ? single +3.3v power supply ? optional data strobe pin (#80) for latching data (see page 12 for detailed timing) description the is61nw6432 is a high-speed, low-power synchronous static ram designed to provide a burstable, high- performance, 'no-wait' bus, secondary cache for the pentium, 680x0, and power pc microprocessors. it is organized as 65,536 words by 32 bits, fabricated with issi 's advanced cmos technology. incorporating a 'no-wait' bus, wait cycles are eliminated when the bus switches from read to write, or write to read. this device integrates a 2-bit burst counter, high-speed sram core, and high-drive capability outputs into a single monolithic circuit. all synchronous inputs pass through registers controlled by a positive-edge-triggered clock input. operations may be suspended and all synchronous inputs ignored when clock enable, cen is high. in this state the internal device will hold their previous values. when the adv/ ld is high the internal burst counter is incremented. new external addresses can be loaded when adv/ ld is low. write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when rd/ we is low. separate byte enables allow individual bytes to be written. bw1 controls i/o1-i/o8; bw2 controls i/o9-i/o16; bw3 controls i/o17-i/o24; bw4 controls i/o25-i/o32. all bytes are written when bw1 , bw2 , bw3 , and bw4 are low. mode pin upon power up is in interleave burst mode. it can be connected to gndq or vccq to alter power up state. is61nw6432 64k x 32 synchronous static ram with no-wait state bus feature advance information july 1998 issi
is61nw6432 2 integrated silicon solution, inc. advance information sr050-0b 07/15/98 block diagram 64k x 32 bit memory array address control d in d out i mode a0-a15 ce1, ce2, ce3 r/w cen adv/ld bw1 bw2 bw3 bw4 o o o o i i i oe mux sel clock oe control logic gate output register data i/o1-i/o32 ds (optional) input register
is61nw6432 integrated silicon solution, inc. 3 advance information sr050-0b 07/15/98 nc i/o16 i/o15 vccq gndq i/o14 i/o13 i/o12 i/o11 gndq vccq i/o10 i/o9 gnd vcc vcc gnd i/o8 i/o7 vccq gndq i/o6 i/o5 i/o4 i/o3 gndq vccq i/o2 i/o1 nc a6 a7 ce1 ce2 bw4 bw3 bw2 bw1 ce3 vcc gnd clk r/w cen oe adv/ld nc nc a8 a9 nc i/o17 i/o18 vccq gndq i/o19 i/o20 i/o21 i/o22 gndq vccq i/o23 i/o24 vcc vcc vcc gnd i/o25 i/o26 vccq gndq i/o27 i/o28 i/o29 i/o30 gndq vccq i/o31 i/o32 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a5 a4 a3 a2 a1 a0 nc nc gnd vcc nc nc a10 a11 a12 a13 a14 a15 nc 46 47 48 49 50 pin configuration 100-pin tqfp and pqfp (top view) pin descriptions a0-a15 address inputs clk clock cen clock enable adv/ cd advance load bw1 - bw4 synchronous byte write enable r/ w read/write ce1 , ce2, ce3 synchronous chip enable oe output enable ds (1) data strobe i/o1-i/o32 data input/output mode burst sequence mode v cc +3.3v power supply gnd ground v ccq isolated output buffer supply: +3.3v gnd q isolated output buffer ground nc no connect note: 1. optional, nc or ds.
is61nw6432 4 integrated silicon solution, inc. advance information sr050-0b 07/15/98 truth table (1) address operation used r/ w w w w w cex cex cex cex cex adv/ ld ld ld ld ld cen cen cen cen cen bwx bwx bwx bwx bwx clk begin new write cycle external llll valid l-h begin new read cycle external h l l l x l-h advance burst counter (2) internal x x h l valid l-h (burst write) advance burst counter internal x x h l x l-h (burst read) deselect (2 cycle) (3) x x h l l x l-h hold/noop (4) xxxxhxl-h notes: 1. "x" means don't care. 2. when adv/ ld signal is sampled high, the internal burst counter is incremented. the r/ w signal is ignored when the counter is advanced. therefore, the nature of the burst cycle (read or write) is determined by the status of the r/ w signal when the first address is loaded at the beginning of the burst cycle. 3. deselect cycle is initiated when cex is sampled high and adv/ ld sampled low at rising edge of clock. the data bus will tri-state two cycles after deselect is initiated. 4. when cen is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. the state of all the internal registers remains unchanged. partial truth table (non-burst) function r/ w w w w w bw1 bw1 bw1 bw1 bw1 bw2 bw2 bw2 bw2 bw2 bw3 bw3 bw3 bw3 bw3 bw4 bw4 bw4 bw4 bw4 cex cex cex cex cex adv/ ld ld ld ld ld read h xxxxl l write byte 1 l l h h h l l write byte 2 l h l h h l l write byte 3 l h h l h l l write byte 4 l h h h l l l write all bytes llllll l n+29 n+30 n+31 n+32 n+33 n+34 n+35 n+36 n+37 clock address (a0-a15) control (bwx, r/w, adv/ld) data (i/o1-i/o32) cycle a29 a30 a31 a32 a33 a34 a35 a36 a37 c29 c30 c31 c32 c33 c34 c35 c36 c37 d27 d28 d29 d30 d31 d32 d33 d34 d35 functional timing diagram
is61nw6432 integrated silicon solution, inc. 5 advance information sr050-0b 07/15/98 typical operation ( ce1 , ce3 and cen are low, ce2 is high, non-burst operation) cycle address r/ w w w w w adv/ ld ld ld ld ld cex cex cex cex cex cen cen cen cen cen bwx bwx bwx bwx bwx oe oe oe oe oe i/o comments n a0 h l l l x ? dC2 ? n+1 a1 l l lll?dC1 ? n+2 a2 h l l l x l d0 data out n+3 a3 l l l l l x d1 data in n+4 a4 h l l l x l d2 data out n+5 a5 l l l l l x d3 data in n+6 a6 h l l l x l d4 data out n+7 a7 l l l l l x d5 data in n+8 a8 h l l l x l d6 data out n+9 a9 l l l l l x d7 data in n+10 a10 h l l l x l d8 data out n+11 a11 h l l l x x d9 data in n+12 a12 l l lllld10 data out n+13 a13 l l lllld11 data out n+14 a14 h l l l x x d12 data in n+15 a15 h l l l x x d13 data in n+16 a16 h l l l x l d14 data out n+17 a17 l l lllld15 data out n+18 a18 l l lllld16 data out n+19 a19 l l l l l x d17 data in n+20 a20 h l l l x x d18 data in n+21 a21 h l l l x x d19 data in note: 1. h = high; l = low; x = don't care; ? = don't know; z = high impedance
is61nw6432 6 integrated silicon solution, inc. advance information sr050-0b 07/15/98 read operation cycle address r/ w w w w w adv/ ld ld ld ld ld cex cex cex cex cex cen cen cen cen cen bwx bwx bwx bwx bwx oe oe oe oe oe i/o comments n a0 h l l l x x x address and control meet setup n+1 x x x l l x x x clock setup valid n+2 x x x x x x l d0 contents of address a0 read out burst read operation cycle address r/ w w w w w adv/ ld ld ld ld ld cex cex cex cex cex cen cen cen cen cen bwx bwx bwx bwx bwx oe oe oe oe oe i/o comments n a0 h l l l x x x address and control meet setup n+1 x x h x l x x x clock setup valid, advance counter n+2 x x h x l x l d0 address a0 read out, inc. count n+3 x x h x l x l d0+1 address a0+1 read out, inc. count n+4 x x h x l x l d0+2 address a0+2 read out, inc. count n+5 a1 h l l l x l d0+3 address a0+3 read out, load a1 n+6 x x h x l x l d0 address a0 read out, inc. count n+7 x x h x l x l d1 address a1 read out, inc. count n+8 a2 h l l l x l d1+1 address a1+1 read out, load a2 write operation cycle address r/ w w w w w adv/ld cex cex cex cex cex cen cen cen cen cen bwx bwx bwx bwx bwx oe oe oe oe oe i/o comments n a0 l l l l l x x address and control meet setup n+1 x x x l l x x x clock setup valid n+2 x x x x l x x d0 write d0 to address a0 burst write operation cycle address r/ w w w w w adv/ ld ld ld ld ld cex cex cex cex cex cen cen cen cen cen bwx bwx bwx bwx bwx oe oe oe oe oe i/o comments n a0 l l l l l x x address and control meet setup n+1 x x h x l l x x clock setup valid, inc. count n+2 x x h x l l x d0 address a0 write, inc. count n+3 x h h l l x x d0+1 address a0+1 write, inc. count n+4 x x h x l l x d0+2 address a0+2 write, inc. count n+5 a1 l l l l l x d0+3 address a0+3 write, load a1 n+6 x x h x l l x d0 address a0 write, inc. count n+7 x x h x l l x d1 address a1 write, inc. count n+8 a2 l l l l l x d1+1 address a1+1 write, load a2 note: 1. h = high; l = low; x = don't care; ? = don't know; z = high impedance
is61nw6432 integrated silicon solution, inc. 7 advance information sr050-0b 07/15/98 read operation with clock enable used cycle address r/ w w w w w adv/ ld ld ld ld ld cex cex cex cex cex cen cen cen cen cen bwx bwx bwx bwx bwx oe oe oe oe oe i/o comments n a0 h l l l x x x address and control meet setup n+1 x x x x h x x x clock n+1 ignored n+2 a1 h l l l x x x clock valid n+3 x x x x h x l d0 clock ignored. data d0 is on the bus n+4 x x x x h x l d0 clock ignored. data d0 is on the bus n+5 a2 h l l l x l d0 address a0 read out (bus trans.) n+6 a3 ? l l l x l d1 address a1 read out (bus trans.) n+7 a4 ? l l l x l d2 address a2 read out (bus trans.) write operation with clock enable used cycle address r/ w w w w w adv/ ld ld ld ld ld cex cex cex cex cex cen cen cen cen cen bwx bwx bwx bwx bwx oe oe oe oe oe i/o comments n a0 l l l l l x x address and control meet setup n+1 x x x x h x x x clock n+1 ignored n+2 a1 l l l l l x x clock valid n+3 x x x x h x l di clock ignored. n+4 x x x x h x l di clock ignored. n+5 a2 l l l l l l d0 write data d0 (bus trans.) n+6 a3 ? l l l l l d1 write data d1 (bus trans.) n+7 a4 ? l l l l l d2 write data d2 (bus trans.) note: 1. h = high; l = low; x = don't care; ? = don't know; z = high impedance; di could be d0 if desired.
is61nw6432 8 integrated silicon solution, inc. advance information sr050-0b 07/15/98 interleaved burst address table (mode = v ccq or no connect) external address 1st burst address 2nd burst address 3rd burst address a1 a0 a1 a0 a1 a0 a1 a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd q ) absolute maximum ratings (1) symbol parameter value unit t bias temperature under bias C10 to +85 c t stg storage temperature C55 to +150 c p d power dissipation 1.8 w i out output current (per i/o) 100 ma v in , v out voltage relative to gnd for i/o pins C0.5 to v ccq + 0.3 v v in voltage relative to gnd for C0.5 to 5.5 v for address and control inputs notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high-z at power up. 0,0 1,0 0,1 a1', a0' = 1,1
is61nw6432 integrated silicon solution, inc. 9 advance information sr050-0b 07/15/98 operating range range ambient temperature v cc commercial 0 c to +70 c 3.3v +10%, C5% dc electrical characteristics (1) (over operating range) symbol parameter test conditions min. max. unit v oh output high voltage i oh = C5.0 ma 2.4 v v ol output low voltage i ol = 5.0 ma 0.4 v v ih input high voltage 2.0 v ccq + 0.3 v v il input low voltage C0.3 0.8 v i li input leakage current gnd v in v ccq (2) com. C5 5 m a i lo output leakage current gnd v out v ccq , oe = v ih com. C5 5 m a power supply characteristics (over operating range) -5 -6 -7 -8 symbol parameter test conditions min. max. min. max. min. max. min. max. unit i cc ac operating device selected, com. 230 220 210 200 ma supply current all inputs = v il or v ih oe = v ih , cycle time 3 t kc min. i sb standby current device deselected, com. 60 60 60 60 ma v cc = max., all inputs = v ih or v il clk cycle time 3 t kc min., cen = v ih notes: 1. mode pin has an internal pull up. this pin may be a no connect, tied to gnd, or tied to v ccq . 2. mode pin should be tied to vcc or gnd. it exhibits 30 m a maximum leakage current when tied to gnd + 0.2v or 3 vcc C 0.2v.
is61nw6432 10 integrated silicon solution, inc. advance information sr050-0b 07/15/98 capacitance (1,2) symbol parameter conditions max. unit c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25 c, f = 1 mhz, vcc = 3.3v. ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 1.5 ns input and output timing 1.5v and reference level output load see figures 1 and 2 ac test loads figure 1 output buffer z o = 50 w 1.5v 50 w 30 pf 317 w 5 pf including jig and scope 351 w output 3.3v figure 2
is61nw6432 integrated silicon solution, inc. 11 advance information sr050-0b 07/15/98 read/write cycle switching characteristics (1) (over operating range) -5 -6 -7 -8 symbol parameter min. max. min. max. min. max. min. max. unit fmax clock frequency 100 83 75 66 mhz t kc cycle time 10 12 13 15 ns t kh clock high time 4 4 6 6 ns t kl clock low time 4 4 6 6 ns t kq clock access time 5 6 7 8 ns t kqx (2) clock high to output invalid 1.5 1.5 1.5 1.5 ns t kqlz (2,3) clock high to output low-z 2.0 2.0 2.0 2.0 ns t kqhz (2,3) clock high to output high-z 1.5 3.5 2 3.5 2 3.5 2 3.5 ns t oeq output enable to output valid 5 6 6 6 ns t oeqx (2) output disable to output invalid 0 0 0 0 ns t oelz (2,3) output enable to output low-z 0 0 0 0 ns t oehz (2,3) output disable to output high-z 3.5 3.5 3.5 3.5 ns t as address setup time 2.0 2.0 2.0 2.0 ns t ws read/write setup time 2.0 2.0 2.0 2.0 ns t ces chip enable setup time 2.0 2.0 2.0 2.0 ns t se clock enable setup time 2.0 2.0 2.0 2.0 ns t avs address advance setup time 2.0 2.0 2.0 2.0 ns t ah address hold time 0.5 0.5 0.5 0.5 ns t he clock enablehold time 0.5 0.5 0.5 0.5 ns t wh write hold time 0.5 0.5 0.5 0.5 ns t ceh chip enable hold time 0.5 0.5 0.5 0.5 ns t als advance/load (adv/ ld ) setup time 2.0 2.0 2.0 2.0 ns t alh advance/load (adv/ ld ) hold time 0.5 0.5 0.5 0.5 ns tds data setup time 2.0 2.0 2.0 2.0 ns tdh data hold time 0.5 0.5 0.5 0.5 ns tzq i/o from tri-state to valid 1.5 2.5 1.5 2.5 1.5 2.5 1.5 2.5 ns notes: 1. configuration signal mode is static and must not change during normal operation. 2. guaranteed but not 100% tested. this parameter is periodically sampled. 3. tested with load in figure 2.
is61nw6432 12 integrated silicon solution, inc. advance information sr050-0b 07/15/98 read/write cycle timing single read single write high-z high-z high-z data out data strobe data in oe ce3 ce2 ce1 bw4-bw1 r/w a15-a0 adv/ld clk cen rd1 rd2 rd3 wr1 wr1 1a 2a 1a 4a 4b 4c 4d unselected burst read t kqx t kc t kl t kh t se t he t als t alh t as t avs t ah t ws t wh t ws t wh rd4 rd5 t ces t ceh t ces t ceh t ces t ceh unselected with ce3 t oeq t oelz t kqlz t zq t kq t kqx t kq t ds t dh t kqhz 3a t oeqx t oehz high-z high-z
is61nw6432 integrated silicon solution, inc. 13 advance information sr050-0b 07/15/98 ordering information commercial range: 0 c to +70 c speed (ns) order part number package 5 is61nw6432-5tq tqfp IS61NW6432-5PQ pqfp 6 is61nw6432-6tq tqfp is61nw6432-6pq pqfp 7 is61nw6432-7tq tqfp is61nw6432-7pq pqfp 8 is61nw6432-8tq tqfp is61nw6432-8pq pqfp notice integrated silicon solution, inc., reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. integrated silicon solution, inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user's specific application. while the information in this publication has been carefully checked, integrated silicon solution, inc. shall not be liable for any damages arising as a result of any error or omission. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the fail ure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assum es all such risks; and (c) potential liability of integrated silicon solution, inc. is adequately protected under the circumstance s. copyright 1998 integrated silicon solution, inc. reproduction in whole or in part, without the prior written consent of integrated silicon solution, inc., is prohibited. integrated silicon solution, inc. 2231 lawson lane santa clara, ca 95054 tel: 1-800-379-4774 fax: (408) 588-0806 e-mail: sales@issi.com http://www.issi.com issi

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