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hmxnv0100 www.hon eywell.com/ae rosp ace h hxnv0100 64k x 16 non-volatile magnetic ram advanced in form ation the 64k x 16 radiation h a rdene d low p o w er n onvolatil e magneti c ra m (mram ) is a high pe rformance 65,53 6 word x 16-bit magneti c ra n dom acce ss memory with indu stry-stan dard fun c tion ality. the mram i s desig ned for very high reli ability. red und ant write cont rol lin es, erro r co rrection codi ng and lo w-volta ge write p r ote c tion en su re the co rrect operation of the memo ry and t hat it is protected from inadverte nt writes. integrated po wer up an d powe r do wn ci rcuit r y cont rol s the con d ition of the device durin g po wer transitio ns. it is fabricate d with ho ney well? s radi atio n hard ene d silicon on insulator (soi) te chnology, and is designed for use in lo w-voltage sy stems op eratin g in radiatio n environ ment s. the mram operates ove r the full milita r y temperature range a nd is o perate d with 3.3 0.3v an d 1.8 0.15 v power suppli e s. features rea d cy cl e time ?60 ns write cy cle t i me 10 0n s typical op erating powe r 500 m w unlimited re ad/write (>1e 15 cy cle s ) > 10 years power-off data retentio n synchrono us operation single-bit error dete ction & cor r e c tion (e cc ) fabri c ate d on s150 silicon on insulato r (so i ) cmos u n de r l a y er te c h n o l og y 150 nm pro c ess (leff = 1 3 0 nm) total dos e hardness ?3x10 5 rad (si o 2 ) dos e rate ups e t hardness ?1x10 10 rad(si )/s dose rate survivability 1x1 0 12 rad ( si)/s soft error r a te 1x10 -10 upsets/bit-d a y neutron hard ness ?1x10 13 cm -2 no lat chu p dual po we r supplie s ? 1.8 v 0.15v, 3.3 v ?0.3v ? 3.3v cmos comp atible i/o operating ra nge is -55 c to +12 5 c package: 64 lead shiel d e d cer a mi c qua d flat p a ck
hmxnv0100 functional blo ck diagram m e m o ry a rra y 6 5 , 536 x 16 co l u m n de c o d e r d a ta inp u t / o u tpu t r ead c i r c u i t s b i t li ne c u r r en t d r i v e r s d i gi t li n e cu r r e n t dr i v e r s a ( 7: 15) we nwi dq( 0 : 1 5 ) e cc ar r a y 65, 53 6 x 5 e cc l o g i c dq c cs dq c oe we _ a s a ( 0: 6) dq c e c c _ d i sab l e er ro r signal description signal defini tion a(0:6) colum n sele ct addre s s input. signals whi c h sele ct a colum n with in the memory a rra y . a?(7:15 ) ro w select a ddre s s input. signals which sele ct a ro w within the memory a rra y . dq (0:15 ) data input/o utput signals. bi-directio n a l data pins wh ich serve a s data outputs d u rin g a read o p e r ation and a s data input s d u ring a write operation. cs chip sele ct. the ri sing e d ge of cs will clo ck in the a ddre s s and we sign als we write ena b le. this si gnal is latched to en able a write. we_as write ena b le asynch ro nou s ? this sign al can b e use d to delay the begin n ing of the write cycle oe output enabl e. nwi_ 0 nwi_ 1 not write inhi bit ? when se t low, these si gnal s inhibit write s to the memory. a high level allo ws the m e mo ry to be writte n. nwi ( 0) cont rols ad dre s s locatio n s a(15 :0) = 0x000 0 to 0x7fff. nwi ( 1) cont rols ad dre s s locatio n s a(15 :0) = 0x100 0 to 0xffff. ecc_ di sabl e erro r co rrecti on di sabl e ? di sable s the error corre c tion functio n . erro r ecc er ror fla g test_1 test_2 these sig nal s are fo r ho n e ywell test pu rpo s e s only. these sh ould be grou nde d in n o rmal o peration. vdd1 dc po we r source input: 1.8v vdd2 dc po we r source input: 3.3v 2 www.h oneywell.com
hmxnv0100 trut h table nwi we & we_ a sy oe mode dq l x l de sele c t e d h i g h z h l l disable d h i g h z h l h rea d d a t a o u t h h x w r i t e d a t a i n x: v i = v ih or v il package pinout 64 g n d 63 d q ( 2 ) 62 d q ( 3 ) 61 d q ( 4 ) 60 d q ( 5 ) 59 d q ( 6 ) 58 d q ( 7 ) 5 7 vd d2 56 g n d 55 a ddr (0 ) 54 a ddr (1 ) 53 a ddr (2 ) 52 a ddr (3 ) 51 a ddr (4 ) 50 a ddr (5 ) 4 9 vd d1 48 g n d 4 7 vd d2 46 a d r ( 6) 45 a d r ( 15 ) 44 we 43 we _ a s y 42 oe 4 1 vd d2 4 0 vd d1 39 g n d 38 a ddr (1 4 ) 37 a ddr (1 3 ) 36 a ddr (1 2 ) 35 a ddr (1 1 ) 34 g n d 3 3 vd d1 v dd1 1 gn d 2 dq (1 ) 3 dq (0 ) 4 cs 5 n wi( 0 ) 6 v dd2 7 v dd1 8 gn d 9 n w i ( 1) 10 eccdisable 11 error 12 dq (8 ) 13 dq (9 ) 14 v dd2 15 gn d 16 hmxnv1000 v dd1 1 7 d q ( 10) 1 8 d q ( 11) 1 9 d q ( 12) 2 0 d q ( 13) 21 d q ( 14) 2 2 d q ( 15) 2 3 gn d 2 4 v dd2 2 5 ad dr( 7 ) 2 6 ad dr( 8 ) 2 7 ad dr( 9 ) 2 8 ad dr( 1 0) 2 9 test 30 test 31 gn d 32 ram and rom functional capability this m r am inco rpo r ate s two write co ntrol sign als allo wi ng the two se ction s of the memory to be controll ed in depe ndently. the two not write inhi bit signal s, nwi ( 0) a nd nwi(1 ) , allow o ne se ction of the device s to op erate a s a ra m and the oth e r to operate a s a rom at the full control of the use r . 3 www.h oneywell.com
hmxnv0100 soi and magnetic me mory technology hon e ywell? s s150 silicon on insul a tor (soi) is radia t ion hard ene d through the use of advanced and prop rieta r y desig n, layout and process hard enin g techniqu es. the 150 nm pro c e s s is a tech nolo g y with a 32? gate oxide for 1.8 v transi s tors and 70? gate oxide for 3.3 v transi s tors. the memo ry element is a magneti c tun nel jun c tion (mtj) that is com p o s ed of a mag netic sto r ag e layer structu r e and a mag n e tic pinn ed la yer stru cture se p a rated by an i n sul a ting tun nel barrier inte rla y er. duri ng a write cy cle, th e stora ge laye r is written by t he appli c atio n of two ortho gon al curre n ts of the desi r ed polarity usi n g row-an d-colu mn add re ssi n g . the re si stan ce of the mtj depe nd s on the magneti c stat e of the stora ge layer, whi c h use s the pin n ed layer st ru cture as a referen c e, an d whi c h en abl es sen s ing, sign al amplifi c ation, an d re adba ck. the resi stan ce ch ange i s a co n s eq uen ce of the cha nge in tun neling ma gne toresi stan ce (tm r ) bet we en the sto r ag e and pin ned layers that de pend s on the magneti c stat e of the storage la yer. with rea d and write cycles in ex ce ss of 1 0 15 , there is no wear-out. error correcti o n code (ecc) ham m i ng 5- bit ec c a 5-bit hamm ing ecc i s ge nerate d for all data written i n to memory. this code all o ws for the co rrection of all sing le-bit er ro rs p e r address. on a read cy cle, the data is re ad from memo ry and co rrecte d, if necessa ry, before b e ing placed on the output data b u s. there is no chang e made t o the actual d a ta in the memory cells ba se d on the ecc results. actu al data in me mory is chan ged only upon wri t ing new valu es. radiatio n characteris tic total ionizin g radia t ion dose the mram will meet all stated functional and ele c tri c al spe c ificatio n s over the ent ire operating tem peratu r e rang e after the spe c ified total ionizin g radi ation do se. all electri c al a n d timing performance parameters will remain wi thin specifications after reb oun d at typical vdd and t =125 q c extrapolate d to ten years of operatio n. total dose hardne ss is a s sure d by wafer level testing of pro c e ss m onitor transi s to rs a n d ram pro d u c t usin g 10 kev x-ray and co60 radiatio n so urce s. tran si stor gate threshold shift co rrel a tions h a ve bee n made bet ween 10 kev x-ray s appli ed at a dose rate of 1x10 5 ra d(si o 2 )/min at t = 25 q c an d g a mma rays (co balt 60 so urce ) to ensure that wafer level x-ray testing is consi s tent with standard milit ary radi ation test environ ment s. transien t pu lse ionizing radia t ion the mram i s capa ble of writing, rea d ing , and retai n ing store d data d u ring a nd afte r exposure to a transie nt ioni zing radiatio n pulse, up to the sp ecifie d tran sient do se rate upset spe c ification, whe n a pplied u nde r recomme nde d operating condition s. to ensure validit y of all specifi ed perfo rma n c e para m eters b e fore, du ring, and after radiatio n (timi ng deg rad a tio n durin g transi ent pul se radiatio n is r 10%), it is sug g e s ted th at stiffening capa citan c e b e placed ne ar the pa ckage v d d 2 an d gro u nd (g nd ). it is recom m e nded that the indu ctan ce betwe en the mram pa cka ge lead s an d the stiffening cap a citan c e b e less that 1.0 nh. if there a r e no operate thro u gh or valid st ored - data req u ire m ents, typical circuit boa rd mounted d e -couplin g cap a c itors are recommended. the mra m will meet any function al or electri c al spe c ificatio n after exposure to a radiation p u l s e up to the transi ent dose rate survivability spe c ification, whe n applie d under 4 www.h oneywell.com
hmxnv0100 recomme nde d operating condition s. not e that the curre n t cond ucte d durin g the pul se by the ram inputs, outp u ts, and po we r sup p ly may significa ntly excee d the normal operating lev e ls. the ap pli c ation d e si gn must a c com m odate the s e effects. neu t ron rad i ation the mram will meet any functional or ti ming spe c ification after exposure to the spe c i f ied neutro n fluen ce un der re co mmend ed operating o r storage con d itions. thi s assume s eq u i valent neutro n energy of 1 mev. soft error rate the mram i s capa ble of meeting the spe c ified soft error rate (ser) und er recomme nde d operating condition s. thi s hard n e ss lev e l is define d by the adams 90% worst case co smic ray envi r onm ent for geo synchro n ous o r bits. latc hup the mram will not latch up under a n y of the above ra diati on expo sure con d ition s wh en applie d unde r reco mmen d e d operating con d ition s . fabri c ation with the simox sub s trate m a terial p r ovide s oxide isolatio n betwe en adj a c ent pmos a nd nm os transi s to rs a n d eliminate s any potential scr-type latchu p stru ctu r es. sufficient transi s to r bod y tie conne ctions to the p - cha nnel a nd n-chan nel su bstrate s a r e made to ensu r e no sou r ce/drain sna pba ck occurs. radiation-hardness ratings p a r a m e t e r l i m i t s u n i t s test conditi o n s total dos e : r-l e v e l f-level h-l e v e l t 1 x 10 5 t 3 x 10 5 t 1 x 10 6 rad s (si o 2 ) vdd1 = 1.95 volts, vdd2 = 3.6 volts t a = 25c, x-ray or co 60 soft error rate: d 1 x 10 - 10 up sets/bit- d a y v d d 1 = 1.8 v o lts, vdd2 = 3.3 volts t c = -5 5 to 125 q c tran sie n t do se rate upset t 1 x 10 10 rad s (si ) / s v d d 1 = 1.65 vo lts, vdd2 = 3.0 volts t c = 1 2 5 q c pulse width = 1sec, x- ray tran sie n t do se rate survivability t 1 x 10 12 rad s (si ) / s v d d 1 = 1.95 vo lts, vdd2 = 3.6 volts t a = 25 q c pulse width = 50 n s e c , x-ray neutron flu e n ce 1x10 13 n / c m -2 1mev equival ent energy magnetic field charact e r istics the mram will meet all stated functional and ele c tri c al spe c ificatio n s over the ent ire operating tem peratu r e rang e whe n expo sed to the spe c ified magn etic fields. the magneti c field hard enin g is achieved throug h a co mbination of soi technolo g y cha r a c teri stics, circuit de si gn and spe c iali zed p a ckagi ng. 5 www.h oneywell.com
hmxnv0100 magnetic field rating p a r a m e t e r l i m i t s u n i t s test conditi o n s magneti c fiel d 50 oe vdd1 = 1. 8 v o lts, vdd2 = 3.3 volts t c = -55 to 1 2 5 q c electrical specifications absolute maximum ratings (1) ratin g s sy m b o l p a r a m e t e r m i n m a x u n i t s v dd 1 positive supp ly voltage (2) -0.5 2.5 volts v dd 2 positive supp ly voltage (2) -0.5 4.5 volts v pin voltage on a n y pin (2) -0.5 v dd 2 + 0.5 volts t store storage te m peratu r e -65 150 q c t solder solderi ng te mperature 225 q c q c* se c (5 ) p d package po wer di ssi pation (3) 2.5 w p jc package t h e r mal resi stan ce (jun ction to case) 2 . 0 q c/w v prot electro s tatic disch a rg e protection voltage (4 ) 2 0 0 0 v t j jun c tion te m peratu r e 175 q c 1. stresse s in e x cess of those listed ab ov e may result in immediate perm ane nt damage to the device. these are stress rating s o n ly, and operation at these levels is not implied. freq uent or exten ded expo su re to absolute maximum co ndition s may affect device reliabil i ty. 2. voltage refe renced to gnd 3. ram po wer d i ssi pation d u e to i dds , i dd op , and i ddsei , plus ram o u tp ut driver po wer dissipatio n du e to external loadin g must not excee d this sp ecifi c atio n 4. cla ss 2 el ectrostatic di scha rge (es d ) inp u t prote c tion voltage per m i l-std-88 3, method 30 15 5. maximum sol derin g temp o f 225 q c can b e maintaine d for no mo re than 5 second s. recommended operating conditions (1) limits sy mbol parameter min ty pi c a l max units v dd 1 positive supp ly voltage 1.65 1.8 1.95 volts v dd 2 positive supp ly v o l t a g e 3 . 0 3 . 3 3 . 6 v o l t s t c external packag e temp erature -55 25 125 q c v pin voltage on a n y pin -0.3 v dd 2 +0. 3 v o lt s (1) voltages refe ren c ed to g n d 6 www.h oneywell.com
hmxnv0100 dc ele c t r ical characte r istics limits sy mbol parameter min ty pi c a l max units test conditi ons vil low l e vel input voltage 0 . 3 v d d v vih high -level inp u t voltage 0.7vdd v v o l l o w - l e v e l out p u t voltage 0.35 0.5 v vdd = 3.0 volts v o h h i g h -level ou t p u t voltage vdd-0.5 2 .66 (2.95 ) v vdd = 3.0 volts (vdd = 3.3 volts) i o z o u t p u t lea ka g e cur r e n t t b d p a il input lea kag e curre n t tbd p a io output drive curre n t 6 ma iddsb standby cu rrent vdd1 (1.8v) vdd2 (3.3v) 3 3 m a ac ele c t r ical characte r istics limits sy mbol parameter min ty pi c a l max units test conditi ons iddwr average writ e curre n t vdd1 (1.8v) vdd2 (3.3v) 15 260 m a contin uou s w r i t e cycle at 10 m h z (1) iddrd average rea d curre n t vdd1 (1.8v) vdd2 (3.3v) 15 3 m a contin uou s r e a d cycle at 10 m h z (1) 1. curre n t con s umption is re duced with lo wer d u ty cycl e. the scale i s linea r with resp ect to duty cycle wit h 3 ma minimum values of on ea ch vdd signal. cap acit ance (1) limits test conditi ons sy mbol parameter min max units c a and c c addre s s and control line cap a cita nce 6 p f t b d c d data lin e ca pacita n ce 9 pf value is i/o b u ffer only. c nw i not write inhi bit cap a cita nce 1 0 0 p f note: 1. these value s are tested at cha r acte ri zation only. 7 www.h oneywell.com
hmxnv0100 8 www.h oneywell.com rise/fal l times value test conditi ons sy mbol parameter min max units r t rise time 1.4 ns cloa d = 5 pf r t rise time 2.9 ns cloa d = 25 p f f t fall time 1.4 ns cloa d = 5 pf f t fall time 2.9 ns cloa d = 25 p f data e n durance ratin g s test conditi ons parameter min max units data endu ra nce 1x10 15 cy cle s data ret e ntion ratin g s test conditi ons parameter min max units data retentio n >10 years tester equivalent load circuit valid high output 3.3v v1 249 valid low output v2 dut output c l > 50 pf
hmxnv0100 read cy cle the ram i s synchrono us i n operation relative to the rising e dge o f the chip select (cs) sign al. with the initia tion of a cs sign al, the ad dre ss a nd the write enabl e (we ) sig nal a r e latch ed int o the device and the read o p e r ation begi ns. the memo ry locatio n s a r e read a nd com pare d with th e ecc value s . any single bit erro rs are detecte d and corre c ted. if we was lo w wh en latch ed in, the data is sent to the ou tput drivers. in addition to we low bei ng latched, output enable (oe) must be set to a hi gh value to e nable the dq output buffers. oe is not latche d, and ma y be set hig h b e fore o r after the risin g edg e of cs. read cy cle ac ti ming charact eris tics re a d cy cle tr d c cs t c s p w a ddr[0:15] a ddr v a l id t ads u t adhd t c s d v we t w es u t w ehd oe t oedv dq[0 :1 5 ] hig h z o ut put dat a valid min t y p max t c s p w c s puls e w i dth ( f or valid r ead) 10ns ------ ------ t c s p i c s ignor ed puls e w i dth ( g litc h toler anc e) ------ ------ 1 n s t w es u w e s e tup tim e w i th r e s pec t to r i s i ng edge of cs 3 n s ------ ------ t w ehd w e hold tim e w i th r e s pec t to r i s i ng edge of cs 2 n s ------ ------ t ads u a ddr es s s e tup tim e w i th r e s pec t to r i s i ng edge of cs 8 n s ------ ------ t adhd addr es s hold tim e w i th r e s pec t to r i s i ng edge of cs 2 n s ------ ------ t c s d v o utput data valid w i th r e s pec t to r i s i ng edge of cs ------ ------ 60ns t oedv o u tput data valid w i th r e s pec t to r i s i ng edge of o e ------ ------ 10ns t r dc cs r i s i ng edge to nex t cs r i s i ng edge ( r ead c y c l e tim e ) 60ns ------ ------ 9 www.h oneywell.com
hmxnv0100 write cy cle the ram i s synchrono us i n operation relative to the rising e dge o f the chip select (cs) sign al. with the initia tion of a cs sign al, the ad dre ss a nd the write enabl e (we ) sig nal a r e latch ed int o the device. if we was high when latc hed in, the write asynch ro nou s (we_as) si gnal is che cked. if we_as is high, the write cycle wi ll begin. if we_ as is low, the write cy cle will be delayed until we_a s is set high. this allows control by the host processo r of the actual time th e data is written to memory . the write cycle b egin s by readi ng the curre n t value in memory. the cu rrent memory data is com p a r ed t o the data to be written. if the locatio n nee d s to cha nge value, the data is then written. the bit cell constructio n of this device d oes not provide a method of si mply writing a ?1? or a ?0 ? to ma tch the data. the ?write ? to a bit can only chang e its stat e, thus the ne ed to read the bit location s first . only the bits whi c h ne ed to ?ch ang e sta t e? are a c tuall y written. write cy cle ac ti ming charact eris tics non-del a ye d w r i t e c y c l e - n on de l a y e d ( w e_ a s y n < 4 0 ns a f t e r c s ) tw r c cs t c s p w a ddr [ 0 : 1 5 ] ad d r val i d t adsu t adh d we t w e s u t w e h d t c s w a we _ a s y n d q [0 :1 5 ] d a t a v a l id d a t a w r it t e n t d q s u t d q h d nw i t csdw , t cshd mi n t y p ma x t cspw c s pul se w i dt h ( f or v a l i d w r i t e) 1 0 n s - - --- - - - --- - t cspi c s i g no r e d pu l s e w i dt h ( g l i t c h t o l e r a nce) -- --- - - - --- - 1 n s t w e s u w e s e tu p ti m e w i th r e s p e c t to r i s i n g e d g e o f c s 3 n s -- --- - - - --- - t w e h d w e h o l d ti m e w i th r e s p e c t to r i s i n g e d g e o f c s 2 n s -- --- - - - --- - t adsu a dd r e ss set u p t i m e w i t h r e spe c t t o r i si ng e dge of c s 8 n s -- --- - - - --- - t adh d a dd r e ss hol d t i m e w i t h r e spect t o r i si ng ed ge of c s 2 n s -- --- - - - --- - t csw a w e _ a s yn d e l a y f r om r i si ng ed ge o f c s 4 0ns t dqsu d q set u p t i m e af t e r r i si ng ed ge o f c s -- --- - - - --- - 2 0 n s t dqh d d q hol d t i m e w i t h r e spect t o r i si n g ed ge of c s 6 0 n s - - --- - - - --- - t csdw v a l i d d a ta w r i t e ti m e wr t r i si ng edg e o f c s -- --- - - - --- - 1 0 0 n s t cshd n w i, w e _ a s y n c h o l d ti m e wr t r i si ng e dge of c s 1 0 0 n s - - --- - - - --- - t w r c c s r i si ng edg e t o next c s r i si ng edg e ( w r i t e cy cl e t i m e ) 1 0 0 n s - - --- - - - --- - 10 www. honeywell.com
hmxnv0100 11 www. honeywell.com delaye d w r i t e c y c l e - d e l a y e d (w e_ a s yn > 4 0 n s a f t e r c s ) tw r d c cs t c s p w addr[ 0 : 1 5 ] a ddr v a l i d t ads u t a dh d we t w es u t w ehd tc s w a we _ a s y n dq [ 0 : 1 5] d a ta v a l i d d a ta w r itte n t d qs u t d qhd nw i tw a h d ty p m a x t c s p w c s p u l s e w i d t h ( f o r v a l i d w r i t e ) --- --- -- -- -- t c s p i c s ign o r e d puls e wid t h ( g lit c h t o ler anc e) - - - - - - 1 n s t w e s u w e s e t u p t i m e w i t h r e s p e c t t o r i s i n g e d g e o f c s --- --- -- -- -- t w e h d w e h o l d t i m e w i t h re s p e c t t o ri s i n g e d g e o f c s --- --- -- -- -- t a ds u a ddr es s s e t u p t i m e wit h r e s p ec t t o r i s i ng ed ge of cs - - - - - - - - - - - - t a d h d a d d r e s s h o l d t i m e w i t h re s p e c t t o ri s i n g e d g e o f c s --- --- -- -- -- t c s w a w e _ a s y n d e l a y f r o m ri s i n g e d g e o f c s --- --- -- -- -- t d q s u d q se t u p t i me t o r i si n g e d g e o f w e _ asyn - - - - - - - - - - - - t d qhd dq h o ld t i m e wr t r i si n g e d g e o f w e _ asyn - - - - - - - - - - - - t w a d w v alid dat a wr it e t i m e wr t r i si n g e d g e o f w e _ asyn c - - - - - - 6 0 n s tw a h d n w i,w e _ a s y n , h o l d ti m e wr t r i s i ng e d g e of w e _a s y n --- --- -- -- -- t w r d c c s r i s i ng ed ge t o nex t cs r i s i ng ed ge ( w r i t e c y c l e t i m e ) - - - - - - - - - - - - mi n 3n s 2n s 60 ns 40 ns 4n s 20 ns 10 ns -- -- -- t csw a + 6 0 n s 8n s 2n s -- -- -- power up timing duri ng po we r-up the r e are no re stri ction s on whi c h supply come s up first provided nwi is ass e rted (low). nwi is de-ass erted within 1us of both supplie s re ach i ng their 90% values.
hmxnv0100 pow e r- up seque nce vdd1 vdd2 1u s nw i power down timing pow e r-dow n sequence vdd1 vdd2 nw i 100ns quality and radi ation hardness ass urance hon e ywell m a intain s a hig h level of pro duct integrity through proc ess control, utilizing statistical pro c e ss a nd six sigma cont rol s . it is part of a ?t otal quality assura nce program?, the compute r -ba s ed p r o c e ss perfo rman ce tracking syste m and a ra dia t ion hard n e ss a ssuran c e stateg y. screeni n g level s h o neyw ell off e r s s e ve ral levels of device screei ng to m eet your nee d s . ?engine eri ng devices? are available with limited perfom r an ce and screeni n g for prototyp e developm ent and evalu a tio n testing. hi-rel level b and s devices u n derg o additio nal scree n ing p e r the requi rem ents of mil-s t d- 883. 12 www. honeywell.com
hmxnv0100 reliabili ty hon e ywell un derstand s the stringe nt reliability req u irem ents tha t space and defen se sy stems requi re. hon e ywell ha s extensive experience in reli ability testing on program s of this nature. reliability attributes of the soi proce s s we re chara c te rized by testing spe c ia lly design ed structu r e s to evaluate failu re me cha n isms incl udin g hot carrie rs, ele c t r o migration, and time- depe ndent di electri c b r ea kdown. the results a r e fe edba ck to improve the p r o c e ss to ensu r e the highe st relia b ility product s . in addition, o u r produ cts a r e su bje c ted to dynamic, a c celerate d life tests. the packa ge s used are q ualifi ed throu gh m i l- std-8 83, tm 5005 cl ass s. the produ ct scree n ing flo w ca n be mo dified to meet the spe c ific requi reme nts. qu ality conform ance testing is p e rf orme d as a n option on all production lots to ens ure on-goi ng reliability. package outline the 64 le ad shielded ceramic qfp pa ckage sho w n is preli m ina r y and is subje c t to change, inclu d ing exte rnal capa cito rs. the outline is for refe ren c e only. vs s v dd2 vs s v dd2 1 10 11 38 39 47 vs s v dd2 vs s v dd2 48 75 21 5 22 0 22 5 23 0 23 5 24 0 24 5 25 0 25 5 26 0 26 5 27 0 27 5 28 0 14 5 15 0 15 5 160 16 5 17 0 17 5 18 0 18 5 19 0 19 5 20 0 20 5 21 0 75 80 85 90 95 10 0 10 5 11 0 11 5 12 0 12 5 13 0 13 5 14 0 51 0 1 5 2 02 5 3 0 3 5 4 0 4 55 0 5 56 06 5 7 0 ho n e y we ll ds e s 22 02 xx xx vs s v dd1 v dd2 .9 0 0 .9 0 0 .0 1 8 .0 5 0 .1 5 0 .0 7 5 13 www. honeywell.com
hmxnv0100 ordering information (1) h x (1) t o order parts or obtain te chnic a l assista n ce, call 1- 80 0 - 323- 829 5 (2) engi neer in g mode l descri p tion: paramet e rs are te sted from-55 to 12 50 c, 24-ho ur bur n-in, no ra di ation guar ante e . 0100 s h a sourc e h = hone yw e l l pro ces s x = soi pack ag e de sig n a tio n a = 64 lead q f p part numbe r 010 0 = 1 meg screen lev e l v = qml class v q = qml class q s = level s b = level b e = eng. model (2) t o t al do se hard n ess r = 1x1 0 5 rad (sio 2 ) f = 3x10 5 rad ( s io 2 ) h = 1x1 0 6 rad (sio 2 ) n = no level guarante e d nv part t y pe nv = non vola tile for more information about hone y w e ll?s mram product and our famil y of me mory and asic products and services, visit www. my spaceparts.com. hone y w ell reserv es the right to m a ke changes to a n y products or te chnol og y herein to improve reliab ility , f unction or de sign. h one ywell does not assume an y liability arising out of t he application or use of an y p r odu ct or circuit described her ein; neith er does it conve y a n y license und er its patent rights no r the rights of othe rs. honeyw e ll international inc. a erospace electronics s y st ems defens e & spa c e electron ics s y stems 120 01 hi gh w a y 5 5 pl y m outh, mn 554 41 1-80 0-32 3-8 2 9 5 w w w .h on eyw e ll .co m form #9 00232 ma y 200 5 ?2005 hon e y well international inc. 14 www. honeywell.com

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