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mos integrated circuit pd8828a 7500 pixels 3 color ccd linear image sensor data sheet the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. document no. s17963ej2v0ds00 (2nd edition) date published october 2006 ns cp (k) printed in japan the mark '' " shows major revised points. the revised points can be easily searched by copying an "" in the pdf file and specifying it in the "find what:" field. 2006 description the pd8828a is a high-speed and high sensitive color ccd (charge coupled device) linear image sensor which changes optical images to electrical signal and has the function of color separation. the pd8828a has 3 rows of 7500 pixels, and it is a 2-output/c olor type ccd sensor with 2 rows/color of charge transfer register, which transfers the photo signal elec trons of 7500 pixels separately in odd and even pixels. therefore, it is suitable for 600 dpi/a3 high-s peed color digital copiers, color scanners and so on. features ? valid photocell : 7500 pixels 3 ? photocell pitch : 4.7 m ? line spacing : 37.6 m (8 lines) red line-green line, green line-blue line ? color filter : primary colors (r ed, green, and blue), pigment filter light resistance is 10 7 lx ? hour with standard sunlight and ultraviolet cut filter (l40) ? resolution : 24 dot/mm a3 (297 420 mm) size (shorter side) ? data rate : 40 mhz max. (20 mhz/ch max.) ? output type : 2 outputs in phase/color ? power supply : +10 v ? drive clock level : cmos output under 5 v operation ? on-chip circuits : reset feed-through level clamp circuit voltage amplifiers ordering information part number package pd8828ad-a ccd linear image sensor 22-pin cerami c dip (cerdip) (10.16 mm (400)) remark the pd8828ad-a is a lead-free product.
2 pd8828a data sheet s17963ej2v0ds block diagram d27 d128 s7499 : : s1 s2 photocell (blue) s7500 d129 : d134 transfer gate transfer gate ccd analog shift register ccd analog shift register gnd 11 16 gnd d27 d128 s7499 : : s1 s2 photocell (green) s7500 d129 : d134 transfer gate transfer gate ccd analog shift register ccd analog shift register d27 d128 s7499 : : s1 s2 photocell (red) s7500 d129 : d134 transfer gate transfer gate ccd analog shift register ccd analog shift register 19 v out 2 (blue, even) 20 v out 1 (blue, odd) 22 v out 3 (green, odd) 1 v out 4 (green, even) 3 v out 6 (red, even) 4 v out 5 (red, odd) 2 gnd 18 v od 1 5 v od 2 13 17 cp 2l 7 6 r 14 1 15 2 8 1 gnd 9 2 10 tg
3 data sheet s17963ej2v0ds pd8828a pin configuration (top view) ccd linear image sensor 22-pin cerami c dip (cerdip) (10.16 mm (400)) pd8828ad-a output signal 4 (green-even) output signal 5 (red-odd) output signal 6 (red-even) output unit drain voltage 2 reset gate clock ground shift register clock 2 shift register clock 1 transfer gate clock v out 4 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 v out 5 v out 6 v od 2 r gnd 2 1 tg red green blue 7500 v out 3 v out 1 v out 2 v od 1 cp 2l gnd 2 1 nc output signal 3 (green-odd) output signal 1 (blue-odd) output signal 2 (blue-even) output unit drain voltage 1 reset feed-through level clamp clock ground shift register clock 2 shift register clock 1 no connection last stage shift register clock 2l 7500 7500 1 ground gnd ground gnd gnd ground 1 1 photocell structure diagram 2.5 m 4.7 m 2.2 m channel stopper aluminum shield
4 pd8828a data sheet s17963ej2v0ds absolute maximum ratings (t a = +25c) parameter symbol ratings unit output drain voltage v od 1, v od 2 ?0.3 to +12.0 v shift register clock voltage v 1 , v 2 ?0.3 to +8.0 v last stage shift register clock voltage v 2l ?0.3 to +8.0 v reset gate clock voltage v r ?0.3 to +8.0 v reset feed-through level clamp clock voltage v cp ?0.3 to +8.0 v transfer gate clock voltage v tg ?0.3 to +8.0 v operating ambient temperature note t a 0 to +60 ? c storage temperature t stg ?40 to +100 ? c note the operating ambient tem perature is defined as an at mosphere temperature in a point 10 mm away on the substrate, and 10 mm away from t he short side of package 1 pin. us e at the condition without dewy condensation. caution product quality may suffer if the absolute m aximum rating is exceeded ev en momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating conditions (t a = +25c) parameter symbol min. typ. max. unit output drain voltage v od 1, v od 2 9.5 10.0 10.5 v shift register clock high level v 1h , v 2h 4.75 5.0 6.0 v shift register clock low level v 1l , v 2l ?0.3 0.0 +0.5 v last stage shift register clock high level v 2lh 4.75 5.0 6.0 v last stage shift register clock low level v 2ll ?0.3 0.0 +0.5 v reset gate clock high level v rh 4.75 5.0 5.5 v reset gate clock low level v rl -0.3 0.0 +0.5 v reset feed-through level clamp clock high level v cph 4.75 5.0 6.0 v reset feed-through level clamp clock low level v cpl ?0.3 0.0 +0.5 v transfer gate clock high level note v tgh 4.75 v 1h v 1h v transfer gate clock low level v tgl ?0.3 0.0 +0.5 v shift register clock amplitude v 1p-p , v 2p-p 4.75 5.0 6.3 v last stage shift register clock amplitude v 2lp-p 4.75 5.0 6.3 v reset gate clock amplitude v rp-p 4.75 5.0 6.3 v reset feed-through level clamp clock amplitude v cpp-p 4.5 5.0 6.3 v transfer gate clock amplitude v tgp-p 4.75 5.0 6.3 v data rate 2 f r 0.2 2 40 mhz note when transfer gate clock high level (v tgh ) is higher than shift register clock high level (v 1h ), image lag can increase.
5 data sheet s17963ej2v0ds pd8828a electrical characteristics t a = +25c, v od = +10 v, f r = 1 mhz, data rate = 2 mhz, storage time = 10 ms, input clock = 5 v p-p light source: 3200 k halogen lamp + c-500s (infrared cut filter, t = 1 mm)+ ha-50 (heat absorbing filter, t = 3 mm) (except res ponse 2) parameter symbol test conditions min. typ. max. unit saturation voltage vsat 1.5 2.0 ? v red ser ? 0.17 ? lx ? s green seg ? 0.2 ? lx ? s saturation exposure blue seb 3200k+c500s+ha50 ? 0.37 ? lx ? s photo response non-uniformity prnu v out = 1 v ? 6.0 18.0 % average dark signal ads light shielding ? 1.0 5.0 mv dark signal non-uniformity dsnu light shielding ? 2.0 10.0 mv power consumption 1 p od 1 ? 130 150 mw power consumption 2 p od 2 ? 340 400 mw output impedance z o ? 0.2 0.4 k red r r 8.47 12.1 15.73 v/lx ? s green r g 6.93 9.9 12.87 v/lx ? s response 1 blue r b 3200k+c500s+ha50 3.78 5.4 7.02 v/lx ? s red r r 6.30 9.0 11.70 v/lx ? s green r g 5.81 8.3 10.79 v/lx ? s response 2 (corresponding value from response 1) blue r b a light source+cm500s 2.66 3.8 4.94 v/lx ? s red ? 610 ? nm green ? 535 ? nm response peak blue ? 460 ? nm image lag il v out = 1 v ? 3.0 5.0 % offset level v os 3.9 4.9 5.9 v output fall delay time note t d 13 15 17 ns register imbalance ri v out = 1 v ? 0 8 % total transfer efficiency tte v out = 1 v, f r = 20 mhz 94 98 ? % dr1 v sat /dsnu ? 1000 ? times dynamic range dr2 v sat / ? 1333 ? times reset feed-through noise rftn light shielding ?1000 ?200 +500 mv light shielding random noise dark bit clamp, t17 > 8 ns ? 1.5 ? mv note t d is defined as period from 10% of 2l of v out 1 to v out 6, and td is reference data after v out 1 to v out 6 pins with fet proving.
6 pd8828a data sheet s17963ej2v0ds input pin capacitance (t a = +25c, v od = +10 v) parameter symbol pin pin no min. typ. max. unit 1 8 360 400 440 pf c 1 1 14 360 400 440 pf 1 total capacitance 720 800 880 pf 2 9 360 400 440 pf c 2 2 15 360 400 440 pf shift register clock pin capacitance note 2 total capacitance 720 800 880 pf last stage shift register clock pin capacitance c 2l 2l 17 14 15 17 pf reset gate clock pin capacitance c r r 6 20 22 24 pf reset feed-through level clamp clock pin capacitance c cp cp 13 35 39 43 pf transfer gate clock pin capacitance c tg tg 10 225 250 275 pf note c 1 , c 2 are equivalent capacitance with driving device, including the co-capacitance between 1 and 2. remark pins 8 and 14 ( 1), pins 9 and 15 ( 2) are each connected in side of the device.
pd8828a data sheet s17963ej2v0ds 7 timing chart 1 1 2 2l tg r note 1 valid photocells (3750 pixels/channel) invalid photocell (3 pixels/channel) optical black (48 pixels/channel) dummy cell (13 pixels/channel) a invalid photocell (3 pixels/channel) cp (bit clamp mode) 5 25 1 27 29 121 123 125 127 129 3 7627 131 7625 119 31 7629 7631 7633 v out 2, v out 4, v out 6 4 6 26 28 30 122 124 126 128 130 2 7628 132 7626 32 120 7630 7632 7634 v out 1, v out 3, v out 5 cp (line clamp mode) note 2 notes 1. set the r and cp to low level during this period (a). 2. the r and cp pulses which surrounded with the dashed line are omissible at the bit clamp mode.
pd8828a 8 data sheet s17963ej2v0ds timing chart 2 (bit clamp mode) 10% 10% t6 t7 90% 90% 2 1 r 2l cp t d 10% v out 1 to v out 6 rftn v os + ? t10 10% 90% t7l t9 10% 90% t6l t8 90% t16 t17 t12 t14 t13 t15 10% 90% 10% 10% caution "10%" and "90%" define as the clock voltage with 5 v p-p condition. i.e. "10%" shows 0.5 v, "90%" shows 4.5 v
pd8828a data sheet s17963ej2v0ds 9 timing chart 3 (line clamp mode) 10% 10% t6 t7 90% 90% 2 1 r 2l cp t d 10% v out 1 to v out 6 rftn v os + ? t10 10% 90% t7l t9 10% 90% t6l t8 10% 90% 10% low t18 caution "10%" and "90%" define as the clock voltage with 5 v p-p condition. i.e. "10%" shows 0.5 v, "90%" shows 4.5 v
10 pd8828a data sheet s17963ej2v0ds timing chart 4 (bit clamp mode, line clamp mode) 1 90% 90% r 10% 90% t16 t12 t11 t13 t14 t5 t17 t10 t9 t8 tg t2 90% 10% t4 t1 t3 10% 90% cp 10% 10% 90% caution "10%" and "90%" define as the clock voltage with 5 v p-p condition. i.e. "10%" shows 0.5 v, "90%" shows 4.5 v symbol min. typ. max. unit t1, t5 100 200 2000 ns t2, t4 0 10 ? ns t3 500 1000 10000 ns t6, t7 0 10 ? ns t6l, t7l 0 3 ? ns t8, t10 0 3 ? ns t9 10 125 ? ns t11 0 250 ? ns t12, t14 0 3 ? ns t13 10 125 ? ns t15 0 250 ? ns t16 0 125 ? ns t17 8 125 ? ns t18 5 125 ? ns
11 pd8828a data sheet s17963ej2v0ds cross points characteristics 1, 2 cross points 1 2 1.5 v or more 1.5 v or more 1, 2l cross points 1 2l 1.5 v or more 0.2 v or more remark adjust cross points of ( 1, 2) and ( 1, 2l) with input resistance of each pin. clock high/low level width characteristics 1, 2 4.75 v min. 7 ns 2l 4.75 v min. 7 ns 1, 2 0.25 v min. 7 ns 2l 0.25 v min. 7 ns
12 pd8828a data sheet s17963ej2v0ds definitions of characteristic items 1. saturation voltage : v sat output signal voltage at which the response linearity is lost. 2. saturation exposure : se product of intensity of illuminati on (lx) and storage time (s) when saturation of output voltage occurs. 3. photo response non-uniformity : prnu the output signal non-uniformity of all the valid pixels w hen the photosensitive su rface is applied with the light of uniform illumination. this is calculated by the following formula. prnu (%) = x 100 x x j : output voltage of valid pixel number j x : maximum of | x j ? x | x = x j 3750 j=1 3750 register dark dc level v out x x 4. average dark signal : ads average output signal voltage of all the valid pixels at light shielding. this is calculated by the following formula. ads (mv) = d j 3750 j=1 3750 d j : dark signal of valid pixel number j
13 pd8828a data sheet s17963ej2v0ds 5. dark signal non-uniformity : dsnu absolute maximum of the difference between ads and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. this is calculated by t he following formula, and it is defined by each six of them. dsnu (mv) : maximum of | d j ? ads | j = 1 to 3750 d j : dark signal of valid pixel number j register dark dc level ads dsnu v out 6. output impedance : z o impedance of the output pins viewed from outside. 7. response : r output voltage divided by exposure (lx?s). note that the response varies with a li ght source (spectral characteristic). 8. image lag : il the rate between the last output voltage and t he next one after read out the data of a line. tg light v out on off v out v 1 il (%) = v 1 / v out 100 9. register imbalance : ri the rate of the difference between the averages of the out put voltage of odd and ev en pixels, against the average output voltage of all the valid pixels. ri (%) = 100 n j=1 v j n 1 n 2 (v 2j -1 ? v 2j ) j=1 2 n n : number of valid pixels v j : output voltage of each pixel
14 pd8828a data sheet s17963ej2v0ds 10. light shielding random noise : dark light shielding random noise dark is defined as the standard deviation of a valid pixel output signal with 100 times (= 100 lines) data sampling at dark (light shielding). v i :a valid pixel output signal among all of the valid pixels for each color. (mv) = 100 100 i=1 ( v i ? v ) 2 v = 100 100 i=1 v i 1 v out v 1 line1 v 2 line2 v 100 line100 , this is measured by the dc level sampling of only the signal level, not by cds (correlated double sampling) 11. total transfer efficiently : tte the total transfer rate of ccd analog shift register. this is calculated by the following formula, it is defined by each odd output. tte(%) = (1-vb/average output of all the valid pixels) 100 vb vb: the spilt pixel output (7635th pixel) 7631 7633 7635
15 pd8828a data sheet s17963ej2v0ds standard characteristic curves (reference value) dark output temperature characteristic relative output voltage 0 10 20 30 40 50 0.1 0.25 0.5 1 2 4 8 operating ambient temperature t a ( c) storage time output voltage characteristic (t a = +25 c) relative output voltage 1 5 10 0.1 0.2 1 2 storage time (ms) response ration (%) total spectral respon se characteristics (without infrared cut filter and heat absorbing filter) (t a = 25c) wavelength (nm) 0 20 40 60 80 100 400 500 600 700 800 b gr
16 pd8828a data sheet s17963ej2v0ds application circuit example +10 v 2 47 f/25 v 47 f/25 v 0.068 f a equivalent circuit b4 b3 b6 b5 b1 b2 a a 1 2 3 4 5 6 7 8 9 10 11 v out 4 gnd v out 6 v out 5 v od 2 r gnd 1 2 tg gnd v out 3 gnd v out 1 v out 2 v od 1 2l gnd 2 1 cp nc 22 21 20 19 18 17 16 15 14 13 12 47 47 2 2 3 3 2 2 3 3 47 47 10 f/16 v 0.1 f +5 v 0.1 f 10 f/16 v +5 v 1 2 r tg 2l 2 1 cp note 1 note 2 note 2 inverter: 74ac04 inverter: 74ac04 notes 1. arrange the circuit a near each power supply terminal (v od 1, v od 2) to prevent the interference between v od 1 and v od 2. 2. connects the 3 inverters for each 1 and 2 pin. caution connect the no connection pins (nc) to gnd. 47 ccd v out b1 to b6 equivalent circuit 2sa1206 4.7 k 110 1 k +10 v + 47 f/25 v 2sc1842
17 pd8828a data sheet s17963ej2v0ds package drawing pd8828ad-a ccd linear image sensor 22-pin ceramic dip (cerdip) (10.16 mm (400)) name refractive index 0.3 42.2 0.25 3.4 1 0.3 the 1st valid pixel 9.65 0.3 10.16 2.54 0.46 0.06 1.02 0.15 4.33 0.5 4.68 0.5 (5.37) glass cap 1 1st valid pixel center of pin 1 2 photosensitive surface of ccd chip bottom of package 3 photosensitive surface of ccd chip top of glass cap 4 the shaded portions are overflow prohibited area of the seal glass. 1.5 (1.6) 0~10 48.6 0.5 47.5 9.25 0.7 1.60 0.25 25.4 0.25 0.05 2.73 (unit : mm) dimensions 3 2 4 4 3.0 3.0 22 12 11 1
18 pd8828a data sheet s17963ej2v0ds recommended soldering conditions when soldering this product, it is highly recomm ended to observe the conditions as shown below. if other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. type of through-hole device pd8828ad-a: ccd linear image sensor 22-pin ceramic dip (cerdip) (10.16 mm (400)) process conditions partial heating method pin temperature: 380c or bel ow, heat time: 3 seconds or less (per pin). cautions 1. during assembly care should be taken to pr event solder or flux fr om contacting the glass cap. the optical characteristics could be degraded by such contact. 2. soldering by the solder flow method may ha ve deleterious effects on prevention of glass cap soiling and heat resistance. so the method cannot be guaranteed.
19 pd8828a data sheet s17963ej2v0ds notes on handling the packages mounting of the package the application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. particular care should be taken when mounting the package on the circuit board. don't have any object come in contact with glass cap. you should not reform the lead frame. we recommended to use a ic-inserter when you assemble to pcb. also, be care that the any of the following can cause the package to crack or dust to be generated. 1. applying heat to the external leads for an extended period of time with soldering iron. 2. applying repetitive bending stress to the external leads. 3. rapid cooling or heating 1 glass cap don?t either touch glass cap surface by hand or have any object come in contact with glass cap surface. care should be taken to avoid mechanical or thermal shock because the glass cap is easily to damage. for dirt stuck through electricity ionized air is recommended. 2 operate and storage environments 3 operate in clean environments. ccd image sensors are precise optical equipment that should not be subject to mechanical shocks. exposure to high temperatures or humidity will affect the characteristics. so avoid storage or usage in such conditions. keep in a case to protect from dust and dirt. dew condensation may occur on ccd image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. avoid such rapid temperature changes. for more details, refer to our document "review of quality and reliability handbook" (c12769e) electrostatic breakdown ccd image sensor is protected against static electricity, but destruction due to static electricity is sometimes detected. before handling be sure to take the following protective measures. 1. ground the tools such as soldering iron, radio cutting pliers of or pincer. 2. install a conductive mat or on the floor or working table to prevent the generation of static electricity. 3. either handle bare handed or use non-chargeable gloves, clothes or material. 4. ionized air is recommended for discharge when handling ccd image sensor. 5. for the shipment of mounted substrates, use box treated for prevention of static charges. 6. anyone who is handling ccd image sensors, mounting them on pcbs or testing or inspecting pcbs on which ccd image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 m . 4
20 pd8828a data sheet s17963ej2v0ds [memo]
21 pd8828a data sheet s17963ej2v0ds [memo]
22 pd8828a data sheet s17963ej2v0ds [memo]
23 pd8828a data sheet s17963ej2v0ds 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
pd8828a the information in this document is current as of october, 2006. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":

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