rev 2.1, october 22, 2007 page 1 of 11 2200 laurelwood road, santa clara, ca 95054 tel: (408) 855-0555 fax: (408) 855-0550 www.spectralinear.com sl2305 ? low jitter and skew 10 to 140 mhz zero dela y buffer ( zdb ) key features ? 10 to 140 mhz operating frequency range ? low output clock jitter: - 140 ps-max c-c-j at 66 mhz ? low output-to-output skew: 150 ps-max ? low product-to-product skew: 400 ps-max ? 3.3 v power supply range ? low power dissipation: - 14 ma-max at 66mhz - 26 ma-max at 133 mhz ? one input drives 5 outputs organized as 4+1 ? spreadthru? pll that allows use of sscg ? standard and high-drive options ? available in 8-pin soic and tssop packages ? available in commercial and industrial grades applications ? printers and mfps ? digital copiers ? pcs and work stations ? dtv ? routers, switchers and servers ? digital embeded systems description the sl2305 is a low skew, low jitter and low power zero delay buffer (zdb) designed to produce up to five (5) clock outputs from one (1) reference input clock for high speed clock distribution applications. the product has an on-chip pll which locks to the input clock at clkin and receives its feedback internally from the clkout pin. the sl2305 is available with two (2) drive strength versions. the -1 is the standard-drive version and -1h is the high- drive version. the sl2305 high-drive version operates up to 140mhz and the standard drive version -1 operates up to 100. the sl2305 enter into power-down (pd) mode if the input at clkin is dc (0 to vdd). in this power-down state all five (5) outputs are tri-stated and the pll is turned off leading to less than 12 a-max of power supply current draw. benefits ? up to five (5) distribution of input clock ? standard and high-drive levels to control impedance level, frequency range and emi ? low jitter and skew ? low power dissipation ? low cost block diagram
rev 2.1, october 22, 2007 page 2 of 11 sl2305 pin configuration 8-pin soic or tssop pin description pin number pin name pin type pin description 1 clkin input reference frequency clock input. weak pull-down (250k ? ). 2 clk2 output buffered clock output weak pull-down (250k ?). 3 clk1 output buffered clock output. weak pull-down (250k ? ). 4 gnd power power ground. 5 clk3 output buffered clock output. weak pull-down (250k ? ). 6 vdd power 3.3v power supply. 7 clk4 output buffered clock output. weak pull-down (250k ? ). 8 clkout output buffered clock output, used for internal feedback to pll input. weak pull- down (250k ?).
rev 2.1, october 22, 2007 page 3 of 11 sl2305 general description the sl2305 is a low skew, low jitter zero delay buffer with very low operating power supply current (idd). the product includes an on-chip high performance pll that locks into the input reference clock and produces five (5) output clock drivers tracking the input reference clock for systems requiring clock distribution. in addition to clkout that is used for internal pll feedback, there is a single bank with four (4) outputs, bringing the number of total available output clocks to five (5). input and output frequency range the input and output frequency range is the same. but, the frequency range depends on the drive levels and load capacitance (cl) as given in the below table 1. drive cl(pf) min(mhz) max(mhz) high (-1h) 15 10 140 high (-1h) 30 10 100 std (-1) 15 10 100 std (-1) 30 10 66 table 1. input/output frequency range if the input clock frequency is dc (0 to vdd), this is detected by an input detection circuitry and all five (5) clock outputs are forced to hi-z. the pll is shutdown to save power. in this shutdown state, the product draws less than 12 a-max supply current. spreadthru ? feature if a spread spectrum clock (ssc) were to be used as an input clock, the sl2305 is designed to pass the modulated spread spectrum clock (ssc) signal from its clkin (reference) input to the output clocks. the same spread characteristics at the input are passed through the pll and drivers without any degradation in spread percent (%), spread profile and modulation frequency. high and low-drive product options the sl2305 is offered with high-drive ?-1h? and standard- drive ?-1? options. these drive options enable the users to control load levels, frequency range and emi control. refer to the ac electrical tables for the details. skew and zero delay all outputs should drive the similar load to achieve output- to-output and input-to-output skew specifications given in the ac electrical tables. however, zero delay between input and outputs can be adjusted by changing the loading of clkout relative to the other clock outputs since clkout is the feedback to the pll. power supply range (vdd) the sl2305 is designed to operate from 3.0v (min) to 3.6v (max), complying with vdd=3.3v+/-10% requirement. an internal on-chip voltage regulator is used to supply pll constant power supply of 1.8v, leading to a consistent and stable pll electrical performance in terms of skew, jitter and power dissipation. temperature range and packages the sl2305 is offered with commercial temperature range of 0 to +70c (c-grade) and industrial temperature range of -40 to +85c (i-grade). the sl2305 is available in 8-pin soic (150-mil) and 8-pin tssop (173-mil) packages. sl23ep05 refer to sl23ep05 for extended frequency operation from 10 to 220mhz and 2.5v to 3.3v power supply operation range.
rev 2.1, october 22, 2007 page 4 of 11 sl2305 absolute maximum ratings description condition min max unit supply voltage, vdd ? 0.5 4.6 v all inputs and outputs ? 0.5 vdd+0.5 v ambient operating temperature in operation, c-grade 0 70 c ambient operating temperature in operation, i-grade ? 40 85 c storage temperature no power is applied ? 65 150 c junction temperature in operation, power is applied ? 125 c soldering temperature ? 260 c esd rating (human body model) jedec22-a114d -4,000 4,000 v esd rating (charge device model) jedec22-c101c -1,500 1,500 v esd rating (machine model) jedec22-a115d -250 250 v latch-up 125c -200 200 ma operating conditions: unless otherwise stated vdd=3.3v+/-10% and both c and i grades symbol description condition min max unit vdd 3.3v supply voltage 3.3v+/-10% 3.0 3.6 v commercial 0 70 c ta operating temperature(ambient) industrial ?40 85 c 10 to 140 mhz, -1h high drive ? 15 pf 10 to 100 mhz, -1h high drive ? 30 pf 10 to 100mhz, -1 standard drive ? 15 pf cload load capacitance 10 to 66mhz, -1 standard drive ? 30 pf cin input capacitance clkin pin ? 7 pf tpu power-up time power-up time for all vdds to reach minimum vdd voltage (vdd=3.0v). 0.05 100 ms clbw closed-loop bandwidth 3.3v, (typical) 1.2 mhz 3.3v (typical), -1h high drive 22 ? zout output impedance 3.3v (typical), -1 standard drive 32 ?
rev 2.1, october 22, 2007 page 5 of 11 sl2305 dc electrical specifications: unless otherwise stated vdd=3.3v+/-10% and both c and i grades symbol description condition min max unit vdd supply voltage 3.0 3.6 v vil input low voltage clkin (pin-1) ? 0.8 v vih input high voltage clkin (pin-1) 2.0 v dd +0.3 v iil input low current clkin, 0 < vin < 0.8v ? 25 a iih input high current clkin, vin = vdd ? 50 a iol = 8 ma (standard drive) ? 0.4 v vol output low voltage (all outputs) iol = 12 ma (high drive) ? 0.4 v ioh = ?8 ma (standard drive) 2.4 ? v voh output high voltage (all outputs) ioh = ?12 ma (high drive) 2.4 ? v c-grade, power-down if clkin=0 to vdd or input is floating ? 12 a iddpd power down supply current clkin=0 to vdd i-grade, power-down if clkin=0 to vdd or input is floating ? 25 a idd1 power supply current all outputs cl=0, 33mhz clkin ? 8 ma idd2 power supply current all outputs cl=0, 66mhz clkin ? 14 ma idd3 power supply current all outputs cl=0, 100mhz clkin ? 20 ma idd4 power supply current all outputs cl=0, 133mhz clkin ? 26 ma rpd pull-down resistors pins-1/2/3/5/7/8, 250k ? -typ 175 325 k ?
rev 2.1, october 22, 2007 page 6 of 11 sl2305 switching specifications: unless otherwise stated vdd=3.3v+/-10% and both c and i grades symbol description condition min max unit high drive (-1h). all outputs cl=15pf 10 140 mhz high drive (-1h), all outputs cl=30pf 10 100 mhz standard drive, (-1), all outputs cl=15pf 10 100 mhz fmax1 maximum frequency [1] (input=output ) all active pll modes standard drive, (-1), all outputs cl=30pf 10 66 mhz indc input duty cycle measured at 1.4v, fout=66mhz, cl=15pf 30 70 % outdc1 output duty cycle [2] measured at 1.4v, fout 50mhz, cl=15pf 40 60 % outdc2 output duty cycle [2] measured at 1.4v, fout 50mhz, cl=15pf 45 55 % high drive (-1h), cl=10pf ? 1.5 ns high drive (-1h), cl=30pf ? 1.8 ns standard drive (-1), cl=10pf ? 2.2 ns tr/f rise, fall time (3.3v) [2] (measured at: 0.8 to 2.0v) standard drive (-1), cl=30pf ? 2.5 ns t1 output-to-output skew [2] (measured at vdd/2) all outputs cl=0 or equally loaded, -1 or -1h drives ? 150 ps t2 product-to-product skew [2] (measured at vdd/2) all outputs cl=0 or equally loaded, -1 or -1h drives ? 400 ps t3 delay time, clkin rising edge to clkout rising edge [2] measured at vdd/2 ?220 220 ps tplock pll lock time [2] time from 90% of vdd to valid clocks on all the output clocks ? 1.0 ms fin=fout=66 mhz, rev 2.1, october 22, 2007 page 7 of 11 sl2305 external components & design considerations typical application schematic comments and recommendations decoupling capacitor: a decoupling capacitor of 0.1 f must be used between vdd and vss on the pins 6 and 4. place the capacitor on the component side of the pcb as close to the vdd pin as possible. the pcb trace to the vdd pin and to the gnd via should be kept as short as possible. do not use vias between the decoupling capacitor and the vdd pin. series termination resistor : a series termination resistor is recommended if the distance between the outputs and the load is over 1 ? inch. the nominal impedance of the clock outputs are about 30 ? . use 20 ? resistor in series with the output to terminate 50 ? trace impedance and place 20 ? resistor as close to the clock outputs as possible. zero delay and skew control: all outputs and clkin pins should be loaded with the same load to achieve ?zero delay? between the clkin and the outputs. the clkout pin is connected to clkin internally on-chip for internal feedback to pll, and sees an additional 2 pf load with respect to the clock pins. for applications requiring zero input/output delay, the load at the all output pins including the clkout pin must be the same. if any delay adjustment is required, the capacitance at the clkout pin could be increased or decreased to in crease or decrease the delay between clocks and clkin. for minimum pin-to-pin skew, the external load at the clock outputs must be the same.
rev 2.1, october 22, 2007 page 8 of 11 sl2305 switching waveforms figure 1. output to output skew figure 2. input- to-output skew figure 3. part-to-part skew
rev 2.1, october 22, 2007 page 9 of 11 sl2305 package outline and package dimensions 8-pin soic package (150-mil) thermal characteristics parameter symbol condition min typ max unit ja still air - 150 - c/w ja 1m/s air flow - 140 - c/w thermal resistance junction to ambient ja 3m/s air flow - 120 - c/w thermal resistance junction to case jc independent of air flow - 40 - c/w
rev 2.1, october 22, 2007 page 10 of 11 sl2305 package outline and package dimensions 8-pin tssop package (4.4-mm) thermal characteristics parameter symbol condition min typ max unit still air - 110 - c/w 1m/s air flow - 100 - c/w thermal resistance junction to ambient 3m/s air flow - 80 - c/w thermal resistance junction to case independent of air flow - 35 - c/w
rev 2.1, october 22, 2007 page 11 of 11 sl2305 ordering information [3] ordering number marking shipping package package temperature sl2305sc-1 sl2305sc-1 tube 8-pin soic 0 to 70c sl2305sc-1t sl2305sc-1 tape and reel 8-pin soic 0 to 70c sl2305si-1 sl2305si-1 tube 8-pin soic -40 to 85c sl2305si-1t sl2305si-1 tape and reel 8-pin soic -40 to 85c sl2305sc-1h sl2305sc-1h tube 8-pin soic 0 to 70c sl2305sc-1ht sl2305sc-1h tape and reel 8-pin soic 0 to 70c sl2305si-1h sl2305si-1h tube 8-pin soic -40 to 85c sl2305si-1ht sl2305si-1h tape and reel 8-pin soic -40 to 85c sl2305zc-1 sl2305zc-1 tube 8-pin tssop 0 to 70c sl2305zc-1t sl2305zc-1 tape and reel 8-pin tssop 0 to 70c sl2305zi-1 sl2305zi-1 tube 8-pin tssop -40 to 85c sl2305zi-1t sl2305zi-1 tape and reel 8-pin tssop -40 to 85c sl2305zc-1h sl2305zc-1h tube 8-pin tssop 0 to 70c SL2305ZC-1HT sl2305zc-1h tape and reel 8-pin tssop 0 to 70c sl2305zi-1h sl2305zi-1h tube 8-pin tssop -40 to 85c sl2305zi-1ht sl2305zi-1h tape and reel 8-pin tssop -40 to 85c notes: 3. the sl2305 products are rohs compliant. while sli has reviewed all information herein for accuracy and re liability, spectra linear inc. assumes no responsibility for t he use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. this produ ct is intended for use in normal commercial applications and is not warranted not is it intended for use in life support, critical medical instrum ents, or any other application requiring extended temperature r ange, high reliability, or any other extraordinary environmental requirements unles s pursuant to additional processing by spectra linear inc., and an expressed written agreement by spectra linear inc. spectra linear inc. re serves the right to change any circuitry or specification without notice.
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