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3 - 1 high speed logic - smt 3 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC987LP5E v00.0611 low noise 1:9 fanout buffer dc - 8 ghz functional diagram general description the HMC987LP5E 1-to-9 fanout buffer is designed for low noise clock distribution. it is intended to generate relatively square wave outputs with rise/ fall times < 100 ps. the low skew and jitter outputs of the HMC987LP5E, combined with its fast rise/ fall times, leads to controllable low-noise switching of downstream circuits such as mixers, adcs/dacs or serdes devices. the noise foor is particularly important in these applications, when the clock- network bandwidth is wide enough to allow square- wave switching. driven at 2 ghz, outputs of the HMC987LP5E have a noise foor of -166 dbc/hz, corresponding to a jitter density of 0.6 asec/rthz - or 50 fs over an 8 ghz bandwidth. the input stage can be driven single-ended or differentially, in a variety of signal formats (cml, lvds, lvpecl or cmos), ac or dc coupled. the input stage also features adjustable input impedance. it has 8 lvpecl outputs, and 1 cml output with adjustable swing/power-level in 3 db steps. individual output stages may be enabled or disabled for power-savings when not required using either hardware control pins, or under control of a serial-port interface. features ultra low noise floor: -166 dbc/hz @ 2 ghz wideband: dc - 8 ghz operating frequency flexible input interface: lvpecl, lvds, cml, cmos compatible ac or dc coupling on-chip termination 50 or 150 ? (100/300 ? diff.) multiple output drivers: up to 8 differential or 16 single-ended lvpecl outputs: 800 mvpp into 50 ? single-ended (+3 dbm fo) one adjustable power cml/rf output: -9 to 3 dbm single-ended serial or parallel control, hardware chip-enable power-down current < 1 ua 32 lead 5x5 mm smt package 25 mm 2 typical applications the HMC987LP5E is suitable for: ? sonet, fibre channel, gige clock distribution ? adc/dac clock distribution ? low skew and jitter clock or data fanout ? wireless/wired communications ? level translation ? high performance instrumentation ? medical imaging ? single-ended to differential conversion
3 - 2 high speed logic - smt 3 HMC987LP5E v00.0611 low noise 1:9 fanout buffer dc - 8 ghz for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com table 1. electrical specifcations unless otherwise specifed: t = 27 c, regulated vdd of 3.3 v, 2 ghz, 6 dbm in, ac coupled single ended input and output, 120 ?/leg dc termination, ac coupled into 50 ? measuring load. effects of customer eval board ( evaluation pcb schematic ) are de-embedded. for convenience, all voltages are referenced to gnd (0v), but negative supply references are acceptable. parameter conditions min. typ. max. units dc input characteristics vdd (vcchf=vcca=vccb=vccrf) 3.0 3.3 3.6 v input common mode voltage 1.35 2 vdd - 0.2 v input swing (single ended) 0.2 2 vpp input capacitance 0.5 pf input impedance single-ended selectable 50 / 150 ? differential selectable 100 / 300 ? input bias current base current under external dc bias, internal termination open. 165 a logic inputs switching threshold (vsw) vih/vil within 50 mv of vsw 38 47 54 %vdd lvpecl dc output characteristics output voltage high level @ 3.3 v = 2.25 vdd - 1.2 vdd - 1.0 vdd - 0.8 v ouput voltage common mode @ 3.3 v = 1.82 vdd - 1.7 vdd - 1.5 vdd - 1.3 v output voltage low level @ 3.3 v = 1.42 vdd - 2.1 vdd - 1.9 vdd - 1.7 v output voltage, single-ended 800 mvpp ac performance input/output frequency [1] > 400 vpp single-ended dc 8000 mhz 3 db bandwidth 4000 mhz output rise/fall time 20% to 80% 65 ps typical channel skew across all lvpecl outputs relative to channel 1 0 1.5 3.1 ps small signal gain s21 1000 mhz 26 db 4000 mhz 15 db input p1db 1000 mhz -20 dbm 4000 mhz -10 dbm saturated power in fundamental tone (single-ended) 1000 mhz 2.5 dbm 4000 mhz -0.5 dbm output voltage swing (vppd into 100 ?) 700 mhz 1.5 1.6 1.7 v 2000 mhz 1.2 1.3 1.4 v [1] for frequencies < 700 mhz, square wave signals should be used to maintain high quality phase noise performance.
3 - 3 high speed logic - smt 3 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC987LP5E v00.0611 low noise 1:9 fanout buffer dc - 8 ghz parameter conditions min. typ. max. units 4000 mhz 1.1 1.2 1.3 v harmonics fo 2 dbm 2fo -25 dbc 3fo -8 dbc 4fo -28 dbc 5fo -12 dbc ssb phase noise at 100 hz offset 622.08 mhz carrier frequency -147 dbc/hz 1750 mhz carrier frequency -147 dbc/hz 4000 mhz carrier frequency -147 dbc/hz ssb phase noise floor [2] 100 mhz carrier frequency -167 dbc/hz 622.08 mhz carrier frequency -167 dbc/hz 1750 mhz carrier frequency -166 dbc/hz 2000 mhz carrier frequency -166 dbc/hz 4000 mhz carrier frequency -163 dbc/hz 4200 mhz carrier frequency -162 dbc/hz floor jitter density 622.08 mhz carrier frequency 1.8 asec/hz 1750 mhz carrier frequency 0.7 asec/hz 4000 mhz carrier frequency 0.5 asec/hz integrated rms jitter 622.08 mhz carrier frequency 100 hz to 100 mhz 17 fs rms 12 khz to 20 mhz 8 fs rms 20 khz to 80 mhz 17 fs rms 50 khz to 80 mhz 17 fs rms 4 mhz to 80 mhz 16 fs rms 1750 mhz carrier frequency 100 hz to 100 mhz 7 fs rms 12 khz to 20 mhz 3 fs rms 20 khz to 80 mhz 6 fs rms 50 khz to 80 mhz 6 fs rms 4 mhz to 80 mhz 6 fs rms 4000 mhz carrier frequency 100 hz to 100 mhz 4 fs rms 12 khz to 20 mhz 2 fs rms 20 khz to 80 mhz 4 fs rms 50 khz to 80 mhz 4 fs rms 4 mhz to 80 mhz 4 fs rms output return loss 500 mhz to 4 ghz -16 -12 -8 db table 1. electrical specifcations (continued...) [2] cml buffer has similar phase noise characteristics at maximum output power level.
3 - 4 high speed logic - smt 3 HMC987LP5E v00.0611 low noise 1:9 fanout buffer dc - 8 ghz for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com parameter conditions min. typ. max. units isolation in to out - chip disabled 47 db off isolation - relative to power of neighboring driven port 700 mhz 60 48 db 4000 mhz 50 32 db output to output isolation with 500 mhz aggressor signal injected into output port to locally paired output buffer 25 db to other buffers 45 db rf output buffer 3 db bandwidth 5000 mhz max output power (vs temperature at 2 ghz) single-ended 3 3.2 dbm power control range (3 db steps) single-ended -9 3 dbm delay relative to lvpecl output -140 ps power supply rejection fm/phase pushing 0.8 ps/v am rejection 7 db current consumption (3.3 v unloaded outputs) chip disabled 1 a 1 output 60 ma 2 outputs 71 ma 3 outputs 97 ma 4 outputs 108 ma 5 outputs 134 ma 6 outputs 144 ma 7 outputs 170 ma 8 outputs 180 ma 8 + rf buffer (min to max power) 198 234 ma table 1. electrical specifcations (continued...)
3 - 5 high speed logic - smt 3 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC987LP5E v00.0611 low noise 1:9 fanout buffer dc - 8 ghz typical performance characteristics unless otherwise specifed: t = 27 c, regulated vdd = 3.3 v, 2 ghz, 6 dbm in, ac coupled single ended input and output, 120 ?/leg dc termination, ac coupled into 50 ? measuring load. figure 1. lvpecl output vs. frequency [1] figure 2. lvpecl output vs. frequency [1] figure 3. current consumption vs. num. of enabled buffers & load resistors [2] figure 4. skew of lvpecl outputs relative to output channel 1 [4] [1] +2dbm input, uncorrected for board loss. measurement is band limited by the trace bandwidth of 7 ghz. [2] buffers 1 through 8 are successively turned on. rf min - rf buffer turned on with minimum gain, rf max - rf buffer turned on with maximum gain [3] 200 ? termination, corrected for board loss. [4] characterized at 2 ghz, effects of customer evaluation board skew and loss are embedded. [5] the graph shows only output trace distortion. -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 -800 -600 -400 -200 0 200 400 600 800 time (picoseconds) output voltage (v) 4 ghz outp 4 ghz outn 2 ghz outn 1 ghz outp 1 ghz outn 2 ghz outp -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0 20 40 60 80 100 120 4 ghz 2 ghz 1 ghz amplitude (v differential) time (ps) figure 5. fundamental output power vs. input power [3] -20 -15 -10 -5 0 5 -30 -24 -18 -12 -6 0 6 input power (dbm) output power (dbm) 400 mhz 2 ghz 3 ghz 4 ghz 5 ghz 6 ghz figure 6. evaluation board lvpecl output trace loss vs. frequency [5] -15 -10 -5 0 5 10 15 p1 p2 p3 p4 p5 p6 p7 p8 relative delay (psec) output channel 0 100 200 300 400 500 1 2 3 4 5 5 6 7 8 rf min rf max current (ma) number of outputs successively turned on ground current (does not depend on termination) 120 ohm dc termination 300 ohm dc termination 200 ohm dc termination -7 -6 -5 -4 -3 -2 -1 0 100 1000 10000 output trace loss (db) output frequency (mhz)
3 - 6 high speed logic - smt 3 HMC987LP5E v00.0611 low noise 1:9 fanout buffer dc - 8 ghz for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com figure 7. rf buffer fo output power vs. frequency & temperature (max gain) figure 8. rf output power control figure 9. fundamental output power vs. frequency & temperature [6] [6] measured single-ended. corrected for trace loss. 200 ? dc termination, 3.3 v +6 dbm single-ended input. HMC987LP5E ac coupled to 50 ? instrument. [7] input signal power = + 6 dbm. 120 ?/leg dc termination. ac coupled via 50 pf to 26 ghz oscilloscope (50 ohm/leg termination). figure 10. fundamental output power vs. frequency & supply voltage at 27 c [6] figure 11. fundamental output power vs. frequency & termination at 27 c [6] figure 12. signal swing vs. frequency [7] -3 -2 -1 0 1 2 3 4 100 1000 10000 -40 c 27 c 85 c output power (dbm) output frequency (mhz) -3 -2 -1 0 1 2 3 4 100 1000 10000 output power (dbm) output frequency (mhz) 3.0 v 3.2 v 3.3 v 3.5 v 3.6 v -3 -2 -1 0 1 2 3 100 1000 10000 120 ohms 200 ohms 300 ohms output power (dbm) output frequency (mhz) -3 -2 -1 0 1 2 3 4 100 1000 10000 -40 c 27 c 85 c output power (dbm) frequency (mhz) -12 -9 -6 -3 0 3 6 100 1000 10000 output power (dbm) frequency (mhz) reg04h[2:0] = 1d reg04h[2:0] = 2d reg04h[2:0] = 3d reg04h[2:0] = 4d reg04h[2:0]= 5d 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0 1000 2000 3000 4000 5000 6000 7000 8000 signal swing (vppd) frequency (mhz) corrected for evaluation board loss observed and not corrected for evaluation board loss
3 - 7 high speed logic - smt 3 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC987LP5E v00.0611 low noise 1:9 fanout buffer dc - 8 ghz -260 -258 -256 -254 -252 -250 -248 0 500 1000 1500 2000 fom (dbc/hz) sinusoidal input frequency (mhz) -180 -170 -160 -150 -140 -130 -120 -110 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) frequency offset (hz) hmc830lp6ge used as source source + fanout output noise -170 -168 -166 -164 -162 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 phase noise (dbc/hz) vdd 300 ohm termination 120 ohm termination 200 ohm termination figure 13. phase noise performance at 2 ghz (differential drive) [9] -170 -168 -166 -164 -162 -160 -50 0 50 100 phase noise (dbc/hz) temperature (deg. c) frequency = 100 mhz frequency = 2 ghz frequency = 4.2 ghz figure 14. phase noise floor vs. slew rate -168 -166 -164 -162 -160 -158 -156 -15 -10 -5 0 5 10 phase noise (dbc/hz) input power (dbm) [8] input power = 10 dbm single-ended. phase noise floor (dbc/hz) = fom (dbc/hz)) + 10log(fout [hz]) [9] hmc830lp6ge used as signal source, driving +9 dbm differentially. figure 15. phase noise floor at 1.6 ghz vs. input power figure 16. phase noise performance with low frequency sinusoidal inputs [8] figure 17. phase noise floor at 2 ghz vs. vdd and dc termination figure 18. phase noise floor vs. temperature -169 -168 -167 -166 -165 -164 -163 -162 -161 0 2 4 6 8 10 12 phase noi se (dbc/hz) slew rate (v/nsec) pin = 10 dbm pin = 0 dbm pin = 10 dbm pin = 0 dbm 2 ghz 4 ghz 100 mhz pin = -3 dbm pin = 3 dbm
3 - 8 high speed logic - smt 3 HMC987LP5E v00.0611 low noise 1:9 fanout buffer dc - 8 ghz for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com figure 19. harmonic performance (single-ended input & output) [10] -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 power (dbm) frequency (mhz) fo 2fo 3f0 4fo 3fo 5fo [10] not corrected for board/cable loss. [11] effects of the customer evaluation board are not corrected. improvements in s11 and s22 are possible under different evaluation board confgurations figure 20. s-parameters - s11 [11] -30 -25 -20 -15 -10 -5 0 0 2000 4000 6000 8000 10000 s11 (db) frequency (mhz) single-ended differential figure 21. s-parameters - s12 [11] figure 22. s-parameters - s22 [11] -110 -100 -90 -80 -70 -60 -50 -40 -30 0 2000 4000 6000 8000 10000 s12 (db) frequency (mhz) single-ended differential -30 -25 -20 -15 -10 -5 0 0 2000 4000 6000 8000 10000 s22 (db) frequency (mhz) differential single-ended
3 - 9 high speed logic - smt 3 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC987LP5E v00.0611 low noise 1:9 fanout buffer dc - 8 ghz table 2. pin descriptions pin number function description 1 vcchf power supply 2 clkp differential clock inputs 3 clkn 4 sdi serial port data input 5 sdo serial port data output 6 pmode-sel parallel mode select. if 1, pins (sclk, sdi, sen) are interpreted as a control-word which enables different buffers. see section parallel port control 7 rfoutp differential signal output 8 rfoutn 9 vccrf power supply 10 sclk serial port clock 11 sen serial port latch enable 12 outp8 differential signal output 13 outn8 14 outp7 differential signal output 15 outn7 16 vccb power supply 17 outn6 differential signal output 18 outp6 19 outn5 differential signal output 20 outp5 21 outp4 differential signal output 22 outn4 23 outp3 differential signal output 24 outn3 25 vcca power supply 26 outn2 differential signal output 27 outp2 28 outn1 differential signal output 29 outp1 30 rfbufen active high rf buffer enable. the polarity of this control input can be swapped via spi bit reg03h [4]. 31 cen hardware chip enable 32 nc no connect
3 - 10 high speed logic - smt 3 HMC987LP5E v00.0611 low noise 1:9 fanout buffer dc - 8 ghz for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com table 3. absolute maximum ratings parameter rating max vdc to paddle on supply pins 1, 9, 16, 25 -0.3 v to +4 v max rf power clkp, clkn 15 dbm single-ended clkp, clkn - 0.3 v to 3.6 v lvpecl min output load resistor 100 ohms to gnd lvpecl output load current 40 ma/leg digital load 1 k? min digital input voltage range -0.3 to 3.6 v thermal resistance (junction to ground paddle) 25 0 c/w operating temperature range -40 o c to +85 o c storage temperature range -65 o c to + 125 o c maximum junction temperature +125 o c refow soldering peak temperature 260 o c time at peak temperature 40 sec esd sensitivity hbm class 1b stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
3 - 11 high speed logic - smt 3 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC987LP5E v00.0611 low noise 1:9 fanout buffer dc - 8 ghz outline drawing notes: [1] package body material: low stress injection molded plastic silica and silicon impregnated. [2] lead and ground paddle material: copper alloy. [3] lead and ground paddle plating: 100% matte tin. [4] dimensions are in inches [millimeters]. [5] lead spacing tolerance is non-cumulative. [6] pad burr length shall be 0.15 mm max. pad burr height shall be 0.05 mm max. [7] package warp shall not exceed 0.05 mm [8] all ground leads and ground paddle must be soldered to pcb rf ground. [9] refer to hittite application note for suggested pcb land pattern. table 4. package information part number package body material lead finish msl rating package marking [1] HMC987LP5E rohs-compliant low stress injection molded plastic 100% matte sn msl1 [2] h987 xxxx [1] 4-digit lot number xxxx [2] max peak refow temperature of 260 c
3 - 12 high speed logic - smt 3 HMC987LP5E v00.0611 low noise 1:9 fanout buffer dc - 8 ghz for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com evaluation pcb the circuit board used in the application should use rf circuit design techniques. signal lines should have 50 ohms impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown. a sufficient number of via holes should be used to connect the top and bottom ground planes. the evaluation circuit board shown is available from hittite upon request. table 5. evaluation order information item contents part number evaluation pcb HMC987LP5E evaluation pcb eval01- HMC987LP5E evaluation kit HMC987LP5E evaluation pcb usb interface board 6 usb a male to usb b female cable cd rom (contains user manual, evaluation pcb schematic, evaluation software, ekit01- HMC987LP5E
3 - 13 high speed logic - smt 3 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC987LP5E v00.0611 low noise 1:9 fanout buffer dc - 8 ghz evaluation pcb schematic c114 depop c113 depop c112 depop c111 depop c110 depop c109 depop c108 depop c6 4.7uf vcchf j7 1 2 130-00080-00 sch, eval customer 11/18/2010 b 1 1 d.young HMC987LP5E a cp110719 ----- production release cp110719 v.vaduva 05/25/11 06/23/11 d. aceval changer32,r35,r36,r63,r38,r39,r41,r42,r44,r45,r47,r48,r49,r50,r51,r52,r53,r54,r56,r57cp110885 cp110885 b 29-06-2011_13:34 ---- 20 alpha rd chelmsford, ma 01824 hittite microwave corporation a b notice of proprietary property: this document and the information contained in it are the proprietary property of hittite microwave corporation. it may not be copied or used in any manner nor may any of the information in or upon it be used for any purpose without the expressed written consent of an authorized agent of hittite microwave corporation. a b 4 3 2 1 of 3 2 1 drawn by date code id no. size rev 1cn88 revisions title drawing #: project c sheet rev ecn# zone name date description c c d d 5 6 5 6 4 nc nc nc c21 0.1uf j30 ssw-106-01-t-d 9 11 1 3 5 7 2 4 6 8 10 12 tp2 tp1 j11 1 2 vccb vcca vccrf j26 j19 j14 j1 j2 j25 c22 0.1uf j23 j29 j27 j24 j22 c17 depop c31 depop c32 depop c39 depop c49 depop j20 c20 depop c52 depop c42 depop c74 depop c93 depop c65 depop c61 depop c75 depop c66 depop c87 depop c76 depop c23 depop c33 depop c24 depop c34 depop c26 depop c36 depop c95 depop c73 depop c72 depop c71 depop c80 depop c82 depop c90 depop c91 depop c60 depop c64 depop c63 depop c70 depop c68 depop c78 depop c43 depop c44 depop c46 depop c58 depop c56 depop c55 depop r33 depop r34 depop j12 j28 j21 j17 j18 j15 j13 j3 j4 r31 depop j5 1 2 j6 1 2 j8 1 2 j10 1 2 c4 0.1uf vccb vcca vccrf c101 100pf vcchf c54 0.1uf c102 100pf c53 0.1uf c100 100pf c5 100pf c3 4.7uf j9 1 2 r5 200k r6 200k r8 200k r9 200k r10 200k r7 200k r2 200k vccrf nc u1 hmc976lp3e 1 2 3 4 15 12 11 10 9 13 16 14 5 6 7 8 hv vr vdd vrx ref rd en band gap 400 nc nc nc nc nc nc nc nc nc c1 0.1uf c2 4.7uf HMC987LP5E u2 24 6 1 9 8 7 25 16 2 32 31 30 29 28 27 26 5 4 3 17 18 19 20 21 22 23 10 11 12 13 14 15 outn7 outp7 outn8 outp8 sen sclk outp3 outn4 outp4 outp5 outn5 outp6 outn6 clkn sdi sdo outn2 outp2 outn1 outp1 rfbufen cen clkp vccb vcca rfoutp rfoutn vccrf vcchf pmode_sel outn3 spi nc c106 depop c105 depop r63 1k 0 r4 0 r1 c10 100pf c12 100pf r11 0 r13 0 r14 0 depop r32 r12 0 depop r35 depop r36 r41 200 c83 depop c84 depop c18 100pf c16 100pf c28 100pf c48 100pf c50 100pf c40 100pf r47 200 c41 depop c51 depop c38 100pf c79 100pf c62 100pf c69 100pf c88 100pf c81 100pf c92 100pf c98 100pf c99 100pf c96 100pf c94 100pf r53 200 c85 100pf c86 100pf c67 100pf c97 100pf r50 200 c77 100pf c47 100pf c59 100pf c37 100pf c27 100pf nc c7 0.1uf r62 0 c104 depop c103 depop c89 100pf c9 depop c13 depop c8 depop c11 depop r25 0 r61 depop r3 82k r17 0 r16 0 r15 0 r21 0 r23 0 r24 0 r26 0 r29 0 r30 0 r20 0 r19 0 r18 0 r22 0 c25 100pf c35 100pf c14 100pf c15 100pf c57 100pf c45 100pf r39 200 r40 0 r42 200 r48 200 r45 200 r46 0 nc c29 depop r44 200 r43 0 r55 0 r49 200 r51 200 r59 0 r52 200 r56 200 r57 200 r54 200 r58 0 r27 0 r28 0 r60 0 j16 r38 200 r37 0 c19 depop c30 100pf c107 depop sdo sen cen rfbuf_en pmod_sel sdi sck header to usb board out5-p out5-n out6-p out6-n out7-n out7-p out8-n out8-p out2-p out2-n out1-n out1-p clk-n clk-p gnd +5v max 350ma 3.3v rfout-p rfout-n out3-p out3-n out4-n out4-p
3 - 14 high speed logic - smt 3 HMC987LP5E v00.0611 low noise 1:9 fanout buffer dc - 8 ghz for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com theory of operation HMC987LP5E parallel port control the various outputs of the HMC987LP5E can be enabled/disabled by using parallel pin control, or via the spi. in parallel-mode (pmode-sel = 1), the spi input pins (sclk, ski, sen) are re-interpreted as a 3-bit control bus, and enable the lvpecl drivers according to the following truth table. sclk, sdi, sen 000: out2 001: out2 + out7 010: out2 + out7 + out4 011: out2 + out7 + out4 + out6 100: out2 + out7 + out4 + out6 + out5 101: out2 + out7 + out4 + out6 + out5 + out3 110: out2 + out7 + out4 + out6 + out5 + out3 + out8 111: out2 + out7 + out4 + out6 + out5 + out3 + out8 + out1 under spi control (pmode-sel = 0, see section register map for the register map and spi protocol details), there is slightly more fexibility in that any combination of buffers can be enabled or disabled via the individual buffer enable bits in reg02h . the part features switches on both the input and output signals, so that when the part is disabled (via either the cen pin, or the spi control bit reg01h [0]), the power-down current drops to < 2 a, regardless of the io termination scheme. HMC987LP5E input stage the HMC987LP5E input stage, figure 23 , is fexible. it can be driven single-ended or differential, with lvpecl, lvds, or cml signals. if driven single-ended, a large ac coupling cap to ground should be used on the undriven input. the input impedance is selectable, via reg03h [3], between 50 ? or 150 ? (100 ? or 300 ? differential). the dc bias level of 2.0 v can be generated internally by programming reg03h [1] =1 (default confguration), supplied externally, or generated via an lvpecl termination network inside the part.
3 - 15 high speed logic - smt 3 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC987LP5E v00.0611 low noise 1:9 fanout buffer dc - 8 ghz figure 23. HMC987LP5E input stage figure 24 to figure 28 illustrate common HMC987LP5E input interface confgurations. figure 24. HMC987LP5E dc coupled cml interface figure 25. HMC987LP5E dc coupled cmos interface
3 - 16 high speed logic - smt 3 HMC987LP5E v00.0611 low noise 1:9 fanout buffer dc - 8 ghz for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com figure 26. HMC987LP5E dc coupled lvpecl interface figure 27. HMC987LP5E ac coupled differential cml / lvpecl / lvds / cmos interface figure 28. HMC987LP5E ac coupled single-ended cml / lvpecl / lvds / cmos interface HMC987LP5E lvpecl output stage the lvpecl output driver produces up to 1.6 vppd swing into 50 ? loads. lvpecl drivers are terminated with off-chip resistors that provide the dc current through the emitter-follower output stage. the output stage has a switch which disconnects the output driver from the load when not used. the switch series resistor signifcantly improves the output match when driving into 50 ? transmission lines. the switch series resistor causes a small dc level shift and swing degradation, depending on the termination current. if unused, disabled lvpecl outputs can be left foating, terminated, or grounded.
3 - 17 high speed logic - smt 3 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC987LP5E v00.0611 low noise 1:9 fanout buffer dc - 8 ghz figure 29. HMC987LP5E output stage figure 30 to figure 32 illustrate common HMC987LP5E output interface confgurations. figure 30. HMC987LP5E dc coupled to lvpecl interface figure 31. HMC987LP5E ac coupled to lvds / cml / lvpecl / cmos
3 - 18 high speed logic - smt 3 HMC987LP5E v00.0611 low noise 1:9 fanout buffer dc - 8 ghz for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com figure 32. HMC987LP5E dc coupled to cmos interface the user has a number of choices in how they connect lvpecl drivers and receivers, and there are great number of resources that deal in detail with this issue. as a quick introduction, there are compromises between matching performance, common mode levels, and signal swing. for clocking applications, the user often has the luxury of using ac coupling, unlike in many data-path situations. figure 33 shows a simplifed interface schematic between an lvpecl output and input stage - where various options and trade-offs for the termination components are provided in table 6 . the hittite evaluation board has a great deal of fexibility in how the i/os are confgured, and allows the confguration in figure 33 , among many others. figure 33. recommended HMC987LP5E interface diagram table 6. HMC987LP5E interface values rs - used to increase ro to match to 50 ? environment. HMC987LP5E already has ~ 10 ? internally. 0 ? hittite evb: largest signal swing, lowest common mode shift 10 ? better s22 r l - dc current termination for lvpecl output stage 120 ? hittite evb default: standard lvpecl termination voltages 200 ? reduced current, no performance degradation 300 ? further reduced current, lower output power but fatter frequency response open if using internal dc termination network at the rx cac - ac coupling cap big cap hittite evb default: if using ac coupling short if using internal dc termination network at the rx
3 - 19 high speed logic - smt 3 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC987LP5E v00.0611 low noise 1:9 fanout buffer dc - 8 ghz HMC987LP5E rf output stage the rf output buffer is a cml output stage with 50 ? impedance (single-ended) and adjustable power. in parallel mode (the pmode_sel pin = 1), it is at max gain (~ +3 dbm single-ended), whereas under spi control, the gain can be lowered in ~3 db steps down to -9 dbm single-ended. see reg04h for more information. figure 34. HMC987LP5E output stage HMC987LP5E serial port interface (spi) control HMC987LP5E can be controlled via spi or parallel port control (for more information on parallel control see HMC987LP5E parallel port control ). spi control offers more fexibility. external pin pmode-sel = 1 confgures the HMC987LP5E for parallel port operation, while pmode-sel = 0 will enable the spi control of HMC987LP5E. the spi control is required in order to re-confgure the input bias network from its default state ( reg03h ), to adjust the output power control on the rf/cml buffer, and to individually enable arbitrary lvpecl outputs. operational modes serial port interface features: a. compatibility with general serial port protocols that use a shift and strobe approach to communication. b. compatible with hmc multi-chip solutions, useful to address multiple chips of various types from a single serial port bus.
3 - 20 high speed logic - smt 3 HMC987LP5E v00.0611 low noise 1:9 fanout buffer dc - 8 ghz for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com serial port write operation table 7. spi open mode - write timing characteristics parameter conditions min. typ. max. units t 1 t2 t3 t4 t5 t 6 sdi setup time sdi hold time sen low duration sen high duration sclk 9 rising edge to sen rising edge serial port clock speed sen to sclk recovery time 3 3 10 10 10 dc 10 50 ns ns ns ns ns mhz ns a typical write cycle is shown in figure 35 . a. the master (host) places 9 bit data, d8:d0, msb frst, on sdi on the frst 9 falling edges of sclk. b. the slave ( HMC987LP5E ) shifts in data on sdi on the frst 9 rising edges of sclk c. master places 4 bit register address to be written to, r3:r0, msb frst, on the next 4 falling edges of sclk (10-13) d. slave shifts the register address bits on the next 4 rising edges of sclk (10-13). e. master places 3 bit chip address, a2:a0, msb frst, on the next 3 falling edges of sclk (14-16). the HMC987LP5E chip address is fxed at 001. f. slave shifts the chip address bits on the 3 rising edges of sclk (14-16). g. master asserts sen after the 16th rising edge of sclk. h. slave registers the sdi data on the rising edge of sen. figure 35. spi timing diagram, write operation serial port read operation in order ensure correct read operation a pull-down resistor to ground (~1-2kohm) is recommended on the serial data out line from the part. a typical read cycle is shown in figure 36 . in general, sdo line is always active during the write cycle. sdo will contain the data from the addresses pointed to by reg00h . if reg00h is not changed, the same data will always be present on the sdo. if it is desired to read from a specifc address, it is necessary in the frst spi cycle to write the desired address to reg00h , then in the next spi cycle the desired data will be available on the sdo. an example of the two cycle procedure to read from any random address is as follows:
3 - 21 high speed logic - smt 3 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC987LP5E v00.0611 low noise 1:9 fanout buffer dc - 8 ghz the master (host), on the frst 9 falling edges of sclk places 9 bit data, d8:d0, msb frst, on sdi as shown in figure 36 . d8:d0 should be set to zero. d3:d0 = address of the register to be read on the next cycle. a. the slave ( HMC987LP5E ) shifts in data on sdi on the frst 9 rising edges of sclk b. master places 4 bit register address , r3:r0, ( the address the write address register), msb frst, on the next 4 falling edges of sclk (10-13). r3:r0=0000. c. slave shifts the register bits on the next 4 rising edges of sclk (10-13). d. master places 3 bit chip address, a2:a0, msb frst, on the next 3 falling edges of sclk (14-16). the HMC987LP5E chip address is fxed at 001. e. slave shifts the chip address bits on the next 3 rising edges of sclk (14-16). f. master asserts sen after the 16th rising edge of sclk. g. slave registers the sdi data on the rising edge of sen. h. master clears sen to complete the address transfer of the two part read cycle. i. if we do not wish to write data to the chip at the same time as we do the second cycle , then it is recommended to simply rewrite the same contents on sdi to register zero on the read back part of the cycle. j. master places the same sdi data as the previous cycle on the next 16 falling edges of sclk. k. slave ( HMC987LP5E ) shifts the sdi data on the next 16 rising edges of sclk. l. slave places the desired data (i.e. data from address in reg00h [3:0]) on sdo on the next 16 rising edges of sclk. m. master asserts sen after the 16th rising edge of sclk to complete the cycle. note that if the chip address bits are unrecognized (a2:a0), the slave will tri-state the sdo output to prevent a possible bus contention issue. table 8. spi open mode - read timing characteristics parameter conditions min. typ. max. units t 1 t2 t3 t4 t5 t6 t7 sdi setup time sdi hold time sen low duration sen high duration sclk rising edge to sdo time sen to sclk recovery time sclk 16 rising edge to sen rising edge 3 3 10 10 10 10 8.2+0.2ns/pf ns ns ns ns ns ns ns
3 - 22 high speed logic - smt 3 HMC987LP5E v00.0611 low noise 1:9 fanout buffer dc - 8 ghz for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com figure 36. spi diagram, read operation 2- cycles
3 - 23 high speed logic - smt 3 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC987LP5E v00.0611 low noise 1:9 fanout buffer dc - 8 ghz register map table 9. reg00h id register (read only) bit name width default description [3:0] read control 4 (write only) [4] soft reset [4:0] chip id (read only) table 10. reg01h master enable bit name width default description [0] master chip enable 1 1 table 11. reg02h individual enables bit name width default description [0] en1 1 1 enable buffer 1 [1] en2 1 1 enable buffer 2 [2] en3 1 1 enable buffer 3 [3] en4 1 1 enable buffer 4 [4] en5 1 1 enable buffer 5 [5] en6 1 1 enable buffer 6 [6] en7 1 1 enable buffer 7 [7] en8 1 1 enable buffer 8 table 12. reg03h rx buffer confguration bit name width default description [0] 1 0 reserved 0 [1] dc internal 1 1 use internal dc bias string [2] dc lvpecl 1 0 use internal lvpecl rx termination [3] zin 50 1 1 input termination select 1 - 50 ? single-ended, 100 ? differential 0- 150 ? single-ended, 300 ? differential [4] rfbuf xor 1 0 toggle (xor with rfbufen pin) the internal rf buffer on/off [8:5] 4 0 reserved 0 table 13. reg04h gain select bit name width default description [2:0] rf buffer gain 3 7 0: disabled 1: -9 dbm single-ended 2: -6 dbm single-ended 3: -3 dbm single-ended 4: 0 dbm single-ended >4: 3 dbm single-ended
3 - 24 high speed logic - smt 3 HMC987LP5E v00.0611 low noise 1:9 fanout buffer dc - 8 ghz for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com table 14. reg05h biases bit name width default description [1:0] reserved 2 2 reserved - 2 [3:2] reserved 2 2 reserved - 2 [5:4] reserved 2 3 reserved - 3 [8:6] reserved 3 0 reserved - 0

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