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? s14025.b LSI53C1010-33 pci to dual channel ultra160 scsi multifunction controller technical manual february 2001 version 3.2
ii this document contains proprietary information of lsi logic corporation. the information contained herein is not to be used by or disclosed to third parties without the express written permission of an of?cer of lsi logic corporation. lsi logic products are not intended for use in life-support appliances, devices, or systems. use of any lsi logic product in such applications without written consent of the appropriate lsi logic of?cer is prohibited. document db14-000132-02, third edition (february 2001) this document describes the lsi logic LSI53C1010-33 pci to dual channel ultra160 scsi multifunction controller and will remain the of?cial reference source for all revisions/releases of this product until rescinded by an update. to receive product literature, visit us at http://www.lsilogic.com. lsi logic corporation reserves the right to make changes to any products herein at any time without notice. lsi logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase or use of a product from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or third parties. ultra scsi is the term used by the scsi trade association (sta) to describe fast-20 scsi, as documented in the scsi-3 fast-20 parallel interface standard, x3.277-199x. ultra2 scsi is the term used by the scsi trade association (sta) to describe fast-40 scsi, as documented in the scsi parallel interfaceC2 standard, (spiC2) x3t10/1142d. copyright ? 1997C2001 by lsi logic corporation. all rights reserved. trademark acknowledgment the lsi logic logo design, tolerant, scripts, lvdlink, sdms, and surelink are registered trademarks or trademarks of lsi logic corporation. all other brand and product names may be trademarks of their respective companies. hh/ap
preface iii preface this book is the primary reference and technical manual for the lsi logic LSI53C1010-33 pci to dual channel ultra160 scsi multifunction controller. it contains a complete functional description for the product and includes complete physical and electrical speci?cations. audience this document was prepared for system designers and programmers who are using this device to design an ultra160 scsi port for pci-based personal computers, workstations, servers or embedded applications. organization this document has the following chapters and appendixes: chapter 1, introduction , describes the general information about the LSI53C1010-33. chapter 2, functional description , describes the main functional areas of the chip in more detail, including the interfaces to the scsi bus and external memory. chapter 3, signal descriptions , contains the pin diagram and signal descriptions. chapter 4, registers , describes each bit in the operating registers, and is organized by register address. chapter 5, scsi scripts instruction set , de?nes all of the scsi scripts instructions that are supported by the LSI53C1010-33. chapter 6, speci?cations , contains the electrical characteristics and ac timing diagrams. appendix a, register summary , is a register summary.
iv preface appendix b, external memory interface diagram examples , contains several example interface drawings for connecting the LSI53C1010-33 to external roms. related publications for background please contact: ansi 11 west 42nd street new york, ny 10036 (212) 642-4900 ask for document number x3.131-199x (scsi-2) global engineering documents 15 inverness way east englewood, co 80112 (800) 854-7179 or (303) 397-7956 (outside u.s.) fax (303) 397-2740 ask for document number x3.131-1994 (scsi-2) or x3.253 (scsi-3 parallel interface) endl publications 14426 black walnut court saratoga, ca 95070 (408) 867-6642 document names: scsi bench reference, scsi encyclopedia, scsi tutor prentice hall 113 sylvan avenue englewood cliffs, nj 07632 (800) 947-7700 ask for document number isbn 0-13-796855-8, scsi: understanding the small computer system interface lsi logic world wide web home page www.lsil.com scsi scripts processors programming guide, order number s14044.a
preface v lsi logic internet anonymous ftp site ftp.lsil.com (204.131.200.1) directory: /pub/symchips/scsi pci special interest group 2575 n. e. katherine hillsboro, or 97214 (800) 433-5177; (503) 693-6232 (international); fax (503) 693-8344 conventions used in this manual the word assert means to drive a signal true or active. the word deassert means to drive a signal false or inactive. hexadecimal numbers are indicated by the pre?x 0x for example, 0x32cf. binary numbers are indicated by the pre?x 0b for example, 0b0011.0010.1100.1111. revision record revision date remarks 0.5 4/99 advanced information data - contains signal descriptions, registers, and mechanical drawings. 1.0 11/15/99 preliminary technical manual. 1.1 12/26/99 numerous rewordings. 2.0 3/00 final release. 3.0 5/00 miscellaneous edits, update to figure 6.42. 3.1 11/00 product names changed from sym to lsi. 3.2 2/01 changed ultra3 references to ultra160.
vi preface
contents vii contents chapter 1 introduction 1.1 general description 1-1 1.1.1 new features in the LSI53C1010-33 1-4 1.2 bene?ts of ultra160 scsi 1-4 1.3 bene?ts of surelink (ultra160 scsi domain validation) 1-5 1.4 bene?ts of lvdlink 1-6 1.5 bene?ts of tolerant ? technology 1-6 1.6 summary of LSI53C1010-33 bene?ts 1-7 1.6.1 scsi performance 1-7 1.6.2 pci performance 1-9 1.6.3 integration 1-10 1.6.4 ease of use 1-10 1.6.5 flexibility 1-11 1.6.6 reliability 1-11 1.6.7 testability 1-12 chapter 2 functional description 2.1 pci functional description 2-2 2.1.1 pci addressing 2-3 2.1.2 pci bus commands and functions supported 2-4 2.1.3 internal arbiter 2-11 2.1.4 pci cache mode 2-11 2.2 scsi functional description 2-19 2.2.1 scripts processor 2-20 2.2.2 internal scripts ram 2-20 2.2.3 64-bit addressing in scripts 2-21 2.2.4 hardware control of scsi activity led 2-22 2.2.5 designing an ultra160 scsi system 2-23 2.2.6 prefetching scripts instructions 2-32
viii contents 2.2.7 opcode fetch burst capability 2-33 2.2.8 load and store instructions 2-33 2.2.9 jtag boundary scan testing 2-34 2.2.10 parity/crc/aip options 2-34 2.2.11 dma fifo 2-38 2.2.12 scsi data paths 2-38 2.2.13 scsi bus interface 2-40 2.2.14 select/reselect during selection/reselection 2-42 2.2.15 synchronous operation 2-43 2.2.16 interrupt handling 2-47 2.2.17 interrupt routing 2-55 2.2.18 chained block moves 2-57 2.3 parallel rom interface 2-60 2.4 serial eeprom interface 2-62 2.4.1 default download mode 2-62 2.4.2 no download mode 2-63 2.5 power management 2-63 2.5.1 power state d0 2-64 2.5.2 power state d1 2-65 2.5.3 power state d2 2-65 2.5.4 power state d3 2-65 chapter 3 signal descriptions 3.1 signal organization 3-1 3.2 internal pull-ups and pull-downs on lsi53c1010 signals 3-4 3.3 pci bus interface signals 3-5 3.3.1 system signals 3-5 3.3.2 address and data signals 3-6 3.3.3 interface control signals 3-7 3.3.4 arbitration signals 3-8 3.3.5 error reporting signals 3-9 3.3.6 interrupt signals 3-9 3.3.7 scsi function a gpio signals 3-11 3.3.8 scsi function b gpio signals 3-12 3.4 scsi bus interface signals 3-13 3.4.1 scsi function a signals 3-13 3.4.2 scsi function b signals 3-16
contents ix 3.5 flash rom and memory interface signals 3-19 3.6 test interface signals 3-20 3.7 power and ground signals 3-21 3.8 mad bus programming 3-22 chapter 4 registers 4.1 pci con?guration registers 4-1 4.2 scsi registers 4-22 4.3 scsi shadow registers 4-123 chapter 5 scsi scripts instruction set 5.1 scsi scripts 5-1 5.1.1 sample operation 5-3 5.2 block move instructions 5-5 5.2.1 first dword 5-5 5.2.2 second dword 5-14 5.2.3 third dword 5-14 5.3 i/o instructions 5-15 5.3.1 first dword 5-15 5.3.2 second dword 5-22 5.4 read/write instructions 5-23 5.4.1 first dword 5-23 5.4.2 second dword 5-24 5.4.3 read-modify-write cycles 5-24 5.4.4 move to/from sfbr cycles 5-25 5.5 transfer control instructions 5-27 5.5.1 first dword 5-27 5.5.2 second dword 5-33 5.5.3 third dword 5-33 5.6 memory move instructions 5-34 5.6.1 read/write system memory from a script 5-35 5.6.2 second dword 5-36 5.6.3 third dword 5-36 5.7 load and store instructions 5-37 5.7.1 first dword 5-38 5.7.2 second dword 5-39
x contents chapter 6 speci?cations 6.1 dc characteristics 6-1 6.2 tolerant technology electrical characteristics 6-7 6.3 ac characteristics 6-10 6.4 pci and external memory interface timing diagrams 6-14 6.4.1 target timing 6-15 6.4.2 initiator timing 6-24 6.4.3 external memory timing 6-41 6.5 scsi timing diagrams 6-62 6.6 package drawings 6-73 appendix a register summary appendix b external memory interface diagram examples index customer feedback figures 1.1 typical LSI53C1010-33 board application 1-2 1.2 typical LSI53C1010-33 system application 1-3 2.1 LSI53C1010-33 block diagram 2-2 2.2 dma fifo sections 2-38 2.3 lsi53c1010 host interface scsi data paths 2-39 2.4 regulated termination for ultra160 scsi 2-42 2.5 determining the synchronous transfer rate 2-47 2.6 interrupt routing hardware using the lsi53c1010 2-56 2.7 block move and chained block move instructions 2-57 3.1 LSI53C1010-33 functional signal grouping 3-3 4.1 single transition transfer waveforms 4-105 4.2 double transition transfer waveforms (xclks examples) 4-106 4.3 double transition transfer waveforms (xclkh examples) 4-107
contents xi 5.1 scripts overview 5-4 5.2 block move instruction - first dword 5-5 5.3 block move instruction - second dword 5-14 5.4 block move instruction - third dword 5-14 5.5 first 32-bit word of the i/o instruction 5-15 5.6 second 32-bit word of the i/o instruction 5-22 5.7 read/write instruction - first dword 5-23 5.8 read/write instruction - second dword 5-24 5.9 transfer control instructions - first dword 5-27 5.10 transfer control instructions - second dword 5-33 5.11 transfer control instructions - third dword 5-33 5.12 memory move instructions - first dword 5-35 5.13 memory move instructions - second dword 5-36 5.14 memory move instructions - third dword 5-36 5.15 load and store instructions - first dword 5-38 5.16 load and store instructions - second dword 5-39 6.1 lvd driver 6-3 6.2 lvd receiver 6-4 6.3 rise and fall time test condition 6-8 6.4 scsi input filtering 6-8 6.5 hysteresis of scsi receivers 6-9 6.6 input current as a function of input voltage 6-9 6.7 output current as a function of output voltage 6-10 6.8 external clock 6-11 6.9 reset input 6-12 6.10 interrupt output 6-13 6.11 pci con?guration register read 6-16 6.12 pci con?guration register write 6-17 6.13 32-bit operating registers/scripts ram read 6-18 6.14 64-bit operating register/scripts ram read 6-19 6.15 32-bit operating register/scripts ram write 6-21 6.16 64-bit operating register/scripts ram write 6-23 6.17 nonburst opcode fetch, 32-bit address and data 6-25 6.18 burst opcode fetch, 32-bit address and data 6-27 6.19 back-to-back read, 32-bit address and data 6-29 6.20 back-to-back write, 32-bit address and data 6-31 6.21 burst read, 32-bit address and data 6-33 6.22 burst read, 64-bit address and data 6-35
xii contents 6.23 burst write, 32-bit address and data 6-37 6.24 burst write, 64-bit address and data 6-39 6.25 external memory read 6-42 6.26 external memory write 6-46 6.27 normal/fast memory ( 3 128 kbytes) single byte access read cycle 6-48 6.28 normal/fast memory ( 3 128 kbytes) single byte access write cycle 6-50 6.29 normal/fast memory ( 3 128 kbytes) multiple byte access read cycle 6-52 6.30 normal/fast memory ( 3 128 kbytes) multiple byte access write cycle 6-54 6.31 slow memory ( 3 128 kbytes) read cycle 6-56 6.32 slow memory ( 3 128 kbytes) write cycle 6-58 6.33 64 kbytes rom read cycle 6-60 6.34 64 kbytes rom write cycle 6-61 6.35 initiator asynchronous send 6-62 6.36 initiator asynchronous receive 6-63 6.37 target asynchronous send 6-63 6.38 target asynchronous receive 6-64 6.39 initiator and target st synchronous transfer 6-67 6.40 initiator and target dt synchronous transfer 6-71 6.41 left half of the LSI53C1010-33 329 bga chip - top view 6-74 6.42 LSI53C1010-33 329 ball grid array (bottom view) 6-78 6.43 LSI53C1010-33 329 bga mechanical drawing 6-79 b.1 16 kbyte interface with 200 ns memory b-1 b.2 64 kbyte interface with 150 ns memory b-2 b.3 128, 256, 512 kbyte or 1 mbyte interface with 150 ns memory b-3 b.4 512 kbyte interface with 150 ns memory b-4 tables 2.1 pci bus commands and encoding types 2-5 2.2 pci cache mode alignment 2-14 2.3 new phases on scsi bus 2-24 2.4 protocol options (byte 7) 2-26 2.5 bits used for parity/crc/aip control and generation 2-36 2.6 scsi parity errors and interrupts 2-37
contents xiii 2.7 scf divisor values 2-44 2.8 parallel rom support 2-61 2.9 default download mode serial eeprom data format 2-63 2.10 power states 2-64 3.1 lsi53c1010 internal pull-ups and pull-downs 3-4 3.2 system signals 3-5 3.3 address and data signals 3-6 3.4 interface control signals 3-7 3.5 arbitration signals 3-8 3.6 error reporting signals 3-9 3.7 interrupt signals 3-9 3.8 scsi function a gpio signals 3-11 3.9 scsi function b gpio signals 3-12 3.10 scsi bus interface signals 3-13 3.11 scsi function a signals 3-13 3.12 scsi function a control signals 3-15 3.13 scsi function b signals 3-16 3.14 scsi function b control signals 3-18 3.15 flash rom and memory interface signals 3-19 3.16 test interface signals 3-20 3.17 power and ground signals 3-21 3.18 mad[3:1] pin decoding 3-23 4.1 pci con?guration register map 4-2 4.2 scsi register map 4-23 4.3 maximum synchronous offset 4-35 4.4 double transition transfer rates 4-108 4.5 single transition transfer rates 4-110 5.1 read/write instructions 5-25 6.1 absolute maximum stress ratings 6-2 6.2 operating conditions 6-2 6.3 lvd driver scsi signalssd[15:0], sdp[1:0], sreq/, sack/, smsg/, sio/, scd/, satn/, sbsy/, ssel/, srst/ 6-3 6.4 lvd receiver scsi signalssd[15:0], sdp[1:0], sreq/, sack/, smsg/, sio/, scd/, satn/, sbsy/, ssel/, srst/ 6-3 6.5 a and b diffsens scsi signals 6-4 6.6 input capacitance 6-4 6.7 8 ma bidirectional signalsgpio0_fetch/, gpio1_master/, gpio2, gpio3, gpio4 6-5
xiv contents 6.8 4 ma bidirectional signalsmad[7:0] 6-5 6.9 4 ma output signalsmas[1:0]/, mce/, moe/_testout, mwe/, tdo 6-5 6.10 8 ma pci bidirectional signalsad[63:0], c_be[7:0]/, frame/, irdy/, trdy/, devsel/, stop/, perr/, par, par64, req64/, ack64/ 6-6 6.11 input signalsclk, gnt/, idsel, int_dir, rst/, sclk, tck, tdi, test_hsc, test_rst/, test_pd, tms 6-6 6.12 8 ma output signalsinta/, intb/, alt_inta/, alt_intb/, req/, serr/ 6-6 6.13 tolerant technology electrical characteristics for se scsi signals 6-7 6.14 external clock 6-11 6.15 reset input 6-12 6.16 interrupt output 6-13 6.17 pci con?guration register read 6-16 6.18 pci con?guration register write 6-17 6.19 32-bit operating register/scripts ram read 6-18 6.20 64-bit operating register/scripts ram read 6-19 6.21 32-bit operating register/scripts ram write 6-21 6.22 64-bit operating register/scripts ram write 6-22 6.23 nonburst opcode fetch, 32-bit address and data 6-24 6.24 burst opcode fetch, 32-bit address and data 6-26 6.25 back-to-back read, 32-bit address and data 6-28 6.26 back-to-back write, 32-bit address and data 6-30 6.27 burst read, 32-bit address and data 6-32 6.28 burst read, 64-bit address and data 6-34 6.29 burst write, 32-bit address and data 6-36 6.30 burst write, 64-bit address and data 6-38 6.31 external memory read 6-41 6.32 external memory write 6-45 6.33 normal/fast memory ( 3 128 kbytes) single byte access read cycle 6-48 6.34 normal/fast memory ( 3 128 kbytes) single byte access write cycle 6-50 6.35 slow memory ( 3 128 kbytes) read cycle 6-56 6.36 slow memory ( 3 128 kbytes) write cycle 6-58
contents xv 6.37 64 kbytes rom read cycle 6-60 6.38 64 kbytes rom write cycle 6-61 6.39 initiator asynchronous send 6-62 6.40 initiator asynchronous receive 6-63 6.41 target asynchronous send 6-63 6.42 target asynchronous receive 6-64 6.43 scsi-1 transfers (se 5.0 mbytes) 6-65 6.44 scsi-2 fast transfers 10.0 mbytes (8-bit transfers) or 20.0 mbytes (16-bit transfers) 40 mhz clock 6-65 6.45 ultra scsi se transfers 20.0 mbytes (8-bit transfers) or 40.0 mbytes (16-bit transfers) quadrupled 40 mhz clock 6-66 6.46 ultra2 scsi transfers 40.0 mbyte (8-bit transfers) or 80.0 mbyte (16-bit transfers) quadrupled 40 mhz clock 6-67 6.47 scsi-2 fast transfers 10.0 mbytes (8-bit transfers) or 20.0 mbytes (16-bit transfers) 40 mhz clock 6-68 6.48 ultra scsi se transfers 20.0 mbytes (8-bit transfers) or 40.0 mbytes (16-bit transfers) quadrupled 40 mhz clock 6-69 6.49 ultra2 scsi transfers 40.0 mbyte (8-bit transfers) or 80.0 mbyte (16-bit transfers) quadrupled 40 mhz clock 6-70 6.50 ultra160 scsi transfers 160.0 mbyte (16-bit transfers) quadrupled 40 mhz clock 6-71 6.51 signal names and bga position 6-76 6.52 signal names by bga position 6-77 a.1 LSI53C1010-33 pci register map a-1 a.2 LSI53C1010-33 scsi register map a-3
xvi contents
LSI53C1010-33 pci to dual channel ultra160 scsi multifunction controller 1-1 chapter 1 introduction this chapter provides a general overview on the LSI53C1010-33 pci to dual channel ultra160 scsi multifunction controller. this chapter contains the following sections: section 1.1, general description section 1.2, bene?ts of ultra160 scsi section 1.3, bene?ts of surelink (ultra160 scsi domain validation) section 1.4, bene?ts of lvdlink section 1.5, bene?ts of tolerant? technology section 1.6, summary of LSI53C1010-33 bene?ts 1.1 general description the LSI53C1010-33 brings ultra160 scsi performance to host adapter, workstation, and server designs, making it easy to add a high-performance scsi bus to any pci system. the lsi53c1010 is pin and software compatible with the lsi53c896 pci to dual channel ultra2 scsi multifunction controller, thus making migration easy (pin compatible means that the lsi53c896 can operate in an lsi53c1010 socket but the lsi53c1010 cannot operate in an lsi53c896 socket). the lsi53c1010 supports a 64-bit or 32-bit, 33 mhz pci bus. the ultra160 scsi features in the lsi53c1010 are: double transition (dt) clocking, cyclic redundancy check (crc), and domain validation. these features comply with the ultra160 scsi industry initiative.
1-2 introduction dt clocking permits the lsi53c1010 to transfer data up to 160 megabytes per second (mbytes/s) on each channel for a total of 320 mbytes/s. crc improves the integrity of the scsi data transmission through enhanced detection of communication errors. asynchronous information protection (aip) augments crc to protect all nondata phases, providing complete end-to-end protection of the scsi i/o. surelink? domain validation detects the scsi bus con?guration and automatically tests and adjusts the scsi transfer rate to optimize interoperability. three levels of domain validation are provided, assuring robust system operation. the lsi53c1010 has a local memory bus. this allows local storage of the devices bios rom in ?ash memory or standard eproms. the lsi53c1010 supports programming of local ?ash memory for bios updates. the chip is packaged in a 329 ball grid array (bga). figure 1.1 shows a typical lsi53c1010 board application connected to external rom or ?ash memory. figure 1.1 typical LSI53C1010-33 board application lvdlink? technology is the lsi logic implementation of low voltage differential (lvd). lvdlink transceivers allow the lsi53c1010 to perform either single-ended (se) or lvd transfers. the lsi53c1010 integrates flash eeprom serial eeprom function a serial eeprom function b memory control block lsi53c1010 64-bit / 33 mhz pci to dual channel function a 68 pin wide scsi connector scsi data, parity, and control signals scsi data, parity, and control signals pci interface pci address, data, parity and control signals memory address/data bus a_gpio/[1:0] b_gpio/[1:0] ultra160 scsi controller and terminator function a 68 pin wide scsi connector and terminator
general description 1-3 two high-performance scsi cores, a 64-bit/33 mhz pci bus master dma core, and the lsi logic scsi scripts? processor to meet the ?exibility requirements of ultra160 scsi standards. it implements multithreaded i/o algorithms with minimum processor intervention, solving the protocol overhead problems of previous intelligent and nonintelligent adapter designs. figure 1.2 illustrates a typical lsi53c1010 system application. figure 1.2 typical LSI53C1010-33 system application fixed disk, optical disk, printer, tape, and other scsi peripherals fixed disk, optical disk, printer, tape, and other scsi peripherals one pci bus load pci graphic accelerator pci fast ethernet memory controller memory pci bus interface controller central processing unit (cpu) typical pci computer system architecture processor bus LSI53C1010-33 pci to wide ultra160 scsi function a and LSI53C1010-33 pci to wide ultra160 scsi function b scsi bus scsi bus pci bus
1-4 introduction 1.1.1 new features in the LSI53C1010-33 the lsi53c1010 is functionally similar to the lsi53c896, with additional features and bene?ts. following is a list of new lsi53c1010 features from the lsi53c896: complies with pci rev. 2.2 speci?cation supports ultra160 dt clocking for data transfers up to 160 mbytes/s per channel supports enhanced protection on nondata asynchronous phases through aip supports crc checking and generation in dt phases supports domain validation C basic (level 1) with inquiry command (inquiry check) C enhanced (level 2) with read/write buffer C margined (level 3) with margining of lvd drivers and programmable skew test all cycles to scripts ram stay internal to the device, not generating pci cycles scripts engine with improved instruction fetch performance 1.2 bene?ts of ultra160 scsi ultra160 scsi delivers data up to two times faster than ultra2 scsi. ultra160 scsi is an extension of the spi-3 draft standard that allows faster synchronous scsi data transfer rates than ultra2 scsi. when enabled, ultra160 scsi performs 80 megatransfers per second (megatransfers/s) resulting in approximately double the synchronous data transfer rates of ultra2 scsi. the lsi53c1010 performs 16-bit, ultra160 scsi synchronous data transfers as fast as 160 mbytes/s on each channel providing a total bandwidth of 320 mbytes/s. this advantage is most noticeable in heavily loaded systems, or large block size applications such as video on-demand and image processing. the ultra160 data transfer speed is accomplished using dt clocking. dt clocking refers to transferring data on both polarity edges of the
bene?ts of surelink (ultra160 scsi domain validation) 1-5 request or acknowledge signals. data is clocked on both rising and falling edges of the request and acknowledge signals. double-edge clocking doubles data transfer speeds without increasing the clock rate. ultra160 scsi also includes crc, which offers higher levels of data reliability by ensuring complete integrity of transferred data. crc is a 32-bit scheme, referred to as crc-32. crc is guaranteed to detect all single bit errors, any two bits in error, or any combination of errors within a single 32-bit range. aip is also supported by the lsi53c1010, protecting all nondata phases, including command, status, and messages. crc, along with aip, provides end-to-end protection of the scsi i/o. an advantage of ultra160 scsi is that it signi?cantly improves scsi bandwidth while preserving existing hardware and software investments. the primary software changes required are to enable the chip to perform synchronous negotiations for ultra160 scsi rates and to enable the clock quadrupler. ultra160 scsi uses the same connectors as ultra scsi and ultra2 scsi. chapter 2, functional description, contains more information on migrating an ultra scsi or ultra2 scsi design to an ultra160 scsi design. 1.3 bene?ts of surelink (ultra160 scsi domain validation) surelink represents the very latest scsi interconnect management solution. it ensures robust and low risk ultra160 scsi implementations by extending the domain validation guidelines documented in the ansi t10 spi-3 speci?cations. domain validation veri?es that the system is capable of transferring data at ultra160 speeds, allowing it to renegotiate to lower speed and bus width if necessary. surelink is the software control for the manageability enhancements in the lsi53c1010. fully integrated in the sdms? software solution, surelink provides domain validation at boot time as well as throughout system operation. surelink extends to the dmi (desktop management interface) based system management components of sdms, providing the network administrator remote management capability. surelink domain validation provides 3 levels of integrity checking: basic (level 1), enhanced (level 2), and margined (level 3). the basic check consists of an inquiry command to detect gross problems. the enhanced
1-6 introduction check sends a known data pattern using the read and write buffer commands to detect additional problems. margined check veri?es that the physical parameters have some degree of margin. by varying lvd drive strength and req/ack timing characteristics level 3 veri?es that no errors occur on the transfers. these altered signals are only used during the diagnostic check and not during normal system operation. should errors occur with any of these checks, the system can drop back to a lower transmission speed on a per target basis to ensure robust system operation. 1.4 bene?ts of lvdlink the lsi53c1010 supports lvd through lvdlink. this signaling technology increases the reliability of scsi data transfers over longer distances than are supported by se scsi. the low current output of lvd allows the i/o transceivers to be integrated directly onto the chip. lvd provides the reliability of high voltage differential (hvd) scsi without the added cost of external differential transceivers. ultra160 scsi with lvd allows a longer scsi cable and more devices on the bus, with the same cables de?ned in the scsi-3 parallel interface standard for ultra scsi. lvd provides a long-term migration path to even faster scsi transfer rates without compromising signal integrity, cable length, or connectivity. for backward compatibility to existing se devices, the lsi53c1010 features universal lvdlink transceivers that support lvd scsi and se scsi. this allows use of the lsi53c1010 in both legacy and ultra160 scsi applications. 1.5 bene?ts of tolerant ? technology the lsi53c1010 features tolerant technology, which includes active negation on the scsi drivers and input signal ?ltering on the scsi receivers. active negation causes the scsi request, acknowledge, data, and parity signals to be actively driven high rather than passively pulled up by terminators.
summary of LSI53C1010-33 bene?ts 1-7 tolerant receiver technology improves data integrity in unreliable cabling environments where other devices would be subject to data corruption. tolerant receivers ?lter the scsi bus signals to eliminate unwanted transitions, without the long signal delay associated with rc-type input ?lters. this improved driver and receiver technology helps eliminate double clocking of data which is the single biggest reliability issue with scsi operations. tolerant input signal ?ltering is a built-in feature of the lsi53c1010 and all lsi logic fast scsi, ultra scsi, ultra2 scsi, and ultra160 scsi devices. the bene?ts of tolerant technology include increased immunity to noise when the signal is going high, better performance due to balanced duty cycles, and improved fast scsi transfer rates. in addition, tolerant scsi devices do not cause glitches on the scsi bus at power-up or power-down. this protects other devices on the bus from data corruption. when it is used with the lvdlink transceivers, tolerant technology provides excellent signal quality and data reliability in real world cabling environments. tolerant technology is compatible with both the alternative one and alternative two termination schemes proposed by the american national standards institute. 1.6 summary of LSI53C1010-33 bene?ts this section provides a summary of the lsi53c1010 features and bene?ts. it contains information on scsi performance , pci performance , integration , ease of use , flexibility , reliability , and testability . 1.6.1 scsi performance the LSI53C1010-33: performs wide, ultra160 scsi synchronous data transfers as fast as 160 mbytes/s on each scsi channel for a total of 320 mbytes/s using dt clocking. supports crc checking and generation in dt phases. protects nondata phases with aip. supports domain validation: C basic (level 1)
1-8 introduction C enhanced (level 2) C margined (level 3) includes integrated lvdlink universal transceivers: C supports se and lvd signals. C allows greater device connectivity and longer cable length. C lvdlink transceivers save the cost of external differential transceivers. C supports a long-term performance migration path. bursts of up to 512 bytes across the pci bus with an independent 896C920 byte fifo on each scsi channel. includes two separate scsi channels on one chip. handles phase mismatches in scripts without interrupting the system processor. includes an on-chip scsi clock quadrupler that allows the chip to achieve ultra160 scsi transfer rates with an input frequency of 40 mhz. includes 8 kbytes of internal ram for scripts instruction storage for each scsi channel. supports 31 levels of scsi synchronous offset in the single transition (st) mode and 62 levels in the dt mode. supports variable block size and scatter/gather data transfers. performs sustained memory-to-memory dma transfers to approximately 100 mbytes/s. minimizes the scsi i/o start latency. performs complex bus sequences without interrupts, including restoring data pointers. reduces isr overhead through a unique interrupt status reporting method. includes raid ready scsi on the motherboard with separate interrupts for routing to a raid adapter. supports load/store scripts instructions to increase the performance of data transfers to and from the chip registers without using pci cycles.
summary of LSI53C1010-33 bene?ts 1-9 includes scripts support of 64-bit addressing. supports target disconnect and later reconnect with no interrupt to the system processor. supports multithreaded i/o algorithms in scsi scripts with fast i/o context switching. supports expanded register move instructions to support additional arithmetic capability. 1.6.2 pci performance the lsi53c1010: complies with pci 2.2 speci?cation. supports a 64-bit/33 mhz pci interface for 264 mbytes/s bandwidth that: C can function in a 32-bit pci slot. C operates at 33 mhz. C supports dual address cycle generation for all scripts. C presents a single electrical load to the pci bus (true pci multifunction device). bursts 2/4, 4/8, 8/16, 16/32, 32/64, or 64/128 qword/dword transfers across the pci bus. supports 32-bit or 64-bit word data bursts with variable burst lengths. prefetches up to 8 dwords of scripts instructions. bursts scripts opcode fetches across the pci bus. performs zero wait-state bus master data bursts up to 264 mbytes/s (@ 33 mhz). supports pci cache line size (cls) register. supports pci write and invalidate, read line, and read multiple commands. complies with pci bus power management speci?cation revision 1.1. complies with pc99.
1-10 introduction 1.6.3 integration the following features ease integration of the lsi53c1010 into a system: dual channel ultra160 scsi pci multifunction controller. integrated lvd transceivers. full 32-bit or 64-bit pci dma bus master. memory-to-memory move instructions allow use as a third-party pci bus dma controller. integrated scripts processor. 1.6.4 ease of use the following features of the lsi53c1010 make the device user friendly: the lsi53c1010 is pin and software compatible with the lsi53c896, thus making migration easy (pin compatible means that the lsi53c896 can operate in an lsi53c1010 socket but the lsi53c1010 cannot operate in an lsi53c896 socket). up to one mbyte of add-in memory support for bios and scripts storage. reduced scsi development effort. compiler-compatible with existing lsi53c7xx and lsi53c8xx family scripts. direct connection to pci and scsi se and lvd. development tools and sample scsi scripts available. maskable and pollable interrupts. wide scsi, a or p cable, and up to 15 devices per scsi channel supported. three programmable scsi timers: select/reselect, handshake-to- handshake, and general purpose. software for pc-based operating system support.
summary of LSI53C1010-33 bene?ts 1-11 support for relative jumps. scsi selected as id bits for responding with multiple ids. 1.6.5 flexibility the following features increase the ?exibility of the lsi53c1010: universal lvd transceivers are backward compatible with se devices. high level programming interface (scsi scripts). programs local and bus ?ash memory. tailored scsi sequences execute from main system ram or internal scripts ram. flexible programming interface to tune i/o performance or to adapt to unique scsi devices. support for changes in the logical i/o interface de?nition. low level access to all registers and all scsi bus signals. fetch, master, and memory access control pins. separate scsi and system clocks. scsi clock quadrupler bits enable ultra160 scsi transfer rates with a 40 mhz scsi clock input. selectable irq pin disable bit. compatible with 3.3 v and 5 v pci. 1.6.6 reliability the following features enhance the reliability of the lsi53c1010: crc and aip provide end-to-end scsi i/o protection. 2 kv esd protection on scsi signals. protection against bus re?ections due to impedance mismatches. controlled bus assertion times (reduces rfi, improves reliability, and eases fcc certi?cation). latch-up protection greater than 150 ma.
1-12 introduction voltage feed-through protection (minimum leakage current through scsi pads). a high proportion of pins are power and ground. power and ground isolation of i/o pads and internal chip logic. tolerant technology provides: C active negation of scsi data, parity, request, and acknowledge signals for improved fast scsi transfer rates. C input signal ?ltering on scsi receivers improves data integrity, even in noisy cabling environments. 1.6.7 testability the following features enhance the testability of the lsi53c1010: all scsi signals accessible through programmed i/o. scsi bus signal continuity checking. support for single-step mode operation. jtag boundary scan.
LSI53C1010-33 pci to dual channel ultra160 scsi multifunction controller 2-1 chapter 2 functional description this chapter provides a functional description of the LSI53C1010-33. this chapter is divided into the following sections: section 2.1, pci functional description section 2.2, scsi functional description section 2.3, parallel rom interface section 2.4, serial eeprom interface section 2.5, power management the LSI53C1010-33 is composed of the following modules: 64-bit pci interface two independent pci to wide ultra160 scsi controllers rom/flash memory controller serial eeprom controller figure 2.1 illustrates the relationship between these modules.
2-2 functional description figure 2.1 LSI53C1010-33 block diagram the lsi53c1010 has two wide ultra160 scsi channels in a single package. each scsi channel (a and b) incorporates an independent dma fifo and a separate internal 8 kbyte scripts ram. 2.1 pci functional description the lsi53c1010 implements two pci to wide ultra160 scsi controllers in a single package. this con?guration presents only one load to the pci bus and uses only one req/ - gnt/ pair for pci bus arbitration. separate interrupt signals are generated for scsi function a and scsi function b. 8 kbyte scripts ram 8 dword scripts prefetch buffer operating registers scsi scripts processor 920 byte dma fifo scsi fifo and scsi control block universal tolerant drivers and receivers 64-bit pci interface, pci con?guration registers (2 sets) wide ultra160 scsi channel serial eeprom controller and autocon?guration rom/flash memory control local bus memory 8 kbyte scripts ram 8 dword scripts prefetch buffer scsi scripts processor 920 byte dma fifo scsi fifo and scsi control block universal tolerant drivers and receivers wide ultra160 scsi channel operating registers pci bus scsi function b wide ultra160 scsi bus scsi function a wide ultra160 scsi bus jtag rom/flash memory bus 2-wire serial eeprom bus (function a) 2-wire serial eeprom bus (function b) jtag bus
pci functional description 2-3 2.1.1 pci addressing there are three physical address spaces de?ned in the pci speci?cation: pci con?guration space i/o space for operating registers memory space for operating registers 2.1.1.1 con?guration space the host processor uses this con?guration space to initialize the lsi53c1010. two independent sets of con?guration space registers are de?ned, one set for each scsi function. each scsi function contains the same register set with identical default values except for the interrupt pin. the con?guration registers are initialized by the system bios using pci con?guration cycles. each con?guration space is a contiguous 256 x 8-bit set of addresses. decoding c_be[3:0]/ determines if a pci cycle is intended to access the con?guration register space. the idsel bus signal is a chip select that allows access to the con?guration register space only. a con?guration read/write cycle without idsel is ignored. the host processor uses the eight lower order address bits (ad[7:0]) to select a speci?c 8-bit register. since the lsi53c1010 is a pci multifunction device, bits ad[10:8] decode either scsi function a con?guration register (ad[10:8] = 0b000) or scsi function b con?guration register (ad[10:8] = 0b001). table 4.1 on page 4-2 is an illustration of the pci con?guration register map. at initialization time, each pci device is assigned a base address for memory and i/o accesses. in the lsi53c1010, the upper 24 bits of the address are selected. on every access, the lsi53c1010 compares its assigned base addresses with the value on the address/data bus during the pci address phase. if the upper 24 bits match, the access is designated for the lsi53c1010. the low order eight bits de?ne the register to be accessed. a decode of c_be[3:0]/ determines which register and what type of access is performed.
2-4 functional description 2.1.1.2 i/o space the pci speci?cation de?nes i/o space as a contiguous 32-bit i/o address that is shared by all system resources, including the lsi53c1010. base address register zero (bar0) (i/o) determines which 256-byte i/o area this device occupies. 2.1.1.3 memory space the pci speci?cation de?nes memory space as a contiguous 64-bit memory address that is shared by all system resources. base address register one (bar1) (memory) determines which 1-kbyte memory area this device occupies. each scsi function uses an 8-kbyte scripts ram memory space. base address register two (bar2) (memory) determines the 8-kbyte memory area the scripts ram occupies. 2.1.2 pci bus commands and functions supported bus commands indicate to the target the type of transaction the master is requesting. bus commands are encoded on the c_be[3:0]/ lines during the address phase. pci bus commands and encoding types appear in table 2.1 .
pci functional description 2-5 2.1.2.1 interrupt acknowledge command the lsi53c1010 does not respond to this command as a slave and it never generates this command as a master. 2.1.2.2 special cycle command the lsi53c1010 does not respond to this command as a slave and it never generates this command as a master. table 2.1 pci bus commands and encoding types c_be[3:0]/ command type supported as master supported as slave 0000 interrupt acknowledge no no 0001 special cycle no no 0010 i/o read yes yes 0011 i/o write yes yes 0100 reserved n/a n/a 0101 reserved n/a n/a 0110 memory read yes yes 0111 memory write yes yes 1000 reserved n/a n/a 1001 reserved n/a n/a 1010 con?guration read no yes 1011 con?guration write no yes 1100 memory read multiple yes 1 1. see the dma mode (dmode) register. yes (defaults to 0110) 1101 dual address cycle (dac) yes yes 1110 memory read line yes 1 yes (defaults to 0110) 1111 memory write and invalidate ye s 2 2. see the chip test three (ctest3) register. yes (defaults to 0111)
2-6 functional description 2.1.2.3 i/o read command the lsi53c1010 uses the i/o read command to read data from an agent mapped in the i/o address space. when decoding i/o cycles, the LSI53C1010-33 decodes the lower 32 address bits and ignores the upper 32 address bits. 2.1.2.4 i/o write command the lsi53c1010 uses the i/o write command to write data to an agent mapped in the i/o address space. when decoding i/o cycles, the LSI53C1010-33 decodes the lower 32 address bits and ignores the upper 32 address bits. 2.1.2.5 reserved command the given bus encoding is reserved. 2.1.2.6 memory read command the lsi53c1010 uses the memory read command to read data from an agent mapped in the memory address space. the target may perform an anticipatory read if such a read produces no side effects. 2.1.2.7 memory write command the lsi53c1010 uses the memory write command to write data to an agent mapped in the memory address space. when the target returns ready, it assumes responsibility for data coherency, which includes ordering. 2.1.2.8 con?guration read command the con?guration read command reads the con?guration space of a device. the lsi53c1010 never generates this command as a master, but does respond to it as a slave. a device on the pci bus selects the lsi53c1010 by asserting its idsel signal when ad[1:0] are 0b00. during the address phase of a con?guration cycle, ad[7:2] address one of the 64 dword registers in the con?guration space of each device. c_be[3:0]/ address the individual bytes within each dword. ad[10:8] indicate which device on the lsi53c1010 is being addressed. the lsi53c1010 treats ad[63:11] as logical dont cares.
pci functional description 2-7 2.1.2.9 con?guration write command the con?guration write command writes the con?guration space of a device. the lsi53c1010 never generates this command as a master, but does respond to it as a slave. a device on the pci bus selects the lsi53c1010 by asserting its idsel signal when ad[1:0] are 0b00. during the address phase of a con?guration cycle, ad[7:2] address one of the 64 dword registers in the con?guration space of each device. c_be[3:0]/ address the individual bytes within each dword. ad[10:8] indicate which device on the lsi53c1010 is being addressed. the lsi53c1010 treats ad[63:11] as logical dont cares. 2.1.2.10 memory read multiple command this command is identical to the memory read command, except it additionally indicates that the master intends to fetch multiple cache lines before disconnecting. the lsi53c1010 supports pci memory read multiple functionality and issues memory read multiple commands on the pci bus when the read multiple mode is enabled. this mode is enabled by setting bit 2 (ermp) of the dma mode (dmode) register. if the cache mode is enabled, a memory read multiple command is issued on all read cycles, except opcode fetches, when the following conditions are met: the clse bit (cache line size enable, bit 7, dma control (dcntl) register) is set. the ermp bit (enable read multiple, bit 2, dma mode (dmode) register) is set. the cache line size (cls) register for each function contains a legal burst size value (4, 8, 16, 32, 64, or 128 dwords) that is less than or equal to the dmode burst size. the transfer crosses a cache line boundary. when these conditions are met, the chip issues a memory read multiple command instead of a memory read during all pci read cycles. burst size selection C the read multiple command reads in multiple cache lines of data during a single bus ownership. revision 2.2 of the pci speci?cation speci?es the number of cache lines to read as a multiple of the cache line size. the logic selects the largest multiple of
2-8 functional description the cache line size based on the amount of data to transfer. the maximum allowable burst size is determined from the dma mode (dmode) burst size bits and the chip test five (ctest5) register, bit 2. 2.1.2.11 dual address cycle (dac) command when 64-bit addressing is required, the lsi53c1010 performs dacs, per the pci 2.2 speci?cation. if any of the selector registers contain a nonzero value, a dac is generated. 2.1.2.12 memory read line command this command is identical to the memory read command, except it additionally indicates that the master intends to fetch a complete cache line. this command is intended for use with bulk sequential data transfers where the memory system and the requesting master might gain some performance advantage by reading to a cache line boundary rather than a single memory cycle. the read line function in the lsi53c1010 takes advantage of the pci 2.2 speci?cation regarding issuance of this command. if the cache mode is disabled, no read line commands are issued. if the cache mode is enabled, a read line command is issued on all read cycles, except nonprefetch opcode fetches, when the following conditions are met: the clse bit (cache line size enable, bit 7, of the dma control (dcntl) register) is set. the erl bit (enable read line, bit 3, of the dma mode (dmode) register) is set. the cache line size (cls) register for each function must contain a legal burst size value (4, 8, 16, 32, 64, or 128 dwords) that is less than or equal to the dmode burst size. the transfer crosses a dword boundary but not a cache line boundary. when these conditions are met, the chip issues a read line command instead of a memory read during all pci read cycles. otherwise, it issues a normal memory read command.
pci functional description 2-9 read multiple with read line enabled C when both the read multiple and read line modes are enabled, the read line command is not issued if the above conditions are met. instead, a read multiple command is issued. if the read multiple mode is enabled, read multiple commands are issued if the read multiple conditions are met. 2.1.2.13 memory write and invalidate command the memory write and invalidate command is identical to the memory write command, except it additionally guarantees a minimum transfer of one complete cache line. that is, the master intends to write all bytes within the addressed cache line in a single pci transaction unless interrupted by the target. this command requires implementation of the pci cache line size (cls) register. the lsi53c1010 enables memory write and invalidate cycles when bit 0 (wrie), in the chip test three (ctest3) register, and bit 4 (wie), in the pci command register, are set. when the following conditions are met, memory write and invalidate commands are issued: the following bits are set: C the clse bit (cache line size enable, bit 7, of the dma control (dcntl) register), C the wrie bit (write and invalidate enable, bit 0, of the chip test three (ctest3) register), C bit 4 of the pci con?guration command register. the cache line size (cls) register for each function contains a legal burst size value (4, 8, 16, 32, 64, or 128 dwords) that is less than or equal to the dma mode (dmode) burst size. the chip has enough bytes in the dma fifo to complete at least one full cache line burst. the chip is aligned to a cache line boundary. when these conditions are met, the lsi53c1010 issues a write and invalidate command instead of a memory write command during all pci write cycles.
2-10 functional description multiple cache line transfers C the memory write and invalidate command can write multiple cache lines of data in a single bus ownership. the chip issues a burst transfer as soon as it reaches a cache line boundary. the transfer size is not automatically the cache line size, but rather a multiple of the cache line size speci?ed in revision 2.2 of the pci speci?cation. the logic selects the largest multiple of the cache line size based on the transfer size. the maximum allowable burst size is determined from the dma mode (dmode) burst size bits, and bit 2 of the chip test five (ctest5) register. if multiple cache line size transfers are not desired, set the dmode burst size to exactly the cache line size and the chip will only issue single cache line transfers. after each data transfer, the chip re-evaluates the burst size based on the amount of remaining data to transfer. it again selects the highest possible multiple of the cache line size, and no larger than the dma mode (dmode) burst size. usually, the chip selects the dmode burst size after alignment and issues bursts of this size. the burst size is, in effect, throttled down toward the end of a long memory move or block move transfer until only the cache line size left is burst size. the chip ?nishes the transfer with this burst size. latency C in accordance with the pci speci?cation, the latency timer is ignored when issuing a memory write and invalidate command. therefore, when a latency time-out occurs, the lsi53c1010 continues to transfer up to a cache line boundary. at that point, the chip relinquishes the bus, and ?nishes the transfer at a later time using another bus ownership. if the chip is transferring multiple cache lines it continues to transfer until the next cache boundary is reached. pci target retry C a retry is de?ned as a stop with no trdy/, indicating that no data was transferred. if the target issues a retry during a memory write and invalidate transfer, the chip relinquishes the bus and immediately tries to ?nish the transfer on another bus ownership. the chip issues another memory write and invalidate command on the next ownership, in accordance with the pci speci?cation. pci target disconnect C if the target device issues a disconnect during a memory write and invalidate transfer, the lsi53c1010 relinquishes the bus and immediately tries to ?nish the transfer on another bus ownership. the chip does not issue another memory write and invalidate command on the next ownership unless the address is aligned.
pci functional description 2-11 2.1.3 internal arbiter the pci to scsi controller uses a single req/ - gnt/ signal pair to arbitrate for access to the pci bus. an internal arbiter circuit allows the different bus mastering functions resident in the chip to arbitrate among themselves for the privilege of arbitrating for pci bus access. there are two independent bus mastering functions inside the lsi53c1010, one for each of the scsi functions. the internal arbiter uses a round robin arbitration scheme to decide which internal bus mastering function may arbitrate for access to the pci bus. this ensures that no function is starved for access to the pci bus. 2.1.4 pci cache mode the lsi53c1010 supports the pci speci?cation for an 8-bit cache line size (cls) register located in the pci con?guration space. the cache line size (cls) register provides the ability to sense and react to nonaligned addresses corresponding to cache line boundaries. in conjunction with the cache line size (cls) register, the pci commands memory read line (mrl), memory read multiple (mrm), and memory write and invalidate (mwi) are individually software enabled or disabled. information on pci cache mode alignment is provided in table 2.2 . 2.1.4.1 enabling cache mode to enable the cache logic to issue pci cache commands (memory read line, memory read multiple, and memory write and invalidate) on any pci master operation, the following conditions must be met: the cache line size enable bit in the dma control (dcntl) register must be set. the pci cache line size (cls) register must contain a valid binary cache size, i.e., 4, 8, 16, 32, 64, or 128 dwords. these values are the only valid cache sizes. the programmed burst size (in dwords) must be equal to or greater than the cache line size register. the dma mode (dmode) register, bits [7:6], and the chip test five (ctest5) register, bit 2, denote the burst length.
2-12 functional description the device must be performing a pci master transfer. the following pci master transactions do not utilize the pci cache logic so no pci cache commands are issued during these types of cycles: a nonprefetch scripts fetch, a load/store data transfer, and a data ?ush operation. all other types of pci master transactions utilize the pci cache logic. not only must the above four conditions be met in order for the cache logic to control the type of pci cache command that is issued, proper alignment is also necessary during write operations. if these conditions are not met for any given pci master transaction, a memory read or memory write is issued and no cache write alignment is done. 2.1.4.2 issuing cache commands in order to issue each type of pci cache command, the corresponding enable bit(s) must be set. to issue memory read line commands, the enable read line (erl) bit in the dma mode (dmode) register must be set. to issue memory read multiples, the enable read multiple (ermp) bit in the dma mode (dmode) register must be set. to issue memory write and invalidates, both the write and invalidate enable (wrie) bit in the chip test three (ctest3) register and the write and invalidate enable (wie) bit in the pci con?guration command register must be set. if the corresponding cache command is not enabled, the cache logic falls back to the next command enabled. for example, if the memory read multiple command is not enabled and the memory read line command is, memory read line command is issued in place of memory read multiple command. if no cache commands are enabled, cache write alignment still occurs but no cache commands are issued; only memory reads and memory writes are issued. 2.1.4.3 memory read caching the type of memory read command issued depends on the starting location of the transfer and the number of bytes to be transferred. during reads, no cache alignment is done, as it is neither required nor optional according to pci 2.2 speci?cation. reads are a programmed burst length
pci functional description 2-13 in size, as set in the dma mode (dmode) and chip test five (ctest5) registers. in the case of a transfer that is smaller than the burst length, all bytes for that transfer are read in one pci burst transaction. if the transfer crosses a dword boundary (a[1:0] = 0b00) a memory read line command is issued. if the transfer crosses a cache boundary, as speci?ed by the cache line size programmed into the pci con?guration register, a memory read multiple command is issued. if a transfer does not cross a dword or cache boundary or if cache mode is not enabled a memory read command is issued. 2.1.4.4 memory write caching memory writes are aligned in a single burst transfer to reach a cache boundary. at that point, memory write and invalidate commands are issued and continue at the burst length programmed into the dma mode (dmode) register. memory write and invalidate commands continue to be issued as long as the remaining byte count is greater than the memory write and invalidate threshold. when the remaining byte count drops below this threshold, a single memory write burst is issued to complete the transfer. in summary, the general pattern for pci writes is: a single memory write to align to a cache boundary multiple memory write and invalidates a single data residual memory write to complete the transfer table 2.2 describes pci cache mode alignment.
2-14 functional description table 2.2 pci cache mode alignment host memory a 0x00 b 0x04 0x08 c 0x0c d 0x10 0x14 0x18 0x1c e 0x20 0x24 0x28 0x2c f 0x30 0x34 0x38 0x3c g 0x40 0x44 0x48 0x4c h 0x50 0x54 0x58 0x5c 0x60
pci functional description 2-15 2.1.4.5 examples the examples in this section employ the following abbreviations: mr = memory read, mrl = memory read line, mrm = memory read, multiple, mw = memory write, mwi = memory write and invalidate. read example 1 C burst = 4 dwords, cache line size = 4 dwords: atob: mrl (6 bytes) atoc: mrl (13 bytes) atod: mrm (16 bytes) mr (1 byte) ctod: mrm (5 bytes) ctoe: mrm (16 bytes) mrm (5 bytes) dtof: mrm (16 bytes) mrm (16 bytes) atoh: mrm (16 bytes) mrm (16 bytes) mrm (16 bytes) mrm (16 bytes) mrm (16 bytes) mr (1 byte) atog: mrm (16 bytes) mrm (16 bytes) mrm (16 bytes) mrm (16 bytes) mr (2 bytes)
2-16 functional description read example 2 C burst = 8 dwords, cache line size = 4 dwords: read example 3 C burst = 16 dwords, cache line size = 8 dwords: atob: mrl (6 bytes) atoc: mrl (13 bytes) atod: mrm (17 bytes) ctod: mrm (5 bytes) ctoe: mrm (21 bytes) dtof: mrm (32 bytes) atoh: mrm (32 bytes) mrm (32 bytes) mrm (17 bytes) atog: mrm (32 bytes) mrm (32 bytes) mr (2 bytes) atob: mrl (6 bytes) atoc: mrl (13 bytes) atod: mrl (17 bytes) ctod: mrl (5 bytes) ctoe: mrm (21 bytes) dtof: mrm (32 bytes) atoh: mrm (64 bytes) mrl (17 bytes) atog: mrm (64 bytes) mr (2 bytes)
pci functional description 2-17 write example 1 C burst = 4 dwords, cache line size = 4 dwords: atob: mw (6 bytes) atoc: mw (13 bytes) atod: mw (17 bytes) ctod: mw (5 bytes) ctoe: mw (3 bytes) mwi (16 bytes) mw (2 bytes) dtof: mw (15 bytes) mwi (16 bytes) mw (1 byte) atoh: mw (15 bytes) mwi (16 bytes) mwi (16 bytes) mwi (16 bytes) mwi (16 bytes) mw (2 bytes) atog: mw (15 bytes) mwi (16 bytes) mwi (16 bytes) mwi (16 bytes) mw (3 bytes)
2-18 functional description write example 2 C burst = 8 dwords, cache line size = 4 dwords: write example 3 C burst = 16 dwords, cache line size = 8 dwords: atob: mw (6 bytes) atoc: mw (13 bytes) atod: mw (17 bytes) ctod: mw (5 bytes) ctoe: mw (3 bytes) mwi (16 bytes) mw (2 bytes) dtof: mw (15 bytes) mwi (16 bytes) mw (1 byte) atoh: mw (15 bytes) mwi (32 bytes) mwi (32 bytes) mw (2 bytes) atog: mw (15 bytes) mwi (32 bytes) mwi (16 bytes) mw (3 bytes) atob: mw (6 bytes) atoc: mw (13 bytes) atod: mw (17 bytes) ctod: mw (5 bytes) ctoe: mw (21 bytes) dtof: mw (32 bytes) atoh: mw (31 bytes) mwi (32 bytes) mw (18 bytes) atog: mw (31 bytes) mwi (32 bytes) mw (3 bytes)
scsi functional description 2-19 2.1.4.6 memory-to-memory moves memory-to-memory moves also support pci cache commands, as described above, with one limitation: memory write and invalidate on memory-to-memory move writes are only supported if the source and destination address are quad word aligned. if the source and destination are not quad word aligned, i.e., source address[2:0] == destination address[2:0], write alignment is not performed and memory write and invalidates are not issued. the lsi53c1010 is little endian. this mode assigns the least signi?cant byte to bits [7:0]. 2.2 scsi functional description both ultra160 scsi controllers on the lsi53c1010 provide a scsi function that supports either an 8-bit or 16-bit bus. each controller supports wide ultra160 scsi synchronous transfer rates up to 160 mbytes/s on a lvd scsi bus. scsi functions can be programmed with scsi scripts, making it easy to ?ne tune the system for speci?c mass storage devices or ultra160 scsi requirements. figure 2.1 on page 2-2 illustrates the relationship between the lsi53c1010 modules. the lsi53c1010 offers low level register access or a high level control interface. like ?rst generation scsi devices, the lsi53c1010 is accessed as a register-oriented device. the ability to sample and/or assert any signal on the scsi bus is used in error recovery and diagnostic procedures. the lsi53c1010 is controlled by the integrated scripts processor through a high level logical interface. commands controlling the scsi functions are fetched out of the main host memory or local memory. these commands instruct the scsi functions to select, reselect, disconnect, wait for a disconnect, transfer information, change bus phases, and implement all other aspects of the scsi protocol. the scripts processor is a special high speed processor optimized for scsi protocol.
2-20 functional description 2.2.1 scripts processor the scsi scripts processor allows fetches of both dma and scsi commands from host memory or internal scripts ram. algorithms written in scsi scripts control the actions of the scsi and dma cores. the scripts processor, running off of the pci clock, executes complex scsi bus sequences independently of the host cpu. algorithms can be designed to tune scsi bus performance to adjust to new bus device types, such as scanners, communication gateways, etc. they can also incorporate changes in the scsi logical bus de?nitions without sacri?cing i/o performance. scsi scripts are hardware independent, so they can be used interchangeably on any host or cpu system bus. scsi scripts handle conditions such as phase mismatch. 2.2.1.1 phase mismatch handling in scripts the lsi53c1010 can handle phase mismatches due to drive disconnects without needing to interrupt the processor. the primary goal of this logic is to completely eliminate the need for cpu intervention during an i/o disconnect/reselect sequence. scripts control the storage of appropriate information needed to restart the i/o state, eliminating the need for processor intervention during an i/o disconnect/reselect sequence. calculations are performed such that the appropriate information is available to scripts so that an i/o state can be properly stored for restart later. the phase mismatch jump logic is disabled at power-up. it must be enabled by setting the phase mismatch jump enable bit (enpmj, bit 7 in the chip control zero (ccntl0) register). utilizing the information supplied in the phase mismatch jump address registers allows all overhead involved in a disconnect/reselect sequence to be handled with a modest amount of scripts instructions. these registers are described in detail in chapter 4, registers. 2.2.2 internal scripts ram the lsi53c1010 has 8 kbytes (2048 x 32 bits) of internal, general purpose ram for each scsi function. the ram is designed for scripts program storage, but is not limited to this type of information. when the chip fetches scripts instructions or table indirect information
scsi functional description 2-21 from the internal ram, these fetches remain internal to the chip and do not use the pci bus. in addition, any scripts instruction that contains a source or destination address residing in scripts ram memory space remains internal to the chip and does not generate pci cycles. scripts instructions able to access scripts ram memory space in this manner include memory-to-memory moves, load/stores, and block moves. while an internal cycle is occurring, any external pci slave cycle is retried on the pci bus. setting the disrc (disable internal scripts ram cycles) bit in the chip control zero (ccntl0) register disables this feature. scripts ram should be initialized before it is read. reading scripts ram before initialization will result in the scripts ram parity bit, bit 7, being set in the shadowed scsi sge status 0 register. pci system bios can relocate the ram anywhere in the 64-bit address space. base address register three (bar3) (scripts ram) and base address register four (bar4) (scripts ram) , in the pci con?guration space, contain the base address of the internal ram. to simplify scripts instruction loading, the base address of the ram appears in the scratch register b (scratchb) register when bit 3 of the chip test two (ctest2) register is set. the upper 32 bits of a 64-bit base address are in the script fetch selector (sfs) register. the ram is byte accessible from the pci bus and is visible to any bus mastering device on the bus. external, cpu accesses to the ram follow the same timing sequence as a standard slave register access, except that the required target wait-states drop from 5 to 3. scripts ram must ?rst be written before being read in order to initialize scripts ram parity. if a scripts ram parity error is encountered a scsi gross error interrupt will be signaled. a complete set of development tools is available for writing custom drivers with scsi scripts. for more information on the scsi scripts instructions supported by the lsi53c1010, see chapter 5, scsi scripts instruction set. 2.2.3 64-bit addressing in scripts the pci interface for the lsi53c1010 provides 64-bit address and data capability in the initiator mode. the chip can also respond to 64-bit addressing in the target mode.
2-22 functional description dacs can be generated for all scripts operations. there are six selector registers which hold the upper dword of a 64-bit address. all but one of these is static and requires manual loading using a cpu access, a load and store instruction, or a memory move instruction. one of the selector registers is dynamic and is used during 64-bit direct block moves only. all selectors will default to zero, meaning the lsi53c1010 will power-up in a state where only single address cycles (sacs) are generated. when any of the selector registers are written to a nonzero value, dacs are generated. direct, table indirect and indirect block moves, memory-to-memory moves, load/stores, and jumps are all instructions with 64-bit address capability. note: crossing the 4 gbyte boundary on any one scripts operation is not permitted. therefore, software must handle all such transactions. 2.2.4 hardware control of scsi activity led the lsi53c1010 controls an led through the gpio_0 pin to indicate that it is connected to the scsi bus. this function was previously handled by a software driver. bit 3 (con), in the interrupt status zero (istat0) register, is presented at the gpio_0 pin when the following occurs: bit 5 (led_cntl) in the general purpose pin control (gpcntl) register is set, bit 6 (fetch enable) in the general purpose pin control (gpcntl) register is cleared, the lsi53c1010 is not performing an eeprom autodownload. the con (connected) bit in interrupt status zero (istat0) register is set anytime the lsi53c1010 is connected to the scsi bus either as an initiator or a target. this happens after the lsi53c1010 has successfully completed a selection or when it has successfully responded to a selection or reselection. it will also be set when the lsi53c1010 wins arbitration in low level mode.
scsi functional description 2-23 2.2.5 designing an ultra160 scsi system software modi?cations are needed to take advantage of the ultra160 speed in the lsi53c1010. since ultra160 scsi is based on existing scsi standards, it can use existing drivers if they are able to negotiate for ultra160 synchronous transfer rates. also, the target device must be able to communicate at ultra160 speed. the lsi53c1010 uses domain validation to determine whether or not the system is capable of ultra160 scsi before activating dt clocking. refer to section 2.2.5.1, ultra160 scsi features, for more information on dt clocking. lvd scsi ful?lls the hardware requirements for ultra160 scsi transfer rates, increased cable lengths, and additional devices on the bus. all devices on the bus must have lvd scsi capabilities to guarantee ultra160 scsi transfer rates. for additional information on ultra160 scsi, refer to the scsi parallel interface-3 (spi-3) working document that is available on the world wide web at the t10 home page, http://www.t10.org. also, check the scsi trade association web site at http://www.scsita.org/. chapter 6, speci?cations, contains ultra160 scsi timing information. in addition to the guidelines in the draft standard, make the following software adjustments to accommodate ultra160 scsi transfers. 2.2.5.1 ultra160 scsi features domain validation C domain validation is a procedure in which a host queries a device to determine its ability to communicate at the negotiated ultra160 data rate. in software, the following steps are performed to ensure the selected device can successfully transfer data at the negotiated speed. step 1. select a device. step 2. issue inquiry command. step 3. issue parallel protocol request (ppr) message. step 4. issue write buffer command. step 5. issue read buffer command. step 6. examine the data pattern to ensure validity. if the commands complete successfully with no crc errors, bus hangs, or data pattern errors, then the negotiated speed is valid.
2-24 functional description crc C crc is the error detecting code used in ultra160 scsi. four bytes are transferred with data to increase the reliability of data transfers. crc is used in the dt data-in and dt data-out phases only. because crc is implied with dt mode and only works with dt mode, the dt setting can be used for crc. dt clocking C ultra160 scsi implements dt clocking to provide speeds up to 80 megatransfers/s. dt clocking means that the data is sampled on both the asserting and deasserting edge of req/ack. dt clocking is only valid using a lvd scsi bus. in order to support dt clocking, there are two new phases for the scsi bus. the old data-in and data-out phases are now called single transition (st) data-in and st data-out. the new phases are dt data-in and dt data-out. the use of dt and st phases implies that the scripts engine may use a different jump point for dt or st. table 2.3 illustrates scsi signal con?guration for these phases. to indicate dt or st mode, a bit is set in the current selection data reserved byte. bmove instructions identify the current bmove as either dt or st through the phase bits. table 2.3 new phases on scsi bus phase msg c/d i/o description st data-out 0 0 0 C st data-in 0 0 1 C dt data-out 1 0 0 previously reserved dt data-in 1 0 1 previously reserved
scsi functional description 2-25 2.2.5.2 parallel protocol request (ppr) crc, sync/wide, dt, quick arbitration and selection (qas), and information units are negotiated with a new scsi extended message: transfer period factor (byte 3) C transfer period factor is the old synchronous period value. these are the same with one addition for 80 megatransfers/s rate: the transfer period is related to the data transfer speed, not the clock period. so, in dt mode, 0x09 means 12.5 ns between clock edges which really means a 25 ns clock period. in dt mode, 0x0a would mean a clock period of 50 ns but a data rate of 40 megatransfers/s (25 ns). in st mode, 0x0a would mean a clock period of 25 ns and a data rate of 40 megatransfers/s. req/ack offset (byte 5) C req/ack offset is the maximum scsi offset. transfer width exponent (byte 6) C transfer width exponent is the old width value. it is set to 0 (8-bit scsi width) or 1 (16-bit scsi width). byte 0 0x01 extended message byte 1 0x06 length byte 2 0x04 ppr byte 3 0xxx transfer period factor byte 4 0x00 reserved byte 5 0xxx req/ack offset byte 6 0xxx transfer width exponent byte 7 0x0x protocol options 0x09 = 12.5 ns (ultra160 scsi) only valid when using dt 0x0a = 25 ns (ultra2 scsi) 0x0b = 30.3 ns 0x0c = 50 ns (ultra scsi) 0x0dC0xff = value x4= period in ns
2-26 functional description note: for dt mode or when the protocol options ?eld is nonzero, the transfer width exponent must be one indicating a scsi width of 16 bits. the table indirect data (used during selection/reselection) must be updated to enable certain control bits in the scsi control four (scntl4) register. speci?c bits to look at include: bit 7, u3en (ultra160 transfer enable); bit 6, aipen (asynchronous information protection enable); and bits [3:0] (extra clock setup/hold). protocol options (byte 7) C a bus or device reset, power cycle, or change between lvd/se modes invalidates these settings. a renegotiation resets the protocol options. 2.2.5.3 asynchronous information protection (aip) the aip feature provides error checking for asynchronous, nondata phases through bch encoding. during the command, status, message in/out phases, the bch code is transferred on the upper scsi data bus. for details on the bch code, see t10 119r3 document protection for the asynchronous phases . the aip error status and the live aip code values are captured in the aip control one (aipcntl1) register for debug purposes. aip checking and generation are enabled by setting bit 6 in the scsi control four (scntl4) register. qas_req dt_req iu_req description 0 0 0 use st data-in and st data-out phase to transfer data 0 1 0 use dt data-in and dt data-out phase to transfer data with crc 0 1 1 use dt data-in and dt data-out phase to transfer data with information units 1 1 0 use dt data-in and dt data-out phase to transfer data with crc and use the qas method for arbitration 1 1 1 use dt data-in and dt data-out phase to transfer data with information units and use the qas method for arbitration
scsi functional description 2-27 the sequence id is reset on any phase change, chip reset, bus free, or synchronous phase. it is also reset by writing the rsqaip bit in the aip control zero (aipcntl0) register. the aip sequence value can be read using this register (the seqaip bits). all aip errors are treated in the same fashion as parity errors. bit 0 of the scsi interrupt status zero (sist0) register indicates if scsi parity, crc, or aip errors are present. the raiper bit in the aip control one (aipcntl1) register indicates if the error is an aip error. 2.2.5.4 register considerations the following is a summary of the registers and bits required to enable ultra160 scsi on the lsi53c1010 device. the pci device id register value must be 0x20. the pci max_lat (ml) register contains a value of 0x12, indicating it requires the bus every 4.5 m s. the scsi control zero (scntl0) register: C bit 3, epc (enable parity/crc/aip checking) is set to enable the crc feature. C bit 1, aap (assert satn/ on parity/crc/aip error), is set in the initiator mode to automatically assert satn/ on the detection of an error. the scsi control one (scntl1) register: C bit 5, dhp (disable halt on parity/crc/aip error or atn) (target only), is set in accordance with user requirements. when bit 5 is cleared, a scsi transfer halts if an error occurs. when bit 5 is set, a scsi transfer continues if an error occurs. the scsi control three (scntl3) register: C bit 7 is now reserved. it was previously the ultra enable bit. C bits [6:4], scf[2:0] (synchronous clock conversion factor), select the divisor of the sclk frequency. the sclk is divided before its presentation to the synchronous scsi control logic. C bit 3, ews (enable wide scsi), is set to enable wide scsi. ultra160 requires wide scsi. therefore, this bit must be set during these transfers.
2-28 functional description C bits [2:0] are reserved. the scsi transfer (sxfer) register: C bits [7:6] are reserved. C bits [5:0], mo[5:0] (max scsi synchronous offset), are set for the maximum offset. the scsi status two (sstat2) register: C bit 2 is reserved. hvd scsi is not supported. the scsi interrupt enable zero (sien0) register: C bit 0, par (scsi parity/crc/aip error), is set to detect a parity/crc/aip error while receiving or sending scsi data. for more information, see scsi control one (scntl1) , bit 5. the chip control three (ccntl3) register: C bit 4, endskew (enable req/ack to data skew control) is set to enable control of the relative skew between the scsi req/ack signal and the data signals. C bits [3:2], dskew[1:0] (req/ack C data skew control), control the amount of skew between the scsi req/ack signal and the scsi data signals. these bits are used for ultra160 scsi domain validation only and control the skew only if bit 4 is set. C bits [1:0], lvddl[1:0] (lvd drive strength select), control the drive level of the lvd pad drivers. this feature is intended for use in ultra160 scsi domain validation testing environments only. these bits should be set to 0b00 during normal operation. the scsi control four (scntl4) register: C bit 7, u3en (ultra160 transfer enable) is set to enable ultra160 transfers. C bit 6, aipen (asynchronous information protection enable), is set to enable checking and generation of the upper byte lane of protection information during command, status, and message phases. C bits [5:4] are reserved. C bit 3, xclkh_dt (extra clock of data hold on dt transfer edge) is set to add a clock of data hold to synchronous dt scsi transfers on the dt edge.
scsi functional description 2-29 C bit 2, xclkh_st (extra clock of data hold on st transfer edge) is set to add a clock of data hold to synchronous dt or st scsi transfers on the st edge. this bit impacts both st and dt transfers as it affects data hold to the st edge. C bit 1, xclks_dt (extra clock of data setup on dt transfer edge) is set to add a clock of data setup to synchronous dt scsi transfers on the dt edge. this bit only impacts dt transfers as it affects data setup to the dt edge. C bit 0, xclks_st (extra clock of data setup on st transfer edge) is set to add a clock of data setup to synchronous dt or st scsi transfers on the st edge. this bit impacts both st and dt transfers as it affects data setup to the st edge. note: the xclkh_dt, xclkh_st, xclks_dt, and xclks_st bits do not affect crc timings. the aip control zero (aipcntl0) register: C bit 7, fbaip (force bad aip parity value), forces bad aip values to be sent over the scsi bus. C bit 6, rsqaip (reset aip sequence value), resets the sequence value used in the protection code calculation. C bits [5:4], seqaip (aip sequence value), contain the current aip sequence value. C bits [3:0] are reserved. the aip control one (aipcntl1) register: C bit 7, aiperr (aip error status), indicates the live value of the aip checking logic error status. C bit 6, laiperr (latched aip error status), represents the latched version of the aip checking logic. C bits [5:0], aipv (aip value), indicate the current, calculated protection code value. the crc pad byte value (crcpad) register: C bits [15:0], the crc pad byte value, contain the value placed onto the bus for the crc pad bytes. the crc control zero (crccntl0) register:
2-30 functional description C bit 7, dcrcc (disable crc checking), is set to cause the internal logic to not check or report crc errors during ultra160 transfers. the device continues to calculate and send crcs as requested by the target per spi-3 speci?cation. C bit 6, dcrcpc (disable crc protocol checking) causes the lsi53c1010 to not check for a crc request prior to a phase change on the scsi bus. this condition creates a scsi error condition and makes the device noncompliant with the spi-3 speci?cation. this bit should not be set under normal operating conditions. C bit 5, rstcrcint (reset crc interval counter) resets the internal crc interval counter to zero. C bit 4 is reserved. C bits [3:0], crcint[3:0] (crc request interval (target mode only)), determine when a crc request is sent by the device when operating in target mode and transferring data in dt data-in or dt data-out phases. the crc control one (crccntl1) register: C bit 7, crcerr (crc error), indicates whether or not a crc error has been detected during a dt data-in scsi transfer. this bit is independent of the discrcchk bit setting. to clear this condition, either write this bit to a one or read the scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) registers. when crc checking and the parity/crc/aip error interrupt are both enabled, crcerr is mirrored in the sist0 register, bit 0, as a parity/crc/aip error. C bit 6 is reserved. C bit 5, enas (enable crc auto seed), is set to cause the crc logic to automatically reseed itself after every crc check performed during dt data-in scsi transfers. when this bit is cleared, the scsi control logic controls when the crc logic is reseeded. C bit 4, tstsd (test crc seed), is set to cause the crc logic to immediately reseed itself. this bit should never be set during normal operation as it may cause corrupt crcs to be generated.
scsi functional description 2-31 C bit 3, tstchk (test crc check), is set to cause the crc logic to initiate a crc check. this bit should never be set during normal operation as it creates spurious crc errors. C bit 2, crcadd (crc accumulate), is set to cause the crc block to include the value present in the input register in the current crc calculation. a new output crc value results. this bit should not be set during normal operation as corrupt crc values result. C bits [1:0], crcdsel[1:0] (crc data register selector), control the data visible in the crc data register. the crc data (crcd) register: C bits [31:0] crcdata (crc data). the value in this register is dependent upon the setting of the crcdsel bits. 2.2.5.5 using the scsi clock quadrupler the lsi53c1010 can quadruple the frequency of a 40 mhz scsi clock, allowing the system to perform ultra160 scsi transfers. this option is user selectable with bit settings in the scsi test one (stest1) , scsi test three (stest3) , and scsi control three (scntl3) registers. at power-on or reset, the quadrupler is disabled and powered down. follow these steps to use the clock quadrupler: 1. set the sclk quadrupler enable bit ( scsi test one (stest1) register, bit 3). 2. do not poll bit 5 of the scsi test four (stest4) register. bit 5 is reserved. use a delay of 50 m s after the quadrupler enable bit is set in step 1. 3. halt the scsi clock by setting the halt scsi clock bit ( scsi test three (stest3) register, bit 5). 4. set the clock conversion factor using the scf (synchronous clock conversion factor) ?eld in the scsi control three (scntl3) register. 5. set the sclk quadrupler select bit ( scsi test one (stest1) , bit 2). 6. clear the halt scsi clock bit.
2-32 functional description 2.2.6 prefetching scripts instructions the prefetch logic in the lsi53c1010 fetches 8 dwords of instructions when enabled by setting the prefetch enable bit (bit 5) in the dma control (dcntl) register. the maximum burst size that can be performed is automatically determined using the burst length values in the dma mode (dmode) register. if the unit cannot perform bursts of at least four dwords, it disables itself. while the chip is prefetching scripts instructions, it uses the pci cache commands memory read line and memory read multiple, if pci caching is enabled. note: this feature is only useful when fetching scripts instructions from main memory. due to the short access time of scripts ram, prefetching is not necessary when fetching instructions from scripts ram. to ensure the lsi53c1010 always operates from the current version of the scripts instruction, the contents of the prefetch unit may be ?ushed under certain conditions. the contents of the prefetch unit are automatically ?ushed under the following conditions: on every memory move instruction the memory move instruction is used to place modi?ed code into memory. to assure the device executes recent modi?cations, the prefetch unit ?ushes its contents and reloads the code each time an instruction is issued. to avoid inadvertently ?ushing the prefetch unit contents, use the no flush option for all memory move operations that do not modify code within the next 8 dwords. for more information refer to chapter 5, scsi scripts instruction set. on every store instruction the store instruction may also be used to place modi?ed code directly into memory. to avoid inadvertently ?ushing the prefetch unit contents use the no flush option for all store operations that do not modify code within the next 8 dwords. on every write to the dma scripts pointer (dsp) register on all transfer control instructions, when the transfer conditions are met this is necessary since the next instruction to be executed is not the sequential next instruction in the prefetch unit.
scsi functional description 2-33 when the prefetch flush bit ( dma control (dcntl) register, bit 6) is set the unit ?ushes whenever this bit is set. this bit is self-clearing. 2.2.7 opcode fetch burst capability setting the burst opcode fetch enable bit (bit 1) in the dma mode (dmode) register (0x38) causes the lsi53c1010 to burst in the ?rst two dwords of all instruction fetches. if the instruction is a memory-to- memory move, the third dword is accessed in a separate ownership. if the instruction is an indirect type, the additional dword is accessed in a subsequent bus ownership. if the instruction is a table indirect block move, the device uses two accesses, each a two dword burst, to obtain the four dwords required. note: this feature is only useful if prefetching is disabled. this feature is only useful if fetching scripts instructions from main memory. due to the short access time of scripts ram, burst opcode fetching is not necessary when fetching instructions from scripts ram. 2.2.8 load and store instructions the lsi53c1010 supports the load and store instruction type, which simpli?es data movement between memory and the internal registers. it also enables the chip to transfer bytes to addresses relative to the data structure address (dsa) register. load and store data transfers to or from the scripts ram remain internal to the chip and do not generate pci bus cycles. while a load/store to or from scripts ram is occurring, any external pci slave cycles that occur are retried on the pci bus. setting the disrc (disable internal scripts ram cycles) bit in the chip control zero (ccntl0) register disables this feature. for more information on the load and store instructions, refer to chapter 5, scsi scripts instruction set. 2.2.9 jtag boundary scan testing with one exception, the lsi53c1010 includes support for jtag boundary scan testing in accordance with the ieee 1149.1 speci?cation. the exception concerns the tst_rstn pin. this pin must not be
2-34 functional description toggled as it will reset the jtag tap controller. for more information, refer to the bsdl (boundary scan descriptor language) ?le. this device accepts all required boundary scan instructions including the optional clamp, high-z, and idcode instructions. the optional jtag pin trst is not implemented. reset of the jtag logic through the tap controller occurs when tms is held high for at least 5 tck clock cycles. the lsi53c1010 uses an 8-bit instruction register to support all boundary scan instructions. the data registers included in the device are the boundary data register, the idcode register, and the bypass register. this device can handle a 20 mhz tck frequency with all tap pins having a 50% duty cycle. 2.2.10 parity/crc/aip options the lsi53c1010 implements a ?exible parity scheme that permits control of the parity sense, allows parity checking to be turned on or off, and can deliberately send a byte with bad parity over the scsi bus. table 2.5 de?nes the bits that are involved in parity control and observation. table 2.6 describes the parity control function of the enable parity checking and assert scsi even parity bits in the scsi control one (scntl1) register, bit 2. scripts ram must ?rst be written before being read in order to initialize scripts ram parity. if a scripts ram parity error is encountered, a scsi gross error interrupt will be signaled. the lsi53c1010 supports crc checking and generation in dt phases and crc checking and generation during dt data transfers. the new crc registers are crc pad byte value (crcpad) , crc control zero (crccntl0) , crc control one (crccntl1) , crc data (crcd) , scsi control zero (scntl0) , bit 3; epc (enable parity/crc/aip checking), bit 1; aap (assert satn/ on parity/crc/aip error); scsi control one (scntl1) , bit 5; dhp (disable halt on parity/crc/aip error or atn), and scsi interrupt enable zero (sien0) , bit 0, (scsi parity/crc/aip error). the new aip registers are scsi control zero (scntl0) , aip control zero (aipcntl0) , and aip control one (aipcntl1) .
scsi functional description 2-35 table 2.4 bits used for parity/crc/aip control and generation bit name location description aap (assert satn/ on parity/crc/aip errors) scsi control zero (scntl0) , bit 1 when this bit is set, the lsi53c1010 scsi function automatically asserts the satn/ signal upon detection of a parity, crc, or aip error. satn/ is only asserted in initiator mode. epc (enable parity/crc/aip checking) scsi control zero (scntl0) , bit 3 when set, this bit enables parity checking on the lsi53c1010. the lsi53c1010 checks for odd parity. assert even scsi parity scsi control one (scntl1) , bit 2 when set, this bit forces even scsi parity on each byte sent to the scsi bus from the lsi53c1010. disable halt on satn/ or parity/crc/aip error (target mode only) scsi control one (scntl1) , bit 5 this bit determines if the lsi53c1010 should halt operations when a parity error is detected in target mode. enable parity/crc/aip error interrupt scsi interrupt enable zero (sien0) , bit 0 this bit determines whether the lsi53c1010 generates an interrupt when it detects a scsi parity/crc/aip error. parity error scsi interrupt status zero (sist0) , bit 0 this status bit is set whenever the lsi53c1010 detects a parity/crc/aip error on the scsi bus. status of scsi parity signal scsi status zero (sstat0) , bit 0 this status bit represents the active high current state of the scsi sdp0 parity signal. scsi sdp1 signal scsi status two (sstat2) , bit 0 this bit represents the active high current state of the scsi sdp1 parity signal. latched scsi parity scsi status two (sstat2) , bit 3 scsi status one (sstat1) , bit 3 these bits re?ect the scsi odd parity signal corresponding to the data latched into the scsi input data latch (sidl) register. master parity error enable chip test four (ctest4) , bit 3 this bit enables parity checking during pci master data phases. master data parity error dma status (dstat) , bit 6 this bit is set when the lsi53c1010, as a pci master, detects a target device signaling a parity error during a data phase. master data parity error interrupt enable dma interrupt enable (dien) , bit 6 by clearing this bit, a master data parity error does not cause assertion of inta/ (or intb/) but the status bit is set in the dma status (dstat) register. aip checking scsi control four (scntl4) , bit 6 setting this bit enables the aip checking and generation of the upper byte lane of protection information during command, status, and message phases.
2-36 functional description crc request pending scsi control zero (scntl0) , bit 2 this bit indicates it is acceptable to force a crc request. this bit will only be clear when a crc request has been sent and no data has been transferred since the request. this bit may be used to prevent back-to-back crc conditions. disable crc checking crc control zero (crccntl0) , bit 7 this bit is set to cause internal logic not to check or report crc errors during ultra160 transfers. disable crc protocol checking crc control zero (crccntl0) , bit 6 this bit is set to cause the device to not check for a crc request prior to a phase change on the scsi bus. this condition normally causes a scsi error condition. note: setting this bit makes the lsi53c1010 noncompliant to the spi-3 speci?cation. this bit should not be set under normal operating conditions. crc reset counter (target mode only) crc control zero (crccntl0) , bit 5 when set, this bit resets the internal crc interval counter to zero. crc interval counter (target mode only) crc control zero (crccntl0) , bits [3:0] these bits determine when a crc request is sent out by the device. the interval is only applicable when the device is operating in target mode and transferring data in dt data-in or dt data-out phases. the intervals are provided, in bytes, as: 0x0 = disabled; 0x1 = 128; 0x2 = 256; 0x3 = 512; ... ; 0x9 = 32768; 0xa = 65536; 0xbC0xf = reserved. table 2.5 scsi parity errors and interrupts dhp 1 1. dhp = disable halt on satn/ or parity error (bit 5, scsi control one (scntl1) ) pa r 2 2. par = parity error (bit 0 scsi interrupt enable one (sien1) ) description 0 0 halts when a parity error occurs in the target or initiator mode and does not generate an interrupt. 0 1 halts when a parity error occurs in the target mode and generates an interrupt in the target or initiator mode. 1 0 does not halt in target mode when a parity error occurs until the end of the transfer. an interrupt is not generated. 1 1 does not halt in target mode when a parity error occurs until the end of the transfer. an interrupt is generated. table 2.4 bits used for parity/crc/aip control and generation (cont.) bit name location description
scsi functional description 2-37 2.2.11 dma fifo the dma fifo is 8 bytes wide by 112C115 transfers deep depending on the type and direction of data transfer. the dma fifo is illustrated in figure 2.2 . the small fifo mode (112 bytes) is not supported by the lsi53c1010. figure 2.2 dma fifo sections the lsi53c1010 supports 64-bit memory and automatically supports misaligned dma transfers. the fifo allows the lsi53c1010 to support 4, 8, 16, 32, 64, or 128 dword bursts across the pci bus interface. 2.2.12 scsi data paths the data path through the lsi53c1010 is dependent on whether data is moved into or out of the chip and whether the scsi data transfer is asynchronous or synchronous. figure 2.3 illustrates how data is moved to and from the scsi bus in each of the different modes. the following sections determine if any bytes remain in the data path when the device halts an operation. 112C115 transfers deep . . . . . . 8 bytes wide byte lane 7 byte lane 6 byte lane 5 byte lane 4 byte lane 3 byte lane 2 byte lane 1 byte lane 0
2-38 functional description figure 2.3 lsi53c1010 host interface scsi data paths 2.2.12.1 asynchronous scsi send to determine the number of bytes remaining in the dma fifo when a phase mismatch occurs, read the dma fifo byte count (dfbc) register. this 16-bit read only register contains the actual number of bytes remaining in the dma fifo. in addition, the scsi output data latch (sodl) register must be checked to determine if it contains any remaining bytes. if bit 5 (olf) in the scsi status zero (sstat0) register is set, then the least signi?cant byte in the sodl register contains data. if bit 5 (olf1) in the scsi status two (sstat2) register is set, then the most signi?cant byte in the sodl register contains data. checking these bits also reveals bytes left in the sodl register from a chained move operation with an odd byte count. to recover from all other error conditions, the dma fifo should be cleared by setting bit 2 (clf) in chip test three (ctest3) and the i/o should be retried. if the wide scsi send (wss) bit in the scsi control two (scntl2) register is set when a phase mismatch occurs, then adjustments must be made to the previous block move, not the current block move loaded into dcmd/dbc. to recover the byte of chain data in the sodl register the previous block move byte count should be set to 1 and the address set to the last data address for that block move. pci interface dma fifo sodl register scsi interface pci interface dma fifo sidl register scsi interface pci interface dma fifo scsi interface pci interface dma fifo scsi interface scsi fifo asynchronous scsi send asynchronous scsi receive synchronous scsi send synchronous scsi receive swide register chain byte holding register chain byte holding register
scsi functional description 2-39 2.2.12.2 synchronous scsi send the dma fifo is the only location where data can reside when a phase mismatch occurs during a synchronous scsi send transfer. to determine the number of bytes remaining in the dma fifo, read the dma fifo byte count (dfbc) register. this 16-bit, read only register contains the actual number of bytes remaining in the dma fifo. to recover from all other error conditions the dma fifo should be cleared by setting bit 2 (clf) in chip test three (ctest3) and the i/o should be retried. if the wide scsi send (wss) bit in the scsi control two (scntl2) register is set when a phase mismatch occurs, then adjustments must be made to the previous block move, not the current block move loaded into dcmd/dbc. to recover the byte of chain data in the outbound chain byte holding register, the previous block move byte count should be set to one and the address set to the last data address for that block move. 2.2.12.3 asynchronous scsi receive when a phase mismatch occurs during an asynchronous scsi receive, the only data that may remain in the device is a potential wide residue byte in the scsi wide residue (swide) register. if bit 0 (wsr) in scsi control two (scntl2) is set, then the swide register contains a residual byte. this byte can be ?ushed by executing a block move instruction with a byte count of one. to recover from all other error conditions the dma fifo should be cleared by setting bit 2 (clf) in chip test three (ctest3) and the i/o should be retried. 2.2.12.4 synchronous scsi receive when a phase mismatch occurs during a synchronous scsi receive transfer no data recovery operation is necessary. all data, including chain bytes from chained block moves, are ?ushed from the device prior to the phase mismatch occurring. to recover from all other error conditions, the dma fifo should be cleared by setting bit 2 (clf) in chip test three (ctest3) , the scsi fifo should be cleared by setting bit 1 (csf) in scsi test three (stest3) , and the i/o should be retried. 2.2.13 scsi bus interface the lsi53c1010 performs se and lvd transfers.
2-40 functional description 2.2.13.1 scsi bus modes to increase device connectivity and scsi cable length, the lsi53c1010 features lvdlink technology, the lsi logic implementation of lvd scsi. lvdlink transceivers provide the inherent reliability of differential scsi and a long-term migration path for faster scsi transfer rates. hvd is not supported by this device. bit 2 (diff) of the scsi status two (sstat2) register and bit 5 (dif) of the scsi test two (stest2) register are now reserved. the a_diffsens or b_diffsens signals still detect the different input voltages for hvd, lvd, and se but the hvd feature is not present. 2.2.13.2 scsi termination the terminator networks pull signals to an inactive voltage level and match the impedance seen at the end of the cable with the characteristic impedance of the cable. terminators must be installed at the extreme ends of the scsi chain, and only at the ends; no system should ever have more or less than two terminators. scsi host adapters should provide a means of accommodating terminators. there should be a means of disabling the termination. se cables can use a 220 w pull-up resistor to the terminator power supply (term power) line and a 330 w pull-down resistor to ground. because of the high-performance nature of the lsi53c1010, regulated (or active) termination is recommended. figure 2.4 shows an active terminator. tolerant technology active negation can be used with either termination network. for information on terminators that support lvd, refer to the spi-3 draft standard. note: if the lsi53c1010 is used in a design with an 8-bit scsi bus, all 16 data lines must be terminated.
scsi functional description 2-41 figure 2.4 regulated termination for ultra160 scsi 2.2.14 select/reselect during selection/reselection in multithreaded scsi i/o environments, it is not uncommon to be selected or reselected while trying to perform selection/reselection. this situation may occur when a scsi controller (operating in the initiator mode) tries to select a target and is reselected by another. the select scripts instruction has an alternate address to which the scripts will jump when this situation occurs. the analogous situation for target devices is being selected while trying to perform a reselection. once a change in operating mode occurs, either the initiator scripts issues a set initiator instruction or the target scripts issues a set target instruction. the selection and reselection enable bits ( scsi chip id (scid) bits 5 and 6, respectively) should both be asserted, enabling the lsi53c1010 to respond as an initiator or as a target. if only selection is enabled, the lsi53c1010 cannot be reselected as an initiator. status 4 5 6 7 11 12 13 14 15 16 17 line1+ line1 - line2+ line2 - line3+ line3 - line4+ line4 - line5+ line5 - disconnect line9 - line9+ line8 - line8+ line7 - line7+ line6 - line6+ se lv d hvd diffsens diff b 32 31 30 29 25 24 23 22 33 34 35 20 21 4.7 m f to led drivers sdp0 - sdp0+ sd7 - sd7+ sd6 - sd6+ sd5 - sd5+ sd0+ sd0 - sd1+ sd1 - sd2+ sd2 - sd3+ sd3 - sd4+ sd4 - 51 k diffsens connects to the scsi bus diffsens line to detect what type of devices (se, lvd, or hvd) are connected to the scsi bus. disconnect shuts down the terminator when it is not at the end of the bus. the disconnect pin low enables the terminator.
2-42 functional description bits, in the scsi interrupt status zero (sist0) register, and interrupt bits, in the scsi interrupt enable zero (sien0) register, indicate if the lsi53c1010 has been selected or reselected. 2.2.15 synchronous operation the lsi53c1010 can transfer synchronous scsi data in both the initiator and target modes. the lsi53c1010s sclk input must be connected to a 40 mhz oscillator. the scsi transfer (sxfer) register controls the synchronous offset while the scsi control three (scntl3) register controls the synchronous clock converters. these registers may be loaded by the cpu before scripts execution begins, from within scripts, with a table indirect i/o instruction, or with a read-modify- write instruction. the lsi53c1010 can receive data from the scsi bus at a synchronous transfer period as short as 12.5 ns, regardless of the transfer period used to send data. the lsi53c1010 can receive data at one-fourth of the divided sclk frequency. depending on the sclk frequency, the negotiated transfer period, and the synchronous clock divider, the lsi53c1010 can send synchronous data at intervals as short as 12.5 ns for ultra160 scsi, 25 ns for ultra2 scsi, 50 ns for ultra scsi, 100 ns for fast scsi and 200 ns for scsi-1. synchronous data transfer rates are controlled by bits in two different registers of the lsi53c1010. following is a brief description of these bits and the method used to determine the data transfer rate. 2.2.15.1 scsi control three (scntl3) register, bits [6:4] (scf[2:0]) description the scf[2:0] bits select the factor by which the frequency of sclk is divided before its presentation to the synchronous scsi control logic. the synchronous transfer speed is determined by the combination of the divided clock and the setting of the xclks_st, xclks_dt, xclkh_st, and xclkh_dt bits in the scsi control four (scntl4) register. the table below gives the clock dividers available. refer to table 4.4 , double transition transfer rates, and table 4.5, single transition transfer rates, located in the scsi control four (scntl4) register description, for a full list of available synchronous transfer rates.
scsi functional description 2-43 the scf divisor values are provided in table 2.7 . 2.2.15.2 scsi control four (scntl4) register, bits [3:0] description the following extra clock bits add an extra clock of setup or hold to a st or dt transaction. bit 3, xclkh_dt (extra clock of data hold on dt transfer edge), adds a clock of data hold to synchronous dt scsi transfers on the dt edge. this bit only impacts dt transfers as it only affects data hold to the dt edge. setting this bit reduces the synchronous transfer send rate but will not reduce the rate at which the lsi53c1010 receives outbound reqs, acks, or data. bit 2, xclkh_st (extra clock of data hold on st transfer edge), adds a clock of data hold to synchronous dt or st scsi transfers on the st edge. this bit impacts dt and st transfers as it affects data hold to the st edge. setting this bit reduces the synchronous transfer send rate but will not reduce the rate at which the lsi53c1010 receives outbound reqs, acks, or data. bit 1, xclks_dt (extra clock of data setup on dt transfer edge), adds a clock of data setup to synchronous dt scsi transfers on the dt edge. this bit only impacts dt transfers as it only affects data hold to the dt edge. setting this bit reduces the synchronous transfer send rate but will not reduce the rate at which the lsi53c1010 receives outbound reqs, acks, or data. table 2.6 scf divisor values scf2 scf1 scf0 sclk divisor 0 0 0 sclk/3 0 0 1 sclk/1 0 1 0 sclk/1.5 0 1 1 sclk/2 1 0 0 sclk/3 1 0 1 sclk/4 1 1 0 sclk/6 1 1 1 sclk/8
2-44 functional description bit 0, xclks_st (extra clock of data setup on st transfer edge), adds a clock of data setup to synchronous dt or st scsi transfers on the st edge. this bit impacts dt and st transfers as it affects data hold to the st edge. setting this bit reduces the synchronous transfer send rate but will not reduce the rate at which the lsi53c1010 receives outbound reqs, acks, or data. 2.2.15.3 determining the data transfer rate the synchronous receive rate can be calculated using the following formula: note: the receive rate is independent of the settings of the xclks_dt, xclks_st, xclkh_dt, xclkh_st bits. the synchronous send rate, in units of megatransfers/s, can be calculated using the following formula: to con?gure the lsi53c1010 for ultra160 dt transfers, perform the following steps: step 1. enable the scsi clock quadrupler C the lsi53c1010 can quadruple the frequency of a 40 mhz scsi clock, allowing the system to perform ultra160 scsi transfers. this option is user selectable through bit settings in the scsi test one (stest1) register. at power-up or reset, the quadrupler is disabled and powered down. follow the steps in the bit description to enable the clock quadrupler. step 2. program the transfer rate C using scsi control three (scntl3) and scsi control four (scntl4) , program the register to the 160 mbytes/s transfer rate. receive rate (dt) input clock rate scf divisor 2 () ---------------------------------------------- (megatransfers/s) = receive rate (st) input clock rate scf divisor 4 () ---------------------------------------------- (megatransfers/s) = send rate (dt) input clock rate scf divisor 2 xclks_dt+xclks_st+xclkh_dt+xclkh_st 2 ------------------------------------------------------------------------------------------------------------------------------- ------- + ? ?? ------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------ - = send rate (st) input clock rate scf divisor 4 xclks_st+xclkh_st + () --------------------------------------------------------------------------------------------------------------------- - =
scsi functional description 2-45 step 3. program the maximum scsi offset C using scsi transfer (sxfer) , program the maximum scsi dt synchronous offset to 0x3e. step 4. enable tolerant C set the tolerant enable bit, scsi test three (stest3) , bit 7. active negation must be enabled for the lsi53c1010 to perform ultra160 scsi transfers. figure 2.5 illustrates the clock division factors used in each register as well as the role of the register bits in determining the transfer rate. an example of con?guring the ultra160 scsi transfer speed is: 1. set scntl3 to 0x18. 2. set sxfer to 0x3e. 3. set scntl4 to 0x80. these settings program the lsi53c1010 scsi clocks to send and receive at 160 mhz with a synchronous scsi offset of 0x3e.
2-46 functional description figure 2.5 determining the synchronous transfer rate 2.2.16 interrupt handling the scripts processors in the lsi53c1010 perform most functions independently of the host microprocessor. however, certain interrupt situations must be handled by the external microprocessor. this section explains all aspects of interrupts as they apply to the lsi53c1010. 2.2.16.1 polling and hardware interrupts the external microprocessor is informed of an interrupt condition by polling or hardware interrupts. polling means that the microprocessor must continually loop and read a register until it detects a bit that is set 40 mhz clock quadrupler scf divider asynchronous divider asynchronous scsi logic divide by 4 (st) scf2 scf1 scf0 scf divisor 0003 0011 0101.5 0112 1003 1014 1106 receive/send divide by 2 (dt) sclk rate received rate (dt) input clock rate scf divisor 2 () ---------------------------------------------- (megatransfers/s) = receive rate (st) input clock rate scf divisor 4 () ---------------------------------------------- (megatransfers/s) = send rate (dt) input clock rate scf divisor 2 xclks_dt xclks_st xclkh_dt xclkh_st ++ + 2 ------------------------------------------------------------------------------------------------------------------------------- --------------- - + ? ?? ------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------- - = send rate (st) input clock rate scf divisor 4 xclks_st xclkh_st ++ () ------------------------------------------------------------------------------------------------------------------------ - =
scsi functional description 2-47 indicating an interrupt. this method is the fastest, but it diverts cpu time from other system tasks. the preferred method of detecting interrupts in most systems is hardware interrupts. in this case, the lsi53c1010 asserts the interrupt request (inta/ or intb/) line that interrupts the microprocessor, causing the microprocessor to execute an interrupt service routine (isr). a hybrid approach would use hardware interrupts for long waits and polling for short waits. scsi function a is routed to pci interrupt inta/. scsi function b is normally routed to intb/, but can be routed to inta/ if a pull-up is connected to mad[4]. see section 3.8, mad bus programming, for additional information. 2.2.16.2 registers the registers in the lsi53c1010 used for detecting or de?ning interrupts are scsi interrupt status zero (sist0) , scsi interrupt status one (sist1) , dma status (dstat), scsi interrupt enable zero (sien0) , scsi interrupt enable one (sien1) , and dma interrupt enable (dien) . see the register descriptions in chapter 4, registers for additional information. istat C the istat register includes the interrupt status zero (istat0), interrupt status one (istat1) , mailbox zero (mbox0) , and mailbox one (mbox1) registers. it is the only register that can be accessed as a slave during the scripts operation. therefore, it is the register that is polled when polled interrupts are used. it is also the ?rst register that should be read after the inta/ (or intb/) pin is asserted in association with a hardware interrupt. the intf (interrupt-on-the-fly) bit should be the ?rst interrupt serviced. it must be written to one in order to clear it. this interrupt must be cleared before servicing any other interrupts indicated by sip or dip. do not attempt to read the other chip status registers if the intf bit is set, but sip or dip are not set. if the sip bit in the interrupt status zero (istat0) register is set, then a scsi-type interrupt has occurred and the scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) registers should be read.
2-48 functional description if the dip bit in the interrupt status zero (istat0) register is set, then a dma-type interrupt has occurred and the dma status (dstat) register should be read. scsi-type and dma-type interrupts may occur simultaneously, so in some cases both sip and dip may be set. to avoid missing a scsi interrupt the scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) registers should be read before the dma status (dstat) register is read. when set, the sirqd bit in interrupt status one (istat1) disables the int/ pin for the corresponding scsi function. the interrupt is not lost or ignored but is merely masked at the pin. if the int/ pin is already asserted when sirqd is set the int/ pin will remain asserted until the interrupt is serviced. future interrupts will be masked at the pin until sirqd is cleared. note that the host can read istat as the scripts code is writing to i s tat. i n this case the data will be unstable so the read should be retried. sist0 and sist1 C the scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) registers contain the status of scsi-type interrupts whether they are enabled in scsi interrupt enable zero (sien0) and scsi interrupt enable one (sien1) or not. reading these registers determines the conditions that caused the scsi-type interrupt, clears any bits that are set in sist0 and sist1, and clears the sip bit in interrupt status zero (istat0) . since the LSI53C1010-33 scsi functions stack interrupts, sist0 and sist1 are not necessarily cleared after a read; additional interrupts may still be pending. if the lsi53c1010 is receiving data from the scsi bus and a fatal interrupt condition occurs, the chip attempts to send the contents of the dma fifo to memory before generating the interrupt. reading scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) will clear the crc error bit (bit 7) in the crc control one (crccntl1) register. if the lsi53c1010 is sending data to the scsi bus and a fatal scsi interrupt condition occurs, data could remain in the dma fifo. to determine if the dma fifo is empty, check the dma fifo empty (dfe) bit in dma status (dstat) register. if this bit is cleared, set the clf (clear dma fifo) and csf (clear scsi fifo) bits before continuing.
scsi functional description 2-49 the clf bit is bit 2 in chip test three (ctest3) register. the csf bit is bit 1 in scsi test three (stest3) register. dstat C the dma status (dstat) register contains the status of dma-type interrupts whether they are enabled in dien or not. reading this register determines which condition(s) caused the dma-type interrupt, clears any interrupt related bits in ds tat, a n d clears the dip bit in interrupt status zero (istat0) . since the LSI53C1010-33 scsi functions stack interrupts, reading dstat does not necessarily clear the register as additional interrupts may be pending. bit 7 in dma status (dstat) , dfe, is purely a status bit; it will not generate an interrupt and will not be cleared when read. dma interrupts do not ?ush the dma or scsi fifos before generating the interrupt. therefore, the dfe bit in the dstat register should be checked after any dma interrupt. if the dfe bit is cleared, the fifos must either be cleared by setting the clf (clear dma fifo in ctest3) and csf (clear scsi fifo in stest3) bits, or ?ushed by setting the flf (flush dma fifo in ctest3) bit. sien0 and sien1 C the scsi interrupt enable zero (sien0) and scsi interrupt enable one (sien1) registers are the interrupt enable registers for the scsi interrupts in scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) . clearing the appropriate mask bit masks an interrupt. dien C the dma interrupt enable (dien) register is the interrupt enable register for dma interrupts in dma status (dstat) . clearing the appropriate mask bit masks an interrupt. 2.2.16.3 fatal vs. nonfatal interrupts a fatal interrupt, as the name implies, always causes the scripts to stop running. all nonfatal interrupts become fatal when they are enabled by setting the appropriate interrupt enable bit. interrupt masking is discussed in section 2.2.16.4, masking. all dma interrupts are fatal. the dma interrupts are indicated by the dip bit in interrupt status zero (istat0) and one or more bits in dma status (dstat) .
2-50 functional description some scsi interrupts are nonfatal. the scsi interrupts are indicated by the sip bit in the interrupt status zero (istat0) register and one or more bits in scsi interrupt status zero (sist0) register or scsi interrupt status one (sist1) register. when the lsi53c1010 is operating in the initiator mode, interrupt-on-the- fly, function complete (cmp), selected (sel), reselected (rsl), general purpose timer expired (gen), and handshake-to-handshake timer expired (hth) interrupts are nonfatal. when operating in the target mode, interrupt-on-the-fly, satn/ active (m/a), cmp, sel, rsl, gen, and hth are nonfatal. refer to the description for the disable halt on a parity/crc/aip error or satn/ active (target mode only) bit, dhp, in the scsi control one (scntl1) register to con?gure the chips behavior when the satn/ interrupt is enabled during target mode operation. the reason for nonfatal interrupts is to prevent the scripts from stopping when an interrupt occurs that does not require service from the cpu. this prevents an interrupt when arbitration is complete (cmp set), when the lsi53c1010 is selected or reselected (sel or rsl set), when the initiator asserts atn (target mode: satn/ active), or when the general purpose or handshake-to-handshake timers expire. these interrupts are not needed for events that occur during high level scripts operation. 2.2.16.4 masking masking an interrupt means disabling or ignoring that interrupt. clearing bits in the scsi interrupt enable zero (sien0) and scsi interrupt enable one (sien1) registers will mask scsi interrupts. clearing bits in the dma interrupt enable (dien) register will mask dma interrupts. masking an interrupt after inta/ (or intb/) is asserted does not cause inta/ (or intb/) to be negated. how the chip responds to masked interrupts depends on: whether polling or hardware interrupts are being used; whether the interrupt is fatal or nonfatal; and whether the chip is operating in the initiator or target mode. if a nonfatal interrupt occurs while masked, scripts continues. the appropriate bit in the scsi interrupt status zero (sist0) or scsi interrupt status one (sist1) is still set, the sip bit in the interrupt status zero (istat0) is not set, and the inta/ (or intb/) pin is not asserted.
scsi functional description 2-51 if a fatal interrupt occurs while masked, scripts halts. the appropriate bit in the dma status (dstat) , scsi interrupt status zero (sist0) ,or scsi interrupt status one (sist1) register is set, the sip or dip bit in the interrupt status zero (istat0) register is set, but the inta/ (or intb/) pin is not asserted. setting the sirqd bit in the interrupt status one (istat1) register disables the interrupt pin for the corresponding scsi function. if an interrupt pin is already asserted and sirqd is then set, the interrupt pin will remain asserted until serviced. further interrupts will be blocked from the interrupt pin. when the lsi53c1010 is initialized, enable all fatal interrupts if hardware interrupts are being used. if a fatal interrupt is disabled and that interrupt condition occurs, the scripts halts and the system never knows it unless it times out and checks the interrupt status zero (istat0) , interrupt status one (istat1) , mailbox zero (mbox0) , and mailbox one (mbox1) registers after a certain period of inactivity. if istat is being polled instead of using hardware interrupts, then masking a fatal interrupt makes no difference since the sip and dip bits in the interrupt status zero (istat0) inform the system of interrupts, not the inta/ (or intb/) pin. 2.2.16.5 stacked interrupts the lsi53c1010 will stack interrupts, if they occur, one after the other. if the sip or dip bits in the interrupt status zero (istat0) register are set (?rst level), there is already at least one pending interrupt. any future interrupts are stacked in extra registers behind the scsi interrupt status zero (sist0) , scsi interrupt status one (sist1) , and dma status (dstat) registers (second level). when two interrupts have occurred and the two levels of the stack are full, any further interrupts set additional bits in the extra registers behind sist0, sist1, and dstat. when the ?rst level of interrupts are cleared, all the later interrupts move into sist0, sist1, and ds tat. after the ?rst interrupt is cleared, the inta/ (or intb/) pin is deasserted for a minimum of three clks; the stacked interrupts move into sist0, sist1, or dstat; and the inta/ (or intb/) pin is asserted once again.
2-52 functional description since a masked nonfatal interrupt does not set the sip or dip bits, interrupt stacking does not occur. a masked, nonfatal interrupt still posts the interrupt in scsi interrupt status zero (sist0) , but does not assert the inta/ (or intb/) pin. since no interrupt is generated, future interrupts move into scsi interrupt status zero (sist0) or scsi interrupt status one (sist1) instead of stacking behind another interrupt. when another interrupt condition occurs, the bit corresponding to the earlier masked nonfatal interrupt is set. a related situation to interrupt stacking is when two interrupts occur simultaneously. since stacking does not occur until the sip or dip bits are set, there is a small timing window in which multiple interrupts can occur but are not stacked. these could be multiple scsi interrupts (sip set), multiple dma interrupts (dip set), or multiple scsi and multiple dma interrupts (both sip and dip set). as previously mentioned, dma interrupts do not attempt to ?ush the fifos before generating the interrupt. it is important to set either the clear dma fifo (clf) and clear scsi fifo (csf) bits if a dma interrupt occurs and the dma fifo empty (dfe) bit is not set. this is because any future scsi interrupts are not posted until the dma fifo is cleared of data. these locked out scsi interrupts are posted as soon as the dma fifo is empty. 2.2.16.6 halting in an orderly fashion when an interrupt occurs, the lsi53c1010 attempts to halt in an orderly fashion. if the interrupt occurs in the middle of an instruction fetch, the fetch is completed, except in the case of a bus fault. execution does not begin, but the dsp points to the next instruction since it is updated when the current instruction is fetched. if the dma direction is a write to memory and a scsi interrupt occurs, the lsi53c1010 attempts to ?ush the dma fifo to memory before halting. under any other circumstances, only the current cycle is completed before halting, so the dfe bit in dma status (dstat) should be checked to determine if any data remains in the dma fifo. scsi sreq/sack handshakes that are in progress are completed before halting.
scsi functional description 2-53 the lsi53c1010 attempts to clean up any outstanding synchronous offset before halting. in the case of transfer control instructions, once instruction execution begins it continues to completion before halting. in the case of a jump/call when/if instruction, the dma scripts pointer (dsp) is updated to the transfer address before halting. all other instructions may halt before completion. 2.2.16.7 sample interrupt service routine the following is a sample of an interrupt service routine (isr) for the lsi53c1010. it can be repeated if polling is used, or should be called when the inta/ (or intb/) pin is asserted if hardware interrupts are used. 1. read interrupt status zero (istat0) . 2. if the intf bit is set, write it to a one to clear this status. 3. if only the sip bit is set, read scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) to clear the scsi interrupt condition and get the scsi interrupt status. the bits in the sist0 and sist1 tell which scsi interrupts occurred and determine what action is required to service the interrupts. 4. if only the dip bit is set, read dma status (dstat) to clear the interrupt condition and determine the dma interrupt status. the bits in the dstat register indicate which dma interrupts occurred and determine what action is required to service the interrupts. 5. if both the sip and dip bits are set, read scsi interrupt status zero (sist0) , scsi interrupt status one (sist1) , and dma status (dstat) to clear the scsi and dma interrupt condition and determine the interrupt status. if using 8-bit reads of the sist0, sist1, and dstat registers to clear interrupts, insert a 12 clock delay between the consecutive reads to ensure that the interrupts clear properly. both the scsi and dma interrupt conditions should be handled before leaving the isr. it is recommended that the dma interrupt is serviced before the scsi interrupt, because a serious dma interrupt condition could in?uence how the scsi interrupt is acted upon.
2-54 functional description 6. when using polled interrupts go back to step 1 before leaving the isr in case any stacked interrupts moved in when the ?rst interrupt was cleared. when using hardware interrupts, the inta/ (or intb/) pin is asserted again if there are any stacked interrupts. this should cause the system to re-enter the isr. 2.2.17 interrupt routing this section documents the recommended approach to raid ready interrupt routing for the lsi53c1010. in order to be compatible with raid upgrade products and the lsi53c1010, the following requirements must be met: when a raid upgrade card is installed in the upgrade slot, interrupts from the mainboard scsi controller(s) assigned to the raid upgrade card must be routed to intc/ and intd/ of the upgrade slot and isolated from the mainboard interrupt controller. the system processor must not see interrupts from the scsi controllers that are serviced by the raid upgrade card. an upgrade slot is one that is connected to the interrupt routing logic for mainboard scsi device(s). when a pci raid upgrade board is installed into the system, it will be plugged into this slot if it is to control mainboard scsi device(s). the tdi pin of the upgrade slot must be connected to the int_dir/ pin of the lsi53c1010. when a raid upgrade card is not installed, interrupts from a scsi core must not be presented to the systems interrupt controller using multiple interrupt inputs. figure 2.6 shows an example con?guration. in this example the lsi53c1010 contains the interrupt routing logic. the lsi53c1010 supports four different interrupt routing modes. additional information for these modes may be found in the register description of scsi test one (stest1) description in chapter 4, registers. each scsi core within the chip may be con?gured independently by selecting the interrupt routing mode using bits [1:0] in the scsi test one (stest1) register within each core. mode 0 is the default mode and is compatible with raid upgrade products.
scsi functional description 2-55 if the implementation shown in figure 2.6 is used, intc/ and intd/ of the pci raid upgrade slot cannot be used when a non-raid upgrade card is installed in the slot. if this restriction is not acceptable, additional buffer logic must be implemented on the mainboard. as long as the interrupt routing requirements stated above are satis?ed, a mainboard designer could implement this design with external logic. figure 2.6 interrupt routing hardware using the lsi53c1010 there can only be one entity controlling a mainboard scsi core or con?icts will occur. typically a scsi core will be controlled by the scsi bios and an operating system driver. when a scsi core is allocated to a raid adapter, however, a mechanism must be implemented to prevent the scsi bios and operating system driver from trying to access the scsi core. the mainboard designer has several options to choose from for doing this: the ?rst option is to have the scsi core load its pci subsystem id using a serial eprom on power-up. if bit 15 in this id is set, the lsi logic bios and operating system drivers will ignore the chip. this makes it possible to control the assignment of the mainboard scsi cores using a con?guration utility. a4 a6 a7 b8 b7 scsi core a scsi core b lsi53c1010 alt_inta/ 2.7 k + 5 v inta/ alt_intb/ intb/ 2.7 k + 5 v intb/ intd/ inta/ intc/ tdi + 5 v int_dir pci raid upgrade slot inta/ pci raid upgrade slot intb/ mbyte scsi inta/ mbyte scsi intb/ these interrupt lines are connected to the other pci slot interrupt lines as determined by the mainboard interrupt routing scheme. 10 k pci raid upgrade slot
2-56 functional description the second option is to provide mainboard and system bios support for nonvolatile storage (nvs). the scsi core may then be enabled or disabled using the scsi bios con?guration utility. not all versions of the lsi logic drivers support this capability. the third option is to have the system bios not report the existence of the scsi controller chips when the scsi bios and operating systems make pci bios calls. this approach requires modi?cations to the system bios and assumes the operating system uses pci bios calls when searching for pci devices. 2.2.18 chained block moves since the lsi53c1010 has the capability to transfer 16-bit wide scsi data, a unique situation occurs when dealing with odd bytes. the chained move (chmov) scripts instruction along with the wide scsi send (wss) and wide scsi receive (wsr) bits in the scsi control two (scntl2) register are used to facilitate these situations. the chained block move instruction is illustrated in figure 2.7 . figure 2.7 block move and chained block move instructions chmov 5, 3 when data-out 0x03 0x02 0x01 0x00 0x07 0x06 0x05 0x04 0x0b 0x0a 0x09 0x08 0x0f 0x0e 0x0d 0x0c 0x13 0x12 0x11 0x10 0x04 0x03 0x06 0x05 0x09 0x07 0x0b 0x0a 0x0d 0x0c 32 bits 16 bits host memory scsi bus 0x00 0x04 0x08 0x0c 0x10
scsi functional description 2-57 moves ?ve bytes from address 0x03 in the host memory to the scsi bus. bytes 0x03, 0x04, 0x05, and 0x06 are moved and byte 0x07 remains in the scsi core (in the lower byte of the scsi output data latch (sodl) register for asynchronous transfers, in the outbound chain byte holding register for synchronous transfers). the stored byte is combined with the ?rst byte of the following chmove instruction. chain move 0x5, 0x9 when data-in moves ?ve bytes from address 0x09 in the host memory to the scsi bus. the data in address 0x09 is married with the stored data (0x07) and transferred to the scsi bus. 2.2.18.1 wide scsi send bit the wss bit is set following a wide scsi send operation (data-out for initiator mode or data-in for target mode) when the scsi core is holding a byte of chain data. the scsi core holds the byte when the controller detects a partial transfer at the end of a chained block move scripts instruction. this ?ag is not set if a normal block move instruction is used. under this condition, the scsi controller does not send the low-order byte of the last partial memory transfer across the scsi bus. instead, the low-order byte is temporarily stored in the lower byte of the scsi output data latch (sodl) register for asynchronous transfers or in the chain byte holding register for synchronous transfers and the wss ?ag is set. the hardware uses the wss bit to determine what behavior must occur at the start of the next data send transfer. if the wss bit is set at the start of the next transfer, the ?rst byte (the high-order byte) of the next data send transfer is married with the byte of chain data. the two bytes are sent out across the bus regardless of the type of block move instruction (normal or chained). the wss bit is automatically cleared when the married word is sent. performing either a scsi receive operation or any narrow transfer also clears the bit. in addition, scripts and the microprocessor can clear the wss bit as well as use it for error detection and recovery purposes. 2.2.18.2 wide scsi receive bit the wsr bit is set following a wide scsi receive operation (data-in for initiator mode or data-out for target mode) when the scsi core is holding a byte of chain data. the scsi core holds the byte when the
2-58 functional description controller detects a partial transfer at the end of a chained block move instruction. under this condition the high-order byte is not transferred out of the dma channel to memory. instead, it is stored in the scsi wide residue (swide) register and the wsr ?ag is set. the hardware uses the wsr bit to determine what behavior must occur at the start of the next data receive transfer. if set the stored high-order byte may be residual data, valid data for a subsequent data transfer, or overrun data. the byte may be read as normal by starting a data receive transfer. the wsr bit is automatically cleared at the start of the next data receive transfer. performing either a scsi send operation or any narrow transfer also clears the bit. in addition, scripts and the microprocessor can clear the wsr bit as well as use it for error detection and recovery purposes. 2.2.18.3 swide register for wide asynchronous receive data transfers, the scsi wide residue (swide) register holds the high-order byte of a partial scsi transfer which has not yet been transferred to memory. this stored data may be a residue byte (and therefore ignored) or it may be valid data that is transferred to memory at the beginning of the next block move instruction. 2.2.18.4 sodl register for wide asynchronous send data transfers, the low-order byte of the scsi output data latch (sodl) register holds the low-order byte of a partial memory transfer which has not yet been transferred across the scsi bus. this stored data is usually married with the ?rst byte of the next data send transfer, and both bytes are sent across the scsi bus at the start of the next data send block move instruction. 2.2.18.5 chained block move scripts instruction a chained block move scripts instruction is primarily used to transfer consecutive data send or data receive blocks. using the chained block move instruction facilitates partial receive transfers and allows correct partial send behavior without additional opcode overhead. behavior of the chained block move instruction varies slightly for sending and receiving data.
parallel rom interface 2-59 for receive data (data-in for the initiator or data-out for the target), a chained block move instruction indicates that if a partial transfer occurred at the end of the instruction the wsr ?ag is set. the high-order byte of the last scsi transfer is stored in the scsi wide residue (swide) register rather than transferred to memory. the stored byte should be the ?rst byte transferred to memory at the start of the chained block move or regular block move data stream. since the byte count always represents data transfers to/from memory (as opposed to/from the scsi bus), the stored byte transferred out is one of the bytes in the count. if the wsr bit is cleared when a receive data chained block move instruction is executed, the data transfer occurs similar to that of the regular block move instruction. it is recommended that all block move instructions be chained block moves. for send data (data-out for the initiator or data-in for the target), a chained block move instruction indicates that if a partial transfer terminates the chained block move the wss ?ag is set. the low-order byte should be stored in the lower byte of the scsi output data latch (sodl) register for asynchronous transfers or in the outbound chain byte holding register for synchronous transfers and not sent across the scsi bus. without the chained block move instruction, the last low-order byte would be sent across the scsi bus. the starting byte count represents data bytes transferred from memory but not to the scsi bus when a partial transfer exists. for example, if the instruction is an initiator chained block move data out of ?ve bytes (and wss is not previously set), ?ve bytes are transferred out of memory to the scsi controller. four bytes are transferred from the scsi controller across the scsi bus and one byte is temporarily stored as described above, waiting to be married with the ?rst byte of the next block move instruction. if the wss bit is set at the start of a data send command the ?rst byte of the transfer is assumed to be the high-order byte and is married with the stored byte (which will be the low-order byte) before the two bytes are sent across the scsi bus. it is recommended that all block move instructions be chained block moves. 2.3 parallel rom interface the lsi53c1010 supports up to 1 mbyte of external memory in binary increments from 16 kbytes to allow the use of expansion rom for add-in pci cards. both functions of the device share the rom interface.
2-60 functional description this interface is designed for low speed operations such as downloading instruction code from rom; it is not intended for dynamic activities such as executing instructions. system requirements include the lsi53c1010, two or three external 8-bit address holding registers (hct273 or hct374), and the appropriate memory device. the 4.7 k w pull-up resistors on the mad bus require hc or hct external components to be used. pull-up resistors on the 8-bit bidirectional memory bus at power-up determine the memory size and speed. the lsi53c1010 senses this bus shortly after the release of the reset signal and con?gures the expansion rom base address (erba) register and the memory cycle state machines for the appropriate conditions. the lsi53c1010 supports a variety of sizes and speeds of expansion rom. an example set of interface drawings is in appendix b, external memory interface diagram examples. the encoding of pins mad[3:1] allows the user to de?ne how much external memory is available to the lsi53c1010. table 2.8 shows the memory space associated with the possible values of mad[3:1]. the mad[3:1] pins are fully described in chapter 3, signal descriptions. to use one of the con?gurations mentioned above in a host adapter board design, put 4.7 k w pull-up resistors on the mad pins corresponding to the available memory space. each mad pin has an table 2.7 parallel rom support mad[3:1] available memory space 000 16 kbytes 001 32 kbytes 010 64 kbytes 011 128 kbytes 100 256 kbytes 101 512 kbytes 110 1024 kbytes 111 no external memory present, rom interface disabled
serial eeprom interface 2-61 internal static pull-down therefore no external pull-down resistors are needed. for example, to connect to a 64 kbytes external rom use a pull-up on mad[2]. if the external memory interface is not used, mad[3:1] should be pulled high. the lsi53c1010 allows the system to determine the size of the available external memory using the expansion rom base address (erba) register in the pci con?guration space. for more information on how this works, refer to the pci speci?cation or the expansion rom base address register description in chapter 4, registers. mad[0] is the slow rom pin. when pulled up it enables two extra clock cycles of data access time to allow use of slower memory devices. the external memory interface also supports updates to ?ash memory. 2.4 serial eeprom interface for each scsi function, the lsi53c1010 implements an interface permitting attachment of a serial eeprom device to the gpio[0] and gpio[1] pins. there are two modes of operation relating to the serial eeprom, the subsystem id (sid) register, and the subsystem vendor id (svid) register for each scsi function. these modes are programmable through the mad[7] pin, which is sampled at power-up. 2.4.1 default download mode in this mode, mad[7] is pulled down internally, gpio[0] is the serial data signal (sda) and gpio[1] is the serial clock signal (scl). certain data in the serial eeprom is automatically loaded into chip registers at power-up. the format of the serial eeprom data is de?ned in table 2.9 . if the download is enabled and an eeprom is not present or the checksum fails, the subsystem id (sid) and subsystem vendor id (svid) registers read back all zeros. at power-up, ?ve bytes are loaded into the chip from locations 0xfb through 0xff. the subsystem id and subsystem vendor id registers are read only in accordance with the pci speci?cation, with a default value of all zeros if the download fails.
2-62 functional description note: the speed of the serial eeprom must be 400 kbits/s. 2.4.2 no download mode when mad[7] is pulled up through an external resistor, the automatic download is disabled and data is not automatically loaded into chip registers at power-up. the subsystem id (sid) and subsystem vendor id (svid) registers are read only, per the pci speci?cation, with a default value of 0x1000 and 0x1000 respectively. 2.5 power management the lsi53c1010 complies with the pci bus power management interface speci?cation, revision 1.1. the pci function power states d0, d1, d2, and d3 are de?ned in that speci?cation. table 2.8 default download mode serial eeprom data format byte name description 0xfb svid(0) subsystem vendor id (svid) , lsb. this byte is loaded into the least signi?cant byte of the subsystem vendor id register in the appropriate pci con?guration space at chip power-up. 0xfc svid(1) subsystem vendor id (svid) , msb. this byte is loaded into the most signi?cant byte of the subsystem vendor id register in the appropriate pci con?guration space at chip power-up. 0xfd sid(0) subsystem id (sid) , lsb. this byte is loaded into the least signi?cant byte of the subsystem id register in the appropriate pci con?guration space at chip power-up. 0xfe sid(1) subsystem id (sid) , msb. this byte is loaded into the most signi?cant byte of the subsystem id register in the appropriate pci con?guration space at chip power-up. 0xff cksum checksum (cksum). this 8-bit checksum is formed by adding, bytewise, each byte contained in locations 0xfbC0xfe to the seed value (0x55) and then taking the 2s complement of the result.
power management 2-63 d0 is the maximum powered state, and d3 is the minimum powered state. power state d3 is further categorized as d3hot or d3cold. a function that is powered off is said to be in the d3cold power state. the lsi53c1010 power states are independently controlled through two power state bits that are located in the pci con?guration space power management control/status (pmcsr) register, 0x44C0x45 . the power state bit settings are provided in table 2.10 . although the pci bus power management interface speci?cation does not allow power state transitions d2 to d1, d3 to d2, or d3 to d1, the lsi53c1010 hardware places no restriction on transitions between power states. the pci function power states d0, d1, d2, and d3 are described below in conjunction with each scsi function. power state actions are separate for each function. as the device transitions from one power level to a lower one, the attributes that occur from the higher power state level are carried over into the lower power state level. for example, d1 disables the scsi clk. therefore, d2 will include this attribute as well as the attributes de?ned in the power state d2 section. the pci function power states d0, d1, d2, and d3 are described below in conjunction with each scsi function. power state actions are separate for each function. 2.5.1 power state d0 power state d0 is the maximum power state and is the power-up default state for each function. the lsi53c1010 is fully functional in this state. table 2.9 power states con?guration register (0x44), bits [1:0] power state function 00 d0 maximum power 01 d1 disables scsi clock 10 d2 coma mode 11 d3 minimum power
2-64 functional description 2.5.2 power state d1 power state d1 is a lower power state than d0. a function in this state places the lsi53c1010 core in the snooze mode and the scsi clock is disabled. in the snooze mode, a scsi reset does not generate an irq/ signal. 2.5.3 power state d2 power state d2 is a lower power state than d1. a function in this state places the lsi53c1010 core in the coma mode. the following pci con?guration space command register enable bits are suppressed: i/o space enable memory space enable bus mastering enable serr/enable enable parity error response thus, the function's memory and i/o spaces cannot be accessed, and the function cannot be a pci bus master. furthermore, scsi and dma interrupts are disabled when the function is in power state d2. if the function is changed from power state d2 to power state d1 or d0, the previous values of the pci command register are restored. also, any pending interrupts before the function entered power state d2 are asserted. 2.5.4 power state d3 power state d3 is the minimum power state, which includes settings called d3hot and d3cold. d3hot allows the device to transition to d0 using software. the lsi53c1010 is considered to be in power state d3cold when power is removed from the device. d3cold can transition to d0 by applying v cc and resetting the device. power state d3 is a lower power level than power state d2. a function in this state places the lsi53c1010 core in the coma mode. furthermore, the function's soft reset is continually asserted while in power state d3, which clears all pending interrupts and 3-states the scsi bus. in
power management 2-65 addition, the function's pci command register is cleared. if both of the lsi53c1010 functions are placed in power state d3, the clock quadrupler is disabled, which results in additional power savings.
2-66 functional description
LSI53C1010-33 pci to dual channel ultra160 scsi multifunction controller 3-1 chapter 3 signal descriptions this chapter describes the input and output signals of the LSI53C1010-33. the chapter consists of the following sections: section 3.1, signal organization section 3.2, internal pull-ups and pull-downs on lsi53c1010 signals section 3.3, pci bus interface signals section 3.4, scsi bus interface signals section 3.5, flash rom and memory interface signals section 3.6, test interface signals section 3.7, power and ground signals section 3.8, mad bus programming 3.1 signal organization the LSI53C1010-33 has four major interfaces: pci interface scsi bus interface memory interface test interface figure 3.1 illustrates the signals, their grouping, and their i/o direction. a slash (/) at the end of a signal name indicates that it is an active low signal. when the slash is absent, the signal is active at a high voltage.
3-2 signal descriptions the pci interface contains many functional groups of signals. the scsi bus interface contains two functional groups of signals as illustrated in figure 3.1 . pinout information and package drawings are available in section 6.6, package drawings. there are ?ve signal type de?nitions: this section of the chapter illustrates the signal groupings in figure 3.1 . i input, a standard input-only signal. o output, a standard output driver (typically a totem pole output). i/o input and output (bidirectional). t/s 3-state, a bidirectional, 3-state input/output signal. s/t/s sustained 3-state, an active low 3-state signal owned and driven by one and only one agent at a time.
signal organization 3-3 figure 3.1 LSI53C1010-33 functional signal grouping clk rst/ ad[63:0] c_be[7:0]/ pa r par64 ack64/ req64/ frame/ trdy/ irdy/ stop/ devsel/ idsel req/ gnt/ perr/ serr/ inta/ intb/ alt_inta/ alt_intb/ int_dir a_gpio0_fetch/ a_gpio1_master/ a_gpio2 a_gpio3 a_gpio4 b_gpio0_fetch/ b_gpio1_master/ b_gpio2 b_gpio3 b_gpio4 mwe/ mce/ moe/_testout mas0/ mas1/ mad[7:0] sclk a_sd[15:0]/ a_sdp[1:0]/ a_sc_d/ a_si_o/ a_smsg/ a_sreq/ a_sbsy/ a_satn/ a_srst/ a_ssel/ b_sdp[1:0]/ b_sc_d/ b_si_o/ b_smsg/ b_sreq/ b_sbsy/ b_satn/ b_srst/ b_ssel/ b_sd[15:0]/ test_rst/ test_hsc moe/_testout tck tms tdi tdo b_diffsens a_diffsens LSI53C1010-33 scsi function a scsi function b test interface scsi bus interface system address and data interface control arbitration error reporting interrupt scsi function a gpio scsi function b gpio flash rom and memory interface pci bus interface a_sctrl/ b_sctrl/ a_sack/ b_sack/ test_pd scan_mode
3-4 signal descriptions 3.2 internal pull-ups and pull-downs on lsi53c1010 signals several lsi53c1010 signals use internal pull-ups and pull-downs. table 3.1 describes the conditions that enable these pull-ups and pull-downs. table 3.1 lsi53c1010 internal pull-ups and pull-downs pin name pull-up current conditions for pull-up inta/, intb/, alt_inta/, alt_intb/ 25 m a pull-up enabled when the and-tree mode is enabled by driving test_rst/ low or when the irq mode bit (bit 3 of dcntl, 0x3b) is cleared. 1 int_dir, tck, tdi, test_rst/, tms 25 m a pulled up internally. ad[63:32], c_be[7:4]/, par64 25 m a pulled down internally. gpio[4:0] - 25 m a pulled up internally. mad[7:0] - 25 m a pulled down internally. test_hsc, test_pd, scan_mode - 25 m a pulled down internally. 1. when bit 3 of the dma control (dcntl) register is set, the pad becomes a totem pole output pad and drives both high and low.
pci bus interface signals 3-5 3.3 pci bus interface signals the pci bus interface signals section contains tables describing the signals for the following signal groups: system signals , address and data signals , interface control signals , arbitration signals , error reporting signals , interrupt signals , scsi function a gpio signals , and scsi function b gpio signals . 3.3.1 system signals table 3.2 describes the system signals group. table 3.2 system signals name bump type strength description clk h3 i n/a clock provides timing for all transactions on the pci bus and is an input to every pci device. all other pci signals are sampled on the rising edge of clk. other timing parameters are de?ned with respect to this edge. rst/ g1 i n/a reset forces the pci sequencer of each device to a known state. all t/s and s/t/s signals are forced to a high impedance state, and all internal logic is reset. the rst/ input is synchronized internally to the rising edge of clk. to properly reset the device, the clk input must be active while rst/ is active.
3-6 signal descriptions 3.3.2 address and data signals table 3.3 describes the address and data signals group. table 3.3 address and data signals name bump type strength description ad[63:0] y5, ab5, ac5, aa6, y6, ab6, ac6, aa7, ab7, ac7, aa8, y8, ab8, ac8, aa9, y9, ab9, ac9, aa10, y11, ab10, ac10, aa11, ac11, ab11, ac12, aa12, ab12, ab13, ac13, aa13, ac14, h1, j3, j4, j2, j1, k3, l4, k2, l1, l2, m1, m3, m2, n2, n1, n3, t4, t3, u1C u3, v1, v2, v4, w1, w2, w4, w3, y1, y2, aa1, y3. t/s 8 ma pci physical longword address and data are multiplexed on the same pci pins. a bus transaction consists of an address phase followed by one or more data phases. during the ?rst clock of a transaction, ad[63:0] contain a 64-bit physical byte address. if the command is a dual address cycle (dac), implying a 64-bit address, ad[31:0] will contain the upper 32 bits of the address during the second clock of the transaction. during subsequent clocks, ad[63:0] will contain data. pci supports both read and write bursts. ad[7:0] de?ne the least signi?cant byte, and ad[63:56] de?ne the most signi?cant byte. c_be[7:0]/ aa4, ac3, ab4, ac4, k1, p1, t2, v3. t/s 8 ma pci bus command and byte enables are multiplexed on the same pci pins. during the address phase of a transaction, c_be[3:0]/ de?ne the bus command. if the transaction is a dac, c_be[3:0]/ contain the dac command and c_be[7:4]/ de?ne the bus command. c_be[3:0]/ de?ne the bus command during the second clock of the transaction. during the data phase, c_be[7:0]/ are used as byte enables. the byte enables determine which byte lanes carry meaningful data: c_be[0]/ applies to byte 0, and c_be[7]/ to byte 7. par t1 t/s 8 ma pci parity is the even parity bit that protects the ad[31:0] and c_be[3:0]/ lines. during the address phase, both the address and command bits are covered. during the data phase, both the data and byte enables are covered.
pci bus interface signals 3-7 3.3.3 interface control signals table 3.4 describes the interface control signals group. par64 aa5 t/s 8 ma pci parity64 is the even parity bit that protects the ad[63:32] and c_be[7:4]/ lines. during the address phase, the address and command bits are covered. during the data phase, both the data and byte enables are covered. table 3.3 address and data signals (cont.) name bump type strength description table 3.4 interface control signals name bump type strength description ack64/ ab1 s/t/s 8 ma pci acknowledge 64 -bit transfer is driven by the current bus target to indicate its ability to transfer 64-bit data. req64/ aa2 s/t/s 8 ma pci request 64 -bit transfer is driven by the current bus master to indicate a request to transfer 64-bit data. frame/ p2 s/t/s 8 ma pci cycle frame is driven by the current master to indicate the beginning and duration of an access. frame/ is asserted to indicate that a bus transaction is beginning. while frame/ is deasserted, either the transaction is in the ?nal data phase or the bus is idle. trdy/ p3 s/t/s 8 ma pci target ready indicates the targets ability to complete the current data phase of the transaction. trdy/ is used with irdy/. a data phase is completed on any clock when both trdy/ and irdy/ are sampled asserted. during a read, trdy/ indicates that valid data is present on the ad bus. during a write, it indicates that the target is prepared to accept data. irdy/ n4 s/t/s 8 ma pci initiator ready indicates the initiators ability to complete the current data phase of the transaction. irdy/ is used with trdy/. a data phase is completed on any clock when both irdy/ and trdy/ are sampled asserted. during a write, irdy/ indicates that valid data is present on the ad bus. during a read, it indicates that the master is prepared to accept data.
3-8 signal descriptions 3.3.4 arbitration signals table 3.5 describes the arbitration signals group. stop/ r2 s/t/s 8 ma pci stop indicates that the selected target is requesting the master to stop the current transaction. devsel/ r1 s/t/s 8 ma pci device select indicates that the driving device has decoded its address as the target of the current access. as an input, it indicates to a master whether any device on the bus has been selected. idsel l3 i n/a initialization device select is used as a chip select, in place of the upper 24 address lines, during con?guration read and write transactions. table 3.4 interface control signals (cont.) name bump type strength description table 3.5 arbitration signals name bump type strength description req/ h2 o 8 ma pci request indicates to the system arbiter that this agent requests use of the pci bus. this is a point-to-point signal. every master has its own req/ signal. gnt/ h4 i n/a grant indicates to a speci?c agent that access to the pci bus has been granted. this is a point-to-point signal. every master has its own gnt/ signal.
pci bus interface signals 3-9 3.3.5 error reporting signals table 3.6 describes the error reporting signals group. 3.3.6 interrupt signals table 3.7 describes the interrupt signals group. table 3.6 error reporting signals name bump type strength description perr/ r4 s/t/s 8 ma pci parity error may be pulsed active by an agent that detects a data parity error. perr/ can be used by any agent to signal data corruption. on detection of a perr/ pulse, a nonmaskable interrupt is generated to the host cpu, which often implies the system is unable to continue operation once error processing is complete. serr/ r3 o 8 ma pci system error is an open drain output used to report address parity errors as well as critical errors other than parity. table 3.7 interrupt signals name 1 bump type strength description inta/ f4 o 8 ma pci interrupt function a. this signal, when asserted low, indicates that an interrupting condition in scsi function a requires service from the host cpu. the output drive of this pin is open drain. see scsi test one (stest1) for additional information about disabling this interrupt in a raid environment. this interrupt pin is disabled if int_dir is driven low. if the scsi function b interrupt is rerouted at power-up using the inta/ enable sense resistor (pull-up on mad4), this signal indicates that an interrupting condition has occurred in either scsi function a or scsi function b.
3-10 signal descriptions intb/ f2 o 8 ma pci interrupt function b. this signal, when asserted low, indicates that an interrupting condition in scsi function b requires service from the host cpu. the output drive of this pin is open drain. see scsi test one (stest1) for additional information about disabling this interrupt in a raid environment. this interrupt pin is disabled if int_dir is driven low. at power-up, this interrupt can be rerouted to inta/ using the inta/ enable sense resistor (pull-up on mad4). this causes the lsi53c1010 to program the scsi function b pci interrupt pin (ip) register to 0x01. alt_inta/ f1 o 8 ma pci alt interrupt function a. this signal, when asserted low, indicates that an interrupting condition in scsi function a requires service. the output drive of this pin is open drain. see scsi test one (stest1) for additional information about disabling this interrupt in a raid environment. if the scsi function b interrupt is rerouted at power-up using the inta/ enable sense resistor (pull-up on mad4), this signal indicates that an interrupting condition has occurred in either scsi function a or scsi function b. alt_intb/ g3 o 8 ma pci alt interrupt function b. this signal, when asserted low, indicates that an interrupting condition in scsi function b requires service. the output drive of this pin is open drain. see scsi test one (stest1) for additional information about disabling this interrupt in a raid environment. at power-up, this interrupt can be rerouted to inta/ using the inta/ enable sense resistor (pull-up on mad4). this causes the lsi53c1010 to program the scsi function b pci interrupt pin (ip) register to 0x01. table 3.7 interrupt signals (cont.) name 1 bump type strength description
pci bus interface signals 3-11 3.3.7 scsi function a gpio signals table 3.8 describes the scsi function a gpio signals group. int_dir g2 i n/a interrupt direction. this input signal indicates whether internally generated interrupts are presented on inta/ and intb/. if int_dir is high, internal interrupts are generated on both the intx/ pins and the alt_intx pin. if int_dir is low, the internal interrupts are generated only on the alt_intx/ pin. this pin has no effect if either bit 0 or 1 in stest1 is set. this pin has a static pull-up. 1. see register 0x4d, scsi test one (stest1) in chapter 4, registers, for additional information on these signals. table 3.7 interrupt signals (cont.) name 1 bump type strength description table 3.8 scsi function a gpio signals name bump type strength description a_gpio0_ fetch/ ab16 i/o 8 ma scsi function a general purpose i/o pin 0. this pin is programmable at power-up, through the mad7 pin, to serve as the data signal for the serial eeprom interface. when gpio_0 is not in the process of downloading eeprom data it can be used to drive a scsi activity led, if bit 5 in the general purpose pin control (gpcntl) register is set. or, it can be used to indicate that the next bus request will be an opcode fetch if bit 6 in the gpcntl register is set. a_gpio1_ master/ y16 i/o 8 ma scsi function a general purpose i/o pin 1. this pin is programmable at power-up, through the mad7 pin, to serve as the clock signal for the serial eeprom interface. if bit 7 of the general purpose pin control (gpcntl) register is set, this pin drives low when the lsi53c1010 is the bus master. a_gpio2 aa16 i/o 8 ma scsi function a general purpose i/o pin 2. this pin powers up as an input. a_gpio3 ac17 i/o 8 ma scsi function a general purpose i/o pin 3. this pin powers up as an input. a_gpio4 ab17 i/o 8 ma scsi function a general purpose i/o pin 4. this pin powers up as an output. it can be used as the enable line for v pp , the 12 v power supply to the external ?ash memory interface.
3-12 signal descriptions 3.3.8 scsi function b gpio signals table 3.9 describes the scsi function b gpio signals group. table 3.9 scsi function b gpio signals name bump type strength description b_gpio0_ fetch/ aa14 i/o 8 ma scsi function b general purpose i/o pin 0. this pin is programmable at power-up through the mad7 pin to serve as the data signal for the serial eeprom interface. when gpio_0 is not in the process of downloading eeprom data, it can be used to drive a scsi activity led if bit 5 in the general purpose pin control (gpcntl) register is set. or, it can be used to indicate that the next bus request will be an opcode fetch if bit 6 in the gpcntl register is set. b_gpio1_ master/ ac15 i/o 8 ma scsi function b general purpose i/o pin 1. this pin is programmable at power-up through the mad7 pin to serve as the clock signal for the serial eeprom interface. if bit 7 of the general purpose pin control (gpcntl) register is set, this pin is driven low when the lsi53c1010 is the bus master. b_gpio2 ab15 i/o 8 ma scsi function b general purpose i/o pin 2. this pin powers up as an input. b_gpio3 aa15 i/o 8 ma scsi function b general purpose i/o pin 3. this pin powers up as an input. b_gpio4 ac16 i/o 8 ma scsi function b general purpose i/o pin 4. this pin powers up as an output. it can be used as the enable line for v pp , the 12 v power supply to the external ?ash memory interface.
scsi bus interface signals 3-13 3.4 scsi bus interface signals the scsi bus interface signals section contains tables describing the signals for the following signal groups: scsi bus interface signals , scsi function a signals , and scsi function b signals . scsi function a signals and scsi function b signals each have a subgroup: the scsi function a control signals and the scsi function b control signals . table 3.10 contains signals that are common to both scsi buses. 3.4.1 scsi function a signals this section describes the signals for the scsi function a signals group. it is divided into two tables: table 3.11 describes scsi function a signals and table 3.12 describes scsi function a control signals. table 3.10 scsi bus interface signals name bump type strength description sclk a21 i n/a scsi clock is used to derive all scsi related timings. the speed of this clock must be 40 mhz. the clock frequency can be quadrupled to create the 160 mhz clock required internally by both scsi functions. table 3.11 scsi function a signals name bump type strength description a_sd[15:0] - b5, c5, b4, c4, d19, a19, d18, a18, d11, a9, d9, a8, d8, a7, c7, b6. i/o se: 48 ma scsi lvd: 12 ma unilvd scsi function a data. lvd mode: negative half of the lvdlink pair for the scsi data lines. a_sd[15:0] - form the 16-bit scsi data bus. se mode: a_sd[15:0] - form the 16-bit scsi data bus. a_sd[15:0]+ a5, d5, a4, a3, c19, b19, c18, b18, b10, c10, b9, c9, b8, c8, b7, a6. i/o se: 48 ma scsi lvd: 12 ma unilvd scsi function a data. lvd mode: positive half of the lvdlink pair for the scsi data lines. a_sd[15:0]+ form the 16-bit data bus. se mode: a_sd[15:0]+ are at 0 v.
3-14 signal descriptions a_sdp[1:0] - c6, a10. i/o se: 48 ma scsi lvd: 12 ma unilvd scsi function a parity. lvd mode: negative half of the lvdlink pair for the scsi parity lines. a_sdp[1:0] - are the scsi data parity lines. se mode: a_sdp[1:0] - are the scsi data parity lines. a_sdp[1:0]+ d6, c11. i/o se: 48 ma scsi lvd: 12 ma unilvd scsi function a parity. lvd mode: positive half of the lvdlink pair for the scsi parity lines. a_sdp[1:0]+ are the scsi data parity lines. se mode: a_sdp[1:0]+ are at 0 v. a_diffsens a20 i n/a scsi function a differential sense pin detects the present mode of the scsi bus when connected to the diffsens signal on the physical scsi bus. lvd mode: if a voltage between 0.7 v and 1.9 v is present, scsi function a operates in the lvd mode. se mode: when this pin is driven low (below 0.5 v), se operation is indicated. scsi function a operates in the se mode. hvd mode: when this pin is detected high (above 2.0 v), hvd operation is indicated. scsi function a is driven to the high impedance state. this pin is 5 v tolerant. hvd mode is not supported. table 3.11 scsi function a signals (cont.) name bump type strength description
scsi bus interface signals 3-15 table 3.12 scsi function a control signals name 1 1. lvd mode: negative and positive halves of the lvdlink signal pairs are shown for scsi function a control. se mode: the scsi function a control signals are shown. all the positive (+) signals are at 0 volts. bump type strength description scsi function a control includes the following signals: a_sc_d - a_sc_d+ a_si_o - a_si_o+ a_smsg - a_smsg+ a_sreq - a_sreq+ a_sack - a_sack+ a_sbsy - a_sbsy+ a_satn - a_satn+ a_srst - a_srst+ a_ssel - a_ssel+ c15 a16 b17 c17 c14 a15 c16 a17 c13 a14 c12 a12 b11 b12 b14 d13 b15 d15 i/o se: 48 ma scsi lvd: 12 ma unilvd scsi phase line, command/data. scsi phase line, input/output. scsi phase line, message. data handshake line from target device. data handshake signal from the initiator device. scsi bus arbitration signal, busy. scsi attention, the initiator is requesting a message out phase. scsi bus reset. scsi bus arbitration signal, select device.
3-16 signal descriptions 3.4.2 scsi function b signals this section describes the scsi function b signals group. it is divided into two tables: table 3.13 describes scsi function b signals and table 3.14 describes scsi function b control signals. table 3.13 scsi function b signals name bump type strength description b_sd[15:0] - f21, e22, e21, d22, y22, w21, w22, v21, k23, l20, j23, j20, h23, h20, g23, g21. i/o se: 48 ma scsi lvd: 12 ma unilvd scsi function b data. lvd mode: negative half of the lvdlink pair for the scsi data lines. b_sd[15:0] - form the 16-bit scsi data bus. se mode: b_sd[15:0] - form the 16-bit scsi data bus. b_sd[15:0]+ f20, e23, e20, d23, aa23, y23, w20, w23, l21, k22, k21, j22, j21, h22, h21, g22. i/o se: 48 ma scsi lvd: 12 ma unilvd scsi function b data. lvd mode: positive half of the lvdlink pair for the scsi data lines. b_sd[15:0]+ form the 16-bit data bus. se mode: b_sd[15:0]+ are at 0 v. b_sdp[1:0] - f22, l23. i/o se: 48 ma scsi lvd: 12 ma unilvd scsi function b parity. lvd mode: negative half of the lvdlink pair for the scsi parity lines. b_sdp[1:0] - are the scsi data parity lines. se mode: b_sdp[1:0] - are the scsi data parity lines.
scsi bus interface signals 3-17 b_sdp[1:0]+ f23, l22. i/o se: 48 ma scsi lvd: 12 ma unilvd scsi function b parity. lvd mode: positive half of the lvdlink pair for the scsi parity lines. b_sdp[1:0]+ are the scsi data parity lines. se mode: b_sdp[1:0]+ are at 0 v. b_diffsens y21 i n/a scsi function b differential sense pin detects the present mode of the scsi bus when connected to the diffsens signal on the physical scsi bus. lvd mode: if a voltage between 0.7 v and 1.9 v is present, scsi function b operates in the lvd mode. se mode: if a voltage below 0.5 v is present, se operation is indicated. scsi function b operates in the se mode. hvd mode: when this pin is detected high (above 2.0 v) hvd operation is indicated. scsi function b is driven to the high impedance state. this pin is 5 v tolerant. hvd mode is not supported. table 3.13 scsi function b signals (cont.) name bump type strength description
3-18 signal descriptions table 3.14 scsi function b control signals name 1 bump type strength description scsi function b control includes the following signals: b_sc_d - b_sd_d+ b_si_o - b_si_o+ b_smsg - b_smsg+ b_sreq - b_sreq+ b_sack - b_sack+ b_sbsy - b_sbsy+ b_satn - b_satn+ b_srst - b_srst+ b_ssel - b_ssel+ t20 t21 v22 v20 r20 r21 u21 v23 n20 p21 n23 n21 m23 n22 r23 r22 t23 t22 i/o se: 48 ma scsi lvd: 12 ma unilvd scsi phase line, command/data. scsi phase line, input/output. scsi phase line, message. data handshake line from target device. data handshake signal from the initiator device. scsi bus arbitration signal, busy. scsi attention, the initiator is requesting a message out phase. scsi bus reset. scsi bus arbitration signal, select device. 1. lvd mode: negative and positive halves of the lvdlink signal pairs are shown for the scsi function b control. se mode: the scsi function b control signals are shown. all the positive (+) signals are at 0 volts.
flash rom and memory interface signals 3-19 3.5 flash rom and memory interface signals table 3.15 describes the signals for the flash rom and memory interface signals group. table 3.15 flash rom and memory interface signals name bump type strength description mwe/ ac19 o 4 ma memory write enable. this pin is used as a write enable signal to an external ?ash memory. mce/ aa18 o 4 ma memory chip enable. this pin is used as a chip enable signal to an external eprom or ?ash memory device. moe/_ testout y18 o 4 ma memory output enable. this pin is used as an output enable signal to an external eprom or ?ash memory during read operations. it is also used to test the connectivity of the lsi53c1010 signals in the and-tree test mode. mas0/ ac18 o 4 ma memory address strobe 0 . this pin is used to latch in the least signi?cant address byte (bits [7:0]) of an external eprom or ?ash memory. since the lsi53c1010 moves addresses eight bits at a time, this pin connects to the clock of an external bank of ?ip-?ops that assemble up to a 20-bit address for the external memory. mas1/ aa17 o 4 ma memory address strobe 1. this pin is used to latch in the most signi?cant address byte (bits [15:8]) of an external eprom or ?ash memory. since the lsi53c1010 moves addresses eight bits at a time, this pin connects to the clock of an external bank of ?ip-?ops that assemble up to a 20-bit address for the external memory. mad[7:0] y19, aa19, ac20, ab20, aa20, ac22, ab21, ac23. i/o 4 ma memory address/data bus. this bus is used in conjunction with the memory address strobe pins and external address latches to assemble up to a 20-bit address for an external eprom or ?ash memory. this bus ?rst issues the least signi?cant byte and ?nishes with the most signi?cant bits. it is also used to write data to a ?ash memory or read data into the chip from external eprom/?ash memory. these pins have static pull-downs.
3-20 signal descriptions 3.6 test interface signals table 3.16 describes the test interface signals group. table 3.16 is divided into internal test signals and jtag signals. table 3.16 test interface signals name bump type strength description internal test signals: scan_mode c22 i n/a scan mode . for lsi logic test purposes only. this pin has a static pull-down. test_hsc c23 i n/a test halt scsi clock. for lsi logic test purposes only. pulled low internally. this signal can also cause a full chip reset. test_pd a2 i n/a test power down. for lsi logic test purposes only. this pin has a static pull-down. test_rst/ c1 i n/a test reset. for lsi logic test purposes only. pulled high internally. moe/_ testout y18 o 4 ma memory output enable. this pin is used as an output enable signal to an external eprom or ?ash memory during read operations. it is also used to test the connectivity of the lsi53c1010 signals in the and-tree test mode. jtag signals: tck d1 i n/a test clock. this pin provides the clock for the jtag test logic. this pin has a static pull-up. tms e3 i n/a test mode select (tms) . the signal received at tms is decoded by the test access port (tap) controller to control jtag test operations. this pin has a static pull-up. tdi e2 i n/a test data in. this pin receives the serial test instructions for the jtag test logic. this pin has a static pull-up. tdo e1 o 4 ma test data out. this pin is the serial output for test instructions and data from the jtag test logic. reserved ab14 reserved. not used.
power and ground signals 3-21 3.7 power and ground signals table 3.17 describes the power and ground signals group. table 3.17 power and ground signals name 1 bump type strength description v ss_io c3, c21, d4, d12, d20, k10C14, l10C14, m4, m10C14, m20, n10C14, p10C14, y4, y12, y20, aa3, aa21. g n/a ground for pci bus drivers/receivers, scsi bus drivers, local memory interface drivers, and other i/o pins. v dd_io d7, d10, d14, d17, g4, g20, k4, k20, p4, p20, u4, u20, y7, y10, y14, y17. p n/a power for pci bus drivers/receivers, scsi bus drivers/receivers, local memory interface drivers/receivers, and other i/o pins. v dd _core b22, b23, d3, e4, y13, ab3, ab18, ab23, ac1. p n/a power for core logic. v ss _core a22, d2, d21, f3, y15, ab2, aa22, ab19, ac2, ac21. g n/a ground for core logic. v dd _a 2 b2, c20 p n/a power for analog cells (clock quadrupler and diffsens logic). v ss _a 2 b20, c2 g n/a ground for analog cells (clock quadrupler and diffsens logic). v dd _bias m22 p n/a power for scsi function a rbias circuit. v dd _bias2 a11 p n/a power for scsi function b rbias circuit. rbias m21 i n/a used to connect an external resistor to generate the lvdlink pad bias current. the resistor value should be 10 k w . connect the other end of the resistor to v dd . nc a1, a13, a23, b1, b3, b13, b16, b21, d16, p22, p23, u22, u23, ab22. n/a n/a these pins are reserved or have no internal connection. 1. the i/o driver pad rows and digital core have isolated power supplies as indicated by the i/o and core extensions on their respective v ss and v dd names. connect the power and ground pins directly to the primary power and ground planes of the circuit board. apply bypass capacitors of 0.01 m f between adjacent v ss and v dd pairs wherever possible. do not connect bypass capacitors between v ss and v dd pairs that cross power and ground bus boundaries. 2. to reduce signal noise that can affect frequency synthesizer (fsn) functionality, place a ferrite bead in series with the v dd -a and v ss -a pins. the recommended rating of the bead is 150 ohms at 100 mhz.
3-22 signal descriptions 3.8 mad bus programming the mad[7:0] pins, in addition to serving as the address/data bus for the local memory interface, also are used to program power-up options for the chip. a particular option is programmed allowing the internal pull-down current sink to pull the pin low at reset or by connecting a 4.7 k w resistor between the appropriate mad[x] pin and v dd . the pull-down resistors require that hc or hct external components are used for the memory interface. a description of the mad bus pins follows: mad[7] serial eeprom programmable option C when pulled low by the internal pull-down current sink, the automatic data download is enabled. when pulled high by an external resistor, the automatic data download is disabled. see section 2.4, serial eeprom interface, and the subsystem id (sid) and subsystem vendor id (svid) register descriptions. mad[6] C reserved. mad[5] C reserved. mad[4] inta/ routing enable C placing a pull-up resistor on this pin causes scsi function b interrupt requests to appear on the inta/ pin, along with scsi function a interrupt requests, instead of on intb/. placing a pull-up resistor on this pin also programs the scsi function b interrupt pin (ip) register in pci con?guration space to 0x01 instead of 0x02. placing no resistor on this pin causes scsi function b interrupt requests to appear on the intb/ pin and programs the scsi function b interrupt pin (ip) register in pci con?guration space to 0x02.
mad bus programming 3-23 mad[3:1] C these pins set the size of the external expansion rom device attached. the encoding for these pins is listed in table 3.18 . a 0 indicates a pull-down resistor is attached while a 1 indicates a pull-up resistor attached. mad[0] slow rom C when pulled up, it enables use of slower memory devices by including two extra data access cycles. note: all mad pins have internal pull-down resistors. table 3.18 mad[3:1] pin decoding mad[3:1] available memory space 000 16 kbytes 001 32 kbytes 010 64 kbytes 011 128 kbytes 100 256 kbytes 101 512 kbytes 110 1024 kbytes 111 no external memory present
3-24 signal descriptions
LSI53C1010-33 pci to dual channel ultra160 scsi multifunction controller 4-1 chapter 4 registers this section contains descriptions of all LSI53C1010-33 registers. the term set refers to bits programmed to a binary one. similarly, the term cleared refers to bits programmed to a binary zero. do not access reserved bits. reserved bit functions may change at any time. unless otherwise indicated, all bits in the registers are active high; the feature is enabled by setting the bit. the bottom row of every register diagram presents the default register values, which are enabled after the chip is powered on or reset. this chapter contains the following sections: section 4.1, pci con?guration registers section 4.2, scsi registers section 4.3, scsi shadow registers 4.1 pci con?guration registers to access the pci con?guration registers, perform a con?guration read or write to a device with its idsel pin asserted. the appropriate address value is in ad[10:8] during the address phase of the transaction. scsi function a is identi?ed by a binary value of 0b000, and scsi function b by a value of 0b001. each scsi function contains the same register set with identical default values, except the interrupt pin (ip) register. table 4.1 shows the pci con?guration registers implemented in the lsi53c1010. all pci-compliant devices, such as the lsi53c1010, support vendor id , device id , command , and status registers. support of other pci-compliant registers is optional. in the lsi53c1010, registers that are
4-2 registers not supported are not writable and return all zeros when read. only those registers and bits that are currently supported by the lsi53c1010 are described in this chapter. do not access bits marked as reserved. table 4.1 pci con?guration register map 31 16 15 0 address page device id vendor id 0x00 4-3 status command 0x04 4-3 class code (cc) revision id (rid) 0x08 4-7 reserved header type (ht) latency timer (lt) cache line size (cls) 0x0c 4-7 base address register zero (bar0) (i/o) 0x10 4-9 base address register one (bar1) (memory) bits [31:0] 0x14 4-10 base address register two (bar2) (memory) bits [31:0] 0x18 4-10 base address register three (bar3) (scripts ram) bits [31:0] 0x1c 4-11 base address register four (bar4) (scripts ram) bits [31:0] 0x20 4-11 reserved 0x24 4-12 reserved 0x28 4-12 subsystem id (sid) subsystem vendor id (svid) 0x2c 4-12 expansion rom base address (erba) 0x30 4-14 reserved capabilities pointer (cp) 0x34 4-15 reserved 0x38 4-15 max_lat (ml) min_gnt (mg) interrupt pin (ip) interrupt line (il) 0x3c 4-16 power management capabilities (pmc) next item pointer (nip) capability id (cid) 0x40 4-18 data bridge support exten- sions (pmcsr_bse) power management control/status (pmcsr) 0x44 4-20
pci con?guration registers 4-3 registers: 0x00C0x01 vendor id read only vid vendor id [15:0] this 16-bit register identi?es the manufacturer of the device. the vendor id is 0x1000. registers: 0x02C0x03 device id read only did device id [15:0] this 16-bit register identi?es the particular device. the LSI53C1010-33 device id is 0x0020. registers: 0x04C0x05 command read/write the scsi command register provides coarse control over a devices ability to generate and respond to pci cycles. when a zero is written to this register, the lsi53c1010 is logically disconnected from the pci bus for all accesses except con?guration accesses. 15 0 vid 0001000000000000 15 0 did 0000000000100000 15 987 6 543 2 1 0 rse r eper r wie r ebm ems eis 0 0 0 0 0 0 00 00 00 00 00
4-4 registers r reserved [15:9] se serr/ enable 8 when this bit is set, the lsi53c1010 enables the serr/ driver. serr/ is disabled when this bit is cleared. the default value of this bit is zero. this bit and bit 6 must be set to report address parity errors. r reserved 7 eper enable parity error response 6 when this bit is set, the lsi53c1010 detects parity errors on the pci bus and reports these errors to the system. only data parity checking is affected with this bit. the lsi53c1010 always generates parity for the pci bus. r reserved 5 wie write and invalidate enable 4 when this bit is set, the lsi53c1010 can generate write and invalidate commands on the pci bus. the wrie bit in the chip test three (ctest3) register must also be set for the device to generate write and invalidate commands. r reserved 3 ebm enable bus mastering 2 this bit controls the ability of the lsi53c1010 to act as a master on the pci bus. a value of zero disables this device from generating pci bus master accesses. a value of one allows the lsi53c1010 to behave as a bus master. the device must be a bus master to fetch scripts instructions and transfer data. ems enable memory space 1 this bit controls the ability of the lsi53c1010 to respond to memory space accesses. a value of zero disables the device response. a value of one allows the lsi53c1010 to respond to memory space accesses at the address range speci?ed by the base address register one (bar1) (memory) , base address register two (bar2) (memory) , base address register three (bar3) (scripts ram) , and the base address register four (bar4) (scripts ram) registers in the pci con?guration space.
pci con?guration registers 4-5 eis enable i/o space 0 this bit controls the lsi53c1010 response to i/o space accesses. clearing this bit disables the device response. setting this bit allows the lsi53c1010 to respond to i/o space accesses at the address range speci?ed by the base address register zero (bar0) (i/o) register in the pci con?guration space. registers: 0x06C0x07 status read/write reads to this register behave normally. writes are slightly different in that bits can be cleared, but not set. a bit is cleared whenever the register is written, and the data in the corresponding bit location is a one. for example, to clear bit 15 and not affect any other bits, write the value 0x8000 to the register. dpe detected parity error (from slave) 15 this bit is set by the lsi53c1010 upon the detection of a data parity error, even if data parity error handling is disabled. sse signaled system error 14 this bit is set whenever the device asserts the serr/ signal. rma received master abort (from master) 13 a master device should set this bit when its transaction (except for special cycle) is terminated with master abort. rta received target abort (from master) 12 a master device should set this bit whenever its transaction is terminated by target abort. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 dpe sse rma rta r dt[1:0] dpr fbbc r 66c nc r 0000 0000 0 001 0 0 0 0
4-6 registers r reserved 11 dt[1:0] devsel/ timing [10:9] these bits encode the timing of devsel/. the timings are encoded as: these bits are read only and indicate the slowest time that a device asserts devsel/ for any bus command except con?guration read and con?guration write. the lsi53c1010 supports a value of 0b01. dpr data parity error reported 8 this bit is set when the following conditions are met: the bus agent asserts perr/ itself or observes perr/ asserted and; the agent setting this bit acted as the bus master for the errant operation and; the parity error response bit in the command register is set. fbbc fast back-to-back capable 7 this bit is zero. r reserved 6 66c reserved 5 this bit is always set to zero. nc new capabilities 4 this bit is set to indicate a list of extended capabilities such as pci power management. this bit is read only. r reserved [3:0] 0b00 fast 0b01 medium 0b10 slow 0b11 reserved
pci con?guration registers 4-7 register: 0x08 revision id (rid) read only rid revision id [7:0] this register indicates the current revision level of the device. registers: 0x09C0x0b class code (cc) read only cc class code [23:0] this 24-bit register identi?es the generic function of the device. the upper byte of this register is a base class code, the middle byte is a subclass code, and the lower byte identi?es a speci?c register-level programming interface. the value of this register is 0x010000, which identi?es a scsi controller. register: 0x0c cache line size (cls) read/write cls cache line size [7:0] this register speci?es the system cache line size in units of 32-bit words. the value in this register is used by the device to determine whether to use write and invalidate or write commands for performing write cycles, and whether to use read, read line, or read multiple 7 0 rid xxxxxxxx 23 0 cc 000000010000000000000000 7 0 cls 00000000
4-8 registers commands for performing read cycles as a bus master. devices participating in the caching protocol use this ?eld to determine when to retry burst accesses at cache line boundaries. these devices can ignore the pci cache support lines (sdone and sb0/) if this register is set to 0. if this register is programmed to a number which is not a power of 2, the device does not use pci performance commands to execute data transfers. register: 0x0d latency timer (lt) read/write lt latency timer [7:0] the latency timer register speci?es, in units of pci bus clocks, the value of the latency timer for this pci bus master. the scsi functions of the lsi53c1010 support this timer. all eight bits are writable, allowing latency values of 0C255 pci clocks. use the following equation to calculate an optimum latency value for the scsi functions of the lsi53c1010. latency = 2 + (burst size * (typical wait states + 1)) values greater than optimum are also acceptable. 7 0 lt 00000000
pci con?guration registers 4-9 register: 0x0e header type (ht) read only ht header type [7:0] this 8-bit register identi?es the layout of bytes 0x10 through 0x3f in con?guration space and also whether or not the device contains multiple functions. since the lsi53c1010 is a multifunction controller the value of this register is 0x80. register: 0x0f reserved this register is reserved. registers: 0x10C0x13 base address register zero (bar0) (i/o) read/write bar0 base address register zero - i/o [31:0] this base address register is used to map the operating register set into i/o space. the lsi53c1010 requires 256 bytes of i/o space for this base address register. bit 0 is hardwired to one. bit 1 is reserved and returns a zero on all reads. all other bits are used to map the device into i/o space. for detailed information on the operation of this register, refer to the pci 2.2 speci?cation. 7 0 ht 10000000 7 0 r 0 0 0 0 0 0 0 0 31 0 bar0 00000000000000000000000000000001
4-10 registers registers: 0x14C0x17 base address register one (bar1) (memory) read/write bar1 base address register one [31:0] this base address register, in conjunction with base address register two (bar2) (memory) , maps scsi operating registers into memory space and represents the lower 32 bits of the memory address. bits [9:0] are hardwired to 0b0000000100. the default value of this register is 0x00000004. the lsi53c1010 requires 1024 bytes of memory space. for detailed information on the operation of this register, refer to the pci 2.2 speci?cation. registers: 0x18C0x1b base address register two (bar2) (memory) read/write bar2 base address register two [31:0] this base address register, in conjunction with base address register one (bar1) (memory) , maps scsi operating registers into memory space and represents the upper 32 bits of the memory address. the default value of this register is 0x00000000. the lsi53c1010 requires 1024 bytes of memory space. for detailed information on the operation of this register, refer to the pci 2.2 speci?cation. 31 0 bar1 00000000000000000000000000000100 31 0 bar2 00000000000000000000000000000000
pci con?guration registers 4-11 registers: 0x1cC0x1f base address register three (bar3) (scripts ram) read/write bar3 base address register three [31:0] this base address register, in conjunction with base address register four (bar4) (scripts ram) , is used to map the scripts ram into memory space and represents the lower 32 bits of the memory address. bits [12:0] are hardwired to 0b0000000000100. the default value of this register is 0x00000004. the lsi53c1010 requires 8192 bytes of memory space for scripts ram. for detailed information on the operation of this register, refer to the pci 2.2 speci?cation. registers: 0x20C0x23 base address register four (bar4) (scripts ram) read/write bar4 base address register four [31:0] this base address register, in conjunction with base address register three (bar3) (scripts ram) ,is used to map the scripts ram into memory space and represents the upper 32 bits of the memory address. the default value of this register is 0x00000000. the lsi53c1010 requires 8192 bytes of memory space for scripts ram. for detailed information on the operation of this register, refer to the pci 2.2 speci?cation. 31 0 bar3 00000000000000000000000000000100 31 0 bar4 00000000000000000000000000000000
4-12 registers registers: 0x24C0x27 reserved this register is reserved. registers: 0x28C0x2b reserved this register is reserved. registers: 0x2cC0x2d subsystem vendor id (svid) read only svid subsystem vendor id [15:0] this 16-bit register is used to uniquely identify the vendor manufacturing the add-in board or subsystem where this pci device resides. it provides a mechanism for an add-in card vendor to distinguish its cards from another vendors cards, even if the cards have the same pci controller installed on them (and therefore the same vendor id and device id). 31 0 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 0 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 svid if mad7 is high 0001000000000000 if mad7 is low xxxxxxxxxxxxxxxx
pci con?guration registers 4-13 if the external serial eeprom interface is enabled (mad[7] low), this register is automatically loaded at power-up from the external serial eeprom and contains the value downloaded from the serial eeprom or, if the download fails, a value of 0x0000. if the external serial eeprom interface is disabled (mad[7] high), this register returns a value of 0x1000. the 16-bit value that should be stored in the external serial eeprom for this register is the vendors pci vendor id. this value must be obtained from the pci special interest group (sig). please see section 2.4, serial eeprom interface, for more information on downloading a value for this register. registers: 0x2eC0x2f subsystem id (sid) read only sid subsystem id [15:0] this 16-bit register is used to uniquely identify the add-in board or subsystem where this pci device resides. it provides a mechanism for an add-in card vendor to distinguish its cards from one another even if the cards have the same pci controller installed on them (and therefore the same vendor id and device id). if the external serial eeprom interface is enabled (mad[7] is low), this register is automatically loaded at power-up from the external serial eeprom and contains the value downloaded from the serial eeprom or, if the download fails, a value of 0x0000. if the external serial eeprom is disabled (mad[7] pulled high), the register returns a value of 0x1000. the 16-bit value stored in the external serial eeprom is vendor 15 0 sid if mad[7] is high 0001000000000000 if mad[7] is low xxxxxxxxxxxxxxxx
4-14 registers speci?c. please see section 2.4, serial eeprom inter- face, for additional information on downloading a value for this register. registers: 0x30C0x33 expansion rom base address (erba) read/write this four-byte register handles the base address and size information for the expansion rom. erba expansion rom base address [31:11] bits [31:11] correspond to the upper 21 bits of the expansion rom base address. the host system detects the size of the external memory by ?rst writing the expansion rom base address (erba) register with all ones and then reading back the register. the scsi functions of the lsi53c1010 respond with zeros in all dont care locations. the least signi?cant one that remains represents the binary version of the external memory size. for example, to indicate an external memory size of 32 kbytes, this register, when written with ones and read back, returns ones in the upper 17 bits. the size of the external memory is set through mad[3:1]. please see section 3.8, mad bus programming, for the possible size encodings available. r reserved [10:1] eren expansion rom enable 0 the expansion rom enable bit, bit 0, is used to control whether or not the device accepts accesses to its expansion rom. when the bit is set, address decoding is enabled, and a device is used with or without an expansion rom depending on the system con?guration. note: to access the external memory interface, also set the memory space bit in the command register. 31 11 10 1 0 erba r eren 000000000000000000000 0 0 0 0 0 0 0 0 0 00
pci con?guration registers 4-15 register: 0x34 capabilities pointer (cp) read only cp capabilities pointer [7:0] this register indicates that the ?rst extended capability register is located at offset 0x40 in pci con?guration space. registers: 0x35C0x37 reserved this register is reserved. registers: 0x38C0x3b reserved this register is reserved. 7 0 cp 01000000 23 0 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 0 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4-16 registers register: 0x3c interrupt line (il) read/write il interrupt line [7:0] this register is used to communicate interrupt line routing information. post software writes the routing information into this register as it con?gures the system. the value in this register tells which input of the system interrupt controller(s) the devices interrupt pin is connected to. values in this register are speci?ed by system architecture. register: 0x3d interrupt pin (ip) read only ip interrupt pin [7:0] this register is unique to each scsi function. it tells which interrupt pin the device uses. its value is set to 0x01 for the function a (inta/) signal, and 0x02 for the function b (intb/) signal at power-up if mad[4] is pulled low. the function b value is set to 0x01 (inta/) if mad[4] is pulled high. note: please see section 3.8, mad bus programming, for additional information. 7 0 il 00000000 7 0 ip scsi function a 00000001 scsi function b if mad[4] pulled low 00000010 scsi function b if mad[4] pulled high 00000001
pci con?guration registers 4-17 register: 0x3e min_gnt (mg) read only mg min_gnt [7:0] this register is used to specify the desired settings for latency timer values. min_gnt is used to specify how long a burst period the device needs. the value speci?ed in these registers is in units of 0.25 microseconds. the lsi53c1010 sets this register to 0x11. register: 0x3f max_lat (ml) read only ml max_lat [7:0] this register is used to specify the desired settings for latency timer values. max_lat is used to specify how often the device needs to gain access to the pci bus. the value speci?ed in this register is in units of 0.25 microseconds. the lsi53c1010 scsi function sets this register to 0x12 indicating it needs the bus every 4.5 m s to maintain a data stream of 160 mbytes/s. 7 0 mg 00010001 7 0 ml 00010010
4-18 registers register: 0x40 capability id (cid) read only cid capability id [7:0] this register indicates the type of data structure currently being used. it is set to 0x01, indicating the power management data structure. register: 0x41 next item pointer (nip) read only nip next item pointer [7:0] bits [7:0] contain the offset location of the next item in the functions capabilities list. the lsi53c1010 has these bits set to zero indicating no further extended capabilities registers exist. registers: 0x42C0x43 power management capabilities (pmc) read only pmes pme_support [15:11] bits [15:11] de?ne the power management states in which the lsi53c1010 will assert the pme pin. these bits are all set to zero because the lsi53c1010 does not provide a pme signal. 7 0 cid 00000001 7 0 nip 00000000 15 11 10 9 8 6 5 4 3 2 0 pmes d2s d1s aux_c dsi r pmec ver[2:0] 0000 0 1 1 0 0 00 0 0 010
pci con?guration registers 4-19 d2s d2_support 10 the lsi53c1010 sets this bit to indicate support for power management state d2. bits 9 and 10 are set to indicate support for the d1 and d2 power states. d1s d1_support 9 the lsi53c1010 sets this bit to indicate support for power management state d1. bits 9 and 10 are set to indicate support for the d1 and d2 power states. aux_c aux_current [8:6] the lsi53c1010 always returns zeros. this feature is not supported. dsi device speci?c initialization 5 this bit is cleared to indicate that the lsi53c1010 requires no special initialization before the generic class device driver is able to use it. r reserved 4 pmec pme clock 3 bit 3 is cleared because the lsi53c1010 does not provide a pme pin. ver[2:0] version [2:0] these three bits are set to 0b010 to indicate that the lsi53c1010 complies with revision 1.1 of the pci power management interface speci?cation.
4-20 registers registers: 0x44C0x45 power management control/status (pmcsr) read/write pst pme_status 15 the lsi53c1010 always returns a zero for this bit, indicating that pme signal generation is not supported from d3cold. dscl data_scale [14:13] the lsi53c1010 does not support the data register. therefore, these two bits are always cleared. dslt data_select [12:9] the lsi53c1010 does not support the data register. therefore, these four bits are always cleared. pen pme_enable 8 the lsi53c1010 always returns zero for this bit to indicate that pme assertion is disabled. r reserved [7:2] pws[1:0] power state [1:0] bits [1:0] are used to determine the current power state of the lsi53c1010. they are used to place the lsi53c1010 in a new power state. power states are de?ned as: note: see the section 2.5, power management, for descriptions of the power management states. 15 14 13 12 9 8 7 2 1 0 pst dscl dslt pen r pws[1:0] 00000000 0 0 0 0 0 000 0b00 d0 0b01 d1 0b10 d2 0b11 d3 hot
pci con?guration registers 4-21 register: 0x46 bridge support extensions (pmcsr_bse) read only bse bridge support extensions [7:0] this register indicates pci bridge speci?c functionality. the lsi53c1010 always returns 0x00. register: 0x47 data read only data data [7:0] this register provides an optional mechanism for the function to report state-dependent operating data. the lsi53c1010 always returns 0x00. 7 0 bse 00000000 7 0 data 00000000
4-22 registers 4.2 scsi registers the control registers for the scsi core are directly accessible from the pci bus using memory or i/o mapping. scsi function a and scsi function b contain the same register set with identical default values, except the interrupt pin registers. the address map of the scsi registers is shown in table 4.2 . the eight 32-bit phase mismatch registers contain the byte count and addressing information required to update the direct, indirect, or table indirect bmov instructions with new byte counts and addresses. the phase mismatch registers are the phase mismatch jump address one (pmjad1) , phase mismatch jump address two (pmjad2) , remaining byte count (rbc) , updated address (ua) , entry storage address (esa) , instruction address (ia) , scsi byte count (sbc) , and the cumulative scsi byte count (csbc) . all the phase mismatch registers can be read/written using the load and store scripts instructions, memory-to-memory moves, read/write scripts instructions, or the cpu with scripts not running. note: the only registers that the host cpu can access while the lsi53c1010 is executing scripts are the interrupt status zero (istat0) , interrupt status one (istat1) , mailbox zero (mbox0) , and mailbox one (mbox1) registers; attempts to access other registers interfere with the operation of the chip. however, all operating registers are accessible with scripts. all read data is synchronized and stable when presented to the pci bus. do not access reserved bits or registers.
scsi registers 4-23 table 4.2 scsi register map 31 24 23 16 15 8 7 0 address page scntl3 scntl2 scntl1 scntl0 0x00 4-24 gpreg sdid sxfer scid 0x04 4-33 sbcl ssid socl sfbr 0x08 4-37 sstat2 sstat1 sstat0 dstat 0x0c 4-40 dsa 0x10 4-47 mbox1 mbox0 istat1 istat0 0x14 4-47 ctest3 ctest2 ctest1 ctest0 0x18 4-53 temp 0x1c 4-56 ctest6 ctest5 ctest4 reserved 0x20 4-57 dcmd dbc 0x24 4-61 dnad 0x28 4-62 dsp 0x2c 4-63 dsps 0x30 4-63 scratch a 0x34 4-64 dcntl sbr dien dmode 0x38 4-64 adder 0x3c 4-71 sist1 sist0 sien1 sien0 0x40 4-71 gpcntl reserved swide reserved 0x44 4-79 respid1 respid0 stime1 stime0 0x48 4-81 stest3 stest2 stest1 stest0 0x4c 4-85 cso stest4 sidl 0x50 4-90 ccntl1 ccntl0 sodl 0x54 4-92 ccntl3 reserved sbdl 0x58 4-96 scratch b 0x5c 4-98 scratch cCscratch r 0x60C0x9f 4-99 mmrs 0xa0 4-99 mmws 0xa4 4-100 sfs 0xa8 4-100 drs 0xac 4-101 sbms 0xb0 4-101 dbms 0xb4 4-102 dnad64 0xb8 4-102 aipcntl1 aipcntl0 reserved scntl4 0xbc 4-102 pmjad1 0xc0 4-112 pmjad2 0xc4 4-113 rbc 0xc8 4-113 ua 0xcc 4-114 esa 0xd0 4-115 ia 0xd4 4-115 reserved sbc 0xd8 4-116 csbc 0xdc 4-117 crccntl1 crccntl0 crcpbv 0xe0 4-117 crcd 0xe4 4-120 reserved 0xe8C0xef 4-121 reserved dfbc 0xf0 4-122 reserved 0xf4C0xff 4-122
4-24 registers register: 0x00 scsi control zero (scntl0) read/write arb[1:0] arbitration mode bits 1 and 0 [7:6] a combination of the arb bits selects either simple or full arbitration. simple arbitration 1. the lsi53c1010 scsi function waits for a bus free condition to occur. 2. it asserts sbsy/ and its scsi id, contained in the scsi chip id (scid) register, onto the scsi bus. if the ssel/ signal is asserted by another scsi device, the lsi53c1010 scsi function deasserts sbsy/, deasserts its id, and sets the lost arbitration bit (bit 3) in the scsi status zero (sstat0) register. 3. after an arbitration delay, the cpu should read the scsi bus data lines (sbdl) register to check if a higher priority scsi id is present. if no higher priority id bit is set, and the lost arbitration bit is not set, the lsi53c1010 scsi function wins arbitration. 4. once the lsi53c1010 scsi function wins arbitration, ssel/ must be asserted using the scsi output control latch (socl) for a bus clear and a bus settle delay (1.2 m s). then, a low level selection is performed. 76543210 arb[1:0] start watn epc crcrp aap trg 11000x00 arb1 arb0 arbitration mode 0 0 simple arbitration 0 1 reserved 1 0 reserved 1 1 full arbitration, selection/reselection
scsi registers 4-25 full arbitration, selection/reselection 1. the lsi53c1010 scsi function waits for a bus free condition. 2. it asserts sbsy/ and its scsi id onto the scsi bus. the scsi id asserted is the highest priority id stored in the scsi chip id (scid) register. 3. if the ssel/ signal is asserted by another scsi device or if the lsi53c1010 scsi function detects a higher priority id, the lsi53c1010 scsi function deasserts sbsy/, deasserts its id, sets the lost arbitration bit, bit 3 in the scsi status zero (sstat0) register, and waits until the next bus free state to try arbitration again. 4. the lsi53c1010 scsi function repeats arbitration until it wins control of the scsi bus. when it wins, the won arbitration bit is set in the scsi status zero (sstat0) register, bit 2. 5. the lsi53c1010 scsi function performs selection by asserting ssel/, the targets id (stored in the scsi destination id (sdid) register), and the lsi53c1010s id (stored in the scsi chip id (scid) register) onto the scsi bus. 6. after a selection is complete, the function complete bit is set in the scsi interrupt status zero (sist0) register, bit 6. 7. if a selection time-out occurs, the selection time-out bit is set in the scsi interrupt status one (sist1) register, bit 2. start start sequence 5 when this bit is set, the lsi53c1010 starts the arbitration sequence indicated by the arbitration mode bits. the start sequence bit is accessed directly in low level mode; during scsi scripts operations, this bit is controlled by the scripts processor. do not start an arbitration sequence if the connected (con) bit in the scsi control one (scntl1) register, bit 4, is set. this bit indicates that the lsi53c1010 is already connected to the scsi bus. this bit is automatically cleared when the arbitration
4-26 registers sequence is complete. if a sequence is aborted, check bit 4 in the scsi control one (scntl1) register to verify that the lsi53c1010 is not connected to the scsi bus. watn select with satn/ on a start sequence 4 when this bit is set and the scsi function is in the initiator mode, the satn/ signal is asserted during selection of a scsi target device. this is to inform the target that the lsi53c1010 scsi function has a message to send. if a selection time-out occurs while attempting to select a target device, satn/ is deasserted at the same time ssel/ is deasserted. when this bit is cleared, the satn/ signal is not asserted during selection. when executing scsi scripts, this bit is controlled by the scripts processor, but manual setting is possible in the low level mode. epc enable parity/crc/aip checking 3 when this bit is set and the scsi transfers are asynchronous or st synchronous, the scsi data bus is checked for odd parity when data is received from the scsi bus in either the initiator or the target mode. if a parity error is detected, bit 0 of the scsi interrupt status zero (sist0) register is set and an interrupt may be generated. when this bit is set scsi transfers are dt synchronous, the crc is checked when the target requests a crc transfer using the dp0 signal on the scsi bus. if a crc error is detected, bit 0 of the scsi interrupt status zero (sist0) register is set and an interrupt may be generated. if the lsi53c1010 scsi function is operating in the initiator mode and a parity error or crc error is detected, satn/ can optionally be asserted, but the transfer continues until the target changes phase or the block move in which the parity error was detected completes. when this bit is clear, parity and crc errors are not reported. crcrp crc request pending 2 when this bit is set, the lsi53c1010 scsi function has an outstanding crc request pending. when this bit is set and the lsi53c1010 is in target mode, a block move of
scsi registers 4-27 zero should not be issued. if a block move of zero is issued, back-to-back crc requests are issued. back-to- back crc requests are illegal. aap assert satn/ on parity/crc/aip error 1 when this bit is set, the lsi53c1010 scsi function automatically asserts the satn/ signal upon detection of a parity error or crc error. satn/ is only asserted in the initiator mode. the satn/ signal is asserted before deasserting sack/ during the byte transfer with the parity error. also set the enable parity/crc/aip checking bit for the lsi53c1010 scsi function to assert satn/ in this manner. a parity error or crc error is detected on data received from the scsi bus. if the assert satn/ on parity/crc/aip error bit is cleared or the enable parity/crc/aip checking bit is cleared, satn/ is not automatically asserted on the scsi bus when a parity/crc/aip error is received. trg target mode 0 this bit determines the default operating mode of the lsi53c1010 scsi function. the user must manually set the target or initiator mode. this is done using the scripts language ( set target or clear target ). when this bit is set, the chip is a target device. when this bit is cleared, the lsi53c1010 scsi function is an initiator device. caution: writing this bit while not connected may cause the loss of a selection or reselection due to the changing of target or initiator modes.
4-28 registers register: 0x01 scsi control one (scntl1) read/write r reserved 7 adb assert scsi data bus 6 when this bit is set, the lsi53c1010 scsi function drives the contents of the scsi output data latch (sodl) register onto the scsi data bus. when the lsi53c1010 scsi function is an initiator, the scsi i/o signal must be inactive to assert the sodl contents onto the scsi bus. when the lsi53c1010 scsi function is a target, the scsi i/o signal must be active to assert the sodl contents onto the scsi bus. the contents of the sodl register can be asserted at any time, even before the lsi53c1010 scsi function is connected to the scsi bus. clear this bit when executing scsi scripts. it is normally used only for diagnostics testing or operation in low level mode. dhp disable halt on parity/crc/aip error or atn (target only) 5 the dhp bit is only de?ned for the target mode. when this bit is cleared, the lsi53c1010 scsi function halts the scsi data transfer when a parity/crc/aip error is detected or when the satn/ signal is asserted. if satn/ or a parity/crc/aip error is received in the middle of a data transfer, the lsi53c1010 scsi function may transfer up to three additional bytes before halting to synchronize between internal core cells. during synchronous operation, the lsi53c1010 scsi function transfers data until there are no outstanding synchronous offsets. if the lsi53c1010 scsi function is receiving data, any data residing in the dma fifo is sent to memory before halting. when this bit is set, the lsi53c1010 scsi function does not halt the scsi transfer when satn/ or a parity/crc/aip error is received. 76543210 r adb dhp con rst aesp iarb r 0000000 0
scsi registers 4-29 con connected 4 this bit is automatically set any time the lsi53c1010 scsi function is connected to the scsi bus as an initiator or as a target. it is set after the lsi53c1010 scsi function successfully completes arbitration or when it has responded to a bus-initiated selection or reselection. this bit is also set after the chip wins simple arbitration when operating in low level mode. when this bit is cleared, the lsi53c1010 scsi function is not connected to the scsi bus. the cpu can force a connected or disconnected condition by setting or clearing this bit. rst assert scsi rst/ signal 3 setting this bit asserts the srst/ signal. the srst/ output remains asserted until this bit is cleared. the 25 m s minimum assertion time de?ned in the scsi speci?cation must be timed out by the controlling microprocessor or a scripts loop. aesp assert even scsi parity (force bad parity) 2 when this bit is set, the lsi53c1010 scsi function asserts even parity. it forces a scsi parity error on each byte sent to the scsi bus from the chip. if parity checking is enabled, then the lsi53c1010 scsi function checks data received for odd parity. this bit is used for diagnostics testing and is cleared for normal operation. iarb immediate arbitration 1 setting this bit causes the scsi core to immediately begin arbitration once a bus free phase is detected following an expected scsi disconnect. this bit is useful for multithreaded applications. the arb[1:0] bits in scsi control zero (scntl0) are set for full arbitration and selection before setting this bit. arbitration is retried until won. at that point, the lsi53c1010 scsi function holds sbsy and ssel asserted, and waits for a select or reselect sequence. the immediate arbitration bit is cleared automatically when the selection or reselection sequence is completed or times out.
4-30 registers an unexpected disconnect condition clears iarb with it attempting arbitration. see the scsi disconnect unexpected bit ( scsi control two (scntl2) , bit 7) for more information on expected versus unexpected disconnects. it is possible to abort an immediate arbitration sequence. first, set the abort bit in the interrupt status zero (istat0) register. then one of two things eventually happens: the won arbitration bit ( scsi status zero (sstat0), bit 2) will be set. in this case, the immediate arbitration bit needs to be cleared. this completes the abort sequence and disconnects the chip from the scsi bus. if it is not acceptable to go to the bus free phase immediately following the arbitration phase, it is possible to perform a low level selection instead. the abort completes because the lsi53c1010 scsi function loses arbitration. this is detected by the clearing of the immediate arbitration bit. do not use the lost arbitration bit ( scsi status zero (sstat0) , bit 3) to detect this condition. in this case take no further action. r reserved 0 register: 0x02 scsi control two (scntl2) read/write sdu scsi disconnect unexpected 7 this bit is valid in the initiator mode only. when this bit is set, the scsi core is not expecting the scsi bus to enter the bus free phase. if it does, an unexpected disconnect error is generated (see the unexpected disconnect bit in the scsi interrupt status zero (sist0) register, bit 2). during normal scripts mode operation, this bit is set automatically whenever the scsi core is reselected, or successfully selects another scsi device. the sdu bit 76543210 sdu chm r wss vue0 vue1 wsr 00 0 00000
scsi registers 4-31 should be cleared with a register write (move 0x00 to scsi control two (scntl2) ) before the scsi core expects a disconnect to occur, normally prior to sending an abort, abort tag, bus device reset, clear queue or release recovery message, or before deasserting sack/ after receiving a disconnect command or command complete message. chm chained mode 6 this bit determines whether or not the scsi core is programmed for chained scsi mode. this bit is automatically set by the chained block move (chmov) scripts instruction and is automatically cleared by the block move scripts instruction (move). for more information, refer to section 2.2.18, chained block moves. r reserved [5:4] wss wide scsi send 3 when read, this bit returns the value of the wide scsi send (wss) ?ag. asserting this bit clears the wss ?ag. this clearing function is self-clearing. for more information refer to section 2.2.18, chained block moves. vue0 vendor unique enhancements, bit 0 2 this bit is a read only value indicating whether the group code ?eld in the scsi instruction is standard or vendor unique. if cleared, the bit indicates standard group codes; if set, the bit indicates vendor unique group codes. the value in this bit is reloaded at the beginning of all asynchronous target receives. vue1 vendor unique enhancement, bit 1 1 this bit is used to disable the automatic byte count reload during block move instructions in the command phase. if this bit is cleared, the device reloads the block move byte count if the ?rst byte received is one of the standard group codes. if this bit is set, the device does not reload the block move byte count, regardless of the group code.
4-32 registers wsr wide scsi receive 0 when read, this bit returns the value of the wide scsi receive (wsr) ?ag. setting this bit clears the wsr ?ag. this bit is self-clearing. for more information refer to section 2.2.18, chained block moves. register: 0x03 scsi control three (scntl3) read/write this register is automatically loaded when a table indirect select or reselect scripts instruction is executed. r reserved 7 scf[2:0] synchronous clock conversion factor [6:4] these bits select a factor by which the frequency of sclk is divided before being presented to the synchronous scsi control logic. the synchronous transfer speed is determined by the combination of the divided clock and the setting of the xclks and xclkh bits in the scsi control four (scntl4) register. the table below shows the clock dividers that are available. see the table in the scsi control four (scntl4) register description for a full list of available transfer rates. 76 432 0 r scf[2:0] ews r 00000 0 0 0 scf2 scf1 scf0 factor frequency 0 0 0 sclk/3 0 0 1 sclk/1 0 1 0 sclk/1.5 0 1 1 sclk/2 1 0 0 sclk/3 1 0 1 sclk/4 1 1 0 sclk/6 1 1 1 sclk/8
scsi registers 4-33 ews enable wide scsi 3 when this bit is cleared, all information transfer phases are assumed to be eight bits, transmitted on sd[7:0]/ and sdp0/. when this bit is asserted, data transfers are performed 16 bits at a time; the least signi?cant byte is on sd[7:0]/ and sdp0/, and the most signi?cant byte is on sd[15:8]/, sdp1/. command, status, and message phases are not affected by this bit. because ultra160 dt scsi transfers are always wide this bit must be set. if it is not set, a sge interrupt will occur. r reserved [2:0] register: 0x04 scsi chip id (scid) read/write r reserved 7 rre enable response to reselection 6 when this bit is set, the lsi53c1010 scsi function is enabled to respond to bus-initiated reselection at the chip id in the response id zero (respid0) and response id one (respid1) registers. note that the chip does not automatically recon?gure itself to the initiator mode as a result of being reselected. sre enable response to selection 5 when this bit is set, the lsi53c1010 scsi function is able to respond to bus-initiated selection at the chip id in the response id zero (respid0) and response id one (respid1) registers. note that the chip does not automatically recon?gure itself to target mode as a result of being selected. 76543 0 r rre sre r enc[3:0] x00 x0000
4-34 registers r reserved 4 enc[3:0] encoded chip scsi id [3:0] these bits are used to store the lsi53c1010 scsi function encoded scsi id. this is the id which the chip asserts when arbitrating for the scsi bus. the ids that the lsi53c1010 scsi function responds to when selected or reselected are con?gured in the response id zero (respid0) and response id one (respid1) registers. the priority of the 16 possible ids, in descending order is: register: 0x05 scsi transfer (sxfer) read/write this register is automatically loaded when a table indirect select or reselect scripts instruction is executed. r reserved [7:6] mo[5:0] max scsi synchronous offset [5:0] these bits describe the maximum scsi synchronous offset used by the lsi53c1010 scsi function when transferring synchronous scsi data in either the initiator or target mode. table 4.3 describes the possible combinations and their relationship to the synchronous data offset used by the lsi53c1010 scsi function. these bits determine the lsi53c1010 scsi functions method of transfer for st/dt data-in and st/dt data-out phases only; all other information transfers occur asynchronously. please note that the scsi offset for ultra160 transfers is counted as the maximum number of data transfers allowed to be outstanding, not the maximum req pulses allowed to be outstanding. highest lowest 7654321015141312111098 765 0 r mo[5:0] 0 0000000
scsi registers 4-35 during st data-in or st data-out transfers the maximum supported offset is 31 (mo[5:0] = 0x1f). during dt data-in or dt data-out transfers the maximum supported offset is 62 (mo[5:0] = 0x3e). setting offset values outside the allowable range will result in data corruption. a value of 0 in these bits program the device to perform asynchronous transfers. a value of 1 during dt transfers is illegal and will result in data corruption. register: 0x06 scsi destination id (sdid) read/write r reserved [7:4] enc encoded destination scsi id [3:0] writing these bits sets the scsi id of the intended initiator or target during scsi reselection or selection phases, respectively. when executing scripts, the scripts processor writes the destination scsi id to this register. the scsi id is de?ned by the user in a table 4.3 maximum synchronous offset mo5 mo4 mo3 mo2 mo1 mo0 synchronous offset 0 00000 0-asynchronous 0 0 0 0 0 1 reserved 0 00010 2 0 00011 3 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1 11001 57 1 11010 58 1 11011 59 1 11100 60 1 11101 61 1 11110 62 1 1 1 1 1 1 reserved 7430 r enc x x x x0000
4-36 registers scripts select or reselect instruction. the value written is the binary-encoded id. the priority of the 16 possible ids, in descending order, is: register: 0x07 general purpose (gpreg) read/write a write to this register will cause the data written to be output to the appropriate gpio pin if it is set to output mode in that functions general purpose pin control (gpcntl) register. r reserved [7:5] gpio general purpose i/o [4:0] these bits are programmed through the general purpose pin control (gpcntl) register as inputs, outputs, or to perform special functions. as an output, these pins can be used to enable or disable external terminators. it is also possible to program these signals as live inputs and sense them through a scripts register to register move instruction. gpio[3:0] default as inputs and gpio4 defaults as an output pin. when con?gured as inputs, an internal pull-up is enabled. lsi logic software uses the gpio[1:0] signals to access serial eeprom. gpio1 is used as a clock, with the gpio0 pin serving as data. lsi logic software also reserves the use of gpio[4:2]. if there is a need to use gpio[4:2], please check with lsi logic for additional information. highest lowest 7654321015141312111098 754 0 r gpio x x x0xxxx
scsi registers 4-37 register: 0x08 scsi first byte received (sfbr) read/write sfbr scsi first byte received [7:0] this register contains the ?rst byte received in any asynchronous information transfer phase. for example, when a lsi53c1010 scsi function is operating in the initiator mode, this register contains the ?rst byte received in the message-in, status, and data-in phases. when a block move instruction is executed for a particular phase, the ?rst byte received is stored in this register C even if the present phase is the same as the last phase. the ?rst byte received value for a particular input phase is not valid until after a move instruction is executed. this register is also the accumulator for register read- modify-writes with the scsi first byte received (sfbr) as the destination. this allows bit testing after an operation. the scsi first byte received (sfbr) is not writable using the cpu, and therefore not by a memory move. however, it can be loaded using scripts read/write operations. to load the sfbr with a byte stored in system memory, the byte must ?rst be moved to an intermediate lsi53c1010 scsi function register (such as the scratch register), and then to the sfbr. this register also contains the state of the lower eight bits of the scsi data bus during the selection phase if the com bit in the dma control (dcntl) register is clear. if the com bit is cleared, do not access this register using scripts operations, as indeterminate operations may occur. (this includes scripts read/write operations and conditional transfer control instructions that initialize the scsi first byte received (sfbr) register.) 7 0 ib 00000000
4-38 registers register: 0x09 scsi output control latch (socl) read/write this register is used primarily for diagnostics testing or programmed i/o operation. it is controlled by the scripts processor when executing scsi scripts. scsi output control latch (socl) is used only when transferring data using programmed i/o. some bits are set or cleared when executing scsi scripts. do not write to the register once the lsi53c1010 scsi function starts executing normal scsi scripts. req assert scsi req/ signal 7 ack assert scsi ack/ signal 6 bsy assert scsi bsy/ signal 5 sel assert scsi sel/ signal 4 atn assert scsi atn/ signal 3 msg assert scsi msg/ signal 2 c_d assert scsi c_d/ signal 1 i_o assert scsi i_o/ signal 0 76543210 req ack bsy sel atn msg c_d i_o 00000000
scsi registers 4-39 register: 0x0a scsi selector id (ssid) read only val scsi valid 7 if val is asserted, then the two scsi ids are detected on the bus during a bus-initiated selection or reselection, and the encoded destination scsi id bits below are valid. if val is deasserted, only one id is present and the contents of the encoded destination id are meaningless. r reserved [6:4] enid encoded destination scsi id [3:0] reading the ssid register immediately after the lsi53c1010 scsi function is selected or reselected returns the binary-encoded scsi id of the device that performed the operation. these bits are invalid for targets that are selected under the single initiator option of the scsi-1 speci?cation. this condition is detected by examining the val bit above. 76 43 0 val r enid 0 x x x0000
4-40 registers register: 0x0b scsi bus control lines (sbcl) read only this register returns the scsi control line status. a bit is set when the corresponding scsi control line is asserted. these bits are not latched; they are a true representation of what is on the scsi bus at the time the register is read. the resulting read data is synchronized before being presented to the pci bus to prevent parity errors from being passed to the system. this register is used for diagnostics testing or operation in the low level mode. req assert scsi req/ signal 7 ack assert scsi ack/ signal 6 bsy assert scsi bsy/ signal 5 sel assert scsi sel/ signal 4 atn assert scsi atn/ signal 3 msg assert scsi msg/ signal 2 c_d assert scsi c_d/ signal 1 i_o assert scsi i_o/ signal 0 register: 0x0c dma status (dstat) read only reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register in case additional interrupts are pending (the lsi53c1010 scsi functions stack interrupts). 76543210 req ack bsy sel atn msg c_d i_o xxxxxxxx 76543210 dfe mdpe bf abrt ssi sir r iid 100000 x0
scsi registers 4-41 the dip bit in the interrupt status zero (istat0) register is also cleared. it is possible to mask dma interrupt conditions individually through the dma interrupt enable (dien) register. when performing consecutive 8-bit reads of the dma status (dstat) , scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) registers (in any order), insert a delay equivalent to 12 clk periods between the reads to ensure that the interrupts clear properly. see chapter 2, functional description, for more information on interrupts. dfe dma fifo empty 7 this status bit is set when the dma fifo is empty. it is possible to use it to determine if any data resides in the fifo when an error occurs and an interrupt is generated. this bit is a pure status bit and does not cause an interrupt. mdpe master data parity error 6 this bit is set when the lsi53c1010 scsi function, acting as a pci master, detects a data parity error, or, acting as a target device, signals a parity error during a data phase. this bit is completely disabled by the master parity error enable bit (bit 3 of chip test four (ctest4) ). bf bus fault 5 this bit is set when a pci bus fault condition is detected. a pci bus fault can only occur when the lsi53c1010 scsi function is bus master, and is de?ned as a cycle that ends with a bad address or target abort condition. abrt aborted 4 this bit is set when an abort condition occurs. an abort condition occurs when a software abort command is issued by setting bit 7 of the interrupt status zero (istat0) register. ssi single step interrupt 3 if the single-step mode bit in the dma control (dcntl) register is set, this bit is set and an interrupt generated after successful execution of each scripts instruction. sir scripts interrupt instruction received 2 this status bit is set whenever an interrupt instruction is evaluated as true.
4-42 registers r reserved 1 iid illegal instruction detected 0 this status bit is set any time an illegal or reserved instruction opcode is detected, whether the lsi53c1010 scsi function is operating in single-step mode or automatically executing scsi scripts. any of the following conditions during instruction execution also sets this bit: the lsi53c1010 scsi function is executing a wait disconnect instruction and the scsi req line is asserted without a disconnect occurring. a block move instruction is executed as an initiator with 0x000000 loaded into the dma byte counter (dbc) register, indicating there are zero bytes to move. during a transfer control instruction, the compare data (bit 18) and compare phase (bit 17) bits are set in the dma byte counter (dbc) register while the lsi53c1010 scsi function is in target mode. during a transfer control instruction, the carry test bit (bit 21) is set and either the compare data (bit 18) or compare phase (bit 17) bit is set. a transfer control instruction is executed with the reserved bit 22 set. a transfer control instruction is executed with the wait for valid phase bit (bit 16) set while the chip is in the target mode. a load and store instruction is issued with the memory address mapped to the operating registers of the chip, not including rom or ram. a load and store instruction is issued when the register address is not aligned with the memory address. a load and store instruction is issued with bit 5 in the dma command (dcmd) register cleared or bits 3 or 2 set. a load and store instruction when the count value in the dma byte counter (dbc) register is not set at 1 to 4.
scsi registers 4-43 a load and store instruction attempts to cross a dword boundary. a memory move instruction is executed with one of the reserved bits in the dma command (dcmd) register set. a memory move instruction is executed with the source and destination addresses not aligned. a 64-bit table indirect block move instruction is executed with a selector index value greater than 0x16. if the select with atn/ bit is set for any i/o instruction other than a select instruction. register: 0x0d scsi status zero (sstat0) read only ilf sidl least signi?cant byte full 7 this bit is set when the least signi?cant byte in the scsi input data latch (sidl) contains data. data is transferred from the scsi bus to the scsi input data latch register before being sent to the dma fifo and then to the host bus. the scsi input data latch (sidl) register contains scsi data received asynchronously. synchronous data received does not ?ow through this register. r reserved 6 olf sodl least signi?cant byte full 5 this bit is set when the least signi?cant byte in the scsi output data latch (sodl) contains data. the sodl register is the interface between the dma logic and the scsi bus for asynchronous send operations. in the asynchronous mode, data is transferred from the host bus to the sodl register, and then to the scsi bus. it is possible to use this bit to determine how many bytes reside in the device when an error occurs. 76543210 ilf r olf arbip loa woa rst sdp0 0 0000000
4-44 registers arbip arbitration in progress 4 arbitration in progress (arbip = 1) indicates that the lsi53c1010 scsi function has detected a bus free condition, asserted sbsy, and asserted its scsi id onto the scsi bus. loa lost arbitration 3 when set, loa indicates that the lsi53c1010 scsi function has detected a bus free condition, arbitrated for the scsi bus, and lost arbitration due to another scsi device asserting the ssel/ signal. woa won arbitration 2 when set, woa indicates that the lsi53c1010 scsi function has detected a bus free condition, arbitrated for the scsi bus and won arbitration. the arbitration mode selected in the scsi control zero (scntl0) register must be full arbitration and selection to set this bit. rst scsi rst/ signal 1 this bit reports the current status of the scsi rst/ signal, and the rst signal (bit 3) in the scsi control one (scntl1) register. this bit is not latched and may change as it is read. sdp0 scsi sdp0 parity signal 0 this bit represents the present state of the scsi sdp0/ parity signal. this signal is not latched and may change as it is read.
scsi registers 4-45 register: 0x0e scsi status one (sstat1) read only r reserved [7:4] sdp0l latched scsi parity 3 this bit re?ects the scsi parity signal (sdp0/), corresponding to the data latched in the scsi input data latch (sidl) . it changes when a new byte is latched into the least signi?cant byte of the sidl register. this bit is active high, in other words, it is set when the parity signal is active. msg scsi msg/ signal 2 this scsi phase status bit is latched on the asserting edge of sreq/ when operating in either the initiator or target mode. this bit is set when the corresponding signal is active. it is useful when operating in the low level mode. c_d scsi c_d/ signal 1 this scsi phase status bit is latched on the asserting edge of sreq/ when operating in either the initiator or target mode. this bit is set when the corresponding signal is active. it is useful when operating in the low level mode. i_o scsi i_o/ signal 0 this scsi phase status bit is latched on the asserting edge of sreq/ when operating in either the initiator or target mode. this bit is set when the corresponding signal is active. it is useful when operating in the low level mode. 7 43210 r sdp0l msg c_d i_o 0 0 0 0xxxx
4-46 registers register: 0x0f scsi status two (sstat2) read only ilf1 sidl most signi?cant byte full 7 this bit is set when the most signi?cant byte in the scsi input data latch (sidl) contains data. data is transferred from the scsi bus to the scsi input data latch register before being sent to the dma fifo. the data is then sent to the host bus. the sidl register contains scsi data received asynchronously. synchronous data received does not ?ow through this register. r reserved 6 olf1 sodl most signi?cant byte full 5 this bit is set when the most signi?cant byte in the scsi output data latch (sodl) contains data. the sodl register is the interface between the dma logic and the scsi bus for asynchronous send operations. in the asynchronous mode, data is transferred from the host bustothe scsi output data latch (sodl) register, and then to the scsi bus. this bit can be used to determine how many bytes reside in the device when an error occurs. r reserved 4 spl1 latched scsi parity for sd[15:8] 3 this active high bit re?ects the scsi odd parity signal corresponding to the data latched into the most signi?cant byte in the scsi input data latch (sidl) register. r reserved 2 ldsc last disconnect 1 this bit is used in conjunction with the connected (con) bit in scsi control one (scntl1) . it allows the user to detect the case in which a target device disconnects, and then a scsi device selects or reselects the lsi53c1010 76543210 ilf1 r olf1 r spl1 r ldsc sdp1 0 00 0x 01x
scsi registers 4-47 scsi function. if the connected bit and the ldsc bit are asserted, a disconnect is indicated. this bit is set when the connected bit in scntl1 is off. this bit is cleared when a block move instruction is executed while the connected bit in scntl1 is set. sdp1 scsi sdp1 parity signal 0 this bit represents the present state of the scsi sdp1/ parity signal. it is not latched and may change as it is read. registers: 0x10C0x13 data structure address (dsa) read/write dsa data structure address [31:0] this 32-bit register contains the base address used for all table indirect calculations. the dsa register is usually loaded prior to starting an i/o, but it is possible for a scripts memory move to load the dsa during the i/o. during any memory-to-memory move operation, the contents of this register are preserved. the power-up value of this register is indeterminate. register: 0x14 interrupt status zero (istat0) read/write this is the only register that is accessible by the host cpu while a lsi53c1010 scsi function is executing scripts (without interfering in the operation of the function). it is used to poll for interrupts if hardware interrupts are disabled. read this register after servicing an interrupt to check for stacked interrupts. 31 0 dsa 00000000000000000000000000000000 76543210 abrt srst sigp sem con intf sip dip 00000000
4-48 registers abrt abort operation 7 setting this bit aborts the current operation under execution by the lsi53c1010 scsi function. if this bit is set and an interrupt is received, clear this bit before reading the dma status (dstat) register to prevent further aborted interrupts from being generated. the sequence to abort any operation is: 1. set this bit. 2. wait for an interrupt. 3. read the interrupt status zero (istat0) register. 4. if the scsi interrupt pending bit is set, read the scsi interrupt status zero (sist0) or scsi interrupt status one (sist1) register to determine the cause of the scsi interrupt and return to step 2. 5. if the scsi interrupt pending bit is cleared and the dma interrupt pending bit is set, write 0x00 to this register. 6. read the dma status (dstat) register to verify the aborted interrupt and to determine if any other interrupting conditions have occurred. srst software reset 6 setting this bit resets the lsi53c1010 scsi function. all operating registers are cleared to their respective default values and all scsi signals are deasserted. setting this bit does not assert the scsi rst/ signal. this reset does not clear the id mode bit or any of the pci con?guration registers. this bit is not self-clearing; it must be cleared to clear the reset condition. a hardware reset also clears this bit. note: if scripts are running, then the abrt bit (bit 7) must be set prior to setting the srst bit. sigp signal process 5 sigp is a r/w bit that is writable at any time. it is polled and reset using chip test two (ctest2) . the sigp bit is used in various ways to pass a ?ag to or from a running scripts instruction.
scsi registers 4-49 the only scripts instruction directly affected by the sigp bit is wait for selection/reselection. setting the sigp bit causes this instruction to jump to the alternate address immediately. the instructions at the alternate jump address should check the status of sigp to determine the cause of the jump. the sigp bit is usable at any time and is not restricted to the wait for selection/reselection condition. sem semaphore 4 the scripts processor may set this bit using a scripts register write instruction. an external processor may also set it while the lsi53c1010 scsi function is executing a scripts operation. this bit enables the scsi function to notify an external processor of a prede?ned condition while scripts are running. the external processor may also notify the lsi53c1010 scsi function of a prede?ned condition and the scripts processor may take action while scripts are executing. con connected 3 this bit is automatically set any time the lsi53c1010 scsi function is connected to the scsi bus as an initiator or as a target. it is set after successfully completing selection or when the lsi53c1010 scsi function responds to a bus-initiated selection or reselection. it is also set after the scsi function wins arbitration when operating in the low level mode. when this bit is cleared, the lsi53c1010 scsi function is not connected to the scsi bus. intf interrupt-on-the-fly 2 this bit is asserted by an intfly instruction during scripts execution. scripts programs do not halt when the interrupt occurs. this bit can be used to notify a service routine, running on the main processor while the scripts processor is still executing a scripts program. if this bit is set, when the interrupt status zero (istat0) register is read it is not automatically cleared. to clear this bit, write a one to it. the reset operation is self-clearing.
4-50 registers note: if the intf bit is set but sip or dip is not set, do not attempt to read the other chip status registers. an interrupt- on-the-fly must be cleared before servicing any other interrupts indicated by sip or dip. after it has been set, this bit must be written to one to clear it. sip scsi interrupt pending 1 this status bit is set when an interrupt condition is detected in the scsi portion of the lsi53c1010 scsi function. the following conditions cause a scsi interrupt to occur: a phase mismatch (initiator mode) or satn/ becomes active (target mode) an arbitration sequence completes a selection or reselection time-out occurs the lsi53c1010 scsi function is selected the lsi53c1010 scsi function is reselected a scsi gross error occurs an unexpected disconnect occurs a scsi reset occurs a parity error is detected the handshake-to-handshake timer expires the general purpose timer expires to determine which condition(s) caused the interrupt, read the scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) registers. dip dma interrupt pending 0 this status bit is set when an interrupt condition is detected in the dma portion of the lsi53c1010 scsi function. the following conditions cause a dma interrupt to occur: a pci parity error is detected a bus fault is detected an abort condition is detected
scsi registers 4-51 a scripts instruction is executed in the single-step mode a scripts interrupt instruction is executed an illegal instruction is detected to determine exactly which condition(s) caused the interrupt, read the dma status (dstat) register. register: 0x15 interrupt status one (istat1) read/write r reserved [7:3] flsh flushing 2 if this bit is set, the chip is ?ushing data from the dma fifo. if this bit is cleared, no ?ushing is occurring. this bit is read only. writes do not affect the value of this bit. srun scripts running 1 if this bit is set, the scripts engine is currently fetching and executing scripts instructions. if this bit is cleared, the scripts engine is not active. this bit is read only. writes do not affect the value of this bit. si sync_irqd 0 setting this bit disables the inta/ pin for function a and the intb/ pin for function b. clearing this bit enables normal operation of the inta/ (or intb/) pin. if the inta/ (or intb/) is already asserted and this bit is set, int remains asserted until the interrupt is serviced. at this point the interrupt line is blocked for future interrupts until this bit is cleared. in addition, this bit may be read and written while scripts are executing. 7 3210 r flsh srun si 0 0 0 0 0000
4-52 registers register: 0x16 mailbox zero (mbox0) read/write mbox0 mailbox zero [7:0] these are general purpose bits that may be read or written while scripts are running. they also may be read or written by the scripts processor. note: the host and the scripts processor code could access the same mailbox byte at the same time. using one mailbox register as read only and the other as write only prevents this con?ict. register: 0x17 mailbox one (mbox1) read/write mbox1 mailbox one [7:0] these are general purpose bits that may be read or written while scripts are running. they also may be read or written by the scripts processor. note: the host and the scripts processor code could access the same mailbox byte at the same time. using one mailbox register as read only and the other as write only prevents this con?ict. 7 0 mbox0 00000000 7 0 mbox1 00000000
scsi registers 4-53 register: 0x18 chip test zero (ctest0) read/write fmt byte empty in dma fifo [7:0] these bits identify the lower bytes in the dma fifo that are empty. each bit corresponds to a byte lane in the dma fifo. for example, if byte lane three is empty, then fmt bit 3 is set. the fmt ?ags indicate the status of bytes at the bottom of the fifo. therefore, if all fmt bits are set, the dma fifo is empty. register: 0x19 chip test one (ctest1) read only ffl byte full in dma fifo [7:0] these status bits identify the upper bytes in the dma fifo that are full. each bit corresponds to a byte lane in the dma fifo. for example, if byte lane three is full then ffl bit 3 is set. the ffl ?ags indicate the status of bytes at the top of the fifo. therefore, if all ffl bits are set, the dma fifo is full. 7 0 fmt 11111111 7 0 ffl 00000000
4-54 registers register: 0x1a chip test two (ctest2) read only (bit 3 write) r reserved 7 sigp signal process 6 this bit is a copy of the sigp bit in the interrupt status zero (istat0) register (bit 5). the sigp bit is used to signal a running scripts instruction. when this register is read, the sigp bit in the interrupt status zero (istat0) register is cleared. cio con?gured as i/o 5 this bit is de?ned as the con?guration i/o enable status bit. this read only bit indicates if the chip is currently enabled as i/o space. cm con?gured as memory 4 this bit is de?ned as the con?guration memory enable status bit. this read only bit indicates if the chip is currently enabled as memory space. note: bits 4 and 5 may be set if the chip is mapped in both i/o and memory space. also, bits 4 and 5 may be set if the chip is dual-mapped. pcicie pci con?guration info enable 3 this bit controls the shadowing of the pci base address register one (bar1) (memory) , pci base address register two (bar2) (memory) , pci base address register three (bar3) (scripts ram) , pci base address register four (bar4) (scripts ram) , pci device id , and pci revision id (rid) into the scratch register a (scratcha) , memory move read selector (mmrs) , scratch register b (scratchb) , memory move write selector (mmws) , and script fetch selec- tor (sfs) registers. 765432 0 r sigp cio cm pcicie r x0xx0 x x x
scsi registers 4-55 when it is set, mmws contains bits [63:32] and scratch b contains bits [31:0] of the ram base address value from the pci con?guration base address register three (bar3) (scripts ram) and base address register four (bar4) (scripts ram) . this is the base address for the 8 kbytes of internal ram. memory move read selector (mmrs) contains bits [63:32] and scratch register a (scratcha) contains bits [31:0] of the memory mapped operating register base address. bits [23:16] of script fetch selector (sfs) contain the pci revision id (rid) register value and bits [15:0] contain the pci device id register value. when this bit is set, only reads to the registers are affected, writes occur normally. when this bit is cleared, the scratch a, mmrs, scratch b, mmws, and sfs registers return to normal operation. note: bit 3 is the only writable bit in this register. all other bits are read only. when modifying this register, all other bits must be written to zero. do not execute a read-modify-write to this register. r reserved [2:0] register: 0x1b chip test three (ctest3) read/write r reserved [7:4] flf flush dma fifo 3 when this bit is set, data residing in the dma fifo is transferred to memory, starting at the address in the dma next address (dnad) register. the internal dmawr signal, controlled by the chip test five (ctest5) register, determines the direction of the transfer. this bit is not self-clearing; clear it once the data is successfully transferred by the lsi53c1010 scsi function. 7 43210 r flf clf r wrie 0 0 0 000 00
4-56 registers note: polling of fifo ?ags is allowed during ?ush operations. clf clear dma fifo 2 when this bit is set, all data pointers for the dma fifo are cleared. any data in the fifo is lost. after the lsi53c1010 scsi function successfully clears the appropriate fifo pointers and registers, this bit automatically clears. note: this bit does not clear the data visible at the bottom of the fifo. r reserved 1 wrie write and invalidate enable 0 this bit, when set, causes the issuing of write and invalidate commands on the pci bus whenever legal. the write and invalidate enable bit in the pci con?guration command register must also be set for the chip to generate write and invalidate commands. registers: 0x1cC0x1f temporary (temp) read/write temp temporary [31:0] this 32-bit register stores the return instruction address pointer from the call instruction. the address pointer stored in this register is loaded into the dma scripts pointer (dsp) register when a return instruction is executed. this address points to the next instruction to execute. do not write to this register while the lsi53c1010 scsi function is executing scripts. during any memory-to-memory move operation, the contents of this register are preserved. the power-up value of this register is indeterminate. 31 0 temp 00000000000000000000000000000000
scsi registers 4-57 register: 0x20 reserved this register is reserved. register: 0x21 chip test four (ctest4) read/write r reserved 7 fbl3 fifo byte control 3 6 this bit is used with fbl[2:0]. see bits [2:0] description in this register. r reserved 5 srtm shadow register test mode 4 setting this bit allows access to the shadow registers used by memory-to-memory move operations. when this bit is set, register accesses to the temporary (temp) and data structure address (dsa) registers are directed to the shadow copies stemp (shadow temp) and sdsa (shadow dsa). the registers are shadowed to prevent them from being overwritten during a memory-to-memory move operation. the data structure address (dsa) and temporary (temp) registers contain the base address used for table indirect calculations, and the address pointer for a call or return instruction, respectively. for more information, refer to section 4.3, scsi shadow registers. mpee master parity error enable 3 setting this bit enables parity checking during master data phases. a parity error during a bus master read is 7 0 r x x x x x x x x 765432 0 r fbl3 r srtm mpee fbl[2:0] 00 000000
4-58 registers detected by the lsi53c1010 scsi function. a parity error during a bus master write is detected by the target, and the lsi53c1010 scsi function is informed of the error by the perr/ pin being asserted by the target. when this bit is cleared, the lsi53c1010 scsi function does not interrupt if a master parity error occurs. this bit is cleared at power-up. fbl[2:0] fifo byte control [2:0] these bits steer the contents of the chip test six (ctest6) register to the appropriate byte lane of the 64-bit dma fifo. if the fbl3 bit is set, then fbl2 through fbl0 determine which of eight byte lanes can be read or written. when cleared, the byte lane read or written is determined by the current contents of the dma next address (dnad) and dma byte counter (dbc) registers. each of the eight bytes that make up the 64-bit dma fifo is accessed by writing these bits to the proper value. for normal operation, fbl3 must equal zero. fbl3 fbl2 fbl1 fbl0 dma fifo byte lane pins 0 x x x disabled n/a 1 0 0 0 0 d[7:0] 1 0 0 1 1 d[15:8] 1 0 1 0 2 d[23:16] 1 0 1 1 3 d[31:24] 1 1 0 0 4 d[39:32] 1 1 0 1 5 d[47:40] 1 1 1 0 6 d[53:48] 1 1 1 1 7 d[63:54]
scsi registers 4-59 register: 0x22 chip test five (ctest5) read/write adck clock address incrementor 7 setting this bit increments the address pointer contained in the dma next address (dnad) register. the dnad register is incremented based on the dnad contents and the current dma byte counter (dbc) value. this bit automatically clears itself after incrementing the dnad register. bbck clock byte counter 6 setting this bit decrements the byte count contained in the 24-bit dma byte counter (dbc) register. it is decremented based on the dbc contents and the current dma next address (dnad) value. this bit automatically clears itself after decrementing the dbc register. r reserved [5:3] bl2 burst length bit 2 2 this bit works with bits 6 and 7 (bl[1:0]) in the dma mode (dmode) , 0x38 register to determine the burst length. for complete de?nitions of this ?eld, refer to the descriptions of dmode bits 6 and 7. r reserved [1:0] 765 3210 adck bbck r bl2 r 00 0 0 00 0 0
4-60 registers register: 0x23 chip test six (ctest6) read/write df dma fifo [7:0] writing to this register writes data to the appropriate byte lane of the dma fifo, as determined by the fbl bits in the chip test four (ctest4) register. reading this register unloads data from the appropriate byte lane of the dma fifo, as determined by the fbl bits in the ctest4 register. data written to the fifo is loaded into the top of the fifo. data read out of the fifo is taken from the bottom. to prevent dma data from being corrupted, this register should not be accessed before starting or restarting scripts operations. this register should be the last register read when performing register dumps because of its effects on other registers. write to this register only when testing the dma fifo using the ctest4 register. writing to this register while the test mode is not enabled produces unexpected results. 7 0 df 00000000
scsi registers 4-61 registers: 0x24C0x26 dma byte counter (dbc) read/write dbc dma byte counter [23:0] this 24-bit register determines the number of bytes transferred in a block move instruction. while sending data to the scsi bus, the counter is decremented as data is moved into the dma fifo from memory. while receiving data from the scsi bus, the counter is decremented as data is written to memory from the lsi53c1010 scsi function. the dbc counter is decremented each time data is transferred on the pci bus. it is decremented by an amount equal to the number of bytes transferred. the maximum number of bytes transferred in any one block move command is 16,777,215 bytes. the maximum value that can be loaded into the dma byte counter (dbc) register is 0xffffff. if the instruction is a block move and a value of 0x000000 is loaded into the dbc register, an illegal instruction interrupt occurs if the lsi53c1010 scsi function is not in the target mode, command phase. the dma byte counter (dbc) register is also used to hold the least signi?cant 24-bits of the ?rst dword of a scripts fetch, and to hold the offset value during table indirect i/o scripts. for a complete description see chapter 5, scsi scripts instruction set. the power-up value of this register is indeterminate. 23 0 dbc 000000000000000000000000
4-62 registers register: 0x27 dma command (dcmd) read/write dcmd dma command [7:0] this 8-bit register determines the instruction for the lsi53c1010 scsi function to execute. this register has a different format for each instruction. for a complete description see chapter 5, scsi scripts instruction set. registers: 0x28C0x2b dma next address (dnad) read/write dnad dma next address [31:0] this 32-bit register contains the general purpose address pointer. at the start of some scripts operations, its value is copied from the dma scripts pointer save (dsps) register. its value may not be valid except in certain abort conditions. the default value of this register is zero. 7 0 dcmd 00000000 31 0 dnad 00000000000000000000000000000000
scsi registers 4-63 registers: 0x2cC0x2f dma scripts pointer (dsp) read/write dsp dma scripts pointer [31:0] to execute scsi scripts, the address of the ?rst scripts instruction must be written to this register. in normal scripts operation, once the starting address of the script is written to this register, scripts are automatically fetched and executed until an interrupt condition occurs. in the single-step mode, there is a single step interrupt after each instruction is executed. the dma scripts pointer (dsp) register does not need to be written with the next address. however, to fetch and execute the next scripts command, the start dma bit (bit 2, dma con- trol (dcntl) register) must be set each time the step interrupt occurs. when writing this register eight bits at a time, writing the upper eight bits begins execution of scsi scripts. the default value of this register is zero. registers: 0x30C0x33 dma scripts pointer save (dsps) read/write dsps dma scripts pointer save [31:0] this register contains the second dword of a scripts instruction. it is overwritten each time a scripts instruction is fetched. when a scripts interrupt instruction is executed, this register holds the interrupt vector. the power-up value of this register is indeterminate. 31 0 dsp 00000000000000000000000000000000 31 0 dsps 00000000000000000000000000000000
4-64 registers registers: 0x34C0x37 scratch register a (scratcha) read/write scratcha scratch register a [31:0] this is a general purpose, user-de?nable scratch pad register. apart from cpu access, only register read/write and memory moves into the scratch register alter its contents. the power-up value of this register is indeterminate. a special mode of this register is enabled by setting the pci con?guration info enable bit in the chip test two (ctest2) register. if this bit is set, bits [31:10] of scratch register a (scratcha) return bits [31:10] of the pci base address register one (bar1) (memory) . bits [9:0] of scratch a will always return zero in this mode. writes to the scratcha register are unaffected. clearing the pci con?guration info enable bit causes the scratch a register to return to normal operation. register: 0x38 dma mode (dmode) read/write bl[1:0] burst length [7:6] these bits control the maximum number of dwords transferred per bus ownership, regardless of whether the transfers are back-to-back, burst, or a combination of both. this value is also independent of the width (64-bit or 32-bit) of the data transfer on the pci bus. the lsi53c1010 scsi function asserts the bus request (pcireq/) output when the dma fifo can accommodate a transfer of at least one burst threshold of 31 0 scratcha 00000000000000000000000000000000 76543210 bl[1:0] siom diom erl ermp bof man 00000000
scsi registers 4-65 data. bus request (pcireq/) is also asserted during start-of-transfer and end-of-transfer cleanup and alignment, even if less than a full burst of transfers is performed. the lsi53c1010 scsi function inserts a fairness delay of four clks between burst transfers (set in bl[2:0]) during normal operation. the fairness delay is not inserted during pci retry cycles. this gives the cpu and other bus master devices the opportunity to access the pci bus between bursts. siom source i/o-memory enable 5 this bit is de?ned as an i/o memory enable bit for the source address of a memory move or block move command. if this bit is set, then the source address is in i/o space; if cleared, the source address is in memory space. this function is useful for register-to-memory operations using the memory move instruction when a lsi53c1010 scsi function is i/o mapped. bits 4 and 5 of the chip test two (ctest2) register are used to determine the con?guration status of the lsi53c1010 scsi function. diom destination i/o-memory enable 4 this bit is de?ned as an i/o memory enable bit for the destination address of a memory move or block move command. if this bit is set, then the destination address is in i/o space; if cleared, the destination address is in memory space. bl2 (ctest5 bit 2) bl1 bl0 number of 64-bit transfers number of 32-bit transfers 0002 4 0014 8 010816 0111632 1003264 1 0 1 64 128 1 1 0 64 128 1 1 1 reserved reserved
4-66 registers this function is useful for memory-to-register operations using the memory move instruction when a lsi53c1010 scsi function is i/o mapped. bits 4 and 5 of the chip test two (ctest2) register are used to determine the con?guration status of the lsi53c1010 scsi function. erl enable read line 3 this bit enables a pci read line command. if this bit is set and the chip is about to execute a read cycle (other than an opcode fetch), the command is 0b1110. ermp enable read multiple 2 if this bit is set and cache mode is enabled, a read multiple command is used on all read cycles when it is legal. bof burst opcode fetch enable 1 setting this bit causes the lsi53c1010 scsi function to fetch instructions in burst mode. speci?cally, the chip bursts in the ?rst two dwords of all instructions using a single bus ownership. if the instruction is a memory-to- memory move type, the third dword is accessed in a subsequent bus ownership. if the instruction is an indirect type, the additional dword is accessed in a subsequent bus ownership. if the instruction is a table indirect block move type, the chip accesses the remaining two dwords in a subsequent bus ownership, thereby fetching the four dwords required in two bursts of two dwords each. if prefetch is enabled, this bit has no affect. this bit also has no affect on fetches out of scripts ram. man manual start mode 0 setting this bit prevents the lsi53c1010 scsi function from automatically fetching and executing scsi scripts when the dma scripts pointer (dsp) register is written. when this bit is set, the start dma bit in the dma control (dcntl) register must be set to begin scripts execution. clearing this bit causes the lsi53c1010 scsi function to automatically begin fetching and executing scsi scripts when the dma scripts pointer (dsp) register is written. this bit normally is not used for scsi scripts operations.
scsi registers 4-67 register: 0x39 dma interrupt enable (dien) read/write this register contains the interrupt mask bits corresponding to the interrupting conditions described in the dma status (dstat) register. an interrupt is masked by clearing the appropriate mask bit. masking an interrupt prevents inta/ (for function a) or intb/ (for function b) from being asserted for the corresponding interrupt, but the status bit is still set in the dma status (dstat) register. masking an interrupt does not prevent setting the interrupt status zero (istat0) dip. all dma interrupts are considered fatal. therefore, scripts halts when this condition occurs, whether or not the interrupt is masked. setting a mask bit enables the assertion of inta/, or intb/, for the corresponding interrupt. a masked nonfatal interrupt does not prevent unmasked or fatal interrupts from getting through; interrupt stacking begins when either the interrupt status zero (istat0) sip or dip bit is set. the inta/ and intb/ outputs are latched. once asserted, they remain asserted until the interrupt is cleared by reading the appropriate status register. masking an interrupt after the inta/, or intb/, output is asserted does not cause deassertion of inta/ or intb/. for more information on interrupts, see chapter 2, functional description. r reserved 7 mdpe master data parity error 6 bf bus fault 5 abrt aborted 4 ssi single step interrupt 3 sir scripts interrupt instruction received 2 r reserved 1 iid illegal instruction detected 0 76543210 r mdpe bf abrt ssi sir r iid x00000 x0
4-68 registers register: 0x3a scratch byte register (sbr) read/write sbr scratch byte register [7:0] this is a general purpose register. apart from cpu access, only register read/write and memory moves into this register alter its contents. the default value of this register is zero. this register is called the dma watchdog timer on previous lsi53c8xx family products. register: 0x3b dma control (dcntl) read/write clse cache line size enable 7 setting this bit enables the lsi53c1010 scsi function to sense and react to cache line boundaries set up by the dma mode (dmode) or pci cache line size (cls) register, whichever contains the smaller value. clearing this bit disables the cache line size logic. pff prefetch flush 6 setting this bit causes the prefetch unit to ?ush its contents. this bit clears after the ?ush is complete. pfen prefetch enable 5 setting this bit enables an 8-dword scripts instruction prefetch unit. the prefetch unit, when enabled, fetches 8 dwords of instructions and instruction operands in bursts of 4 or 8 dwords. prefetching instructions allows the lsi53c1010 scsi function to make more ef?cient use of the system pci bus, thus improving overall system performance. a ?ush occurs whenever the pff bit is set, on all transfer control instructions (when the transfer 7 0 sbr 00000000 76543210 clse pff pfen ssm irqm std r com 000000 00
scsi registers 4-69 conditions are met), on writes to the dma scripts pointer (dsp) , on regular mmov instructions, and when an interrupt is generated. based on the burst length as determined by the values in the dma mode (dmode) register, the unit automatically determines the maximum burst size that it is capable of performing. if the burst threshold is set to 8 dwords, the prefetch unit fetches instructions in two bursts of 4 dwords. if the burst threshold is set to 16 dwords or greater, the prefetch unit fetches instructions in one burst of 8 dwords. burst thresholds of less than 8 dwords cause the prefetch unit to be disabled. pci cache commands (read line and read multiple) are issued if pci caching is enabled. prefetching from scripts ram is not supported and is unnecessary due to the speed of the fetches. when fetching from scripts ram, the setting of this bit has no effect on the fetch mechanism from scripts ram. the prefetch unit does not support 64-bit data instruction fetches across the pci bus. prefetches of scripts instructions are 32-bits in width. ssm single-step mode 4 setting this bit causes the lsi53c1010 scsi function to stop after executing each scripts instruction and to generate a single step interrupt. when this bit is cleared the lsi53c1010 scsi function does not stop after each instruction. it continues fetching and executing instructions until an interrupt condition occurs. for normal scsi scripts operation, keep this bit cleared. to restart the lsi53c1010 scsi function after it generates a scripts step interrupt, read the interrupt status zero (istat0) and dma status (dstat) registers to recognize and clear the interrupt. then set the start dma bit in this register. irqm irq mode 3 when set, this bit enables a totem pole driver for the inta/, or intb/ pin. when cleared, this bit enables an open drain driver for the inta/, or intb/, pin with an internal weak pull-up. the bit should remain cleared to retain full pci compliance. std start dma operation 2 the lsi53c1010 scsi function fetches a scsi scripts instruction from the address contained in the dma
4-70 registers scripts pointer (dsp) register when this bit is set. this bit is required if the lsi53c1010 scsi function is in one of the following modes: manual start mode C bit 0 in the dma mode (dmode) register is set single-step mode C bit 4 in the dma control (dcntl) register is set when the lsi53c1010 scsi function is executing scripts in manual start mode, the start dma bit must be set to start instruction fetches, but need not be set again until an interrupt occurs. when the lsi53c1010 scsi function is in the single-step mode, set the start dma bit to restart execution of scripts after a single-step interrupt. r reserved 1 com lsi53c700 family compatibility 0 when the com bit is cleared, the lsi53c1010 scsi function behaves in a manner compatible with the lsi53c700 family; selection/reselection ids are stored in both the scsi selector id (ssid) and scsi first byte received (sfbr) registers. this bit is not affected by a software reset. if the com bit is cleared, do not access this register using scripts operation as indeterminate operations may occur. this includes scripts read/write operations and conditional transfer control instructions that initialize the scsi first byte received (sfbr) register. when the com bit is set, the id is stored only in the scsi selector id (ssid) register, protecting the scsi first byte received (sfbr) from being overwritten if a selection/reselection occurs during a dma register-to- register operation.
scsi registers 4-71 registers: 0x3cC0x3f adder sum output (adder) read only adder adder sum output [31:0] this register contains the output of the internal adder, and is used primarily for test purposes. the power-up value for this register is indeterminate. register: 0x40 scsi interrupt enable zero (sien0) read/write this register contains the interrupt mask bits corresponding to the interrupting conditions described in the scsi interrupt status zero (sist0) register. an interrupt is masked by clearing the appropriate mask bit. for more information on interrupts see chapter 2, functional description. m/a scsi phase mismatch - initiator mode; scsi atn condition - target mode 7 in the initiator mode, this bit is set when the scsi phase asserted by the target and sampled during sreq/ does not match the expected phase in the scsi output control latch (socl) register. this expected phase is automatically written by scsi scripts. in the target mode, this bit is set when the initiator asserts satn/. see the disable halt on parity error or satn/ condition bit in the scsi control one (scntl1) register for more information on when this status is actually raised. cmp function complete 6 when set, this bit indicates the full arbitration and selection sequence is completed. 31 0 adder 00000000000000000000000000000000 76543210 m/a cmp sel rsl sge udc rst par 00000000
4-72 registers sel selected 5 when set, this bit indicates the lsi53c1010 scsi function is selected by a scsi initiator device. for this to occur, set the enable response to selection bit in the scsi chip id (scid) register. rsl reselected 4 when set, this bit indicates the lsi53c1010 scsi function is reselected by a scsi target device. for this to occur, set the enable response to reselection bit in the scsi chip id (scid) register. sge scsi gross error 3 the following conditions are considered scsi gross errors: offset under?ow occurs in target mode when a sack/ signal is received before the corresponding sreq/ signal has been sent. offset over?ow occurs in initiator mode when an sreq/ signal is received and causes the maximum offset, as de?ned by the mo[5:0] bits in the scsi transfer (sxfer) register, to be exceeded. in initiator mode, a phase change occurs with an outstanding sreq/sack offset. residual data in scsi fifo occurs when a transfer other than synchronous data received is started with data left in the scsi synchronous receive fifo. multiple crc requests occur when, during a synchronous dt transfer, multiple crc requests are received within the same offset. a request for a pad crc word is received without the subsequent crc word requests. a phase change occurs without a crc request. note: checking for this condition can be disabled by setting the discrc bit in the crc control zero (crccntl0) register. an illegal force crc request block move is executed. a scripts ram parity error occurs.
scsi registers 4-73 note: the shadowed scsi sge status 0 register indicates which condition caused an sce scsi interrupt. the register is shadowed behind the sist registers. it can be accessed by setting bit 4, the shadow register test mode (strm) bit, in the chip test four (ctest4) register. udc unexpected disconnect 2 this condition only occurs in the initiator mode. it happens when the target, which the lsi53c1010 scsi function is connected to, unexpectedly disconnects from the scsi bus. see the scsi disconnect unexpected bit in the scsi control two (scntl2) register for more information on expected versus unexpected disconnects. any disconnect in the low level mode causes this condition. rst scsi reset condition 1 indicates assertion of the srst/ signal by the lsi53c1010 scsi function or any other scsi device. this condition is edge-triggered, so multiple interrupts cannot occur because of a single srst/ pulse. par scsi parity/crc/aip error 0 this bit indicates the lsi53c1010 scsi function detected a parity/crc/aip error while receiving or sending scsi data. see the disable halt on parity/crc/aip error or satn/ condition bits in the scsi control one (scntl1) register for more information about when this condition is raised. register: 0x41 scsi interrupt enable one (sien1) read/write this register contains the interrupt mask bits corresponding to the interrupting conditions described in the scsi interrupt status one (sist1) register. an interrupt is masked by clearing the appropriate mask bit. for more information on interrupts refer to chapter 2, functional description. 7 543210 r sbmc r sto gen hth x x x0 x000
4-74 registers r reserved [7:5] sbmc scsi bus mode change 4 setting this bit allows the lsi53c1010 to generate an interrupt when the diffsens pin detects a change in voltage level that indicates the scsi bus has changed between se, lvd, or hvd modes. for example, when this bit is cleared and the scsi bus changes modes, irq/ does not assert and the sip bit in the interrupt status zero (istat0) register is not set. however, bit 4 in the scsi interrupt status one (sist1) register is set. setting this bit allows the interrupt to occur. r reserved 3 sto selection or reselection time-out 2 this bit is set when the scsi device which the lsi53c1010 scsi function is attempting to select or reselect does not respond within the programmed time-out period. see the description of the scsi timer zero (stime0) register, bits [3:0], for more information on the time-out timer. gen general purpose timer expired 1 this bit is set when the general purpose timer is expired. the time measured is the time between enabling and disabling of the timer. see the description of the scsi timer one (stime1) register, bits [3:0], for more information on the general purpose timer. hth handshake-to-handshake timer expired 0 this bit is set when the handshake-to-handshake timer is expired. the time measured is the scsi request-to- request (target) or acknowledge-to-acknowledge (initiator) period. see the description of the scsi timer zero (stime0) register, bits [7:4], for more information on the handshake-to-handshake timer.
scsi registers 4-75 register: 0x42 scsi interrupt status zero (sist0) read only reading the scsi interrupt status zero (sist0) register returns the status of the various interrupt conditions, whether they are enabled in the scsi interrupt enable zero (sien0) register or not. each bit set indicates occurrence of the corresponding condition. reading the sist0 clears the interrupt status. reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register because additional interrupts may be pending; the lsi53c1010 scsi functions stack interrupts. scsi interrupt conditions are individually masked through the scsi interrupt enable zero (sien0) register. when performing consecutive 8-bit reads of the dma status (dstat) , scsi interrupt status zero (sist0) , and scsi interrupt status one (sist1) registers (in any order), insert a delay equivalent to 12 clock periods between the reads to ensure the interrupts clear properly. also, if reading the registers when both the interrupt status zero (istat0) sip and dip bits may not be set, read the sist0 and sist1 registers before the dstat register to avoid missing a scsi interrupt. for more information on interrupts refer to chapter 2, functional description. m/a initiator mode: phase mismatch; target mode: satn/ active 7 in the initiator mode, this bit is set if the scsi phase asserted by the target does not match the instruction. the phase is sampled when sreq/ is asserted by the target. in the target mode, this bit is set when the satn/ signal is asserted by the initiator. cmp function complete 6 this bit is set when an arbitration only or full arbitration sequence is completed. 76543210 m/a cmp sel rsl sge udc rst par 00000000
4-76 registers sel selected 5 this bit is set when the lsi53c1010 scsi function is selected by another scsi device. for the lsi53c1010 scsi function to respond to selection attempts, the enable response to selection bit must be set in the scsi chip id (scid) register. the response id zero (respid0) and response id one (respid1) registers must hold the chips id. rsl reselected 4 this bit is set when the lsi53c1010 scsi function is reselected by another scsi device. the enable response to reselection bit must be set in the scsi chip id (scid) register (and the response id zero (respid0) and response id one (respid1) registers must hold the chips id) for the lsi53c1010 scsi function to respond to reselection attempts. sge scsi gross error 3 this bit is set when the lsi53c1010 scsi function encounters a scsi gross error condition. the following conditions can result in a scsi gross error: offset under?ow occurs in target mode when a sack/ signal is received before the corresponding sreq/ signal has been sent. offset over?ow occurs in initiator mode when an sreq/ signal is received and causes the maximum offset, as de?ned by the mo[5:0] bits in the scsi transfer (sxfer) register, to be exceeded. in initiator mode, a phase change occurs with an outstanding sreq/sack offset. residual data in scsi fifo occurs when a transfer other than synchronous data received is started with data left in the scsi synchronous receive fifo. multiple crc requests occur when, during a synchronous dt transfer, multiple crc requests are received within the same offset. a request for a pad crc word is received without the subsequent crc word requests.
scsi registers 4-77 a phase change occurs without a crc request. note: checking for this condition can be disabled by setting the dcrc bit in the crc control zero (crccntl0) register. an illegal force crc request block move is executed. a scripts ram parity error occurs. udc unexpected disconnect 2 this bit is set when the lsi53c1010 scsi function is operating in the initiator mode and the target device unexpectedly disconnects from the scsi bus. this bit is only valid when the lsi53c1010 scsi function operates in the initiator mode. when the scsi function operates in the low level mode, any disconnect causes an interrupt, even a valid scsi disconnect. this bit is also set if a selection time-out occurs. since a selection time-out is not considered an expected disconnect, an unexpected disconnect may occur before, at the same time, or stacked after the sto interrupt. rst scsi rst/ received 1 this bit is set when the lsi53c1010 scsi function detects an active srst/ signal, whether the reset is generated external to the chip or caused by the assert srst/ bit in the scsi control one (scntl1) register. this scsi reset detection logic is edge-sensitive, so that multiple interrupts are not generated for a single assertion of the srst/ signal. par parity/crc/aip error 0 this bit indicates the lsi53c1010 scsi function detected a parity/crc/aip error while receiving or sending scsi data. see the disable halt on parity/crc/aip error or atn/ condition bit in the scsi control one (scntl1) register for more information about when this condition will actually be raised.
4-78 registers register: 0x43 scsi interrupt status one (sist1) read only reading the sist1 register returns the status of the various interrupt conditions, whether they are enabled in the scsi interrupt enable one (sien1) register or not. each bit set indicates an occurrence of the corresponding condition. reading the sist1 clears the interrupt condition. r reserved [7:5] sbmc scsi bus mode change 4 this bit is set when the diffsens pin detects a change in voltage level indicating the scsi bus has switched between se, lvd, or hvd modes. r reserved 3 sto selection or reselection time-out 2 this bit is set when the scsi device which the lsi53c1010 scsi function is attempting to select or reselect does not respond within the programmed time-out period. see the description of the scsi timer zero (stime0) register, bits [3:0], for more information on the time-out timer. gen general purpose timer expired 1 this bit is set when the general purpose timer expires. the time measured is the time between enabling and disabling of the timer. see the description of the scsi timer one (stime1) register, bits [3:0], for more information on the general purpose timer. hth handshake-to-handshake timer expired 0 this bit is set when the handshake-to-handshake timer expires. the time measured is the scsi request-to- request (target) or acknowledge-to-acknowledge 7 543210 r sbmc r sto gen hth 0 0 00 0000
scsi registers 4-79 (initiator) period. see the description of the scsi timer zero (stime0) register, bits [7:4], for more information on the handshake-to-handshake timer. register: 0x44 reserved this register is reserved. register: 0x45 scsi wide residue (swide) read/write swide scsi wide residue [7:0] after an asynchronous wide scsi data receive operation, this register contains a residual data byte if the last byte received was never sent across the dma bus. it represents either the ?rst data byte of a subsequent data transfer, a residue byte which should be cleared when an ignore wide residue message is received, or an overrun data byte. the power-up value of this register is indeterminate. register: 0x46 reserved this register is reserved. 7 0 r x x x x x x x x 7 0 swide 00000000 7 0 r x x x x x x x x
4-80 registers register: 0x47 general purpose pin control (gpcntl) read/write this register is used to determine if the pins controlled by the general purpose (gpreg) register are inputs or outputs. bits [4:0] in gpcntl correspond to bits [4:0] in the gpreg register. when the bits are enabled as inputs, an internal pull-down is also enabled. me master enable 7 when the me bit is set, the bus master state of the device is presented on gpio1. gpio1 goes low when the part is a bus master. when set, the me bit is independent of the setting of bit 1 (gpio1). if the gpio1 is con?gured as an input while the me bit is set, the master bit will still toggle the gpio1 pin. fe fetch enable 6 if the fe bit is set, gpio0 re?ects when an internal opcode fetch is being performed. gpio0 goes low when an opcode fetch is performed. when set, the fe bit is independent of the setting of bit 0 (gpio0). if gpio0 is con?gured as an input, the fetch bit still toggles gpio0. ledc led_cntl 5 if the led_cntl bit is set gpio0 re?ects the state of the scsi bus, connected (low) or not connected (gpio0 high). this occurs if bit 6 (fe) is not set and the chip is not currently performing an eeprom autodownload. this bit provides a hardware solution for driving an external scsi activity led. gpio[4:2] gpio enable [4:2] the general purpose control corresponds to bits [4:2] in the general purpose (gpreg) register and to the gpio4Cgpio2 pins. gpio4 powers up as a general purpose output. gpio[3:2] power-up as general purpose inputs. 7654 210 me fe ledc gpio[4:2] gpio[1:0] 00x01111
scsi registers 4-81 gpio[1:0] gpio enable [1:0] these bits are set at power-up causing the gpio1 and gpio0 pins to become inputs. clearing these bits cause gpio[1:0] to become outputs. register: 0x48 scsi timer zero (stime0) read/write hth[3:0] handshake-to-handshake timer period [7:4] these bits select the handshake-to-handshake time-out period, which is the maximum time between scsi handshakes (sreq/ to sreq/ in target mode; or, sack/ to sack/ in initiator mode). when this timing is exceeded, an interrupt is generated and the hth bit in the scsi interrupt status one (sist1) register is set. the following table contains time-out periods for the handshake-to-handshake timer, the selection/ reselection timer (bits [3:0]), and the general purpose timer ( scsi timer one (stime1), bits [3:0]). for a more detailed explanation of interrupts, refer to chapter 2, functional description. 743 0 hth[3:0] sel[3:0] 00000000
4-82 registers sel[3:0] selection time-out [3:0] these bits select the scsi selection/reselection time-out period. when this timing (plus the 200 m s selection abort time) is exceeded, the sto bit in the scsi interrupt status one (sist1) register is set. for a more detailed explanation of interrupts, refer to chapter 2, functional description. register: 0x49 scsi timer one (stime1) read/write r reserved 7 hthba handshake-to-handshake timer bus activity enable 6 setting this bit causes this timer to begin testing for scsi req/ and ack/ activity as soon as sbsy/ is asserted, regardless of the agents participating in the transfer. hth [3:0], sel [3:0] minimum time-out 0000 disabled 0001 125 m s 0010 250 m s 0011 500 m s 0100 1 ms 0101 2 ms 0110 4 ms 0111 8 ms 1000 16 ms 1001 32 ms 1010 64 ms 1011 128 ms 1100 256 ms 1101 512 ms 1110 1.024 s 1111 2.048 s 76543 0 r hthba gensf hthsf gen[3:0] x0000000
scsi registers 4-83 gensf general purpose timer scale factor 5 setting this bit causes this timer to shift by a factor of 16. refer to the scsi timer zero (stime0) register description for details. hthsf handshake-to-handshake timer scale factor 4 setting this bit causes this timer to shift by a factor of 16. refer to the scsi timer zero (stime0) register description for details. gen[3:0] general purpose timer period [3:0] these bits select the period of the general purpose timer. the time measured is the time between enabling and disabling of the timer. when this timing is exceeded, the gen bit in the scsi interrupt status one (sist1) register is set. refer to the table under scsi timer zero (stime0) , bits [3:0], for the available time-out periods. note: to reset a timer before it expires and obtain repeatable delays, the time value must be written to zero ?rst, and then written back to the desired value. this is also required when changing from one time value to another. hth[3:0], sel[3:0], gen [3:0] minimum time-out hthsf = 0, gensf = 0 hthsf = 1, gensf = 1 0000 disabled disabled 0001 125 m s2ms 0010 250 m s4ms 0011 500 m s8ms 0100 1 m s16ms 0101 2 ms 32 ms 0110 4 ms 64 ms 0111 8 ms 128 ms 1000 16 ms 256 ms 1001 32 ms 512 ms 1010 64 ms 1 s 1011 128 ms 2 s 1100 256 ms 4.1 s 1101 512 ms 8.2 s 1110 1.024 s 16.4 s 1111 2.048 s 32.8 s
4-84 registers register: 0x4a response id zero (respid0) read/write respid0 response id zero [7:0] respid0 and response id one (respid1) contain the selection or reselection ids. these two 8-bit registers contain the scsi id that the chip responds to on the scsi bus. each bit represents one possible id; the most signi?cant bit of response id one (respid1) represents id 15, and the least signi?cant bit of respid0 represents id 0. the scsi chip id (scid) register still contains the chip id used during arbitration. the chip can respond to more than one id because more than one bit can be set in the respid1 and respid0 registers. however, the chip can arbitrate with only one id value in the scsi chip id (scid) register. register: 0x4b response id one (respid1) read/write respid1 response id one [7:0] response id zero (respid0) and respid1 contain the selection or reselection ids. these two 8-bit registers contain the scsi id that the chip responds to on the scsi bus. each bit represents one possible id; the most signi?cant bit of respid1 represents id 15, and the least signi?cant bit of respid0 represents id 0. the scsi chip id (scid) register still contains the chip id used during arbitration. the chip can respond to more than one id because more than one bit can be set in the respid1 and respid0 registers. however, the chip can arbitrate with only one id value in the scid register. 7 0 respid0 xxxxxxxx 7 0 respid1 xxxxxxxx
scsi registers 4-85 register: 0x4c scsi test zero (stest0) read only ssaid[3:0] scsi selected as id [7:4] these bits contain the encoded value of the scsi id that the lsi53c1010 scsi function is selected or reselected as during a scsi selection or reselection phase. these bits are read only and contain the encoded value of 16 possible ids that could be used to select the lsi53c1010 scsi function. during a scsi selection or reselection phase when a valid id is put on the bus, and the lsi53c1010 scsi function responds to that id, the selected as id is written into these bits. these bits are used with response id zero (respid0) and response id one (respid1) registers to allow response to multiple ids on the bus. slt selection response logic test 3 this bit is set when the lsi53c1010 scsi function is ready to be selected or reselected. this does not take into account the bus settle delay of 400 ns. this bit is used for functional test and fault purposes. art arbitration priority encoder test 2 this bit is always set when the lsi53c1010 scsi function exhibits the highest priority id asserted on the scsi bus during arbitration. it is primarily used for chip level testing. it may be used during low level mode operation to determine if the lsi53c1010 scsi function won arbitration. soz scsi synchronous offset zero 1 this bit indicates that the current synchronous sreq/, sack/ offset is zero. this bit is not latched and may change at any time. it is used in low level synchronous scsi operations. when this bit is set and if the lsi53c1010 is functioning as an initiator, the device is waiting for the target to request data transfers. when this 7 43210 ssaid[3:0] slt art soz som 00000x11
4-86 registers bit is set and if the lsi53c1010 is functioning as a target, then the initiator has sent the offset number of acknowledges. som scsi synchronous offset maximum 0 this bit indicates that the current synchronous sreq/, sack/ offset is the maximum speci?ed by bits [5:0] in the scsi transfer (sxfer) register. this bit is not latched and may change at any time. it is used in low level synchronous scsi operations. if this bit is set and if the lsi53c1010 is functioning as a target, it is waiting for the initiator to acknowledge the data transfers. if the lsi53c1010 scsi is functioning as an initiator, the target has sent the offset number of requests. register: 0x4d scsi test one (stest1) read/write r reserved [7:6] dosge disable outbound scsi gross errors 5 when set, this bit disables all scsi gross errors related to outbound data transfers. disge disable inbound scsi gross errors 4 when set, this bit disables all scsi gross errors related to inbound data transfers. qen sclk quadrupler enable 3 this bit, when set, powers up the internal clock quadrupler circuit, which quadruples the sclk 40 mhz clock to the internal 160 mhz scsi clock required for ultra2 and ultra160 scsi operation. when cleared, this bit powers down the internal quadrupler circuit. refer to chapter 2, functional description, for information concerning the operation of the quadrupler. 76543210 r dosge disge qen qsel irm[1:0] 0 0000000
scsi registers 4-87 qsel sclk quadrupler select 2 this bit, when set, selects the output of the internal clock quadrupler as the internal scsi clock. when cleared, this bit selects the clock presented on sclk as the internal scsi clock. refer to chapter 2, functional description, for information concerning the operation of the quadrupler. irm[1:0] interrupt routing mode [1:0] the lsi53c1010 supports four different interrupt routing modes. these modes are described in the following table. each scsi core within the chip can be con?gured independently. mode 0, the default mode, is compatible with raid upgrade products. mode bits [1:0] operation 0 00 if the int_dir/ input pin is low, interrupts are signaled on alt_intx/. otherwise, interrupts are signaled on both intx/ and alt_intx/. 1 01 interrupts are only signaled on intx/, not alt_intx/. the int_dir/ input pin is ignored. 2 10 interrupts are only signaled on alt_intx/. the int_dir/ input pin is ignored. 3 11 interrupts are signaled on both intx/ and alt_intx/. the int_dir input pin is ignored.
4-88 registers register: 0x4e scsi test two (stest2) read/write sce scsi control enable 7 setting this bit allows assertion of all scsi control and data lines through the scsi output control latch (socl) and scsi output data latch (sodl) registers regardless of whether the lsi53c1010 scsi function is con?gured as a target or initiator. note: do not set this bit during normal operation, since it could cause contention on the scsi bus. it is included for diagnostics purposes only. rof reset scsi offset 6 setting this bit clears any outstanding synchronous sreq/sack offset. if a scsi gross error occurs, set this bit. this bit automatically clears itself after resetting the synchronous offset. r reserved [5:4] szm scsi high impedance mode 3 setting this bit places all the open drain 48 ma scsi drivers into a high impedance state. r reserved [2:1] low scsi low level mode 0 setting this bit places the lsi53c1010 scsi function in the low level mode. in this mode, no dma operations occur and no scripts execute. arbitration and selection may be performed by setting the start sequence bit as described in the scsi control zero (scntl0) register. scsi bus transfers are performed by manually asserting and polling scsi signals. clearing this bit allows instructions to be executed in the scsi scripts mode. 76543210 sce rof r szm rlow 00 0 00 0 00
scsi registers 4-89 note: it is not necessary to set this bit for access to the scsi bit-level registers ( scsi output data latch (sodl) , scsi bus control lines (sbcl) , and input registers). register: 0x4f scsi test three (stest3) read/write te tolerant enable 7 setting this bit enables the active negation portion of lsi logic tolerant technology. active negation causes the scsi request, acknowledge, data, and parity signals to be actively deasserted, instead of relying on external pull-ups, when the lsi53c1010 scsi function is driving these signals. active deassertion of these signals occurs only when the lsi53c1010 scsi function is in an information transfer phase. when performing synchronous transfers, tolerant should be enabled to improve setup and deassertion times. active negation is disabled after reset or when this bit is cleared. for more information on lsi logic tolerant technology, see chapter 1, introduction. r reserved 6 hsc halt scsi clock 5 setting this bit causes the internal, divided scsi clock to come to a stop in a glitchless manner. this bit is used for test purposes or to lower i dd during a power-down mode. refer to chapter 2, functional description, for operation of the scsi clock quadrupler. dsi disable single initiator response 4 if this bit is set, the lsi53c1010 scsi function ignores all bus-initiated selection attempts that employ the single initiator option from scsi-1. in order to select the lsi53c1010 scsi function while this bit is set, the lsi53c1010 scsi functions scsi id and the initiators 76543210 te r hsc dsi r ttm csf r 0 000 000 0
4-90 registers scsi id must both be asserted. assert this bit in scsi-2 systems so that a single bit error on the scsi bus is not interpreted as a single initiator response. r reserved 3 ttm timer test mode 2 setting this bit facilitates testing of the selection time-out, general purpose, and handshake-to-handshake timers by greatly reducing all three time-out periods. setting this bit starts all three timers. if the respective bits in the scsi interrupt enable one (sien1) register are asserted, the lsi53c1010 scsi function generates interrupts at time-out. this bit is intended for internal manufacturing diagnosis and should not be used in normal operation. csf clear scsi fifo 1 setting this bit causes the full ?ags for the scsi fifo to be cleared. this empties the fifo. this bit is self-clearing. in addition to the scsi fifo pointers, the sidl, sodl, and sodr full bits in the scsi status zero (sstat0) and scsi status two (sstat2) are cleared. r reserved 0 registers: 0x50C0x51 scsi input data latch (sidl) read only sidl scsi input data latch [15:0] this register is used primarily for diagnostics testing, programmed i/o operation, or error recovery. asynchronous data received from the scsi bus can be read from this register. when receiving asynchronous scsi data, the data ?ows into this register and out to the host fifo. this register differs from the scsi bus data lines (sbdl) register; the scsi input data latch (sidl) contains latched data and the scsi bus data lines (sbdl) always contains exactly what is currently on the 15 0 sidl xxxxx x x x x xxx x xxx
scsi registers 4-91 scsi data bus. reading this register causes the scsi parity bit to be checked, and causes a parity error interrupt if the data is invalid. the power-up values are indeterminate. register: 0x52 scsi test four (stest4) read only smode[1:0] scsi mode [7:6] these bits contain the encoded value of the scsi operating mode that is indicated by the voltage level sensed at the diffsens pin. the incoming scsi signal goes to a pair of analog comparators that determine the voltage window of the diffsens signal. these voltage windows indicate lvd, se, or hvd operation. the bit values are de?ned in the following table. when the hvd mode is detected, all of the lsi53c1010 3-state outputs go to the high impedance state. r reserved [5:0] 765 0 smode[1:0] r xx 0 0 0 0 0 0 smode [1:0] operating mode 00 reserved 01 high impedance state 10 se 11 lvd scsi
4-92 registers register: 0x53 current inbound scsi offset (cso) read only r reserved [7:6] cso[5:0] current scsi offset [5:0] these bits indicate the scsi offset for synchronous inbound transfers. this also represents the number of data bytes in the scsi fifo in narrow transfer modes and half the number of bytes in wide transfer mode. this does not include any crc or pad bytes that may be in the fifo. registers: 0x54C0x55 scsi output data latch (sodl) read/write sodl scsi output data latch [15:0] this register is used primarily for diagnostics testing and programmed i/o operations. data written to this register is asserted on the scsi data bus by setting the assert data bus bit in the scsi control one (scntl1) register. this register is used to send data using programmed i/o. data ?ows through this register when sending data in asynchronous mode. it is also used to write to the synchronous data fifo when testing the chip. the power-up value of this register is indeterminate. 765 0 r cso[5:0] 0 0000000 15 0 sodl xxxxx x x x x xxx x xxx
scsi registers 4-93 register: 0x56 chip control zero (ccntl0) read/write enpmj enable phase mismatch jump 7 upon setting this bit, any phase mismatches do not interrupt but force a jump to an alternate location to handle the phase mismatch. prior to actually taking the jump, the appropriate remaining byte counts and addresses are calculated to facilitate storage. in the case of a scsi send, any data in the part is automatically cleared after being accounted for. in the case of a scsi receive, all data will be ?ushed out of the part and accounted for prior to taking the jump. this feature does not cover, however, the byte that may appear in scsi wide residue (swide) . this byte must be ?ushed manually. this bit also enables the ?ushing mechanism to ?ush data during a data-in phase mismatch in a more ef?cient manner. pmjctl jump control 6 this bit controls which decision mechanism is used when jumping on phase mismatch. when this bit is cleared the lsi53c1010 will use phase mismatch jump address one (pmjad1) when the wsr bit is cleared and phase mismatch jump address two (pmjad2) when the wsr bit is set. when this bit is set, the lsi53c1010 will use phase mismatch jump address one (pmjad1) on data-out (data-out, command, message-out) transfers and phase mismatch jump address two (pmjad2) on data-in (data-in, status, message-in) transfers. the phase referred to here is the phase encoded in the block move scripts instruction, not the phase on the scsi bus that caused the phase mismatch. enndj enable jump on nondata phase mismatches 5 this bit controls whether or not a jump is taken during a nondata phase mismatch (message-in, message-out, 76543210 enpmj pmjctl enndj disfc r disrc dpr 0000 x x00
4-94 registers status, or command). when this bit is cleared, jumps will only be taken on data-in or data-out phases, and a phase mismatch interrupt will be generated for all other phases. when this bit is set, jumps will be taken regardless of the phase in the block move. note that the phase referred to here is the phase encoded in the block move scripts instruction, not the phase on the scsi bus that caused the phase mismatch. disfc disable auto fifo clear 4 this bit controls whether or not the fifo is automatically cleared during a data-out phase mismatch. when set, data in the dma fifo and in the scsi output data latch (sodl) and sodr (a hidden buffer register which is not accessible) registers are not cleared after calculations on them are complete. when cleared, the dma fifo, sodl, and sodr are automatically cleared. this bit also disables the enhanced ?ushing mechanism. r reserved [3:2] disrc disable internal scripts ram cycles 1 this bit controls whether or not data transfers, for which the source/destination is located in scripts ram, generate external pci cycles. if cleared, data transfers of this type do not generate pci cycles and stay internal to the chip. if set, data transfers of this type generate pci cycles. this does not affect scripts fetch operations from scripts ram, including table indirect and indirect opcode fetches. dpr disable pipe req 0 this bit controls whether or not overlapped arbitration on the pci bus occurs. overlapped arbitration is performed by asserting pci req/ for one scsi function while the other scsi function is executing a pci cycle. if set, overlapped arbitration is disabled.
scsi registers 4-95 register: 0x57 chip control one (ccntl1) read/write pulldis pull disable 7 setting this bit causes all internal pulls to be disabled on all pins. this bit is intended for manufacturing test only and should not be set for normal operation. pulldis has precedence over pullen if both bits are set. pullen pull enable 6 setting this bit causes all internal pulls to be enabled on all pins. this bit is intended for manufacturing test only and should not be set for normal operation. dis64mas disable 64-bit master operation 5 setting this bit causes the lsi53c1010 to no longer request 64-bit master data transfers. if this bit is set by either scsi channel, 64-bit data transfers will be disabled for all master transactions. dis64slv disable 64-bit slave cycles 4 setting this bit disables 64-bit slave data transfers to the scripts ram. this causes only 32-bit data transfers to occur. ddac disable dual address cycle 3 when this bit is set, all 64-bit addressing as a master is disabled. no dual address cycles will be generated by the lsi53c1010. when this bit is cleared, the lsi53c1010 generates dual address cycles based on the master operation performed and the value of its associated selector register. 64timod 64-bit table indirect indexing mode 2 when this bit is cleared, bits [28:24] of the ?rst table entry dword will select one of 22 possible selectors to be used in a bmov operation. when this bit is set, bits [31:24] of the ?rst table entry dword will be copied directly into dma 76 5 432 1 0 pulldis pullen dis64mas dis64slv ddac 64timod en64tibmv en64dbmv 00 0 0xx 0 0
4-96 registers next address 64 (dnad64) to provide 40-bit addressing capability. this bit will only function if the en64tibmv bit is set. index mode 0 (64timod clear) table entry format: index mode 1 (64timod set) table entry format: en64tibmv enable 64-bit table indirect bmov 1 setting this bit enables 64-bit addressing for table indirect bmovs using the upper byte (bits [31:24]) of the ?rst dword of the table entry. when this bit is cleared, table indirect bmovs use the static block move selector (sbms) register to obtain the upper 32 bits of the data address. en64dbmv enable 64-bit direct bmov 0 setting this bit enables the 64-bit version of a direct bmov. when this bit is cleared, direct bmovs use the static block move selector (sbms) register to obtain the upper 32 bits of the data address. registers: 0x58C0x59 scsi bus data lines (sbdl) read only sbdl scsi bus data lines [15:0] this register contains the scsi data bus status. even though the scsi data bus is active low, these bits are active high. the signal status is not latched and is a true representation of exactly what is on the data bus at the [31:29] [28:24] [23:0] reserved sel index byte count source/destination address [31:0] [31:24] [23:0] src/dest addr [39:32] byte count source/destination address [31:0] 15 0 sbdl 0000 0 0 0 0 0 000 0 000
scsi registers 4-97 time the register is read. this register is used when receiving data using programmed i/o. this register can also be used for diagnostics testing or in the low level mode. the power-up value of this register is indeterminate. if the chip is in wide mode scsi control three (scntl3) , bit 3 is set) and scsi bus data lines (sbdl) is read, both byte lanes are checked for parity regardless of phase. when in a nondata phase, this will cause a parity error interrupt to be generated because the upper byte lane parity is invalid. register: 0x5a reserved this register is reserved. register: 0x5b chip control three (ccntl3) read/write r reserved [7:5] endskew enable req/ack to data skew control 4 setting this bit enables the control of the relative skew between the scsi req/ack signals and the data signals. the actual amount of skew time is controlled by dskew[1:0] in this register. dskew[1:0] data skew control [3:2] these bits control the amount of skew between the scsi req/ack signal and the scsi data signals. the skew is affected only if the endskew bit is set. 7 0 r x x x x x x x x 7543210 r endskew dskew[1:0] lvddl[1:0] 0 0 000000
4-98 registers note: these bits are used for ultra160 scsi domain validation only and should not be set during normal data transfer operations. lvddl[1:0] lvd drive strength select [1:0] these bits control the drive level of the lvd pad drivers. note: this feature is for ultra160 scsi domain validation testing environments only and should not be set during normal data transfer operations. the table below shows the relative strength increase or decrease based on the lvddl values. note: if one of the lvddl [1:0] bits are set on either channel, both channels are affected. registers: 0x5cC0x5f scratch register b (scratchb) read/write scratchb scratch register b [31:0] this is a general purpose user-de?nable scratch pad register. apart from cpu access, only register read/write and memory moves directed at the scratch register will alter its contents. the power-up values are indeterminate. a special mode of this register can be enabled by setting the pci con?guration info enable bit in the chip test two (ctest2) register. if this bit is set, bits [31:13] of the scratch register b (scratchb) register return bits [31:13] of the pci base address register three (bar3) (scripts ram) . in this mode, bits [12:0] of scratch b will always return zeros. lvddl drive level 00 nominal 01 - 20% nominal 10 +20% nominal 11 reserved 31 0 scratchb 00000000000000000000000000000000
scsi registers 4-99 writes to the scratch b register have no effect. resetting the pci con?guration info enable bit causes the scratch b register to return to normal operation. registers: 0x60C0x9f scratch registers cCr (scratchcCscratchr) read/write these are general purpose user-de?nable scratch pad registers. apart from cpu access, only register read/write, memory moves, and load/stores directed at a scratch register alter its contents. the power-up values are indeterminate. registers: 0xa0C0xa3 memory move read selector (mmrs) read/write mmrs memory move read selector [31:0] this register supplies ad[63:32] during data read operations for memory-to-memory moves and absolute address load operations. a special mode of this register can be enabled by setting the pci con?guration info enable bit in the chip test two (ctest2) register. if this bit is set, the memory move read selector (mmrs) register returns bits [31:0] of the memory mapped operating register, pci base address register two (bar2) (memory) , when read. in this mode, writes to the mmrs register have no effect. clearing the pci con?guration info enable bit causes the mmrs register to return to normal operation. 31 0 mmrs 00000000000000000000000000000000
4-100 registers registers: 0xa4C0xa7 memory move write selector (mmws) read/write mmws memory move write selector [31:0] this register supplies ad[63:32] during data write operations during memory-to-memory moves and absolute address store operations. a special mode of this register can be enabled by setting the pci con?guration info enable bit in the chip test two (ctest2) register. if this bit is set, the mmws register returns bits [31:0] of the scripts ram pci base address register four (bar4) (scripts ram) in bits [31:0] of the mmws register when read. in this mode, writes to the mmws register have no effect. clearing the pci con?guration info enable bit causes the mmws register to return to normal operation. registers: 0xa8C0xab script fetch selector (sfs) read/write sfs script fetch selector [31:0] this register supplies ad[63:32] during script fetches and indirect fetches (excluding table indirect fetches). this register can be loaded automatically using a 64-bit jump instruction. a special mode of this register can be enabled by setting the pci con?guration info enable bit in the chip test two (ctest2) register. if this bit is set, bits [16:23] of this register return the pci revision id (rid) register value and bits [0:15] return the pci device id register value when read. 31 0 mmws 00000000000000000000000000000000 31 0 sfs 00000000000000000000000000000000
scsi registers 4-101 writes to the script fetch selector (sfs) register are unaffected. clearing the pci con?guration info enable bit causes the sfs register to return to normal operation. registers: 0xacC0xaf dsa relative selector (drs) read/write drs dsa relative selector [31:0] this register supplies ad[63:32] during table indirect fetches and load/store data structure address (dsa) relative operations. registers: 0xb0C0xb3 static block move selector (sbms) read/write sbms static block move selector [31:0] this register supplies ad[63:32] during block move operations, reads, or writes. this register is static and is not changed when a 64-bit direct bmov is used. 31 0 drs 00000000000000000000000000000000 31 0 sbms 00000000000000000000000000000000
4-102 registers registers: 0xb4C0xb7 dynamic block move selector (dbms) read/write dbms dynamic block move selector [31:0] this register supplies ad[63:32] during block move operations, reads, or writes. this register is used only during 64-bit direct bmov instructions. it is reloaded with the upper 32 bit data address upon execution of 64-bit direct bmovs. registers: 0xb8C0xbb dma next address 64 (dnad64) read/write dnad64 dma next address 64 [31:0] this register holds the current selector being used in a host transaction. the appropriate selector is copied to this register prior to beginning the host transaction. note: the crossing of selector boundaries in one memory operation is not supported. register: 0xbc scsi control four (scntl4) read/write this register is automatically loaded when a table indirect select or reselect scripts instruction is executed. 31 0 dbms 00000000000000000000000000000000 31 0 dnad64 00000000000000000000000000000000 76543210 u3en aipen r xclkh_dt xclkh_st xclks_dt xclks_st 00 0 00 0 0 0
scsi registers 4-103 u3en ultra160 transfer enable 7 setting this bit enables ultra160 transfers. this bit will force all scsi block move scripts instructions for st data-in or st data-out phases to become dt data-in or dt data-out phases. aipen asynchronous information protection enable 6 setting this bit enables the aip checking and generation of the upper byte lane of protection information during command, status, and message phases. r reserved [5:4] xclkh_dt extra clock of data hold on dt transfer edge 3 setting this bit adds a clock of data hold to synchronous dt scsi transfers on the dt edge. this bit only impacts dt transfers as it affects data hold to the dt edge. setting this bit reduces the synchronous transfer send rate but does not reduce the transfer rate at which the lsi53c1010 can receive inbound reqs, acks or data. refer to table 4.4 and table 4.5 for a summary of available transfer rates and to figure 4.1 through figure 4.3 for examples of how the xclkh bits function. note: this bit does not affect crc timings. xclkh_st extra clock of data hold on st transfer edge 2 setting this bit adds a clock of data hold to synchronous dt or st scsi transfers on the st edge. this bit impacts both st and dt transfers as it affects data hold to the st edge. setting this bit reduces the synchronous send transfer rate but does not reduce the transfer rate at which the lsi53c1010 can receive inbound reqs, acks or data. refer to table 4.4 and table 4.5 for a summary of available transfer rates and to figure 4.1 through figure 4.3 for examples of how the xclkh bits function. note: this bit does not affect crc timings. xclks_dt extra clock of data setup on dt transfer edge 1 setting this bit adds a clock of data setup to synchronous dt scsi transfers on the dt edge. this bit only impacts dt transfers as it only affects data setup to the dt edge. setting this bit reduces the synchronous transfer send rate but does not reduce the transfer rate at which the lsi53c1010 can receive inbound reqs, acks or data.
4-104 registers refer to table 4.4 and table 4.5 for a summary of available transfer rates and to figure 4.1 through figure 4.3 for examples of how the xclks bits function. note: this bit does not affect crc timings. xclks_st extra clock of data setup on st transfer edge 0 setting this bit adds a clock of data setup to synchronous dt or st scsi transfers on the st edge. this bit impacts both st and dt transfers as it affects data setup to the st edge. setting this bit reduces the synchronous send transfer rate but does not reduce the transfer rate at which the lsi53c1010 can receive inbound reqs, acks or data. refer to table 4.4 and table 4.5 for a summary of available transfer rates and to figure 4.1 through figure 4.3 for examples of how the xclks bits function. note: this bit does not affect crc timings. synchronous receive rate calculation the synchronous receive rate, in megatransfers/s, can be calculated using the following formulas: note: the receive rate is independent of the settings of the xclks_dt, xclks_st, xclkh_dt, and xclkh_st bits. synchronous send rate calculation the synchronous send rate, in megatransfers/s, can be calculated using the following formula: receive rate (dt) input clock rate scf divisor 2 ------------------------------------------- - = receive rate (st) input clock rate scf divisor 4 ------------------------------------------- - = send rate (dt) input clock rate scfdivisor 2 xclks_dt xclks_st+xclkh_dt+xclkh_st + 2 ------------------------------------------------------------------------------------------------------------------------------- ----------- ) + () ? ------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------ = send rate (st) input clock rate scfdivisor 4 xclks_st xclkh_st + ) + () ( ------------------------------------------------------------------------------------------------------------------------------- --- - =
scsi registers 4-105 figure 4.1 single transition transfer waveforms clk 1 req/ack data xclks_st = 0 xclkh_st = 0 clk 1 req/ack data xclks_st = 1 xclkh_st = 0 clk 1 req/ack data xclks_st = 0 xclkh_st = 1 clk 1 req/ack data xclks_st = 1 xclkh_st = 1 1. clk = sclk/scf divisor
4-106 registers figure 4.2 double transition transfer waveforms (xclks examples) ) clk 1 req/ack data clk 1 req/ack data clk 1 req/ack data clk 1 req/ack data xclks_dt = 1/xclks_st = 1 xclkh_dt = 0/xclkh_st = 0 1. clk = sclk/scf divisor xclks_dt = 1/xclks_st = 0 xclkh_dt = 0/xclkh_st = 0 xclks_dt = 0/xclks_st = 1 xclkh_dt = 0/xclkh_st = 0 xclks_dt = 0/xclks_st = 0 xclkh_dt = 0/xclkh_st = 0
scsi registers 4-107 figure 4.3 double transition transfer waveforms (xclkh examples) clk 1 req/ack data clk 1 req/ack data clk 1 req/ack data clk 1 req/ack data xclks_dt = 1 / xclks_st = 1 xclkh_dt = 1 / xclkh_st = 1 1. clk = sclk/scf divisor xclks_dt = 0 / xclks_st = 0 xclkh_dt = 1 / xclkh_st = 1 xclks_dt = 0 / xclks_st = 0 xclkh_dt = 0 / xclkh_st = 1 xclks_dt = 0 / xclks_st = 0 xclkh_dt = 1 / xclkh_st = 0
4-108 registers table 4.4 double transition transfer rates clock (mhz) divisor number xclks 1 base period (ns) receive rate (megatransfers/s) send rate (megatransfers/s) 160 1 0 6.25 80.00 80.00 160 1 1 6.25 80.00 64.00 160 1 2 6.25 80.00 53.33 160 1 3 6.25 80.00 45.71 160 1 4 6.25 80.00 40.00 160 1.5 0 9.38 53.33 53.33 160 1.5 1 9.38 53.33 42.67 160 1.5 2 9.38 53.33 35.56 160 1.5 3 9.38 53.33 30.48 160 1.5 4 9.38 53.33 26.67 160 2 0 12.50 40.00 40.00 160 2 1 12.50 40.00 32.00 160 2 2 12.50 40.00 26.67 160 2 3 12.50 40.00 22.86 160 2 4 12.50 40.00 20.00 160 3 0 18.75 26.67 26.67 160 3 1 18.75 26.67 21.33 160 3 2 18.75 26.67 17.78 160 3 3 18.75 26.67 15.24 160 3 4 18.75 26.67 13.33 160 4 0 25.00 20.00 20.00 160 4 1 25.00 20.00 16.00 160 4 2 25.00 20.00 13.33 160 4 3 25.00 20.00 11.43 160 4 4 25.00 20.00 10.00 160 6 0 37.50 13.33 13.33 160 6 1 37.50 13.33 10.67 160 6 2 37.50 13.33 8.89 160 6 3 37.50 13.33 7.62 160 6 4 37.50 13.33 6.67 160 8 0 50.00 10.00 10.00 160 8 1 50.00 10.00 8.00 160 8 2 50.00 10.00 6.67 160 8 3 50.00 10.00 5.71 160 8 4 50.00 10.00 5.00 40 1 0 25.00 20.00 20.00 40 1 1 25.00 20.00 16.00 40 1 2 25.00 20.00 13.33 40 1 3 25.00 20.00 11.43 40 1 4 25.00 20.00 10.00
scsi registers 4-109 40 1.5 0 37.50 13.33 13.33 40 1.5 1 37.50 13.33 10.67 40 1.5 2 37.50 13.33 8.89 40 1.5 3 37.50 13.33 7.62 40 1.5 4 37.50 13.33 6.67 40 2 0 50.00 10.00 10.00 40 2 1 50.00 10.00 8.00 40 2 2 50.00 10.00 6.67 40 2 3 50.00 10.00 5.71 40 2 4 50.00 10.00 5.00 40 3 0 75.00 6.67 6.67 40 3 1 75.00 6.67 5.33 40 3 2 75.00 6.67 4.44 40 3 3 75.00 6.67 3.81 40 3 4 75.00 6.67 3.33 40 4 0 100.00 5.00 5.00 40 4 1 100.00 5.00 4.00 40 4 2 100.00 5.00 3.33 40 4 3 100.00 5.00 2.86 40 4 4 100.00 5.00 2.50 40 8 0 200.00 2.50 2.50 40 8 1 200.00 2.50 2.00 40 8 2 200.00 2.50 1.67 40 8 3 200.00 2.50 1.43 40 8 4 200.00 2.50 1.25 1. number xclks = xclks_dt + xclks_st + xclkh_dt + xclkh_st table 4.4 double transition transfer rates (cont.) clock (mhz) divisor number xclks 1 base period (ns) receive rate (megatransfers/s) send rate (megatransfers/s)
4-110 registers table 4.5 single transition transfer rates clock (mhz) divisor number xclks 1 base period (ns) receive rate (megatransfers/s) send rate (megatransfers/s) 160 1 0 6.25 40.00 40.00 160 1 1 6.25 40.00 32.00 160 1 2 6.25 40.00 26.67 160 1.5 0 9.38 26.67 26.67 160 1.5 1 9.38 26.67 21.33 160 1.5 2 9.38 26.67 17.78 160 2 0 12.50 20.00 20.00 160 2 1 12.50 20.00 16.00 160 2 2 12.50 20.00 13.33 160 3 0 18.75 13.33 13.33 160 3 1 18.75 13.33 10.67 160 3 2 18.75 13.33 8.89 160 4 0 25.00 10.00 10.00 160 4 1 25.00 10.00 8.00 160 4 2 25.00 10.00 6.67 160 6 0 37.50 6.67 6.67 160 6 1 37.50 6.67 5.33 160 6 2 37.50 6.67 4.44 160 8 0 50.00 5.00 5.00 160 8 1 50.00 5.00 4.00 160 8 2 50.00 5.00 3.33 40 1 0 25.00 10.00 10.00 40 1 1 25.00 10.00 8.00 40 1 2 25.00 10.00 6.67 40 1.5 0 37.50 6.67 6.67 40 1.5 1 37.50 6.67 5.33 40 1.5 2 37.50 6.67 4.44 40 2 0 50.00 5.00 5.00 40 2 1 50.00 5.00 4.00 40 2 2 50.00 5.00 3.33 40 3 0 75.00 3.33 3.33 40 3 1 75.00 3.33 2.67 40 3 2 75.00 3.33 2.22 40 4 0 100.00 2.50 2.50 40 4 1 100.00 2.50 2.00 40 4 2 100.00 2.50 1.67
scsi registers 4-111 register: 0xbd reserved this register is reserved. register: 0xbe aip control zero (aipcntl0) read/write fbaip force bad aip value 7 setting this bit causes bad aip values to be sent over the scsi bus. rsqaip reset aip sequence value 6 setting this bit causes the sequence value used in the calculation of the protection code to reset. seqaip aip sequence value [5:4] these two bits contain the current aip sequence value. the seqaip bits are read only and should only be accessed for diagnostics purposes. the sequence value is automatically reset on every phase change. 40 6 0 150.00 1.67 1.67 40 6 1 150.00 1.67 1.33 40 6 2 150.00 1.67 1.11 40 8 0 200.00 1.25 1.25 40 8 1 200.00 1.25 1.00 40 8 2 200.00 1.25 0.83 1. number xclks = xclks_st + xclkh_st 7 0 r x x x x x x x x 76543 0 fbaip rsqaip seqaip r 00 0 0 0 0 0 table 4.5 single transition transfer rates (cont.) clock (mhz) divisor number xclks 1 base period (ns) receive rate (megatransfers/s) send rate (megatransfers/s)
4-112 registers r reserved [3:0] register: 0xbf aip control one (aipcntl1) read/write aiperr aip error status 7 this bit represents the live value of the error status for the aip checking logic. this bit may indicate false errors and should not be used except for diagnostics purposes. raiper latched aip error status 6 this bit represents the latched version of the error status for the aip checking logic. this bit accurately re?ects the fact that an aip error was detected. this bit will be cleared when the parity/crc/aip error bit is cleared in the scsi interrupt status zero (sist0) register. aipv aip value [5:0] this value represents the current calculated value of the protection code. this value is based off of the eight scsi data bits, the three phase signals, the two scsi reserved signals, and the sequence value. registers: 0xc0C0xc3 phase mismatch jump address one (pmjad1) read/write pmjad1 phase mismatch jump address one [31:0] this register contains the 32-bit address that is jumped to upon a phase mismatch. depending upon the state of the pmjctl bit, this address is either used during an outbound (data-out, command, message-out) phase mismatch (pmjctl = 0) or when the wsr bit is cleared (pmjctl = 1). this register is loaded with the address of 765 0 aiperr rapier aipv 00000000 31 0 pmjad1 00000000000000000000000000000000
scsi registers 4-113 a scripts routine that updates the memory data structures of the bmov that was executing when the phase mismatch occurred. registers: 0xc4C0xc7 phase mismatch jump address two (pmjad2) read/write pmjad2 phase mismatch jump address two [31:0] this register contains the 32-bit address that is jumped to upon a phase mismatch. depending upon the state of the pmjctl bit, this address is either used during an inbound (data-in, status, message-in) phase mismatch (pmjctl = 0) or when the wsr bit is set (pmjctl = 1). this register is loaded with the address of a scripts routine that updates the memory data structures of the bmov that was executing when the phase mismatch occurred. registers: 0xc8C0xcb remaining byte count (rbc) read/write rbc remaining byte count [31:0] this register contains the byte count that remains for the bmov that was executing when the phase mismatch occurred. in the case of direct or indirect bmov instructions, the upper byte of this register also contains the opcode of the bmov that was executing. in the case of a table indirect bmov instruction, the upper byte contains the upper byte of the table indirect entry that was fetched. 31 0 pmjad2 00000000000000000000000000000000 31 0 rbc 00000000000000000000000000000000
4-114 registers in the case of a scsi data receive, this byte count re?ects all data received from the scsi bus, including any byte in scsi wide residue (swide) . there is no data remaining in the part that must be ?ushed to memory with the exception of a possible byte in the swide register. that byte must be ?ushed to memory manually in scripts. in the case of a scsi data send, this byte count re?ects all data sent out onto the scsi bus. any data left in the part from the phase mismatch is ignored and automatically cleared from the fifos. registers: 0xccC0xcf updated address (ua) read/write ua updated address [31:0] this register contains the updated data address for the bmov that was executing when the phase mismatch occurred. in the case of a scsi data receive, if there is a byte in the scsi wide residue (swide) register then this address points to the location where that byte must be stored. the swide byte must be manually written to memory and this address must be incremented prior to updating any scatter/gather entry. in the case of a scsi data receive, if there is not a byte in the swide register then this address is the next location that should be written to when this i/o restarts. no manual ?ushing will be necessary. in the case of a scsi data send, all data sent to the scsi bus will be accounted for and any data left in the part is ignored and is automatically cleared from the fifos. 31 0 ua 00000000000000000000000000000000
scsi registers 4-115 registers: 0xd0C0xd3 entry storage address (esa) read/write esa entry storage address [31:0] this register's value depends on the type of bmov being executed. the three types of bmovs are: registers: 0xd4C0xd7 instruction address (ia) read/write ia instruction address [31:0] this register always contains the address of the bmov instruction that was executing when the phase mismatch occurred. this value will always match the value in the entry storage address (esa) except in the case of a table indirect bmov in which case the esa will have the address of the table indirect entry and this register points to the address of the bmov instruction. 31 0 esa 00000000000000000000000000000000 direct bmov: in the case of a direct bmov, this register contains the address the bmov was fetched from when the phase mismatch occurred. indirect bmov: in the case of an indirect bmov, this register contains the address the bmov was fetched from when the phase mismatch occurred. table indirect bmov: in the case of a table indirect bmov, this register contains the address of the table indirect entry being used when the phase mismatch occurred. 31 0 ia 00000000000000000000000000000000
4-116 registers registers: 0xd8C0xda scsi byte count (sbc) read only sbc scsi byte count [23:0] this register contains the count of the number of bytes transferred to or from the scsi bus during any given bmov. this value is used in calculating the information placed into the remaining byte count (rbc) and updated address (ua) registers and should not need to be used in normal operations. there are several conditions for which the byte count does not match the number of bytes transferred. if a bmov transfers an odd number of bytes across a wide bus, the byte count at the end of the bmov is one byte greater than the number of bytes sent. this also occurs in an odd byte count wide receive case. lastly, when a wide send occurs and a chain byte from a previous transfer is present, the byte count does not re?ect the chain byte sent across the bus during that bmov. to determine the correct address to start fetching data from after a phase mismatch, this byte is not counted for this bmov. it is included in the previous bmovs byte count. register: 0xdb reserved this register is reserved. 23 0 sbc 000000000000000000000000 7 0 r x x x x x x x x
scsi registers 4-117 registers: 0xdcC0xdf cumulative scsi byte count (csbc) read/write csbc cumulative scsi byte count [31:0] this loadable register contains a cumulative count of the number of bytes transferred across the scsi bus during data phases. it does not count bytes sent in command, status, message-in or message-out phases. it counts bytes as long as the phase mismatch enable bit (enpmj) in the chip control zero (ccntl0) register is set. unlike the scsi byte count (sbc) , this count is not cleared on each bmov instruction but continues to count across multiple bmov instructions. this register can be loaded with any arbitrary start value. registers: 0xe0C0xe1 crc pad byte value (crcpad) read/write crcpbv crc pad byte value [15:0] this register contains the value placed onto the bus for the crc pad bytes. 31 0 csbc 00000000000000000000000000000000 15 0 crcpbv 0000000000000000
4-118 registers register: 0xe2 crc control zero (crccntl0) read/write dcrcc disable crc checking 7 setting this bit causes the internal logic not to check or report crc errors during ultra160 transfers. the lsi53c1010 continues to calculate and send crcs as requested by the target according to the spi-3 speci?cation. dcrcpc disable crc protocol checking 6 setting this bit causes the internal logic to not check or report crc protocol errors during ultra160 transfers. the lsi53c1010 continues to calculate and send crcs as requested by the target according to the spi-3 speci?cation but does not set a sge interrupt if a crc protocol error occurs. this bit should not be set in normal operation. rcrcic reset crc interval counter (target mode only) 5 setting this bit resets the internal crc interval counter to zero. this bit is not self-clearing. r reserved 4 crcri[3:0] crc request interval (target mode only) [3:0] these bits determine when a crc request is to be sent by the device when operating in the target mode and transferring data in the dt data-in or dt data-out phases. the interval is independent of individual block moves, allowing consistent crc requests across multiple block moves of varying byte counts as in scatter/gather types of operations. the following table de?nes the valid crc request intervals. a setting of zero will disable the automatic crc request interval and the device will not request a crc at any time. the spi-3 speci?cation states that all dt data-in and dt data-out phases must end with a crc transfer. thus, to maintain compliance 76543 0 dcrcc dcrcpc rcrcic r crcri[3:0] 000 00000
scsi registers 4-119 with the spi-3 speci?cation it is necessary to manually request a crc by executing a force crc block move instruction. register: 0xe3 crc control one (crccntl1) read/write crcerr crc error 7 this bit indicates whether or not a crc error has been detected during a dt data-in scsi transfer. this bit is set independent of the dcrcc bit. to clear this condition, either write this bit t oa1or read the scsi interrupt sta- tus zero (sist0) and scsi interrupt status one (sist1) registers. when crc checking and the parity/crc/aip error interrupt are enabled, this error condition is also indicated as a parity/crc/aip error (bit 0 of the sist0 register). crcri interval (bytes) 0x0 disabled 0x1 128 0x2 256 0x3 512 0x4 1024 0x5 2048 0x6 4096 0x7 8192 0x8 16384 0x9 32768 0xa 65536 0xb reserved 0xc reserved 0xd reserved 0xe reserved 0xf reserved 76543210 crcerr r enas tstsd tstchk tstadd crcdsel 0 0000000
4-120 registers r reserved 6 enas enable crc auto seed 5 setting this bit causes the crc logic to automatically reseed after every crc check performed during dt data-in scsi transfers. when this bit is cleared, the scsi control logic controls when the reseeding occurs. tstsd test crc seed 4 setting this bit causes the crc logic to immediately reseed itself. this bit should never be set during normal operation as it may cause corrupt crcs to be generated. tstchk test crc check 3 setting this bit causes the crc logic to initiate a crc check. this bit should never be set during normal operation as it results in spurious crc errors. tstadd test crc accumulate 2 setting this bit causes the crc block to take the value in its input register and add it into the current crc calculation, resulting in a new output crc value. this bit should not be set during normal operation as it results in corrupt crc values. crcdsel crc data register selector [1:0] these bits control the data that is visible in the crc data (crcd) register. registers: 0xe4C0xe7 crc data (crcd) read/write the value in this register is dependent on the setting of the crcdsel bits in the crc control one (crccntl1) register. note: data written to this register may not be available for immediate read back due to synchronization between the pci and scsi clock domains. after a write, wait at least 16 pci clock cycles before reading this register. 31 0 crcd xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
scsi registers 4-121 crcd crc data [31:0] if crcdsel = 0b00, this register represents the current crc value. after sending data during the dt data-out phase, this register contains the crc calculation for that data, if no crc request occurred during the transfer. in this mode, this register is read only. if crcdsel = 0b01, this register represents the crc input register and contains its current value. it normally contains the scsi data transferred to or from the scsi bus during a dt transfer phase. in this mode, this register can be written to in order to manually alter the input data used for crc calculation. for normal operations, this register should never be written to. if crcdsel = 0b10, this register represents the crc accumulator and contains its current value. in this mode, this register can be written to in order to manually modify the value in the accumulator. this register should not be written to during normal operation as corrupt crc values result. if crcdsel = 0b11, this register contains the saved bad crc value that was calculated when a crc error was detected. after a crc error is detected, this register is not overwritten until the error condition is cleared. registers: 0xe8C0xef reserved this register is reserved. 31 0 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4-122 registers registers: 0xf0C0xf1 dma fifo byte count (dfbc) read only dfbc dma fifo byte count [15:0] this 16-bit read only register contains the actual number of bytes contained in the dma fifo. this register is not stable while data is actually being transferred. this register can be used during error recovery. registers: 0xf2C0xf3 reserved this register is reserved. registers: 0xf4C0xff reserved this register is reserved. 15 0 dfbc xxxxxxxxxxxxxxxx 15 0 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 0 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
scsi shadow registers 4-123 4.3 scsi shadow registers note: for more information concerning shadow registers, refer to the chip test four (ctest4) , scratch register a (scratcha) , scratch register b (scratchb) , memory move read selector (mmrs) , memory move write selec- tor (mmws) , and script fetch selector (sfs) register descriptions. registers: 0x34C0x37 shadowed scratch register a (scratcha) read/write scratcha scratch register a [31:0] register: 0x42 shadowed scsi sge status 0 read/write this register contains the individual status bits which cause a sge scsi interrupt. these bits correspond to the sge conditions described in the scsi interrupt status zero (sist0) register description. unlike the other registers in the device, these bits must be set to one to clear the condition. this register is shadowed behind the sist registers. setting bit 4 (srtm) in the chip test four (ctest4) register, enables access to this register. srp scripts ram parity 7 dfp dma fifo parity 6 rd residual data in scsi fifo 5 31 0 scratcha 00000000000000000000000000000000 76543210 srp dfp rd pco oo ou do du 0 0000000
4-124 registers pco phase change with outstanding offset 4 oo offset over?ow 3 ou offset under?ow 2 do data over?ow 1 du data under?ow 0 register: 0x43 shadowed scsi interrupt status one (sist1) read only this register contains the individual status bits which cause a sge scsi interrupt. these bits correspond to the sge conditions described in the scsi interrupt status zero (sist0) register description. unlike the other registers in the device, these bits must be set to one to clear the condition. this register is shadowed behind the sist registers. setting bit 4 (srtm) in the chip test four (ctest4) register, enables access to this register. r reserved [7:6] pncrc pad request with no crc request following 5 fcrc force crc 4 dtst switch from dt to st timings during a transfer 3 nfcrc phase change with no final crc request 2 mcrc multiple crc requests with the same offset 1 r reserved 0 76543210 r pncrc fcrc dtst nfcrc mcrc r 0 000000 0
scsi shadow registers 4-125 registers: 0x5cC0x5f shadowed scratch register b (scratchb) read/write scratchb scratch register b [31:0] registers: 0x60C0x9f shadowed scratch registers cCr (scratchcCscratchr) read/write these are general purpose user-de?nable shadows of the scratch pad registers. registers: 0xa0C0xa3 shadowed memory move read selector (mmrs) read/write mmrs shadowed memory move read selector [31:0] 31 0 scratchb 00000000000000000000000000000000 31 0 mmrs 00000000000000000000000000000000
4-126 registers registers: 0xa4C0xa7 shadowed memory move write selector (mmws) read/write mmws shadowed memory move write selector [31:0] registers: 0xa8C0xab shadowed script fetch selector (sfs) read/write sfs shadowed script fetch selector [31:0] 31 0 mmws 00000000000000000000000000000000 31 0 sfs 00000000000000000000000000000000
LSI53C1010-33 pci to dual channel ultra160 scsi multifunction controller 5-1 chapter 5 scsi scripts instruction set after power-up and initialization, the LSI53C1010-33 can operate in the low level register interface mode, or use scsi scripts. with the low level register interface, the user has access to the dma control logic and the scsi bus control logic. an external processor has access to the scsi bus signals and the low level dma signals, which allow creation of complicated board level test algorithms. the low level interface is useful for backward compatibility with scsi devices that require certain unique timings or bus sequences to operate properly. the following sections describe the bene?ts and use of scsi scripts. section 5.1, scsi scripts section 5.2, block move instructions section 5.3, i/o instructions section 5.4, read/write instructions section 5.5, transfer control instructions section 5.6, memory move instructions section 5.7, load and store instructions 5.1 scsi scripts to operate in the scsi scripts mode, the LSI53C1010-33 requires only a scripts start address. the start address must be at a dword (four byte) boundary. this aligns all the following scripts at a dword boundary since all scripts are 8 or 12 bytes long. instructions are fetched until an interrupt instruction is encountered, or until an unexpected event (such as a hardware error) causes an interrupt to the external processor.
5-2 scsi scripts instruction set once an interrupt is generated, the LSI53C1010-33 halts all operations until the interrupt is serviced. then, the start address of the next scripts instruction is written to the dma scripts pointer (dsp) register to restart the automatic fetching and execution of instructions. in the scsi scripts mode the LSI53C1010-33 is allowed to make decisions based on the status of the scsi bus, which frees the microprocessor from servicing the numerous interrupts inherent in i/o operations. given the rich set of scsi-oriented features included in the instruction set, and the ability to re-enter the scsi algorithm at any point, this high level interface is all that is required for both normal and exception conditions. switching to the low level mode for error recovery is not required. the following types of scripts instructions are implemented in the LSI53C1010-33: block move C used to move data between the scsi bus and memory. i/o or read/write C causes the LSI53C1010-33 to trigger common scsi hardware sequences, or to move registers. transfer control C allows scripts instructions to make decisions based on real time scsi bus conditions. memory move C causes the LSI53C1010-33 to execute block moves between different parts of main memory. load/store C provides a more ef?cient way to move data to/from memory from/to an internal register in the chip without using the memory move instruction. each instruction consists of two or three 32-bit words. the ?rst 32-bit word is always loaded into the dma command (dcmd) and dma byte counter (dbc) registers, the second into the dma scripts pointer save (dsps) register. the third word, used only by memory move instructions, is loaded into the temporary (temp) shadow register. in an indirect i/o or move instruction, the ?rst two 32-bit opcode fetches are followed by one or two more 32-bit fetch cycles.
scsi scripts 5-3 5.1.1 sample operation the following example describes execution of a scripts block move instruction. the host cpu, through programmed i/o, gives the dma scripts pointer (dsp) register (in the operating register ?le) the starting address in main memory that points to a scsi scripts program for execution. loading the dma scripts pointer (dsp) register causes the LSI53C1010-33 to fetch its ?rst instruction at the address just loaded. this fetch is from main memory or the internal ram, depending on the address. the LSI53C1010-33 typically fetches two dwords (64 bits) and decodes the high-order byte of the ?rst dword as a scripts instruction. if the instruction is a block move, the lower three bytes of the ?rst dword are stored and interpreted as the number of bytes to move. the second dword is stored and interpreted as the 32-bit beginning address in main memory to which the move is directed. for a scsi send operation, the LSI53C1010-33 waits until there is enough space in the dma fifo to transfer a programmable size block of data. for a scsi receive operation, it waits until enough data is collected in the dma fifo for transfer to memory. at this point, the LSI53C1010-33 requests use of the pci bus again to transfer the data. when the LSI53C1010-33 is granted the pci bus, it executes (as a bus master) a burst transfer (programmable size) of data, decrements the internally stored remaining byte count, increments the address pointer, and then releases the pci bus. the LSI53C1010-33 stays off the pci bus until the fifo can again hold (for a write) or has collected (for a read) enough data to repeat the process. the process repeats until the internally stored byte count has reached zero. the LSI53C1010-33 releases the pci bus and then performs another scripts instruction fetch cycle, using the incremented stored address maintained in the dma scripts pointer (dsp) register. execution of scripts instructions continues until an error condition occurs or an interrupt scripts instruction is received. at this point, the LSI53C1010-33 interrupts the host cpu and waits for further servicing
5-4 scsi scripts instruction set by the host system. it can execute independent block move instructions specifying new byte counts and starting locations in main memory. in this manner, the LSI53C1010-33 performs scatter/gather operations on data without requiring help from the host program, generating a host interrupt, or programming of an external dma controller. figure 5.1 provides an overview of scripts operation. figure 5.1 scripts overview system processor system memory (or internal ram) scsi initiator write example select atn0, alt_addr move 1, identify_msg_buf, when msg_out move 6, cmd_buf, when cmd move 512, data_buf, when data_out move 1, stat_in_buf, when status move 1, msg_in_buf, when msg_in move scntl2 & 7f to scntl2 clear ack wait disconnect alt2 int 10 data structure message buffer command buffer data buffer status buffer LSI53C1010-33 scsi bus write dsp fetch scripts data (data is not fetched across system bus if internal ram is enabled.) s y s t e m b u s
block move instructions 5-5 5.2 block move instructions for block move instructions, bits 5 and 4 (siom and diom) in the dma mode (dmode) register determine whether the source/destination address resides in memory or i/o space. when data is moved onto the scsi bus, siom controls whether that data comes from the i/o or memory space. when data is moved off of the scsi bus, diom controls whether that data goes to the i/o or memory space. 5.2.1 first dword figure 5.2 block move instruction - first dword it[1:0] instruction type - block move [31:30] the con?guration of these two bits de?ne the scripts instruction type. the block move instruction is 0b00. ia indirect addressing 29 when this bit is cleared, user data is moved to or from the 32-bit data start address for the block move instruction. the value is loaded into the chips address register and incremented as data is transferred. the address of the data to move is in the second dword of this instruction. when the en64dbmv bit in chip control one (ccntl1) is set, a third dword is fetched to provide the upper dword of a 64-bit address. the upper dword address is fetched along with the instruction and loaded into the dynamic block move selector (dbms) register. if the en64dbmv bit is cleared, the upper dword address is copied from the static block move selector (sbms) register. 31 30 29 28 27 26 24 23 0 dcmd register dbc register it[1:0] ia tia opc scsip[2:0] tc[23:0] x x x x x x x x x xxxxxx x x xxxxxxxxxxxxxx x
5-6 scsi scripts instruction set direct addressing the byte count and absolute address are as follows: indirect when set, the 32-bit user data start address for the block move is the address of a pointer to the actual data buffer address. the value at the 32-bit start address is loaded into the chips dma next address (dnad) register using a third dword fetch (4-byte transfer across the host computer bus). use the fetched byte count, but fetch the data address from the address in the instruction. if 64-bit addressing is desired, the upper dword of the address is stored in the static block move selector (sbms) register. when the value in sbms is 0x0, 32-bit addressing is assumed. once the data pointer address is loaded, it is executed as when the chip operates in the direct mode. this indirect feature allows speci?cation of a table of data buffer addresses. using the scsi scripts compiler, the table offset is placed in the script at compile time. then at the actual data transfer time, the offsets are added to the base address of the data address table by the external processor. the logical i/o driver builds a structure of addresses for an i/o rather than treating each address individually. note: using indirect and table indirect addressing simultaneously is not permitted; use only one addressing method at a time. command byte count lower dword address of data upper dword address of data (en64dbmv = 1) command byte count address of pointer to data
block move instructions 5-7 tia table indirect 28 32-bit addressing when this bit is set, the 24-bit signed value in the start address of the move is treated as a relative displacement from the value in the data structure address (dsa) register. both the transfer count and the source/ destination address are fetched from this location. use the signed integer offset in bits [23:0] of the second four bytes of the instruction, added to the value in the data structure address (dsa) register, to fetch ?rst the byte count and then the data address. the signed value is combined with the data structure base address to generate the physical address used to fetch values from the data structure. sign-extended values of all ones for negative values are allowed, but bits [31:24] are ignored. note: using indirect and table indirect addressing simultaneously is not permitted; use only one addressing method at a time. prior to the start of an i/o, load the data structure address (dsa) register with the base address of the i/o data structure. any address on a dword boundary is allowed. after a table indirect opcode is fetched, the data structure address (dsa) is added to the 24-bit signed offset value from the opcode to generate the address of the required data; both positive and negative offsets are allowed. a subsequent fetch from that address brings the data values into the chip. for a move instruction, the 24-bit byte count is fetched from system memory. then the 32-bit physical address is brought into the LSI53C1010-33. execution of the move begins at this point. scripts can directly execute operating system i/o data structures, saving time at the beginning of an i/o operation. the i/o data structure can begin on any dword boundary and may cross system segment boundaries. command not used dont care table offset
5-8 scsi scripts instruction set there are two restrictions on the placement of pointer data in system memory: the eight bytes of data in the move instruction must be contiguous. indirect data fetches are not available during execution of a memory-to-memory dma operation. 64-bit addressing if the enable 64-bit table indirect block move (en64tibmv) bit is cleared, table indirect block moves remain as 2 dword opcodes plus a 2 dword table entry. the upper 32 bits of the address are copied from the static block move selector (sbms) when performing data transfers during block move operations. the sbms register must be loaded manually. if the enable 64-bit table indirect block move (en64tibmv) bit is set and the 64-bit table indirect index mode (64timod) bit is cleared, bits [28:24] of the ?rst dword of the table entry (where the byte count is located) select one of the 16 scratch registers or any of the six 64-bit selector registers as a selector for the upper 32-bit address. please see the table indirect index mode mapping table for a breakdown of index values and the corresponding registers selected. the selected address is automatically loaded into the dma next address 64 (dnad64) register. note: if en64tibmv is set and 64timod is set, bits [31:24] of the ?rst dword of the table entry (where the byte count is located) are loaded directly into dma next address 64 (dnad64) to provide a 40-bit address. the format for the table indirect entries for each mode is shown below. the table for table indirect block moves upper 32 bit address locations summarizes the available modes for table indirect block moves. 00 byte count physical data address
block move instructions 5-9 index mode 0 (64timod clear) table entry format: index mode 1 (64timod set) table entry format: table indirect block moves upper 32-bit address locations: 31 29 28 24 23 0 r sel index byte count source/destination address [31:0] xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 31 24 0 src/dest addr [39:32] byte count source/destination address [31:0] xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx en64tibmv 64timod upper 32-bit data address comes from 0 0 sbms 0 1 sbms 1 0 scratchcCj, mmws, mmrs, sfs, drs, sbms, dbms 1 1 1st table entry dword bits [31:24] (40-bit addressing only)
5-10 scsi scripts instruction set table indirect index mode mapping: opc opcode 27 this 1-bit ?eld de?nes the instruction to execute as a block move (move). target mode index value selector used 0x00 scratch c 0x01 scratch d 0x02 scratch e 0x03 scratch f 0x04 scratch g 0x05 scratch h 0x06 scratch i 0x07 scratch j 0x08 scratch k 0x09 scratch l 0x0a scratch m 0x0b scratch n 0x0c scratch o 0x0d scratch p 0x0e scratch q 0x0f scratch r 0x10 mmrs 0x11 mmws 0x12 sfs 0x13 drs 0x14 sbms 0x15 sbms 0x16C0x1f illegal (results in an iid interrupt) opc instruction de?ned 0 move/move64 1 chmov/chmov64
block move instructions 5-11 the LSI53C1010-33 veri?es that it is connected to the scsi bus as a target before executing this instruction. the LSI53C1010-33 asserts the scsi phase signals (smsg/, sc_d/, and si_o/) as de?ned by the phase field bits in the instruction. if the instruction is for the command phase, the LSI53C1010-33 receives the ?rst command byte and decodes its scsi group code. if the scsi group code is either group 0, group 1, group 2, or group 5, then the LSI53C1010-33 overwrites the dma byte counter (dbc) register with the length of the command descriptor block: 6, 10, or 12 bytes. if the vendor unique enhancement 0 (vue0) bit ( scsi control two (scntl2) , bit 1) is cleared and the scsi group code is a vendor unique code, the LSI53C1010-33 overwrites the dma byte counter (dbc) register with the length of the command descriptor block: 6, 10, or 12 bytes. if the vue0 bit is set, the LSI53C1010-33 receives the number of bytes in the byte count regardless of the group code. if any other group code is received, the dma byte counter (dbc) register is not modi?ed and the LSI53C1010-33 requests the number of bytes speci?ed in the dma byte counter (dbc) register. if the dbc register contains 0x000000, an illegal instruction interrupt is generated. the LSI53C1010-33 transfers the number of bytes speci?ed in the dma byte counter (dbc) register starting at the address speci?ed in the dma next address (dnad) register. if the opcode bit is set and a data transfer ends on an odd byte boundary, the LSI53C1010-33 stores the last byte in the scsi wide residue (swide) register during a receive operation. this byte is combined with the ?rst byte from the subsequent transfer so that a wide transfer can complete. if the satn/ signal is asserted by the initiator or a parity error occurred during the transfer, it is possible to halt the transfer and generate an interrupt. the disable halt on parity error or atn bit in the scsi control one (scntl1)
5-12 scsi scripts instruction set register controls whether the LSI53C1010-33 halts on these conditions immediately, or waits until completion of the current move. initiator mode the LSI53C1010-33 veri?es that it is connected to the scsi bus as an initiator before executing this instruction. the LSI53C1010-33 waits for an unserviced phase to occur. an unserviced phase is de?ned as any phase (with sreq/ asserted) for which the LSI53C1010-33 has not yet transferred data by responding with a sack/. the LSI53C1010-33 compares the scsi phase bits in the dma command (dcmd) register with the latched scsi phase lines stored in the scsi status one (sstat1) register. these phase lines are latched when sreq/ is asserted. if the scsi phase bits match the value stored in the scsi status one (sstat1) register, the LSI53C1010-33 transfers the number of bytes speci?ed in the dma byte counter (dbc) register starting at the address pointed to by the dma next address (dnad) register. if the opcode bit is cleared and a data transfer ends on an odd byte boundary, the LSI53C1010-33 stores the last byte in the scsi wide residue (swide) register during a receive operation, or in the scsi output data latch (sodl) register during a send operation. this byte is combined with the ?rst byte from the subsequent transfer so that a wide transfer can complete. if the scsi phase bits do not match the value stored in the scsi status one (sstat1) register, the LSI53C1010-33 generates a phase mismatch interrupt and the instruction is not executed. during a message-out phase, after the LSI53C1010-33 has performed a select with attention (or satn/ is manually asserted with a set atn instruction), the LSI53C1010-33 deasserts satn/ during the ?nal sreq/sack/ handshake. opc instruction de?ned 0 chmov/chmov64 1 move/move64
block move instructions 5-13 when the LSI53C1010-33 is performing a block move for message-in phase, it does not deassert the sack/ signal for the last sreq/sack/ handshake. clear the sack/ signal using the clear sack i/o instruction. scsip[2:0] scsi phase [26:24] this ?eld de?nes the desired scsi information transfer phase. when the LSI53C1010-33 operates in the initiator mode, these bits are compared with the latched scsi phase bits in the scsi status one (sstat1) register. when the LSI53C1010-33 operates in the target mode, it asserts the phase de?ned in this ?eld. the following table describes the possible combinations and the corresponding scsi phase. tc[23:0] transfer counter [23:0] this 24-bit ?eld speci?es the number of data bytes to be moved between the LSI53C1010-33 and system memory. the ?eld is stored in the dma byte counter (dbc) register. when the LSI53C1010-33 transfers data to/from memory, the dbc register is decremented by the number of bytes transferred. in addition, the dma next address (dnad) register is incremented by the number of bytes transferred. this process is repeated until the dbc register is decremented to zero. at this time, the LSI53C1010-33 fetches the next instruction. if bit 28 is set, indicating table indirect addressing, this ?eld is not used. the byte count is instead fetched from a table pointed to by the data structure address (dsa) register. msg c_d i_o scsi phase 0 0 0 st data-out 0 0 1 st data-in 0 1 0 command 0 1 1 status 1 0 0 dt data-out 1 0 1 dt data-in 1 1 0 message-out 1 1 1 message-in
5-14 scsi scripts instruction set 5.2.2 second dword figure 5.3 block move instruction - second dword start address [31:0] this 32-bit ?eld speci?es the starting address of the data to move to/from memory. this ?eld is copied to the dma next address (dnad) register. when the LSI53C1010-33 transfers data to or from memory, the dnad register is incremented by the number of bytes transferred. when bit 29 is set, indicating indirect addressing, this address is a pointer to an address in memory that points to the data location. when bit 28 is set, indicating table indirect addressing, the value in this ?eld is an offset into a table pointed to by the data structure address (dsa) . the table entry contains byte count and address information. 5.2.3 third dword figure 5.4 block move instruction - third dword start address [63:32] this 32-bit ?eld speci?es the upper dword of a 64-bit starting address of data to move to/from memory. this ?eld is copied to the dynamic block move selector (dbms) register. the en64dbmv bit in the chip control one (ccntl1) register must be set for this dword to be fetched. 31 0 dsps register xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 31 0 dbms register xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
i/o instructions 5-15 5.3 i/o instructions this section contains information about the i/o instruction register. it is divided into first dword and second dword. 5.3.1 first dword figure 5.5 first 32-bit word of the i/o instruction it[1:0] instruction type - i/o instruction [31:30] opc[2:0] opcode [29:27] the following opcode bits have different meanings, depending on whether the LSI53C1010-33 is operating in the initiator or target mode. opcode selections 0b101C 0b111 are considered read/write instructions, and are described in section 5.4, read/write instructions. target mode reselect instruction the LSI53C1010-33 arbitrates for the scsi bus by asserting the scsi id stored in the scsi chip id (scid) register. if it loses arbitration, it tries again during the next available arbitration cycle without reporting any lost arbitration status. 31 30 29 27 26 25 24 23 20 19 16 15 11 10 9 8 7 6 5 4 3 2 0 dcmd register dbc register it[1:0] opc[2:0] ra ti sel r endid[3:0] rcatm ra ratn r 01xxx x x x 0 0 0 0xxxx 0 0 0 0 0x x 0 0x 0 0x 0 0 0 opc2 opc1 opc0 instruction de?ned 0 0 0 reselect 0 0 1 disconnect 0 1 0 wait select 011set 1 0 0 clear
5-16 scsi scripts instruction set if the LSI53C1010-33 wins arbitration, it attempts to reselect the scsi device whose id is de?ned in the destination id ?eld of the instruction. once the LSI53C1010-33 wins arbitration, it fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register. this way the scripts can move on to the next instruction before the reselection completes. it continues executing scripts until a script that requires a response from the initiator is encountered. if the LSI53C1010-33 is selected or reselected before winning arbitration, it fetches the next instruction from the address pointed to by the 32-bit jump address ?eld stored in the dma next address (dnad) register. manually set the LSI53C1010-33 to the initiator mode if it is reselected, or to the target mode if it is selected. disconnect instruction the LSI53C1010-33 disconnects from the scsi bus by deasserting all scsi signal outputs. wait select instruction if the LSI53C1010-33 is selected, it fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register. if reselected, the LSI53C1010-33 fetches the next instruction from the address pointed to by the 32-bit jump address ?eld stored in the dma next address (dnad) register. manually set the LSI53C1010-33 to the initiator mode when it is reselected. if the cpu sets the sigp bit in the interrupt status zero (istat0) register, the LSI53C1010-33 aborts the wait select instruction and fetches the next instruction from the address pointed to by the 32-bit jump address ?eld stored in the dma next address (dnad) register. set instruction when the sack/ or satn/ bits are set, the corresponding bits in the scsi output control latch (socl) register are set. do not set sack/ or satn/ except for testing purposes. when the target bit is set, the corresponding bit in the scsi control zero (scntl0)
i/o instructions 5-17 register is also set. when the carry bit is set, the corresponding bit in the arithmetic logic unit (alu) is set. note: none of the signals are set on the scsi bus in target mode. clear instruction when the sack/ or satn/ bits are cleared, the corresponding bits are cleared in the scsi output control latch (socl) register. do not set sack/ or satn/ except for testing purposes. when the target bit is cleared, the corresponding bit in the scsi control zero (scntl0) register is cleared. when the carry bit is cleared, the corresponding bit in the alu is cleared. note: none of the signals are cleared on the scsi bus in the target mode. initiator mode select instruction the LSI53C1010-33 arbitrates for the scsi bus by asserting the scsi id stored in the scsi chip id (scid) register. if it loses arbitration, it tries again during the next available arbitration cycle without reporting any lost arbitration status. if the LSI53C1010-33 wins arbitration, it attempts to select the scsi device whose id is de?ned in the destination id ?eld of the instruction. once the LSI53C1010-33 wins arbitration, it fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register. this way the scripts can move to the next instruction before the selection opc2 opc1 opc0 instruction de?ned 0 0 0 select 0 0 1 wait disconnect 0 1 0 wait reselect 0 1 1 set 1 0 0 clear
5-18 scsi scripts instruction set completes. it continues executing scripts until a script that requires a response from the target is encountered. if the LSI53C1010-33 is selected or reselected before winning arbitration, it fetches the next instruction from the address pointed to by the 32-bit jump address ?eld stored in the dma next address (dnad) register. manually set the LSI53C1010-33 to the initiator mode if it is reselected, or to the target mode if it is selected. if the select with satn/ ?eld is set, the satn/ signal is asserted during the selection phase. wait disconnect instruction the LSI53C1010-33 waits for the target to perform a legal disconnect from the scsi bus. a legal disconnect occurs when sbsy/ and ssel/ are inactive for a minimum of one bus free delay (400 ns), after the LSI53C1010-33 receives a disconnect message or a command complete message. wait reselect instruction if the LSI53C1010-33 is selected before being reselected, it fetches the next instruction from the address pointed to by the 32-bit jump address ?eld stored in the dma next address (dnad) register. manually set the LSI53C1010-33 to the target mode when it is selected. if the LSI53C1010-33 is reselected, it fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register. if the cpu sets the sigp bit in the interrupt status zero (istat0) register, the LSI53C1010-33 aborts the wait reselect instruction and fetches the next instruction from the address pointed to by the 32-bit jump address ?eld stored in the dma next address (dnad) register. set instruction when the sack/ or satn/ bits are set, the corresponding bits in the scsi output control latch (socl) register are set. when the target bit is set, the corresponding bit in the scsi control zero (scntl0) register is also set. when the carry bit is set, the corresponding bit in the alu is set.
i/o instructions 5-19 clear instruction when the sack/ or satn/ bits are cleared, the corresponding bits are cleared in the scsi output control latch (socl) register. when the target bit is cleared, the corresponding bit in the scsi control zero (scntl0) register is cleared. when the carry bit is cleared, the corresponding bit in the alu is cleared. ra relative addressing mode 26 when this bit is set, the 24-bit signed value in the dma next address (dnad) register is used as a relative displacement from the current dma scripts pointer (dsp) address. use this bit only in conjunction with the select, reselect, wait select, and wait reselect instructions. the select and reselect instructions can contain an absolute alternate jump address or a relative transfer address. ti table indirect mode 25 when this bit is set, the 24-bit signed value in the dma byte counter (dbc) register is added to the value in the data structure address (dsa) register, and used as an offset relative to the value in the data structure address (dsa) register. the scsi control three (scntl3) value, scsi id, synchronous offset and synchronous period are loaded from this address. prior to the start of an i/o, load the data structure address (dsa) with the base address of the i/o data structure. any address on a dword boundary is allowed. after a table indirect opcode is fetched, the data structure address (dsa) is added to the 24-bit signed offset value from the opcode to generate the address of the required data. both positive and negative offsets are allowed. a subsequent fetch from that address brings the data values into the chip. scripts can directly execute operating system i/o data structures, saving time at the beginning of an i/o operation. the i/o data structure can begin on any dword boundary and may cross system segment boundaries. there are two restrictions on the placement of data in system memory: the i/o data structure must lie within the 8 mbytes above or below the base address.
5-20 scsi scripts instruction set an i/o command structure must have all four bytes contiguous in system memory, as shown below. the offset/period bits are ordered as in the scsi transfer (sxfer) register. the con?guration bits are ordered as in the scsi control three (scntl3) register. use this bit only in conjunction with the select, reselect, wait select, and wait reselect instructions. it is allowable to set bits 25 and 26 individually or in combination: direct uses the device id and physical address in the instruction. table indirect uses the physical jump address, but fetches data using the table indirect method. relative uses the device id in the instruction, but treats the alternate address as a relative jump. con?g id offset/period 00 bit 25 bit 26 direct 0 0 table indirect 0 1 relative 1 0 table relative 1 1 command id not used not used absolute alternate address command table offset absolute alternate address command id not used not used absolute jump offset
i/o instructions 5-21 table relative treats the alternate jump address as a relative jump and fetches the device id, synchronous offset, and synchronous period indirectly. the value in bits [23:0] of the ?rst four bytes of the scripts instruction is added to the data structure base address to form the fetch address. sel select with atn/ 24 this bit speci?es whether satn/ is asserted during the selection phase when the LSI53C1010-33 is executing a select instruction. when operating in the initiator mode, set this bit for the select instruction. if this bit is set on any other i/o instruction, an illegal instruction interrupt is generated. r reserved [23:20] endid[3:0] encoded scsi destination id [19:16] this 4-bit ?eld speci?es the destination scsi id for an i/o instruction. r reserved [15:11] ca set/clear carry 10 this bit is used in conjunction with a set or clear instruction to set or clear the carry bit. setting this bit with a set instruction asserts the carry bit in the alu. clearing this bit with a clear instruction deasserts the carry bit in the alu. tm set/clear target mode 9 this bit is used in conjunction with a set or clear instruction to set or clear the target mode. setting this bit with a set instruction con?gures the LSI53C1010-33 as a target device (this sets bit 0 of the scsi control zero (scntl0) register). clearing this bit with a clear instruction con?gures the LSI53C1010-33 as an initiator device (this clears bit 0 of the scntl0 register). command table offset absolute jump offset
5-22 scsi scripts instruction set r reserved [8:7] a set/clear sack/ 6 r reserved [5:4] atn set/clear satn/ 3 these two bits are used in conjunction with a set or clear instruction to assert or deassert the corresponding scsi control signal. bit 6 controls the scsi sack/ signal. bit 3 controls the scsi satn/ signal. the set instruction is used to assert sack/ and/or satn/ on the scsi bus. the clear instruction is used to deassert sack/ and/or satn/ on the scsi bus. the corresponding bit in the scsi output control latch (socl) register will be set or cleared depending on the instruction used. since sack/ and satn/ are initiator signals, they are not asserted on the scsi bus. the set/clear scsi ack/, atn/ instruction is used after message phase block move operations to give the initiator the opportunity to assert attention before acknowledging the last message byte. for example, if the initiator wishes to reject a message, it issues an assert scsi atn instruction before a clear scsi ack instruction. r reserved [2:0] 5.3.2 second dword figure 5.6 second 32-bit word of the i/o instruction sa start address [31:0] this 32-bit ?eld contains the memory address to fetch the next instruction if the selection or reselection fails. if relative or table relative addressing is used, this value is a 24-bit signed offset relative to the current dma scripts pointer (dsp) register value. 31 0 dsps register xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
read/write instructions 5-23 5.4 read/write instructions the read/write instruction supports addition, subtraction, and comparison of two separate values within the chip. it performs the desired operation on the speci?ed register and the scsi first byte received (sfbr) register and stores the result back to the speci?ed register or to the sfbr. if the com bit ( dma control (dcntl) , bit 0) is cleared, read/write instructions cannot be used. 5.4.1 first dword figure 5.7 read/write instruction - first dword it[1:0] instruction type - read/write instruction [31:30] the read/write instruction uses operator bits [26:24] in conjunction with the opcode bits to determine which instruction is currently selected. opc[2:0] opcode [29:27] these bits determine if the instruction is a read/write or an i/o instruction. opcodes 0b000 through 0b100 are considered i/o instructions. o[2:0] operator [26:24] the operator bits are used in conjunction with the opcode bits to determine which instruction is currently selected. refer to table 5.1 on page 5-25 for ?eld de?nitions. d8 use data8/sfbr 23 when this bit is set, scsi first byte received (sfbr) is used, instead of the data8 value, during a read-modify- write instruction (see table 5.1 ). this allows the user to add two register values. 31 30 29 27 26 24 23 22 16 15 8 7 0 dcmd register dbc register it[1:0] opc[2:0] o[2:0] d8 a[6:0] immd r - must be 0 01xxxxxxxxxxxxxxxxxxxxxx 0 0 0 0 0 0 0 0
5-24 scsi scripts instruction set a[6:0] register address - a[6:0] [22:16] it is possible to change register values from scripts in read-modify-write cycles or move to/from scsi first byte received (sfbr) cycles. a[6:0] selects an 8-bit source/destination register within the LSI53C1010-33. immd immediate data [15:8] this 8-bit value is used as a second operand in logical and arithmetic functions. a7 upper register address line (a7) 7 this bit is used to access registers 0x80C0xff. r reserved [6:0] 5.4.2 second dword figure 5.8 read/write instruction - second dword da destination address [31:0] this ?eld contains the 32-bit destination address where the data is to move. 5.4.3 read-modify-write cycles during these cycles the register is read, the selected operation is performed, and the result is written back to the source register. the add operation is used to increment or decrement register values (or memory values if used in conjunction with a memory-to-register move operation) for use as loop counters. subtraction is not available when scsi first byte received (sfbr) is used instead of data8 in the instruction syntax. to subtract one value from another when using sfbr, ?rst xor the value to subtract (subtrahend) with 0xff, and add 1 to the resulting value. this creates the 2s complement of the subtrahend. the two values are then added to obtain the difference. 31 0 dsps register xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
read/write instructions 5-25 5.4.4 move to/from sfbr cycles all operations are read-modify-writes. however, two registers are involved, one of which is always the scsi first byte received (sfbr) . the possible functions of this instruction are: write one byte (value contained within the scripts instruction) into any chip register. move to/from the scsi first byte received (sfbr) from/to any other register. alter the value of a register with and, or, add, xor, shift left, or shift right operators. after moving values to the scsi first byte received (sfbr) , the compare and jump, call, or similar instructions are used to check the value. a move-to-sfbr followed by a move-from-sfbr is used to perform a register to register move. table 5.1 read/write instructions 1 operator opcode 111 read modify write opcode 110 move to sfbr opcode 101 move from sfbr 000 move data into register. syntax: move data8 to rega move data into scsi first byte received (sfbr) register. syntax: move data8 to sfbr move data into register. syntax: move data8 to rega 001 2 shift register one bit to the left and place the result in the same register. syntax: move rega shl rega shift register one bit to the left and place the result in the scsi first byte received (sfbr) register. syntax: move rega shl sfbr shift the sfbr register one bit to the left and place the result in the register. syntax: move sfbr shl rega 010 or data with register and place the result in the same register. syntax: move rega | data8 to rega or data with register and place the result in the scsi first byte received (sfbr) register. syntax: move rega | data8 to sfbr or data with sfbr and place the result in the register. syntax: move sfbr | data8 to rega
5-26 scsi scripts instruction set 011 xor data with register and place the result in the same register. syntax: move rega xor data8 to rega xor data with register and place the result in the scsi first byte received (sfbr) register. syntax: move rega xor data8 to sfbr xor data with sfbr and place the result in the register. syntax: move sfbr xor data8 to rega 100 and data with register and place the result in the same register. syntax: move rega & data8 to rega and data with register and place the result in the scsi first byte received (sfbr) register. syntax: move rega & data8 to sfbr and data with sfbr and place the result in the register. syntax: move sfbr & data8 to rega 101 2 shift register one bit to the right and place the result in the same register. syntax: move rega shr rega shift register one bit to the right and place the result in the scsi first byte received (sfbr) register. syntax: move rega shr sfbr shift the sfbr register one bit to the right and place the result in the register. syntax: move sfbr shr rega 110 add data to register without carry and place the result in the same register. syntax: move rega + data8 to rega add data to register without carry and place the result in the scsi first byte received (sfbr) register. syntax: move rega + data8 to sfbr add data to sfbr without carry and place the result in the register. syntax: move sfbr + data8 to rega 111 add data to register with carry and place the result in the same register. syntax: move rega + data8 to rega with carry add data to register with carry and place the result in the scsi first byte received (sfbr) register. syntax: move rega + data8 to sfbr with carry add data to sfbr with carry and place the result in the register. syntax: move sfbr + data8 to rega with carry 1. substitute the desired register name or address for rega in the syntax examples. data8 indicates eight bits of data. use sfbr instead of data8 to add two register values. 2. data is shifted through the carry bit and the carry bit is shifted into the data byte. table 5.1 read/write instructions 1 (cont.) operator opcode 111 read modify write opcode 110 move to sfbr opcode 101 move from sfbr
transfer control instructions 5-27 5.5 transfer control instructions this section describes transfer control instructions for the ?rst dword, second dword, and third dword. 5.5.1 first dword figure 5.9 transfer control instructions - first dword it[1:0] instruction type - [31:30] transfer control instruction opc[2:0] opcode [29:27] this 3-bit ?eld speci?es the type of transfer control instruction to execute. all transfer control instructions can be conditional. they can be dependent on a true/false comparison of the alu carry bit or a comparison of the scsi information transfer phase with the phase ?eld, and/or a comparison of the first byte received with the data compare ?eld. each instruction can operate in the initiator or target mode. jump instruction the LSI53C1010-33 can do a true/false comparison of the alu carry bit, or compare the phase and/or data as de?ned by the phase compare, data compare and true/false bit ?elds. if the comparisons are true, it loads the dma scripts pointer (dsp) register with the 31 30 29 27 26 24 23 22 21 20 19 18 17 16 15 8 7 0 dcmd register dbc register it[1:0] opc[2:0] scsip[2:0] ra j ct if tf cd cp vp mc dc xxxxx x x x x xxxx x x xxxxxxxxxxxxxxxxx opc2 opc1 opc0 instruction de?ned 000jump 0 0 1 call 0 1 0 return 0 1 1 interrupt 1 x x reserved
5-28 scsi scripts instruction set contents of the dma scripts pointer save (dsps) register. the dsp register now contains the address of the next instruction. if the comparisons are false, the LSI53C1010-33 fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register, leaving the instruction pointer unchanged. when the jump64 instruction is used, a third dword is fetched and loaded into the script fetch selector (sfs) register. bit 22 indicates whether the jump is to a 32-bit address (0) or a 64-bit address (1). all combinations of jumps are still valid for jump64. call instruction the LSI53C1010-33 can do a true/false comparison of the alu carry bit, or compare the phase and/or data as de?ned by the phase compare, data compare, and true/false bit ?elds. if the comparisons are true, it loads the dma scripts pointer (dsp) register with the contents of the dma scripts pointer save (dsps) register and that address value becomes the address of the next instruction. when the LSI53C1010-33 executes a call instruction, the instruction pointer contained in the dma scripts pointer (dsp) register is stored in the temporary (temp) register. since the temp register is not a stack and can only hold one dword, nested call instructions are not allowed. if the comparisons are false, the LSI53C1010-33 fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register and the instruction pointer is not modi?ed. return instruction the LSI53C1010-33 can do a true/false comparison of the alu carry bit, or compare the phase and/or data as de?ned by the phase compare, data compare, and true/false bit ?elds. if the comparisons are true, it loads the dma scripts pointer (dsp) register with the contents of the dma scripts pointer save (dsps) register. that address value becomes the address of the next instruction.
transfer control instructions 5-29 when a return instruction is executed, the value stored in the temporary (temp) register is returned to the dma scripts pointer (dsp) register. the LSI53C1010-33 does not check to see whether the call instruction has already been executed. it does not generate an interrupt if a return instruction is executed without previously executing a call instruction. if the comparisons are false, the LSI53C1010-33 fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register and the instruction pointer is not modi?ed. interrupt instruction the LSI53C1010-33 can do a true/false comparison of the alu carry bit, or compare the phase and/or data as de?ned by the phase compare, data compare, and true/false bit ?elds. if the comparisons are true, the LSI53C1010-33 generates an interrupt by asserting the irq/ signal. the 32-bit address ?eld stored in the dma scripts pointer save (dsps) register can contain a unique interrupt service vector. when servicing the interrupt, this unique status code allows the isr to quickly identify the point at which the interrupt occurred. the LSI53C1010-33 halts and the dma scripts pointer (dsp) register must be written to before starting any further operation. interrupt-on-the-fly instruction the LSI53C1010-33 can do a true/false comparison of the alu carry bit or compare the phase and/or data as de?ned by the phase compare, data compare, and true/false bit ?elds. if the comparisons are true, and the interrupt-on-the-fly bit interrupt status zero (istat0) , bit 2) is set, the LSI53C1010-33 asserts the interrupt-on- the-fly bit. scsip[2:0] scsi phase [26:24] this 3-bit ?eld corresponds to the three scsi bus phase signals that are compared with the phase lines latched when sreq/ is asserted. comparisons can be performed to determine the scsi phase actually being driven on the scsi bus. the following table describes the possible
5-30 scsi scripts instruction set combinations and their corresponding scsi phase. these bits are only valid when the LSI53C1010-33 is operating in the initiator mode. clear these bits when the LSI53C1010-33 is operating in the target mode. ra relative addressing mode 23 when this bit is set, the 24-bit signed value in the dma scripts pointer save (dsps) register is used as a relative offset from the current dma scripts pointer (dsp) address, which is pointing to the next instruction and not the one currently executing. the relative mode does not apply to return and interrupt scripts. jump/call an absolute address start execution at the new absolute address. jump/call a relative address start execution at the current address plus (or minus) the relative offset. the scripts program counter is a 32-bit value pointing to the scripts currently under execution by the LSI53C1010-33. the next address is formed by adding the 32-bit program counter to the 24-bit signed value of msg c/d i/o scsi phase 0 0 0 st data-out 0 0 1 st data-in 0 1 0 command 0 1 1 status 1 0 0 dt data-out 1 0 1 dt data-in 1 1 0 message-out 1 1 1 message-in command condition codes absolute alternate address command condition codes dont care alternate jump offset
transfer control instructions 5-31 the last 24 bits of the jump or call instruction. because it is signed (2s complement), the jump can be forward or backward. a relative transfer can be to any address within a 16 mbyte segment. the program counter is combined with the 24-bit signed offset (using addition or subtraction) to form the new execution address. scripts programs may contain a mixture of direct jumps and relative jumps to provide maximum versatility when writing scripts. for example, major sections of code can be accessed with far calls using the 32-bit physical address, then local labels can be called using relative transfers. if a script is written using only relative transfers it does not require any run time alteration of physical addresses, and can be stored in and executed from a prom. j 32/64 bit jump 22 when this bit is cleared, the jump address is 32-bits wide. when this bit is set, the jump address is 64-bits wide. ct carry test 21 when this bit is set, decisions based on the alu carry bit can be made. true/false comparisons are legal, but data compare and phase compare are illegal. if interrupt-on-the-fly 20 when this bit is set, the interrupt instruction does not halt the scripts processor. once the interrupt occurs, the interrupt-on-the-fly bit ( interrupt status zero (istat0), bit 2) is asserted. tf jump if true/false 19 this bit determines whether the LSI53C1010-33 branches when a comparison is true or when a comparison is false. this bit applies to phase compares, data compares, and carry tests. if both the phase compare and data compare bits are set, then both compares must be true to branch on a true condition. both compares must be false to branch on a false condition.
5-32 scsi scripts instruction set cd compare data 18 when this bit is set, the ?rst byte received from the scsi data bus (contained in the scsi first byte received (sfbr) register) is compared with the data to be compared field in the transfer control instruction. the wait for valid phase bit controls when this compare occurs. the jump if true/false bit determines the condition (true or false) to branch on. cp compare phase 17 when the LSI53C1010-33 is in the initiator mode, this bit controls phase compare operations. when this bit is set, the scsi phase signals (latched by sreq/) are compared to the phase field in the transfer control instruction. if they match, the comparison is true. the wait for valid phase bit controls when the compare occurs. when the LSI53C1010-33 is operating in the target mode and this bit is set it tests for an active scsi satn/ signal. vp wait for valid phase 16 if the wait for valid phase bit is set, the LSI53C1010-33 waits for a previously unserviced phase before comparing the scsi phase and data. if the wait for valid phase bit is cleared, the LSI53C1010-33 compares the scsi phase and data immediately. mc data compare mask [15:8] the data compare mask allows a script to test certain bits within a data byte. during the data compare, if any mask bits are set, the corresponding bit in the scsi first byte received (sfbr) data byte is ignored. for instance, a mask of 0b01111111 and data compare value of bit 19 result of compare action 0 false jump taken 0 true no jump 1 false no jump 1 true jump taken
transfer control instructions 5-33 0b1xxxxxxx allows the scripts processor to determine whether or not the high-order bit is set while ignoring the remaining bits. dc data compare value [7:0] this 8-bit ?eld is the data compared against the scsi first byte received (sfbr) register. these bits are used in conjunction with the data compare mask field to test for a particular data value. if the com bit ( dma control (dcntl) , bit 0) is cleared, the value in the sfbr register may not be stable. in this case, do not use instructions using this data compare value. 5.5.2 second dword figure 5.10 transfer control instructions - second dword jump address [31:0] this 32-bit ?eld contains the address of the next instruction to fetch when a jump is taken. once the LSI53C1010-33 fetches the instruction from the address pointed to by these 32 bits, this address is incremented by 4, loaded into the dma scripts pointer (dsp) register and becomes the current instruction pointer. 5.5.3 third dword figure 5.11 transfer control instructions - third dword jump64 address [31:0] this 32-bit ?eld contains the upper dword of a 64-bit address of the next instruction to fetch when a jump64 is taken. 31 0 dsps register xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 31 0 sfs register (used for jump64 instruction) xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
5-34 scsi scripts instruction set 5.6 memory move instructions for memory move instructions, bits 5 and 4 (siom and diom) in the dma mode (dmode) register determine whether the source or destination addresses reside in memory or i/o space. by setting these bits appropriately, data may be moved within memory space, within i/o space, or between the two address spaces. the memory move instruction is used to copy the speci?ed number of bytes from the source address to the destination address. for memory moves where the data read is from the 64-bit address space, the upper dword of the address resides in the memory move read selector (mmrs) register. for memory moves where the data is written to the 64-bit address space, the upper dword of the address resides in the memory move write selector (mmws) register. allowing the LSI53C1010-33 to perform memory moves frees the system processor for other tasks and moves data at higher speeds than available from current dma controllers. up to 16 mbytes may be transferred with one instruction. there are two restrictions: both the source and destination addresses must start with the same address alignment (a[1:0]) must be the same). if the source and destination are not aligned, then an illegal instruction interrupt occurs. for the pci cache line size (cls) register setting to take effect, the source and destination must be the same distance from a cache line boundary. indirect addresses are not allowed. a burst of data is fetched from the source address, put into the dma fifo and then written out to the destination address. the move continues until the byte count decrements to zero, then another script is fetched from system memory. the dma scripts pointer save (dsps) and data structure address (dsa) registers are additional holding registers used during the memory move. however, the contents of the data structure address (dsa) register are preserved.
memory move instructions 5-35 figure 5.12 memory move instructions - first dword it[2:0] instruction type - memory move [31:29] r reserved [28:25] these bits are reserved and must be zero. if any of these bits are set, an illegal instruction interrupt occurs. nf no flush 24 when this bit is set, the LSI53C1010-33 performs a memory move without ?ushing the prefetch unit. when this bit is cleared, the memory move instruction automatically ?ushes the prefetch unit. use the no flush option if the source and destination are not within four instructions of the current memory move instruction. note: this bit has no effect unless the prefetch enable bit in the dma control (dcntl) register is set. for information on scripts instruction prefetching, see chapter 2, func- tional description. tc[23:0] transfer count [23:0] the number of bytes to transfer is stored in the lower 24 bits of the ?rst instruction word. 5.6.1 read/write system memory from a script by using the memory move instruction, single or multiple register values are transferred to or from system memory. because the LSI53C1010-33 responds to addresses as de?ned in the base address register zero (bar0) (i/o) or base address register one (bar1) (memory) registers, the device can be accessed during a memory move operation if the source or destination address decodes to within the chips register space. if this occurs, the register indicated by the lower seven bits of the address is taken as the data source or 31 29 28 25 24 23 0 dcmd register dbc register it[2:0] r nf tc[23:0] xxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxx
5-36 scsi scripts instruction set destination. in this way, register values are saved to system memory and later restored, and scripts can make decisions based on data values in system memory. the scsi first byte received (sfbr) is not writable using the cpu, and therefore not by a memory move. however, it can be loaded using scripts read/write operations. to load the sfbr with a byte stored in system memory, ?rst move the byte to an intermediate LSI53C1010-33 register (for example, a scratch register), and then to the scsi first byte received (sfbr) . the same address alignment restrictions apply to register access operations as to normal memory-to-memory transfers. 5.6.2 second dword figure 5.13 memory move instructions - second dword - dsps register [31:0] these bits contain the source address of the memory move. if the source address is in the 64-bit address space, the bits will be contained in the memory move read selector (mmrs) register. 5.6.3 third dword figure 5.14 memory move instructions - third dword 31 0 dsps register xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 31 0 mmrs register xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 31 0 temp register xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
load and store instructions 5-37 temp register [31:0] these bits contain the destination address for the memory move. if the destination address is in the 64-bit address space, the bits will be contained in the memory move write selector (mmws) register. 5.7 load and store instructions the load and store instructions provide a more ef?cient way to move data from/to memory to/from an internal register in the chip without using the normal memory move instruction. the load and store instructions are represented by two-dword opcodes. the ?rst dword contains the dma command (dcmd) and dma byte counter (dbc) register values. the second dword contains the dma scripts pointer save (dsps) value. this is either the actual memory location of where to load/store, or the offset from the data structure address (dsa) , depending on the value of bit 28 (dsa relative). for load operations where the data is read from the 64-bit address space, the upper dword of address resides in the memory move read selector (mmrs) register. for store operations where the data is written to the 64-bit address space, the upper dword of address resides in the memory move write selector (mmws) register. a maximum of 4 bytes may be moved with these instructions. the register address and memory address must have the same byte alignment, and the count set such that it does not cross dword boundaries. the memory address may not map back to the chip, excluding ram and rom. if it does, a pci read/write cycle occurs (the data does not actually transfer to/from the chip), and the chip issues an interrupt (illegal instruction detected) immediately following. 31 0 mmws register xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
5-38 scsi scripts instruction set the siom and diom bits in the dma mode (dmode) register determine whether the destination or source address of the instruction is in memory space or i/o space, as illustrated in the following table. the load/store utilizes the pci commands for i/o read and i/o write to access the i/o space. 5.7.1 first dword figure 5.15 load and store instructions - first dword it[2:0] instruction type [31:29] these bits should be 0b111, indicating the load and store instruction. dsa dsa relative 28 when this bit is cleared, the value in the dma scripts pointer save (dsps) is the actual 32-bit memory address used to perform the load/store to/from. when this bit is set, the chip determines the memory address to perform the load/store to/from by adding the 24-bit signed offset value in the dma scripts pointer save (dsps) to the data structure address (dsa) . bits a1, a0 number of bytes allowed to load/store 00 one, two, three or four 01 one, two, or three 10 one or two 11 one bit source destination siom (load) memory register diom (store) register memory 31 29 28 27 26 25 24 23 16 15 3 2 0 dcmd register dbc register it[2:0] dsa r nf ls a[7:0] rbc 111 x 0 0xxxxxxxxxx 0 0 0 0 0 0 0 0 0 0 0 0 0xxx
load and store instructions 5-39 r reserved [27:26] nf no flush (store instruction only) 25 when this bit is set, the LSI53C1010-33 performs a store without ?ushing the prefetch unit. when this bit is cleared, the store instruction automatically ?ushes the prefetch unit. use no flush if the source and destination are not within four instructions of the current store instruction. this bit has no effect on the load instruction. note: this bit has no effect unless the prefetch enable bit in the dma control (dcntl) register is set. for information on scripts instruction prefetching, see chapter 2, func- tional description. ls load/store 24 when this bit is set, the instruction is a load. when cleared, it is a store. a[7:0] register address [23:16] a[7:0] selects the register to load/store to/from within the LSI53C1010-33. r reserved [15:3] bc byte count [2:0] this value is the number of bytes to load/store. 5.7.2 second dword figure 5.16 load and store instructions - second dword memory i/o address/dsa offset [31:0] this is the actual memory location of where to load/store, or the offset from the data structure address (dsa) register value. 31 0 dsps register - memory i/o address/dsa offset xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 31 0 mmrs/mmws register xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
5-40 scsi scripts instruction set
LSI53C1010-33 pci to dual channel ultra160 scsi multifunction controller 6-1 chapter 6 speci?cations this chapter speci?es the LSI53C1010-33 electrical and mechanical characteristics. it is divided into the following sections: section 6.1, dc characteristics section 6.2, tolerant technology electrical characteristics section 6.3, ac characteristics section 6.4, pci and external memory interface timing diagrams section 6.5, scsi timing diagrams section 6.6, package drawings 6.1 dc characteristics this section of the manual describes the LSI53C1010-33 dc characteristics. tables 6.1 through 6.12 give current and voltage speci?cations. figures 6.1 and 6.2 are driver schematics.
6-2 speci?cations table 6.1 absolute maximum stress ratings symbol parameter min max 1 1. stresses beyond those listed above may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions beyond those indicated in the operating conditions section of the manual is not implied. unit test conditions t stg storage temperature - 55 150 cC v dd supply voltage - 0.5 4.5 v C v in input voltage - 0.3 5.55 v C v in-pci input voltage pci pins - .5 11.0 v C i lp 2 2. - 2v dc characteristics 6-3 figure 6.1 lvd driver table 6.3 lvd driver scsi signals 1 sd[15:0], sdp[1:0], sreq/, sack/, smsg/, sio/, scd/, satn/, sbsy/, ssel/, srst/ 1. v cm = 0.7C1.8 v (common mode, nominal ~1.2 v), r l = 0C110 w, r bias =10k w. symbol parameter min max units test conditions i o-assert + source (+) current - 9.6 - 14.4 ma asserted state i o-assert - sink ( - ) current 9.6 14.4 ma asserted state i o-neg + source (+) current - 6.4 - 9.6 ma negated state i o-neg - sink ( - ) current 6.4 9.6 ma negated state i oz 3-state leakage C 20 m aC r l 2 v cm + i o + r l 2 i o - - table 6.4 lvd receiver scsi signals 1 sd[15:0], sdp[1:0], sreq/, sack/, smsg/, sio/, scd/, satn/, sbsy/, ssel/, srst/ 1. v cm = 0.7C1.8 v (common mode voltage, nominal ~1.2 v.) symbol parameter min max units test conditions v i lvd receiver voltage asserting 60 C mv differential voltage v i lvd receiver voltage negating - 60 C mv differential voltage
6-4 speci?cations figure 6.2 lvd receiver v cm + - + + + - - - v i 2 v i 2 table 6.5 a and b diffsens scsi signals symbol parameter min max unit test conditions v ih hvd sense voltage 2.4 5.05 v note 1 v s lvd sense voltage 0.7 1.9 v note 1 v il se sense voltage v ss - 0.35 0.5 v note 1 i oz 3-state leakage - 10 10 m a0v dd = 3 max 1. functional test speci?ed v ih /v il for each mode. table 6.6 input capacitance symbol parameter min max unit test conditions c i input capacitance of input pads C 7 pf guaranteed by design c io input capacitance of i/o pads C 15 pf guaranteed by design c pci input capacitance of pci pads C 8 pf guaranteed by design c lv d input capacitance of lvd pads C 8 pf 6.5 pf pad 1.5 pf package
dc characteristics 6-5 table 6.7 8 ma bidirectional signalsgpio0_fetch/, gpio1_master/, gpio2, gpio3, gpio4 1 1. for channels a and b (except mad[7:0]). symbol parameter min max unit test conditions v ih input high voltage 2.0 5.55 v C v il input low voltage - 0.3 0.8 v C v oh output high voltage 2.4 v dd v - 8ma v ol output low voltage v ss 0.4 v 8 ma i oz 3-state leakage - 10 10 m aC i pull pull up current 25 C m aC table 6.8 4 ma bidirectional signalsmad[7:0] symbol parameter min max unit test conditions v ih input high voltage 2.0 5.55 v C v il input low voltage - 0.3 0.8 v C v oh output high voltage 2.4 v dd v - 4ma v ol output low voltage v ss 0.4 v 4 ma i oz 3-state leakage - 10 10 m aC i pull pull down current 25 C m aC table 6.9 4 ma output signalsmas[1:0]/, mce/, moe/_testout 1 , mwe/, tdo 1. moe/_testout is not tested for 3-state leakage. it cannot be 3-stated. symbol parameter min max unit test conditions v oh output high voltage 2.4 v dd v - 4ma v ol output low voltage v ss 0.4 v 4 ma i oz 3-state leakage - 10 10 m aC
6-6 speci?cations table 6.10 8 ma pci bidirectional signalsad[63:0], c_be[7:0]/, frame/, irdy/, trdy/, devsel/, stop/, perr/, par, par64, req64/, ack64/ symbol parameters min max unit test conditions v ih input high voltage 0.5 v dd v dd +0.5 v C v il input low voltage - 0.5 0.3 v dd vC v oh output high voltage 0.9 v dd v dd v - 8ma v ol output low voltage v ss 0.1 v dd v8ma i oz 3-state leakage - 10 10 m aC i pull-down 1 1. pull-down text does not apply to ad[31:0] and c_be[3:0]/. pull down current 25 C m aC table 6.11 input signalsclk, gnt/, idsel, int_dir, rst/, sclk, tck, tdi, test_hsc, test_rst/, test_pd, tms symbol parameters min max unit test conditions v ih input high voltage 2.0 5.55 v C v il input low voltage - 0.3 0.8 v C i in 3-state leakage - 10 10 m aC i pull-up 1 1. pull-up text does not apply to clk, gnt/, idsel, rst/, and sclk. pull current 25 C m aC table 6.12 8 ma output signalsinta/, intb/, alt_inta/, alt_intb/, req/, serr/ symbol parameters min max unit test conditions v oh output high voltage 0.9 v dd v dd v - 8ma v ol output low voltage v dd 0.1 v dd v8ma i oz 3-state leakage - 10 10 m aC i pull-up 1 1. pull-up text does not apply o req/, serr/. pull current 25 C m aC
tolerant technology electrical characteristics 6-7 6.2 tolerant technology electrical characteristics the LSI53C1010-33 features tolerant technology, which includes active negation on the scsi drivers and input signal ?ltering on the scsi receivers. active negation actively drives the scsi request, acknowledge, data, and parity signals high rather than allowing them to be passively pulled up by terminators. table 6.13 provides electrical characteristics for se scsi signals. figures 6.3 through 6.7 provide reference information for testing scsi signals. table 6.13 tolerant technology electrical characteristics for se scsi signals 1 symbol parameter min max units test conditions v oh 2 output high voltage 2.2 3.7 v i oh =7ma v ol output low voltage 0.0 0.5 v i ol =48ma v ih input high voltage 1.9 C v C v il input low voltage C 1.0 v referenced to v ss v ik input clamp voltage - 0.66 - 0.77 v v pp = 4.75 v; i 1 = - 20 ma v th threshold, high to low 1.15 1.25 v C v tl threshold, low to high 1.55 1.65 v C v th -v tl hysteresis 300 500 mv C i oh 2 output high current 0 7 ma v oh = 2.4 v i ol output low current 48 C ma v ol = 0.5 v i osh 2 short-circuit output high current 48 C ma short to v dd 3 i osl short-circuit output low current 22 C ma short to v ss i lh input high leakage C 20 m a - 0.5 6-8 speci?cations figure 6.3 rise and fall time test condition figure 6.4 scsi input filtering c p capacitance per pin C 8 pf pqfp t r 2 rise time, 10% to 90% 6.7 14.7 ns figure 6.3 t f fall time, 90% to 10% 5.7 17.2 ns figure 6.3 dv h /dt slew rate low to high 100 470 mv/ns figure 6.3 dv l /dt slew rate high to low 110 440 mv/ns figure 6.3 esd electrostatic discharge 2 C kv mil-std-883c; 3015-7 latch-up 100 C ma C filter delay 20 30 ns figure 6.4 ultra ?lter delay 10 15 ns figure 6.4 ultra2 ?lter delay 5 8 ns figure 6.4 extended ?lter delay 40 60 ns figure 6.4 1. these values are guaranteed by periodic characterization; they are not 100% tested on every device. 2. active negation outputs only: data, parity, sreq/, sack/. scsi mode only (minus pins). table 6.13 tolerant technology electrical characteristics for se scsi signals 1 (cont.) symbol parameter min max units test conditions + - 2.5 v 47 w 20 pf req/ or ack/ input t 1 v th note: t 1 is the input ?ltering period.
tolerant technology electrical characteristics 6-9 figure 6.5 hysteresis of scsi receivers figure 6.6 input current as a function of input voltage 1 0 received logic level input voltage (volts) 1.1 1.3 1.5 1.7 +40 +20 0 - 20 - 40 - 4 0 4 8 12 16 - 0.7 v 8.2 v high-z output active input voltage (volts) input current (milliamperes) 14.4 v
6-10 speci?cations figure 6.7 output current as a function of output voltage 6.3 ac characteristics the ac characteristics described in this section apply over the entire range of operating conditions (refer to section 6.1, dc characteristics ). chip timing is based on simulation at worst case voltage, temperature, and processing. timing was developed with a load capacitance of 50 pf. table 6.14 and figure 6.8 provide external clock timing data. output sink current (milliamperes) 0 - 200 - 400 - 600 - 800 012345 output voltage (volts) output source current (milliamperes) output voltage (volts) 0123 45 100 80 60 40 20 0
ac characteristics 6-11 figure 6.8 external clock table 6.14 external clock symbol parameter min max units t 1 pci bus clock period 30 dc ns scsi clock period 1 1. timing is for an external 40 mhz clock. a quadrupled 40 mhz clock is required for ultra160 scsi operation. 25 25 ns t 2 pci clk low time 2 2. duty cycle not to exceed 60/40. 11 C ns sclk low time 2 10 15 ns t 3 pci clk high time 2 11 C ns sclk high time 2 10 15 ns t 4 pci clk slew rate 1 4 v/ns pci clock spread spectrum modulation frequency 30 33 khz pci clock spread spectrum frequency spread - 19% clk, sclk 1.4 v t 1 t 3 t 4 t 2
6-12 speci?cations table 6.15 and figure 6.9 provide reset input timing data. figure 6.9 reset input table 6.15 reset input symbol parameter min max units t 1 reset pulse width 10 C t clk t 2 reset deasserted setup to clk high 0 C ns t 3 mad setup time to clk high (for con?guring the mad bus only) 20 C ns t 4 mad hold time from clk high (for con?guring the mad bus only) 20 C ns t 1 t 2 t 3 t 4 clk rst/ mad* *when enabled valid data
ac characteristics 6-13 table 6.16 and figure 6.10 provide interrupt output timing data. figure 6.10 interrupt output table 6.16 interrupt output symbol parameter min max units t 1 clk high to irq/ low 2 11 ns t 2 clk high to irq/ high 2 11 ns t 3 irq/ deassertion time 3 C clk t 1 t 2 t 3 irq/ clk
6-14 speci?cations 6.4 pci and external memory interface timing diagrams tables 6.17 through 6.38 and ?gures 6.11 through 6.34 represent signal activity when the LSI53C1010-33 accesses the pci bus. this section includes timing diagrams for access to three groups of memory con?gurations. the ?rst group applies to target timing . the second group applies to initiator timing . the third group applies to external memory timing . note: multiple byte accesses to the external memory bus increase the read or write cycle by 11 clocks for each additional byte. timing diagrams included in this section are: target timing C pci con?guration register read C pci con?guration register write C 32-bit operating registers/scripts ram read C 64-bit operating register/scripts ram read C 32-bit operating register/scripts ram write C 64-bit operating register/scripts ram write initiator timing C nonburst opcode fetch, 32-bit address and data C burst opcode fetch, 32-bit address and data C back-to-back read, 32-bit address and data C back-to-back write, 32-bit address and data C burst read, 32-bit address and data C burst read, 64-bit address and data C burst write, 32-bit address and data C burst write, 64-bit address and data external memory timing C external memory read C external memory write
pci and external memory interface timing diagrams 6-15 C normal/fast memory ( 128 kbytes) single byte access read cycle C normal/fast memory ( 128 kbytes) single byte access write cycle C normal/fast memory ( 128 kbytes) multiple byte access read cycle C normal/fast memory ( 128 kbytes) multiple byte access write cycle C slow memory ( 128 kbytes) read cycle C slow memory ( 128 kbytes) write cycle C 64 kbytes rom read cycle C 64 kbytes rom write cycle 6.4.1 target timing tables 6.17 through 6.22 and ?gures 6.11 through 6.16 describe target timing.
6-16 speci?cations figure 6.11 pci con?guration register read table 6.17 pci con?guration register read symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns data out byte enable addr in cmd t 2 in out t 1 t 2 t 1 t 3 t 2 t 1 t 1 t 2 t 2 t 3 t 3 t 2 t 1 t 3 t 2 t 1 clk (driven by system) frame/ (driven by system) ad[31:0] (driven by master-addr; lsi53c1010-data) c_be[3:0]/ (driven by master) pa r (driven by master-addr; lsi53c1010-data) irdy/ (driven by master) trdy/ (driven by lsi53c1010) stop/ (driven by lsi53c1010) devsel/ (driven by lsi53c1010) idsel (driven by master)
pci and external memory interface timing diagrams 6-17 figure 6.12 pci con?guration register write table 6.18 pci con?guration register write symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns data in byte enable addr in cmd t 2 t 1 t 2 t 1 t 2 t 1 t 1 t 2 t 2 t 3 t 2 t 1 t 3 t 2 t 1 clk (driven by system) frame/ (driven by master) ad[31:0] (driven by master) c_be[3:0]/ (driven by master) pa r (driven by master) irdy/ (driven by master) trdy/ (driven by lsi53c1010) stop/ (driven by lsi53c1010) devsel/ (driven by lsi53c1010) idsel (driven by master) t 1 t 2
6-18 speci?cations figure 6.13 32-bit operating registers/scripts ram read table 6.19 32-bit operating register/scripts ram read symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns data byte enable addr in cmd t 2 t 1 t 2 t 1 t 2 t 1 t 1 t 2 t 2 t 3 t 2 t 1 t 3 clk (driven by system) frame/ (driven by master) ad[31:0] (driven by master-addr; c_be[3:0]/ (driven by master) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by lsi53c1010) stop/ (driven by lsi53c1010) devsel/ (driven by lsi53c1010) out t 3 in out t 3 lsi53c1010-data) lsi53c1010-data)
pci and external memory interface timing diagrams 6-19 figure 6.14 64-bit operating register/scripts ram read table 6.20 64-bit operating register/scripts ram read symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns data byte enable t 2 t 1 t 2 t 1 t 2 t 2 t 2 t 3 t 2 t 1 t 3 clk (driven by system) frame/ (driven by master) ad[31:0] (driven by master-addr; c_be[3:0]/ (driven by master) par; par64 (driven by master-addr; irdy/ (driven by master) trdy/ (driven by lsi53c1010) stop/ (driven by lsi53c1010) devsel/ (driven by lsi53c1010) out t 3 in out t 3 lsi53c1010-data) lsi53c1010-data) t 1 t 2 addr lo addr hi t 1 dual addr t 1 ad[63:32] (driven by master-addr; lsi53c1010-data) hi addr t 2 byte enable t 2 c_be[7:4]/ (driven by master) t 1 bus cmd t 1 t 1 t 2 bus cmd in t 3 req64/ (driven by master) ack64/ (driven by lsi53c1010) t 1
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pci and external memory interface timing diagrams 6-21 figure 6.15 32-bit operating register/scripts ram write table 6.21 32-bit operating register/scripts ram write symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns byte enable addr in cmd t 2 t 1 t 2 t 1 t 2 t 1 t 1 t 2 t 2 t 3 t 2 t 1 t 3 clk (driven by system) frame/ (driven by master) ad[31:0] (driven by master) c_be[3:0]/ (driven by master) pa r (driven by master) irdy/ (driven by master) trdy/ (driven by lsi53c1010) stop/ (driven by lsi53c1010) devsel/ (driven by lsi53c1010) in t 2 data in t 1 in t 2 t 1
6-22 speci?cations table 6.22 64-bit operating register/scripts ram write symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns
pci and external memory interface timing diagrams 6-23 figure 6.16 64-bit operating register/scripts ram write byte enable t 2 t 1 t 2 t 1 t 2 t 1 t 2 t 2 t 3 t 2 t 1 t 3 clk (driven by system) frame/ (driven by master) ad[31:0] (driven by master) c_be[3:0]/ (driven by master) par; par64 (driven by master) irdy/ (driven by master) trdy/ (driven by lsi53c1010) stop/ (driven by lsi53c1010) devsel/ (driven by lsi53c1010) in in t 1 t 2 addr lo addr hi t 1 dual addr t 1 ad[63:32] (driven by master) hi addr byte enable t 2 c_be[7:4]/ (driven by master) t 1 bus cmd t 1 t 2 bus cmd in req64/ (driven by master) ack64/ (driven by lsi53c1010) data in t 2 t 1 t 2 t 1 data in
6-24 speci?cations 6.4.2 initiator timing tables 6.23 through 6.30 and ?gures 6.17 and 6.24 describe initiator timing. table 6.23 nonburst opcode fetch, 32-bit address and data symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns t 4 side signal input setup time 10 C ns t 5 side signal input hold time 0 C ns t 6 clk to side signal output valid 2 12 ns
pci and external memory interface timing diagrams 6-25 figure 6.17 nonburst opcode fetch, 32-bit address and data t 3 t 4 t 1 t 3 t 1 clk (driven by system) gpio0_fetch/ (driven by lsi53c1010) gpio1_master/ (driven by lsi53c1010) req/ (driven by lsi53c1010) pa r (driven by lsi53c1010- irdy/ (driven by lsi53c1010) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) t 1 t 6 t 3 ad[31:0] (driven by lsi53c1010- c_be[3:0]/ (driven by lsi53c1010) t 3 cmd t 2 req64/ (driven by lsi53c1010) ack64/ (driven by lsi53c1010) t 1 t 2 gnt/ (driven by arbiter) frame/ (driven by lsi53c1010) t 5 data in addr out data in addr out byte enable cmd byte enable t 3 t 2 t 2 addr; target-data) addr; target-data)
6-26 speci?cations table 6.24 burst opcode fetch, 32-bit address and data symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns t 4 side signal input setup time 10 C ns t 5 side signal input hold time 0 C ns t 6 clk to side signal output valid 2 12 ns
pci and external memory interface timing diagrams 6-27 figure 6.18 burst opcode fetch, 32-bit address and data t 3 t 4 t 1 t 3 t 1 clk (driven by system) gpio0_fetch/ (driven by lsi53c1010) gpio1_master/ (driven by lsi53c1010) req/ (driven by lsi53c1010) pa r (driven by lsi53c1010- irdy/ (driven by lsi53c1010) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) t 1 t 6 t 3 ad[31:0] (driven by lsi53c1010- c_be[3:0]/ (driven by lsi53c1010) t 3 cmd req64/ (driven by lsi53c1010) ack64/ (driven by lsi53c1010) t 1 t 2 gnt/ (driven by arbiter) frame/ (driven by lsi53c1010) data in data in byte enable t 3 t 2 t 2 addr; target-data) addr; target-data) addr out out in in t 5 t 3 t 2
6-28 speci?cations table 6.25 back-to-back read, 32-bit address and data symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns t 4 side signal input setup time 10 C ns t 5 side signal input hold time 0 C ns t 6 clk to side signal output valid 2 12 ns
pci and external memory interface timing diagrams 6-29 figure 6.19 back-to-back read, 32-bit address and data t 4 t 1 t 3 t 1 clk (driven by system) gpio0_fetch/ (driven by lsi53c1010) gpio1_master/ (driven by lsi53c1010) req/ (driven by lsi53c1010) pa r (driven by lsi53c1010- irdy/ (driven by lsi53c1010) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) t 1 t 6 t 3 ad[31:0] (driven by lsi53c1010- c_be[3:0]/ (driven by lsi53c1010) t 3 cmd t 2 req64/ (driven by lsi53c1010) ack64/ (driven by lsi53c1010) t 1 t 2 gnt/ (driven by arbiter) frame/ (driven by lsi53c1010) t 5 data in addr out data in addr out cmd t 3 t 2 t 2 addr; target-data) addr; target-data) t 3 be be out in out in
6-30 speci?cations table 6.26 back-to-back write, 32-bit address and data symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns t 4 side signal input setup time 10 C ns t 5 side signal input hold time 0 C ns t 6 clk to side signal output valid 2 12 ns
pci and external memory interface timing diagrams 6-31 figure 6.20 back-to-back write, 32-bit address and data t 9 t 4 t 3 clk (driven by system) gpio0_fetch/ (driven by lsi53c1010) gpio1_master/ (driven by lsi53c1010) req/ (driven by lsi53c1010) pa r (driven by lsi53c1010- irdy/ (driven by lsi53c1010) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) t 6 t 3 ad[31:0] (driven by lsi53c1010- c_be[3:0]/ (driven by lsi53c1010) t 3 cmd t 2 req64/ (driven by lsi53c1010) ack64/ (driven by lsi53c1010) t 10 gnt/ (driven by arbiter) frame/ (driven by lsi53c1010) t 5 addr out addr out cmd t 3 addr; target-data) addr; target-data) t 3 be be data out t 3 t 3 t 3 data out
6-32 speci?cations table 6.27 burst read, 32-bit address and data symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns
pci and external memory interface timing diagrams 6-33 figure 6.21 burst read, 32-bit address and data t 1 t 2 clk (driven by system) gpio0_fetch/ (driven by lsi53c1010) gpio1_master/ (driven by lsi53c1010) req/ (driven by lsi53c1010) pa r (driven by lsi53c1010- irdy/ (driven by lsi53c1010) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) ad[31:0] (driven by lsi53c1010- c_be[3:0]/ (driven by lsi53c1010) t 3 cmd gnt/ (driven by arbiter) frame/ (driven by lsi53c1010) addr out t 2 addr; target-data) addr; target-data) be data in out in in
6-34 speci?cations table 6.28 burst read, 64-bit address and data symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns
pci and external memory interface timing diagrams 6-35 figure 6.22 burst read, 64-bit address and data t 1 t 2 clk (driven by system) gpio0_fetch/ (driven by lsi53c1010) gpio1_master/ (driven by lsi53c1010) req/ (driven by lsi53c1010) par; par64 (addr drvn by lsi53c1010;- irdy/ (driven by lsi53c1010) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) ad[31:0] (driven by lsi53c1010- c_be[3:0]/ (driven by lsi53c1010) t 3 gnt/ (driven by arbiter) frame/ (driven by lsi53c1010) addr out lo t 2 addr; target-data) data drvn by target) be data in out in in req64/ (driven by lsi53c1010) ack64/ (driven by target) addr out hi t 2 bus dual addr cmd ad[63:32] (driven by lsi53c1010- c_be[7:4]/ (driven by lsi53c1010) addr; target-data) be data in hi address bus cmd in
6-36 speci?cations table 6.29 burst write, 32-bit address and data symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns
pci and external memory interface timing diagrams 6-37 figure 6.23 burst write, 32-bit address and data t 1 clk (driven by system) gpio0_fetch/ (driven by lsi53c1010) gpio1_master/ (driven by lsi53c1010) req/ (driven by lsi53c1010) pa r (driven by lsi53c1010) irdy/ (driven by lsi53c1010) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) ad[31:0] (driven by lsi53c1010) c_be[3:0]/ (driven by lsi53c1010) t 3 cmd gnt/ (driven by arbiter) frame/ (driven by lsi53c1010) addr out t 2 be data out data out t 1 t 2
6-38 speci?cations table 6.30 burst write, 64-bit address and data symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns
pci and external memory interface timing diagrams 6-39 figure 6.24 burst write, 64-bit address and data t 1 clk (driven by system) gpio0_fetch/ (driven by lsi53c1010) gpio1_master/ (driven by lsi53c1010) req/ (driven by lsi53c1010) par; par64 (driven by lsi53c1010) irdy/ (driven by lsi53c1010) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) ad[31:0] (driven by lsi53c1010) c_be[3:0]/ (driven by lsi53c1010) t 3 gnt/ (driven by arbiter) frame/ (driven by lsi53c1010) addr out lo t 2 req64/ (driven by lsi53c1010) ack64/ (driven by target) addr out hi t 2 bus dual addr cmd ad[63:32] (driven by lsi53c1010) c_be[7:4]/ (driven by lsi53c1010) hi address bus cmd t 1 data out data out be be data out data out be be t 3 t 1 t 2
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pci and external memory interface timing diagrams 6-41 6.4.3 external memory timing tables 6.31 through 6.38 and ?gures 6.25 through 6.34 describe external memory timing. table 6.31 external memory read symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns t 11 address setup to mas/ high 25 C ns t 12 address hold from mas/ high 15 C ns t 13 mas/ pulse width 25 C ns t 14 mce/ low to data clocked in 150 C ns t 15 address valid to data clocked in 205 C ns t 16 moe/ low to data clocked in 100 C ns t 17 data hold from address, moe/, mce/ change 0 C ns t 19 data setup to clk high 5 C ns
6-42 speci?cations figure 6.25 external memory read clk (driven by system) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by lsi53c1010) stop/ (driven by lsi53c1010) devsel/ (driven by lsi53c1010) ad[31:0] (driven by master-addr; c_be[3:0]/ (driven by master) frame/ (driven by master) data driven by memory) 1234 56 78910 lsi53c1010-data) addr in byte enable lsi53c1010-data) mad (addr drvn by lsi53c1010; high order address middle order address low order address mas1/ (driven by lsi53c1010) mas0/ (driven by lsi53c1010) mce/ (driven by lsi53c1010) moe/ (driven by lsi53c1010) mwe/ (driven by lsi53c1010) t 1 t 2 t 1 t 2 cmd in t 1 t 2 t 1 t 2 t 1 t 3 t 13 t 11 t 12 t 15
pci and external memory interface timing diagrams 6-43 figure 6.25 external memory read (cont.) clk (driven by system) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by lsi53c1010) stop/ (driven by lsi53c1010) devsel/ (driven by lsi53c1010) ad[31:0] (driven by master-addr; c_be[3:0]/ (driven by master) frame/ (driven by master) data driven by memory) 11 12 13 14 15 16 17 18 19 20 lsi53c1010-data) data out lsi53c1010-data) mad (addr driven by lsi53c1010; mas1/ (driven by lsi53c1010) mas0/ (driven by lsi53c1010) mce/ (driven by lsi53c1010) moe/ (driven by lsi53c1010) mwe/ (driven by lsi53c1010) t 3 t 2 t 2 t 15 21 t 3 out t 3 t 3 data in t 19 t 17 t 14 t 16
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pci and external memory interface timing diagrams 6-45 table 6.32 external memory write symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid 2 11 ns t 11 address setup to mas/ high 25 C ns t 12 address hold from mas/ high 15 C ns t 13 mas/ pulse width 25 C ns t 20 data setup to mwe/ low 30 C ns t 21 data hold from mwe/ high 20 C ns t 22 mwe/ pulse width 100 C ns t 23 address setup to mwe/ low 60 C ns t 24 mce/ low to mwe/ high 120 C ns t 25 mce/ low to mwe/ low 25 C ns t 26 mwe/ high to mce/ high 25 C ns
6-46 speci?cations figure 6.26 external memory write clk (driven by system) pa r irdy/ (driven by master) trdy/ (driven by lsi53c1010) stop/ (driven by lsi53c1010) devsel/ (driven by lsi53c1010) ad[31:0] c_be[3:0]/ (driven by master) frame/ (driven by master) 12 3 4 5 6 78 910 addr in mad (driven by lsi53c1010) high order address middle order address low order address mas1/ (driven by lsi53c1010) mas0/ (driven by lsi53c1010) mce/ (driven by lsi53c1010) moe/ (driven by lsi53c1010) mwe/ (driven by lsi53c1010) t 1 t 2 t 1 t 2 cmd in t 1 t 2 t 1 t 2 t 1 t 13 t 11 t 12 data in t 2 t 1 byte enable t 2 in t 1 t 2 t 2 t 3 t 3 t 3 (driven by master) (driven by master) t 23
pci and external memory interface timing diagrams 6-47 figure 6.26 external memory write (cont.) clk (driven by system) pa r irdy/ (driven by master) trdy/ (driven by lsi53c1010) stop/ (driven by lsi53c1010) devsel/ (driven by lsi53c1010) ad[31:0] c_be[3:0]/ (driven by master) frame/ (driven by master) 11 12 13 14 15 16 17 18 19 20 mad (driven by lsi53c1010) mas1/ (driven by lsi53c1010) mas0/ (driven by lsi53c1010) mce/ (driven by lsi53c1010) moe/ (driven by lsi53c1010) mwe/ (driven by lsi53c1010) 21 t 24 t 22 byte enable t 25 t 26 t 21 t 20 t 23 (driven by master) (driven by master) data out
6-48 speci?cations figure 6.27 normal/fast memory ( 3 128 kbytes) single byte access read cycle table 6.33 normal/fast memory ( 3 128 kbytes) single byte access read cycle symbol parameter min max unit t 11 address setup to mas/ high 25 C ns t 12 address hold from mas/ high 15 C ns t 13 mas/ pulse width 25 C ns t 14 mce/ low to data clocked in 150 C ns t 15 address valid to data clocked in 205 C ns t 16 moe/ low to data clocked in 100 C ns t 17 data hold from address, moe/, mce/ change 0 C ns t 18 address out from moe/, mce/ high 50 C ns t 19 data setup to clk high 5 C ns clk (driven by system) data driven by memory) 1234 56 78910 mad (addr drvn by lsi53c1010; high order address middle order address low order address mas1/ (driven by lsi53c1010) mas0/ (driven by lsi53c1010) mce/ (driven by lsi53c1010) moe/ (driven by lsi53c1010) mwe/ (driven by lsi53c1010) t 13 t 11 t 12 t 15 t 14 t 16
pci and external memory interface timing diagrams 6-49 figure 6.27 normal/fast memory ( 3 128 kbytes) single byte access read cycle (cont.) clk (driven by system) data driven by memory) 11 12 13 14 15 16 17 18 19 20 mad (addr driven by lsi53c1010; mas1/ (driven by lsi53c1010) mas0/ (driven by lsi53c1010) mce/ (driven by lsi53c1010) moe/ (driven by lsi53c1010) mwe/ (driven by lsi53c1010) t 15 21 read data t 19 t 17 t 14 t 16 valid t 18
6-50 speci?cations figure 6.28 normal/fast memory ( 3 128 kbytes) single byte access write cycle table 6.34 normal/fast memory ( 3 128 kbytes) single byte access write cycle symbol parameter min max unit t 11 address setup to mas/ high 25 C ns t 12 address hold from mas/ high 15 C ns t 13 mas/ pulse width 25 C ns t 20 data setup to mwe/ low 30 C ns t 21 data hold from mwe/ high 20 C ns t 22 mwe/ pulse width 100 C ns t 23 address setup to mwe/ low 60 C ns t 24 mce/ low to mwe/ high 120 C ns t 25 mce/ low to mwe/ low 25 C ns t 26 mwe/ high to mce/ high 25 C ns clk (driven by system) 12 3 4 5 6 78 910 mad (driven by lsi53c1010) high order address middle order address low order address mas1/ (driven by lsi53c1010) mas0/ (driven by lsi53c1010) mce/ (driven by lsi53c1010) moe/ (driven by lsi53c1010) mwe/ (driven by lsi53c1010) t 13 t 11 t 12 t 24 t 25 write data valid t 23 t 20
pci and external memory interface timing diagrams 6-51 figure 6.28 normal/fast memory ( 3 128 kbytes) single byte access write cycle (cont.) clk (driven by system) 11 12 13 14 15 16 17 18 19 20 mad (driven by lsi53c1010) mas1/ (driven by lsi53c1010) mas0/ (driven by lsi53c1010) mce/ (driven by lsi53c1010) moe/ (driven by lsi53c1010) mwe/ (driven by lsi53c1010) 21 t 24 t 25 t 21 valid write data t 20 t 23 t 22 t 26
6-52 speci?cations figure 6.29 normal/fast memory ( 3 128 kbytes) multiple byte access read cycle clk (driven by system) pa r (driven by lsi53c1010- irdy/ (driven by master) trdy/ (driven by lsi53c1010) stop/ (driven by lsi53c1010) devsel/ (driven by lsi53c1010) ad[31:0] (driven by lsi53c1010- c_be[3:0]/ (driven by master) frame/ (driven by master) master-addr; data) master-addr;-data) mad (addr driven by lsi53c1010 mas1/ (driven by lsi53c1010) mas0/ (driven by lsi53c1010) mce/ (driven by lsi53c1010) moe/ (driven by lsi53c1010) mwe/ (driven by lsi53c1010) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 in addr cmd byte enable in data driven by memory) high order address order address middle order address low
pci and external memory interface timing diagrams 6-53 figure 6.29 normal/fast memory ( 3 128 kbytes) multiple byte access read cycle (cont.) clk (driven by system) pa r (driven by lsi53c1010- irdy/ (driven by master) trdy/ (driven by lsi53c1010) stop/ (driven by lsi53c1010) devsel/ (driven by lsi53c1010) ad[31:0] (driven by lsi53c1010- c_be[3:0]/ (driven by master) frame/ (driven by master) master-addr; data) master-addr;-data) mad (addr driven by lsi53c1010 mas1/ (driven by lsi53c1010) mas0/ (driven by lsi53c1010) mce/ (driven by lsi53c1010) moe/ (driven by lsi53c1010) mwe/ (driven by lsi53c1010) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 byte enable data driven by memory) 16 32 33 data out out data in low order address data in
6-54 speci?cations figure 6.30 normal/fast memory ( 3 128 kbytes) multiple byte access write cycle clk (driven by system) pa r irdy/ (driven by master) trdy/ (driven by lsi53c1010) stop/ (driven by lsi53c1010) devsel/ (driven by lsi53c1010) ad[31:0] c_be[3:0]/ (driven by master) frame/ (driven by master) mad (driven by lsi53c1010) mas1/ (driven by lsi53c1010) mas0/ (driven by lsi53c1010) mce/ (driven by lsi53c1010) moe/ (driven by lsi53c1010) mwe/ (driven by lsi53c1010) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 in addr cmd in high order address order address middle order address low data out data in byte enable in (driven by master) (driven by master)
pci and external memory interface timing diagrams 6-55 figure 6.30 normal/fast memory ( 3 128 kbytes) multiple byte access write cycle (cont.) clk (driven by system) pa r irdy/ (driven by master) trdy/ (driven by lsi53c1010) stop/ (driven by lsi53c1010) devsel/ (driven by lsi53c1010) ad[31:0] c_be[3:0]/ (driven by master) frame/ (driven by master) mad (driven by lsi53c1010) mas1/ (driven by lsi53c1010) mas0/ (driven by lsi53c1010) mce/ (driven by lsi53c1010) moe/ (driven by lsi53c1010) mwe/ (driven by lsi53c1010) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 byte enable 16 32 33 low order address data in data out (driven by master) (driven by master)
6-56 speci?cations figure 6.31 slow memory ( 3 128 kbytes) read cycle table 6.35 slow memory ( 3 128 kbytes) read cycle symbol parameter min max unit t 11 address setup to mas/ high 25 C ns t 12 address hold from mas/ high 15 C ns t 13 mas/ pulse width 25 C ns t 14 mce/ low to data clocked in 150 C ns t 15 address valid to data clocked in 205 C ns t 16 moe/ low to data clocked in 100 C ns t 17 data hold from address, moe/, mce/ change 0 C ns t 18 address out from moe/, mce/ high 50 C ns t 19 data setup to clk high 5 C ns clk (driven by system) 1234 56 78910 mad (addr drvn by lsi53c1010 high order address middle order address low order address mas1/ (driven by lsi53c1010) mas0/ (driven by lsi53c1010) mce/ (driven by lsi53c1010) moe/ (driven by lsi53c1010) mwe/ (driven by lsi53c1010) t 13 t 11 t 12 t 15 t 16 data drvn by mem) t 14
pci and external memory interface timing diagrams 6-57 figure 6.31 slow memory ( 3 128 kbytes) read cycle (cont.) clk (driven by system) data driven by memory) 11 12 13 14 15 16 17 18 19 20 mad (addr driven by lsi53c1010; mas1/ (driven by lsi53c1010) mas0/ (driven by lsi53c1010) mce/ (driven by lsi53c1010) moe/ (driven by lsi53c1010) mwe/ (driven by lsi53c1010) t 15 21 read data t 19 t 17 t 14 t 16 valid t 18 22
6-58 speci?cations figure 6.32 slow memory ( 3 128 kbytes) write cycle table 6.36 slow memory ( 3 128 kbytes) write cycle symbol parameter min max unit t 11 address setup to mas/ high 25 C ns t 12 address hold from mas/ high 15 C ns t 13 mas/ pulse width 25 C ns t 20 data setup to mwe/ low 30 C ns t 21 data hold from mwe/ high 20 C ns t 22 mwe/ pulse width 100 C ns t 23 address setup to mwe/ low 60 C ns t 24 mce/ low to mwe/ high 120 C ns t 25 mce/ low to mwe/ low 25 C ns t 26 mwe/ high to mce/ high 25 C ns clk (driven by system) 1234 56 78910 mad (driven by lsi53c1010) high order address middle order address low order address mas1/ (driven by lsi53c1010) mas0/ (driven by lsi53c1010) mce/ (driven by lsi53c1010) moe/ (driven by lsi53c1010) mwe/ (driven by lsi53c1010) t 13 t 11 t 12 t 24 t 25 write data valid t 23 t 20
pci and external memory interface timing diagrams 6-59 figure 6.32 slow memory ( 3 128 kbytes) write cycle (cont.) clk (driven by system) 11 12 13 14 15 16 17 18 19 20 mad (driven by lsi53c1010) mas1/ (driven by lsi53c1010) mas0/ (driven by lsi53c1010) mce/ (driven by lsi53c1010) moe/ (driven by lsi53c1010) mwe/ (driven by lsi53c1010) 21 t 24 t 25 t 21 valid write data t 20 t 23 t 22 t 26
6-60 speci?cations figure 6.33 64 kbytes rom read cycle table 6.37 64 kbytes rom read cycle symbol parameter min max unit t 11 address setup to mas/ high 25 C ns t 12 address hold from mas/ high 15 C ns t 13 mas/ pulse width 25 C ns t 14 mce/ low to data clocked in 150 C ns t 15 address valid to data clocked in 205 C ns t 16 moe/ low to data clocked in 100 C ns t 17 data hold from address, moe/, mce/ change 0 C ns t 18 address out from moe/, mce/ high 50 C ns t 19 data setup to clk high 5 C ns clk (driven by system) 1234 5 6 78910 high order address low order address mas1/ (driven by lsi53c1010) mas0/ (driven by lsi53c1010) mce/ (driven by lsi53c1010) moe/ (driven by lsi53c1010) mwe/ (driven by lsi53c1010) t 13 t 11 t 12 t 15 t 16 11 12 13 14 1 5 valid read data t 14 t 18 t 19 t 17 mad (addr drvn by lsi53c1010; data drvn by mem)
pci and external memory interface timing diagrams 6-61 figure 6.34 64 kbytes rom write cycle table 6.38 64 kbytes rom write cycle symbol parameter min max unit t 11 address setup to mas/ high 25 C ns t 12 address hold from mas/ high 15 C ns t 13 mas/ pulse width 25 C ns t 20 data setup to mwe/ low 30 C ns t 21 data hold from mwe/ high 20 C ns t 22 mwe/ pulse width 100 C ns t 23 address setup to mwe/ low 60 C ns t 24 mce/ low to mwe/ high 120 C ns t 25 mce/ low to mwe/ low 25 C ns t 26 mwe/ high to mce/ high 25 C ns clk (driven by system) 1234 5 6 78910 mad (driven by lsi53c1010) high order address low order address mas1/ (driven by lsi53c1010) mas0/ (driven by lsi53c1010) mce/ (driven by lsi53c1010) moe/ (driven by lsi53c1010) mwe/ (driven by lsi53c1010) t 13 t 11 t 12 t 22 11 12 13 t 24 t 21 valid write data t 23 t 25 t 26 t 20
6-62 speci?cations 6.5 scsi timing diagrams tables 6.39 through 6.50 and ?gures 6.35 through 6.40 and describe the lsi53c1010 scsi timing. figure 6.35 initiator asynchronous send table 6.39 initiator asynchronous send symbol parameter min max units t 1 sack/ asserted from sreq/ asserted 5 C ns t 2 sack/ deasserted from sreq/ deasserted 5 C ns t 3 data setup to sack/ asserted 55 C ns t 4 data hold from sreq/ deasserted 0 C ns valid n valid n + 1 n + 1 n + 1 n n t 1 t 2 t 3 t 4 sreq/ sack/ sd[15:0]/, sdp[1:0]/
scsi timing diagrams 6-63 figure 6.36 initiator asynchronous receive figure 6.37 target asynchronous send table 6.40 initiator asynchronous receive symbol parameter min max units t 1 sack/ asserted from sreq/ asserted 5 C ns t 2 sack/ deasserted from sreq/ deasserted 5 C ns t 3 data setup to sreq/ asserted 0 C ns t 4 data hold from sack/ asserted 0 C ns valid n valid n + 1 n + 1 n + 1 n n t 1 t 2 t 3 t 4 sreq/ sack/ sd[15:0]/, sdp[1:0]/ table 6.41 target asynchronous send symbol parameter min max units t 1 sreq/ deasserted from sack/ asserted 5 C ns t 2 sreq/ asserted from sack/ deasserted 5 C ns t 3 data setup to sreq/ asserted 55 C ns t 4 data hold from sack/ asserted 0 C ns valid n valid n + 1 n + 1 n + 1 n n t 1 t 2 t 3 t 4 sreq/ sack/ sd[15:0]/, sdp[1:0]/
6-64 speci?cations figure 6.38 target asynchronous receive table 6.42 target asynchronous receive symbol parameter min max units t 1 sreq/ deasserted from sack/ asserted 5 C ns t 2 sreq/ asserted from sack/ deasserted 5 C ns t 3 data setup to sack/ asserted 0 C ns t 4 data hold from sreq/ deasserted 0 C ns valid n valid n + 1 n + 1 n + 1 n n t 1 t 2 t 3 t 4 sreq/ sack/ sd[15:0]/, sdp[1:0]/
scsi timing diagrams 6-65 table 6.43 scsi-1 transfers (se 5.0 mbytes) symbol parameter min max units t st1 send sreq/ or sack/ assertion pulse width 80 C ns t st2 send sreq/ or sack/ deassertion pulse width 80 C ns t st1 receive sreq/ or sack/ assertion pulse width 70 C ns t st2 receive sreq/ or sack/ deassertion pulse width 70 C ns t st3 send data setup to sreq/ or sack/ asserted 24 C ns t st4 send data hold from sreq/ or sack/ asserted 54 C ns t st5 receive data setup to sreq/ or sack/ asserted 14 C ns t st6 receive data hold from sreq/ or sack/ asserted 24 C ns table 6.44 scsi-2 fast transfers 10.0 mbytes (8-bit transfers) or 20.0 mbytes (16-bit transfers) 40 mhz clock symbol parameter min max units t st1 send sreq/ or sack/ assertion pulse width 30 C ns t st2 send sreq/ or sack/ deassertion pulse width 30 C ns t st1 receive sreq/ or sack/ assertion pulse width 22 C ns t st2 receive sreq/ or sack/ deassertion pulse width 22 C ns t st3 send data setup to sreq/ or sack/ asserted 24 C ns t st4 send data hold from sreq/ or sack/ asserted 34 C ns t st5 receive data setup to sreq/ or sack/ asserted 14 C ns t st6 receive data hold from sreq/ or sack/ asserted 24 C ns
6-66 speci?cations table 6.45 ultra scsi se transfers 20.0 mbytes (8-bit transfers) or 40.0 mbytes (16-bit transfers) quadrupled 40 mhz clock 1 1. note: for fast scsi, set the tolerant enable bit (bit 7 in scsi test three (stest3) ). symbol parameter min max unit t st1 send sreq/ or sack/ assertion pulse width 15 C ns t st2 send sreq/ or sack/ deassertion pulse width 15 C ns t st1 receive sreq/ or sack/ assertion pulse width 11 C ns t st2 receive sreq/ or sack/ deassertion pulse width 11 C ns t st3 send data setup to sreq/ or sack/ asserted 12 C ns t st4 send data hold from sreq/ or sack/ asserted 17 C ns t st5 receive data setup to sreq/ or sack/ asserted 6 C ns t st6 receive data hold from sreq/ or sack/ asserted 11 C ns
scsi timing diagrams 6-67 figure 6.39 initiator and target st synchronous transfer table 6.46 ultra2 scsi transfers 40.0 mbyte (8-bit transfers) or 80.0 mbyte (16-bit transfers) quadrupled 40 mhz clock symbol parameter min max unit t st1 send sreq/ or sack/ assertion pulse width 8 C ns t st2 send sreq/ or sack/ deassertion pulse width 8 C ns t st1 receive sreq/ or sack/ assertion pulse width 6.5 C ns t st2 receive sreq/ or sack/ deassertion pulse width 6.5 C ns t st3 send data setup to sreq/ or sack/ asserted 9.5 C ns t st4 send data hold from sreq/ or sack/ asserted 9.5 C ns t st5 receive data setup to sreq/ or sack/ asserted 4.5 C ns t st6 receive data hold from sreq/ or sack/ asserted 4.5 C ns t st1 sreq/sack send data (sd[15:0]/) receive data (sd[15:0]/) t st2 t st3 t st4 t st6 t st5
6-68 speci?cations table 6.47 scsi-2 fast transfers 10.0 mbytes (8-bit transfers) or 20.0 mbytes (16-bit transfers) 40 mhz clock symbol parameter min max unit t dt1 send sreq/ or sack/ assertion pulse width 92 C ns t dt2 send sreq/ or sack/ deassertion pulse width 92 C ns t dt1 receive sreq/ or sack/ assertion pulse width 80 C ns t dt2 receive sreq/ or sack/ deassertion pulse width 80 C ns t dt3 send data setup to sreq/ or sack/ transition 40 C ns t dt4 send data hold from sreq/ or sack/ transition 40 C ns t dt5 receive data setup to sreq/ or sack/ transition 10 C ns t dt6 receive data hold from sreq/ or sack/ transition 10 C ns t dt7 send crc request setup to sreq/ transition 50 C ns t dt8 send crc request hold to sreq/ transition 40 C ns t dt9 receive crc request setup to sreq/ transition 17 C ns t dt10 receive crc request hold to sreq/ transition 10 C ns
scsi timing diagrams 6-69 table 6.48 ultra scsi se transfers 20.0 mbytes (8-bit transfers) or 40.0 mbytes (16-bit transfers) quadrupled 40 mhz clock symbol parameter min max unit t dt1 send sreq/ or sack/ assertion pulse width 46 C ns t dt2 send sreq/ or sack/ deassertion pulse width 46 C ns t dt1 receive sreq/ or sack/ assertion pulse width 40 C ns t dt2 receive sreq/ or sack/ deassertion pulse width 40 C ns t dt3 send data setup to sreq/ or sack/ transition 20 C ns t dt4 send data hold from sreq/ or sack/ transition 20 C ns t dt5 receive data setup to sreq/ or sack/ transition 5 C ns t dt6 receive data hold from sreq/ or sack/ transition 5 C ns t dt7 send crc request setup to sreq/ transition 30 C ns t dt8 send crc request hold to sreq/ transition 20 C ns t dt9 receive crc request setup to sreq/ transition 12 C ns t dt10 receive crc request hold to sreq/ transition 5 C ns
6-70 speci?cations table 6.49 ultra2 scsi transfers 40.0 mbyte (8-bit transfers) or 80.0 mbyte (16-bit transfers) quadrupled 40 mhz clock symbol parameter min max unit t dt1 send sreq/ or sack/ assertion pulse width 23 C ns t dt2 send sreq/ or sack/ deassertion pulse width 23 C ns t dt1 receive sreq/ or sack/ assertion pulse width 20 C ns t dt2 receive sreq/ or sack/ deassertion pulse width 20 C ns t dt3 send data setup to sreq/ or sack/ transition 10 C ns t dt4 send data hold from sreq/ or sack/ transition 10 C ns t dt5 receive data setup to sreq/ or sack/ transition 2.5 C ns t dt6 receive data hold from sreq/ or sack/ transition 2.5 C ns t dt7 send crc request setup to sreq/ transition 20 C ns t dt8 send crc request hold to sreq/ transition 10 C ns t dt9 receive crc request setup to sreq/ transition 9.5 C ns t dt10 receive crc request hold to sreq/ transition 2.5 C ns
scsi timing diagrams 6-71 figure 6.40 initiator and target dt synchronous transfer table 6.50 ultra160 scsi transfers 160.0 mbyte (16-bit transfers) quadrupled 40 mhz clock symbol parameter min max unit t dt1 send sreq/ or sack/ assertion pulse width 11.5 C ns t dt2 send sreq/ or sack/ deassertion pulse width 11.5 C ns t dt1 receive sreq/ or sack/ assertion pulse width 10 C ns t dt2 receive sreq/ or sack/ deassertion pulse width 10 C ns t dt3 send data setup to sreq/ or sack/ transition 5 C ns t dt4 send data hold from sreq/ or sack/ transition 5 C ns t dt5 receive data setup to sreq/ or sack/ transition 1.25 C ns t dt6 receive data hold from sreq/ or sack/ transition 1.25 C ns t dt7 send crc request setup to sreq/ transition 15 C ns t dt8 send crc request hold to sreq/ transition 5 C ns t dt9 receive crc request setup to sreq/ transition 8.25 C ns t dt10 receive crc request hold to sreq/ transition 1.25 C ns t dt1 sreq/sack send data (sd[15:0]/) receive data (sd[15:0]/) t dt2 t dt5 send crc request (dp0/) receive crc request (dp0/) t dt3 t dt4 t dt6 t dt5 t dt6 t dt3 t dt4 t dt8 t dt7 t dt10 t dt9
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package drawings 6-73 6.6 package drawings the signal locations on the 329 ball grid array (bga) are illustrated in figure 6.41 . the signal names are listed alphabetically, in table 6.51 , and numerically, in table 6.52 . figure 6.42 is the pinout for the bga and figure 6.43 is the package drawing for the LSI53C1010-33.
6-74 speci?cations figure 6.41 left half of the LSI53C1010-33 329 bga chip - top view 123456789101112 a nc test_pd a_sd12+ a_sd13+ a_sd15+ a_sd0+ a_sd2 - a_sd4 - a_sd6 - a_sdp0 - v dd - bias2 a_sbsy+ a bnc v dd _a nc a_sd13 - a_sd15 - a_sd0 - a_sd1+ a_sd3+ a_sd5+ a_sd7+ a_satn - a_satn+ b c test_ rst/ v ss _a v ss _io a_sd12 - a_sd14 - a_sdp1 - a_sd1 - a_sd2+ a_sd4+ a_sd6+ a_sdp0+ a_sbsy - c d tck v ss _ core v dd _ core v ss _io a_sd14+ a_sdp1+ v dd _io a_sd3 - a_sd5 - v dd _io a_sd7 - v ss _io d e tdo tdi tms v dd _ core e falt_ inta/ intb/ v ss _ core inta/ f g rst/ int_dir alt_ intb/ v dd _io g h ad31 req/ clk gnt/ h j ad27 ad28 ad30 ad29 j k c_be3/ ad24 ad26 v dd _io v ss _io v ss _io v ss _io k l ad23 ad22 idsel ad25 v ss _io v ss _io v ss _io l m ad21 ad19 ad20 v ss _io v ss _io v ss _io v ss _io m n ad17 ad18 ad16 irdy/ v ss _io v ss _io v ss _io n p c_be2/ frame/ trdy/ v dd _io v ss _io v ss _io v ss _io p r devsel/ stop/ serr/ perr/ r t par c_be1/ ad14 ad15 t u ad13 ad12 ad11 v dd _io u v ad10 ad9 c_be0/ ad8 v w ad7 ad6 ad4 ad5 w y ad3 ad2 ad0 v ss _io ad63 ad59 v dd _io ad52 ad48 v dd _io ad44 v ss _io y aa ad1 req64/ v ss _io c_be7/ par64 ad60 ad56 ad53 ad49 ad45 ad41 ad37 aa ab ack64/ v ss _ core v dd _ core c_be5/ ad62 ad58 ad55 ad51 ad47 ad43 ad39 ad36 ab ac v dd _ core v ss _ core c_be6/ c_be4/ ad61 ad57 ad54 ad50 ad46 ad42 ad40 ad38 ac 123456789101112
package drawings 6-75 figure 6.41 right half of the LSI53C1010-33 329 bga chip - top view 13 14 15 16 17 18 19 20 21 22 23 a nc a_sack+ a_smsg+ a_sc_d+ a_sreq+ a_sd8 - a_sd10 - a_ diffsens sclk v ss _ core nc a b nc a_srst - a_ssel - nc a_si_o - a_sd8+ a_sd10+ v ss _a nc v dd _ core v dd _ core b c a_sack - a_smsg - a_sc_d - a_sreq - a_si_o+ a_sd9+ a_sd11+ v dd _a v ss _io scan_ mode test_ hsc c d a_srst+ v dd _io a_ssel+ nc v dd _io a_sd9 - a_sd11 - v ss _io v ss _ core b_sd12 - b_sd12+ d e b_sd13+ b_sd13 - b_sd14 - b_sd14+ e f b_sd15+ b_sd15 - b_sdp1 - b_sdp1+ f g v dd _io b_sd0 - b_sd0+ b_sd1 - g h b_sd2 - b_sd1+ b_sd2+ b_sd3 - h j b_sd4 - b_sd3+ b_sd4+ b_sd5 - j kv ss _io v ss _io v dd _io b_sd5+ b_sd6+ b_sd7 - k lv ss _io v ss _io b_sd6 - b_sd7+ b_sdp0+ b_sdp0 - l mv ss _io v ss _io v ss _io rbias v dd _bias b_satn - m nv ss _io v ss _io b_sack - b_sbsy+ b_satn+ b_sbsy - n pv ss _io v ss _io v dd _io b_sack+ nc nc p r b_smsg - b_smsg+ b_srst+ b_srst - r t b_sc_d - b_sc_d+ b_ssel+ b_ssel - t u v dd _io b_sreq - nc nc u v b_si_o+ b_sd8 - b_si_o - b_sreq+ v w b_sd9+ b_sd10 - b_sd9 - b_sd8+ w yv dd _ core v dd _io v ss _ core a_gpio1_ master/ v dd _io moe/_ testout mad7 v ss _io b_ diffsens b_sd11 - b_sd10+ y aa ad33 b_gpio0_ fetch/ b_gpio3 a_gpio2 mas1/ mce/ mad6 mad3 v ss _io v ss _ core b_sd11+ aa ab ad35 reserved b_gpio2 a_gpio0_ fetch/ a_gpio4 v dd _ core v ss _ core mad4 mad1 nc v dd _ core ab ac ad34 ad32 b_gpio1_ master/ b_gpio4 a_gpio3 mas0/ mwe/ mad5 v ss _ core mad2 mad0 ac 13 14 15 16 17 18 19 20 21 22 23
6-76 speci?cations table 6.51 signal names and bga position a_diffsens a20 a_gpio0_ fetch/ ab16 a_gpio1_ master/ y16 a_gpio2 aa16 a_gpio3 ac17 a_gpio4 ab17 a_sack - c13 a_sack+ a14 a_satn - b11 a_satn+ b12 a_sbsy - c12 a_sbsy+ a12 a_sc_d - c15 a_sc_d+ a16 a_sd0 - b6 a_sd0+ a6 a_sd1 - c7 a_sd1+ b7 a_sd2 - a7 a_sd2+ c8 a_sd3 - d8 a_sd3+ b8 a_sd4 - a8 a_sd4+ c9 a_sd5 - d9 a_sd5+ b9 a_sd6 - a9 a_sd6+ c10 a_sd7 - d11 a_sd7+ b10 a_sd8 - a18 a_sd8+ b18 a_sd9 - d18 a_sd9+ c18 a_sd10 - a19 a_sd10+ b19 a_sd11 - d19 a_sd11+ c19 a_sd12 - c4 a_sd12+ a3 a_sd13 - b4 a_sd13+ a4 a_sd14 - c5 a_sd14+ d5 a_sd15 - b5 a_sd15+ a5 a_sdp0 - a10 a_sdp0+ c11 a_sdp1 - c6 a_sdp1+ d6 a_si_o - b17 a_si_o+ c17 a_smsg - c14 a_smsg+ a15 a_sreq - c16 a_sreq+ a17 a_srst - b14 a_srst+ d13 a_ssel - b15 a_ssel+ d15 ack64/ ab1 ad0 y3 ad1 aa1 ad2 y2 ad3 y1 ad4 w3 ad5 w4 ad6 w2 ad7 w1 ad8 v4 ad9 v2 ad10 v1 ad11 u3 ad12 u2 ad13 u1 ad14 t3 ad15 t4 ad16 n3 ad17 n1 ad18 n2 ad19 m2 ad20 m3 ad21 m1 ad22 l2 ad23 l1 ad24 k2 ad25 l4 ad26 k3 ad27 j1 ad28 j2 ad29 j4 ad30 j3 ad31 h1 ad32 ac14 ad33 aa13 ad34 ac13 ad35 ab13 ad36 ab12 ad37 aa12 ad38 ac12 ad39 ab11 ad40 ac11 ad41 aa11 ad42 ac10 ad43 ab10 ad44 y11 ad45 aa10 ad46 ac9 ad47 ab9 ad48 y9 ad49 aa9 ad50 ac8 ad51 ab8 ad52 y8 ad53 aa8 ad54 ac7 ad55 ab7 ad56 aa7 ad57 ac6 ad58 ab6 ad59 y6 ad60 aa6 ad61 ac5 ad62 ab5 ad63 y5 alt_inta/ f1 alt_intb/ g3 b_diffsens y21 b_gpio0_ fetch/ aa14 b_gpio1_ master/ ac15 b_gpio2 ab15 b_gpio3 aa15 b_gpio4 ac16 b_sack - n20 b_sack+ p21 b_satn - m23 b_satn+ n22 b_sbsy - n23 b_sbsy+ n21 b_sc_d - t20 b_sc_d+ t21 b_sd0 - g21 b_sd0+ g22 b_sd1 - g23 b_sd1+ h21 b_sd2 - h20 b_sd2+ h22 b_sd3 - h23 b_sd3+ j21 b_sd4 - j20 b_sd4+ j22 b_sd5 - j23 b_sd5+ k21 b_sd6 - l20 b_sd6+ k22 b_sd7 - k23 b_sd7+ l21 b_sd8 - v21 b_sd8+ w23 b_sd9 - w22 b_sd9+ w20 b_sd10 - w21 b_sd10+ y23 b_sd11 - y22 b_sd11+ aa23 b_sd12 - d22 b_sd12+ d23 b_sd13 - e21 b_sd13+ e20 b_sd14 - e22 b_sd14+ e23 b_sd15 - f21 b_sd15+ f20 b_sdp0 - l23 b_sdp0+ l22 b_sdp1 - f22 b_sdp1+ f23 b_si_o - v22 b_si_o+ v20 b_smsg - r20 b_smsg+ r21 b_sreq - u21 b_sreq+ v23 b_srst - r23 b_srst+ r22 b_ssel - t23 b_ssel+ t22 c_be0/ v3 c_be1/ t2 c_be2/ p1 c_be3/ k1 c_be4/ ac4 c_be5/ ab4 c_be6/ ac3 c_be7/ aa4 clk h3 devsel/ r1 frame/ p2 gnt/ h4 idsel l3 int_dir g2 inta/ f4 intb/ f2 irdy/ n4 mad0 ac23 mad1 ab21 mad2 ac22 mad3 aa20 mad4 ab20 mad5 ac20 mad6 aa19 mad7 y19 mas0/ ac18 mas1/ aa17 mce/ aa18 moe/_testout y18 mwe/ ac19 nc a1 nc a13 nc a23 nc b1 nc b3 nc b13 nc b16 nc b21 nc d16 nc u22 nc u23 nc p22 nc p23 nc ab22 pa r t 1 par64 aa5 perr/ r4 rbias m21 req/ h2 req64/ aa2 reserved ab14 rst/ g1 scan_mode c22 sclk a21 serr/ r3 stop/ r2 tck d1 tdi e2 tdo e1 test_hsc c23 tms e3 trdy/ p3 test_pd a2 test_rst/ c1 v dd _io d7 v dd _io d10 v dd _io d14 v dd _io d17 v dd _io g4 v dd _io k4 v dd _io k20 v dd _io p4 v dd _io p20 v dd _io u4 v dd _io u20 v dd _io y7 v dd _io y10 v dd _io y14 v dd _io y17 v dd _a b2 v dd _a c20 v dd _bias m22 v dd _bias2 a11 v dd _core b22 v dd _core b23 v dd _core d3 v dd _core e4 v dd _core y13 v dd _core ab3 v dd _core ab18 v dd _core ab23 v dd _core ac1 v ss _io c3 v ss _io c21 v ss _io d4 v ss _io d12 v ss _io d20 v ss _io k10 v ss _io k11 v ss _io k12 v ss _io k13 v ss _io k14 v ss _io l10 v ss _io l11 v ss _io l12 v ss _io l13 v ss _io l14 v ss _io m4 v ss _io m10 v ss _io m11 v ss _io m12 v ss _io m13 v ss _io m14 v ss _io m20 v ss _io n10 v ss _io n11 v ss _io n12 v ss _io n13 v ss _io n14 v ss _io p10 v ss _io p11 v ss _io p12 v ss _io p13 v ss _io p14 v ss _io y4 v ss _io y12 v ss _io y20 v ss _io aa3 v ss _io aa21 v ss _a b20 v ss _a c2 v ss _core a22 v ss _core d2 v ss _core d21 v ss _core f3 v ss _core y15 v ss _core ab2 v ss _core aa22 v ss _core ab19 v ss _core ac2 v ss _core ac21 signal bga name pos signal bga name pos signal bga name pos signal bga name pos signal bga name pos
package drawings 6-77 table 6.52 signal names by bga position nc a1 test_pd a2 a_sd12+ a3 a_sd13+ a4 a_sd15+ a5 a_sd0+ a6 a_sd2 - a7 a_sd4 - a8 a_sd6 - a9 a_sdp0 - a10 v dd -bias2 a11 a_sbsy+ a12 nc a13 a_sack+ a14 a_smsg+ a15 a_sc_d+ a16 a_sreq+ a17 a_sd8 - a18 a_sd10 - a19 a_diffsens a20 sclk a21 v ss _core a22 nc a23 ad1 aa1 req64/ aa2 v ss_ io aa3 c_be7/ aa4 par64 aa5 ad60 aa6 ad56 aa7 ad53 aa8 ad49 aa9 ad45 aa10 aad41 aa11 ad37 aa12 ad33 aa13 b_gpio0_ fetch/ aa14 b_gpio3 aa15 a_gpio2 aa16 mas1/ aa17 mce/ aa18 mad6 aa19 mad3 aa20 v ss _io aa21 v ss _core aa22 b_sd11+ aa23 ack64/ ab1 v ss _core ab2 v dd _core ab3 c_be5/ ab4 ad62 ab5 ad58 ab6 ad55 ab7 ad51 ab8 ad47 ab9 ad43 ab10 ad39 ab11 ad36 ab12 ad35 ab13 reserved ab14 b_gpio2 ab15 a_gpio0_ fetch/ ab16 a_gpio4 ab17 v dd _core ab18 v ss _core ab19 mad4 ab20 mad1 ab21 nc ab22 v dd _core ab23 v dd _core ac1 v ss _core ac2 c_be6/ ac3 c_be4/ ac4 ad61 ac5 ad57 ac6 ad54 ac7 ad50 ac8 ad46 ac9 ad42 ac10 ad40 ac11 ad38 ac12 ad34 ac13 ad32 ac14 b_gpio1_ master/ ac15 b_gpio4 ac16 a_gpio3 ac17 mas0/ ac18 mwe/ ac19 mad5 ac20 v ss _core ac21 mad2 ac22 mad0 ac23 nc b1 v dd _a b2 nc b3 a_sd13 - b4 a_sd15 - b5 a_sd0 - b6 a_sd1+ b7 a_sd3+ b8 a_sd5+ b9 a_sd7+ b10 a_satn - b11 a_satn+ b12 nc b13 a_srst - b14 a_ssel - b15 nc b16 a_si_o - b17 a_sd8+ b18 a_sd10+ b19 v ss _a b20 nc b21 v dd _core b22 v dd _core b23 test_rst/ c1 v ss _a c2 v ss _io c3 a_sd12 - c4 a_sd14 - c5 a_sdp1 - c6 a_sd1 - c7 a_sd2+ c8 a_sd4+ c9 a_sd6+ c10 a_sdp0+ c11 a_sbsy - c12 a_sack - c13 a_smsg - c14 a_sc_d - c15 a_sreq - c16 a_si_o+ c17 a_sd9+ c18 a_sd11+ c19 v dd _a c20 v ss _io c21 scan_mode c22 test_hsc c23 tck d1 v ss _core d2 v dd _core d3 v ss _io d4 a_sd14+ d5 a_sdp1+ d6 v dd _io d7 a_sd3 - d8 a_sd5 - d9 v dd _io d10 a_sd7 - d11 v ss _io d12 a_srst+ d13 v dd _io d14 a_ssel+ d15 nc d16 v dd _io d17 a_sd9 - d18 a_sd11 - d19 v ss _io d20 v ss _core d21 b_sd12 - d22 b_sd12+ d23 tdo e1 tdi e2 tms e3 v dd _core e4 b_sd13+ e20 b_sd13 - e21 b_sd14 - e22 b_sd14+ e23 alt_inta/ f1 intb/ f2 v ss _core f3 inta/ f4 b_sd15+ f20 b_sd15 - f21 b_sdp1 - f22 b_sdp1+ f23 rst/ g1 int_dir g2 alt_intb/ g3 v dd _io g4 v dd _io g20 b_sd0 - g21 b_sd0+ g22 b_sd1 - g23 ad31 h1 req/ h2 clk h3 gnt/ h4 b_sd2 - h20 b_sd1+ h21 b_sd2+ h22 b_sd3 - h23 ad27 j1 ad28 j2 ad30 j3 ad29 j4 b_sd4 - j20 b_sd3+ j21 b_sd4+ j22 b_sd5 - j23 c_be3/ k1 ad24 k2 ad26 k3 v dd _io k4 v ss _io k10 v ss _io k11 v ss _io k12 v ss _io k13 v ss _io k14 v dd _io k20 b_sd5+ k21 b_sd6+ k22 b_sd7 - k23 ad23 l1 ad22 l2 idsel l3 ad25 l4 v ss _io l10 v ss _io l11 v ss _io l12 v ss _io l13 v ss _io l14 b_sd6 - l20 b_sd7+ l21 b_sdp0+ l22 b_sdp0 - l23 ad21 m1 ad19 m2 ad20 m3 v ss _io m4 v ss _io m10 v ss _io m11 v ss _io m12 v ss _io m13 v ss _io m14 v ss _io m20 rbias m21 v dd -bias m22 b_satn - m23 ad17 n1 ad18 n2 ad16 n3 irdy/ n4 v ss _io n10 v ss _io n11 v ss _io n12 v ss _io n13 v ss _io n14 b_sack - n20 b_sbsy+ n21 b_satn+ n22 b_sbsy - n23 c_be2/ p1 frame/ p2 trdy/ p3 v dd _io p4 v ss _io p10 v ss _io p11 v ss _io p12 v ss _io p13 v ss _io p14 v dd _io p20 b_sack+ p21 nc p22 nc p23 devsel/ r1 stop/ r2 serr/ r3 perr/ r4 b_smsg - r20 b_smsg+ r21 b_srst+ r22 b_srst - r23 pa r t 1 c_be1/ t2 ad14 t3 ad15 t4 b_sc_d - t20 b_sc_d+ t21 b_ssel+ t22 b_ssel - t23 ad13 u1 ad12 u2 ad11 u3 v dd _io u4 v dd _io u20 b_sreq - u21 nc u22 nc u23 ad10 v1 ad9 v2 c_be0/ v3 ad8 v4 b_si_o+ v20 b_sd8 - v21 b_si_o - v22 b_sreq+ v23 ad7 w1 ad6 w2 ad4 w3 ad5 w4 b_sd9+ w20 b_sd10 - w21 b_sd9 - w22 b_sd8+ w23 ad3 y1 ad2 y2 ad0 y3 v ss_ io y4 ad63 y5 ad59 y6 v dd_ io y7 ad52 y8 ad48 y9 v dd _io y10 ad44 y11 v ss _io y12 v dd _core y13 v dd _io y14 v ss _core y15 a_gpio1_ master/ y16 v dd _io y17 moe/_ testout y18 mad7 y19 v ss _io y20 b_diffsens y21 b_sd11 - y22 b_sd10+ y23 signal bga name pos signal bga name pos signal bga name pos signal bga name pos signal bga name pos
6-78 speci?cations figure 6.42 LSI53C1010-33 329 ball grid array (bottom view)
package drawings 6-79 figure 6.43 LSI53C1010-33 329 bga mechanical drawing impor tant: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code vw.
6-80 speci?cations
LSI53C1010-33 pci to dual channel ultra160 scsi multifunction controller a-1 appendix a register summary table a.1 lists the lsi53c1010 pci registers by register name. table a.1 LSI53C1010-33 pci register map register name address read/write page pci registers base address register four (bar4) (scripts ram) 0x20C0x23 read/write 4-11 base address register one (bar1) (memory) 0x14C0x17 read/write 4-10 base address register three (bar3) (scripts ram) 0x1cC0x1f read/write 4-11 base address register two (bar2) (memory) 0x18C0x1b read/write 4-10 base address register zero (bar0) (i/o) 0x10C0x13 read/write 4-9 bridge support extensions (pmcsr_bse) 0x46 read only 4-21 cache line size (cls) 0x0c read/write 4-7 capabilities pointer (cp) 0x34 read only 4-15 capability id (cid) 0x40 read only 4-18 class code (cc) 0x09C0x0b read only 4-7 command 0x04C0x05 read/write 4-3 data 0x47 read only 4-21 device id 0x02C0x03 read only 4-3 expansion rom base address (erba) 0x30C0x33 read/write 4-14 header type (ht) 0x0e read only 4-9 interrupt line (il) 0x3c read/write 4-16 interrupt pin (ip) 0x3d read only 4-16
a-2 register summary latency timer (lt) 0x0d read/write 4-8 max_lat (ml) 0x3f read only 4-17 min_gnt (mg) 0x3e read only 4-17 next item pointer (nip) 0x41 read only 4-18 power management capabilities (pmc) 0x42C0x43 read only 4-18 power management control/status (pmcsr) 0x44C0x45 read/write 4-20 reserved 0x0f C 4-9 reserved 0x24C0x27 C 4-12 reserved 0x28C0x2b C 4-12 reserved 0x35C0x37 C 4-15 reserved 0x38C0x3b C 4-15 revision id (rid) 0x08 read only 4-7 status 0x06C0x07 read/write 4-5 subsystem id (sid) 0x2eC0x2f read only 4-13 subsystem vendor id (svid) 0x2cC0x2d read only 4-12 vendor id 0x00C0x01 read only 4-3 table a.1 LSI53C1010-33 pci register map (cont.) register name address read/write page
register summary a-3 table a.2 lists the lsi53c1010 scsi registers, phase mismatch jump registers, and shadow registers by register name. table a.2 LSI53C1010-33 scsi register map register name address read/write page scsi registers adder sum output (adder) 0x3cC0x3f read only 4-71 aip control one (aipcntl1) 0xbf read/write 4-112 aip control zero (aipcntl0) 0xbe read/write 4-111 chip control one (ccntl1) 0x57 read/write 4-95 chip control three (ccntl3) 0x5b read/write 4-97 chip control zero (ccntl0) 0x56 read/write 4-93 chip test five (ctest5) 0x22 read/write 4-59 chip test four (ctest4) 0x21 read/write 4-57 chip test one (ctest1) 0x19 read only 4-53 chip test six (ctest6) 0x23 read/write 4-60 chip test three (ctest3) 0x1b read/write 4-55 chip test two (ctest2) 0x1a read only (bit 3 write) 4-54 chip test zero (ctest0) 0x18 read/write 4-53 current inbound scsi offset (cso) 0x53 read only 4-92 data structure address (dsa) 0x10C0x13 read/write 4-47 dma byte counter (dbc) 0x24C0x26 read/write 4-61 dma command (dcmd) 0x27 read/write 4-62 dma control (dcntl) 0x3b read/write 4-68 dma interrupt enable (dien) 0x39 read/write 4-67 dma mode (dmode) 0x38 read/write 4-64 dma next address (dnad) 0x28C0x2b read/write 4-62 dma next address 64 (dnad64) 0xb8C0xbb read/write 4-102
a-4 register summary dma scripts pointer (dsp) 0x2cC0x2f read/write 4-63 dma scripts pointer save (dsps) 0x30C0x33 read/write 4-63 dma status (dstat) 0x0c read only 4-40 dsa relative selector (drs) 0xacC0xaf read/write 4-101 dynamic block move selector (dbms) 0xb4C0xb7 read/write 4-102 general purpose (gpreg) 0x07 read/write 4-36 general purpose pin control (gpcntl) 0x47 read/write 4-80 interrupt status one (istat1) 0x15 read/write 4-51 interrupt status zero (istat0) 0x14 read/write 4-47 mailbox one (mbox1) 0x17 read/write 4-52 mailbox zero (mbox0) 0x16 read/write 4-52 memory move read selector (mmrs) 0xa0C0xa3 read/write 4-99 memory move write selector (mmws) 0xa4C0xa7 read/write 4-100 reserved 0x20 C 4-57 reserved 0x44 C 4-79 reserved 0x46 C 4-79 reserved 0x5a C 4-97 reserved 0xbd C 4-111 response id one (respid1) 0x4b read/write 4-84 response id zero (respid0) 0x4a read/write 4-84 scratch byte register (sbr) 0x3a read/write 4-68 scratch register a (scratcha) 0x34C0x37 read/write 4-64 scratch register b (scratchb) 0x5cC0x5f read/write 4-98 scratch registers cCr (scratchcCscratchr) 0x60C0x9f read/write 4-99 script fetch selector (sfs) 0xa8C0xab read/write 4-100 table a.2 LSI53C1010-33 scsi register map (cont.) register name address read/write page
register summary a-5 scsi bus control lines (sbcl) 0x0b read only 4-40 scsi bus data lines (sbdl) 0x58C0x59 read only 4-96 scsi chip id (scid) 0x04 read/write 4-33 scsi control four (scntl4) 0xbc read/write 4-102 scsi control one (scntl1) 0x01 read/write 4-28 scsi control three (scntl3) 0x03 read/write 4-32 scsi control two (scntl2) 0x02 read/write 4-30 scsi control zero (scntl0) 0x00 read/write 4-24 scsi destination id (sdid) 0x06 read/write 4-35 scsi first byte received (sfbr) 0x08 read/write 4-37 scsi input data latch (sidl) 0x50C0x51 read only 4-90 scsi interrupt enable one (sien1) 0x41 read/write 4-73 scsi interrupt enable zero (sien0) 0x40 read/write 4-71 scsi interrupt status one (sist1) 0x43 read only 4-78 scsi interrupt status zero (sist0) 0x42 read only 4-75 scsi output control latch (socl) 0x09 read/write 4-38 scsi output data latch (sodl) 0x54C0x55 read/write 4-92 scsi selector id (ssid) 0x0a read only 4-39 scsi status one (sstat1) 0x0e read only 4-45 scsi status two (sstat2) 0x0f read only 4-46 scsi status zero (sstat0) 0x0d read only 4-43 scsi test four (stest4) 0x52 read only 4-91 scsi test one (stest1) 0x4d read/write 4-86 scsi test three (stest3) 0x4f read/write 4-89 scsi test two (stest2) 0x4e read/write 4-88 table a.2 LSI53C1010-33 scsi register map (cont.) register name address read/write page
a-6 register summary scsi test zero (stest0) 0x4c read only 4-85 scsi timer one (stime1) 0x49 read/write 4-82 scsi timer zero (stime0) 0x48 read/write 4-81 scsi transfer (sxfer) 0x05 read/write 4-34 scsi wide residue (swide) 0x45 read/write 4-79 static block move selector (sbms) 0xb0C0xb3 read/write 4-101 temporary (temp) 0x1cC0x1f read/write 4-56 phase mismatch jump registers crc control one (crccntl1) 0xe3 read/write 4-119 crc control zero (crccntl0) 0xe2 read/write 4-118 crc data (crcd) 0xe4C0xe7 read/write 4-120 crc pad byte value (crcpad) 0xe0C0xe1 read/write 4-117 cumulative scsi byte count (csbc) 0xdcC0xdf read/write 4-117 dma fifo byte count (dfbc) 0xf0C0xf1 read only 4-122 entry storage address (esa) 0xd0C0xd3 read/write 4-115 instruction address (ia) 0xd4C0xd7 read/write 4-115 phase mismatch jump address one (pmjad1) 0xc0C0xc3 read/write 4-112 phase mismatch jump address two (pmjad2) 0xc4C0xc7 read/write 4-113 remaining byte count (rbc) 0xc8C0xcb read/write 4-113 reserved 0xdb C 4-116 reserved 0xe8C0xef C 4-121 reserved 0xf2C0xf3 C 4-122 reserved 0xf4C0xff C 4-122 scsi byte count (sbc) 0xd8C0xda read only 4-116 updated address (ua) 0xccC0xcf read/write 4-114 table a.2 LSI53C1010-33 scsi register map (cont.) register name address read/write page
register summary a-7 shadow registers shadowed memory move read selector (mmrs) 0xa0C0xa3 read/write 4-125 shadowed memory move write selector (mmws) 0xa4C0xa7 read/write 4-126 shadowed scratch register a (scratcha) 0x34C0x37 read/write 4-123 shadowed scratch register b (scratchb) 0x5cC0x5f read/write 4-125 shadowed scratch registers cCr (scratchcCscratchr) 0x60C0x9f read/write 4-125 shadowed script fetch selector (sfs) 0xa8C0xab read/write 4-126 shadowed scsi interrupt status one (sist1) 0x43 read only 4-124 shadowed scsi sge status 0 0x42 read/write 4-123 table a.2 LSI53C1010-33 scsi register map (cont.) register name address read/write page
a-8 register summary
LSI53C1010-33 pci to dual channel ultra160 scsi multifunction controller b-1 appendix b external memory interface diagram examples appendix b has example external memory interface diagrams. figure b.1 16 kbyte interface with 200 ns memory lsi53c1010 27c128 moe/ oe mce/ ce d[7:0] 8 mad[7:0] bus ck q[7:0] 8 a[7:0] qe d[5:0] ck q[5:0] qe 6 a[13:8] 6 v dd mas0/ mas1/ 8 note: mad[3:1] pulled low internally. mad bus sense logic enabled for 16 kbyte of slow memory (200 ns devices @ 33 mhz). hct374 hct374 d[7:0] mad0 4.7 k
b-2 external memory interface diagram examples figure b.2 64 kbyte interface with 150 ns memory lsi53c1010 27c512-15/ moe/ oe mce/ ce d[7:0] 8 mad[7:0] bus ck q[7:0] 8 a[7:0] qe d[7:0] ck q[7:0] qe 8 a[15:8] 8 v dd mas0/ mas1/ 8 note: mad 3, 1, 0 pulled low internally. mad bus sense logic enabled for 64 kbyte of fast memory (150 ns devices @ 33 mhz). hct374 hct374 gpio4 mwe/ vpp control +12 v vpp we optional - for flash memory only, not required for eeproms. 28f512-15/ socket d[7:0] mad2 4.7 k
external memory interface diagram examples b-3 figure b.3 128, 256, 512 kbyte or 1 mbyte interface with 150 ns memory lsi53c1010 27c020-15/ moe/ oe mce/ ce d[7:0] 8 mad[7:0] bus ck q[7:0] 8 a[7:0] qe d[7:0] ck q[7:0] qe 8 a[15:8] 8 v dd mas0/ mas1/ 8 note: mad[2:0] pulled low internally. mad bus sense logic enabled for 128, 256, 512 kbytes, or 1 mbyte of fast memory (150 ns devices @ 33 mhz). the hct374s may be replaced with hct377s. hct374 hct374 gpio4 mwe/ vpp control +12 v vpp we optional - for flash memory only, not required for eeproms. 28f020-15/ socket d[7:0] mad3 4.7 k d[3:0] ck q[3:0] qe 4 4 hct377 mad[3:0] bus e a[19:16]
b-4 external memory interface diagram examples figure b.4 512 kbyte interface with 150 ns memory lsi53c1010 moe/ d[7:0] 8 mad[7:0] bus ck q[7:0] 8 a[7:0] qe d[7:0] ck q[7:0] qe 8 a[15:8] 8 v dd mas0/ mas1/ 8 note: mad2 pulled low internally. mad bus sense logic enabled for 512 kbytes of slow memory (150 ns devices, additional time required for hct139 @ 33 mhz). the hct374s may be replaced with hct377s. hct374 hct374 gpio4 mwe/ vpp control +12 v vpp optional - for flash memory only, not required for eeproms. d[7:0] mad3 4.7 k d[2:0] ck q0 q2 3 hct377 mad[2:0] bus e mad1 4.7 k mad3 4.7 k oe we d[7:0] a0 a16 . . . oe we d[7:0] a0 a16 . . . oe we d[7:0] a0 a16 . . . oe we d[7:0] a0 a16 . . . a b gb y0 y1 y2 y3 mce/ hct139 ce ce ce ce 27c010-15/28f010-15 sockets
LSI53C1010-33 pci to dual channel ultra160 scsi multifunction controller ix-1 index symbols (64timod) 4-95 (a7) 5-24 (aap) 4-27 (abrt) 4-41 , 4-48 (ack) 4-38 , 4-40 (adb) 4-28 (adder) 4-71 (aesp) 4-29 (aip) 4-44 (arb[1:0]) 4-24 (art) 4-85 (atn) 4-38 , 4-40 (bar0[31:0]) 4-9 (bar1[31:0]) 4-10 (bar2[31:0]) 4-10 (bar3[31:0]) 4-11 (bar4[31:0]) 4-11 (bf) 4-41 , 4-67 (bl[1:0]) 4-64 (bl2) 4-59 (bof) 4-66 (bse[7:0]) 4-21 (bsy) 4-38 , 4-40 (c_d) 4-38 , 4-40 , 4-45 (cc[23:0]) 4-7 (ccntl0) 4-93 (ccntl1) 4-95 (chm) 4-31 (cid[7:0]) 4-18 (cio) 4-54 (clf) 2-53 , 4-56 (cls[7:0]) 4-7 (clse) 2-7 , 4-68 (cm) 4-54 (cmp) 4-71 , 4-75 (con) 4-29 , 4-49 (cp[7:0]) 4-15 (csbc) 4-117 (csf) 2-53 , 4-90 (cso) 4-92 (cso[5:0])) 4-92 (ctest0) 4-53 (ctest1) 4-53 (ctest2) 4-54 (ctest3) 4-55 (ctest4) 4-57 (ctest5) 4-59 (ctest6) 4-60 (d1s) 4-19 (d2s) 4-19 (data[7:0]) 4-21 (dbc) 4-61 (dbms) 4-102 (dcmd) 4-62 (dcntl) 4-68 (ddac) 4-95 (df) 4-60 (dfe) 4-41 (dhp) 4-28 (did[15:0]) 4-3 (dien) 4-67 (diom) 4-65 (dip) 4-50 (disrc) 4-94 (dmode) 4-64 (dnad) 4-62 (dnad64) 4-102 (dpe) 4-5 (dpr) 4-6 , 4-94 (drs) 4-101 (dsa) 4-47 (dscl) 4-20 (dsi) 4-19 , 4-89 (dslt) 4-20 (dsp) 4-63 (dsps) 4-63 (dstat) 4-40 (dt[1:0]) 4-6 (ebm) 4-4 (eis) 4-5 (ems) 4-4 (en64dbmv) 4-96 (en64tibmv) 4-96 (enc) 4-35 (enc[3:0]) 4-34 (enid) 4-39 (enndj) 4-93 (enpmj) 4-93 (epc) 4-26 (eper) 4-4 (erba) 4-14 (erl) 4-66 (ermp) 4-66 (esa) 4-115 (ews) 4-33 (fbl[2:0]) 4-58 (fbl3) 4-57 (fe) 4-80 (ffl) 4-53 (flf) 4-55 (flsh) 4-51
ix-2 index (fmt) 4-53 (gen) 4-74 , 4-78 (gen[3:0]) 4-83 (gensf) 4-83 (gpcntl) 4-80 (gpio) 4-36 (gpio[1:0]) 4-81 (gpio[4:2]) 4-80 (gpreg) 4-36 (ht[7:0]) 4-9 (hth) 4-74 , 4-78 (hth[3:0]) 4-81 (hthba) 4-82 (hthsf) 4-83 (i/o) 4-9 , 4-38 , 4-40 (i_o) 4-45 (ia) 4-115 (iarb) 4-29 (iid) 4-42 , 4-67 (il[7:0]) 4-16 (ilf) 4-43 (ilf1) 4-46 (intf) 4-49 (ip[7:0]) 4-16 (irm[1:0]) 4-87 (irqm) 4-69 (istat0) 4-47 (istat1) 4-51 (ldsc) 4-46 (ledc) 4-80 (loa) 4-44 (low) 4-88 (lt[7:0]) 4-8 (m/a) 4-71 , 4-75 (man) 4-66 (mbox0) 4-52 (mbox1) 4-52 (mdpe) 4-41 , 4-67 (me) 4-80 (memory) 4-10 (mg[7:0]) 4-17 (ml[7:0]) 4-17 (mmrs) 4-99 , 4-125 (mmws) 4-100 , 4-126 (mo[5:0]) 4-34 (mpee) 4-57 (msg) 4-38 , 4-40 , 4-45 (nc) 4-6 (nip[7:0]) 4-18 (olf) 4-43 (olf1) 4-46 (par) 4-73 , 4-77 (pcicie) 4-54 (pen) 4-20 (pfen) 4-68 (pff) 4-68 (pmc) 4-18 (pmcsr) 4-20 (pmcsr_bse) 4-21 (pmec) 4-19 (pmes) 4-18 (pmjad1) 4-112 (pmjad2) 4-113 (pmjctl) 4-93 (pst) 4-20 (pws[1:0]) 4-20 (qen) 4-86 (qsel) 4-87 (rbc) 4-113 (req) 4-38 , 4-40 (respid0) 4-84 (respid1) 4-84 (rid[7:0]) 4-7 (rma) 4-5 (rof) 4-88 (rre) 4-33 (rsl) 4-72 , 4-76 (rst) 4-29 , 4-44 , 4-73 , 4-77 (rta) 4-5 (sbc) 4-116 (sbcl) 4-40 (sbdl) 4-96 (sbmc) 4-74 , 4-78 (sbms) 4-101 (sbr) 4-68 (sce) 4-88 (scf[2:0]) 4-32 (scid) 4-33 (scntl0) 4-24 (scntl1) 4-28 (scntl2) 4-30 (scntl3) 4-32 (scratcha) 4-64 , 4-123 (scratchb) 4-98 , 4-125 (scratchcCscratchr) 4-99 , 4-125 (scripts ram) 4-11 (sdid) 4-35 (sdp0) 4-44 (sdp0l) 4-45 (sdp1) 4-47 (sdu) 4-30 (se) 4-4 (sel) 4-38 , 4-40 , 4-72 , 4-76 (sem) 4-49 (sfbr) 4-37 (sfs) 4-100 , 4-126 (sge) 4-72 , 4-76 (si) 4-51 (sid[15:0]) 4-13 (sien0) 4-71 (sien1) 4-73 (sigp) 4-48 , 4-54 (sip) 4-50 (sir) 4-41 , 4-67 (sist0) 4-75 (sist1) 4-78 , 4-124 (slt) 4-85 (smode[1:0]) 4-91 (socl) 4-38 (sodl) 4-92 (som) 4-86 (soz) 4-85 (spl1) 4-46 (sre) 4-33 (srst) 4-48 (srtm) 4-57 (srun) 4-51 (ssaid[3:0]) 4-85 (sse) 4-5 (ssi) 4-41 , 4-67 (ssid) 4-39 (ssm) 4-69
index ix-3 (sstat0) 4-43 (sstat1) 4-45 (sstat2) 4-46 (start) 4-25 (std) 4-69 (stest0) 4-85 (stest1) 4-86 (stest2) 4-88 (stest3) 4-89 (stest4) 4-91 (stime0) 4-81 (stime1) 4-82 (sto) 4-74 , 4-78 (swide) 4-79 (sxfer) 4-34 (szm) 4-88 (te) 4-89 (temp) 4-56 (trg) 4-27 (ttm) 4-90 (ua) 4-114 (udc) 4-73 , 4-77 (val) 4-39 (ver[2:0]) 4-19 (vue0) 4-31 (vue1) 4-31 (watn) 4-26 (wie) 4-4 (woa) 4-44 (wrie) 4-56 (wsr) 4-32 (wss) 4-31 numerics 32/64 bit jump 5-31 32-bit addressing 5-7 3-state 3-2 64 kbytes rom read cycle 6-60 , 6-61 64-bit addressing 5-8 addressing in scripts 2-21 table indirect indexing mode (64timod) 4-95 a a and b diffsens scsi signals 6-4 a[6:0] 5-24 a_diffsens 3-14 a_gpio0_ fetch/ 3-11 a_gpio1_ master/ 3-11 a_gpio2 3-11 a_gpio3 3-11 a_gpio4 3-11 a_sack+- 3-15 a_satn+- 3-15 a_sbsy+- 3-15 a_sc_d+- 3-15 a_sdp[1:0]+- 3-14 a_si_o+- 3-15 a_smsg+- 3-15 a_sreq+- 3-15 a_srst+- 3-15 a_ssel+- 3-15 abort operation (abrt) 4-48 aborted (abrt) 4-41 , 4-67 absolute maximum stress ratings 6-2 ac characteristics 6-10 ack64/ 3-7 acknowledge 64 3-7 active termination 2-41 ad[63:0] 3-6 adder sum output (adder) 4-71 address and data signals 3-6 address/data bus 2-3 alt interrupt a 3-10 b 3-10 arbitration in progress (aip) 4-44 mode bits 1 and 0 (arb[1:0]) 4-24 priority encoder test (art) 4-85 signals 3-8 assert even scsi parity (force bad parity) (aesp) 4-29 satn/ on parity/crc error (aap) 4-27 scsi ack/ signal (ack) 4-38 , 4-40 atn/ signal (atn) 4-38 , 4-40 bsy/ signal (bsy) 4-38 , 4-40 c_d/ signal (c_d) 4-38 , 4-40 data bus (adb) 4-28 i_o/ signal (i/o) 4-38 , 4-40 msg/ signal (msg) 4-38 , 4-40 req/ signal (req) 4-38 , 4-40 rst/ signal (rst) 4-29 sel/ signal (sel) 4-38 , 4-40 asynchronous scsi receive 2-40 send 2-39 b b_diffsens 3-17 b_gpio0_fetch/ 3-12 b_gpio1_master/ 3-12 b_gpio2 3-12 b_gpio3 3-12 b_gpio4 3-12 b_sack+- 3-18 b_satn+- 3-18 b_sbsy+- 3-18 b_sc_d+- 3-18 b_sd[15:0]+- 3-16 b_sdp[1:0]+- 3-16 b_si_o+- 3-18 b_smsg+- 3-18 b_sreq+- 3-18 b_srst+- 3-18 b_ssel+- 3-18 back-to-back read 32-bits address and data 6-28 back-to-back write 32-bit address and data 6-30 base address register four (bar4[31:0]) 4-11 one 2-4 one (bar1[31:0]) 4-10 three (bar3[31:0]) 4-11 two (bar2[31:0]) 4-10 zero 2-4 zero - i/o (bar0[31:0]) 4-9
ix-4 index bidirectional 3-2 signals 6-5 , 6-6 bios 2-3 bits used for parity control and generation 2-36 block move 2-10 instructions 5-5 bridge support extensions (bse[7:0]) 4-21 burst length (bl[1:0]) 4-64 length bit 2 (bl2) 4-59 opcode fetch 32-bit address and data 6-26 opcode fetch enable (bof) 4-66 size selection 2-7 burst read 32-bit address and data 6-32 64-bit address and data 6-34 burst write 32-bit address and data 6-36 64-bit address and data 6-38 bus command and byte enables 3-6 fault (bf) 4-41 , 4-67 byte count 5-39 empty in dma fifo (fmt) 4-53 full in dma fifo (ffl) 4-53 c c_be[3:0]/ 2-3 c_be[7:0]/ 3-6 cache line size (cls) 2-8 (cls[7:0]) 4-7 enable (clse) 2-8 , 4-68 register 2-7 , 2-11 cache mode, see pci cache mode 2-11 call instruction 5-28 cap_id (cid[7:0]) 4-18 capabilities pointer (cp[7:0]) 4-15 capability id register 4-18 carry test 5-31 chained block moves 2-57 chained mode (chm) 4-31 change bus phases 2-19 chip control one (ccntl1) 4-95 control zero (ccntl0) 4-93 test five (ctest5) 2-8 , 4-59 test four (ctest4) 2-36 , 4-57 test one (ctest1) 4-53 test six (ctest6) 4-60 test three (ctest3) 2-9 , 2-12 , 4-55 test two (ctest2) 4-54 test zero (ctest0) 4-53 class code register 4-7 clear dma fifo (clf) 2-53 , 4-56 clear instruction 5-17 , 5-19 clear scsi fifo (csf) 2-53 , 4-90 clk 3-5 clock 3-5 quadrupler 2-31 command register 2-12 compare data 5-32 phase 5-32 configuration read command 2-6 space 2-3 write command 2-7 configured as i/o (cio) 4-54 as memory (cm) 4-54 connected (con) 4-29 , 4-49 cumulative scsi byte count (csbc) 4-117 current function of input voltage 6-9 function of output voltage 6-10 cycle frame 3-7 d d1_support (d1s) 4-19 d2_support (d2s) 4-19 dacs 2-22 data (data[7:0]) 4-21 compare mask 5-32 compare value 5-33 parity error reported (dpr) 4-6 paths 2-38 structure address (dsa) 4-47 data_scale 4-20 data_select (dslt) 4-20 dc characteristics 6-1 default download mode 2-62 destination address 5-24 i/o-memory enable (diom) 4-65 detected parity error (from slave) (dpe) 4-5 device id (did[15:0]) 4-3 select 3-8 specific initialization (dsi) 4-19 devsel/ 3-8 timing (dt[1:0]) 4-6 dip 2-53 , 2-54 direct 5-20 disable auto fifo clear (disfc) 4-94 dual address cycle (ddac) 4-95 halt on parity/crc error or atn (target only) (dhp) 4-28 pipe req (dpr) 4-94 single initiator response (dsi) 4-89 disable internal scripts ram cycles 4-94 disconnect 2-19 disconnect instruction 5-16 dma byte counter (dbc) 4-61 command (dcmd) 4-62 control (dcntl) 2-7 , 2-8 , 2-9 , 4-68 fifo 2-9 , 2-38 , 2-49 (df) 4-60 empty (dfe) 4-41 sections 2-38 interrupt 2-53 enable (dien) 2-36 , 2-50 , 4-67 interrupt pending (dip) 4-50 interrupts 2-53 mode (dmode) 2-7 , 2-8 , 2-9 , 2-12 , 2-33 , 4-64 next address (dnad) 4-62
index ix-5 dma (cont.) next address 64 (dnad64) 4-102 scripts pointer (dsp) 4-63 pointer save (dsps) 4-63 status (dstat) 2-36 , 2-50 , 2-52 , 2-53 , 2-54 , 4-40 dsa relative 5-38 relative selector (drs) 4-101 dsps register 5-36 dual address cycles 2-22 dynamic block move selector (dbms) 4-102 e enable 64-bit direct bmov (en64dbmv) 4-96 table indirect bmov (en64tibmv) 4-96 bus mastering (ebm) 4-4 i/o space (eis) 4-5 jump on nondata phase mismatches (enndj) 4-93 memory space (ems) 4-4 parity checking 2-34 checking (epc) 4-26 error response (eper) 4-4 phase mismatch jump (enpmj) 4-93 read line (erl) 4-66 multiple (ermp) 4-66 response to reselection (rre) 4-33 selection (sre) 4-33 wide scsi (ews) 4-33 enabling cache mode 2-11 encoded chip scsi id (enc[3:0]) 4-34 destination scsi id (enc[3:0]) 4-35 (enid) 4-39 scsi destination id 5-21 entry storage address (esa) 4-115 error reporting signals 3-9 even parity 2-34 expansion rom base address 4-14 external clock 6-11 memory interface configuration 2-61 diagram examples b-1 multiple byte accesses 6-14 memory read 6-41 memory timing 6-41 memory write 6-45 f fast back to back capable 4-6 fetch enable (fe) 4-80 fifo byte control (fbl[2:0]) 4-58 byte control (fbl3) 4-57 first dword 5-5 , 5-15 , 5-23 , 5-27 , 5-38 flush dma fifo (flf) 4-55 flushing (flsh) 4-51 frame/ 3-7 full arbitration, selection/reselection 4-25 function complete (cmp) 4-71 , 4-75 g general description 1-1 general purpose (gpreg) 4-36 i/o (gpio) 4-36 i/o pin 0 3-11 , 3-12 i/o pin 1 3-11 , 3-12 i/o pin 2 3-11 , 3-12 i/o pin 3 3-11 , 3-12 i/o pin 4 3-11 , 3-12 pin control (gpcntl) 4-80 timer expired (gen) 4-74 , 4-78 timer period (gen[3:0]) 4-83 timer scale factor (gensf) 4-83 gnt/ 2-11 , 3-8 gpio enable (gpio[1:0]) 4-81 gpio enable (gpio[4:2]) 4-80 grant 3-8 h halting 2-53 handshake-to-handshake timer bus activity enable (hthba) 4-82 timer expired (hth) 4-74 , 4-78 timer period (hth[3:0]) 4-81 timer scale factor (hthsf) 4-83 hardware control of scsi activity led 2-22 hardware interrupts 2-47 header type (ht[7:0]) 4-9 high impedance mode (szm) 4-88 i i/o 3-2 read command 2-6 space 2-3 , 2-4 write command 2-6 idsel 2-3 , 3-8 illegal instruction detected (iid) 4-42 , 4-67 immediate arbitration (iarb) 4-29 data 5-24 indirect addressing 5-5 initialization device select 3-8 initiator asynchronous receive 6-63 asynchronous send 6-62 mode 5-12 , 5-17 phase mismatch 4-75 ready 3-7 synchronous transfer 6-67 , 6-71 timing 6-24 input 3-2 capacitance 6-4 current as a function of input voltage 6-9 signals 6-6 instruction address (ia) 4-115
ix-6 index instruction (cont.) type 5-38 block move 5-5 i/o instruction 5-15 memory move 5-35 read/write instruction 5-23 transfer control instruction 5-27 inta routing enable 3-22 inta/ 2-48 , 2-55 , 3-22 intb/ 2-48 , 2-55 , 3-22 interface 128, 256, 512 kbyte or 1 mbyte 150 ns memory b-3 16 kbyte 200 ns memory b-1 512 kbyte 150 ns memory b-4 64 kbyte 150 ns memory b-2 control signals 3-7 internal arbiter 2-11 scripts ram 2-20 internal ram see also scripts ram 2-20 interrupt a 3-9 acknowledge command 2-5 b 3-10 direction 3-11 handling 2-47 instruction 5-29 line 4-16 on the fly 5-31 on the fly (intf) 4-49 output 6-13 pin (ip[7:0]) 4-16 request 2-48 routing mode (irm[1:0]) 4-87 status one (istat1) 2-48 , 4-51 status zero (istat0) 2-48 , 4-47 interrupt-on-the-fly instruction 5-29 interrupts 2-50 fatal vs. nonfatal interrupts 2-50 halting 2-53 masking 2-51 sample interrupt service routine 2-54 stacked interrupts 2-52 irdy/ 3-7 irq mode (irqm) 4-69 issuing cache commands 2-12 j jtag boundary scan testing 2-34 jump address 5-33 call a relative address 5-30 call an absolute address 5-30 control (pmjctl) 4-93 if true/false 5-31 instruction 5-27 jump64 address 5-33 l last disconnect (ldsc) 4-46 latched scsi parity (sdp0l) 4-45 for sd[15:8] (spl1) 4-46 latency 2-10 timer (lt[7:0]) 4-8 led_cntl (ledc) 4-80 load and store instructions 2-33 , 5-37 prefetch unit and store instructions 2-33 load/store 5-39 lost arbitration (loa) 4-44 low voltage differential see lvdlink 2-41 lsi53c1010 329 ball grid array 6-78 329 bga mechanical drawing 6-79 new features 1-4 LSI53C1010-33 register map a-1 , a-3 lvd driver scsi signals 6-3 receiver scsi signals 6-3 lvdlink 1-2 , 1-6 benefits 1-6 operation 2-41 m mad bus programming 3-22 mad[0] 3-23 mad[3:1] 3-23 mad[3:1] pin decoding 3-23 mad[4] 3-22 mad[5] 3-22 mad[6] 3-22 mad[7:0] 3-19 , 3-22 mad[7] 3-22 mailbox one (mbox1) 2-48 , 4-52 mailbox zero (mbox0) 2-48 , 4-52 manual start mode (man) 4-66 mas0/ 3-19 mas1/ 3-19 masking 2-51 master data parity error (mdpe) 4-41 , 4-67 enable (me) 4-80 parity error enable (mpee) 4-57 max scsi synchronous offset (mo[5:0]) 4-34 max_lat (ml[7:0]) 4-17 maximum stress ratings 6-2 mce/ 3-19 memory address strobe 0 3-19 address strobe 1 3-19 address/data bus 3-19 chip enable 3-19 i/o address/dsa offset 5-39 move 2-10 move instructions 2-32 , 5-34 no flush option 2-32 move read selector (mmrs) 4-99 , 4-125 move write selector (mmws) 4-100 , 4-126 output enable 3-19 , 3-20 read 2-12
index ix-7 memory (cont.) read caching 2-12 read command 2-6 read line 2-11 , 2-13 read line command 2-8 read multiple 2-11 , 2-13 read multiple command 2-7 space 2-3 , 2-4 to memory 2-19 to memory moves 2-19 write 2-12 , 2-13 write and invalidate 2-11 write and invalidate command 2-9 write caching 2-13 write command 2-6 write enable 3-19 min_gnt (mg[7:0]) 4-17 moe/_testout 3-19 , 3-20 move to/from sfbr cycles 5-25 multiple cache line transfers 2-10 mwe/ 3-19 n new capabilities (nc) 4-6 new features in the lsi53c1010 1-4 next item pointer register 4-18 next_item_ptr (nip[7:0]) 4-18 no download mode 2-63 no flush 5-35 store instruction only 5-39 nonburst opcode fetch 32-bit address and data 6-24 normal/fast memory ( 128 kbytes) multiple byte access read cycle 6-52 multiple byte access write cycle 6-54 single byte access read cycle 6-48 single byte access write cycle 6-50 o opcode 5-10 , 5-15 , 5-23 , 5-27 fetch burst capability 2-33 operating conditions 6-2 operating register/scripts ram read 32-bit 6-18 64-bit 6-19 operating register/scripts ram write 32-bit 6-21 64-bit 6-22 operator 5-23 output current as a function of output voltage 6-10 output signals 6-5 p par 3-6 par64 3-7 parallel rom interface 2-60 parallel rom support 2-61 parity 3-6 error 3-9 (par) 4-77 options 2-34 parity64 3-7 pci addressing 2-3 bus commands and encoding types 2-5 bus commands and functions supported 2-4 cache line size register 2-9 cache mode 2-11 command register 2-9 commands 2-4 configuration info enable (pcicie) 4-54 configuration register read 6-16 configuration register write 6-17 configuration registers 4-1 configuration space 2-3 external memory interface timing diagrams 6-14 functional description 2-2 i/o space 2-4 interface signals 3-5 master transaction 2-12 master transfer 2-12 memory space 2-4 performance 1-9 target disconnect 2-10 target retry 2-10 perr/ 3-9 phase mismatch handling in scripts 2-20 jump address one (pmjad1) 4-112 jump address two (pmjad2) 4-113 physical longword address and data 3-6 pme clock (pmec) 4-19 enable (pen) 4-20 status (pst) 4-20 support (pmes) 4-18 polling 2-47 power and ground signals 3-21 management 2-63 capabilities 4-18 control/status 4-20 state (pws[1:0]) 4-20 state d0 2-64 state d1 2-65 state d2 2-65 state d3 2-65 prefetch enable (pfen) 4-68 flush 2-33 flush (pff) 4-68 scripts instructions 2-32 pull-ups, internal, conditions 3-4 r ram, see also scripts ram 2-20 rbias 3-21 read line 2-11 , 2-12 line function 2-8 modify-write cycles 5-24 multiple 2-9 , 2-11 , 2-12 multiple with read line enabled 2-9 write instructions 5-23 write system memory from a script 5-35 read/write instructions 5-23 , 5-25
ix-8 index read/write (cont.) system memory from a script 5-35 received master abort (from master) (rma) 4-5 target abort (from master) (rta) 4-5 register address 5-39 address - a[6:0] 5-24 register map a-1 , a-3 registers 2-48 relative 5-20 relative addressing mode 5-19 , 5-30 remaining byte count (rbc) 4-113 req/ 2-11 , 3-8 req/ - gnt/ 2-2 req64/ 3-7 request 3-8 request 64 3-7 reselect 2-19 during reselection 2-42 instruction 5-15 reselected (rsl) 4-72 , 4-76 reserved command 2-6 reset 3-5 input 6-12 scsi offset (rof) 4-88 response id one (respid1) 4-84 response id zero (respid0) 4-84 return instruction 5-28 revision id register (rid[7:0]) 4-7 rise and fall time test condition 6-8 rom flash and memory interface signals 3-19 rst/ 3-5 s sack 2-53 sacs 2-22 scan mode 3-20 scan_mode 3-20 sclk 3-13 quadrupler enable (qen) 4-86 quadrupler select (qsel) 4-87 scratch byte register (sbr) 4-68 register a (scratcha) 4-64 , 4-123 register b (scratchb) 4-98 , 4-125 registers cCr (scratchcCscratchr) 4-99 , 4-125 script fetch selector (sfs) 4-100 , 4-126 scripts interrupt instruction received (sir) 4-41 , 4-67 processor 2-20 internal ram for instruction storage 2-20 performance 2-20 ram 2-4 , 2-20 running (srun) 4-51 scsi atn condition - target mode (m/a) 4-71 bus control lines (sbcl) 4-40 bus data lines (sbdl) 4-96 bus interface 2-40 bus mode change (sbmc) 4-74 , 4-78 bus modes 2-41 byte count (sbc) 4-116 c_d/ signal (c_d) 4-45 chip id (scid) 4-33 clock 3-13 control enable (sce) 4-88 control four (scntl4) 2-44 control one (scntl1) 2-36 , 4-28 control three (scntl3) 2-43 , 4-32 control two (scntl2) 4-30 control zero (scntl0) 2-36 , 4-24 cumulative byte count 4-117 destination id (sdid) 4-35 disconnect unexpected (sdu) 4-30 encoded destination id 5-21 first byte received (sfbr) 4-37 function a control 3-15 function a gpio signals 3-11 function a signals 3-13 function b control 3-18 function b gpio signals 3-12 function b signals 3-16 functional description 2-19 gross error (sge) 4-72 , 4-76 hysteresis of receivers 6-9 i_o/ signal (i_o) 4-45 input data latch (sidl) 4-90 input filtering 6-8 instructions block move 5-5 i/o 5-15 read/write 5-23 interface signals 3-13 interrupt enable one (sien1) 2-50 , 4-73 interrupt enable zero (sien0) 2-36 , 2-50 , 4-71 interrupt pending (sip) 4-50 interrupt status one (sist1) 2-49 , 2-50 , 2-52 , 2-54 , 4-78 , 4-124 interrupt status zero (sist0) 2-36 , 2-49 , 2-50 , 2-52 , 2-54 , 4-75 interrupts 2-53 low level mode (low) 4-88 lvdlink 2-41 mode (smode[1:0]) 4-91 msg/ signal (msg) 4-45 output control latch (socl) 4-38 output data latch (sodl) 4-92 parity/crc error (par) 4-73 performance 1-7 phase 5-13 , 5-29 phase mismatch - initiator mode 4-71 registers 4-22 reset condition (rst) 4-73 rst/ received (rst) 4-77 rst/ signal (rst) 4-44 scripts operation 5-1 sample instruction 5-3 sdp0/ parity signal (sdp0) 4-44 sdp1/ parity signal (sdp1) 4-47 selected as id (ssaid[3:0]) 4-85 selector id (ssid) 4-39 status one (sstat1) 2-36 , 4-45 status two (sstat2) 2-36 , 4-46 status zero (sstat0) 2-36 , 4-43 synchronous offset maximum (som) 4-86 synchronous offset zero (soz) 4-85 termination 2-41 test four (stest4) 4-91
index ix-9 scsi (cont.) test one (stest1) 4-86 test three (stest3) 4-89 test two (stest2) 4-88 test zero (stest0) 4-85 timer one (stime1) 4-82 timer zero (stime0) 4-81 timing diagrams 6-62 tolerant technology 1-6 transfer (sxfer) 4-34 ultra160 scsi 2-23 valid (val) 4-39 wide residue (swide) 4-79 scsi-1 transfers (single-ended 5.0 mbytes) 6-65 scsi-2 fast transfers 10.0 mbytes (8-bit transfers) 40 mhz clock 6-68 40 mhz clock 6-65 20.0 mbytes (16-bit transfers) 40 mhz clock 6-65 , 6-68 second dword 5-14 , 5-22 , 5-24 , 5-33 , 5-36 , 5-39 select 2-19 during selection 2-42 instruction 5-17 with atn/ 5-21 with satn/ on a start sequence (watn) 4-26 selected (sel) 4-72 , 4-76 selection or reselection time-out (sto) 4-74 , 4-78 selection response logic test (slt) 4-85 semaphore (sem) 4-49 serial eeprom data format 2-63 interface 2-62 serr/ 3-9 serr/ enable (se) 4-4 set instruction 5-16 , 5-18 set/clear carry 5-21 sack/ 5-22 satn/ 5-22 target mode 5-21 shadow register test mode (srtm) 4-57 sidl least significant byte full (ilf) 4-43 most significant byte full (ilf1) 4-46 signal process (sigp) 4-48 , 4-54 signaled system error (sse) 4-5 simple arbitration 4-24 single address cycles 2-22 ended scsi signals 6-7 step interrupt (ssi) 4-41 , 4-67 step mode (ssm) 4-69 sip 2-53 slow memory ( 128 kbytes) read cycle 6-56 write cycle 6-58 slow rom pin 3-23 sodl least significant byte full (olf) 4-43 most significant byte full (olf1) 4-46 software reset (srst) 4-48 source i/o-memory enable (siom) 4-65 special cycle command 2-5 sreq 2-53 stacked interrupts 2-52 start address 5-14 , 5-22 dma operation (std) 4-69 sequence (start) 4-25 static block move selector (sbms) 4-101 stop command 2-10 stop signal 3-8 stop/ 3-8 store instruction 2-33 stress ratings 6-2 subsystem id 2-63 (sid[15:0]) 4-13 subsystem vendor id 2-63 (svid[15:0]) 4-12 sync_irqd (si) 4-51 synchronous clock conversion factor (scf[2:0]) 4-32 data transfer rates 2-43 operation 2-43 scsi receive 2-40 scsi send 2-40 system error 3-9 system signals 3-5 t table indirect 5-7 , 5-20 mode 5-19 table relative 5-21 target asynchronous receive 6-64 asynchronous send 6-63 mode 5-10 , 5-15 satn/ active (m/a) 4-75 mode (trg) 4-27 ready 3-7 synchronous transfer 6-67 , 6-71 timing 6-15 tck 3-20 tdi 3-20 tdo 3-20 temp register 5-37 temporary (temp) 4-56 termination 2-41 test clock 3-20 test data in 3-20 test data out 3-20 test halt scsi clock 3-20 test interface signals 3-20 test mode select 3-20 test power down 3-20 test reset 3-20 test_hsc 3-20 test_pd 3-20 test_rstn 3-20 third dword 5-14 , 5-33 , 5-36 timer test mode (ttm) 4-90 tms 3-20 tolerant 1-6 enable (te) 4-89 technology 1-6 benefits 1-7 electrical characteristics 6-7
ix-10 index totem pole output 3-2 transfer control 2-33 control instructions 5-27 and scripts instruction prefetching 2-33 count 5-35 counter 5-13 information 2-19 rate synchronous 2-43 trdy/ 2-10 , 3-7 u ultra scsi single-ended transfers 20.0 mbytes (8-bit transfers) quadrupled 40 mhz clock 6-66 , 6-69 40.0 mbytes (16-bit transfers) quadrupled 40 mhz clock 6-66 , 6-69 ultra160 scsi 1-4 benefits 1-4 designing an ultra160 scsi system 2-23 lvdlink 2-41 ultra2 scsi transfers 40.0 mbytes (8-bit transfers) quadrupled 40 mhz clock 6-67 , 6-70 , 6-71 80.0 mbytes (16-bit transfers) quadrupled 40 mhz clock 6-67 , 6-70 , 6-71 unexpected disconnect (udc) 4-73 , 4-77 updated address (ua) 4-114 upper register address line (a7) 5-24 use data8/sfbr 5-23 v vdd 3-21 -a 3-21 -bias 3-21 -bias2 3-21 -core 3-21 vendor id (vid[15:0]) 4-3 unique enhancement, bit 1 (vue1) 4-31 unique enhancements, bit 0 (vue0) 4-31 version (ver[2:0]) 4-19 vss 3-21 -a 3-21 -core 3-21 w wait disconnect instruction 5-18 for disconnect 2-19 for valid phase 5-32 reselect instruction 5-18 select instruction 5-16 wide scsi chained block moves 2-57 receive (wsr) 4-32 send (wss) 4-31 won arbitration (woa) 4-44 write read instructions 5-23 read system memory from a script 5-35 write and invalidate 2-10 , 2-11 , 2-12 enable (wie) 4-4 enable (wrie) 4-56
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u.s. distributors by state a. e. avnet electronics http://www.hh.avnet.com b. m. bell microproducts, inc. (for habs) http://www.bellmicro.com i. e. insight electronics http://www.insight-electronics.com w. e. wyle electronics http://www.wyle.com alabama daphne i. e. tel: 334.626.6190 huntsville a. e. tel: 256.837.8700 b. m. tel: 256.705.3559 i. e. tel: 256.830.1222 w. e. tel: 800.964.9953 alaska a. e. tel: 800.332.8638 arizona phoenix a. e. tel: 480.736.7000 b. m. tel: 602.267.9551 w. e. tel: 800.528.4040 tempe i. e. tel: 480.829.1800 tucson a. e. tel: 520.742.0515 arkansas w. e. tel: 972.235.9953 california agoura hills b. m. tel: 818.865.0266 granite bay b. m. tel: 916.523.7047 irvine a. e. tel: 949.789.4100 b. m. tel: 949.470.2900 i. e. tel: 949.727.3291 w. e. tel: 800.626.9953 los angeles a. e. tel: 818.594.0404 w. e. tel: 800.288.9953 sacramento a. e. tel: 916.632.4500 w. e. tel: 800.627.9953 san diego a. e. tel: 858.385.7500 b. m. tel: 858.597.3010 i. e. tel: 800.677.6011 w. e. tel: 800.829.9953 san jose a. e. tel: 408.435.3500 b. m. tel: 408.436.0881 i. e. tel: 408.952.7000 santa clara w. e. tel: 800.866.9953 woodland hills a. e. tel: 818.594.0404 westlake village i. e. tel: 818.707.2101 colorado denver a. e. tel: 303.790.1662 b. m. tel: 303.846.3065 w. e. tel: 800.933.9953 englewood i. e. tel: 303.649.1800 idaho springs b. m. tel: 303.567.0703 connecticut cheshire a. e. tel: 203.271.5700 i. e. tel: 203.272.5843 wallingford w. e. tel: 800.605.9953 delaware north/south a. e. tel: 800.526.4812 tel: 800.638.5988 b. m. tel: 302.328.8968 w. e. tel: 856.439.9110 florida altamonte springs b. m. tel: 407.682.1199 i. e. tel: 407.834.6310 boca raton i. e. tel: 561.997.2540 bonita springs b. m. tel: 941.498.6011 clearwater i. e. tel: 727.524.8850 fort lauderdale a. e. tel: 954.484.5482 w. e. tel: 800.568.9953 miami b. m. tel: 305.477.6406 orlando a. e. tel: 407.657.3300 w. e. tel: 407.740.7450 tampa w. e. tel: 800.395.9953 st. petersburg a. e. tel: 727.507.5000 georgia atlanta a. e. tel: 770.623.4400 b. m. tel: 770.980.4922 w. e. tel: 800.876.9953 duluth i. e. tel: 678.584.0812 hawaii a. e. tel: 800.851.2282 idaho a. e. tel: 801.365.3800 w. e. tel: 801.974.9953 illinois north/south a. e. tel: 847.797.7300 tel: 314.291.5350 chicago b. m. tel: 847.413.8530 w. e. tel: 800.853.9953 schaumburg i. e. tel: 847.885.9700 indiana fort wayne i. e. tel: 219.436.4250 w. e. tel: 888.358.9953 indianapolis a. e. tel: 317.575.3500 iowa w. e. tel: 612.853.2280 cedar rapids a. e. tel: 319.393.0033 kansas w. e. tel: 303.457.9953 kansas city a. e. tel: 913.663.7900 lenexa i. e. tel: 913.492.0408 kentucky w. e. tel: 937.436.9953 central/northern/ western a. e. tel: 800.984.9503 tel: 800.767.0329 tel: 800.829.0146 louisiana w. e. tel: 713.854.9953 north/south a. e. tel: 800.231.0253 tel: 800.231.5775 maine a. e. tel: 800.272.9255 w. e. tel: 781.271.9953 maryland baltimore a. e. tel: 410.720.3400 w. e. tel: 800.863.9953 columbia b. m. tel: 800.673.7461 i. e. tel: 410.381.3131 massachusetts boston a. e. tel: 978.532.9808 w. e. tel: 800.444.9953 burlington i. e. tel: 781.270.9400 marlborough b. m. tel: 800.673.7459 woburn b. m. tel: 800.552.4305 michigan brighton i. e. tel: 810.229.7710 detroit a. e. tel: 734.416.5800 w. e. tel: 888.318.9953 clarkston b. m. tel: 877.922.9363 minnesota champlin b. m. tel: 800.557.2566 eden prairie b. m. tel: 800.255.1469 minneapolis a. e. tel: 612.346.3000 w. e. tel: 800.860.9953 st. louis park i. e. tel: 612.525.9999 mississippi a. e. tel: 800.633.2918 w. e. tel: 256.830.1119 missouri w. e. tel: 630.620.0969 st. louis a. e. tel: 314.291.5350 i. e. tel: 314.872.2182 montana a. e. tel: 800.526.1741 w. e. tel: 801.974.9953 nebraska a. e. tel: 800.332.4375 w. e. tel: 303.457.9953 nevada las vegas a. e. tel: 800.528.8471 w. e. tel: 702.765.7117 new hampshire a. e. tel: 800.272.9255 w. e. tel: 781.271.9953 new jersey north/south a. e. tel: 201.515.1641 tel: 609.222.6400 mt. laurel i. e. tel: 856.222.9566 pine brook b. m. tel: 973.244.9668 w. e. tel: 800.862.9953 parsippany i. e. tel: 973.299.4425 wayne w. e. tel: 973.237.9010 new mexico w. e. tel: 480.804.7000 albuquerque a. e. tel: 505.293.5119
u.s. distributors by state (continued) new york hauppauge i. e. tel: 516.761.0960 long island a. e. tel: 516.434.7400 w. e. tel: 800.861.9953 rochester a. e. tel: 716.475.9130 i. e. tel: 716.242.7790 w. e. tel: 800.319.9953 smithtown b. m. tel: 800.543.2008 syracuse a. e. tel: 315.449.4927 north carolina raleigh a. e. tel: 919.859.9159 i. e. tel: 919.873.9922 w. e. tel: 800.560.9953 north dakota a. e. tel: 800.829.0116 w. e. tel: 612.853.2280 ohio cleveland a. e. tel: 216.498.1100 w. e. tel: 800.763.9953 dayton a. e. tel: 614.888.3313 i. e. tel: 937.253.7501 w. e. tel: 800.575.9953 strongsville b. m. tel: 440.238.0404 valley view i. e. tel: 216.520.4333 oklahoma w. e. tel: 972.235.9953 tulsa a. e. tel: 918.459.6000 i. e. tel: 918.665.4664 oregon beaverton b. m. tel: 503.524.1075 i. e. tel: 503.644.3300 portland a. e. tel: 503.526.6200 w. e. tel: 800.879.9953 pennsylvania mercer i. e. tel: 412.662.2707 philadelphia a. e. tel: 800.526.4812 b. m. tel: 877.351.2355 w. e. tel: 800.871.9953 pittsburgh a. e. tel: 412.281.4150 w. e. tel: 440.248.9996 rhode island a. e. 800.272.9255 w. e. tel: 781.271.9953 south carolina a. e. tel: 919.872.0712 w. e. tel: 919.469.1502 south dakota a. e. tel: 800.829.0116 w. e. tel: 612.853.2280 tennessee w. e. tel: 256.830.1119 east/west a. e. tel: 800.241.8182 tel: 800.633.2918 texas arlington b. m. tel: 817.417.5993 austin a. e. tel: 512.219.3700 b. m. tel: 512.258.0725 i. e. tel: 512.719.3090 w. e. tel: 800.365.9953 dallas a. e. tel: 214.553.4300 b. m. tel: 972.783.4191 w. e. tel: 800.955.9953 el paso a. e. tel: 800.526.9238 houston a. e. tel: 713.781.6100 b. m. tel: 713.917.0663 w. e. tel: 800.888.9953 richardson i. e. tel: 972.783.0800 rio grande valley a. e. tel: 210.412.2047 stafford i. e. tel: 281.277.8200 utah centerville b. m. tel: 801.295.3900 murray i. e. tel: 801.288.9001 salt lake city a. e. tel: 801.365.3800 w. e. tel: 800.477.9953 vermont a. e. tel: 800.272.9255 w. e. tel: 716.334.5970 virginia a. e. tel: 800.638.5988 w. e. tel: 301.604.8488 haymarket b. m. tel: 703.754.3399 spring?eld b. m. tel: 703.644.9045 washington kirkland i. e. tel: 425.820.8100 maple valley b. m. tel: 206.223.0080 seattle a. e. tel: 425.882.7000 w. e. tel: 800.248.9953 west virginia a. e. tel: 800.638.5988 wisconsin milwaukee a. e. tel: 414.513.1500 w. e. tel: 800.867.9953 wauwatosa i. e. tel: 414.258.5338 wyoming a. e. tel: 800.332.9326 w. e. tel: 801.974.9953
direct sales representatives by state (components and boards) e. a. earle associates e. l. electrodyne - ut grp group 2000 i. s. in?nity sales, inc. ion ion associates, inc. r. a. rathsburg associ- ates, inc. sgy synergy associates, inc. arizona tempe e. a. tel: 480.921.3305 california calabasas i. s. tel: 818.880.6480 irvine i. s. tel: 714.833.0300 san diego e. a. tel: 619.278.5441 illinois elmhurst r. a. tel: 630.516.8400 indiana cicero r. a. tel: 317.984.8608 ligonier r. a. tel: 219.894.3184 plain?eld r. a. tel: 317.838.0360 massachusetts burlington sgy tel: 781.238.0870 michigan byron center r. a. tel: 616.554.1460 good rich r. a. tel: 810.636.6060 novi r. a. tel: 810.615.4000 north carolina cary grp tel: 919.481.1530 ohio columbus r. a. tel: 614.457.2242 dayton r. a. tel: 513.291.4001 independence r. a. tel: 216.447.8825 pennsylvania somerset r. a. tel: 814.445.6976 texas austin ion tel: 512.794.9006 arlington ion tel: 817.695.8000 houston ion tel: 281.376.2000 utah salt lake city e. l. tel: 801.264.8050 wisconsin muskego r. a. tel: 414.679.8250 saukville r. a. tel: 414.268.1152
sales of?ces and design resource centers lsi logic corporation corporate headquarters 1551 mccarthy blvd milpitas ca 95035 tel: 408.433.8000 fax: 408.433.8989 north america california irvine 18301 von karman ave suite 900 irvine, ca 92612 tel: 949.809.4600 fax: 949.809.4444 pleasanton design center 5050 hopyard road, 3rd floor suite 300 pleasanton, ca 94588 tel: 925.730.8800 fax: 925.730.8700 san diego 7585 ronson road suite 100 san diego, ca 92111 tel: 858.467.6981 fax: 858.496.0548 silicon valley 1551 mccarthy blvd sales of?ce m/s c-500 milpitas, ca 95035 tel: 408.433.8000 fax: 408.954.3353 design center m/s c-410 tel: 408.433.8000 fax: 408.433.7695 wireless design center 11452 el camino real suite 210 san diego, ca 92130 tel: 858.350.5560 fax: 858.350.0171 colorado boulder 4940 pearl east circle suite 201 boulder, co 80301 tel: 303.447.3800 fax: 303.541.0641 colorado springs 4420 arrowswest drive colorado springs, co 80907 tel: 719.533.7000 fax: 719.533.7020 fort collins 2001 dan?eld court fort collins, co 80525 tel: 970.223.5100 fax: 970.206.5549 florida boca raton 2255 glades road suite 324a boca raton, fl 33431 tel: 561.989.3236 fax: 561.989.3237 georgia alpharetta 2475 north winds parkway suite 200 alpharetta, ga 30004 tel: 770.753.6146 fax: 770.753.6147 illinois oakbrook terrace two mid american plaza suite 800 oakbrook terrace, il 60181 tel: 630.954.2234 fax: 630.954.2235 kentucky bowling green 1262 chestnut street bowling green, ky 42101 tel: 270.793.0010 fax: 270.793.0040 maryland bethesda 6903 rockledge drive suite 230 bethesda, md 20817 tel: 301.897.5800 fax: 301.897.8389 massachusetts waltham 200 west street waltham, ma 02451 tel: 781.890.0180 fax: 781.890.6158 burlington - mint technology 77 south bedford street burlington, ma 01803 tel: 781.685.3800 fax: 781.685.3801 minnesota minneapolis 8300 norman center drive suite 730 minneapolis, mn 55437 tel: 612.921.8300 fax: 612.921.8399 new jersey red bank 125 half mile road suite 200 red bank, nj 07701 tel: 732.933.2656 fax: 732.933.2643 cherry hill - mint technology 215 longstone drive cherry hill, nj 08003 tel: 856.489.5530 fax: 856.489.5531 new york fairport 550 willowbrook of?ce park fairport, ny 14450 tel: 716.218.0020 fax: 716.218.9010 north carolina raleigh phase ii 4601 six forks road suite 528 raleigh, nc 27609 tel: 919.785.4520 fax: 919.783.8909 oregon beaverton 15455 nw greenbrier parkway suite 235 beaverton, or 97006 tel: 503.645.0589 fax: 503.645.6612 texas austin 9020 capital of tx highway north building 1 suite 150 austin, tx 78759 tel: 512.388.7294 fax: 512.388.4171 plano 500 north central expressway suite 440 plano, tx 75074 tel: 972.244.5000 fax: 972.244.5001 houston 20405 state highway 249 suite 450 houston, tx 77070 tel: 281.379.7800 fax: 281.379.7818 canada ontario ottawa 260 hearst way suite 400 kanata, on k2l 3h1 tel: 613.592.1263 fax: 613.592.3253 international france paris lsi logic s.a. immeuble europa 53 bis avenue de l'europe b.p. 139 78148 velizy-villacoublay cedex, paris tel: 33.1.34.63.13.13 fax: 33.1.34.63.13.19 germany munich lsi logic gmbh orleansstrasse 4 81669 munich tel: 49.89.4.58.33.0 fax: 49.89.4.58.33.108 stuttgart mittlerer pfad 4 d-70499 stuttgart tel: 49.711.13.96.90 fax: 49.711.86.61.428 italy milan lsi logic s.p.a. centro direzionale colleoni palazzo orione ingresso 1 20041 agrate brianza, milano tel: 39.039.687371 fax: 39.039.6057867 japan tokyo lsi logic k.k. rivage-shinagawa bldg. 14f 4-1-8 kounan minato-ku, tokyo 108-0075 tel: 81.3.5463.7821 fax: 81.3.5463.7820 osaka crystal tower 14f 1-2-27 shiromi chuo-ku, osaka 540-6014 tel: 81.6.947.5281 fax: 81.6.947.5287
sales of?ces and design resource centers (continued) korea seoul lsi logic corporation of korea ltd 10th fl., haesung 1 bldg. 942, daechi-dong, kangnam-ku, seoul, 135-283 tel: 82.2.528.3400 fax: 82.2.528.2250 the netherlands eindhoven lsi logic europe ltd world trade center eindhoven building rijder bogert 26 5612 lz eindhoven tel: 31.40.265.3580 fax: 31.40.296.2109 singapore singapore lsi logic pte ltd 7 temasek boulevard #28-02 suntec tower one singapore 038987 tel: 65.334.9061 fax: 65.334.4749 sweden stockholm lsi logic ab finlandsgatan 14 164 74 kista tel: 46.8.444.15.00 fax: 46.8.750.66.47 taiwan taipei lsi logic asia, inc. taiwan branch 10/f 156 min sheng e. road section 3 taipei, taiwan r.o.c. tel: 886.2.2718.7828 fax: 886.2.2718.8869 united kingdom bracknell lsi logic europe ltd greenwood house london road bracknell, berkshire rg12 2ub tel: 44.1344.426544 fax: 44.1344.481039 sales of?ces with design resource centers
international distributors australia new south wales reptechnic pty ltd 3/36 bydown street neutral bay, nsw 2089 tel: 612.9953.9844 fax: 612.9953.9683 belgium acal nv/sa lozenberg 4 1932 zaventem tel: 32.2.7205983 fax: 32.2.7251014 china beijing lsi logic international services inc. beijing representative of?ce room 708 canway building 66 nan li shi lu xicheng district beijing 100045, china tel: 86.10.6804.2534 to 38 fax: 86.10.6804.2521 france rungis cedex azzurri technology france 22 rue saarinen sillic 274 94578 rungis cedex tel: 33.1.41806310 fax: 33.1.41730340 germany haar ebv elektronik hans-pinsel str. 4 d-85540 haar tel: 49.89.4600980 fax: 49.89.46009840 munich avnet emg gmbh stahlgruberring 12 81829 munich tel: 49.89.45110102 fax: 49.89.42.27.75 wuennenberg-haaren peacock ag graf-zepplin-str 14 d-33181 wuennenberg-haaren tel: 49.2957.79.1692 fax: 49.2957.79.9341 hong kong hong kong avt industrial ltd unit 608 tower 1 cheung sha wan plaza 833 cheung sha wan road kowloon, hong kong tel: 852.2428.0008 fax: 852.2401.2105 serial system (hk) ltd 2301 nanyang plaza 57 hung to road, kwun tong kowloon, hong kong tel: 852.2995.7538 fax: 852.2950.0386 india bangalore spike technologies india private ltd 951, vijayalakshmi complex, 2nd floor, 24th main, j p nagar ii phase, bangalore, india 560078 tel: 91.80.664.5530 fax: 91.80.664.9748 israel tel aviv eastronics ltd 11 rozanis street p.o. box 39300 tel aviv 61392 tel: 972.3.6458777 fax: 972.3.6458666 japan tokyo daito electron sogo kojimachi no.3 bldg 1-6 kojimachi chiyoda-ku, tokyo 102-8730 tel: 81.3.3264.0326 fax: 81.3.3261.3984 global electronics corporation nichibei time24 bldg. 35 tansu-cho shinjuku-ku, tokyo 162-0833 tel: 81.3.3260.1411 fax: 81.3.3260.7100 technical center tel: 81.471.43.8200 marubeni solutions 1-26-20 higashi shibuya-ku, tokyo 150-0001 tel: 81.3.5778.8662 fax: 81.3.5778.8669 shinki electronics myuru daikanyama 3f 3-7-3 ebisu minami shibuya-ku, tokyo 150-0022 tel: 81.3.3760.3110 fax: 81.3.3760.3101 yokohama-city innotech 2-15-10 shin yokohama kohoku-ku yokohama-city, 222-8580 tel: 81.45.474.9037 fax: 81.45.474.9065 macnica corporation hakusan high-tech park 1-22-2 hadusan, midori-ku, yokohama-city, 226-8505 tel: 81.45.939.6140 fax: 81.45.939.6141 the netherlands eindhoven acal nederland b.v. beatrix de rijkweg 8 5657 eg eindhoven tel: 31.40.2.502602 fax: 31.40.2.510255 switzerland brugg lsi logic sulzer ag mattenstrasse 6a ch 2555 brugg tel: 41.32.3743232 fax: 41.32.3743233 taiwan taipei avnet-mercuries corporation, ltd 14f, no. 145, sec. 2, chien kuo n. road taipei, taiwan, r.o.c. tel: 886.2.2516.7303 fax: 886.2.2505.7391 lumax international corporation, ltd 7th fl., 52, sec. 3 nan-kang road taipei, taiwan, r.o.c. tel: 886.2.2788.3656 fax: 886.2.2788.3568 prospect technology corporation, ltd 4fl., no. 34, chu luen street taipei, taiwan, r.o.c. tel: 886.2.2721.9533 fax: 886.2.2773.3756 wintech microeletronics co., ltd 7f., no. 34, sec. 3, pateh road taipei, taiwan, r.o.c. tel: 886.2.2579.5858 fax: 886.2.2570.3123 united kingdom maidenhead azzurri technology ltd 16 grove park business estate waltham road white waltham maidenhead, berkshire sl6 3lw tel: 44.1628.826826 fax: 44.1628.829730 milton keynes ingram micro (uk) ltd garamonde drive wymbush milton keynes buckinghamshire mk8 8df tel: 44.1908.260422 swindon ebv elektronik 12 interface business park bincknoll lane wootton bassett, swindon, wiltshire sn4 8sy tel: 44.1793.849933 fax: 44.1793.859555 sales of?ces with design resource centers

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