sg559 mobile pentium processor application clock generator with sscg, usb and power management support approved product international microcircuits, inc. 525 los coches st. rev. 1.0 4/12/1999 milpitas, ca 95035 tel: 408-263-6300 ext. 275 fax 408-263-6571 page 1 of 8 product features ? supports clock requirements for mobile pentium ? processor ? 2 host and 5 pci clocks ? separate supply pins for mixed (3.3/2.5v) voltage application. ? <175ps skew among cpu clocks. ? < 250ps skew among pci clocks. ? 48mhz for usb. ? 28-pin ssop package for minimum board space. ? power management capabilities block diagram frequency table sel100/66# cpu pci 0 66.4 mhz* 33.3 mhz 1 99.8 mhz** 33.2 mhz *down spread 1.25% (total); **down spread .5% (total) connection diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 vss vddr ref vddc cpu0 cpu1 vss vdd vss pci_stop# cpu_stop# pwr_dwn# 48m sel100/66# xin xout vss pci_f pci1 vddp pci2 pci3 vddp pci4 pci5 vss vdd vss osc sel1066# pwr_dwn# pci_stop# vddr ref vddc cpuclk (0:1) vddp 48 mhz pci_f pci (1:5) cpu_stop# pll pll xin xout
sg559 mobile pentium processor application clock generator with sscg, usb and power management support approved product international microcircuits, inc. 525 los coches st. rev. 1.0 4/12/1999 milpitas, ca 95035 tel: 408-263-6300 ext. 275 fax 408-263-6571 page 2 of 8 pin description pin no. pin name pwr i/o type description 1 xin vdd i osc1 on-chip reference oscillator input pin. requires either an external parallel resonant crystal (nominally 14.318 mhz) or externally generated reference signal 2 xout vdd o osc1 on-chip reference oscillator output pin. drives an external parallel resonant crystal. when an externally generated reference signal is used at xin, this pin is left unconnected 15 sel100/66# - i padi4 pu frequency select input pins. see frequency select table on page 1.this pin has internal pull-up. 23, 24 cpuclk (0:1) vddc o buf1 clock outputs. cpu frequency table specified on page 1. 4 pci_f vddp o buf4 free running pci clock. when pci_stp# = 0, this clock does not stop. 16 48m vdd48 o buf3 48 mhz fixed clock. 5, 7, 8, 10, 11 pci(1:5) vddp o buf4 pci bus clocks. see frequency select table on page 1. 26 ref vddr o buf3 buffered outputs of on-chip reference oscillator. 19 pci_stop# - i pad pu when driven to a logic low level, this pin will synchronously stop all pci clocks (except pci_f) at a logic low level. 18 cpu_stop# - i pad pu when driven to a logic low level, this pin will synchronously stop all cpu clocks at a logic low level. 17 pwr_dwn# - i pad pu this pin is active low. when asserted low, the device is in shutdown mode. vcos, crystal, and outputs are turned off. 13, 21 vdd - p - 3.3 volt power supply for core logic. 3, 12, 14, 20, 22, 28 vss - p - ground pins for the device. 9, 6 vddp - p - 3.3 volt power supply pins for pci (1:5) and pci_f clock output buffers. 25 vddc - p - 3.3 or 2.5 volt power supply for cpuclk (0:1) outputs. 27 vddr - p 3.3 volt power supply pins for reference clock output buffers and crystal circuit.
sg559 mobile pentium processor application clock generator with sscg, usb and power management support approved product international microcircuits, inc. 525 los coches st. rev. 1.0 4/12/1999 milpitas, ca 95035 tel: 408-263-6300 ext. 275 fax 408-263-6571 page 3 of 8 power management functions all pci (excluding pci_f) and cpu clocks can be enabled or stopped via the pci_stop# and cpu_stop# input pins. all clocks are stopped in the low state. all clocks maintain a valid high period on transitions from running to stopped and on transitions from stopped to running when the chip was not powered down. on power up, the vcos will stabilize to the correct pulse widths within 0.2 ms. the cpu and pci clocks transition between running and stopped by waiting for one positive edge on pci_f followed by a negative edge on the clock of interest, after which high levels of the output are either enabled or disabled. pwr_dwn# cpu_stop# pci_stop# cpuclk pciclk other clks xtal & vcos 1 0 0 low low running running 1 0 1 low running running running 1 1 0 running low running running 1 1 1 running running running running 0 x (dont care) x (dontcare) low low low off power management timing pci_f pci_stop# pciclk(1:5) cpu_stop# cpuclk(0:1) power management timing latency signal signal state no. of rising edges of free running pciclk (pcif) cpu_st0p# 0 (disabled) 1 1 (enabled) 1 pci_st0p# 0 (disabled) 1 1 (enabled) 1 notes: 1. clock on/off latency is defined in the number of rising edges of free running pci clock between the clock disable goes low/high to the first valid clock comes out of the device.
sg559 mobile pentium processor application clock generator with sscg, usb and power management support approved product international microcircuits, inc. 525 los coches st. rev. 1.0 4/12/1999 milpitas, ca 95035 tel: 408-263-6300 ext. 275 fax 408-263-6571 page 4 of 8 spectrum spread clocking spectrum analysis maximum ratings voltage relative to vss: -0.3v voltage relative to vdd: 0.3v storage temperature: -65oc to + 150oc operating temperature: -40oc to +85oc maximum power supply: 7v this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, vin and vout should be constrained to the range: vss<(vin or vout) sg559 mobile pentium processor application clock generator with sscg, usb and power management support approved product international microcircuits, inc. 525 los coches st. rev. 1.0 4/12/1999 milpitas, ca 95035 tel: 408-263-6300 ext. 275 fax 408-263-6571 page 5 of 8 electrical characteristics characteristic symbol min typ max units conditions input low voltage vil - - 0.8 vdc - input high voltage vih 2.0 - - vdc - input low current iil -66 a input high current iih 5 a output low voltage iol = 4ma vol - - 0.4 vdc all outputs (see buffer spec) output high voltage ioh = 4ma voh 2.4 - - vdc all outputs using 3.3v power (see buffer spec) tri-state leakage current ioz - - 10 a dynamic supply current idd - - 140 ma cpu = 66.6 mhz, pci = 33.3 mhz static supply current isdd - - 70 m a pwr_dwn# (pin17) = 0 short circuit current isc 25 - - ma 1 output at a time - 30 seconds vdd = vddp=vddr =3.3v 5 %, vddc = 2.5v 5 %,, ta = -40oc to +85oc switching characteristics characteristic symbol min typ max units conditions output duty cycle - 45 50 55 % measured at 1.5v cpu to pci offset toff 1 3 4 ns 15 pf load measured at 1.5v buffer out skew all cpu and pci buffer outputs tskew - - 250 ps 15 pf load measured at 1.5v d period adjacent cycles d p - - +250 ps - jitter spectrum 20 db bandwidth from center bw j 500 khz vdd = vddp =vddr =3.3v 5 %, vddc = 2.5v 5 %,, ta = -40oc to +85oc
sg559 mobile pentium processor application clock generator with sscg, usb and power management support approved product international microcircuits, inc. 525 los coches st. rev. 1.0 4/12/1999 milpitas, ca 95035 tel: 408-263-6300 ext. 275 fax 408-263-6571 page 6 of 8 buffer 1 characteristics for cpuclk(0:1) characteristic symbol min typ max units conditions pull-up current min ioh min -27 - - ma vout = 1.0 v pull-up current max ioh max - - -27 ma vout = 2.6 v pull-down current min iol min 27 - - ma vout = 1.2 v pull-down current max iol max - - 27 ma vout = 0.3 v dynamic output impedance z o 10 - 15 ohms 66 and 100 mhz rise time between 0.4 v and 2.0 v tr 0.4 - 1.6 ns 20 pf load fall time between 0.4 v and 2.0 v tf 0.5 - 1.6 ns 20 pf load vdd = vddp= vddr =3.3v 5 %, vddc = 2.5v 5 %,, ta = -40oc to +85oc buffer 3 characteristics for ref, 48m characteristic symbol min typ max units conditions pull-up current min ioh min -29 - - ma vout = 1.0 v pull-up current max ioh max - - -23 ma vout = 3.135 v pull-down current min iol min 29 - - ma vout = 1.95 v pull-down current max iol max - - 27 ma vout = 0.4 v dynamic output impedance z o 18 - 25 ohms 66 and 100 mhz rise time between 0.4 v and 2.4 v tr 0.5 - 2.0 ns 20 pf load fall time between 0.4 v and 2.4 v tf 0.5 - 2.0 ns 20 pf load vdd = vddp= vddr =3.3v 5 %, vddc = 2.5v 5 %,, ta = -40oc to +85oc
sg559 mobile pentium processor application clock generator with sscg, usb and power management support approved product international microcircuits, inc. 525 los coches st. rev. 1.0 4/12/1999 milpitas, ca 95035 tel: 408-263-6300 ext. 275 fax 408-263-6571 page 7 of 8 buffer 4 characteristics for pci_f, pci(1:5) characteristic symbol min typ max units conditions pull-up current min ioh min -33 - - ma vout = 1.0 v pull-up current max ioh max - - -33 ma vout = 3.135 v pull-down current min iol min 30 - - ma vout = 1.95 v pull-down current max iol max - - 38 ma vout = 0.4 v dynamic output impedance z o 14 - 20 ohms 66 and 100 mhz rise time between 0.4 v and 2.4 v tr 0.5 - 2.0 ns 30 pf load fall time between 0.4 v and 2.4 v tf 0.5 - 2.0 ns 30 pf load vddp= vddr =3.3v 5 %, vddc = 2.5v 5 %,, ta = -40oc to +85oc crystal and reference oscillator parameters characteristic symbol min typ max units conditions frequency f o 12.00 14.31818 16.00 mhz tolerance tc - - +/-100 ppm calibration note 1 ts - - +/- 100 ppm stability (ta -10 to +60c) note 1 ta - - 5 ppm aging (first year @ 25c) note 1 mode om - - - parallel resonant pin capacitance cp 5 pf capacitance of xin and xout pins dc bias voltage v bias 0.3vdd vdd/2 0.7vdd v startup time ts - - 30 m s load capacitance cl - 20 - pf note 1 effective series resonant resistance r1 - - 40 ohms power dissipation dl - - 0.10 mw note 1 shunt capacitance co - -- 7 pf x1 and x2 load cl 17 pf internal crystal loading capacitors on each pin (to ground) for maximum accuracy, the total circuit loading capacitance should be equal to cl. this loading capacitance is the effective capacitance across the crystal pins and includes the device pin capacitance (cp) in parallel with any circuit traces, the clock generator and any onboard discrete load capacitors. budgeting calculations typical trace capacitance, (< half inch) is 4 pf, load to the crystal is therefore 2.0 pf clock generator internal pin capacitance of 36 pf, load to the crystal is therefore 18.0 pf the total parasitic capacitance would therefore be = 20.0 pf(matching cl) note 1: it is recommended but not mandatory that a crystal meets these specifications.
sg559 mobile pentium processor application clock generator with sscg, usb and power management support approved product international microcircuits, inc. 525 los coches st. rev. 1.0 4/12/1999 milpitas, ca 95035 tel: 408-263-6300 ext. 275 fax 408-263-6571 page 8 of 8 package drawing and dimensions 28 pin ssop outline dimensions inches millimeters symbol min nom max min nom max a 0.068 0.073 0.078 1.73 1.86 1.99 a 1 0.002 0.005 0.008 0.05 0.13 0.21 a2 0.066 0.068 0.070 1.68 1.73 1.78 b 0.010 0.012 0.015 0.25 0.30 0.38 c 0.005 0.006 0.009 0.13 0.15 0.22 d 0.397 0.402 0.407 10.07 10.20 10.33 e 0.205 0.209 0.212 5.20 5.30 5.38 e 0.0256 bsc 0.65 bsc h 0.301` 0.307 0.311 7.65 7.80 7.90 a 0 4 8 0 4 8 l 0.022 0.030 0.037 0.55 0.75 0.95 ordering information part number package type production flow imisg559ayb 28 pin ssop commercial, -40oc to +85oc note: the ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. marking: example: imi sg559ayb date code, lot # imisg559ayb flow b = commercial, -40oc to + 85oc package y = ssop revision imi device number b e a a 1 a 2 e a l c d h
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