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41d1c855d 863c@39 9c4>"24c 9c4>84<3696?s_^db_\\ub gydx cdq^t@39y^dubvqsu q^t esxy`ce``_bd copyright 1994-1999 cologne chip designs gmbh all rights reserved the information presented can not be considered as assured characteristics. data can change without notice. parts of the information presented may be protected by patent or other rights. 6urbeqbi!)))
863c @39 "_v&$ 6urbeqbi !))) revision history date remarks feb. 1999 changes made on: clkdel register bit description. jan. 1999 new chip released: hfc-s pci a is compliant to pci spec 2.2 . the old chip hfc-s pci is not recommended for new projects. sep. 1998 changes made on: electrical characteristics, part list: c3 and c4 must be 22pf. aug. 1998 changes made on: fifo_en register bit description. aug. 1998 changes made on: part list: c3 and c4 must be 47pf, c5 and c6 have been removed . july 1998 changes made on: pci buffer signaling and power supply environment, pci configuration registers, b_mode register bit description july 1998 changes made on: block diagram, sample circuitry, part list: q2 and q3 must be bc850c instead of bc848b june 1998 schematic of pci sample board corrected; digital part added may 1998 changes made on: reset characteristics, pci modes supported, pci buffer signaling environment, pci configuration registers, timer, fifo counters location in mw, automatically d-channel frame repetition, fifo initialisation, trxr register bit description, ctmt register bit description, chip_id register bit description, fifo_en register bit description, trm register bit description, electrical characteristics, s/t module part numbers and manufacturers, sample circuitry eintrachtstrasse 113 d-50668 k?ln germany tel.: +49 (0) 221 / 912 96 04 fax: +49 (0) 221 / 912 96 05 http://www.colognechip.com http://www.colognechip.de colognechip@t-online.de
863c @39 6urbeqbi !))) #_v&$ contents 1 general description.......................................................................................................... ........................ 6 1.1 applications ............................................................................................................... ............................. 7 2 pin description.............................................................................................................. ............................ 8 2.1 pci bus interface.......................................................................................................... ........................... 8 2.2 auxiliary port............................................................................................................. ........................... 10 2.3 s/t interface transmit signals ............................................................................................. .................. 10 2.4 s/t interface receive signals .............................................................................................. ................... 10 2.5 oscillator................................................................................................................. .............................. 11 2.6 gci/iom2 bus interface ..................................................................................................... .................. 11 2.7 gci/iom2 timeslot enable signals ........................................................................................... ........... 11 2.8 eeprom interface ........................................................................................................... .................... 11 2.9 power supply............................................................................................................... .......................... 12 2.10 reset characteristics ..................................................................................................... ................... 12 3 functional description....................................................................................................... .................... 13 3.1 pci-interface .............................................................................................................. ........................... 13 3.1.1 pci access types used by hfc-s pci....................................................................................... ..... 13 3.1.2 pci modes supported...................................................................................................... ............... 13 3.1.3 pci buffer signaling and power supply environment .................................................................... 13 3.1.4 pci configuration registers.............................................................................................. .............. 14 3.2 internal hfc-s pci register description.................................................................................... ........... 17 3.2.1 registers of the s/t section............................................................................................. .............. 18 3.2.2 registers of the gci/iom2 bus section .................................................................................... .... 19 3.2.3 interrupt and status registers........................................................................................... ............... 20 3.3 timer...................................................................................................................... ............................... 21 3.4 fifos ...................................................................................................................... .............................. 22 3.4.1 fifo counters location in memory window ................................................................................ 23 3.4.2 fifo data location in memory window ...................................................................................... .24 3.4.3 fifo channel operation ................................................................................................... .............. 25 3.4.3.1 send channels (b1, b2 and d transmit) ................................................................................. 2 5 3.4.3.2 automatically d-channel frame repetition............................................................................. 26 3.4.3.3 fifo full condition in send channels ................................................................................... .. 26 3.4.3.4 receive channels (b1, b2 and d receive)............................................................................. 26 3.4.3.5 fifo full condition in receive channels................................................................................ .28 3.4.3.6 fifo initialisation .................................................................................................... .............. 28 3.4.4 transparent mode of hfc-s pci ............................................................................................ ...... 29 4 register bit description ..................................................................................................... .................... 30 4.1 register bit description of s/t section .................................................................................... ............. 30 4.2 register bit description of gci/iom2 bus section ........................................................................... .... 33 4.3 register bit description of connect register............................................................................... ..... 36 4.4 register bit description of auxiliary and cross data registers ............................................................. .. 37 5 electrical characteristics ................................................................................................... .................... 42 6 timing characteristics ....................................................................................................... .................... 46 6.1 pci bus timing ............................................................................................................. ......................... 46 6.2 gci/iom2 bus clock and data alignment for mitel st tm bus.............................................................. 46 6.3 gci/iom2 timing............................................................................................................ ...................... 47 6.4 eeprom access .............................................................................................................. ..................... 48
863c @39 $_v&$ 6urbeqbi !))) 7 s/t interface circuitry ...................................................................................................... ..................... 49 7.1 external receiver circuitry ................................................................................................ .................... 49 7.2 external transmitter circuitry............................................................................................. ................... 50 7.3 oscillator circuitry ....................................................................................................... ......................... 53 7.4 eeprom circuitry........................................................................................................... ..................... 53 7.5 pme pin circuitry.......................................................................................................... ........................ 54 8 state matrices for nt and te................................................................................................. .............. 55 8.1 s/t interface activation/deactivation layer 1 for finite state matrix for nt ......................................... 55 8.2 activation/deactivation layer 1 for finite state matrix for te ............................................................. .56 9 binary organisation of the frames............................................................................................ ............ 57 9.1 s/t frame structure ........................................................................................................ ....................... 57 9.2 gci frame structure ........................................................................................................ ...................... 58 10 clock synchronisation ....................................................................................................... .................. 59 10.1 clock synchronisation in nt-mode .......................................................................................... .......... 59 10.2 clock synchronisation in te-mode .......................................................................................... .......... 60 11 hfc-s pci package dimensions ................................................................................................ ........ 61 12 isdn pci card sample circuitry with hfc-s pci........................................................................... 62 figures figure 1: hfc-s pci block diagram.............................................................................................. ............... 7 figure 2: pin connection ....................................................................................................... ....................... 8 figure 3: hfc-s pci in i/o address mapped mode................................................................................. ... 17 figure 4: hfc-s pci in memory address mapped mode............................................................................ 17 figure 5: fifo organisation (shown for b-channel, similar for d-channel) ............................................. 25 figure 6: fifo data organisation ............................................................................................... ............... 27 figure 7: function of the connect register bits................................................................................ ..... 36 figure 8: gci/iom2 bus clock and data alignment................................................................................ .... 46 figure 9: external receiver circuitry.......................................................................................... ................. 49 figure 10: external transmitter circuitry ...................................................................................... .............. 50 figure 11: oscillator circuitry................................................................................................ .................... 53 figure 12: eeprom circuitry .................................................................................................... ................ 53 figure 13: pme pin circuitry ................................................................................................... ................... 54 figure 14: frame structure at reference point s and t .......................................................................... ..... 57 figure 15: single channel gci format........................................................................................... ............. 58 figure 16: clock synchronisation in nt-mode .................................................................................... ...... 59 figure 17: clock synchronisation in te-mode .................................................................................... ....... 60 figure 18: hfc-s pci package dimensions ........................................................................................ ....... 61
863c @39 6urbeqbi !))) %_v&$ tables table 1: pci command types ..................................................................................................... ................. 13 table 2: pci configuration registers' initial values........................................................................... .......... 17 table 3: s/t module part numbers and manufacturer .............................................................................. .. 52 table 4: activation/deactivation layer 1 for finite state matrix for nt ..................................................... 55 table 5: activation/deactivation layer 1 for finite state matrix for te...................................................... 56 timing diagrams timing diagram 3: gci/iom2 timing.............................................................................................. ........... 47 timing diagram 4: eeprom access ................................................................................................ .......... 48
863c @39 &_v&$ 6urbeqbi !))) features ? one chip isdn-s-controller with b- and d-channel hdlc support ? independent read and write hdlc-channels for 2 isdn b-channels and one isdn d-channel ? b1- and b2-channel transparent mode independently selectable ? fifo-memory-window: 4x 7.5 kbyte (b-channel) and 2x 512 byte (d-channel) ? max. 31 hdlc frames (b-channel) and 15 hdlc frames (d-channel) per channel and direction in fifo ? 56 kbit/s restricted mode for u.s. isdn lines selectable ? full i.430 itu s/t isdn support in te and nt mode ? b1+b2 hdlc mode ? pcm30 interface configurable to interface mitel st tm bus (mvip tm ), siemens iom2 tm or gci tm for interface to u-chip or external codecs ? integrated pci spec. 2.1 bus interface for 3.3v and 5v bus signals ? direct access to pcm30 interface for tone synthetisation ? 3.3v and 5v supply voltage ? rectangular qfp 100 case 1 general description the hfc-s pci is an isdn s/t hdlc basic rate controller for so called ?passive isdn pc cards with integrated s/t interface and pcm30 highway interface. it is the first all in one solution for a pci isdn pc-card world wide with power management and windows 98 support. a 32kbyte memory window of the pc is used for the deep fifos. also an industrial standard serial interface for telecom peripheral ics is implemented. codecs are normally connected to this interface.
863c @39 6urbeqbi !))) '_v&$ 1.1 applications ? isdn pci pc card figure 1: hfc-s pci block diagram
863c @39 (_v&$ 6urbeqbi !))) 2 pin description 2.1 pci bus interface for further information please refer to the pci local bus specification. pin no. pin name input output function 47 ad0 i/o pci address bus address bit 0 46 ad1 i/o address bit 1 45 ad2 i/o address bit 2 44 ad3 i/o address bit 3 43 ad4 i/o address bit 4 42 ad5 i/o address bit 5 41 ad6 i/o address bit 6 40 ad7 i/o address bit 7 37 ad8 i/o address bit 8 36 ad9 i/o address bit 9 35 ad10 i/o address bit 10 34 ad11 i/o address bit 11 33 ad12 i/o address bit 12 32 ad13 i/o address bit 13 31 ad14 i/o address bit 14 30 ad15 i/o address bit 15 figure 2: pin connection
863c @39 6urbeqbi !))) )_v&$ pin no. pin name input output function 16 ad16 i/o address bit 16 15 ad17 i/o address bit 17 14 ad18 i/o address bit 18 13 ad19 i/o address bit 19 12 ad20 i/o address bit 20 11 ad21 i/o address bit 21 10 ad22 i/o address bit 22 9 ad23 i/o address bit 23 4 ad24 i/o address bit 24 3 ad25 i/o address bit 25 2 ad26 i/o address bit 26 1 ad27 i/o address bit 27 100 ad28 i/o address bit 28 99 ad29 i/o address bit 29 98 ad30 i/o address bit 30 97 ad31 i/o address bit 31 26 par i/o parity bit 38 c/be0 i/o bus command and byte enable 0 27 c/be1 i/o bus command and byte enable 1 18 c/be2 i/o bus command and byte enable 2 5 c/be3 i/o bus command and byte enable 3 93 clk i pci clock 92 rst# i reset 19 frame# i/o cycle frame 20 irdy# i/o initiator ready 21 trdy# i/o target ready 23 stop# i/o stop 6 idsel i initialisation device select 22 devsel# i/o device select 95 req# o request 94 gnt# i grant 24 perr# i/o parity error 25 serr# o system error 53 pme o power management event (high active) see also: figure 13 on page 54 91 inta# o interrupt a
863c @39 ! _v &$ 6urbeqbi !))) 2.2 auxiliary port pin no. pin name input output function 75 daux0 i/o aux data bit 0 74 daux1 i/o aux data bit 1 73 daux2 i/o aux data bit 2 72 daux3 i/o aux data bit 3 71 daux4 i/o aux data bit 4 70 daux5 i/o aux data bit 5 69 daux6 i/o aux data bit 6 68 daux7 i/o aux data bit 7 67 /aux_wr o aux write 66 /aux_rd o aux read 65 /adr_wr i/o d) aux address write d) internal pull down 2.3 s/t interface transmit signals 88 tx2_hi o transmit output 2 87 /tx1_lo o gnd driver for transmitter 1 86 /tx_en o transmit enable 85 /tx2_lo o gnd driver for transmitter 2 84 tx1_hi o transmit output 1 see also: 7.2 external transmitter circuitry. 2.4 s/t interface receive signals 82 r2 i receive data 2 81 lev_r2 i level detect for r2 80 lev_r1 i level detect for r1 79 r1 i receive data 1 78 adj_lev o levelgenerator see also: 7.1 external receiver circuitry.
863c @39 6urbeqbi !))) !! _v &$ 2.5 oscillator pin no. pin name input output function 51 osc_in i oscillator input or quarz connection 12.288 mhz 50 osc_out o oscillator output or quarz connection 2.6 gci/iom2 bus interface 54 c4io i/o u) 4.096 mhz clock gci/iom2 bus clock master: output gci/iom2 bus clock slave: input (reset default) 55 f0io i/o u) frame synchronisation, 8khz pulse for gci/iom2 bus frame synchronisation gci/iom2 bus master: output gci/iom2 bus slave: input (reset default) 56 stio1 i/o u) gci/iom2 bus databus i slotwise programmable as input or output 57 stio2 i/o u) gci/iom2 bus databus ii slotwise programmable as input or output u) internal pull up 2.7 gci/iom2 timeslot enable signals (e. g. for pcm codecs) 58 f1_a o enable signal for external codec a programmable as positive (reset default) or negative pulse. 59 f1_b o enable signal for external codec b programmable as positive (reset default) or negative pulse. 2.8 eeprom interface the external eeprom is optional. ee_scl/en must be connected to gnd if no external eeprom is available. 63 ee_sda i/o u) serial data of external eeprom 62 ee_scl/en i/o u) clock of external eeprom / eeprom enable u) internal pull up
863c @39 !" _v &$ 6urbeqbi !))) 2.9 power supply pin no. pin name function 7, 28, 48, 60, 76, 89 vdd vdd (+3.3v or +5v) 8, 17, 29, 39, 49, 52, 61, 64, 77, 83, 90, 96 gnd gnd * important! all power supply pins vdd must be directly connected to each other. also all pins gnd must be directly connected to each other. to keep vdd and gnd bounce to a minimum a bypass capacitor (10 nf to 100 nf) should be placed between each pair of vdd/gnd pins. 2.10 reset characteristics the reset signal (hardware reset or software reset) must be active for at least 4 clock cycles. the gci/iom2 bus lines stio1, stio2 and the interrupt lines are in tristate mode after a reset. the hfc-s pci is in slave mode after reset. c4io and f0io are inputs. the s/t state machine is stuck to '0' after reset. this means the hfc-s pci does not react to any signal on the s/t interface before the s/t state machine is initialised. the registers' initial values are described in the register bit description (section 4 of this data sheet). during initialisation phase the hfc-s pci must not be accessed. bit 1 of the status register is cleared to '0' to indicate that the initialisation phase has been finished.
863c @39 6urbeqbi !))) !# _v &$ 3 functional description 3.1 pci-interface 3.1.1 pci access types used by hfc-s pci c/be3# c/be2# c/be1# c/be0# command type hfc-s pci mode 0 0 1 0 i/o read target mode 0 0 1 1 i/o write target mode 0 1 1 0 memory read target mode and master mode 0 1 1 1 memory write target mode and master mode 1 0 1 0 configuration read target mode 1 0 1 1 configuration write target mode table 1: pci command types 3.1.2 pci modes supported the hfc-s pci supports both target mode and master mode. before the hfc-s pci can operate in master mode the 32k memory window base address register (mwba) must be configured. afterwards all fifo data accesses are done by the hfc-s pci automatically by pci master accesses. only control and configuration register accesses must be done by pci target accesses by the host cpu. 3.1.3 pci buffer signaling and power supply environment the hfc-s pci supports 5v and 3.3v pci bus environments. the environment mode is set during reset (rst# low) by the input value of /adr_wr. pci bus power and signaling environment /ard_wr during rst# low 3.3v high *) 5v low *) external pull-up resistor required (10k)
863c @39 !$ _v &$ 6urbeqbi !))) 3.1.4 pci configuration registers
863c @39 6urbeqbi !))) !% _v &$ the external eeprom is optional. if no eeprom is available, ee_scl/en must be connected to gnd. without eeprom the pci configuration registers will be loaded with the default values shown in table 2. all registers which can be read from eeprom can also be written by configuration write accesses. the addresses for configuration write are shown in the table below. register name default value remarks vendor id 1397h value can be read from eeprom. base address for configuration write is c0h. device id 2bd0h value can be read from eeprom. base address for configuration write is c0h. command register bits function 0 enables/disables i/o space accesses. 1 enables/disables memory space accesses. 2 enables/disables master accesses. 5..3 fixed to '0' 6 perr# enable/disable 7 fixed to '0' 8 serr# enable/disable 15..9 fixed to '0' status register 0210h bits[7:0] can be read from eeprom. base address for configuration write is c4h. bits function 3..0 reserved 4 fixed to '1' 5 66mhz capable 6 user definable features supported 7 fast back-to-back capable 8 data parity error detected 10..9 fixed to '01': timing of devsel# is medium 11 signaled target abort (fixed to '0') 12 received target abort 13 received master abort 14 signaled system error (addr. parity error) 15 detected partity error revision id 01h class code 02 80 00h value can be read from eeprom. base address for configuration write is c8h. latency timer 10h set to 16 clocks, value is fixed. header type 00h header type 0 bist 00h no build in self test supported. i/o base address bits[31:3] are r/w by configuration accesses memory base address bits[31:8] are r/w by configuration accesses subsystem vendor id 1397h value can be read from eeprom. base address for configuration write is ech. subsystem id 2bd0h value can be read from eeprom. base address for configuration write is ech. cap_ptr 40h offset to power management register block.
863c @39 !& _v &$ 6urbeqbi !))) register name default value remarks interrupt line ffh this register must be configured by configuration write. interrupt pin 01h inta supported min_gnt 00h value can be read from eeprom. base address for configuration write is fch. max_lat 10h value can be read from eeprom. base address for configuration write is fch. cap_id 01h capability id. 01h identifies the linked list item as pci power management registers. next ptr 00h there are no next items in the linked list. pmc 7e21h power management capabilities. see also pci bus power management interface specification. this register's value can be read from eeprom. base address for configuration write is e0h. pme# can be asserted from d0, d1, d2 and d3 hot . device specific initialisation is required. the hfc-s pci does not require pci-clock to generate pme# (if s/t change state is selected). this function complies with the pci power management spec. version 1.0. pmcsr 0000h power management control/status bits function 15 pme_status - this bit is set when the function would normally assert the pme # signal independent of the state of the pme_en bit. writing a '1' to this bit will clear it and cause the function to stop asserting a pme # (if enabled). writing a '0' has no effect. 14..9 fixed to '0' 8 pme_en - a '1' enables the function to assert pme#. when '0', pme # assertion is disabled. 7..2 fixed to '0' 1..0 powerstate - this 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. 00b - d0 01b - d1 10b - d2 11b - d3 hot all states except d0 disable hfc-s pci master accesses.
863c @39 6urbeqbi !))) !' _v &$ register name default value remarks 32k memory window base address (mwba) 0000h bits[31:15] are r/w by configuration accesses. the 32k memory window is for hfc-s pci internal use and for the b- and d-channel fifos. this register must be written by a "dword config write" to enable the hfc-s pci to operate in master mode. table 2: pci configuration registers' initial values unimplemented registers return all 0's when read. 3.2 internal hfc-s pci register description if the hfc-s pci is used in memory mapped mode all register can directly be accessed by adding their cip address to the configured memory base address. in i/o address mapped mode the hfc-s pci occupies 8 bytes in the i/o address space. byte 0 is for data read/write, byte 4 for register selection. the aux-port address is selected by byte 3, aux-port data is read/written by byte 1. figure 3: hfc-s pci in i/o address mapped mode figure 4: hfc-s pci in memory address mapped mode
863c @39 !( _v &$ 6urbeqbi !))) 3.2.1 registers of the s/t section cip / i/o-address name r/w function 1100 0000 c0h states r/w state of the te/nt state machine 1100 0100 c4h sctrl w s/t control register 1100 1000 c8h sctrl_e w s/t control register (extended) 1100 1100 cch sctrl_r w receive enable for b-channels 1101 0000 d0h sq_rec r receive register for s/q bits sq_send w send register for s/q bits 1101 1100 dch clkdel w setup of the delay time between receive and send direction (te) receive data sample time (nt) 1111 0000 f0h b1_rec *) r b1-channel receive register b1_send *) w b1-channel transmit register 1111 0100 f4h b2_rec *) r b2-channel receive register b2_send *) w b2-channel transmit register 1111 1000 f8h d_rec *) r d-channel receive register d_send *) w d-channel transmit register 1111 1100 fch e_rec *) r e-channel receive register *) these registers are read/written automatically by the hdlc fifo controller (hfc) or gci/iom2 bus controller and need not be accessed by the user. to read/write data the fifos in the memory window should be used.
863c @39 6urbeqbi !))) !) _v &$ 3.2.2 registers of the gci/iom2 bus section gci/iom2 bus timeslot selection registers cip / i/o-address name r/w function 0000 1000 08h c/i r/w c/i command/indication register 0000 1100 0ch trxr r monitor tx ready handshake 0010 1000 28h mon1_d r/w first monitor byte 0010 1100 2ch mon2_d r/w second monitor byte gci/iom2 bus timeslot selection registers cip / i/o-address name r/w function 1000 0000 80h b1_ssl w b1-channel transmit slot (0..31) 1000 0100 84h b2_ssl w b2-channel transmit slot (0..31) 1000 1000 88h aux1_ssl w aux1-channel transmit slot (0..31) 1000 1100 8ch aux2_ssl w aux2-channel transmit slot (0..31) 1001 0000 90h b1_rsl w b1-channel receive slot (0..31) 1001 0100 94h b2_rsl w b2-channel receive slot (0..31) 1001 1000 98h aux1_rsl w aux1-channel receive slot (0..31) 1001 1100 9ch aux2_rsl w aux2-channel receive slot (0..31) gci/iom2 bus data registers cip / i/o-address name r/w function 1010 0000 a0h b1_d *) r/w gci/iom2 bus b1-channel data register 1010 0100 a4h b2_d *) r/w gci/iom2 bus b2-channel data register 1010 1000 a8h aux1_d r/w aux1-channel data register 1010 1100 ach aux2_d r/w aux2-channel data register *) these registers are read/written automatically by the hdlc fifo controller (hfc) or by the s/t controller and need not be accessed by the user.
863c @39 " _v &$ 6urbeqbi !))) gci/iom2 bus configuration registers cip / i/o-address name r/w function 1011 0100 b4h mst_emod w extended mode register for gci/iom2 bus 1011 1000 b8h mst_mode w mode register for gci/iom2 bus 1011 1100 bch connect w connect functions for s/t, hfc, gci/iom2 3.2.3 interrupt and status registers cip / i/o address name r/w function 0100 0100 44h fifo_en w fifo enable/disable 0100 1000 48h trm w transparent mode interrupt mode register 0100 1100 4ch b_mode w mode of b-channels 0101 1000 58h chip_id r register for chip identification 0110 0000 60h cirm w interrupt selection and softreset register 0110 0100 64h ctmt w transparent mode and timer control register 0110 1000 68h int_m1 w interrupt mask register 1 0110 1100 6ch int_m2 w interrupt mask register 2 0111 1000 78h int_s1 r interrupt status register 1 0111 1100 7ch int_s2 r interrupt status register 2 0111 0000 70h status r common status register
863c @39 6urbeqbi !))) "! _v &$ 3.3 timer the hfc-s pci includes a timer with interrupt capability. the timer counts f0io pulses. so the timer counter is incremented every 125s. it can be reset by bit 7 of of the ctmt register. furthermore the timer is reset at every hfc-s pci access when bit 5 of the ctmt register is set. seven different timer values can be selected.
863c @39 "" _v &$ 6urbeqbi !))) 3.4 fifos all fifos are located in the 32k memory window (mw) in host pc's memory. there are 6 fifos with 6 hdlc-controllers handled by the hfc-s pci. the hdlc circuits are located on the s/t device side of the hfc-s pci. so always plain data is stored in the fifo. zero insertion and deletion is done in hdlc mode: C if the data goes to the s/t or gci/iom device in send fifos and C when the hdlc data comes from the s/t device or gci/iom2 bus in receive operation. there are a send and a receive fifo for each of the two b-channels and for the d-channel. the fifos are realized as ring buffers in the 32k memory window in host pc's memory. to control them there are some counters. b-channel d-channel z1: fifo input counter 13 bit 9 bit z2: fifo output counter 13 bit 9 bit each counter points to a byte position in the memory window. this is an offset to the 32k memory window base address in the configuration space. on a fifo input operation z1 is incremented. on an output operation z2 is incremented. after every pulse on the f0io signal two hdlc-bytes are written into the s/t interface (fifos no. 0 and 2) and two hdlc-bytes are read from the s/t interface (fifos no. 1 and 3). d-channel data is handled in a similar way but only 2 bits are processed. * important! instead of the s/t interface also gci/iom2 bus is selectable for each b-channel (see connect register). if z1 = z2 the fifo is empty. additionally there are two counters f1 and f2 for every fifo channel (5bit for b-channel, 4bit for d- channel). they count the hdlc-frames in the fifos and form a ring buffer as z1 and z2 do, too. f1 is incremented when a complete frame has been received and stored in the fifo. f2 is incremented when a complete frame has been read from the fifo. if f1 = f2 there is no complete frame in the fifo. when the reset line is active or software reset is active z1, z2, f1 and f2 are all initialized to all 1s. all zx and fx counters are also stored in the memory window. so it is easy to read and write the counters by simple host memory accesses.
863c @39 6urbeqbi !))) "# _v &$ because the hfc-s pci is limited to the 32k memory window data in different regions of the host pc can not be overwritten even if counter and pointer values are handled in a wrong way. * important! the counter state 0200h of the z-counters follows counter state 1fffh in the b-channel fifos. the counter state 000h of the z-counters follows counter state 1ffh in the d-channel fifos. the counter state 00h of the f-counters follows counter state 1fh in the b-channel fifos. the counter state 10h of the f-counters follows counter state 1fh in the d-channel fifos. 3.4.1 fifo counters location in memory window for each fifo one f1 and one f2 counter is available. the counters are located at the following offsets to the memory window base address (mwba) in the memory window (mw). fifo counter offset to memory window base address counter size in bytes b1-transmit f1 2080h 1 f2 *) 2081h 1 b1-receive f1 *) 6080h 1 f2 6081h 1 b2-transmit f1 2180h 1 f2 *) 2181h 1 b2-receive f1 *) 6180h 1 f2 6181h 1 d-transmit f1 20a0h 1 f2 *) 20a1h 1 d-receive f1 *) 60a0h 1 f2 60a1h 1 *) these counters are handled by the hfc-s pci automatically and must not be written by software.
863 c @39 " $ _ v &$ 6urbeqb i !))) for each f i fo an arra y of z 1 and z 2 counters is a v ailable. the offset of the counters to the me m ory window base address (mwba) can be calculated as shown in the followin g table. fifo counter o f f set to memory window base address counter size in bytes b1 - trans m it z 1 2000h + (fx * 4) 2 z2 *) 2000h + (fx * 4) + 2 2 b1 - recei v e z 1 *) 6000h + (fx * 4) 2 z 2 6000h + (fx * 4) + 2 2 b2 - trans m it z 1 2100h + (fx * 4) 2 z2 *) 2100h + (fx * 4) + 2 2 b2 - recei v e z 1 *) 6100h + (fx * 4) 2 z 2 6100h + (fx * 4) + 2 2 d - trans m it z 1 2080h + (fx * 4) 2 z2 *) 2080h + (fx * 4) + 2 2 d - recei v e z 1 *) 6080h + (fx * 4) 2 z 2 6080h + (fx * 4) + 2 2 *) these counters are handled b y the hfc - s pc i auto m aticall y and m ust not be written b y software. fx is either f1 or f2. f1 is used for input data in trans m it f i fos, f2 is used for output data in recei v e f i fos. 3.4.2 fifo data location in memory window fifo starting at o f f set ending at o f f set o f f set to add to z -counters value b1 - trans m it 0200h 1fffh 0000h b1 - recei v e 4200h 5fffh 4000h b2 - trans m it 2200h 3fffh 2000h b2 - recei v e 6200h 7fffh 6000h d - trans m it 0000h 01ffh 0000h d - recei v e 4000h 41ffh 4000h
863c @39 6urbeqbi !))) "% _v &$ 3.4.3 fifo channel operation 3.4.3.1 send channels (b1, b2 and d transmit) the send channels send data from the host bus interface to the fifo and the hfc-s pci converts the data into hdlc code and tranfers it from the fifo into the s/t or/and the gci/iom2 bus interface write registers. the hfc-s pci checks z1 and z2. if z1=z2 (fifo empty) the hfc-s pci generates a hdlc-flag (01111110) and sends it to the s/t device. in this case z2 is not incremented. if also f1=f2 only hdlc flags are sent to the s/t interface and all counters remain unchanged. if the frame counters are unequal f2 is incremented and the hfc-s pci tries to send the next frame to the output device. after the end of a frame (z2 reaches z1) it automatically generates the 16 bit crc checksum and adds the ending flag. if there is another frame in the fifo (f1 1 f2) the f2 counter is incremented. with every byte being sent from the host bus side to the fifo z1 is incremented automatically. if a complete frame has been sent f1 must be incremented to send the next frame. if the frame counter f1 is incremented also the z-counters may change because z1 and z2 are functions of f1 and f2. so there are z1(f1), z2(f1), z1(f2) and z2(f2) (see figure 5). z1(f1) is used for the frame which is just written from the pc-bus side. z2(f2) is used for the frame which is just beeing transmitted to the s/t device side of the hfc-s pci. z1(f2) is the end of frame pointer of the current output frame. figure 5: fifo organisation (shown for b-channel, similar for d-channel)
863c @39 "& _v &$ 6urbeqbi !))) in the send channels f1 is only changed from the pc interface side if the software driver wants to say ?end of send frame. then the current value of z1 is stored, f1 is incremented and z1 is used as start address of the next frame. z1(f2) and z2(f2) can not be accessed. 3.4.3.2 automatically d-channel frame repetition the d-channel send fifo has a special feature. if the s/t interface signals a d-channel contention before the crc is sent the z2 counter is set to the starting address of the current frame and the hfc-s pci tries to repeat the frame automatically. * important! the hfc-s pci begins to transmit bytes from a fifo at the moment z1 1 z2. so if the z1 pointer is updated by software after writing the transmit data into the fifo space of the memory window the transmission starts. 3.4.3.3 fifo full condition in send channels fifo full condition can easily be calculated from the z1/z2 table in the memory window. remember that an increment of z-value 1fffh is 0200h in the b-channels! there are two different fifo full conditions. the first one is met when the fifo contents comes up to 31 frames (b-channel) or 15 frames (d-channel). there is no possibility for the hfc-s pci to manage more frames even if the frames are very small. the second limitation is the size of the fifo which is 512 byte for the d-channel and 7.5 kbyte for the b-channels. 3.4.3.4 receive channels (b1, b2 and d receive) the receive channels receive data from the s/t or gci/iom2 bus interface read registers. the data is converted from hdlc into plain data and sent to the fifo. the data can then be read via the host bus interface. the hfc-s pci checks the hdlc data coming in. if it finds a flag or more than 5 consecutive 1s it does not generate any output data. in this case z1 is not incremented. proper hdlc data being received is converted by the hfc-s pci into plain data. after the ending flag of a frame the hfc-s pci checks the hdlc crc checksum. if it is correct one byte with all 0s is inserted behind the crc data in the fifo named stat. this last byte of a frame in the fifo is different from all 0s if there is no correct crc field at the end of the frame.
863c @39 6urbeqbi !))) "' _v &$ the ending flag of a hdlc-frame can also be the starting flag of the next frame. after a frame is received completely f1 is incremented by the hfc-s pci automatically and the next frame can be received. after reading a frame via the host bus interface f2 must be incremented. if the frame counter f2 is incremented also the z-counters may change because z1 and z2 are functions of f1 and f2. so there are z1(f1), z2(f1), z1(f2) and z2(f2) (see figure 5). z1(f1) is used for the frame which is just received from the s/t device side of the hfc. z2(f2) is used for the frame which is just beeing transmitted to the host bus interface. z1(f2) is the end of frame pointer of the current output frame. to calculate the length of the current receive frame the software has to evaluate z1-z2+1. in the receive channels f2 must be incremented to point to the next z1/z2 pair. if z1 = z2 and f1 = f2 the fifo is totally empty. figure 6: fifo data organisation
863c @39 "( _v &$ 6urbeqbi !))) 3.4.3.5 fifo full condition in receive channels because the isdn-b-channels and the isdn-d-channels have no hardware based flow control there is no possibility to stop input data if a receive fifo is full. so there is no fifo full condition implemented in the hfc-s pci. the hfc-s pci assumes that the fifos are so deep that the host processor hard- and software is able to avoid any overflow of the receive fifos. overflow conditions are again more than 31 input frames (15 frames for d-channel) or a real overflow of the fifo because of excessive data. because hdlc procedures only know a window size of 7 frames no more than 7 frames are sent without software intervention. due to the great size of the fifos of the hfc-s pci it is easy to poll counters in the memory window even in large time intervalls without having to fear a fifo overflow condition. however to avoid any undetected fifo overflows the software driver should check the number of frames in the fifo which is f1-f2. an overflow exists if the number (f1-f2) is less than the number in the last reading even if there was no reading of a frame in between. after a detected fifo overflow condition this fifo must be reset. 3.4.3.6 fifo initialisation all counters z1, z2, f1 and f2 of all fifos are initialized to all 1s after a reset. then the result is z1 = z2 = 1fffh and f1 = f2 = 1fh for the b-channels and z1 = z2 = 1ffh and f1 = f2 = 1fh for the d-channel. this information is written in the memory window for initialisation. please mask bit 4 of d-channel from counter f1, f2. the same initialisation is done if the bit 3 in the cirm register is set (soft reset). during initialisation phase the hfc-s pci must not be accessed. bit 1 of the status register is cleared to '0' to indicate that the initialisation phase has been finished.
863c @39 6urbeqbi !))) ") _v &$ 3.4.4 transparent mode of hfc-s pci you can switch off hdlc operation for each b-channel independently. there is one bit for each b- channel in the ctmt control register. if this bit is set data in the fifo is sent directly to the s/t or gci/iom2 bus interface and data from the s/t or gci/iom2 bus interface is sent directly to the fifo. be sure to switch into transparent mode only if f1=f2. being in transparent mode the fx counters remain unchanged. z1 and z2 are the input and output pointers respectively. because f1=f2 both z-counters are always accessable and have valid data. if a send fifo channel changes to fifo empty condition no crc is generated and the last data byte written into the fifo is repeated until there is new data. in receive channels there is no check on flags or correct crcs and no status byte is added. the byte bounderies are not arbitrary like in hdlc mode where byte synchronisation is achieved with hdlc-flags. the data is just the same as it comes from the s/t or gci/iom2 bus interface or is sent to this. send and receive transparent data can be handled in two ways. the usual way is transmitting b-channel data with the lsb first as it is usual in hdlc mode. the second way is sending the bytes in reverse bit order as it is usual for pwm data. so the first bit is the msb. the bit order can be reversed by setting the corresponding bits in the cirm register.
863c @39 # _v &$ 6urbeqbi !))) 4 register bit description 4.1 register bit description of s/t section name addr. bits r/w function states c0h 3..0 r w binary value of actual state (nt: gx, te: fx) prepare for new state xxxx 4 w '1' loads the prepared state (bit 3..0) and stops the state machine.this bit needs to be set for a minimum period of 5.21 p s and must be cleared by software. (reset default) '0' enables the state machine. after writing an invalid state the state machine goes to deactivated state (g1, f2) 5 w '0' prepare deactivation '1' prepare activation 6 w '1' start activation/deactivation as selected by bit 5 this bit is automatically cleared after activation/deactivation. 7 w '0' no operation '1' in nt mode allows transition from g2 to g3. this bit is automatically cleared after the transition. * important! the state machine is stuck to '0' after a reset. writing a '0' to bit 4 of the states register restarts the state machine. in this state the hfc-s pci sends no signal on the s/t-line and it is not possible to activate it by incoming infox. nt mode: the nt state machine does not change automatically from g2 to g3 if the te side sends info3 frames. this transition must be activated each time by bit 7 of the states register.
863c @39 6urbeqbi !))) #! _v &$ name addr. bits r/w function sctrl c4h b-channel enable 0 w '0' b1 send data disabled (permanent 1 sent in activated states, reset default) '1' b1 data enabled 1 w '0' b2 send data disabled (permanent 1 sent in activated states, reset default) '1' b2 data enabled 2 w s/t interface mode '0' te mode (reset default) '1' nt mode 3 w d-channel priority '0' high priority 8/9 (reset default) '1' low priority 10/11 4 w s/q bit transmission '0' s/q bit disable (reset default) '1' s/q bit and multiframe enable 5 w '0' normal operation (reset default) '1' send 96khz transmit test signal (alternating zeros) 6 w tx_lo line setup this bit must be configured depending on the used s/t module and circuitry to match the 400 w pulse mask test. '0' capacitive line mode (reset default) '1' non capacitive line mode 7 w power down '0' power up, oscillator active (reset default) '1' power down, oscillator stopped sctrl_e c8h 0 w power down mode bit '0' s/t awake disable (reset default) power up can only be programmed by register access (sctrl bit 7). '1' s/t awake enable. oscillator starts on every non info0 s/t signal. 1 w must be '0' 2 w d reset '0' normal operation (reset default) '1' d bits are forced to '1' 3 w d_u enable '0' normal operation (reset default) '1' d channel is always send enabled regardless of e receive bit 6..4 w must be '0' 7 w '0' normal operation (reset default) '1' b1/b2 are exchanged in the s/t interface
863c @39 #" _v &$ 6urbeqbi !))) name addr. bits r/w function sctrl_r cch 0 1 w w b1-channel receive enable b2-channel receive enable '0' b-receive bits are forced to '1' '1' normal operation 7..2 w unused sq_rec d0h 3..0 r te mode: s bits (bit 3 = s1, bit 2 = s2, bit 1 = s3, bit 0 = s4) nt mode: q bits (bit 3 = q1, bit 2 = q2, bit 1 = q3, bit 0 = q4) 4 r '1' a complete s or q multiframe has been received reading sq_rec clears this bit. 6..5 r not defined 7 r '1' ready to send a new s or q multiframe writing to sq_send clears this bit. sq_send d0h 3..0 w te mode: q bits (bit 3 = q1, bit 2 = q2, bit 1 = q3, bit 0 = q4) nt mode: s bits (bit 3 = s1, bit 2 = s2, bit 1 = s3, bit 0 = s4) 7..4 w not defined clkdel dch 3..0 w te: 4 bit delay value to adjust the 2 bit delay time between receive and transmit direction. the delay of the external s/t-interface circuit can be compensated. the lower the value the smaller the delay between receive and transmit direction (see also figure 14) nt: data sample point. the lower the value the earlier the input data is sampled. the steps are 163ns. 6..4 w nt mode only early edge input data shaping low pass characteristic of extended bus configurations can be compensated. the lower the value the earlier input data pulse is sampled. no compensation means a value of 6 (110b). step size is the same as for bits 3-0. 7 w unused * note! the register is not initialized with a '0' after reset. the register should be initialized as follows before activating the te/nt state machine: te mode: 0dh .. 0fh nt mode: 6ch
863c @39 6urbeqbi !))) ## _v &$ 4.2 register bit description of gci/iom2 bus section timeslots for transmit direction name addr. bits r/w function b1_ssl 80h 4..0 w select gci/iom2 bus transmission slot (0..31) b2_ssl 84h 5 w unused aux1_ssl aux2_ssl 88h 8ch 6 w select gci/iom2 bus data lines '0' stio1 output '1' stio2 output 7 w transmit channel enable for gci/iom2 bus '0' disable (reset default) '1' enable * important! enabling more than one channel on the same slot causes undefined output data. timeslots for receive direction name addr. bits r/w function b1_rsl 90h 4..0 w select gci/iom2 bus receive slot (0..31) b2_rsl 94h 5 w unused aux1_rsl aux2_rsl 98h 9ch 6 w select gci/iom2 bus data lines '0' stio2 is input '1' stio1 is input 7 w receive channel enable for gci/iom2 bus '0' disable (reset default) '1' enable data registers name addr. bits r/w function b1_d b2_d aux1_d aux2_d a0h a4h a8h ach 0..7 r/w read/write data registers for selected timeslot data * note! if the data registers aux1_d and aux2_d are not overwritten, the transmisson slots aux1_ssl and aux2_ssl mirror the data received in aux1_rsl and aux2_rsl slots. this is useful for an internal connection between two codecs. this mirroring is disabled by setting bit 1 in mst_emod register
863c @39 #$ _v &$ 6urbeqbi !))) name addr. bits r/w function mst_mode b8h 0 w gci/iom2 bus mode '0' slave (reset default) (c4io and f0io are inputs) '1' master (c4io and f0io are outputs) 1 w polarity of c4- and c2o-clock '0' f0io is sampled on negative clock transition '1' f0io is sampled on positive clock transition 2 w polarity of f0-signal '0' f0 positive pulse '1' f0 negative pulse 3 w duration of f0-signal '0' f0 active for one c4-clock (244ns) (reset default) '1' f0 active for two c4-clocks (488ns) 5, 4 w time slot for codec-a signal f1_a '00' b1 receive slot '01' b2 receive slot '10' aux1 receive slot '11' signal c2o ? pin f1_a (c2o is 2048 khz clock) 7, 6 w time slot for codec-b signal f1_b '00' b1 receive slot '01' b2 receive slot '10' aux1 receive slot '11' aux2 receive slot the pulse shape and polarity of the codec signals f1_a and f1_b is the same as the pulseshape of the f0io signal. the polatity of c2o can be changed by bit 1. reset sets register mst_mode to all '0's.
863c @39 6urbeqbi !))) #% _v &$ name addr. bits r/w function mst_emod b4h 0 w slow down c4io clock adjustment (see figure 17) '0' c4io clock is adjusted in the 31th time slot twice for one half clock cycle (reset default) '1' c4io clock is adjusted in the 31th time slot once for one half clock cycle 1 w enable/disable aux channel mirroring '0' normal opration (reset default) '1' disable aux channel data mirroring 2 w unused 5..3 w select d-channel data flow (see also: connect register) destination source bit 3: '0' d-hfc ? d-s/t '1' d-hfc ? d-gci/iom2 bit 4: '0' d-s/t ? d-hfc '1' d-s/t ? d-gci/iom2 bit 5: '0' d-gci/iom2 ? d-hfc '1' d-gci/iom2 ? d-s/t 6 w unused 7 w enable gci/iom2 write slots '0' disable gci/iom2 write slots; slot #2 and slot #3 may be used for normal data '1' enables slot #2 and slot #3 as master, d- and c/i-channel c/i 08h 3..0 r/w on read: indication on write: command 7..4 unused trxr 0ch 0 r '1' monitor receive ready (2 bytes received) this bit is reset after read of second monitor byte (mon2_d) 1 r '1' monitor transmitter ready writing on mon2_d starts transmisssion and resets this bit. 5..2 r reserved 6rstio2 in 7rstio1 in reset sets register mst_emod to all '0's.
863c @39 #& _v &$ 6urbeqbi !))) 4.3 register bit description of connect register name addr. bits r/w function connect bch 2..0 w select b1-channel data flow destination source bit 0: '0' b1-hfc ? b1-s/t '1' b1-hfc ? b1-gci/iom2 bit 1: '0' b1-s/t ? b1-hfc '1' b1-s/t ? b1-gci/iom2 bit 2: '0' b1-gci/iom2 ? b1-hfc '1' b1-gci/iom2 ? b1-s/t 5..3 w select b2-channel data flow destination source bit 3: '0' b2-hfc ? b2-s/t '1' b2-hfc ? b2-gci/iom2 bit 4: '0' b2-s/t ? b2-hfc '1' b2-s/t ? b2-gci/iom2 bit 5: '0' b2-gci/iom2 ? b2-hfc '1' b2-gci/iom2 ? b2-s/t 7..6 w unused reset sets connect register to all '0's. the following figure shows the different options for switching the b-channels with the connect register. figure 7: function of the connect register bits
863c @39 6urbeqbi !))) #' _v &$ 4.4 register bit description of auxiliary and cross data registers name addr. bits r/w function cirm 60h 2..0 w defines the length of the auxiliary port access: value cycle time (aux_wr or aux_rd low) 000b 1 pci-clock 001b 3 pci-clocks 010b 5 pci-clocks 011b 7 pci-clocks 100b 9 pci-clocks 101b 11 pci-clocks 110b 13 pci-clocks 111b 15 pci-clocks 3 w soft reset, similar as hardware reset; the registers cip, cirm and ctmt are not changed. the pci interface is not reset. the reset is active until the bit is cleared. '0' deactivate reset (reset default) '1' activate reset 5..4 w must be '0' 6 w select bit order for b1 channel '0' normal read/write data operation '1' reverse bit order read/write data operation 7 w select bit order for b2 channel '0' normal read/write data operation '1' reverse bit order read/write data operation fifo_en 44h 5..0 w fifo enable/disable ('1' = enable (reset default)) bit fifo 0 b1-transmit 1 b1-receive 2 b2-transmit 3 b2-receive 4 d-transmit 5 d-receive the enable/disable change becomes valid between 0 and 250s after the bit has been written. all pci bus accesses and fifo activities are disabled for the selected fifos. to avoid unnecessary pci transfers all unused fifos should be disabled. at least one fifo (usually d-receive) must be enabled. 7..6 w unused, should be '0'
863c @39 #( _v &$ 6urbeqbi !))) name addr. bits r/w function ctmt 64h 0 w hdlc/transparent mode for b1-channel '0' hdlc mode (reset default) '1' transparent mode 1 w hdlc/transparent mode for b2-channel '0' hdlc mode (reset default) '1' transparent mode 4..2 w select timer (bit 4 = msb) timer '000' off '001' 3.125ms '010' 6.25ms '011' 12.5ms '100' 25ms '101' 50ms '110' 400ms '111' 800ms 5 w timer reset mode '0' reset timer by ctmt bit 7 (reset default) '1' automatically reset timer at each access to hfc-s pci 6 w ignored 7 w reset timer '1' reset timer this bit is automatically cleared. chip_id 58h 0 r power supply '0' 5v pci signaling environment '1' 3.3v pci signaling environment 3..1 r reserved 7..4 r chip identification 0011b hfc-s pci b_mode 4ch 1..0 w unused 2 w in 64 kbit/s mode: bit is ignored in 56 kbit/s mode: value of the lsb in 7-bit mode 3 w unused 4 w 56 kbit/s mode selection bit for b1-channel '0' 64 kbit/s mode (reset default) '1' 56 kbit/s mode 5 w 56 kbit/s mode selection bit for b2-channel '0' 64 kbit/s mode (reset default) '1' 56 kbit/s mode 6 w '0' data not inverted for b1-channel (reset default) '1' data inverted for b1-channel 7 w '0' data not inverted for b2-channel (reset default) '1' data inverted for b2-channel
863c @39 6urbeqbi !))) #) _v &$ name addr. bits r/w function int_m1 68h 0 w interrupt mask for channel b1 in transmit direction 1 w interrupt mask for channel b2 in transmit direction 2 w interrupt mask for channel d in transmit direction 3 w interrupt mask for channel b1 in receive direction 4 w interrupt mask for channel b2 in receive direction 5 w interrupt mask for channel d in receive direction 6 w interrupt mask for state change of te/nt state machine 7 w interrupt mask for timer for mask bits a '1' enables and a '0' disables interrupt. reset clears all bits to '0'. name addr. bits r/w function int_m2 6ch 0 w interrupt mask for processing/non processing phase transition 1 w interrupt mask for gci i-change 2 w interrupt mask for gci monitor receive 3 w enable for interrupt output ('1' = enable) 6..4 w unused 7 w pmesel '0' pme triggered on d-channel receive int '1' pme triggered on s/t interface state change for mask bits a '1' enables and a '0' disables interrupt. reset clears all bits to '0'. name addr. bits r/w function trm 48h 1..0 w interrupt in transparent mode is generated if z1 in receive fifos or z2 in transmit fifos change from: 00: x xxxx x011 1111 ? x xxxx x100 0000 01: x xxxx 0111 1111 ? x xxxx 1000 0000 10: x xxx0 1111 1111 ? x xxx1 0000 0000 11: x 0111 1111 1111 ? x 1000 0000 0000 4..2 w must be '0' 5w e ? b2 receive channel when set the e receive channel of the s/t interface is connected to the b2 receive channel. 6 w b1+b2 mode '0' normal operation (reset default) '1' b1+b2 are combined to one hdlc or transparent channel. all settings for data shape and connect are derived from b1. 7 w iom test loop when set mst output data is looped to the mst input.
863c @39 $ _v &$ 6urbeqbi !))) name addr. bits r/w function int_s1 78h 0 1 r r b1-channel interrupt status in transmit direction b2-channel interrupt status in transmit direction in hdlc mode: '1' a complete frame has been transmitted, the frame counter f2 has been incremented in transparent mode: '1' interrupt as selected in trm register bits 1..0 2 r d-channel interrupt status in transmit direction '1' a complete frame was transmitted, the frame counter f2 was incremented 3 4 r r b1-channel interrupt status in receive direction b2-channel interrupt status in receive direction in hdlc mode: '1' a complete frame has been transmitted, the frame counter f1 has been incremented in transparent mode: '1' interrupt as selected in trm register bits 1..0 5 r d-channel interrupt status in receive direction '1' a complete frame was received, the frame counter f1 was incremented 6 r te/nt state machine interrupt status '1' state of state machine changed 7 r timer interrupt status '1' timer is elapsed int_s2 7ch 0 r processing/non processing transition interrupt status '1' the hfc-s pci has changed from processing to non processing state. 1 r gci i-change interrupt '1' a different i-value on gci was detected 2 r receiver ready (rxr) of monitor channel '1' 2 monitor bytes have been received 6..3 r unused, '0' 7 r '1' fatal error: synchronisation lost. pci performance too low for hfc-s pci. only soft reset recovers from this situation. * important! reading the int_s1 or int_s2 register resets all active read interrupts in the int_s1 or int_s2 register. new interrupts may occur during read. these interrupts are reported at the next read of int_s1 or int_s2. all interrupt bits are reported regardless of the mask registers settings (int_m1 and int_m2). the mask register settings only influence the interrupt output condition. the interrupt output goes inactive during the read of int_s1 or int_s2. if interrupts occur during this read the interrupt line goes active immediately after the read is finished. so processors with level or transition triggered interrupt inputs can be connected.
863c @39 6urbeqbi !))) $! _v &$ name addr. bits r/w function status 70h 0 r always '0' 1 r processing/non processing status '1' the hfc-s pci is in processing phase (every 125s) '0' the hfc-s pci is not in processing phase 2 r processing/non processing transition interrupt status '1' the hfc-s pci has finished internal processing phase (every 125s) 3ralways '0' 4 r timer status '0' timer not elapsed '1' timer elapsed 5 r te/nt state machine interrupt state '1' state of state machine has changed 6 r frame interrupt has occured (any data channel interrupt) all masked d-channel and b-channel interrupts are "ored" 7 r any interrupt all masked interrupts are "ored" reading the status register clears no bit.
863c @39 $" _v &$ 6urbeqbi !))) 5 electrical characteristics absolute maximum ratings parameter symbol rating supply voltage v dd -0.3v to +7.0v input voltage v i -0.3v to v dd + 0.3v output voltage v o -0.3v to v dd + 0.3v operating temperature t opr -10c to +85c storage temperature t stg -40c to +125c recommended operating conditions parameter symbol condition min. typ. max. supply voltage v dd v dd =5v v dd =3.3v 4.75v 3.15v 5.0v 3.3v 5.25v 3.45v operating temperature t opr 0c +70c electrical characteristics for 5v power supply v dd = 4.75v to 5.25v, t opr = 0c to +70c parameter symbol condition ttl level cmos level min. typ. max. min. typ. max. input low voltage v il 0.8v 1.0v input high voltage v ih 2.0v 3.5v output low voltage v ol 0.4v 0.4v output high voltage v oh 4.3v 4.3v output leakage current | i oz | high z 10a 10a pull-up resistor input current | i il |v i = v ss 50a 50a electrical characteristics for 3.3v power supply v dd = 3.15v to 3.45v, t opr = 0c to +70c parameter symbol condition ttl level cmos level min. typ. max. min. typ. max. input low voltage v il 0.8v 1.0v input high voltage v ih 2.0v 2.3v output low voltage v ol 0.4v 0.4v output high voltage v oh 2.4v 2.4v
863c @39 6urbeqbi !))) $# _v &$ dc current consumption of hfc-s pci 25c ambient temperature, 5 v operating voltage, 33 mhz pci clock condition min. typ. max. pci master, pcm master (full operational) 24,5 ma power down, no s/t awake (12.288 mhz osc off) 15 ma all pins gnd (except power supply) 1 ma
863c @39 $$ _v &$ 6urbeqbi !))) i/o characteristics input interface level ad0-31 pci par pci c/be0-3 pci rst# pci frame# pci irdy# pci trdy# pci stop# pci idsel pci devsel# pci gnt# pci perr# pci daux0-7 ttl c4io ttl, internal pull-up resistor f0io ttl, internal pull-up resistor stio1-2 ttl, internal pull-up resistor ee_sda ttl, internal pull-up resistor ee_scl/en ttl, internal pull-up resistor
863c @39 6urbeqbi !))) $% _v &$ driver capability low high output 0.4v 0.6v v dd - 0.4v ad0-31 *) 6ma 3ma par *) 6ma 3ma c/be0-3 *) 6ma 3ma frame# *) 6ma 3ma irdy# *) 6ma 3ma trdy# *) 6ma 3ma stop# *) 6ma 3ma devsel# *) 6ma 3ma req# *) 6ma 3ma perr# *) 6ma 3ma serr# *) 6ma 3ma pme 2ma 1ma inta# *) 6ma 3ma daux0-7 4ma 2ma /aux_wr 2ma 1ma /aux_rd 2ma 1ma /adr_wr 8ma 4ma tx2_hi 6ma 3ma /tx1_lo 6ma 3ma /tx_en 4ma 2ma /tx2_lo 6ma 3ma tx1_hi 6ma 3ma adj_lev 1ma 0.5ma c4io 8ma 4ma f0io 8ma 4ma stio1-2 8ma 4ma f1_a-b 6ma 3ma ee_sda 1ma 0.5ma ee_scl/en 1ma 0.5ma *) pci buffer is pci spec. 2.1 compliant.
863c @39 $& _v &$ 6urbeqbi !))) 6 timing characteristics 6.1 pci bus timing the timing characteristics of the hfc-s pcis integrated pci bus interface is compliant with version 2.1 of the pci local bus specification. 6.2 gci/iom2 bus clock and data alignment for mitel st tm bus figure 8: gci/iom2 bus clock and data alignment
863c @39 6urbeqbi !))) $' _v &$ 6.3 gci/iom2 timing *) f0io starts one c4io clock earlier if bit 3 in mst_mode register is set. if this bit is set f0io is also awaited one c4io clock cycle earlier. symbol characteristics min. max t c4p clock c4io period (4.096 mhz) 243.9 ns 244.4 ns t c4h clock c4io high width 110 ns 134 ns t c4l clock c4io low width 110 ns 134 ns t c2p clock c2o period 487.8 ns 488.8 ns t c2h clock c2o high width 220 ns 268 ns t f0is f0io setup time 50 ns 150 ns t f0ih f0io hold time 50 ns 150 ns t f0iw f0io width 200 ns 300 ns t stod stio1 delay level 1 output 20 ns 125 ns timing diagram 1: gci/iom2 timing
863c @39 $( _v &$ 6urbeqbi !))) symbol characteristics min. max t stod stio1 delay level 2 output 20 ns 125 ns t stis stio2 set up time 30 ns t stih stio2 hold time 2 ns 30ns all specifications are for 2.048 mb/s streams and f clk = 12.288 mhz. 6.4 eeprom access symbol characteristics typ. f scl serial clock frequency 32.2 khz *) t scl serial clock period 1 / f scl t hd:sta start condition hold time ? t scl t low clock low period ? t scl t high clock high period ? t scl t su:sta start condition setup time ? t scl t hd:dat output data change after clock 10 ns t su data in setup time 100 ns t dh data in hold time 100 ns *) with 33 mhz pci clock timing diagram 2: eeprom access
863c @39 6urbeqbi !))) $) _v &$ 7 s/t interface circuitry in order to comply to the physical requirements of itu-t recommendation i.430 and considering the national requirements concerning overvoltage protection and electromagnetic compatibility (emc), the hfc-s pci needs some additional circuitry, which are shown in the following figures. 7.1 external receiver circuitry part list vdd 5v 3.3v r1, r1' 33 k : r2, r2' 100 k : r3 1 m : 680k : r4 3.9 k : r5, r5' 4.7 k : r6, r6' 4.7 k : r7 1.8 m : 1.2m : c1 47 nf c3, c3' 22pf d1, d2 1n4148 or ll4148 d3, d4 1n4148 or ll4148 s/t module see table 3 on page 52. c3, c3' are for reduction of high frequency input noise and should be located as close as possible to the hfc-s pci. r5 adj_lev r4 r2 r2 lev_r2 c3 gnd c1 r7 r1 r1 lev_r1 r2 r1 c3 r5 gnd r3 vdd r6 d3 d4 12 14 rx - vdd d1 d2 r6 10 11 s/t module 5 s/t side 16 rx + figure 9: external receiver circuitry
863c @39 % _v &$ 6urbeqbi !))) 7.2 external transmitter circuitry part list vdd 5v 3.3v r1 2.2 k : ? 1% 560 : ? 1% r2 3.0 k : ? 1% 3.9 k : ? 1% r3, r3' *) 18 : 18 : r4 100 : 0 : r5 5.6 k : 3.3 k : r6 3.3 k : 2.2 k : r7 3.3 k : 1.8 k : r8 2.2 k : 2.2 k : c3 470 pf d2, d3 1n4148 or ll4148 d4, d5 1n4148 or ll4148 zd1 z-diode 2.7 v (e. g. bzv 55c 2v7) t1, t1' bc550c, bc850c or similar t2, t2' bc550c, bc850c or similar t3 bc560c, bc860c or similar s/t module see table 3 on page 52. *) value is depending on the used s/t module r2 tx2_lo t2 gnd d2 d4 r3 r8 r3 t2 t1 r1 tx1_hi r7 t1 t3 r4 c3 r6 r2 s/t module d5 d3 zd1 7 8 9 tx1_lo gnd tx - s/t side tx + 18 3 1 tx2_hi r1 tx_en r5 vdd figure 10: external transmitter circuitry
863c @39 6urbeqbi !))) %! _v &$ s/t module part number manufacturer apc 56624 apc 42624 apc 5568ds (includes receiver and transmitter circuitry) advanced power components united kingdom phone: +44 1634-290588 fax: +44 1634-290591 http://www.apcisdn.com fe 8131-55z fee gmbh singapore phone: +65 741-5277 fax: +65 741-3013 bangkok phone: +662 718-0726-30 fax: +662 718-0712 germany phone: +49 6106-82980 fax: +49 6106-829898 transformers: pe-64995 pe-64999 pe-65795 pe-65799 pe-68995 pe-68999 t5006 t5007 s 0 -modules: t5012 t5034 t5038 pulse engineering, inc. united states phone: +1-619-674-8100 fax: +1-619-674-8262 http://www.pulseeng.com t 6040... transformers: 3-l4021-x066 3-l4025-x095 3-l5024-x028 3-l4096-x005 3-l5032-x040 s 0 -modules: 7-l5051-x014 7-m5051-x032 7-l5052-x102 7-m5052-x110 7-m5052-x114 vac gmbh germany phone: +49 6181/ 38-0 fax: +49 6181/ 38-2645 http://www.vacuumschmelze.de transformers: st5069 s 0 -modules: pt5135 st5201 st5202 valor electronics, inc. asia phone: +852 2333-0127 fax: +852 2363-6206 north america phone: +1 800 31valor fax: +1 619 537-2525 europe phone: +44 1727-824-875 fax: +44 1727-824-898 http://www.valorinc.com
863c @39 %" _v &$ 6urbeqbi !))) s/t module part number manufacturer 543 76 009 00 vogt electronic ag germany phone: +49 8591/ 17-0 fax: +49 8591/ 17-240 http://www.vogt-electronic.com transformers ut21023 s 0 -modules: ut 21624 ut 28624 umec gmbh germany phone: +49 7131-7617-0 fax: +49 7131-7617-20 taiwan phone: +886-4-3590096 fax: +886-4-3590129 united states phone: +1-310-326-7072 fax: +1-310-326-7058 http://www.umec.de table 3: s/t module part numbers and manufacturer
863c @39 6urbeqbi !))) %# _v &$ 7.3 oscillator circuitry part list: q1 12.288 mhz quartz r1 0..50 : r2 1 m : c1, c2 47 pf the values of c1, c2 and r1 depend on the used quartz. for a load-free check of the oscillator frequency the c4o clock of the gci/iom2 bus should be measured (hfc-s pci as master, s/t interface deactivated, 4.096 mhz frequency intented on the c4io). 7.4 eeprom circuitry osc_out c2 r1 osc_in c1 q1 r2 figure 11: oscillator circuitry figure 12: eeprom circuitry
863c @39 %$ _v &$ 6urbeqbi !))) 7.5 pme pin circuitry the pme pin (pin 53) on the hfc-s pci is high active. to connect it to the low active pme# pin on the pci bus, the following circuitry is neccessary. figure 13: pme pin circuitry
863c @39 6urbeqbi !))) %% _v &$ 8 state matrices for nt and te 8.1 s/t interface activation/deactivation layer 1 for finite state matrix for nt ? no state change / impossible by the definition of peer-to-peer physical layer procedures or system internal reasons | impossible by the definition of the physical layer service note 1: timer 1 (t1) is not implemented in the hfc-s pci and must be implemented in software. note 2: timer 2 (t2) prevents unintentional reactivation. its value is 32ms (256 x 125s). this implies that a te has to recognize info 0 and to react on it within this time. note 3: after reset the state machine is fixed to g0. state name reset deactive pending activation active pending deactivation state number g0 g1 g2 g3 g4 event info 0 info 0 info 2 info 4 info 0 state machine release (note 3) g2|||| activate request g2 (note 1) g2 (note 1) || g2 (note 1) deactivate request ? | start timer t2 g4 start timer t2 g4 | expiry t2 (note 2) ???? g1 receiving info 0 ??? g2 g1 receiving info 1 ? g2 (note 1) ? / ? receiving info 3 ? / g3 (note 1) ?? lost framing ? //g2 ? info sent table 4: activation/deactivation layer 1 for finite state matrix for nt
863c @39 %& _v &$ 6urbeqbi !))) 8.2 activation/deactivation layer 1 for finite state matrix for te ? no change, no action | impossible by the definition of the layer 1 service / impossible situation notes note 1: after reset the state machine is fixed to f0. note 2: this event reflects the case where a signal is received and the te has not (yet) determined wether it is info 2 or info 4. note 3: bit- and frame-synchronisation achieved. note 4: loss of bit- or frame-synchronisation. note 5: timer 3 (t3) is not implemented in the hfc-s pci and must be implemented in software. state name reset sensing deactivated awaiting signal identifying input synchronized activated lost framing state number f0 f2 f3 f4 f5 f6 f7 f8 event info 0 info 0 info 0 info 1 info 0 info 3 info 3 info 0 state machine release (note 1) f2 / / / / / / / activate ? |f5 | | ? | ? request ? |f4 | | ? | ? expiry t3 (note 5) ? / ? f3 f3 f3 ?? receiving info 0 ? f3 ??? f3 f3 f3 receiving any signal (note 2) ?? ? f5 ? // ? receiving info 2 (note 3) ? f6 f6 f6 f6 ? f6 f6 receiving info 4 (note 3) ? f7 f7 f7 f7 f7 ? f7 lost framing (note 4) ? / / / / f8 f8 ? info sent receiving any signal receiving info 0 table 5: activation/deactivation layer 1 for finite state matrix for te
863c @39 6urbeqbi !))) %' _v &$ 9 binary organisation of the frames 9.1 s/t frame structure the frame structures are different for each direction of transmission. both structures are illustrated in figure 14. f framing bit n bit set to a binary value n = f a (nt to te) l d.c. balancing bit b1 bit within b-channel 1 d d-channel bit b2 bit within b-channel 2 e d-echo-channel bit a bit used for activation f a auxiliary framing bit s s-channel bit m multiframing bit * note! lines demarcate those parts of the frame that are independently d.c.-balanced. the f a bit in the direction te to nt is used as q bit in every fifth frame if s/q bit transmission is enabled (see sctrl register). the nominal 2-bit offset is as seen from the te. the offset can be adjusted with the clkdel register in te mode. the corresponding offset at the nt may be greater due to delay in the interface cable and varies by configuration. hdlc-b-channel data start with the lsb, pcm-b-channel data start with the msb. figure 14: frame structure at reference point s and t
863c @39 %( _v &$ 6urbeqbi !))) 9.2 gci frame structure the binary organistation of a single gci channel frame is described below. b1 b-channel 1 data b2 b-channel 2 data m monitor channel data d d-channel data c/i command/indication bits for controlling activation/deactivation and for additional control functions mr handshake bit for monitor channel mx handshake bit for monitor channel figure 15: single channel gci format
863c @39 6urbeqbi !))) %) _v &$ 10 clock synchronisation 10.1 clock synchronisation in nt-mode figure 16: clock synchronisation in nt-mode
863c @39 & _v &$ 6urbeqbi !))) 10.2 clock synchronisation in te-mode the c4io clock is adjusted in the 31th time slot at the gci/iom bus twice for one half clock cycle. this can be reduced to one adjustment of a half clock cycle. this is useful if another hfc-s, hfc-s+, hfc- sp or hfc-s pci is connected as slave in nt mode to the gci/iom2 bus. figure 17: clock synchronisation in te-mode
863c @39 6urbeqbi !))) &! _v &$ 11 hfc-s pci package dimensions figure 18: hfc-s pci package dimensions
863c @39 &" _v &$ 6urbeqbi !))) 12 isdn pci card sample circuitry with hfc-s pci the 8-bit-flip-flop (u3) is only needed for auxiliary port accesses. the eeprom (u2) is also optional.
863c @39 6urbeqbi !))) &# _v &$
863c @39 &$ _v &$ 6urbeqbi !))) part list part value c1 47p c2 47p c3 22p c4 22p c7 47n c8 470p cb1 33n cb2 33n cb3 33n cb5 33n cb6 33n cb7 33u 10v, bf c cb8 33u 10v, bf c cb9 33n con1 pci32pme con5 western d1 bav99 d2 bav99 d5 z-diode 2v7 d10 bav99 part value d11 bav99 jp1 iom jp2 pinhd-2x13 q1 12.288 mhz q2 bc850c q3 bc850c q4 bc850c q5 bc850c q6 bc860c q7 bc850c r1 (330r) r2 (1m) r3 3k9 r4 1m r5 4k7 r5' 4k7 r6 4k7 r6' 4k7 r7 100k r7' 100k r8 33k r8' 33k r9 1m8 part value r10 100r r11 3k3 r12 5k6 r13 2k2 1% r13' 2k2 1% r14 3k3 r15 3k 1% r15' 3k 1% r16 18r r16' 18r r17 3k3 r18 10k r19 10k r20 none r21 none r22 10k r23 none r24 none tr1 sotr u1 hfc-s pci u2 24c04 u3 74374 (optional)

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