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www.fairchildsemi.com rev. 1.07 12/8/04 features 10-bit resolution 150 megapixels per second 0.1% linearity error sync and blank controls 1.0v p-p video into 37.5 ? or 75 ? load internal bandgap voltage reference double-buffered data for low distortion ttl-compatible inputs ? ow glitch energy single +5 volt power supply applications ? ideo signal conversion ? rgb ? yc b c r ? composite, y, c multimedia systems image processing ? rue-color graphics systems (1 billion colors) broadcast television equipment high-de?ition television (hdtv) equipment direct digital synthesis description fms3110/3115 products are low-cost triple d/a converters that are tailored to ? graphics and video applications where speed is critical. two speed grades are available: ttl-level inputs are converted to analog current outputs that can drive 25?7.5 ? loads corresponding to doubly-terminated 50?5 ? loads. a sync current following sync input timing is added to the i og output. blank will override rgb inputs, setting i og , i ob and i or currents to zero when blank = l. although appropriate for many applications the internal 1.235v reference voltage can be overridden by the v ref input. few external components are required, just the current reference resistor, current output load resistors, and decoupling capacitors. p ackage is a 48-lead lqfp. fabrication technology is cmos. performance is guaranteed from 0 to 70?. fms3110 100 ms/s FMS3115 150 ms/s block diagram 10 bit d/a converter sync 10 sync clock g 9-0 comp +1.235v ref io g blank 10 bit d/a converter 10 b 9-0 io b 10 bit d/a converter 10 r 9-0 io r r ref v ref fms3110/3115 triple video d/a converters 3 x 10 bit, 150 ms/s
fms3110/3115 data sheet 2 rev. 1.07 12/8/04 functional description w ithin the fms3110/3115 are three identical 10-bit d/a converters, each with a current source output. external loads are required to convert the current to voltage outputs. data inputs rgb 7-0 are overridden by the blank input. sync = h activates, sync current from i os for sync-on-green video signals. digital inputs all digital inputs are ttl-compatible. data is registered on the rising edge of the clk signal. following one stage of pipeline delay, the analog output changes t do after the rising edge of clk. sync and blank sync and blank inputs control the output level (figure 1 and table 1) of the d/a converters during crt retrace intervals. blank forces the d/a outputs to the blanking level while sync = l turns off a current source that is connected to the green d/a converter. sync = h adds a 40 ire sync pulse to the green output, sync = l sets the green output to 0.0 volts during the sync tip. sync and blank are registered on the rising edge of clk. blank gates the d/a inputs and sets the pedestal voltage. if blank = high, the d/a inputs are added to a pedestal which offsets the current output. if blank = low, data inputs and the pedestal are disabled. figure 1. nominal output levels d/a outputs each d/a output is a current source. to obtain a voltage output, a resistor must be connected to ground. output v oltage depends upon this external resistor, the reference v oltage, and the value of the gain-setting resistor connected between r ref and gnd. normally, a source termination resistor of 75 ohms is connected between the d/a current output pin and gnd near the d/a converter. a 75 ohm line may then be connected with another 75 ohm termination resistor at the f ar end of the cable. this ?ouble termination?presents the d/a converter with a net resistive load of 37.5 ohms. the fms3110/3115 may also be operated with a single 75 ohm terminating resistor. to lower the output voltage swing to the desired range, the nominal value of the resistor on r ref should be doubled. v oltage reference all three d/a converters are supplied with a common v oltage reference. internal bandgap voltage reference voltage is +1.235 volts with a 3k ? source resistance. an external v oltage reference may be connected to the v ref pin, ov erriding the internal voltage reference. a 0.1? capacitor must be connected between the comp pin and v dd to stabilize internal bias circuitry and ensure low-noise operation. po wer and ground required power is a single +5.0 volt supply. to minimize power supply induced noise, analog +5v should be connected to v dd pins with 0.1 and 0.01 ? decoupling capacitors placed adjacent to each v dd pin or pin pair. the high slew-rate of digital data makes capacitive coupling to the outputs of any d/a converter a potential problem. since the digital signals contain high-frequency components of the clk signal, as well as the video output signal, the resulting data feedthrough often looks like harmonic distortion or reduced signal-to-noise performance. all ground pins should be connected to a common solid ground plane for best performance. data: 660 mv max. pedestal: 54 mv sync: 286 mv
data sheet fms3110/3115 rev. 1.07 12/8/04 3 ta b le 1. output voltage versus input code, sync and blank v ref = 1.235 v, r ref = 590 ? , r l = 37.5 ? pin assignments rgb 9-0 (msb?sb) blue and red d/as green d/a sync blank v out sync blank v out 11 1111 1111 x 1 0.7140 1 1 1.0000 11 1111 1111 x 1 0.7140 0 1 0.7140 11 1111 1110 x 1 0.7134 1 1 0.9994 11 1111 1101 x 1 0.7127 1 1 0.9987 10 0000 0000 x 1 0.3843 1 1 0.6703 01 1111 1111 x 1 0.3837 1 1 0.6697 00 0000 0010 x 1 0.0553 1 1 0.3413 00 0000 0001 x 1 0.0546 1 1 0.3406 00 0000 0000 x 1 0.0540 1 1 0.3400 xx xxxx xxxx x 0 0.0000 1 0 0.2860 xx xxxx xxxx x 0 0.0000 0 0 0.0000 g 1 g 2 g 3 g 4 g 5 g 6 g 7 g 8 g 9 blank v dd r 2 r 1 nc r ref v ref comp io g io r ov dd v dd io b gnd gnd nc g 0 r 9 r 8 r 7 r 6 r 5 r 4 r 3 nc b 0 b 1 b 2 b 3 b 4 b 6 b 5 nc 1 2 3 4 5 6 7 8 9 10 sync 11 12 36 35 34 33 32 31 30 29 28 27 clock 26 25 13 14 15 16 17 18 19 20 21 22 b 7 b 8 b 9 23 24 48 47 46 45 44 43 42 41 40 39 r 0 38 37 lqfp fms3110/3115 g 1 g 2 g 3 g 4 g 5 g 6 g 7 g 8 g 9 blank v dd r 2 r 1 nc r ref v ref comp io g io r v dd v dd io b gnd gnd nc g 0 r 9 r 8 r 7 r 6 r 5 r 4 r 3 nc b 0 b 1 b 2 b 3 b 4 b 6 b 5 nc 1 2 3 4 5 6 7 8 9 10 sync 11 12 36 35 34 33 32 31 30 29 28 27 clock 26 25 13 14 15 16 17 18 19 20 21 22 b 7 b 8 b 9 23 24 48 47 46 45 44 43 42 41 40 39 r 0 38 37 lqfp fms3110/3115
fms3110/3115 data sheet 4 rev. 1.07 12/8/04 pin descriptions pin name pin number value description clock and pixel i/o clk 26 ttl clock input. the clock input is ttl-compatible and all pixel data is registered on the rising edge of clk. it is recommended that clk be driven by a dedicated ttl buffer to avoid reflection induced jitter, overshoot, and undershoot. r 9-0 47-37 ttl red pixel data inputs. ttl-compatible red data inputs are registered on the rising edge of clk. g 9-0 48, 9? ttl green pixel data inputs. ttl-compatible green data inputs are registered on the rising edge of clk. b 9-0 23?4 ttl blue pixel data inputs. ttl-compatible blue data inputs are registered on the rising edge of clk. controls sync 11 ttl sync pulse input. bringing sync low, turns off a 40 ire (7.62 ma) current source which forms a sync pulse on the green d/a converter output. sync is registered on the rising edge of clk with the same pipeline latency as blank and pixel data. sync does not override any other data and should be used only during the blanking interval. since this is a single-supply d/a and all signals are positive-going, sync is added to the bottom of the green d/a range. so turning sync off means turning the current source on. when a sync pulse is desired, the current source is turned off. if the system does not require sync pulses from the green d/a converter, sync should be connected to gnd. blank 10 ttl blanking input. when blank is low, pixel inputs are ignored and the d/a converter outputs fall to the blanking level. blank is registered on the rising edge of clk and has the same pipeline latency as sync . video outputs io r 33 0.714 v p-p red current output. the current source outputs of the d/a converters are capable of driving rs-343a/smpte-170m compatible levels into doubly-terminated 75 ohm lines. io g 32 1 v p-p green current output. the current source outputs of the d/a converters are capable of driving rs-343a/smpte-170m compatible levels into doubly-terminated 75 ohm lines. sync pulses may be added to the green d/a output. io b 29 0.714 v p-p blue current output. the current source outputs of the d/a converters are capable of driving rs-343a/smpte-170m compatible levels into doubly-terminated 75 ohm lines.
data sheet fms3110/3115 rev. 1.07 12/8/04 5 v oltage reference v ref 35 +1.235 v voltage reference output/input. an internal voltage source of +1.235 volts is output on this pin. an external +1.235 volt reference may be applied here which overrides the internal reference. decoupling v ref to gnd with a 0.1? ceramic capacitor is required. r ref 36 560 ? current-setting resistor. full-scale output current of each d/a converter is determined by the value of the resistor connected between r ref and gnd. nominal value of r ref is found from: r ref = 9.1 (v ref /i fs ) where i fs is the full-scale (white) output current (in amps) from the d/a converter (without sync). sync is 0.4 * i fs . d/a full-scale (white) current may also be calculated from: i fs = v fs /r l where v fs is the white voltage level and r l is the total resistive load (in ohms) on each d/a converter. v fs is the blank to full-scale voltage. comp 34 0.1 ? compensation capacitor. a 0.1 ? ceramic capacitor must be connected between comp and v dd to stabilize internal bias circuitry. po wer and ground v dd 12, 30, 31 +5 v power supply. gnd 27, 28 0.0v ground. pin descriptions (continued) pin name pin number value description equivalent circuits figure 2. equivalent digital input circuit figure 3. equivalent analog output circuit digital input v dd p n gnd v dd v dd np gnd out
fms3110/3115 data sheet 6 rev. 1.07 12/8/04 equivalent circuits (continued) figure 4. equivalent analog input circuit absolute maximum ratings (beyond which the device may be damaged) 1 notes: 1. functional operation under any of these conditions is not implied. performance and reliability are guaranteed only if operating conditions are not exceeded. 2. applied voltage must be current limited to specified range. 3. forcing voltage must be limited to specified range. 4. current is specified as conventional current flowing into the device. p arameter min typ max unit po wer supply voltage v dd (measured to gnd) -0.5 7.0 v inputs applied voltage (measured to gnd) 2 -0.5 v dd + 0.5 v forced current 3,4 -10.0 10.0 ma outputs applied voltage (measured to gnd) 2 -0.5 v dd + 0.5 v forced current 3,4 -60.0 60.0 ma short circuit duration (single output in high state to ground) in?ite second t emperature operating, ambient -20 110 ? junction 150 ? lead soldering (10 seconds) 300 ? vapor phase soldering (1 minute) 220 ? storage -65 150 ? p gnd 27012b r ref v ref v dd p
data sheet fms3110/3115 rev. 1.07 12/8/04 7 operating conditions electrical characteristics notes: 1. values shown in typ column are typical for v dd = +5v and t a = 25?. 2. minimum/maximum values with v dd = max and t a = min. 3. v ref = 1.235v, r load = 37.5 ? , r ref = 540 ? p arameter min nom max units v dd power supply voltage 4.75 5.0 5.25 v f s conversion rate fms3110 100 msps FMS3115 150 msps t pwh clk pulsewidth, high fms3110 3.1 ns FMS3115 2.5 ns t pwl clk pulsewidth, low fms3110 3.1 ns FMS3115 2.5 ns t w clk pulsewidth fms3110 10 ns FMS3115 6.6 ns t s input data setup time 1.7 ns t h input date hold time 0 ns v ref reference voltage, external 1.0 1.235 1.5 v c c compensation capacitor 0.1 ? r l output load 37.5 ? v ih input voltage, logic high 2.0 v dd v v il input voltage, logic low gnd 0.8 v t a ambient temperature, still air 0 70 c p arameter conditions 3 min typ 1 max units i dd power supply current 2 v dd = max 125 ma pd total power dissipation 2 v dd = max 655 mw r o output resistance 100 k ? c o output capacitance i out = 0ma 30 pf i ih input current, high v dd = max, v in = 2.4v -5 ? i il input current, low v dd = max, v in = 0.4v 5 a i ref v ref input bias current 0 ?00 ? v ref reference voltage output 1.235 v v oc output compliance referred to v dd -0.4 0 +1.5 v c di digital input capacitance 4 10 pf
fms3110/3115 data sheet 8 rev. 1.07 12/8/04 switching characteristics notes: 1. values shown in typ column are typical for v dd = +5v and t a = 25?. 2. v ref = 1.235v, r load = 37.5 ? , r ref = 590 ? . system performance characteristics notes: 1. values shown in typ column are typical for v dd = +5v and t a = 25?. 2. v ref = 1.235v, r load = 37.5 ? , r ref = 590 ? . timing diagram p arameter conditions 2 min typ 1 max units t d clock to output delay v dd = min 10 15 ns t skew output skew 1 2 ns t r output risetime 10% to 90% of full scale 3 ns t f output falltime 90% to 10% of full scale 3 ns p arameter conditions 2 min typ 1 max units e li integral linearity error v dd , v ref = nom ?.1 ?.25 %/fs e ld differential linearity error v dd , v ref = nom ?.1 ?.25 %/fs e dm dac to dac matching v dd , v ref = nom 3 10 % psr power supply rejection ratio 0.05 %/% clk pixel data & controls output datan datan+1 datan+2 t pwl t s t h 50% 3%/fs 90% 10% t d t set t f t r t pwh 1/f s
data sheet fms3110/3115 rev. 1.07 12/8/04 9 applications discussion figure 5 illustrates a typical fms3110/3115 interface cir- cuit. in this example, an optional 1.2 volt bandgap reference is connected to the v ref output, overriding the internal volt- age reference source. grounding it is important that the fms3110/3115 power supply is well- regulated and free of high-frequency noise. careful power supply decoupling will ensure the highest quality video sig- nals at the output of the circuit. the fms3110/3115 has sep- arate analog and digital circuits. to keep digital system noise from the d/a converter, it is recommended that power supply v oltages (v dd ) come from the system analog power source and all ground connections (gnd) be made to the analog ground plane. power supply pins should be individually decoupled at the pin. printed circuit board layout designing with high-performance mixed-signal circuits demands printed circuits with ground planes. overall system performance is strongly in?enced by the board layout. capacitive coupling from digital to analog circuits may result in poor d/a conversion. consider the following sug- gestions when doing the layout: 1. keep the critical analog traces (v ref , i ref , comp, io s , io r , io g ) as short as possible and as far as possi- ble from all digital signals. the fms3110/3115 should be located near the board edge, close to the analog out- put connectors. 2. power plane for the fms3110/3115 should be separate from that which supplies the digital circuitry. a single power plane should be used for all of the v dd pins. if the power supply for the fms3110/3115 is the same as that of the system's digital circuitry, power to the fms3110/3115 should be decoupled with 0.1? and 0.01? capacitors and iso- lated with a ferrite bead. 3. the ground plane should be solid, not cross-hatched. connections to the ground plane should have very short leads. 4. if the digital power supply has a dedicated power plane layer, it should not be placed under the fms3110/3115, the voltage reference, or the analog outputs. capacitive coupling of digital power supply noise from this layer to the fms3110/3115 and its related analog circuitry can have an adverse effect on performance. 5. clk should be handled carefully. jitter and noise on this clock will degrade performance. terminate the clock line carefully to eliminate overshoot and ringing. related products fms38xx triple 8-bit 150 msps d/a converters fms9884a 3 x 8-bit 140 ms/s a/d converter figure 5. typical interface circuit r 9-0 g 9-0 b 9-0 +5v 0.1 f 10 f vdd gnd fms31xx triple 10-bit d/a converter clk sync blank red pixel input green pixel input blue pixel input clock sync blank comp v ref r ref +5v 0.1 f 0.1 f 560 ? 3.3k ? (not required without external reference) lm185-1.2 (optional) io r io g io b 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? z o =75 ? red green w/sync blue z o =75 ? z o =75 ?
fms3110/3115 data sheet 10 rev. 1.07 12/8/04 mechanical dimensions 48-lead lqfp package d e1 e e pin 1 identifier b base plane seating plane see lead detail c 0.063" ref (1.60mm) l -c- ccc c lead coplanarity a2 a a1 a .055 .063 1.40 1.60 symbol inches min. max. min. max. millimeters notes a1 .001 .005 .05 .15 .057 1.45 a2 .053 1.35 b .006 .010 .17 .27 d/e d1/e1 .019 bsc .346 .362 8.8 9.2 .268 .284 6.8 7.2 .50 bsc e l .017 .029 .45 .75 6 4 5 2 7 8 0 7 0 7 n48 48 12 12 nd ccc .004 0.08 notes: 1. 2. 3. 4. 5. 6. 7. 8. d1 all dimensions and tolerances conform to ansi y14.5m-1982. dimensions "d1" and "e1" do not include mold protrusion. allowable protrusion is 0.25mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. pin 1 identifier is optional. dimension nd: number of terminals. dimension nd: number of terminals per package edge. "l" is the length of terminal for soldering to a substrate. dimension "b" does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. dambar can not be located on the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm pitch packages. to be determined at seating place ?
fms3110/3115 data sheet ? 2004 fairchild semiconductor corporation life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com ordering information product number conversion rate lead free t emperature range screening package package marking fms3110krc 100 ms/s 0? to 70? commercial 48-lead lqfp 3110krc fms3110krc_nl 100 ms/s yes 0? to 70? commercial 48-lead lqfp 3110krc_nl FMS3115krc 150 ms/s 0? to 70? commercial 48-lead lqfp 3115krc

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