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syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 1 product list SM5964Al25, 25mhz 64kb internal flash mcu general description the SM5964A is a single-chip 8-bits micro- controller manufactured in an advanced cmos process with on chip flas h memory. it supports in- system programming (i sp) function and is a derivative of the 8052 microcontroller family. the SM5964A has the same instru ctions set as the 80c51. the SM5964A contains a 64kb 3.3v on chip program flash, a volatile 1024 x 8 data ram, four 8-bits i/o ports, one 4-b its i/o port, two 16-bits timer/event counters, and an additional 16-bits timer coupled to capture a nd compare latches, a two-priority-level, nested interrupt structure, two pulse-width- modulation (p wm) outputs, two serial interfaces (uart and twsi bus). for system that requires extra capability the SM5964A can be expanded using standard lvttl compatible memory and logic. in addition, the SM5964A has two software selectable modes of power saving ? idle mode and power-down mode. the idle mode freezes the cpu while allowing the ram, timer, serial ports, and interrupt system to continue functioning. the power-down mode saves the ram contents but freezes the oscillator, causing all other chip functions to be inoperative. the SM5964A is designed for 3.3v applications. the on chip flash memory can store data while the program is running. it also can upgrade the user program by down-load new code form pc or other devices. the chip is considered as a small integrated system. ordering information SM5964Aihhkl yymmv i: process identifier {l=3.0v~3.6v} hh: working clock in mhz {25} k: package type postfix {as below table} yy: year mm: month v: version identifier { , a, b, ...} l: pb free identifier {no text is non-pb free, ?p? is pb free} feature z working voltage:3.0v through 3.6v z 80c51 central processor unit (cpu) z 64k x 8 on chip flash memory with in- system-programming(isp) capability and it can be programmed at v cc = 3.3v z 1024 x 8 ram, expandable externally to 64kb z two standard 16-bits timers/counters z an additional 16-bits timer/counter coupled to a capture and compare register. z two 8-bits / 5-bits resolution pulse-width-modulation (pwm) outputs z four 8-bits i/o ports.(for pdip package) z four 8-bits i/o ports pl us one 4-bits i/o port. (for plcc or qfp package) z twsi-bus serial i/o port with master and slave functions z full-duplex uart z 7 interrupt sources with 2 priority levels z temperature range (0 to +70 ) z software enable/disable ale output pulse z wake-up from powe r-down mode by external interrupt or h/w reset. z isp service program space configurable in n*512 byte (n=0 to 8) size taiwan 6f, no.10-2 li- hsin 1st road , science-based industrial park, hsinchu, taiwan 30078 tel: 886-3-567-1820 886-3-567-1880 fax: 886-3-567-1891 886-3-567-1894
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 2 pin configuration package spec. k package pin / pad j 44l plcc figure 1 q 44l qfp figure 2 p 40l pdip figure 3 figure 1 44l plcc package figure 2 44l qfp package figure 3 40l pdip package
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 3 block diagram uart int-ram 256x8 timer0 timer1 int cpu iap flash 64kx8 ext-ram 768x8 twsi pwm timer2 ibus c51 core wr res t0 t1 (3) (3) int0 int1 (3) (3) p0 p1 p2 p3 port0 port1 port2 port3 port4 parallel i/o ports & ext. bus p4 scl sda ( 1 ) ( 1 ) (3) rd (3) psen ale xtal2 xtal1 ea pwm0 pwm1 (1) (1) t2ex t2 (1) (1) notes: (1): alternate function of p1 (3): alternate function of p3 txd rxd (3) (3) pdwu (3) (3) int0 int1
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 4 pin description mnemonic pdip 40 pin pqfp 44 pin plcc 44 pin names and functions vdd 40 38 44 power supply : +3.3v power supply pin during normal operations and power saving modes. p0.0 ? p0.7 39,38,37,36 35,34,33,32 37,36,35,34 33,32,31,30 43,42,41,40 39,38,37,36 port 0 : port 0 is an open-drain, bidirectional i/o port. port 0 pins that have 1s written to them become floating and can be used as high- impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to ex ternal program and data memory. in this application, it uses strong internal pull-ups when emitting 1s. p1.0 ? p1.7 1,2,3,4, 5,6,7,8 40,41,42,43, 44,1,2,3 2,3,4,5, 6,7,8,9 port 1: an 8-bits bidirectional i/o port with internal pull-ups on all pins. port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (see dc electrical characteristics: iil). alternate function of SM5964A include port pin alternative function p1.0 t2 timer2 clock output p1.1 t2ex timer2 reload/capture dir. p1.2 pwm0 pwm channel 0 output p1.3 pwm1 pwm channel 1 output p1.6 scl twsi bus clock p1.7 sda twsi bus data rst 9 4 10 reset : a high on this pin for two machine cycles while the oscillator is running resets the device. an inte rnal resistor to vss permits a power-on reset using only an external capacitor to vcc. p2.0 ? p2.7 21,22,23,24, 25,26,27,28 18,19,20,21 22,23,24,25 24,25,26,27, 28,29,30,31 port 2: port 2 is an 8-bits bidirectional i/ o port with internal pull-ups. port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (see dc electrical characteristics: iil). port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bits addresses (movx @dptr). in this applicat ion, it uses strong internal pull-ups when emitting 1s. during accesses to external data memory that uses 8-bits addresses (mov @ri), port 2 emits the contents of the p2 special function register. p3.0 ? p3.7 10,11,12,13 14,15,16,17 5,7,8,9, 10,11,12,13 11, 13,14,15, 16,17,18,19 port 3 : port 3 is an 8-bits bidirectional i/ o port with internal pull-ups. port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (see dc electrical characteristics: iil). port 3 also serves the special features. port pin alternative function p3.0 rxd uart input p3.1 txd uart output p3.2 #ex0 external interrupt 0 p3.3 #ex1 external interrupt 1 p3.4 t0: timer 0 external input p3.5 t1: timer 1 external input p3.6 #wr external data memory write strobe p3.7 #rd external data memory read strobe
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 5 mnemonic pdip 40 pin pqfp 44 pin plcc 44 pin names and functions ale 30 27 33 address latch enable: output pulse for latching the low byte of the address during an access to external memory. in normal operation, ale is emitted twice every machine cycle, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. setting sfr sconf.0 can disable ale. with this bit set, ale will be active only during a movx instruction. #psen 29 26 32 program store enable: the read strobe to external program memory. when executing code from the external program memory, #psen is activated twice each machine cycle, except that two #psen activations are skipped during each access to external data memory. #psen is not activated during fetches from internal program memory. #ea 31 29 35 external access enable : #ea must be externally held low to enable the device to fetch code from external program memory locat ions. if #ea is held high, the device executes from internal program memory. x1 19 15 21 crystal 1 : input to the inverting oscillator am plifier and input to the internal clock generator circuits. x2 18 14 20 crystal 2 : output from the inverting oscillator amplifier.
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 6 sfr mapping the special function regist er of SM5964A fall into the following categories z c51 core register: acc, b, dpl, dph, psw, sp z i/o ports: p0,p1, p2, p3, p4, p1con z timer/counter register: t2con, t2mod, tcon, tmod, th0, th1, th2, tl0, tl1, tl2, rcap2l, rcap2h z uart i/o register: sbuf, scon z twsi bus register: twsis, twsia, twsic1, twsic2, twsitxd, twsirxd z power and system control register: pcon, sconf z interrupt system register: ip, ie, ip1, ie1, ifr z iap flash programming register :ispfah, ispfal, ispfd, ispc z pwm output register: pwmc0, pwmc1, pwmd0, pwmd1 table 1 sfr map $f8 $ff $f0 b 0000 0000 ispfah 0000 0000 ispfal 0000 0000 ispfd 0000 0000 ispc 0000 0000 $f7 $e8 $ef $e0 acc 0000 0000 $e7 $d8 p4 xxxx 1111 $df $d0 psw 0000 0000 pwmc0 0000 0000 pwmc1 0000 0000 $d7 $c8 t2con 0000 0000 t2mod xxxx xx00 rcap2l 0000 0000 rcap2h 0000 0000 tl2 0000 0000 th2 0000 0000 $cf $c0 twsis 0000 0000 twsia 1010 0000 twsic1 0000 0001 twsic2 0000 0000 twsitxd 1111 1111 twsirxd 0000 0000 $c7 $b8 ip 0000 0000 ip1 0000 0000 sconf 0000 0000 $bf $b0 p3 1111 1111 pwmd0 0000 0000 pwmd1 0000 0000 $b7 $a8 ie 0000 0000 ie1 0000 0000 ifr 0000 0000 $af $a0 p2 1111 1111 $a7 $98 scon 0000 0000 sbuf xxxx xxxx p1con 0000 0000 $9f $90 p1 1111 1111 $97 $88 tcon 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 $8f $80 p0 1111 1111 sp 0000 0111 dpl 0000 0000 dph 0000 0000 rcon 0000 0000 pcon 0000 0000 $87
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 7 table 2 : all sfr list (8051, i/o, ti mer, uart, twsi, system, interrupt) symbol description direct bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset 8051 core acc accumulator e0h 00h b b register f0h 00h sp stack pointer 81h 07h psw process status d0h cy ac f0 rs1 rs0 ov p 00h dph data pointer high 83h 00h dpl data pointer low 82h 00h i/o port p0 port 0 80h p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 ffh p1 port 1 90h p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 ffh p2 port 2 a0h p2.7 p2 .6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 ffh p3 port 3 b0h p3.7 p3 .6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 ffh p4 port 4 d8h p4 .3 p4.2 p4.1 p4.0 xfh p1con p1 control 9bh sdae scle pwm1e pwm0e - - 00h timer / counter tcon timer control register 88h tf1 tf1 tf0 tr0 ie1 it1 ie0 it0 00h tmod timer mode 89h gate c/t m1 m0 gate c/t m1 m0 00h th0 timer 0 high 8ch 00h tl0 timer 0 low 8ah 00h th1 timer 1 high 8dh 00h tl1 timer 1 low 8bh 00h t2con timer 2 control c8h tf2 exf2 rclk tclk exen2 tr2 ct2 cprl2 00h t2mod timer 2 mode c9h t2oe dcen x0h rcap2h rcap2 high cbh 00h rcap2l rcap2 low cah 00h th2 timer 2 high cdh 00h tl2 time 2 low cch 00h uart scon uart control 98h sm0 sm1 sm2 ren tb8 rb8 ti ri 00h sbuf uart buffer 99h xxh twsi bus twsis twsi bus status c0h rxif txif tfif nakif rxak master txak 00h twsia twsi address c1h a0h twsic1 twsi control 1 c2h twsie bus busy twsifs2 twsifs1 twsifs0 01h twsic2 twsi control 2 c3h match srw restart mrw 00h twsitxd twsi transmit data c4h ffh twsirxd twsi received data c5h 00h power and system pcon power control register 87h smod gf1 gf0 pd idle 00h sconf system control bfh pdwue ispe ome alei 00h interrupt system ie interrupt enable a8h ea et2 es0 et1 ex1 et0 ex0 00h ie1 interrupt enable 1 a9h etwsi 00h ifr interrupt flag 1 aah twsiif 00h ip interrupt priority b8h pt2 ps0 pt1 px1 pt0 px0 00h ip1 interrupt priority 1 b9h ptwsi 00h data memory rcon internal ram control 85h rams1 rams0 00h isp flash memory ispfah isp address high f4h 00h ispfal isp address low f5h 00h ispfd isp data f6h 00h ispc isp control f7h start ispf1 ispf0 00h pwm output pwmc0 pwm 0 control d3h pbs pfs1 pfs0 00h pwmc1 pwm 1 control d4h pbs pfs1 pfs0 00h pwmd0 pwm 0 data b3h pwmd.7 pwmd.6 pwmd.5 pwmd.4 pwmd.3 pwmd.2 pwmd.1 pwmd.0 00h pwmd1 pwm 1 data b4h pwmd.7 pwmd.6 pwmd.5 pwmd.4 pwmd.3 pwmd.2 pwmd.1 pwmd.0 00h operating conditions symbol description min. typ. max. unit. remarks ta operating temperature 0 25 70 ambient temperature under bias
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 8 vcc33 supply voltage 3.0 3.3 3.6 v fosc 25 oscillator frequency 25 mhz for 3.3v application dc characteristic vcc = 3.3v ( 10%), vss=0v ta= 0 to +70 limits symbol parameter test conditions min max unit v cc supply voltage 3.0 3.6 v i cc supply current operating see notes 1 f clk = 12mhz v cc = 3.6v 10 ma i id supply current idle mode see note 2 f clk = 12mhz v cc = 3.6v 5 ma i pd supply current power-down mode see note 3 2v < v pc < v ccmax 20 a input vil1 input low voltage, port 0,1,2,3,4,/ea -0.5 0.8 v vil2 input low voltage, res, xtal1 0 0.8 v vih1 input high voltage, port 0,1,2,3,4,ea 2.0 vcc+0.2 v vih2 input high voltage, res, xtal1 70% vcc vcc+0.2 v iil1 input current low level port 1,2,3,4 ( except p1.6,p1.7 ) vin = 0.45v -50 a iil2 input current low level port 0,p1.6,p1.7 vin = 0.45v -650 a itl transition current high to low port 1,2,3,4 vin = 1.5 v -650 a ili input leakage current 0.45v < vin < vcc 10 a isk1 sink current port 1, 2, 3, 4 vcc = 3.3v, vin = 0.4 v 3 6 ma isk2 sink current port 0,ale, /psen vcc = 3.3v, vin = 0.4 v 4 8 ma isr1 source current port 1, 2, 3, 4 vcc = 3.3v, vin = 2.4 v -40 -80 ua isr2 source current port 0,al e, /psen vcc = 3.3v, vin = 2.4 v -4 -8 ma output v ol1 output low voltage, port 0,ale, /psen i ol = 3.2ma v cc =3.3v 0.4 v v ol2 output low voltage, port 1, 2, 3, 4 i ol = 1.6ma v cc =3.3v 0.4 v v oh1 output high voltage port0 ale, /psen i oh = -300ua v cc =3.3v 2.4 v v oh1 output high voltage port 1,2,3,4 i oh = -20 a v cc =3.3v 2.4 v r rst internal reset pull-down resistor vcc=3.6v 50 300 k c io pin capacitance test freq=1mhz, t a =25 10 pf notes for dc electrical characteristics 1. the operating supply current is meas ured with all output disconnected; xtal1 driven with t r = t f = 5ns; v il = v ss +0.5v; v ih =v cc -0.5v; xtal2 not connect;/ea=rst=port0=v dd ; 2. the idle mode supply curre nt is measured with al l output pins disconnected; xtal1 driven with t r = t f = 5ns; v il = v ss +0.5v; v ih =v cc -0.5v; xtal2 not connect;/ea= port0=v dd ; 3. the power-down mode supply current is meas ured with all output pins disconnected; v il = v ss +0.5v; v ih =v cc -0.5v; xtal2 not connect; /ea= port0=v dd ; 4. port 1, 2, 3, and 4 sources a transition current when they are being externally driven from high to low. the transition current reaches its maximum value when v in is approximately 2v. 5. capacities loading on port 0 a nd 2 may cause spurious noise to be superimposed on v ol of ale and port 1, 3, and 4. the noise is due to external bus capacitance discharging into port 0 and port 2 pins when thes e pins make 1-to-0 transitions during bus operations. in the w orst cases (capacities loading > 100pf), the no ise pulse on the ale pin may exceed 0.8v. in su ch cases, it may be de sirable to qualify ale with a schmitt trigger, or use an address latch w ith a schmitt tri gger strobe input. 6. under steady state (non-transient) c onditions, iol must be externally limited as follows: maximum iol per pin (use sign pin only) : 10ma maximum iol per 8-bit port : port 0 : 26ma port 1,2,3 : 15ma maximum total iol for all output pins : 71ma if iol exceeds the condition, vol may exceed the related specifica tion. pins are not guaranteed to sink current greater than th e listed test conditions.
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 9 ac characteristic v cc =3.3v 10%, v ss =0v, t clk min = 1/ f max (maximum operating frequency) t a =0 to + 70 c l =100pf for port0, ale and /psen; c l =80pf for all other outputs unless otherwise specified. symbol figure parameter min max unit external clock drive into xtal1 tclk 4 xtal1 period 40(1) - ns tclkh 4 xtal1 high time 20 - ns tclkl 4 xtal1 low time 20 - ns tclkr 4 xtal1 rise time - 10 ns tclkf 4 xtal1 fall time - 10 ns tcyc 4 controller cycle time = tclk / 12 3.33 - ns notes : 1. operating is 25mhz. symbol figure parameter min max unit program memory 1/tclk 7 system clock frequency 3.0 25 mhz tlhll 7 ale pulse width 2tclk-40 ns tavll 7 address valid to ale low tclk-40 ns tllax 7 address hold after ale low tclk-30 ns tlliv 7 ale low to valid instruction in 4tclk-100 ns tllpl 7 ale low to /psen low tclk-30 ns tplph 7 /psen pulse width 3tclk-45 ns tpliv 7 /psen low to valid instruction in 3tclk-105 ns tpxix 7 input instruction hold after /psen 0 ns tpxiz 7 input instruction float after /psen tclk -25 ns taviv 7 address to valid instruction in 5tclk-105 ns tplaz 7 /psen low to address float 10 ns data memory tavll 8,9 address valid to ale low tclk-40 ns tllax 8,9 address hold after ale low tclk-35 ns trlrh 8 /rd pulse width 6tclk-100 ns twlwh 9 /wr pulse width 6tclk-100 ns trldv 8 /rd low to valid data in 5tclk-165 ns trhdx 8 data hold after /rd 0 ns trhdz 8 data float after /rd 2tclk-70 ns tlldv 8 ale low to valid data in 8tclk-150 ns tavdv 8 address to valid data in 9tclk-165 ns tllwl 8,9 ale low to /rd or /wr low 3tclk-50 3tclk+50 ns tavwl 8,9 address valid to /wr or /rd low 4tclk-130 ns tqvwx 9 data valid to /wr transition tclk-50 ns tqvwh 9 data before /wr 7tclk-150 ns twhqx 9 data hold after /wr tclk-50 ns trlaz 8 /rd low to address float 0 ns twhlh 8,9 /rd or /wr high to ale high tclk-40 tclk+40 ns uart txlxl 10 serial port clock time 12tclk ns tqvxh 10 output data setup to cl ock rising edge 10tclk-133 ns txhqx 10 output data hold after cloc k rising edge 2tclk-117 ns txhdx 10 input data hold after clock rising edge 0 ns txhdv 10 clock rising edge to input data valid 10tclk-133 ns
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 10 figure 4 external clock drive waveform figure 5 ac testing input/output figure 6 ac testing, floating waveform ale /psen port0 port2 a0-a7 instr in a0-a7 a8-a15 a8-a15 a8-a15 a8-a15 t lhll t llpl t plph t llax t aviv t avll t lliv t plaz t pxix t pxiz t pliv figure 7 external program memory read cycle floating 2.0v 0.8v 0.8v 2.0v notes: the float state is define as the point which port 0 pins sinks 3.2ma or source 400 a at the voltage test level. test points 2.0v 0.8v 0.8v 2.0v notes: ac inputs during testing are driven at 2.4v for logic ?high? and 0.45v for logic ?low?. timing measurements are at 2.0v for logic ?high? and 0.8v for lo g ic ?low? t clkh t clkl 0.8v t cl k v ih1 t clkr t clkf
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 11 ale /psen /rd port0 port2 a0 - a7 (ri or dpl) data in a0 - a7 (pcl) instr in a8 - a15 of dph or port2 a8 - a15 (pch) t avwl t avdv t rlaz t rldv t rlrh t lldv t whlh t rhdz t rhdx t avll t llax t llwl figure 8 external memory read cycle ale /psen /wr port0 port2 a0 - a7 (ri or dpl) data out a0 - a7 (pcl) instr in a8 - a15 of dph or port2 a8 - a15 (pch) t avwl t wlwh t whqx t avll t llax t llwl t whlh t qvwx t qvwh figure 9 external memory write cycle n struction ale clock txd rxd 0 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 valid valid valid valid valid valid valid valid set_r t xlxl t qvxh t xhqx t xhdv t xhdx figure 10 uart waveform in shift register mode
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 12 figure 11 timing waveform of twsi interface standard-mode fast-mode symbol figure parameter min max min max unit twsi bus f scl 11 scl clock frequency 0 100 0 400 khz t buf 11 bus free time between a stop and stop condition 4.7 - 1.3 - s t hd;sta 11 hold time (repeated) start condition. after this period, the first clock pulse is generated 4.0 - 0.6 - s t low 11 low period of the scl clock 4.7 - 1.3 - s t high 11 high period of the scl clock 4.7 - 1.3 - s t su;sta 11 set-up time of a repeat ed start condition 4.0 - 0.6 0 s t hd;dat 11 data hold time 0 - 0 0.9 s t su;dat 11 data setup-time 250 - 100 (1) - ns t rd, t rc 11 rise time of both sda and scl - 1000 20+0.1c b (2) 300 ns t fd t fc 11 fall time of both sda and scl - 300 20+0.1c b (2) 300 ns t su;sto t su;sta 11 set-up time for stop a nd start condition 4.0 - 0.6 - s c b 11 capacitive load for each bus line - 400 - 400 pf t sp 11 pulse width of spikes which must be suppressed by input filter - - 0 50 ns notes: 1. a fast-mode twsi bus device can be used in a standard-mode twsi bus system, but the requirement t su;dat 250ns must the be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stre tch the low period of the scl signal, it must output the next data bit to sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode twsi bus sp ecification) before the scl line is released. 2. c b = total capacitance of one bus line in pf. 0.3v cc 0.7v cc sda t fd t hd;sta t low t high t rc t fc t su;dat1 t su;dat t sp t su;dat2 t su;dat3 t buf t su;sta t su;sto start or repeat start condition scl repeat start condition stop condition start t rd t hd;dat
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 13 function description the SM5964A is a stand-alone high-performance microcontrolle r designed for using in 3.3v isp applications, such as lcd monitor, instrumentation, or high-end consumer applications. in addition to the 80c51 standard func tions, the device provides a number of dedicated hardware functions for these applications. the SM5964A is a control-oriented cpu with on-chip program and data memory. it can be extended with external data memory up to 64k bytes. for system requiring extra capability , the SM5964A can be enhanced by using external memory and peripherals. the SM5964A has two software selectab le modes of saving power consumption idle and power- down. the idle mode freezes the cpu while allowing the ram, timer, serial ports and interrupt system to continue functioning. the power-down mode save the ram contents but freezes the osc illator causing all other chip fu nctions to be inoperative. the power-down mode can be terminated by h/w reset , or by any one of the two external interrupt. cpu the cpu of SM5964A is compatible to standard 80c51. the st ructure of this cpu is shown as figure 12. it contains instruction register (ir), instruction decoder, program count er (pc), accumulator (acc), b register, and control logic. this cpu provides a 8-bits bi-direction bus to communicate with other blocks in the chip. the address and data are transferred through on the same 8-bits bus. figure 12 the cpu structure cpu timing the machine cycle consists of a sequence of 6 states, numbere d s1 through s6. each state time lasts for two oscillator periods. thus a machine cycle takes 12 oscillator periods. each state is divided into a phase1 half and a phase2 half. figure 13 shows relationships betwee n oscillator, phase, and s1-s6. alu ir q res cl k data in/out ctrl. bus prog. addr. power ctrl signal control logic timing & reset instruction decoder instruction register sp b re g iste r psw acc tmp1 tmp2 program addr.register buffer program increment program counter dptr pcon
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 14 figure 13 sequences and phases figure 14 shows the fetch / execute sequences in states and phases for various kinds of instructions. normally the program fetches are generated during each machine cycle, even if the instruction being executed doesn?t require it. if the instruction being executed doesn?t need more code bytes, the cpu simply ignores the extra fetch, and the program counter is incremented accordingly. execution of a one-cycle instruction (figure 14 a and b) begi ns during s1 of the machine cycle, when the opcode is latched into instruction register. a second fetch occurs during s4 of the same machine cycle. execution is completed at the end of s6 of this machine cycle. the movx instructions take two machine cycles to execute. no program fetch is generated during the second cycle of a movx instruction. this is the only time program fetches are skipped. the fetch/execute seq uence for movx instructions is shown in figure 14 (d) the fetch / execute sequences are the same whether the pr ogram memory is internal or external to the chip. execution times do not depend on whether the pr ogram memory is internal or external. figure 15 shows the signals and timing involved in progr am fetches when the program memory is external. if program memory is external, the program memory read stobe (/psen) is normally activated twice per machine cycle, as shown in figure 15(a). if an access external data memory occurs, as shown in figure 15(b), two (/psen) are skipped, because the address and data bus are being used for data memory access. note that a data memory bus cycle takes twice as much time as program memory bus cycle. figure 15 shows the relative time of the address begin emitted at port0 and port2, and of ale and / psen. ale is used to latch the low address byte form port0 into the address latch. when cpu is executing from internal program memory, /psen is not activated, and program address are not emitted. however, ale continues to be activated twice per m achine cycle and so is available as clock output signal. note, however, that ale is skipped during th e execution of the movx instruction. p1 p2 p1 p2 p1 p2 p1 osc (xtal2) p2 p1 p2 p1 p2 p1 p2 p1 s1 s2 s3 s4 s5 s6 s1 s2 phase sequence
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 15 figure 14 timing of various instructions a.) 1 byte, 1 cycle instruction read opcode read next opcode discard read next opcode again 1 machine cycle s1 s2 s3 s4 s5 s6 s1 s2 b.) 2 byte, 1 cycle instruction read opcode read 2?nd byte read next opcode 1?st cycle c.) 1 byte, 2 cycle instruction read opcode read next opcode again 1 machine cycle 2?nd cycle read next opcode (discard) 1?st cycle d.) movx: 1 byte, 2 cycle instruction read opcode read next opcode again 2?nd cycle read next opcode (discard) n o fetch n o fetch access external memory addr data s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s1 s2 s3 s4 s5 s6 s1 s2
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 16 figure15: bus cycle in exte rnal program memory mode instruction set the SM5964A uses the powerful instruction set of 80c51. it cons ists of 49 single-byte, 42 two-byte, and 15 three- byte instructions. among them 63 instructions are executed in 1 ma chine-cycle, 46 instructions in 2 machine-cycles, and the multiply, 2 instructions in 4 machine-cycles. a summary of the instruction set is given in table 4. one cycle a.) without movx s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 one cycle ale /psen /rd p2 pch out pch out pch out pch out pcl out inst. in pcl out inst. in pcl out inst. in pcl out inst. in pcl out p0 1?st cycle b.) with movx 2?nd cycle ale /psen /rd p2 pch out p2 or dph out pch out pcl out inst. in addr. out data. in pcl out inst. in pcl out p0 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 17 addressing mode notes on instruction set and address modes: rn register r7-r0 of the curre ntly selected register bank. direct 8-bits internal data location?s address. this could be internal data ram location (0-127) or a sfr [i.e., i/o port, control register, status register, etc. (128-255)] @ri 8-bits ram location addressed indirectly through register r1 or r0 of the actual register bank #data 8-bits constant included in the instruction #data16 16-bits constant included in the instruction addr11 11-bits destination address. used by acall a nd ajmp. the branch can be an ywhere within the same 2 k bytes page of program memory as the first byte of the following instruction. rel signed (2?s complement) 8-bits offset byte. used by sjmp and all conditional jumps. range is -128 to +127 bytes relative to first byte of the following instruction. bit direct addressed bit in internal data ram or sfr table 4: a summary of the instruction set mnemonic operation byte cycle arithmetic instructions add a,rn a = a + rn 1 1 add a,direct a = a + direct 2 1 add a,@ri a = a + <@ri> 1 1 add a,#data a = a + #data 2 1 addc a,rn a = a + rn + c 1 1 addc a,direct a = a + direct + c 2 1 addc a,@ri a = a + @ri + c 1 1 addc a,#data a = a + #data + c 2 1 subb a,rn a = a rn c 1 1 subb a,direct a = a direct c 2 1 subb a,@ri a = a <@ri> c 1 1 subb a,#data a = a #data c 2 1 inc a a = a + 1 1 1 inc rn rn = rn + 1 1 1 inc direct direct = direct + 1 2 1 inc @ri <@ri> = <@ri> + 1 1 1 dec a a = a 1 1 1 dec rn rn = rn 1 1 1 dec direct direct = direct 1 2 1 dec @ri <@ri> = <@ri> 1 1 1 inc dptr dptr = dptr 1 1 2 mul ab b:a = a b 1 4 div ab a = int (a/b) b = mod (a/b) 1 4 da a decimal adjust acc 1 1 logical instructions anl a,rn a .and. rn 1 1 anl a,direct a .and. direct 2 1 anl a,@ri a .and. <@ri> 1 1 anl a,#data a .and. #data 2 1 anl direct,a direct .and. a 2 1 anl direct,#data direct .and. #data 3 2 orl a,rn a .or. rn 1 1 orl a,direct a .or. direct 2 1 orl a,@ri a .or. <@ri> 1 1 orl a,#data a .or. #data 2 1 orl direct,a direct .or. a 2 1 orl direct,#data direct .or. #data 3 2 xrl a,rn a .xor. rn 1 1 xrl a,direct a .xor. direct 2 1 xrl a,@ri a .xor. <@ri> 1 1 xrl a,#data a .xor. #data 2 1 xrl direct,a direct .xor. a 2 1 xrl direct,#data direct .xor. #data 3 2 clr a a = 0 1 1
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 18 cpl a a = /a 1 1 rl a rotate acc left 1 bit 1 1 rlc a rotate left through carry 1 1 rr a rotate acc right 1 bit 1 1 rrc a rotate right through carry 1 1 swap a swap nibbles in a 1 1 data transfers instructions mov a,rn a = rn 1 1 mov a,direct a = direct 2 1 mov a,@ri a = <@ri> 1 1 mov a,#data a = #data 2 1 mov rn,a rn = a 1 1 mov rn,direct rn = direct 2 2 mov rn,#data rn = #data 2 1 mov direct,a direct = a 2 1 mov direct,rn direct = rn 2 2 mov direct,direct direct = direct 3 2 mov direct,@ri direct = <@ri> 2 2 mov direct,#data direct = #data 2 1 mov @ri,a <@ri> = a 1 1 mov @ri,direct <@ri> = direct 2 2 mov @ri,#data <@ri> = #data 2 1 mov dptr,#data16 dptr = #data16 3 2 movc a,@a+dptr a = code memory[a+dptr] 1 2 movc a,@a+pc a = code memory[a+pc] 1 2 movx a,@ri a = external memory [ri] (8-bits address) 1 2 movx a,@dptr a = external memory [dptr] (16-bits address) 1 2 movx @ri,a external memory[ri] = a (8-bits address) 1 2 movx @dptr,a external memory[dpt r] = a (16-bits address) 1 2 push direct inc sp: mov ?@?sp?, < direct > 2 2 pop direct mov < direct >, ?@sp?: dec sp 2 2 xch a,rn acc and < rn > exchange data 1 1 xch a,direct acc and < direct > exchange data 2 1 xch a,@ri acc and < ri > exchange data 1 1 xchd a,@ri acc and @ri exchange low nibbles 1 1 boolean instructions clr c c = 0 1 1 clr bit bit = 0 2 1 setb c c = 1 1 1 setb bit bit = 1 2 1 cpl c c = /c 1 1 cpl bit bit = /bit 2 1 anl c,bit c = c .and. bit 2 2 anl c,/bit c = c .and. /bit 2 2 orl c,bit c = c .or. bit 2 2 orl c,/bit c = c .or. /bit 2 2 mov c,bit c = bit 2 1 mov bit,c bit = c 2 2 jc rel jump if c= 1 2 2 jnc rel jump if c= 0 2 2 jb bit,rel jump if bit = 1 3 2 jnb bit,rel jump if bit = 0 3 2 jbc bit,rel jump if c = 1 3 2 jump instructions acall addr11 call subroutine only at 2k bytes address 2 2 lcall addr16 call subroutine in max 64k bytes address 3 2 ret return from subroutine 1 2 reti return from interrupt 1 2 ajmp addr11 jump only at 2k bytes address 2 2 ljmp addr16 jump to max 64k bytes address 3 2 sjmp rel jump on at 256 bytes 2 2 jmp @a+dptr jump to a+ dptr 1 2 jz rel jump if a = 0 2 2 jnz rel jump if a 0 2 2 cjne a, direct,rel jump if a < direct > 3 2
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 19 cjnz a, #data,rel jump if a < #data > 3 2 cjnz rn, #data,rel jump if rn < #data > 3 2 cjnz @ri, #data,rel jump if @ri < #data > 3 2 djnz rn,rel decrement and jump if rn not zero 2 2 djnz direct,rel decrement and jump if direct not zero 3 2 nop no operation 1 1 memory organization the central processing unit (cpu) manipulates operands in thr ee memory spaces; there are 1024 bytes internal data memory (consisting of 256 bytes standard ram and 768 by tes aux-ram) and 64k bytes internal/external program memory (see figure 16) figure 16 memory organization of SM5964A program memory the program memory of SM5964A consists of 64k bytes flash memory on chip. if during reset, the /ea pin was held high, the SM5964A does not execute out of the inte rnal program memory. if the /ea pin was held low during reset the SM5964A fetch all instructions from the external program memory. the flash memory of SM5964A can be programmed during the program is running by using isp. norm ally, a writer is used for programming. the feature of flash memory is shown as following: z read: byte-wise z write: byte-wise within 30us (previously erased by a chip erase). z erase: full erase (64k bytes) within 2 sec. erased bytes contain ffh z endurance : 10k erase and write cycles each byte at ta=25 z retention : 10 years program code security movc instruction executed from extern al program memory space will not be able to fetch internal codes from on chip program memory after the chip is protected on the writer. internal flash memory /ea=1 0000 64k external flash memory /ea=0 program memory indirect only direct and indirect 0000 0080 02ff overlapped space direct (sfr) xram (ome=1) xram (ome=0) 0000 64k internal data memory external data memory
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 20 internal data memory the data memory of SM5964A consists of 1024 bytes inte rnal data memory (256 bytes standard ram and 768 bytes aux-ram). the aux-ram is enable by sconf.1 ($bf.1), and read/write by movx internal ram control register (rcon, $85) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rams1 rams0 SM5964A has 768 byte on-chip ram which can be accessed by external memory addressing method only. (by instruction movx). the address space of instruction movx @rn is determined by bit 1 and bit 0 (rams1, rams0) of rcon. the default setting of rams1, rams0 bits is 00 (page0). pulse width modulation (pwm) the pwm output pins are p1.2 and p1.3. the pwm clock is {fosc/ (2xdivider)}, the pwm output fre quency is {(pwm clock)/32} at 5 bits resolution and {(pwm clock)/256} at 8 bits resolution. the pwm sfr has shown as below: pwmc [0:1] ($d3h and $d4h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 pbs pfs1 pfs0 pbs: when set, the pwm is 5 bits resolution. pfs [1:0]: the pwm clock divider select. pfs1 pfs0 pwm clock divider select 0 0 2 0 1 4 1 0 8 1 1 16 pwmd [0:1] ($b3h and $b4h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 pwmd.7 pwmd.6 pwmd.5 pwmd.4 pwmd.3 pwmd.2 pwmd.1 pwmd.0 two-wire series interface (twsi) the twsi module uses the scl (clock) and the sda (data) line to communicate with exte rnal twsi interface between other twsi parts. the speed can up to 400k bps (max.) by software setting the twsifs [2:0]. the twsi module used sfr shown as below twsi status register: twsis ($c0h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rxif txif tfif nakif rxak master txak rxif : the data receive interrupt flag (rxif) is set after th e twsirxd (twsi receive data buffer) is loaded with a newly receive data. txif : the data transmit interrupt flag (txif) is set when the data of the twsitxd (twsi transmit data buffer) is downloaded to the shift register or the twsia is downl oaded to the shift register at master transmit mode. tfif : the transmit fail interrupt flag is set when the data transmit fail.
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 21 nakif : the non-acknowledge interrupt flag is only set in the master mode when there is no acknowledge bit detected after one byte data or calling address is transferred. rxak : the acknowledge status indicate bit. when clear, it m eans an acknowledge signal has been received after the complete 8 bits data transmit on the bus. master : this bit define this module is working at master mode. txak : the acknowledge status transmit bit. when received complete 8 bits data, this bit will set (noack) or clear (ack) and transmit to master to indicate the receive status. twsia ($c1h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 twsia.7 twsia.6 twsia.5 twsia.4 twsia.3 twsia.2 twsia.1 extaddr twsia [7:1] : twsi address registers 7 bits. extaddr : its only compare 4 bits msb when set this bit. twsic1 ($c2h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 twsie busbusy twsifs2 twsifs1 twsifs0 twsie : enable twsi module. busbusy : when start condition is detected, this bit will set. when stop condition is detected, this bit will clear. twsifs [2:0] : the twsi scl speed divider select. twsifs [2:0] speed 000 xtal/32 001 xtal/64(default) 010 xtal/128 011 xtal/256 100 xtal/512 101 xtal/1024 110 xtal/2048 111 xtal/4096 twsic2 ($c3h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 match srw restart mrw match : when the first received data (following the start signa l) in twsirxd register is matches with the address that address register (twsia) set, this bit will set. srw : the slave mode read (received) or wrote (transmit) on the twsi bus. when this bit is clear, the slave module received data on the twsi bus (sda). restart : this bit only set by master mode. the master will send a start signal then send twsia after the ack signal when this bit setting. if tfif was set (the nonack signal was received), the master mode will release, and this bit will clear. mrw : this bit is determined the data transmit direction. and this bit will transmit to bus as bit0 at address (address is collection twsia [7:1] and mrw as 8 bits data). when clear th is bit the master is in transmits mode and clear is in receive mode. twsitxd ($c4) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 twsitxd.7 twsitxd.6 twsitxd.5 twsitxd.4 twsitxd.3 twsitxd.2 twsitxd.1 twsitxd.0 the data written into this register will be automatical ly downloaded to the shift register when the module detects a calling address is matched and the bit 0 of the received data is one (slave transmit mode) or when the data in the shift register has been transmitted with received acknowledge bit (rxak) =0 in transmit
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 22 mode. twsirxd ( $c5) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 twsirxd.7 twsirxd.6 twsirxd.5 twsirxd.4 twsirxd.3 twsirxd.2 twsirxd.1 twsirxd.0 the twsi receive data buffer (twsirxd) contains the last received data when the match flag is one or the calling address from master when the match flag is zero. the twsirxd register will be updated after a data byte is received and the previous received data had been read out, otherwise the twsi module will pull down to scl line to inhabit the next data transfer. it is a read-only register. the read opera tion of this register will clear the rxif flag. after the rxif flag is cleared, the register can load the received data again and set the rxif flag to generate interrupt request for reading the newly received data. in-system programming (isp) the SM5964A can generator flash control signal by internal ha rdware circuit. that only need to put the isp service code into isp code area (4 kbytes and divided by 8 zones) the area is set by lock-bit (n), the lock-bit number and isp code area relation ship shown as below: lock-bit number isp code area 1 512 bytes (from $fe00h to $ffff) 2 1k bytes (from $fc00h to $ffff) 3 1.5 k bytes (from $fa00h to $ffff) 4 2 k bytes (from $f800h to $ffff) 5 2.5 k bytes (from $f600h to $ffff) 6 3 k bytes (from $f400h to $ffff) 7 3.5 k bytes (from $f200h to $ffff) 8 4 k bytes (from $f000h to $ffff) there are three ways to into isp code area: 1. blank reset: hardware reset with first flash address blank ($0000h = #ffh). 2. execute the ?ljmp? instruction. 3. by hardware setting: or the isp register: p2.6 rst p2.7 10ms 10ms rst p4.3 10ms 10ms
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 23 ispfah ($f4h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 fa15 fa14 fa13 fa12 fa11 fa10 fa9 fa8 fa15 ~ fa8: flash address-high for isp function ispfal ($f5h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 fa7 fa6 fa5 fa4 fa3 fa2 fa1 fa0 fa7 ~ fa0: flash address-low for isp function the ispfah & ispfal provide the 16-bits flash memory addr ess for isp function. the flash memory address should not include the isp service program space address. if the flash memory address indicated by ispfah & ispfal registers overlay with the isp service program space address, the flash program/page erase of isp function executed thereafter will have no effect. ispfd ($f6h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 fd7 fd6 fd5 fd4 fd3 fd2 fd1 fd0 fd7 ~ fd0: flash data for isp function the ispfd provide the 8-bits data for isp function. ispc ($f7h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 start ispf1 ispf0 ispf[1: 0]: isp function select bit start: isp function start bit = 1: start isp function which indicated by bit 1, bit 0 (ispf1, ispf0) = 0: no operation the start bit is read-only by default, software must wr ite three specific values 55h, a ah and 55h sequentially to the ispfd register to enable the start bit write attribute. that is: ex open isp function: mov ispfd, #55h mov ispfd, #0aah mov ispfd, #55h any attempt to set start bit will not be allowed without the procedure above. after start bit set to 1 then the SM5964A hardware circu it will latch address and data bus and hold the program counter until the start bit reset to 0 when isp function finished. u ser does not need to check st art bit status by software method ispf [1:0] isp function 00 byte program 01 chip protect 10 page erase (512 bytes) 11 chip erase ispf[1:0]: isp function select bits one page of flash memory is 512 bytes. to perform byte program / page erase isp function, user need to specify flash address at first. when performing page erase function, SM5964A will erase entire page which flash a ddress indicated by ispfah registers located within the page. to perform chip erase isp function, SM5964A will erase all the flash program memory and data flash memory except the
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 24 isp service program space if lock bit n been configured. al so, SM5964A will un-protect the flash memory automatically. to perform chip protect isp function, all the flash memory will be read all zero. e.g. isp service program to do the byte program - to program data of #22h to the address of the $1005h mov ispfd, #55h mov ispfd, #0aah mov ispfd, #55h ; open isp function mov sconf, #04h ; enable SM5964A isp function mov ispfah, #10h ; set flash address-high, 10h mov ispfal, #05h ; set flash address-low, 05h mov ispfd, #22h ; set flash data to be programmed, data = 22h mov ispfc, #80h ; start to prog ram data of 22h to the flash address of the $1005h ; after byte program finished, start bit of ispc will reset to 0 automatically ; program counter then point to the next instruction the power down wake up (pdwu) function the device can be put into power down mode by writing 1 to bit pcon.1. the instruction that does this will be the last instruction to be executed before the device goes into power down mode. in th e power down mode, all the clocks are stopped and the device comes to a halt. all activity is comple tely stopped and the power consumption is reduced to the lowest possible value. in this state the ale and psen pins are pulled low. the port pins output the values held by their respective sfrs. pcon ($87h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 smod gf1 gf0 pd idle smod: this bit set to ?1? to make the uart baud-rate double. gf1: general-purpose flag bit. gf0: general-purpose flag bit. pd: when set to ?1? , the mcu will into power down mode idle: when set to ?1? , the mcu will into idle mode sconf ($bfh) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 pdwue ispe ome alei pdwue: when set to ?1?, enable the pdwu function. ispe: when set to ?1?, enable the isp function. ie ($a8h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ea et2 es0 et1 ex1 et0 ex0 ea: when set to ?1?, enable interrupt global. et2: when set to ?1?, enable timer2 interrupt. es0: when set to ?1?, enable uart interrupt. et1: when set to ?1?, enable timer1 interrupt. ex1: when set to ?1?, enable external interrupt 1. et0: when set to ?1?, enable timer0 interrupt. ex0: when set to ?1?, enable external interrupt 0. ie1 ($a9h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 etwsi
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 25 etwsi: when set to ?1?, enable the twsi interrupt. ifr ($aah) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 twsiif twsiif: when set to ?1?, enable the twsi interrupt flag. tcon ($88h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 tf1: timer 1 overflow flag. tr1: timer 1 run control bit. tf0: timer 0 overflow flag. tr0: timer 0 run control bit. ie1: external interrupt 1 edge flag. it1: interrupt 1 type control bit. ie0: external interrupt 0 edge flag. it0: interrupt 0 type control bit. tmod ($89h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 gate c/t m1 m0 gate c/t m1 m0 note: high 4 bits are timer1, low 4 bits are timer0. gate: gating control when set. timer/counter ?x? is enabled only while ?intx? pin is high and ?trx? control pin is set. when cleared timer ?x? is en abled whenever ?trx? control bit is set. c/t: timer or counter selector cleared for timer operati on (input from in=ternal system clock.) set for counter operation (input from ?tx? input pin). m1 m0 mode operating 0 0 0 13-bit timer mode. 8-bit timer/counter thz with tlx as 5-bit prescaler. 0 1 1 16-bit timer mode. 16-bit timer/counters thx and tlx are cascaded; there is no prescaler. 1 0 2 8-bit auto reload. 8-bit auto-reload timer/counter thx holds a value which is to be reloaded into tlx each time it overflows. 1 1 3 split timer mode (timer 0) tl0 is an 8-bit timer/counter contro lled by the standard timer 0 control bits. th0 is an 8-bit timer only controlled by timer 1 control bits. (timer 1) timer/counter 1 stopped. ip ($b8h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 pt2 ps0 pt1 px1 pt0 px0 pt2: timer2 interrupt priority. ps0: uart interrupts priority. pt1: timer1 interrupt priority. px1: external interrupt 1 priority. pt0: timer0 interrupt priority.
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 26 px0: external interrupt 0 priority. ip1($b9h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ptwsi ptwsi: when set to ?1?, enable the twsi interrupt priority. the priority structure and vect or locations of interrupts: source flag priority level vector address external interrupt 0 ie0 1(highest) 03h timer 0 overflow tf0 2 0bh external interrupt 1 ie1 3 13h timer 1 overflow tf1 4 1bh uart interrupt ri+ti 5 23h timer 2 overflow tf2+exf2 6 2bh twsi rxif + txif+ tfif+ nakif 7 3bh t2mod ($c9h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 t2oe dcen t2oe: timer2 clock output enable bit. if set to 1, the timer2 clock will output to p1.0. dcen: down count enable. when set this bit then allo ws timer2 to be configured as an up/down counter. application reference xi x2 SM5964A x'tal r c1 c2 note: oscillation circuit may differs with different crystal or ceramic resonator in higher oscillation frequency which was due to ea ch crystal or ceramic resonator has its own characteristics. user should check with the crystal or ceramic resonator manufacturer for appropriate val ue of external components. valid for SM5964A x'tal 3mhz 6mhz 9mhz 12mhz c1 30 pf 30 pf 30 pf 22 pf c2 30 pf 30 pf 30 pf 22 pf r open open open open x'tal 16mhz 25mhz c1 30 pf 15 pf c2 30 pf 15 pf r open open
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 27 pdip 40l (600mil) package informatio n note: 1. refer to jedec std.ms-011(ac). 2. dimension d and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. d and e1 are maximum plastic body size dimension include mold mismatch. 3. dimension b3 does not include dambar protrusion. allowable dambar protrusion shall not cause the l ead width to exceed the maximum b3 dimension by more than 0.2mm . dimension in mm dimension in mil symbol min nom max min nom max a1 0.254 10 a2 3.683 3.810 3.937 145 150 155 b 0.356 0.500 0.660 14 20 26 b1 0.356 0.457 0.508 14 18 22 b2 1.016 1.270 1.524 40 50 60 b3 1.016 1.321 1.626 40 52 64 c 0.203 0.254 0.432 8 10 17 c1 0.203 0.254 0.356 8 10 14 d 52.07 52.2 52.32 2050 2055 2060 e 14.99 15.24 15.49 590 600 610 e1 13.69 13.87 13.94 539 546 549 e 2.540 100 eb 15.75 16.26 16.76 620 640 660 l 2.921 3.302 3.683 115 130 145 s 1.727 1.981 2.235 68 78 88 q1 1.651 1.778 1.905 65 70 75 0 10 0 10
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 28 plcc 44l package informatio n unit symbol inch(ref) mm(base) a 0.180(max) 4.572(max) a1 0.024 0.005 0.52 0.14 a2 0.105 0.005 2.667 0.127 b 0.018 + 0.004 - 0.002 0.457 + 0.102 - 0.051 b1 0.028 + 0.004 - 0.002 0.711 + 0.102 - 0.051 c 0.010(typ) 0.254(typ) d 0.690 0.010 17.526 0.254 d1 0.653 0.003 16.586 0.076 d2 0.610 0.020 15.494 0.508 e 0.690 0.010 17.526 0.254 e1 0.653 0.003 16.586 0.076 e2 0.610 0.010 15.494 0.254 e 0.050(typ) 1.270(typ) y 0.003(max) 0.076(max) 0~5 0~5
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 29 qfp 44l(10x10x2.0mm) package information note: 1. refer to jedc std.ms-022(ab). 2. dimension e1 do not include mold protrusion. allowable protrusion is 0.25mm per side.e1 are maximum plastic body size dimension include mold mismatch . 3. dimension b does not include dambar protrusion .allowable dambar protrusion shall not cause the lead width to exceed the maximum b3 dimension by more than 0.1 mm. dimension in mm dimension in mil symbol min nom max min nom max a 2.45 964 a1 0.05 0.15 0.25 2.1 6.0 9.6 a2 1.90 2.00 2.10 74.8 78.7 82.7 b 0.29 0.32 0.45 11.4 12.6 17.7 b1 0.29 0.30 0.41 11.4 11.8 16.1 c 0.11 0.17 0.23 4.3 6.7 9.1 c1 0.11 0.15 0.19 4.3 5.9 7.5 e 13.00 13.20 13.40 512 520 528 e1 9.90 10.00 10.10 390 394 398 e 0.800 31.5 l 0.73 0.88 1.03 28.7 34.6 40.6 l1 1.50 1.60 1.70 59.1 63.0 66.9 y 0.076 3 0 7 0 7
syncmos technologies international, inc. SM5964A 8-bit micro-controller with 64kb isp flash & twsi & pwm & 1kb ram embedded specifications subject to change without notice contact your sales representati ves for the most re cent information. ver 2.3 SM5964A 10/2006 30 e mcu writer list company contact info programmer model number advantech 7f, no.98, ming-chung rd., shin-tien city, taipei, taiwan, roc web site: http://www.aec.com.tw tel:02-22182325 fax:02-22182435 e-mail: aecwebmaster@advantech.com.tw lab tool - 48xp (1 * 1) lab tool - 848 (1*8) hi-lo 4f, no. 20, 22, ln, 76, rui guang rd., nei hu, taipei, taiwan, roc. web site: http://www.hilosystems.com.tw tel:02-87923301 fax:02-87923285 e-mail: support@hilosystems.com.tw all - 11 (1*1) gang - 08 (1*8) leap 6th f1-4, lane 609, chunghsin rd., sec. 5, sanchung, taipei hsien, taiwan, roc web site: http://www.leap.com.tw tel:02-29991860 fax:02-29990015 e-mail: service@leap.com.tw leap-48 (1*1) su - 2000 (1*8) xeltek electronic co., ltd 338 hongwu road, nanjing, china 210002 web site: http://www.xeltek-cn.com tel:+86-25-84408399, 84543153-206 e-mail: xelclw@jlonline.com, xelgbw@jlonline.com superpro/2000 (1*1) superpro/280u (1*1) superpro/l+(1*1)

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