BF1009SW 1 jun-28-2001 silicon n-channel mosfet tetrode for low noise, high gain controlled input stages up to 1ghz operating voltage 9v integrated bias network vps05605 4 2 1 3 eha07215 gnd g1 g2 drain agc hf input hf output +dc esd : e lectro s tatic d ischarge sensitive device, observe handling precaution! type marking pin configuration package BF1009SW jls 1 = d 2 = s 3 = g1 4 = g2 sot343 maximum ratings parameter symbol value unit v ds 12 drain-source voltage v ma 25 i d continuos drain current gate 1/gate 2 peak source current 10 i g1/2sm + v g1se 3 gate 1 (external biasing) v mw p tot total power dissipation , t s 76 c 200 storage temperature c -55 ... 150 t stg t ch 150 channel temperature thermal resistance channel - soldering point 1) r thchs 280 k/w 1 for calculation of r thja please refer to application note thermal resistance note: it is not recommended to apply external dc-voltage on gate 1 in active mode.
BF1009SW 2 jun-28-2001 electrical characteristics at t a = 25c, unless otherwise specified. parameter symbol values unit min. typ. max. dc characteristics drain-source breakdown voltage i d = 300 a, v g1s = 0 v, v g2s = 0 v v - v (br)ds - 16 gate 1 - source breakdown voltage + i g1s = 10 ma, v g2s = 0 v, v ds = 0 v - 12 + v (br)g1ss 8 gate 2 source breakdown voltage i g2s = 10 ma, v g1s = 0 v, v ds = 0 v - 16 10 v (br)g2ss gate 1 source current v g1s = 6 v, v g2s = 0 v - - a 60 + i g1ss gate 2 source leakage current v g2s = 8 v, v g1s = 0 v, v ds = 0 v i g2ss - - na 50 i dss - 500 a - drain current v ds = 9 v, v g1s = 0 , v g2s = 6 v i dso 10 14 operating current (selfbiased) v ds = 9 v, v g2s = 6 v ma 19 v g2s(p) - 0.9 - v gate 2-source pinch-off voltage v ds = 9 v, i d = 100 a ac characteristics forward transconductance (self biased) v ds = 9 v, v g2s = 6 v g fs 26 30 - ms gate 1-input capacitance (self biased) v ds = 9 v, v g2s = 6 v, f = 1 mhz c g1ss - 2.1 2.7 pf output capacitance (self biased) v ds = 9 v, v g2s = 6 v, f = 1 mhz c dss - 0.9 - power gain (self biased) v ds = 9 v, v g2s = 6 v, f = 800 mhz g ps 18 22 - db noise figure (self biased) v ds = 9 v, v g2s = 6 v, f = 800 mhz f 800 - 1.4 - gain control range (self biased) v ds = 9 v, vg2s = 6 ... 0v, f = 800 mhz g ps 40 50 -
BF1009SW 3 jun-28-2001 total power dissipation p tot = f ( t s ) 0 20 40 60 80 100 120 c 150 t s 0 50 100 150 200 mw 300 p tot drain current i d = f ( v g2s ) 0.0 1.0 2.0 3.0 4.0 v 6.0 v g2s 0 1 2 3 4 5 6 7 8 9 10 11 12 ma 15 i d forward transfer admittance | y 21 | = f ( v g2s ) 0.0 1.0 2.0 3.0 4.0 v 6.0 v g2s 0 2 4 6 8 10 12 14 16 18 20 22 24 ms 28 | y 21 | insertion power gain | s 21 | 2 = f ( v g2s ) 0.0 1.0 2.0 3.0 4.0 v 6.0 v g2s -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 db 10 | s 21 | 2
BF1009SW 4 jun-28-2001 gate 1 input capacitance c g1ss = f ( v g2s ) f = 200mhz 0.0 1.0 2.0 3.0 4.0 v 6.0 v g2s 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 pf 3.0 c g1ss output capacitance c dss = f ( v g2s ) f = 200mhz 0.0 1.0 2.0 3.0 4.0 v 6.0 v g2s 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 pf 3.0 c dss
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