motorola version 3 coldfire core user? manual i table of contents paragraph page number title number section 1 introduction 1.1 why coldfire! .......................................................................................1-7 section 2 architectural overview section 3 version 3 core 3.1 introduction ...........................................................................................3-1 3.2 cf3core signals ..................................................................................3-1 3.3 coldfire master bus..............................................................................3-7 3.3.1 introduction .................................................................................3-7 3.3.2 m-bus signals ............................................................................3-7 3.3.2.1 m-bus read data (mrdata[31:0]) ................................3-8 3.3.2.2 m-bus address hold (mah) ...........................................3-8 3.3.2.3 m-bus transfer acknowledge (mta ) ..............................3-8 3.3.2.4 m-bus reset (mrsti ) ....................................................3-8 3.3.2.5 m-bus interrupt priority level (mipl[2:0]) ......................3-9 3.3.2.6 m-bus address (maddr[31:0]) ......................................3-9 3.3.2.7 m-bus address phase (map) .........................................3-9 3.3.2.8 m-bus data phase (mdp) ..............................................3-9 3.3.2.9 m-bus transfer size (msiz[1:0]) ....................................3-9 3.3.2.10 m-bus read/write (mrw) ............................................3-10 3.3.2.11 m-bus transfer type (mtt[1:0]) ..................................3-10 3.3.2.12 m-bus transfer modifier (mtm[2:0]) .............................3-10 3.3.2.13 m-bus write data (mwdata[31:0]) .............................3-11 3.3.3 m-bus operation ......................................................................3-11 3.3.3.1 basic bus cycles ..........................................................3-11 3.3.3.2 pipelined bus cycles ....................................................3-12 3.3.3.3 address and data phase interactions ..........................3-13 3.3.3.4 data size operations ....................................................3-16 3.3.3.5 line transfers ...............................................................3-17 3.3.3.6 bus arbitration ..............................................................3-20 3.3.3.7 interrupt support ...........................................................3-22 3.3.3.8 reset operation ............................................................3-23 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
table of contents (continued) paragraph page number title number ii version 3 coldfire core user? manual motorola section 4 v3 cpu 4.1 introduction ........................................................................................... 4-1 4.2 version 3 processor microarchitecture ................................................ 4-1 4.2.1 version 3 processor pipeline overview ..................................... 4-1 4.2.2 version 3 instruction fetch pipeline ........................................... 4-2 4.2.2.1 change of flow acceleration .......................................... 4-2 4.2.3 version 3 operand execution pipeline ...................................... 4-3 4.2.3.1 illegal opcode handling ................................................. 4-4 4.2.3.2 hardware multiply-accumulate (mac) and divide ......... 4-4 4.2.4 version 3 processor pipeline block diagrams and summary ... 4-5 4.3 coldfire processor programming model ............................................. 4-7 4.3.1 user programming model .......................................................... 4-7 4.3.1.1 data registers (d0 ?d7) ............................................... 4-8 4.3.1.2 address registers (a0 ?a6) .......................................... 4-8 4.3.1.3 stack pointer (a7, sp) .................................................... 4-8 4.3.1.4 program counter (pc) .................................................... 4-8 4.3.1.5 condition code register (ccr) ..................................... 4-8 4.3.2 mac programming model ........................................................ 4-10 4.3.2.1 accumulator (acc) ....................................................... 4-10 4.3.2.2 mask register (mask) ................................................. 4-10 4.3.2.3 mac status register (macsr) .................................... 4-10 4.3.3 supervisor programming model ............................................... 4-10 4.3.3.1 cache control register (cacr) ................................... 4-11 4.3.3.2 access control registers (acr0, acr1) ..................... 4-11 4.3.3.3 vector base register (vbr) ......................................... 4-11 4.3.3.4 ram base address register (rambar) ..................... 4-11 4.3.3.5 rom base address register (r0mbar) ..................... 4-11 4.3.3.6 status register (sr) ..................................................... 4-12 4.4 exception processing overview ......................................................... 4-12 4.5 exception stack frame definition ...................................................... 4-14 4.6 processor exceptions ........................................................................ 4-15 4.6.1 access error exception ............................................................ 4-15 4.6.2 address error exception .......................................................... 4-16 4.6.3 illegal instruction exception ..................................................... 4-16 4.6.4 privilege violation ..................................................................... 4-16 4.6.5 trace exception ....................................................................... 4-16 4.6.6 debug interrupt ........................................................................ 4-17 4.6.7 rte and format error exceptions ........................................... 4-17 4.6.8 trap instruction exceptions ................................................... 4-18 4.6.9 non-supported instruction exceptions ..................................... 4-18 4.6.10 interrupt exception ................................................................... 4-18 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
table of contents (continued) paragraph page number title number motorola version 3 coldfire core user? manual iii 4.6.11 fault-on-fault halt ....................................................................4-18 4.6.12 reset exception .......................................................................4-18 4.7 integer data formats .........................................................................4-19 4.8 organization of data in registers ......................................................4-19 4.8.1 organization of integer data formats in registers ..................4-19 4.8.2 organization of integer data formats in memory ....................4-20 4.9 addressing mode summary ...............................................................4-21 4.10 instruction set summary ....................................................................4-22 section 5 processor-local memories 5.1 local memory overview .......................................................................5-1 5.2 the two-stage pipelined local bus (k-bus) .......................................5-3 5.3 unified cache .......................................................................................5-5 5.3.1 cache organization ....................................................................5-6 5.3.2 cache operation ........................................................................5-7 5.3.3 cache control register (cacr) ..............................................5-11 5.3.4 access control registers .........................................................5-13 5.3.5 cache management .................................................................5-15 5.3.6 caching modes ........................................................................5-16 5.3.6.1 cachable accesses ......................................................5-17 5.3.6.1.1 writethrough mode ...................................................................5-17 5.3.6.1.2 copyback mode .......................................................................5-17 5.3.6.2 cache-inhibited accesses ............................................5-17 5.3.7 cache protocol .........................................................................5-18 5.3.7.1 read miss .....................................................................5-19 5.3.7.2 write miss .....................................................................5-19 5.3.7.3 read hit ........................................................................5-19 5.3.7.4 write hit ........................................................................5-19 5.3.8 cache coherency .....................................................................5-19 5.3.9 memory accesses for cache maintenance ..............................5-19 5.3.10 cache filling .............................................................................5-20 5.3.11 cache pushes ..........................................................................5-20 5.3.12 push and store buffers ............................................................5-20 5.3.12.1 push and store buffer bus operation ..........................5-21 5.3.13 cache operation summary ......................................................5-21 5.4 processor-local random access memory (ram) .............................5-24 5.4.1 ram operation .........................................................................5-24 5.4.2 ram programming model ........................................................5-24 5.4.3 ram initialization ......................................................................5-27 5.4.4 ram initialization code ............................................................5-27 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
table of contents (continued) paragraph page number title number iv version 3 coldfire core user? manual motorola 5.4.5 ram power management ........................................................ 5-27 5.5 processor-local read-only memory (rom) ..................................... 5-29 5.5.1 rom operation ........................................................................ 5-29 5.5.2 rom programming model ....................................................... 5-29 5.5.3 rom power management ........................................................ 5-32 5.6 interactions between the kbus memories ........................................ 5-32 section 6 debug support 6.1 signal description ................................................................................ 6-2 6.1.1 breakpoint (bkpt) ..................................................................... 6-2 6.1.1.1 rev. a functionality ........................................................ 6-2 6.1.1.2 rev. b enhancement ...................................................... 6-2 6.1.2 debug data (ddata[3:0]) ......................................................... 6-2 6.1.3 development serial clock (dsclk) .......................................... 6-2 6.1.4 development serial input (dsi) ................................................. 6-3 6.1.5 development serial output (dso) ............................................. 6-3 6.1.6 processor status (pst[3:0]) ...................................................... 6-3 6.1.7 processor status clock (pstclk) ............................................ 6-3 6.2 real-time trace support...................................................................... 6-4 6.2.1 processor status signal encoding ............................................. 6-4 6.2.1.1 continue execution (pst = $0) ...................................... 6-4 6.2.1.2 begin execution of an instruction (pst = $1) ................ 6-4 6.2.1.3 entry into user mode (pst = $3) ................................... 6-4 6.2.1.4 begin execution of pulse/wddata instr. (pst = $4) . 6-4 6.2.1.5 begin execution of taken branch (pst = $5) ................ 6-5 6.2.1.6 begin execution of rte instruction (pst = $7) ............. 6-6 6.2.1.7 begin data transfer (pst = $8 - $b) ............................. 6-6 6.2.1.8 exception processing (pst = $c) .................................. 6-6 6.2.1.9 emulator mode exception processing (pst = $d) ........ 6-6 6.2.1.10 processor stopped (pst = $e) ...................................... 6-6 6.2.1.11 processor halted (pst = $f) ......................................... 6-6 6.3 background-debug mode (bdm) ......................................................... 6-6 6.3.1 cpu halt .................................................................................... 6-7 6.3.2 bdm serial interface .................................................................. 6-8 6.3.2.1 receive packet format .................................................. 6-9 6.3.2.2 transmit packet format ............................................... 6-10 6.3.3 bdm command set ................................................................. 6-10 6.3.3.1 bdm command set summary ..................................... 6-10 6.3.3.2 coldfire bdm commands ............................................ 6-11 6.3.3.3 command sequence diagram ..................................... 6-12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
table of contents (continued) paragraph page number title number motorola version 3 coldfire core user? manual v 6.3.3.4 command set descriptions ..........................................6-14 6.3.3.4.1 read a/d register (rareg/rdreg) .....................................6-14 6.3.3.4.2 write a/d register (wareg/wdreg) ....................................6-15 6.3.3.4.3 read memory location (read) ...............................................6-16 6.3.3.4.4 write memory location (write) .............................................6-18 6.3.3.4.5 dump memory block (dump) ..................................................6-20 6.3.3.4.6 fill memory block (fill) ..........................................................6-22 6.3.3.4.7 resume execution (go) ..........................................................6-24 6.3.3.4.8 no operation (nop) .................................................................6-25 6.3.3.4.9 synchronize pc to the pst/ddata lines(sync_pc) ...........6-26 6.3.3.4.10 read control register (rcreg) .............................................6-26 6.3.3.4.11 write control register (wcreg) .............................................6-28 6.3.3.4.12 read debug module register (rdmreg) ...............................6-29 6.3.3.4.13 write debug module register (wdmreg) ..............................6-29 6.3.3.4.14 unassigned opcodes ...............................................................6-30 6.4 real-time debug support ..................................................................6-31 6.4.1 theory of operation .................................................................6-31 6.4.1.1 emulator mode .............................................................6-32 6.4.1.2 debug module hardware ..............................................6-33 6.4.1.2.1 reuse of debug module hardware (rev. a) ............................6-33 6.4.1.2.2 the new debug module hardware (rev. b) ............................6-33 6.4.2 programming model .................................................................6-34 6.4.2.1 address breakpoint registers (ablr, abhr) .............6-34 6.4.2.2 address attribute trigger register (aatr) .............6-35 6.4.2.3 program counter breakpoint register (pbr, pbmr) ..6-38 6.4.2.4 data breakpoint register (dbr, dbmr) ......................6-38 6.4.2.5 trigger definition register (tdr) .................................6-40 6.4.2.6 configuration/status register (csr) ............................6-42 6.4.2.7 bdm address attribute register (baar) ......................6-45 6.4.3 concurrent bdm and processor operation ..............................6-46 6.4.4 motorola-recommended bdm pinout ......................................6-47 section 7 test 7.1 introduction ...........................................................................................7-1 7.2 cf3core design-for-test .....................................................................7-1 7.2.1 cf3core test goals ..................................................................7-1 7.2.2 cf3core test features ..............................................................7-1 7.2.2.1 functional mode with debug ..........................................7-2 7.2.2.2 the scan modes .............................................................7-2 7.2.2.3 the cpu lock mode ......................................................7-2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
table of contents (continued) paragraph page number title number vi version 3 coldfire core user? manual motorola 7.2.3 alternate, non-covered fault models ........................................ 7-2 7.3 cf3tw test architecture and test interface ....................................... 7-2 7.3.1 access to the cf3core internal scan architecture .................... 7-3 7.3.2 the cf3tw boundary scan architecture .................................. 7-5 7.3.2.1 cf3tw testing of non-core inputs ............................... 7-6 7.3.2.2 cf3tw testing of non-core outputs ............................ 7-9 7.4 chip-level integration & test issues ................................................. 7-12 7.4.1 chip-level test program goals ............................................... 7-12 7.4.2 cf3core integration connections ............................................ 7-13 7.4.3 cf3core scan connections .................................................... 7-14 appendix a cf3core interface timing constraints appendix b instruction execution times b.1 timing assumptions ..............................................................................b-i b.2 move instruction execution times ..................................................... b-ii b.3 standard one operand instruction execution times .......................... b-iii b.4 standard two operand instruction execution times ......................... b-iv b.5 miscellaneous instruction execution times ........................................b-v b.6 branch instruction execution times .................................................... b-vi appendix c processor status, ddata definition c.1 user instruction set ...............................................................................c-i c.2 supervisor instruction set ...................................................................c-iv appendix d local memory connections f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola version 3 coldfire core user? manual i list of illustrations figure page number title number section 2 architectural overview 2-1. generic coldfire system block diagram......................................................... 2-2 2-2. version 3 coldfire processor block diagram.................................................. 2-3 section 3 version 3 core 3-1. generic version 3 coldfire block diagram ..................................................... 3-2 3-2. basic read and write cycles......................................................................... 3-12 3-3. pipelined read and write .............................................................................. 3-13 3-4. address hold followed by 1- and 0-wait state cycles.................................. 3-15 3-5. map and mah generated mid-data phase................................................... 3-15 3-6. mah generation for 1x clock mode.............................................................. 3-16 3-7. line access read with zero wait states ....................................................... 3-18 3-8. line access read with 1 wait state .............................................................. 3-19 3-9. line access write with zero wait states ....................................................... 3-19 3-10. line access write with one wait state.......................................................... 3-20 3-11. multiplexed m-bus structure .......................................................................... 3-21 3-12. multiplexed m-bus operation......................................................................... 3-22 section 4 v3 cpu 4-1. coldfire multiply-accumulate functionality diagram....................................... 4-4 4-2. version 3 coldfire pipeline diagram ............................................................... 4-6 4-3. user programming model ................................................................................ 4-8 4-4. condition code register (ccr)....................................................................... 4-9 4-5. mac unit user programming model.............................................................. 4-10 4-6. supervisor programming model..................................................................... 4-11 4-7. status register (sr) ...................................................................................... 4-12 4-8. exception stack frame form......................................................................... 4-14 4-9. organization of integer data formats in data registers ............................... 4-19 4-10. organization of integer data formats in address registers.......................... 4-20 4-11. memory operand addressing ........................................................................ 4-21 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
list of illustrations (continued) figure page number title number ii version 3 coldfire core user? manual motorola section 5 processor-local memories 5-1. coldfire core synchronous memory interface............................................... 5-1 5-2. synchronous memory timing diagram............................................................ 5-2 5-3. synchronous memory interface block diagram............................................... 5-2 5-4. version 3 unified cache block diagram.......................................................... 5-5 5-5. cf3core generic block diagram .................................................................... 5-7 5-6. cache organization and line format (32 kbyte cache size shown)............... 5-8 5-7. cache line format .......................................................................................... 5-8 5-8. caching operation (32 kbyte cache size shown)............................................ 5-9 5-9. ....................................................................................................................... 5-11 5-10. ....................................................................................................................... 5-13 5-11. ....................................................................................................................... 5-15 5-12. ....................................................................................................................... 5-16 5-13. cache line state diagrams ........................................................................... 5-23 5-14. ram base address register (rambar) ...................................................... 5-25 5-15. rom base address register (rombar) ...................................................... 5-29 section 6 debug support 6-1. processor/debug module interface ................................................................. 6-2 6-2. example pst/ddata diagram ....................................................................... 6-5 6-3. bdm signal sampling ...................................................................................... 6-9 6-4. bdm serial transfer ........................................................................................ 6-9 6-5. receive bdm packet ....................................................................................... 6-9 6-6. transmit bdm packet .................................................................................... 6-10 6-7. command sequence diagram....................................................................... 6-14 6-8. sync_pc reg command............................................................................ 6-26 6-9. debug programming model ........................................................................... 6-34 6-10. address breakpoint low register (ablr)..................................................... 6-35 6-11. address breakpoint high register (abhr) ................................................... 6-35 6-12. address attribute trigger register (aatr) .................................................... 6-36 6-13. program counter breakpoint register (pbr) ................................................ 6-38 6-14. program counter breakpoint mask register (pbmr) ................................... 6-38 6-15. data breakpoint register (dbr).................................................................... 6-39 6-16. data breakpoint mask register (dbmr) ....................................................... 6-39 6-17. trigger definition register (tdr) .................................................................. 6-40 6-18. configuration/status register (csr) ............................................................. 6-42 6-19. bdm address attribute register (baar) ....................................................... 6-46 6-20. recommended bdm connector .................................................................... 6-47 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
list of illustrations (continued) figure page number title number motorola version 3 coldfire core user? manual iii section 7 test 7-1. example registered cf3tw architecture ....................................................... 7-4 7-2. cf3tw to non-core input scan stuck-at vector example ............................. 7-7 7-3. cf3tw to non-core delay scan vector example .......................................... 7-8 7-4. non-core to cf3tw input scan stuck-at vector example ........................... 7-10 7-5. non-core to cf3tw input scan delay vector example ............................... 7-11 7-6. two allowed methods of mtmod distribution.................................................. 7-13 7-7. chip-level cf3core parallel scan input connection .................................... 7-15 7-8. chip-level cf3core parallel scan output connection ................................. 7-15 7-9. chip-level cf3core parallel scan input connection .................................... 7-16 7-10. chip-level cf3core parallel scan output connection ................................. 7-16 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola version 3 coldfire core user? manual i list of tables table page number title number section 3 version 3 core 3-1. cf3core pin specification ..............................................................................3-4 3-2. m-bus signal summary .................................................................................. 3-8 3-3. m-bus interrupt priority level encodings........................................................ 3-9 3-4. m-bus transfer size encodings - 32-bit data bu ........................................... 3-9 3-5. m-bus transfer type encodings................................................................... 3-10 3-6. m-bus transfer modifier encodings for mtt = 0- .........................................3-10 3-7. m-bus transfer modifier encodings for mtt = 10 ........................................3-10 3-8. m-bus transfer modifier encodings for mtt = 11 ........................................3-11 3-9. processor operand representation.............................................................. 3-16 3-10. mrdata requirements for read transfers................................................. 3-17 3-11. mwdata bus requirements for write transfers......................................... 3-17 3-12. allowable line access patterns .................................................................... 3-18 section 4 v3 cpu 4-1. movec register map................................................................................... 4-11 4-2. exception vector assignments ..................................................................... 4-14 4-3. format field encoding .................................................................................. 4-15 4-4. fault status encodings ................................................................................. 4-15 4-5. integer data formats .................................................................................... 4-19 4-6. effective addressing modes and categories ................................................ 4-22 4-7. notational conventions ................................................................................ 4-22 4-8. instruction set summary.............................................................................. 4-24 section 5 processor-local memories 5-1. synchronous memory truth table (sampled @ positive edge of clk) ............ 5-3 5-2. cf3core unified cache sizes and configurations ......................................... 5-7 5-3. cache line state transitions ....................................................................... 5-22 5-4. ram base address bits................................................................................ 5-25 5-5. examples of typical rambar settings........................................................ 5-28 5-6. rom base address bits ............................................................................... 5-29 5-7. examples of typical rombar settings ....................................................... 5-31 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
list of tables (continued) figure page number title number ii version 3 coldfire core user? manual motorola section 6 debug support 6-1. processor status encoding............................................................................. 6-3 6-2. cpu-generated message encoding............................................................. 6-10 6-3. bdm command summary ............................................................................ 6-11 6-4. bdm size field encoding ............................................................................. 6-12 6-5. control register map .................................................................................... 6-27 6-6. definition of drc encoding - read ............................................................... 6-29 6-7. definition of drc encoding - write ............................................................... 6-30 6-8. ddata[3:0], csr[31:28] breakpoint response........................................... 6-31 6-9. shared bdm/breakpoint hardware............................................................... 6-33 6-10. access size and operand data location ..................................................... 6-40 appendix b instruction execution times b-1. misaligned operand references ................................................................... b-ii b-2. move byte and word execution times........................................................... b-ii b-3. move long execution times .......................................................................... b-ii b-4. mac move long instruction execution times ............................................... b-iii b-5. one operand instruction execution times .................................................... b-iii b-6. two operand instruction execution times .................................................... b-iv b-7. miscellaneous instruction execution times .....................................................b-v b-8. general branch instruction execution times................................................. b-vi b-9. bra, bcc instruction execution times .......................................................... b-vi b-10. another table of bcc instruction execution times ....................................... b-vii f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola version 3 coldfire core user? manual 1-1 section 1 introduction this manual summarizes the operation and use of the version 3 coldfire processor complex reference design. the processor complex design includes the processor core, the debug module, high-speed processor local bus and associated memory controllers plus interface bus controller. collectively, this reference design is known as cfxref, where x defines the appropriate version of the microarchitecture. this document details the microarchitecture, functionality, core interface and test strategy for the version 3 coldfire reference design. specific deployments of the cf3ref design are named by a notation which identifies the presence of optional functional blocks. as examples, the cf3 design includes the basic cf3ref design without the optional multiply-accumulate unit (mac), while the cf3m implementation includes the mac unit. the coldfire microprocessor architecture provides new levels of price and performance to the emerging cost-sensitive, high-volume embedded markets, especially in the area of consumer products. based on the concept of a variable-length risc technology, coldfire combines the architectural simplicity of conventional 32-bit risc with a memory-saving, variable-length instruction set. in defining the coldfire architecture for embedded processing applications, motorola has incorporated a risc-based processor design for peak performance and a simplified version of the variable-length instruction set found in the m68000 family for maximum code density. the result is a family of 32-bit microprocessors ideally suited for those embedded applications requiring high performance in a small core size. the coldfire performance roadmap, announced in 3q96, defines a series of microarchitecture versions, which when coupled with improved process technology provides increasing levels of performance, up to 300 dhrystone 2.1 mips by the year 2001. the version 3 processor represents the early-midpoint of the roadmap providing a performance of approximately 70 dhrystone 2.1 mips in a 90 mhz implementation using 0.35 micron semiconductor process technology. this performance metric can also be expressed as 0.78 dhrystone 2.1 mips per mhz for the version 3 coldfire core, assuming a cache size of 4 kbytes or larger. 1.1 why coldfire! the coldfire family of 32-bit microprocessors provides balanced system solutions to a variety of embedded markets. the following list details a number of the basic philosophies applicable to all coldfire designs: the instruction set architecture (isa) and resulting code density directly translate in lower memory costs, both for internal and external memory subsystems f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
introduction 1-2 version 3 coldfire core user? manual motorola small, fully-synthesizable processor complexes - developments are on track with performance roadmap reaching 300 mips by 2001 - 100% synthesizable design and use of compiled memory arrays plus function-level parameterization allow system designers to easily define cpu configurations - can easily move to any process technology targeting different operating voltages and frequencies - supports cost-effective integration capabilities modular system architecture - a hierarchy of system buses provides layers of bandwidth and supports an efficient partitioning of the optional, on-chip modules - cfxref designs support configurable processor-local memories, e.g., cache, ram, rom, with sizes from [0 - 32 kbytes] - standard motorola peripheral bus promotes reuse of synthesizable modules full-featured debug module - common debug architecture does not require traditional connection to external bus, and yet provides background debug mode (bdm) capabil- ities plus real-time trace and debug functionality - standard interface used in motorola parts and completely embedded, customer-specific designs using 3rd-party developer tools bridge from the 19-year m68000 family legacy - reuse of 68k assembly language simplified through conversion tool - leverages system designer and programmer knowledge base - leverages mature 3rd-party developer tools f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola version 3 coldfire core user?s manual 2-1 section 2 architectural overview the following block diagram depicts the standard coldfire microprocessor configuration. the hierarchical bus structure (processor-local, master, slave and external buses) provides varying layers of data bandwidth and supports an efficient partitioning of the optional, on-chip modules. this hierarchy of buses are also known by their abbreviated names: the processor-local bus is the k-bus, the master bus is the m-bus, the slave bus is the s-bus and finally, the external bus is the e-bus. the modular system architecture is readily apparent. the coldfire processor complex reference design is defined by the cfxcore level of hierarchy. the cfxcorekmem boundary includes the core design plus the required processor-local memories for a given design. within the cfxcore, the processor is connected via a local, high-speed bus to a number of memory controllers and a bus controller. the processor-local memories include cache storage, as well as blocks of ram and rom. the memory controllers contained within the cfxcore design all support a range of sizes, allowing the system designer the ability to specify the optimum memory organization for a given application. transfers on the processor-local bus are controlled by the k2m bus controller, which is also responsible for initiation and control of all accesses onto the next-level system bus, the master bus. the processor-local bus is designed to provide a maximum amount of bandwidth from these high-speed memories to support the processor?s efficient execution of instructions. the cfxcore plus all other bus masters are connected at the microprocessor level via the master bus, which provides the primary interface between the coldfire core and the other system-level components. any device which can initiate bus cycles is typically connected to the master bus. example modules include direct-memory access devices (dma), or another coldfire processor complex. the master bus is typically connected to a system bus controller (sbc) which provides two interfaces: one to a simple, on-chip slave bus, and another to an application-specific external bus. the slave bus generally is connected to any number of standard peripheral modules, including functions like timers, uarts and other serial communication devices, parallel ports, etc. the use of a standard motorola-defined bus protocol promotes the reuse of these synthesizable modules. the specific implementation and protocol details of the external bus generally vary widely, depending on system requirements. in many implementations, the process technology may allow the processor complex to operate at a higher frequency compared to the rest of the microprocessor. the cfxcore design supports this notion of multiple clock domains , and features a standard implementation which allows the core to be operated at any integer multiplier (n = 1,2,3,...) faster than the rest of the design. for multiple clock domains, the boundary is the master f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
architectural overview 2-2 version 3 coldfire core user?s manual motorola bus, i.e., the processor complex operates at the higher frequency, while the master bus and the remainder of the microprocessor operate at the slower speed. this design approach provides a well-defined and easy-to-use clock boundary, which simplifies interface design and timing and eases production test complications. this topic is covered in more detail in section 3: coldfire core. the overall coldfire implementation strategy of 100% synthesizable designs and use of compiled memory arrays coupled with the modular system architecture allows easy movement to any process technology, and provides cost-effective integration capabilities while targeting a variety of operating voltages and/or frequencies. figure 2-1. generic coldfire system block diagram c system bus controller slave module slave module master module slave-bus external-bus master-bus debug cf vx k2m cache kram processor-bus kram krom cache krom cache ctrl ctrl ctrl mem array mem array tag array data array cpu cfxcorekmem cfxcore m a v d i f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
architectural overview motorola version 3 coldfire core user?s manual 2-3 all coldfire processor cores consist of two independent, decoupled pipeline structures to maximize performance while minimizing core size. the instruction fetch pipeline (ifp) prefetches instructions, while the operand execution pipeline (oep) decodes the instructions, fetches the required operands and then executes the specified functions. since the ifp and oep are decoupled by an instruction buffer that serves as a fifo queue, the ifp can prefetch instructions in advance of their actual use by the oep, thereby minimizing time stalled waiting for the variable-length instructions. consider the following version 3 coldfire processor block diagram: figure 2-2. version 3 coldfire processor block diagram ia generation instruction fetch cycle 1 fifo instruction buffer decode & select, operand fetch address generation, execute ifp oep cf3 processor kwdata instruction fetch cycle 2 instruction early decode iag ic1 ic2 ied ib dsoc agex krdata kaddr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
architectural overview 2-4 version 3 coldfire core user?s manual motorola here the processor?s non-harvard architecture is readily apparent. the processor?s connection to the local bus (k-bus) is defined by the reference address ( kaddr ), and two unidirectional data buses, krdata (read data) and kwdata (write data), which transfer instructions and operands into the processor core, or to the destination memories. this structure minimizes the core size without compromising performance to a large degree. the ifp is a four-stage pipeline for prefetching instructions and partially decoding them, while the oep is implemented in a two-stage pipeline featuring a traditional risc datapath with a dual-read-ported register file feeding an arithmetic/logic unit. subsequent sections provide further details on the microarchitecture of the version 3 coldfire processor complex, along with a description of the master bus interface. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola version 3 coldfire core user?s manual 3-1 section 3 version 3 core 3.1 introduction this section details the cf3core interface and provides an overview of the functional operation of the master bus (m-bus). note that the cf3core pin naming definition uses all lower case signal names, due to various tool limitations. however, most of the documentation presented in this manual, except for section 3.2: cf3core signals , follows a convention with upper case names. it is important to note that these conventions are meant to be equivalent, i.e., port signal xyz is the same as signal xyz . additionally, the use of a b suffix in the pin naming definition indicates an active-low signal, while the rest of the documentation uses an overbar, i.e., signal xyzb ( xyz bar) is the same as xyz . 3.2 cf3core signals this section details the pin name det nition and pin order f or the v ersion 3 coldfire ref erence design, specit cally , the cf3core design. this core is typically deplo y ed in a contgur ation where the processor-local memor ies are not included in the design to pro vide the system designer with the ability to cont gure and siz e those memor ies f or a giv en application. a gener ic b loc k diag r am of a v ersion 3 coldfire design is sho wn belo w , where the cf3core is represented by the shaded area. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
version 3 core 3-2 version 3 coldfire core user?s manual motorola figure 3- 1. generic version 3 coldfire block diagram this pin name and order ing det nition is used in the f ollowing views of the cf3core design: 1. behavioral rtl model used as input to synthesis and other implementation tools 2. c model used in encrypted form by the isd toolkit 3. gate-level netlist 4. bus functional model 5. interface structure for any cycle-based models it should be noted that the cf3core/kbus cont gurab le memor y interf ace is not actually modeled in the b us functional or cycle-based models . f or these models , the beha vior of this interface is described at a different abstraction level, b ut the pin list remains consistent across all views. system bus controller slave module slave module master module s-bus e-bus m-bus debug cf v3 k2m cache kram k-bus kram krom cache krom cache ctrl ctrl ctrl mem array mem array tag array data array cpu cf3core d i v m a c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
version 3 core motorola version 3 coldfire core user?s manual 3-3 the cf3core pin list can be broadly classited into the following groups: pins {1-41} cf3core outputs pins {1-9} m-bus outputs pins {10-15} debug outputs pins {16-21} test outputs pins {22-41} outputs to k-bus memories pins {42-88} cf3core inputs pins {42-46} m-bus inputs pins {47-50} debug and contguration inputs pins {51-57} test inputs pins {58-86} inputs from k-bus memories + memory contguration detnitions pins {87-88} clock inputs all k-bus memor ies are specit ed to be synchronous de vices , where the cf3core outputs are next-state values which are registered within the memory device. the pin specit cation and order ing f or the cf3core is detailed in the f ollo wing tab le. the use of a b suft x in the name indicates an activ e-low signal. bus widths are specit ed using a vector notation, while no entry in this column indicates a scalar (1-bit) signal. the following notes are applicable to certain cf3core signals: 1. in gener al, most of the m-bus and deb ug input signals are dr iv en directly into input capture registers within the cf3core design. the mahb and mtab signals are dr iv en into combinational logic bef ore being registered, so these inputs ha v e a g reater setup timing requirement. the mrdata[31:0] input capture register is only loaded b y the ter mination of an m-bus data phase. the miplb[2:0] and mrstib input signals are routed into free-r unning input capture registers, while the dsclk , dsdi and mbkptb input signals are routed into tw o levels of free- running registers which effectively serve as synchronizers. all m-bus and deb ug output signals are dr iv en directly from registers within the cf3core design. 2. for cf3core designs, it is necessary to output a clock signal from the microprocessor to the standard coldfire deb ug connector so that e xternal em ulators can correctly sample the pst[3:0] and ddata[3:0] output signals . this output cloc k, typically named pstclk , is a derivativ e of the processor? s cloc k signal and m ust be f or med e xter nal to the cf3core design using the following boolean equation: pstclk = clkfast & enpstclk where pstclk is the output signal, clkfast is the processor s cloc k signal and enpstclk is a logical enab le, dened by the user-programmed congur ation of the deb ug f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
version 3 core 3-4 version 3 coldfire core user?s manual motorola module within the cf3core design. table 3-1. cf3core pin specification no. type name bus width description 1 output maddr [31:0] m-bus address 2 output mtt [1:0] m-bus transfer type 3 output mtm [2:0] m-bus transfer moditer 4 output mrw m-bus read/write 5 output msiz [1:0] m-bus transfer size 6 output mwdata [31:0] m-bus write data 7 output mwdataoe m-bus output enable 8 output mapb m-bus address phase 9 output mdpb m-bus data phase 10 output cpustopb processor is stopped 11 output cpuhaltb processor is halted 12 output enpstclk pst/ddata clock enable 13 output pst [3:0] processor status 14 output ddata [3:0] debug data 15 output dsdo development system data output 16 output so [31:0] core parallel scan outputs 17 output tbso [3:0] test boundary scan outputs 18 output ucpaddr [31:4] u-cache push tag address for bist 19 output ucpdata [31:0] u-cache push data for bist 20 output rcpshdrtyk2 u-cache push written bit for bist 21 output rcpshvldk2 u-cache push valid bit for bist 22 output nsentb next-state u-cache tag enable 23 output nswrttb next-state u-cache tag write 24 output nswlvt [3:0] next-state u-cache tag write level 25 output nsinvat next-state u-cache tag invalidate all 26 output nsrowst [8:0] next-state u-cache tag address f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
version 3 core motorola version 3 coldfire core user?s manual 3-5 27 output nsaddrt [31:9] next-state u-cache tag data 28 output nssw next-state u-cache tag written bit 29 output nssv next-state u-cache tag valid bit 30 output nsendb next-state u-cache data enable 31 output nswrtdb [3:0] next-state u-cache data write level 32 output nswtbyted [3:0] next-state u-cache data byte write 33 output nsrowsd [10:0] next-state u-cache data address 34 output nscwrdata [31:0] next-state u-cache write data 35 output kramaddr [14:2] next-state kram address 36 output kramdi [31:0] next-state kram write data 37 output kramweb [3:0] next-state kram write enable 38 output kramcsb next-state kram chip select 39 output kramdata [31:0] next-state kram data for bist 40 output kromaddr [14:2] next-state krom address 41 output kromcsb next-state krom chip select 42 input mrdata [31:0] m-bus read data 43 input mtab m-bus transfer acknowledge 44 input mahb m-bus address hold 45 input miplb [2:0] m-bus interrupt request priority level 46 input mrstib m-bus reset 47 input dsclk development system clock 48 input dsdi development system data input 49 input mbkptb development system breakpoint 50 input en000iack enable 68000-style iack cycles 51 input bistplltest bist or pll test mode 52 input si [31:0] core parallel scan inputs 53 input se core parallel scan enable 54 input tbsi [3:0] test boundary scan inputs table 3-1. cf3core pin specification no. type name bus width description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
version 3 core 3-6 version 3 coldfire core user?s manual motorola 55 input tbsei test boundary scan enable - inputs 56 input tbseo test boundary scan enable - outputs 57 input tbte test boundary pcell test enable 58 input ucsz [2:0] encoded u-cache size 59 input ucnoif block instructions from u-cache 60 input ucnoop block operands from u-cache 61 input bistmode bist test mode 62 input bisttaglvl [1:0] bist tag level select 63 input bistdatalvl [1:0] bist data level select 64 input uctag3do [31:9] u-cache level 3 tag data output 65 input ucw3do u-cache level 3 written bit output 66 input ucv3do u-cache level 3 valid bit output 67 input uctag2do [31:9] u-cache level 2 tag data output 68 input ucw2do u-cache level 2 written bit output 69 input ucv2do u-cache level 2 valid bit output 70 input uctag1do [31:9] u-cache level 1 tag data output 71 input ucw1do u-cache level 1 written bit output 72 input ucv1do u-cache level 1 valid bit output 73 input uctag0do [31:9] u-cache level 0 tag data output 74 input ucw0do u-cache level 0 written bit output 75 input ucv0do u-cache level 0 valid bit output 76 input uclvl3do [31:0] u-cache level 3 data output 77 input uclvl2do [31:0] u-cache level 2 data output 78 input uclvl1do [31:0] u-cache level 1 data output 79 input uclvl0do [31:0] u-cache level 0 data output 80 input kramsz [2:0] encoded kram size 81 input encf5307kram enable cf5307-style kram 82 input enraptorkram enable raptor-style kram table 3-1. cf3core pin specification no. type name bus width description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
version 3 core motorola version 3 coldfire core user?s manual 3-7 see appendix a: cf3core interface timing constraints f or detailed inf or mation on the synthesis timing budgets for the cf3core interface signals. 3.3 coldfire master bus 3.3.1 introduction the coldfire architecture implements a hierarchy of buses to provide the necessary interconnection and bandwidth among the various components (processors, peripherals, etc.) in a system.the master bus (m-bus) is the system interconnect between multiple masters (including processors) and the system bus controller (sbc). the system bus controller pro vides additional connectivity to an optional inter nal sla v e bus (s-bus) containing on-chip peripheral modules, as well as the external system via the external bus (e-bus). the m-, s-, and e-buses oper ate with a motorola-det ned bus protocol. providing this bus protocol support allows integration of devices at any level in the system. the coldfire architecture is designed to allo w m ultiple cloc k frequency domains . the coldfire processor can be oper ated at an y integer m ultiple (n:1, where n = 1, 2,...) of the m- bus cloc k frequency . the coldfire processor? s m-bus interf ace is the boundar y from the processor?s clock domain to the m-bus clock domain. this section presents the m-bus and its oper ation. it details specit c m-bus protocols needed to support the multiple clock domains and gives system clocking guidelines. 3.3.2 m-bus signals this section det nes the signals required b y the m-bus . although the timing of all of these signals is ref erenced to the system cloc k, the system cloc k is not considered a b us signal. it is expected that the clock is routed as needed to meet application requirements. this section descr ibes m-bus signals as vie w ed b y the bus master . tab le 3-2 giv es a summary of the signals. a brief description of the signal?s functionality follows. note that an overbar indicates an active-low signal. 83 input kramdo [31:0] kram data output 84 input kromsz [2:0] encoded krom size 85 input kromvldrst krom valid at reset 86 input kromdo [31:0] krom data output 87 input mclken clock phase relationship detner 88 input clkfast processor core clock table 3-1. cf3core pin specification no. type name bus width description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
version 3 core 3-8 version 3 coldfire core user?s manual motorola the preceding section provided the actual pin names and order for the version 3 coldfire core reference design, while this section details the m-bus operation from a functional perspective. 3.3.2.1 m-bus read data (mrdata[31:0]). these unidirectional input signals provide the read data path between the system bus controller and internal masters. the read data bus is 32 bits wide and can transfer 8, 16 or 32 bits of data per bus transfer. during a line transfer, the data lines are time-multiplexed across multiple cycles to carry 128 bits. 3.3.2.2 m-bus address hold (mah ). this input signal is asserted to indicate that the address and attributes should be held. this signal indicates that the sbc is not ready to accept the address phase of the bus cycle. this signal is also used in bus arbitration situations to halt the master when it does not have the m-bus. 3.3.2.3 m-bus transfer acknowledge (mta ). this input signal is asser ted to indicate the successful completion of a requested bus transfer. 3.3.2.4 m-bus reset (mrsti ). this input signal directs all m-bus modules (including the core) to enter reset mode. table 3-2. m-bus signal summary signal name direction description mrdata[31:0] in read data bus mah in address hold mta in transfer acknowledge mrsti in m-bus reset mipl [2:0] in interrupt priority level maddr[31:0] out address bus map out address phase mdp out data phase msiz[1:0] out transfer size mrw out read/write mtt[1:0] out transfer type mtm[2:0] out transfer modifier mwdata out write data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
version 3 core motorola version 3 coldfire core user?s manual 3-9 3.3.2.5 m-bus interrupt priority level (mipl [2:0]). these three input signals indicate to the processor that there is a pending interrupt request. table 3-3 shows the encoding for the mipl signals. 3.3.2.6 m-bus address (maddr[31:0]). during a normal bus cycle, these output signals provide the address of the first item of a bus transfer. maddr is 32 bits wide with all signals being unidirectional. 3.3.2.7 m-bus address phase (map ). this output signal indicates that the address and attributes are being driven and that the address phase of the bus cycle is active. 3.3.2.8 m-bus data phase (mdp ). this output signal indicates that the data phase of the cycle is active. this means that data is driven by the bus master during the cycle if the access is a write. during a read, data may be driven back to the bus master. the bus cycle is always terminated during the data phase. 3.3.2.9 m-bus transfer size (msiz[1:0]). these output signals indicate the data size for the bus transfer. refer to table 3-4 for the bus size encodings. table 3-3. m-bus interrupt priority level encodings mipl [2:0] interrupt level 111 no interrupt pending 110 level 1 101 level 2 100 level 3 011 level 4 010 level 5 001 level 6 000 level 7 table 3-4. m-bus transfer size encodings - 32-bit data bus msiz[1:0] transfer size 00 longword (4 bytes) 01 byte (1 byte) 10 word (2 bytes) 11 line (16 bytes) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
version 3 core 3-10 version 3 coldfire core user?s manual motorola 3.3.2.10 m-bus read/write (mrw ). this output signal indicates the data transfer direction for the current bus cycle. a high level indicates a read cycle and a low level indicates a write cycle. 3.3.2.11 m-bus transfer type (mtt[1:0]). these output signals indicate the type of access of the current bus cycle. table 3-5 shows the definition of the transfer type encodings. the alternate master access is used to indicate a non-core master is requesting the transfer. 3.3.2.12 m-bus transfer modifier (mtm[2:0]). these output signals provide supplemental information for each transfer type. refer to table 3-6 for normal transfer encodings and table 3-7 for processor emulator mode transfer encodings. table 3-8 shows the encoding for acknowledge or cpu space accesses. for interrupt acknowledge transfers, the mtm signals carry the interrupt level being acknowledged. for cpu space transfers, the mtm signals are low. table 3-5. m-bus transfer type encodings mtt[1:0] transfer type 00 processor access 01 alternate master access 10 processor emulator mode access 11 acknowledge or cpu space access table 3-6. m-bus transfer modifier encodings for mtt = 0- mtm[2:0] transfer moditer 000 reserved 001 user data access 010 user code access 011 - 100 reserved 101 supervisor data access 110 supervisor code access 111 reserved table 3-7. m-bus transfer modifier encodings for mtt = 10 mtm[2:0] transfer moditer 000 - 100, 111 reserved f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
version 3 core motorola version 3 coldfire core user?s manual 3-11 3.3.2.13 m-bus write data (mwdata[31:0]). these unidirectional output signals provide the write data path between an internal master and the system bus controller. the write data bus is 32 bits wide and can transfer 8, 16 or 32 bits of data per bus transfer. during a line transfer, the data lines are time-multiplexed across multiple cycles to carry 128 bits. 3.3.3 m-bus operation the m-bus is a two-stage, synchronous pipelined bus. this gives it an effective bandwidth rate of up to one transfer per clock. 3.3.3.1 basic bus cycles. the bus transaction is split into two phases. the first phase is the address phase. during this phase, the address ( maddr ) and attribute signals ( msiz , mrw , mtt , and mtm ) are driven. the address phase signal ( map ) is asserted to show that the bus is in the address phase. the second part of the transaction is the data phase. the data phase ( mdp ) signal is asserted to show that the bus is in the data phase and that data transfer may now take place. the data phase stays active until the bus cycle is terminated with a transfer acknowledge ( mta ). on a write cycle, the write data bus ( mwdata ) is driven for the duration of the data phase. on a read cycle, the read data bus ( mrdata ) is sampled by the bus master concurrently with mta at the rising clock edge. figure 3- 4 shows the basic read and write operations. 101 emulator mode data access 110 emulator mode code access table 3-8. m-bus transfer modifier encodings for mtt = 11 mtm[2:0] transfer moditer 000 cpu space 001 interrupt level 1 acknowledge 010 interrupt level 2 acknowledge 011 interrupt level 3 acknowledge 100 interrupt level 4 acknowledge 101 interrupt level 5 acknowledge 110 interrupt level 6 acknowledge 111 interrupt level 7 acknowledge table 3-7. m-bus transfer modifier encodings for mtt = 10 mtm[2:0] transfer moditer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
version 3 core 3-12 version 3 coldfire core user?s manual motorola figure 3- 4. basic read and write cycles 3.3.3.2 pipelined bus cycles. since the bus is pipelined, it is possible for the address phase of the next bus cycle to become valid while the data phase of the current bus cycle is still valid. it is not possible for the address and data phases of the same bus cycle to be concurrently valid. figure 3- 5 shows two basic bus cycles that have been pipelined. for illustration purposes, a read and write cycle are used in figure 3-4. there are no restrictions on cycles being either reads or writes in order for them to be pipelined. maddr & map mah mdp mt a mrw mrdata mwdata address phase data phase address phase data phase read cycle write cycle attributes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
version 3 core motorola version 3 coldfire core user?s manual 3-13 figure 3- 5. pipelined read and write 3.3.3.3 address and data phase interactions. bus timing, performance, and arbitration are controlled by handling the address and data phases of the bus cycle. the general rules for controlling the phases are: the address phase is allowed to begin when there is no active address phase. the address phase is allowed to end and the data phase to begin when the address hold ( mah ) signal is not asserted and there is either no active data phase or the active data phase is being terminated. the data phase is allowed to end when the cycle is terminated with mta . there is one special rule that applies only to m-bus masters that are coldfire processors operating at the same clock frequency as the m-bus (i.e., the processor ?s clock domain and the m-bus clock domain have the same frequency, the so-called 1x clock mode) . this special rule is a restriction on the second general rule above: for a processor operating in 1x clock mode, the processor?s address phase is allowed to end and the data phase to begin when the address hold ( mah ) signal is not asserted and there is either no active data phase or the active data phase is not from this processor and is being terminated. address phase data phase address phase data phase read cycle write cycle maddr & map mah mdp mt a mrw mrdata mwdata attributes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
version 3 core 3-14 version 3 coldfire core user?s manual motorola that is, for a coldfire processor operating in 1x clock mode, there must be one m-bus cycle where that processor?s data phase is inactive before its active address phase can progress to a data phase. the implications of the general bus rules are: the bus master is held off (usually for bus arbitration) by asserting the mah signal. this assures that the address and attributes remain valid and that the data phase is not entered. pipelining is accomplished by allowing the next address phase to begin during the data phase as soon as the next address is available. wait states are introduced by withholding the termination signal mta . the implications of the special 1x clock mode rule are: if a coldfire processor operating in 1x clock mode has both an active address phase and an active data phase, the m-bus control module must assert the mah signal on the last m-bus transfer acknowledge. this forces the coldfire processor to hold in its address phase until its data phase has been idle for at least one cycle. a simple implementation of this 1x clock mode rule is to connect the mta signal from the system bus controller to both the mta and mah inputs ports of the cf3core design. figure 3- 6 shows the map signal asserted during the same clock that mah is asserted. the address phase is held until mah is negated. at this point, mdp is asserted to show that the data phase of the first cycle has begun. since the address for the next bus cycle is available, map remains asserted to indicate that the address phase of the second cycle has begun. one wait state is inserted into the bus cycle by delaying mta until the next clock. in this case, map is negated after termination because there is not another address available from the bus master. mdp is not negated because at termination the address phase of the second cycle transitions to the data phase. since the termination signal remains asserted, the data phase of the second cycle is only one clock long. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
version 3 core motorola version 3 coldfire core user?s manual 3-15 figure 3- 6. address hold followed by 1- and 0-wait state cycles figure 3- 7 demonstrates that map may be generated in the center of the data phase. it also shows that mah may be generated while a data phase is active. in this case, the current data phase is completed, but the next cycle is not allowed to transition to the data phase. figure 3- 7. map and mah generated mid-data phase figure 3-6 demonstrates the special rule for 1x clock mode. it shows a 1x clock mode processor in its address phase (address phase 2) being held on the last mta of its current data phase (data phase 1) by mah . maddr & map mah mdp mt a attributes address phase 1 address phase 2 data data phase 2 phase 1 maddr & map mah mdp mt a attributes address address phase 2 data phase 1 data phase 2 phase 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
version 3 core 3-16 version 3 coldfire core user?s manual motorola figure 3- 8. mah generation for 1x clock mode 3.3.3.4 data size operations. the processor designates all oper ands f or tr ansf ers on a b yte-boundar y system using the nomenclature sho wn in tab le 3-9. these designations shown are used in the subsequent descriptions. a bus cycle is a request to transfer data from the bus master to some slave device. since the coldfire architectures supports byte, word, and longword operand types, on misaligned boundaries, there are certain requirements on the bus architecture to support these data types. the main support is to guarantee that each byte of data is aligned to the proper lane to assure it is handled properly by both master and slave. note also, that for line transfers, the data alignment is treated as 4 longword transfers. specific protocols to handle these transfers are discussed in the next section. all transfers on m-bus assume that the devices on m-bus are 32 bits wide. if dynamic sizing is supported in a system, to word or byte ports, it is handled by the system bus controller. to support this bus sizing feature, there are certain data replication functions which must be performed by all m-bus masters during write cycles . for all data transfers, maddr[31:2] indicates the longword base address of the first byte of the reference item. maddr[1:0] table 3-9. processor operand representation bits[31:24] bits[23:16] bits[15:8] bits[7:0] format op0 op1 op2 op3 longword operand op2 op3 word operand op3 byte operand maddr & map mah mdp mt a attributes address address phase 2 data phase 1 data phase 2 phase 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
version 3 core motorola version 3 coldfire core user?s manual 3-17 indicates the byte offset from this base address. the msiz[1:0] field along with the low-order 2 address bits are used to determine how the data buses are used. the f ollo wing tab les, tab le 3-10 and tab le 3-11, indicate mrdata requirements f or read transf ers and mwdata requirements f or wr ite tr ansfers. a - indicates a don?t care, i.e ., the v alue is ignored. these tab les det ne the complete set of allo wab le combinations of msiz[1:0] and maddr[1:0] . 3.3.3.5 line transfers. a line is defined as a 16-byte value, aligned in memory on 0- modulo-16 address boundary. on the m-bus, this is seen as an address phase followed by a data phase during which 4 longwords of data are transferred. transfers on each of these data phases are longword in size. although the line itself is aligned on 16-byte boundaries, the line access does not necessarily begin on a 0-modulo-16 address. they can begin at table 3-10. mrdata requirements for read transfers transfer size msiz [1:0] maddr [1:0] mrdata [31:24] mrdata [23:16] mrdata [15:8] mrdata [7:0] byte 01 00 op3 - - - 01 01 - op3 - - 01 10 - - op3 - 01 11 - - - op3 word 10 00 op2 op3 - - 10 10 - - op2 op3 long 00 00 op0 op1 op2 op3 line 11 00 op0 op1 op2 op3 table 3-11. mwdata bus requirements for write transfers transfer size msiz [1:0] maddr [1:0] mwdata [31:24] mwdata [23:16] mwdata [15:8] mwdata [7:0] byte 01 00 op3 - - - 01 01 op3 op3 - - 01 10 op3 - op3 - 01 11 op3 op3 - op3 word 10 00 op2 op3 - - 10 10 op2 op3 op2 op3 long 00 00 op0 op1 op2 op3 line 11 00 op0 op1 op2 op3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
version 3 core 3-18 version 3 coldfire core user?s manual motorola any aligned long word address with maddr[1:0] = 00. therefore, the slave system (combination of the sbc, modules, and external devices) must be able to cycle through the longword addresses. the allowable patterns during a line accesses are shown in table 3- 12 below: figure 3-7 shows a line access read with zero wait states. note that another address phase may be initiated at any time during the data phase. this address phase corresponds to the next bus cycle. also note that the address hold may be asserted during this time. address hold has no effect on the data phase of a line access. the line access completes and the address is held before the next data phase is allowed. figure 3- 9. line access read with zero wait states table 3-12. allowable line access patterns maddr[3:2] longword accesses 00 $0 - $4 - $8 - $c 01 $4 - $8 - $c - $0 10 $8 - $c - $0 - $4 11 $c - $0 - $4 - $8 maddr & map mah mdp mt a mrw mrdata attributes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
version 3 core motorola version 3 coldfire core user?s manual 3-19 figure 3- 10. line access read with 1 wait state figure 3-9 and figure 3-10 show line write accesses. note that the next long word of data is available on the clock immediately following the termination. there may be cases where data may be pipelined to the external bus by terminating the access and registering the data in the system bus controller during the first clock of the data phase. this allows the next longword of data to be available at the next rising clock edge. figure 3- 11. line access write with zero wait states maddr & map mah mdp mt a mrw mrdata attributes maddr & map mah mdp mt a mrw mwdata attributes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
version 3 core 3-20 version 3 coldfire core user?s manual motorola figure 3- 12. line access write with one wait state 3.3.3.6 bus arbitration. multiple bus masters are handled on the m-bus through a multiplexed bus scheme. there cannot be multiple masters on the same physical bus. figure 3-11 shows the top level architecture of a two-master, multiplexed m-bus system. mux control is provided by the arbitration block. the address, attributes, write data, map and mdp are multiplexed to the system bus controller. the current bus master?s signals are muxed onto the common bus. the termination and address hold signals are demultiplexed and routed to the appropriate bus master. reset signals and read data do not need to be multiplexed. address hold is generated by the arbitration logic to stall the master that does not currently have the bus. the multiplexed scheme was adopted to more easily accommodate a standard cell methodology. there are no three-state or bidirectional signals on the bus. one implication of this architecture is that the addition of more bus masters causes the multiplexing to become more complex and possibly creates timing problems. designs should seek to limit the number of m-bus masters. for instance, instead of putting three dma modules on the m-bus, a single 3-channel dma should be investigated. maddr & map mah mdp mt a mrw mwdata attributes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
version 3 core motorola version 3 coldfire core user?s manual 3-21 figure 3- 13. multiplexed m-bus structure figure 3-12 shows waveforms with two bus masters multiplexed onto a common m-bus. the exact arbitration scheme and relative priority of bus masters is not defined in this document. that is determined by the implementation of the arbitration logic. in this example, bus master #1 represents the default bus master, such as a core processor. the mah signal for this master is normally high allowing the master to utilize the bus as needed. when bus master #2, which serves as the alternate master, such as a dma controller, needs the bus, it asserts its map signal which serves as the bus request. the arbiter begins the bus transition by asserting mah1 to hold off the first bus master. it also transitions sel_a_1 which is the mux control signal for address, attributes, and map . since there is an active data phase on the bus, the data portion of the bus is not allowed to be muxed until termination of that bus cycle. at that point, sel_d_1 the mux control for mwdata , mdp , and mta is toggled. the second bus master runs its bus cycle, on the common bus, and the bus is then returned to the first bus master. note that there is no need to multiplex mrdata . since data is sampled by the bus master when the data phase is terminated, control of the termination signal is sufficient. bus master #1 bus master #2 bus arbitration and multiplexing system bus controller m-bus #1 m-bus #2 common m-bus external bus s-bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
version 3 core 3-22 version 3 coldfire core user?s manual motorola figure 3- 14. multiplexed m-bus operation 3.3.3.7 interrupt support. interrupts are supported on the m-bus by the mipl signals and interrupt acknowledge cycles. when an interrupt is pending, the sbc is maddr1 & map1 mah1 mdp1 mt a1 mwdata1 attributes maddr2 & map2 mah2 mdp2 mt a2 mwdata2 attributes maddr & map mdp mt a mrdata mwdata attributes sel_a_1 sel_d_1 bus master #1 bus master #2 common m-bus mux control f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
version 3 core motorola version 3 coldfire core user?s manual 3-23 responsible for driving the mipl signals to the processor to request interrupt processing. the interrupted processor runs an acknowledge cycle to request the interrupt vector to begin exception processing. the interrupt acknowledge cycle looks like a standard byte read cycle. for this cycle, the mtt signals indicate an acknowledge cycle ( mtt[1:0] = 11) and the interrupt level of the interrupt being processed is specified in the mtm signals. additionally, the address lines maddr[31:5] are all driven high, the interrupt level is reflected on maddr[4:2] and the lower two address bits, maddr[1:0] , are zero. the 8-bit interrupt vector is returned on mdata[31:24] . 3.3.3.8 reset operation. when a master is reset, that is when mrsti is driven low, the bus control signals of that m-bus master are driven to their inactive state. this means that map , mdp , mrw and mta are all driven high. mah is an exception to this case and may be driven high or low depending on the specific system implementation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola version 3 coldfire core user?s manual 4-1 section 4 v3 cpu 4.1 introduction the design focus of the version 3 (v3) coldfire processor was the development of a higher performance core while maintaining backward code compatibility with the previous generation, the version 2 core. the v3 core represents another step on the coldfire roadmap, and with its enhanced pipeline structure and local memories, provides a high level of performance needed by today?s demanding embedded applications. 4.2 version 3 processor microarchitecture 4.2.1 version 3 processor pipeline overview all coldfire processor cores consist of two independent, decoupled pipeline structures to maximize performance. the instruction fetch pipeline (ifp) prefetches instructions, while the operand execution pipeline (oep) decodes the instruction, fetches the required operands and then executes the specified function. while one of the goals of the original coldfire microarchitecture was to minimize overall size, the driving factor in the version 3 design was to better balance the logic delays associated with each pipeline stage to allow the operating frequency to be raised significantly. for some functions, this required new pipeline stages to be added to support the higher frequency goals. in particular, accesses on the processor?s local, high-speed bus were reimplemented to use a 2-stage pipelined bus to the cache, ram and rom memories. additionally, the time-critical instruction decode functions within the operand execution pipeline were relocated into a new stage in the ifp, named the instruction early decode stage. the implementation of the early decode pipeline stage was first used in the development of the superscalar mc68060 microprocessor, and is a proven technology addressing the decode issues normally associated with variable- length instructions. the net effect is the version 3 pipeline structure is considerably different than the version 2 design. the v3 instruction fetch pipeline is a 4-stage design with an optional instruction buffer stage, while the operand execution pipeline retains its 2-stage structure. in the oep design, each pipeline stage has multiple functions. the v3 processor pipeline stages are: instruction fetch pipeline instruction address generation (iag) calculation of the next prefetch address date: 08-21-98 revision no: 0.1 pages affected: 25, 26 (see change bars) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
v3 cpu 4-2 version 3 coldfire core user?s manual motorola instruction fetch cycle 1 (ic1) initiation of prefetch access on the processor?s local bus instruction fetch cycle 2 (ic2) completion of prefetch access on the processor?s local bus instruction early decode (ied) generation of time-critical decode signals needed for the oep instruction buffer (ib) optional buffer stage using fifo queue operand execution pipeline decode, select/operand fetch cycle (dsoc) decode the instruction and select the required components for the effective address calculation, or the operand fetch cycle address generation/execute cycle (agex) calculate the operand address, or perform the execution of the instruction 4.2.2 version 3 instruction fetch pipeline the resulting four-stage ifp implementation calculates the next prefetch address, fetches the instruction data with two stages mapped onto the 2-stage pipeline local-memory bus structure, followed by the early decode stage. when the instruction buffer is empty, prefetched instruction data is loaded directly from the ied stage into the operand execution pipeline. if the buffer is not empty, the ifp stores the contents of the prefetch in the fifo queue until it is required by the oep. it should be noted that the organization of the version 3 instruction buffer is fundamentally different than the v2 approach. one of the time-critical decode fields provided by the early decode stage of the ifp is the instruction length. by knowing the length of the prefetched instructions, the ied field is able to package the fetched data into machine instructions and load them into the fifo instruction buffer in that form.the version 3 design implements an 8-entry instruction buffer, where each entry contains one machine instruction in the form of the operation word, the early decode information (also known as the extended operation word), and the optional extension words 1 and 2. this approach greatly simplifies and accelerates the oep?s read logic. as one instruction is completed in the oep, the next instruction, regardless of instruction length, is read from the next sequential buffer location and loaded into the instruction registers. 4.2.2.1 change of flow acceleration. since the version 3 instruction fetch and operand execution pipelines are decoupled by the instruction buffer, the increased depth of the ifp is generally hidden from the oep?s instruction execution. the one exception is change-of-flow instructions, e.g., unconditional branches or jumps, subroutine calls, taken conditional branches, etc. for these instructions, the increased depth of the ifp pipeline is fully exposed. to minimize the effects of this increased depth, a logic module dedicated to f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
v3 cpu motorola version 3 coldfire core user?s manual 4-3 change-of-flow acceleration was developed for the ied stage of the instruction fetch pipeline. given that the instruction boundaries are known in the ied stage, a logical extension was the creation of branch acceleration module which could monitor the prefetched stream, looking for change-of-flow opcodes.the basic premise of the version 3 branch acceleration is to detect certain types of change-of-flow instructions, calculate their target instruction address, and immediately begin fetching down the target stream. by allowing the switching of the prefetch stream to be handled completely within the ifp without any operand execution pipeline intervention, the typical execution time is greatly improved. as an example, consider a pc-relative unconditional branch using the bra instruction. the branch acceleration logic searches the prefetch stream for this type of opcode. once encountered, the acceleration logic calculates the target address by summing the current instruction prefetch address with a displacement contained in the instruction. this detection and calculation of the target address occurs in the ied stage of the bra prefetch. the target address is then immediately fed back into the iag stage, causing the current prefetch stream to be discarded and a new stream at the target address established. given that the two pipelines are decoupled, in many cases, the target instruction is available to the oep immediately after the bra instruction, making its execution time appear as a single cycle. the acceleration logic uses a static prediction algorithm when processing conditional branch (bcc) instructions. the default prediction scheme is forward bcc instructions are predicted as not-taken, while backward bcc opcodes are predicted as taken. a user-mode control bit (bit 7 of the ccr) is provided to allow users to dynamically alter the prediction algorithm for forward bcc instructions. see section 4.4.5: condition code register for details. depending on the runtime characteristics of an application, processor performance may be increased significantly by the assertion or negation of this configuration bit. see appendix b on branch instruction execution times for details on individual instruction performance. 4.2.3 version 3 operand execution pipeline the oep is implemented in a two-stage pipeline featuring a traditional risc datapath with a dual-read-ported register file feeding an arithmetic/logic unit. for simple register-to- register instructions, the first stage of the oep performs the instruction decode and fetching of the required register operands (oc), while the actual instruction execution is performed in the second stage (ex). for memory-to-register (embedded-load) instructions, the instruction is effectively staged through the oep twice. first, the instruction is decoded and the components of the operand address are selected (ds). second, the operand address is generated using the execute engine (ag). third, the memory operand is fetched from the processor local bus, while any register operand is simultaneously fetched (oc). finally, in the last cycle, the instruction is executed (ex). for register-to-memory operations, the stage functions (ds/oc, ag/ex) are effectively performed simultaneously allowing single-cycle execution. for read-modify-write instructions, the pipeline effectively combines an embedded-load with a store operation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
v3 cpu 4-4 version 3 coldfire core user?s manual motorola 4.2.3.1 illegal opcode handling. as an aid in conversion from m68000 family code, the complete space defined by the 16-bit opcode is decoded. if the processor attempts execution of an illegal or non-supported instruction, an illegal instruction exception is taken. 4.2.3.2 hardware multiply-accumulate (mac) and divide execution units. the optional mac unit is designed to provide hardware support for a limited set of signal processing operations that are currently being used in embedded code today, while supporting the integer multiply instructions in the coldfire microprocessor family. the mac unit provides functionality in three related areas: signed and unsigned integer multiplies multiply-accumulate operations supporting signed and unsigned operands miscellaneous register operations the coldfire mac has been optimized for 16x16 multiplies to minimize silicon costs. the mac unit is tightly coupled to the processor?s operand execution pipeline and features a 3- stage execution pipeline. the oep can issue a 16 x 16 multiply with a 32-bit accumulate operation in a single cycle, while a 32 x 32 multiply with a 32-bit accumulation requires three cycles before the next instruction can be issued. figure 4-1 shows the basic functionality of the coldfire mac. the operand execution pipeline also includes a hardware execute engine which performs all integer divide operations. the supported divide functions include: 32/16 producing a 16- figure 4-1. coldfire multiply-accumulate functionality diagram x +/- operand x operand y shift 0,1,-1 accumulator f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
v3 cpu motorola version 3 coldfire core user?s manual 4-5 bit quotient and a 16-bit remainder, 32/32 producing a 32-bit quotient, and 32/32 producing a 32-bit remainder. if execution of a mac or divide opcode is attempted and the corresponding hardware unit is not present , then a non-supported instruction exception is generated. for detailed instruction descriptions on the mac and divide opcodes, see the coldfire microprocessor family programmer?s reference manual (mcf5200prm/ad). 4.2.4 version 3 processor pipeline block diagrams and summary the following diagrams present a more detailed view of the internal pipeline structures for the version 3 processor. compared to the two-stage version 2 design, note the increased length of the ifp with the early decode (ed) table lookup and the branch acceleration target address adders in the ied stage with the feedback to the prefetch address logic in the iag stage. the oep is essentially unchanged from the version 2 design with the exception of the extended opword provided from the ifp as part of the instruction interface: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
v3 cpu 4-6 version 3 coldfire core user?s manual motorola figure 4-2. version 3 coldfire pipeline diagram iag ic 1 ib kaddr krdata opword ext 1 ext 2 fifo ib instruction fetch pipeline operand execution pipeline dsoc agex opword extension 1 extension 2 krdata kaddr kwdata rgf ic 2 ied kaddr_ic2 extended opword ed extended opword +4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
v3 cpu motorola version 3 coldfire core user?s manual 4-7 as a result of the increased ifp pipelining and an exposed cycle of latency on most operand read references, the cycles per instruction performance of the v3 core is usually slightly lower than v2 at a given frequency. however, the entire design focus of the v3 development was to maximize the operating frequency, and comparison of speeds in a given process technology indicate this goal was achieved. using a common 0.35 micron process technology, the version 3 core synthesizes into a ~200,000 transistor implementation with a size of 3 mm 2 (no mac or div units) and 3.8 mm 2 with the mac and div. operating frequency is increased to 1.5x relative to v2 and reaches 90-100 mhz. finally, the version 3 microarchitecture provides a 0.78 dhrystone 2.1 mips per mhz performance with an 8 kbyte unified cache. a comprehensive analysis using a standard set of embedded benchmarks has measured the following relative performance based on initial implementation for each core generation: 90/45 mhz v3 = 2.5 x 33.3 mhz v2 with the following configurations: - a 90 mhz v3 processor complex with an 8 kbyte unified cache with a 1/2x speed external bus with a 4-2-2-2 memory response speed - a 33.3 mhz v2 processor complex with a 2 kbyte unified cache with a 3-1-1-1 memory response speed - copyback cache mode for both processors, no kram memory, and no mac or div instructions 4.3 coldfire processor programming model refer to the coldfire microprocessor family programmer?s reference manual (mcf5200prm/ad) for detailed information on the operation of the instruction set and addressing modes. the core programming model consists of three instruction and register groups: user, user- mode mac, and supervisor. programs executing in user mode are restricted to the basic user and mac programming models. system software executing in supervisor mode can reference all user-mode and mac instructions and registers, plus an additional set of privileged instructions and control registers. the appropriate programming model is selected based on the privilege level (user or supervisor) of the processor as defined by the s-bit of the status register. the following paragraphs describe the registers in the user, mac and supervisor programming models. 4.4 user programming model figure 4-3 illustrates the user programming model. it consists of the following registers: 16 general-purpose 32-bit registers 32-bit program counter 8-bit condition code register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
v3 cpu 4-8 version 3 coldfire core user?s manual motorola 4.4.1 data registers (d0 e d7) . registers d0ed7 are used as data registers for bit (1 bit), byte (8 bits), word (16 bits), and longword (32 bits) operations and may also be used as index registers. 4.4.2 address registers (a0 e a6) . these registers can be used as software stack pointers, index registers, or base address registers and may be used for word and longword operations. 4.4.3 stack pointer (a7, sp) . the processor core supports a single hardware stack pointer (a7) used during stacking for subroutine calls, returns, and exception handling. the initial value of a7 is loaded from the reset exception vector, address $0. the same register is used for user and supervisor modes, and may be used for word and longword operations. a subroutine call saves the pc on the stack, and the return restores the pc from the stack. both the pc and the status register (sr) are saved on the stack during the processing of exceptions and interrupts. the return from exception instruction restores the sr and pc values from the stack. 4.4.4 program counter (pc). the pc contains the address of the currently executing instruction. during instruction execution and exception processing, the processor automatically increments the contents of the pc or places a new value in the pc, as appropriate. for some addressing modes, the pc can be used as a pointer for pc-relative operand addressing. 4.4.5 condition code register (ccr). the ccr is the least significant byte of the processor status register (sr), as shown later. 31 16 15 8 7 0 data register 0 (d0) data register 1 (d1) data register 2 (d2) data register 3 (d3) data register 4 (d4) data register 5 (d5) data register 6 (d6) data register 7 (d7) address register 0 (a0) address register 1 (a1) address register 2 (a2) address register 3 (a3) address register 4 (a4) address register 5 (a5) address register 6 (a6) stack pointer (sp,a7) program counter (pc) condition code register (ccr) figure 4-3. user programming model f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
v3 cpu motorola version 3 coldfire core user?s manual 4-9 bit 7, the branch prediction bit, provides a mechanism to alter the static prediction algorithm used by the branch acceleration logic in the instruction fetch pipeline. the prediction algorithm is defined as: if bcc instruction is a forward branch && (ccr.p == 0) then the bcc is predicted as not-taken if bcc instruction is a forward branch && (ccr.p == 1) then the bcc is predicted as taken all backwards bcc instructions are predicted as taken. the forward/backward classification is defined by the sign of the address displacement: if the address displacement is positive, the bcc is forward, while a negative displacement produces a backward branch. depending on the dynamic characteristics of a given application, the processor performance may be increased by the assertion or negation of this control bit. bits 4e0 represent indicator flags based on results generated by processor operations. bit 4, the extend bit (x bit), is also used as an input operand during multiprecision arithmetic computations. field definitions: p[7]?branch prediction bit setting this bit causes forward conditional branches to be predicted as taken. clearing this bit causes forward conditional branch instructions to be predicted as not-taken. x[4]?extend condition code assigned the value of the carry bit for arithmetic operations; otherwise not affected. n[3]?negative condition code set if the most significant bit of the result is set; otherwise cleared. z[2]?zero condition code set if the result equals zero; otherwise cleared. v[1]?overflow condition code set if an arithmetic overflow occurs implying that the result cannot be represented in the operand size; otherwise cleared. bits 76543210 field p- -xnzvc reset 000----- r/w r/w r r r/w r/w r/w r/w r/w condition code register (ccr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
v3 cpu 4-10 version 3 coldfire core user?s manual motorola c[0]?carry condition code set if a carry out of the most significant bit of the operand occurs for an addition, or if a borrow occurs in a subtraction; otherwise cleared. see the coldfire microprocessor family programmer?s reference manual (mcf5200prm/ ad) for more information on how specific instructions affect the condition code register bits. 4.5 mac programming model figure 4-4 illustrates the mac portion of the user programming model available on the processor core. it consists of the following registers: 32-bit accumulator (acc) 16-bit mask register (mask) 8-bit mac status register (macsr) the instructions which reference the mac registers always transfer 32 bits of data, regardless of the implemented size of the register. 4.5.1 accumulator (acc). this is a 32-bit general-purpose register used to accumulate the results of mac operations. 4.5.2 mask register (mask). this is a 16-bit general-purpose register for use as an optional address mask during mac instructions which fetch operands from memory. it is useful in the implementation of circular queues in operand memory. 4.5.3 mac status register (macsr). this is an 8-bit special-purpose register which defines the operating configuration of the mac unit, and contains indicator flags from the results of mac instructions. 4.6 supervisor programming model system programmers use the supervisor programming model to implement sensitive operating systems, i/o control, memory configuration and management. the following paragraphs briefly describe the registers in the supervisor programming model. all accesses that affect the control features of the processor are in the supervisor programming model, which consists of the instructions and registers accessible in the user and mac models, as well as the registers listed in figure 4-5. 31 16 15 8 7 0 accumulator (acc) mask register (mask) mac status register (macsr) figure 4-4. mac unit user programming model f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
v3 cpu motorola version 3 coldfire core user?s manual 4-11 most of the control registers are accessed via the movec instruction using the control register definitions shown in table 4-1. 4.6.1 cache control register (cacr). the cacr controls the operation of the unified cache memory. this register includes enable, freeze and invalidate controls, plus line fill buffer configuration control as well as the default cache mode and write protect fields. see section 4.3 for a complete description of the cacr. 4.6.2 access control registers (acr0, acr1). the acr registers allow specification of certain attributes for two user-defined regions of memory. these attributes include definition of cache mode, write protect and buffer write enables. see section 5.3.3 for a complete description of the acr registers. 4.6.3 vector base register (vbr). the vbr contains the base address of the exception vector table in memory. the displacement of an exception vector is added to the value in this register to access the vector table. the lower 20 bits of the vbr are not implemented by coldfire processors; they are assumed to be zero, forcing the table to be aligned on a 0-modulo-1 mbyte boundary. 4.6.4 ram base address register (rambar). this register determines the base address location of the processor local ram module, plus provides definition of the types of references that are mapped into it. the register includes a base address, write protect bit, address space mask bits and enable. see section 5.4.2 for a complete description of the rambar register. 4.6.5 rom base address register (r0mbar). this register determines the base address location of the processor local rom module, plus provides definition of the types of references that are mapped into it. the register includes a base address, write protect bit, 31 16 15 0 cache control register (cacr) access control register 0 (acr0) access control register 1 (acr1) vector base register (vbr) rom base address register (r0mbar) ram base address register (rambar) status register (sr) figure 4-5. supervisor programming model table 4-1. movec register map rc[11:0] register definition $002 cache control register (cacr) $004 access control register 0 (acr0) $005 access control register 1 (acr1) $801 vector base register(vbr) $c00 rom base address register (r0mbar) $c04 ram base address register (rambar) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
v3 cpu 4-12 version 3 coldfire core user?s manual motorola address space mask bits and enable. see section 5.5.2 for a complete description of the r0mbar register. 4.6.6 status register (sr). the following illustrates the sr, which stores the processor status, the interrupt priority mask, and other control bits. in supervisor mode, software can access the entire sr, but in user mode, only the lower 8 bits are accessible as the ccr. the control bits indicate the following states for the processor: trace mode (t-bit), supervisor mode (s-bit) and master mode (m-bit). field definitions: t[15]?trace enable when set, the processor performs a trace exception after every instruction; otherwise no trace exception is performed. s[13]?supervisor / user state denotes the processor privilege mode: supervisor mode (s =1) or user mode (s = 0). m[12]?master / interrupt state this bit is cleared by an interrupt exception, and can be set by software during execution of the rte or move to sr instructions. i[10:8]?interrupt priority mask defines the current interrupt priority. interrupt requests are inhibited for all priority levels less than or equal to the current priority, except the level seven request, which cannot be masked. 4.7 exception processing overview exception processing for coldfire processors is streamlined for performance. differences from previous m68000 family processors include: a simplified exception vector table reduced relocation capabilities using the vector base register a single exception stack frame format use of a single, self-aligning system stack pointer coldfire processors use an instruction restart exception model but do require software support to recover from certain access errors. see section 4.7.1 access error exception for details. bits 15 14 13 12 11 10 876543210 field t-sm- i p - xnzvc reset 00100 7 0 00 ----- r/w r/w r r/w r/w r r/w r/w r r/w r/w r/w r/w r/w status register (sr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
v3 cpu motorola version 3 coldfire core user?s manual 4-13 exception processing is comprised of four major steps and can be defined as the time from the detection of the fault condition until the fetch of the first handler instruction has been initiated. first, the processor makes an internal copy of the sr and then enters supervisor mode by setting the s-bit and disabling trace mode by clearing the t-bit. the occurrence of an interrupt exception also forces the m-bit to be cleared and the debug priority mask to be set to the level of the current interrupt request. second, the processor determines the exception vector number. for all faults except interrupts, the processor performs this calculation based on the exception type. for interrupts, the processor performs an interrupt-acknowledge (iack) bus cycle to obtain the vector number from a peripheral device. the iack cycle is mapped to a special acknowledge address space with the interrupt level encoded in the address. third, the processor saves the current context by creating an exception stack frame on the system stack. coldfire processors support a single stack pointer in the a7 address register; therefore, there is no notion of separate supervisor or user stack pointers. as a result, the exception stack frame is created at a 0-modulo-4 address on the top of the current system stack. additionally, the processor uses a simplified fixed-length stack frame for all exceptions. the exception type determines whether the program counter placed in the exception stack frame defines the location of the faulting instruction (fault) or the address of the next instruction to be executed (next). fourth, the processor acquires the address of the first instruction of the exception handler. by definition, the exception vector table is aligned on a 1 mbyte boundary. this instruction address is obtained by fetching a value from the table located at the address defined in the vector base register. the index into the exception table is calculated as (4 x vector_number). once the index value has been generated, the contents of the vector table determine the address of the first instruction of the desired handler. after the instruction fetch for the first opcode of the handler has been initiated, exception processing terminates and normal instruction processing continues in the handler. coldfire processors support a 1024-byte vector table aligned on any 1 mbyte address boundary (see table 4-2). the table contains 256 exception vectors where the first 64 are defined by motorola and the remaining 192 are user-defined interrupt vectors. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
v3 cpu 4-14 version 3 coldfire core user?s manual motorola coldfire processors inhibit sampling for interrupts during the first instruction of all exception handlers. this allows any handler to effectively disable interrupts, if necessary, by raising the interrupt mask level contained in the status register. 4.6 exception stack frame definition the exception stack frame is shown in figure 4-6. the first longword of the exception stack frame contains the 16-bit format/vector word (f/v) and the 16-bit status register. the second longword contains the 32-bit program counter address. the 16-bit format/vector word contains 3 unique fields: table 4-2. exception vector assignments vector number(s) vector offset (hex) stacked program counter assignment 0 $000 - initial stack pointer 1 $004 - initial program counter 2 $008 fault access error 3 $00c fault address error 4 $010 fault illegal instruction 5-7 $014-$01c - reserved 8 $020 fault privilege violation 9 $024 next trace 10 $028 fault unimplemented line-a opcode 11 $02c fault unimplemented line-f opcode 12 $030 next debug interrupt 13 $034 - reserved 14 $038 fault format error 15 $03c next uninitialized interrupt 16-23 $040-$05c - reserved 24 $060 next spurious interrupt 25-31 $064-$07c next level 1-7 autovectored interrupts 32-47 $080-$0bc next trap # 0-15 instructions 48-60 $0c0-$0f0 - reserved 61 $0f4 fault non-supported instruction 62-63 $0f8-$0fc - reserved 64-255 $100-$3fc next user-defined interrupts fault refers to the pc of the instruction that caused the exception next refers to the pc of the next instruction that follows the instruction that caused the fault. figure 4-6. exception stack frame form format fs[3:2] vector[7:0] fs[1:0] program counter[31:0] a7 + $04 31 27 25 17 15 0 status register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
v3 cpu motorola version 3 coldfire core user?s manual 4-15 a 4-bit format field at the top of the system stack is always written with a value of {4,5,6,7} by the processor indicating a two-longword frame format. see table 4-3. this field records any longword misalignment of the stack pointer which might have existed at the time the exception occurred. a 4-bit fault status field, fs[3:0], at the top of the system stack. this field is defined for access and address errors only and written as zeros for all other types of exceptions. see table 4-4. the 8-bit vector number, vector[7:0], defines the exception type and is calculated by the processor for all internal faults and represents the value supplied by the peripheral in the case of an interrupt. refer to table 4-2. 4.7 processor exceptions 4.7.1 access error exception for the version 3 coldfire core, access errors are only reported in conjunction with an attempted store to a write-protected memory space. thus, access errors associated with instruction fetch or operand read accesses are not possible. table 4-3. format field encoding original a7 @ time of exception, bits 1:0 a7 @ 1st instruction of handler format field bits 31:28 00 original a7 - 8 0100 01 original a7 - 9 0101 10 original a7 - 10 0110 11 original a7 - 11 0111 table 4-4. fault status encodings fs[3:0] definition 0000 not an access or address error 0001 reserved 001x reserved 0100 error on instruction fetch 0101 reserved 011x reserved 1000 error on operand write 1001 attempted write to write-protected space 101x reserved 1100 error on operand read 1101 reserved 111x reserved f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
v3 cpu 4-16 version 3 coldfire core user?s manual motorola the coldfire processor uses an imprecise reporting mechanism for access errors on operand writes. since the actual write cycle may be decoupled from the processor?s issuing of the operation, the signaling of an access error appears to be decoupled from the instruction that generated the write. accordingly, the pc contained in the exception stack frame merely represents the location in the program when the access error was signaled. all programming model updates associated with the write instruction are completed. the nop instruction can collect access errors for writes. this instruction delays its execution until all previous operations, including all pending write operations, are complete. if any previous write terminates with an access error, it is guaranteed to be reported on the nop instruction. 4.7.2 address error exception any attempted execution transferring control to an odd-byte instruction address (i.e., if bit 0 of the target address is set) results in an address error exception. any attempted use of a word-sized index register (xi.w) or a scale factor of 8 on an indexed effective addressing mode generates an address error as does an attempted execution of an instruction with a full-format indexed addressing mode. 4.7.3 illegal instruction exception on the version 2 coldfire microprocessor implementation, only certain illegal opcodes were decoded and generated an illegal instruction exception. however, the version 3 processor decodes the full 16-bit opcode and generates an illegal instruction exception if the execution of any non-supported instruction is attempted. additionally, if execution of any illegal line a or line f opcode is attempted, unique exception types are generated: vector numbers 10 and 11, respectively. coldfire processors do not provide illegal instruction detection on the extension words on any instruction, including movec. if execution of any instruction with an illegal extension word is attempted, the resulting operation is undefined. 4.7.4 privilege violation the attempted execution of a supervisor mode instruction while in user mode generates a privilege violation exception. see the coldfire microprocessor family programmer?s reference manual for lists of supervisor- and user-mode instructions. 4.7.5 trace exception to aid in program development, the coldfire processors provide an instruction-by- instruction tracing capability. while in trace mode, indicated by the assertion of the t-bit in the status register (sr[15] = 1), the completion of an instruction execution signals a trace exception. this functionality allows a software debugger to monitor program execution. the single exception to this definition is the stop instruction. if the processor is executing in trace mode, the instruction preceding the stop executes and then generates a trace exception. in the exception stack frame, the pc is pointing to the stop opcode. once the trace handler is exited, control returns to the stop instruction, which is then executed, f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
v3 cpu motorola version 3 coldfire core user?s manual 4-17 loading the sr with the immediate operand from the instruction. the processor then immediately generates a trace exception. the pc in the exception stack frame points to the instruction following the stop, and the sr reflects the just-loaded value. if the processor is not operating in trace mode, but executes a stop instruction where the immediate operand sets the trace bit in the sr, the hardware loads the sr, and then immediately generates a trace exception. the pc in the exception stack frame points to the instruction following the stop, and the sr reflects the just-loaded value. since coldfire processors do not support any hardware stacking of multiple exceptions, it is the responsibility of the operating system to check for trace mode after processing other exception types. as an example, consider the execution of a trap instruction while in trace mode. the processor initiates the trap exception and then passes control to the corresponding handler. if the system requires that a trace exception be processed, it is the responsibility of the trap exception handler to check for this condition (sr[15] in the exception stack frame asserted) and pass control to the trace handler before returning from the original exception. 4.7.6 debug interrupt this special type of program interrupt is discussed in detail in section 6: debug support . this exception is generated in response to a hardware breakpoint register trigger. the processor does not generate an iack cycle but rather calculates the vector number internally (vector number 12). additionally, the m-bit and the interrupt priority mask fields of the status register are unaffected by the occurrence of a debug interrupt. 4.7.7 rte and format error exceptions when an rte instruction is executed, the processor first examines the 4-bit format field to validate the frame type. for a coldfire processor, any attempted execution of an rte where the format is not equal to {4,5,6,7} generates a format error. the exception stack frame for the format error is created without disturbing the original exception frame and the stacked pc points to the rte instruction. the selection of the format value provides some limited debug support for porting code from 68000 applications. on m68000 family processors, the sr was located at the top of the stack. on those processors, bit[30] of the longword addressed by the system stack pointer is typically zero. thus, if an rte is attempted using this old format, it generates a format error on a coldfire processor. if the format field defines a valid type, the processor: (1) reloads the sr operand, (2) fetches the second longword operand, (3) adjusts the stack pointer by adding the format value to the auto-incremented address after the fetch of the first longword, and then (4) transfers control to the instruction address defined by the second longword operand within the stack frame. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
v3 cpu 4-18 version 3 coldfire core user?s manual motorola 4.7.8 trap instruction exceptions the trap #n instruction always forces an exception as part of its execution and is useful for implementing system calls. the trap instruction may be used to change from the user to supervisor mode. 4.7.9 non-supported instruction exceptions if a coldfire processor attempts to execute a valid instruction, but the required optional hardware module is not physically present in the operand execution pipeline, a non- supported instruction exception is generated (vector number 61). control is then passed to an exception handler which can then process the opcode as required by the system. 4.7.10 interrupt exception the interrupt exception processing, with interrupt recognition and vector fetching, includes uninitialized and spurious interrupts as well as those where the requesting device supplies the 8-bit interrupt vector. autovectoring may optionally be supported through the system bus controller. 4.7.11 fault-on-fault halt if a coldfire processor encounters any type of fault during the exception processing of another fault, the processor immediately halts execution with the catastrophic fault-on-fault condition. a reset is required to force the processor to exit this halted state. 4.7.12 reset exception asserting the reset input signal to the processor causes a reset exception. the reset exception has the highest priority of any exception; it provides for system initialization and recovery from catastrophic failure. reset also aborts any processing in progress when the reset input is recognized. processing cannot be recovered. the reset exception places the processor in the supervisor mode by setting the s-bit and disables tracing by clearing the t-bit in the sr. this exception clears the m-bit and sets the processor?s interrupt priority mask in the sr to the highest level (level 7). the branch prediction bit in the ccr is also cleared. next, the vbr is initialized to zero ($00000000). the control registers specifying the operation of any memories (e.g., cache, ram and rom modules) connected directly to the processor are disabled. refer to the specific sections covering those modules for more information. after the reset signal is negated, the processor waits for sixteen cycles before beginning the actual reset exception process. during this window of time, certain events are sampled, including the assertion of the debug breakpoint signal. if the processor is not halted, it then initiates the reset exception by performing two longword read bus cycles. the first longword at address 0 is loaded into the stack pointer and the second longword at address 4 is loaded into the program counter. after the initial instruction is fetched from memory, program execution begins at the address in the pc. if an access error or address error occurs before the first instruction is executed, the processor enters the fault-on-fault halted state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
v3 cpu motorola version 3 coldfire core user?s manual 4-19 4.8 integer data formats table 4-5 lists the integer operand data formats. integer operands can reside in registers, memory, or instructions. the operand size for each instruction is either explicitly encoded in the instruction or implicitly defined by the instruction operation. 4.9 organization of data in registers the following paragraphs describe data organization within the data, address, and control registers. 4.9.1 organization of integer data formats in registers figure 4-7 shows the integer format for data registers. each integer data register is 32 bits wide. byte and word operands occupy the lower 8- and 16-bit portions of integer data registers, respectively. longword operands occupy the entire 32 bits of integer data registers. a data register that is either a source or destination operand only uses or changes the appropriate lower 8 or 16 bits in byte or word operations, respectively. the remaining high-order portion does not change. the least significant bit (lsb) of all integer sizes is bit zero, the most significant bit (msb) of a longword integer is bit 31, the msb of a word integer is bit 15, and the msb of a byte integer is bit 7. because address registers and stack pointers are 32-bits wide, address registers cannot be used for byte-size operands. when an address register is a source operand, either the low- order word or the entire longword operand is used, depending on the operation size. when an address register is used, the entire register is affected, regardless of the operation size. if the source operand is a word size, it is sign-extended to 32 bits and then used in the table 4-5. integer data formats operand data format size bit 1 bit byte integer 8 bits word integer 16 bits longword integer 32 bits figure 4-7. organization of integer data formats in data registers lsb msb 10 31 30 bit (0 modulo (offse t < 31,offset of 0 = msb) < _ 0 7 31 byte 0 31 16-bit word 0 31 long word 15 low-order word long word lsb lsb msb msb lsb msb not used not used f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
v3 cpu 4-20 version 3 coldfire core user?s manual motorola operation to an address register destination. address registers are primarily for addresses and address computation support. control registers vary in size according to function. some control registers have undefined bits reserved for future definition by motorola. those particular bits read as zeros and must be written as zeros for future compatibility. all operations to the sr and ccr are word-size operations. for all ccr operations, the upper byte is read as all zeros and is ignored when written, regardless of privilege mode. 4.8.2 organization of integer data formats in memory all coldfire processors use a big-endian addressing scheme. the byte-addressable organization of memory allows lower addresses to correspond to higher order bytes. the address n of a longword data item corresponds to the address of the high order word. the lower order word is located at address n + 2. the address n of a word data item corresponds to the address of the high order byte. the lower order byte is located at address n + 1. this organization is shown in figure 4-8. 31 16 15 0 sign-extended 16-bit address operand 31 0 full 32-bit address operand figure 4-8. organization of integer data formats in address registers f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
v3 cpu motorola version 3 coldfire core user?s manual 4-21 4.10 addressing mode summary the addressing modes are grouped into categories according to the mode of use. data addressing modes refer to data operands. memory addressing modes refer to memory operands. alterable addressing modes refer to alterable (writable) operands. control addressing modes refer to memory operands without an associated size. these categories sometimes combine to form new categories that are more restrictive. two combined classifications are alterable memory (both alterable and memory) and data alterable (both alterable and data). table 4-6 lists a summary of effective addressing modes figure 4-9. memory operand addressing 31 23 15 7 0 byte $00000000 word $00000000 long word $00000000 byte $00000001 byte $00000002 byte $00000003 word $00000002 byte $00000004 word $00000004 long word $00000004 byte $00000005 byte $00000006 byte $00000007 word $00000006 byte $fffffffc word $fffffffc long word $fffffffc byte $fffffffd byte $fffffffe byte $ffffffff word $fffffffe f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
v3 cpu 4-22 version 3 coldfire core user?s manual motorola and their categories. twelve of the most commonly used addressing modes from the m68000 family are available on coldfire microprocessors. 4.11 instruction set summary table 4-7 lists the notational conventions used throughout this manual unless otherwise specified. table 4-8 lists the coldfire instruction set by opcode. this instruction set is a simplified version of the m68000 instruction set. the removed instructions include bcd, bit field, logical rotate, decrement and branch, and integer multiply with a 64-bit result. in addition, nine new mac instructions have been added. see appendix b for detailed information on the instruction execution times for the version 3 coldfire processor core. table 4-6. effective addressing modes and categories addressing modes syntax mode field reg. field category data memory control alterable register direct data address dn an 000 001 reg. no. reg. no. x ? ? ? ? ? x x register indirect address address with postincrement address with predecrement address with displacement (an) (an)+ e(an) (d 16 , an) 010 011 100 101 reg. no. reg. no. reg. no. reg. no. x x x x x x x x x ? ? x x x x x address register indirect with index 8-bit displacement (d 8 , an, xi) 110 reg. no. x x x x program counter indirect with displacement (d 16 , pc) 111 010 x x x ? program counter indirect with index 8-bit displacement (d 8 , pc, xi) 111 011 x x x ? absolute data addressing short long (xxx).w (xxx).l 111 111 000 001 x x x x x x ? ? immediate # 111 100 x x ? ? table 4-7. notational conventions opcode wildcards cc logical condition (example: ne for not equal) register operands an any address register n (example: a3 is address register 3) ay,ax source and destination address registers, respectively dn any data register n (example: d5 is data register 5) dy,dx source and destination data registers, respectively rn any address or data register ry,rx any source and destination registers, respectively rw any second destination register rc any control register (example: vbr is the vector base register) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
v3 cpu motorola version 3 coldfire core user?s manual 4-23 register/port names acc mac accumulator ddata debug data port ccr condition code register (lower byte of status register) macsr mac status register mask mask register pc program counter pst processor status port sr status register miscellaneous operands # immediate data following the instruction word(s) effective address y,x source and destination effective addresses, respectively
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