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TC9447F 2002-02-05 1 toshiba cmos digital integrated circuit silicon monolithic TC9447F single-chip audio digital signal processor the TC9447F is a single-chip audio digital signal processor incorporating an ad/da converter. the built-in program memory (rom) can contain a range of application programs for concert hall acoustic field simulation, for digital filters such as equalizers, and for dynamic range control. in addition, the device includes 64kb of data delay ram, making external ram unnecessary. features incorporates a 1-bit ? -type ad converter (two channels). thd: ? 82db, s/n ratio: 95db (typ.) incorporates a 1-bit ? -type da converter (four channels). thd: ? 85db, s/n ratio: 100db (typ.) a 10-db attenuator is built into the da converter output block (two channels only) each port has a digital input/output (three lead-type) a built-in self-boot function automatically sets the coefficients and register values at initialization. boot rom : 1024 words 18 bits the dsp block specifications are as follows: data bus : 24 bits multiplier/adder : 24 bits 16 bits + 43 bits 43 bits accumulator : 43 bits (sign extension: 4 bits) program rom : 1024 words 32 bits coefficient ram : 320 words 16 bits coefficient rom : 256 words 16 bits offset ram : 64 words 16 bits data ram : 256 words 24 bits operation speed : 44ns (510-step (approx) operation per cycle at fs = 44.1 khz) interface buffer ram : 32 words 16 bits incorporates data delay ram. delay ram : 4096 words 16 bits (64 kbits) the microcontroller interface can be selected between standard transmission mode and i 2 c bus mode. cmos silicon structure supports high speed. the package is a 100-pin flat package. weight: 1.57g (typ.)
TC9447F 2002-02-05 2 pin connection
TC9447F 2002-02-05 3 block diagram
TC9447F 2002-02-05 4 pin function pin no. symbol i/o function remarks 1 ecko o amp output pin for external clock input 2 ecki i amp input pin for external clock input pulled-down resistor (with on/off switching function) 3 gndx D ground pin for oscillator circuit 4 gndal D ground pin for dac l channel 5 aol o dac analog signal output pin (l channel) 6 vrl D dac reference voltage pin (l channel) 7 vdal D power pin for dac l channel 8 vdar D power pin for dac r channel 9 vrr D dac reference voltage pin (r channel) 10 aor o dac analog signal output pin (r channel) 11 gndar D ground pin for dac r channel 12 gndac D ground pin for dac c channel 13 aoc o dac analog signal output pin (c channel) 14 aoct o dac analog signal output pin with attenuator (c channel) 15 vrc D dac reference voltage pin (c channel) 16 vdac D power pin for dac c channel 17 vro o reference voltage pin for attenuator (buffer output) 18 vri i reference voltage pin for attenuator (buffer input) 19 vdas D power pin for dac s channel 20 vrs D dac reference voltage pin (s channel) 21 aost o dac analog signal output pin with attenuator (s channel) 22 aos o dac analog signal output pin (s channel) 23 gndas D ground pin for dac s channel 24 gnd D ground pin 25~29 tp0~tp4 o test pins (leave open) 30 vdd D power pin 31 vddr D power pin for dlram 32 gndr D ground pin for dlram 33~40 tp5~tp12 o test pins (leave open) 41 fs o clock output pin (1 fs) 42 cko0 o clock output pin 0 43 cko1 o clock output pin 1 44 gnd D ground pin 45 tp13 o test pin (leave open) 46 mck o mck clock output pin (256 fs/512 fs/ (384/768 fs) ) push-pull output 47 v dd D power pin 48~53 tp14~tp19 o test pin (leave open) 54 cks i master clock switching pin schmitt input 55 step0 i execution step switching pin 0 schmitt input 56 step1 i execution step switching pin 1 schmitt input 57 rst i reset pin schmitt input
TC9447F 2002-02-05 5 pin no. symbol i/o function remarks 58 v dd D power pin 59 sync i program sync signal input pin schmitt input 60 elro i lr clock input pin for serial data output schmitt input 61 elri i lr clock input pin for serial data input schmitt input 62 ebco i bit clock input pin for serial data output schmitt input 63 ebci i bit clock input pin for serial data input schmitt input 64 din i serial data input pin schmitt input 65 dout o serial data output pin push-pull output 66 em0 i de-emphasis setting pin 0 schmitt input 67 em1 i de-emphasis setting pin 1 schmitt input 68 iff0 i interface flag pin 0 schmitt input 69 iff1 i interface flag pin 1 schmitt input 70 iff2 i interface flag pin 2 schmitt input 71 gnd D ground pin 72 cs i microcontroller interface chip select signal input pin schmitt input 73 ifck i microcontroller interface data shift clock input pin schmitt input 74 ifdi i/o microcontroller interface data input pin (data input/output pin when i 2 c bus selected) schmitt input/ open drain output 75 ifdo o microcontroller interface data output pin (leave open when i 2 c bus selected.) push-pull output 76 ifok o microcontroller interface operation flag output pin open drain output 77 ack o microcontroller interface acknowledge output pin open drain output 78 err o microcontroller interface error flag output pin open drain output 79 i 2 cs i microcontroller interface i 2 c bus switching pin 80 boot i self-boot control pin schmitt input 81 ba0 i boot address setting pin 0 schmitt input 82 ba1 i boot address setting pin 1 schmitt input 83 vdd D power pin 84~87 tst0~tst3 i test pins. use fixed to low level. schmitt input 88 gnd D ground pin 89 vsal D ground pin for analog mode (adc l channel) 90 lin i adc analog signal input pin (l channel) 91 avrl D adc reference voltage pin (l channel) 92 vdl D power pin for analog mode (adc l channel) 93 vdr D power pin for analog mode (adc r channel) 94 avrr D adc reference voltage pin (r channel) 95 rin i adc analog signal input pin (r channel) 96 vsar D ground pin for analog mode (adc r channel) 97 gndx D ground pin for oscillator circuit 98 xi i crystal oscillator connecting pin (input) pulled-down resistor (with on/off switching function) 99 xo o crystal oscillator connecting pin (output) 100 vdx D power pin for oscillator circuit
TC9447F 2002-02-05 6 operation 1. pin operations pin no. symbol function 1 ecko 2 ecki supplies an external clock to ecki (for slave operations). when cks pin = h, oscillation activated. when cks = l, pulled down internally. 3~24 omitted D 25~40 tp [0:12] test pins (leave open) (tpx description is omitted.) 41 fs 1 fs output 42, 43 cko [1:0] timing output pins. the output frequency is set from the microcontroller. (cmd-40h) ckos0 ckos1 2 1 0 cko0 210 cko1 0 fixed to l (initial value) 0 fixed to l (initial value) 0 1 fs2 0 1fs2 0 fs4 0 fs4 0 1 1 fs8 0 1 1fs8 0 fs16 0 fs16 0 1 fs32 0 1 fs32 0 fs64 0 fs64 1 1 1 fs128 1 1 1 1/2 xi or 1/2 ecki 46 mck master clock output pin. output is validated/invalidated and the frequency is switched from the microcontroller. (cmd-4dh) mcke mck mcke step1 mck 0 fixed to l 0 don't care 256 fs 1 output valid (initial value) 0 source oscillation (xi/xo or ecki) 1 1 for testing 54 cks source oscillation selector pin cks source oscillation 0 xi/xo pin 1 ecki/ecko pin 55, 56 step [1:0] source oscillation frequency/asp operation speed switching pins step1 step0 source oscillation frequency no. of asp operation steps 0 512 fs 340/fs 0 1 768 fs 510/fs 1 * for testing * : don't care 57 rst reset input (l at initialization) 59 sync program operation sync signal input pin. valid when program is executing a slave operation. 60 elro lr clock signal input pin for serial output data. valid when serial data are output in a slave operation. 61 elri lr clock signal input pin for serial input data. valid when serial data are input in a slave operation. 62 ebco bit clock signal input pin for serial output data. valid when serial data are output in a slave operation. 63 ebci bit clock signal input pin for serial input data. valid when serial data are input in a slave operation.
TC9447F 2002-02-05 7 pin no. symbol function 64 din serial input data signal input pin. normally connected to internal register si2 in asp block. 65 dout serial output data signal output pin. normally connected to internal register so2 in asp block. 66, 67 em [1:0] de-emphasis control pins em1 em0 de-emphasis settings 0 de-emphasis off 0 1 for fs = 48 khz 0 for fs = 44.1 khz 1 1 for fs = 32 khz 68~70 iff [2:0] iff control input pins. this functions the same as the microcontroller iff [2:0] setting. the program uses the latest changes to the flags. 72 cs 73 ifck 74 ifdi 75 ifdo 76 ifok 77 ack 78 err 79 i 2 cs microcontroller interface pins standard transmission mode (i 2 cs = l) i 2 c mode (i 2 cs = h) i 2 cs transmit/receive mode switching (standard transmission mode/i 2 c mode) cs chip select (control required) chip select (can be fixed to l) ifck transmit/receive clock ifdi mcu data input mcu data input/output ifdo monitor data output fixed to l output ack acknowledge signal output fixed to hz err error flag signal output ifok internal operation confirmation flag signal output for details, see 2, microcontroller interface below. 80 boot self-boot select pin boot operation 0 does not boot at reset 1 boot at reset 81, 82 ba [1:0] self-boot start address pins (at reset) ba1 ba0 start address 0 000h 0 1 001h 0 002h 1 1 003h 84~87 tst [3:0] pins for inputting test settings. use fixed to l. 88~97 omitted D 98 xi 99 xo connect the crystal oscillator (master mode). setting cks = l enables oscillation. setting cks = h pulls down xi/xo using the internal resistor.
TC9447F 2002-02-05 8 2. microcontroller interface (1) standard transmission mode 1 when i 2 cs = l, data can be transmitted or received in standard transmission mode. when the cs signal is low, control from the microcontroller is enabled. the ifck signal is the transmit/receive clock. the ifdi signal is the data. the TC9447F loads the ifdi data on the ifck signal rising edge. when cs = h, the ifck and ifdi signals are don't care. (1-1) setting registers the registers are set by command data using the ifdi signal. the first byte is a command, which differs for each register. the data sent after that are fixed to two bytes. both command and data are sent starting from the msb. the ack signal is the acknowledge signal that the TC9447F returns to the microcontroller. because the ack signal is open drain output, it must be pulled up outside the pin. data are loaded on the rising edge of the ifck signal. note that commands or data that must be switched on the sync signal, such as the run command or the iff flag, must be synchronized with the sync signal and loaded on that signal. (1-2) setting ram (sequential) the rams are set by command data using the ifdi signal. the first byte is a command, which differs for each ram. the next two bytes contain the start address for the ram written. the length of the data field following the ram address bytes is 2 n bytes. the address is automatically incremented by 1.
TC9447F 2002-02-05 9 (1-3) setting ram (acmp mode) in acmp mode, the TC9447F does not write data directly to coefficient ram (cram) or offset ram (ofram). in this mode, data must first be written to the interface buffer ram (ifb-ram). then, all the data are updated together in a period of 1 fs. for example, if a signal flow filter is designed as in the following diagram, unless the k1 to k5 data are batch-updated, the circuit may resonate. the same applies to the k6 to k10 data. using acmp mode can reduce the noise caused by updating coefficients while the TC9447F is operating. this mode can suppress noise in almost all cases. ifb-ram is 32-word memory. therefore, data can be updated at one time in units of up to 32 words. the format of ifb-ram is similar to the format of the ram in 1-2 above. the length of the data field is 2 n bytes, where n 32. in acmp mode, the ifok pin outputs an acmp operation end flag. when acmp operations complete, the flag is set to low (1) and is initialized at the next low chip select cs signal (2).
TC9447F 2002-02-05 10 (1-4) monitor mode monitor mode is used to monitor the data bus or pointers. there are two further modes: a mode where the data bus or pointer (s) is monitored at a preset program counter (pc) and a mode where a loop counter (lc) is added to monitor conditions in addition to the pc. after the command is issued, when the TC9447F loads data to the ifdo register (ifdor), the ifok pin signal is set to low (see (1) above). next, when the ifck signal is sent, the data are output on the ifck signal falling edge starting from the msb. the data length is at its maximum (24 bits or three bytes) during monitoring of the data bus. in cases where transfer must be interrupted, such as where only eight or 16 bits of the msb side are required, monitoring can be interrupted at any time by setting the cs signal to high. when the cs signal goes high, the ifok signal also goes high. when cs = h, all monitor circuits are initialized.
TC9447F 2002-02-05 11 (2) standard transmission mode 2 when i 2 cs = l, data can be transmitted or received in standard transmission mode. when the cs signal is low, control from the microcontroller is enabled. the ifck signal is the transmit/receive clock. the ifdi signal is the data. the TC9447F loads the ifdi data on the ifck signal rising edge. when cs = h, the ifck and ifdi signals are don't care. (2-1) setting registers the registers are set by command data using the ifdi signal. the first byte is a command, which differs for each register. the data sent after that are fixed to two bytes. both command and data are sent starting from the msb. the ack signal is the acknowledge signal that the TC9447F returns to the microcontroller. as the ack signal is open drain output, it must be pulled up outside the pin. the data are loaded on the rising edge of the ifck signal. note that commands or data that must be switched on the sync signal, such as the run command or the iff flag, must be synchronized with the sync signal and loaded on that signal. (2-2) setting ram (sequential) the rams are set by command data using the ifdi signal. the first byte is a command, which differs for each ram. the next two bytes contain the start address for the ram written. the length of the data field following the ram address bytes is 2 n bytes. the address is automatically incremented by 1.
TC9447F 2002-02-05 12 (2-3) setting ram (acmp mode) in acmp mode, the TC9447F does not write data directly to coefficient ram (cram) or offset ram (ofram). in this mode, data must first be written to the interface buffer ram (ifb-ram). then, all the data are updated together in a period of 1 fs. for example, if a signal flow filter is designed as in the following diagram, unless the k1 to k5 data are batch-updated, the circuit may resonate. the same applies to the k6 to k10 data. using acmp mode can reduce the noise caused by updating coefficients while the TC9447F is operating. this mode can suppress noise in almost all cases. ifb-ram is 32-word memory. therefore, data can be updated at one time in units of up to 32 words. the format of ifb-ram is similar to the format of the ram in 2-2 above. the length of the data field is 2 n bytes, where n 32. in acmp mode, the ifok pin outputs an acmp operation end flag. when acmp operations complete, the flag is set to low (1) and is initialized at the next low chip select cs signal (2).
TC9447F 2002-02-05 13 (2-4) monitor mode monitor mode is used to monitor the data bus or pointers. there are two further modes: a mode where the data bus or pointer (s) is monitored at a preset program counter (pc) and a mode where a loop counter (lc) is added to monitor conditions in addition to the pc. after the command is issued, when the TC9447F loads data to the ifdo register (ifdor), the ifok pin signal is set to low (see (1) above). next, when the ifck signal is sent, data are output on the ifck signal falling edge from the msb first. the data length is at its maximum (24 bits or three bytes) during monitoring of the data bus. in cases where transfer must be interrupted, such as where only eight or 16 bits of the msb side are required, monitoring can be interrupted at any time by setting the cs signal to high. when the cs signal goes high, the ifok signal also goes high. when cs = h, all monitor circuits are initialized.
TC9447F 2002-02-05 14 (3) i 2 c bus mode when i 2 cs = h, data can be transmitted or received in standard transmission mode. when the cs signal is low, control from the microcontroller is enabled. in i 2 c mode, the cs signal can be used fixed to l. the ifck signal is the transmit/receive clock. the ifdi signal is the data. the TC9447F loads the ifdi data on the ifck signal rising edge. when cs = h, the ifck and ifdi signals are don't care. (3-1) setting registers the registers are set by command data using the ifdi signal. the first byte after the i 2 c address (32h) is a command, which differs for each register. the data sent after that are fixed to two bytes. both command and data are sent starting from the msb in i 2 c format. the ack pin cannot be used in i 2 c format. however, the acknowledge signal can be read by using data signals in i 2 c format. the data are loaded internally every two bytes. note that commands or data that must be switched on the sync signal, such as the run command or the iff flag, must be synchronized with the sync signal and loaded on that signal. (3-2) setting ram (sequential) the rams are set by command data using the ifdi signal. the first byte after the i 2 c address (32h) is a command, which differs for each ram. the next two bytes contain the start address for the ram to be written to. the length of the data field following the ram address bytes is 2 n bytes. the address is automatically incremented by 1.
TC9447F 2002-02-05 15 (3-3) monitor mode monitor mode is used to monitor the data bus or pointers. there are two further modes: a mode where the data bus or pointer (s) is monitored at a preset program counter (pc) and a mode where a loop counter (lc) is added to monitor conditions in addition to the pc. first, issue the monitoring command, which has no data. when the TC9447F loads data to the ifdo register (ifdor), the ifok pin signal is set to low (see (1) above). next, the i 2 c read command (id = 33h) is issued, then when the ifck signal is sent, the data are output on the ifck signal falling edge starting from the msb. the data length is at its maximum (24 bits or three bytes) during monitoring of the data bus. in cases where transfer must be interrupted, such as where only eight or 16 bits of the msb side are required, monitoring can be interrupted by sending the i 2 c end condition (set data level to h while the clock = h). after issuing a monitor command (50h~56h), be sure to perform a continuous read operation by issuing the i 2 c read command (id = 33h). (3-4) mcu does not write data by acmp mode at i 2 c bus controlling.
TC9447F 2002-02-05 16 (4) ifok pin description the ifok signal has the following three functions. (4-1) acmp mode end flag output after the completion of a ram data update with cram-acmp (cmd: 47h) or ofram-acmp (cmd: 49h), the ifok pin goes low. setting the cs signal to low changes the ifok signal from low to high. example: (4-2) loading end flag output in monitor mode when monitoring using the bus monitor command (cmd: 50h), for example, after data are loaded to the internal register under the specified conditions, the ifok signal goes low. in monitor mode, when the cs signal goes high, the ifok signal also goes high. example: (4-3) mute end flag output for digital filter (df) block when using a command to control the df block mute on/off (cmd: 36h, bit 5), the mute end flag is output from the ifok pin after the mute operation completes. example: note 1: at power on, the ifok pin output is undefined. when the cs signal goes low, the ifok signal goes high.
TC9447F 2002-02-05 17 3. control commands the following table lists the control commands that can be used from the microcontroller. (1) control commands table 1 control commands command code r/w description ram sequential transfer sync with/async to sync signal timing 40h timing D async boot 41h self-boot rom start address D async dac 42h dac output attenuator D async sio 43h sio setting D async run-mute 44h program execution, mute D sync (note 2) mseq 45h sequential ram sync (run)/async (stop) cram 46h cram sync (run)/async (stop) cram-acmp 47h cram (acmp mode) async ofram 48h ofram sync (run)/async (stop) ofram-acmp 49h ofram (acmp mode) enable async iff 4ah interface flag (iff) D sync (note 2) moni-pc 4bh monitor (pc conditions) D async moni-lc 4ch monitor (lc conditions) D async misc 4dh others D async D 4eh (prohibited) D D m-rst 4fh w initialization D async moni-db 50h db monitor D async moni-cp 51h cp monitor D async moni-ofp 52h ofp monitor D async moni-dp 53h dp monitor D async moni-ar 54h ar monitor D async moni-crp 55h crp monitor D async moni-sr 56h r sr monitor D async note 2: the command which is "sync" in the transfer sync with sync signal needs to set the cs = h section to a minimum of 1 fs more until it transmits the following command.(it needs more than 22.68 s at fs = 44.1 khz)
TC9447F 2002-02-05 18 (2) control commands command-40h (timing) 0100 0000 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sypd syd1 syd0 sypa sya1 sya0 syps sys1 sys0 unas- signed ckos1 2 ckos1 1 ckos1 0 ckos0 2 ckos0 1 ckos0 0 name description value operation 0 asp program starts on falling edge sypd digital block sync polarity switching 1 asp program starts on rising edge (initial value) 0 signal after sync output (initial value) 1 sync pin 2 elri pin syd [1:0] asp digital block sync signal input switching 3 elro pin 0 digital filter (df) program starts on falling edge (initial value) sypa analog block sync polarity switching 1 digital filter (df) program starts on rising edge 0 signal after sync output (initial value) 1 sync pin 2 elri pin sya [1:0] analog block sync signal input switching 3 elro pin 0 operates at polarity for sypd, sypa settings above (initial value). syps overall system sync polarity switching 1 reverses all polarities for sypd, sypa settings above. 0 internal sync signal (initial value) 1 sync pin 2 elri pin sys [1:0] sync circuit input switching 3 elro pin 0 fixed to l (initial value) 1 fs2 2 fs4 3 fs8 4 fs16 5 fs32 6 fs64 ckos1 [2:0] cko1 pin output selection 7 outputs xi or ecki clock divided by 2 0 fixed to l (initial value) 1 fs2 2 fs4 3 fs8 4 fs16 5 fs32 6 fs64 ckos0 [2:0] cko0 pin output selection 7 fs128
TC9447F 2002-02-05 19 command-41h (boot) 0100 0001 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 bta9 bta8 bta7 bta6 bta5 bta4 bta3 bta2 bta1 bta0 name description value operation bta [9:0] self-boot rom start address 000h ~ 3ffh starts self-boot operation from specified address. command-42h (dac) 0100 0010 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 attc4 attc3 attc2 attc1 attc0 0 0 0 atts4 atts3 atts2 atts1 atts0 name description value operation attc dac c channel attenuator value 00h ~ 1fh 00h 0db, 01h = ? 1db, 02h = ? 2db, , 15h~1fh = ? (initial value = 1fh= ) atts dac s channel attenuator value 00h ~ 1fh 00h 0db, 01h = ? 1db, 02h = ? 2db, , 15h~1fh = ? (initial value = 1fh = ? )
TC9447F 2002-02-05 20 command-43h (sio) 0100 0011 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 chsi 0 islt 1 islt 2 ibcs 1 ibcs 0 ifmt 1 ifmt 0 chso 1 chso 0 oslt 1 oslt 0 obcs 1 obcs 0 ofmt 1 ofmt 0 name description value operation 0 adc si0 register, din pin si1 register (initial value) chsi serial input switching 1 adc si1 register, din pin si0 register 0 16 bits/channel (initial value) 1 20 bits/channel 2 24 bits/channel islt [1:0] number of serial input slots 3 32 bits/channel 0 16 bits (initial value) 1 18 bits 2 20 bits ibcs [1:0] serial input bit length 3 24 bits 0 pads from the beginning (initial value) 1 pads from the end 2 ifmt [1:0] serial input format 3 i 2 s format 0 so0 register dout pin 1 so1 register dout pin 2 chso [1:0] serial output switching 3 so2 register dout pin (initial value = 2) 0 16 bits/channel (initial value) 1 20 bits/channel 2 24 bits/channel oslt [1:0] number of serial output slots 3 32 bits/channel 0 16 bits (initial value) 1 18 bits 2 20 bits obcs [1:0] serial output bit length 3 24 bits 0 pads from the beginning (initial value) 1 pads from the end 2 ofmt [1:0] serial output format 3 i 2 s format
TC9447F 2002-02-05 21 command-44h (run-mute) 0100 0100 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 run 0 df mute da mute imute so- mute omute 1 omute 0 name description value operation 0 stops program (initial value). run asp program execution 1 runs program. 0 mute off df mute df block mute 1 mute on (initial value) 0 mute off da mute dac mute (all four channels) 1 mute on (initial value) 0 mute off imute asp block input mute (si0, si1) 1 mute on (initial value) 0 mute off so- mute asp block serial output mute (mutes dout output whichever register is selected in chso.) 1 mute on (initial value) 0 mute off omute 1 asp block output mute (so1) 1 mute on (initial value) 0 mute off omute 0 asp block output mute (so0) 1 mute on (initial value) command-45h (mseq) 0100 0101 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 name description value operation msa [9:0] sequential ram address 000h ~ 3ffh set sequential ram. enable a sequential write to ram. command-46h (mseq) 0100 0110 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name description value operation d [15:0] cram 0000h ~ ffffh set cram. enable a sequential write to ram.
TC9447F 2002-02-05 22 command-47h (cram-acmp) 0100 0111 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name description value operation d [15:0] cram-acmp 0000h ~ ffffh set cram in acmp mode. command-48h (ofram) 0100 1000 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name description value operation d [15:0] ofram 0000h ~ ffffh set ofram. enable a sequential write to ram. command-49h (ofram-acmp) 0100 1001 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name description value operation d [15:0] ofram-acmp 0000h ~ ffffh set ofram in acmp mode. command-4ah (iff) 0100 1010 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 0 0 0 0 0 iff2 iff1 iff0 name description value operation 0 iffn = 0 (initial value) iff [2:0] interface flag (iff) 1 iffn = 1
TC9447F 2002-02-05 23 command-4bh (moni-pc) 0100 1011 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 i2cos 1 i2cos 0 0 0 0 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 name description value operation i2cos [1:0] monitor data length in i 2 c mode 0h ~ 3h set the data byte length when monitoring in i 2 c mode. (3 = 3 byte, 2 = 2 byte, 1 or 0 = 1 byte) a [9:0] monitor conditions (pc: program counter) 000h ~ 3ffh set the pc conditions when monitoring. command-4ch (moni-lc) 0100 1100 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 lce lcs lcde lca7 lca6 lca5 lca4 lca3 lca2 lca1 lca0 name description value operation 0 does not add lc value to the conditions (initial value). lce adds the lc (loop counter) value to the monitor conditions. 1 adds lc value to the conditions. 0 compares with lc0 value. lcs lc selection 1 compares with lc1 value. 0 after a match, does not change the value to be compared with the lc. lcde automatic lc decrement 1 after a match, automatically decrements by 1 the value to be compared with the lc. lca [7:0] monitor conditions (lc) 00h ~ ffh set the value to be compared with the lc.
TC9447F 2002-02-05 24 command-4dh (misc) 0100 1101 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 sis sos erdet zst dp7f syrc syro mcke mcks dlsep dlac4 name description value operation 0 master (lrck = fs, bck = fsxx) (initial value) sis serial input 1 slave (lrck = elri, bck = ebci) 0 master (lrck = fs, bck = fsxx) (initial value) sos serial output 1 slave (lrck = elro, bck = ebco) 0 invalid erdet error detection 1 valid (initial value) 0 2-cycle access zst switches to access crom using log-lin adjustment. 1 1-cycle access (initial value) 0 256 words (initial value) dp7f data-ram 128/256 word switching 1 128 words 0 does not initialize. syrc initializes cp at each sync. 1 initializes (initial value). 0 does not initialize. syro initializes ofp at each sync 1 initializes (initial value). 0 fixes to l mcke mck pin output enable 1 output (initial value) 0 256 fs mcks mck pin output switching 1 when step1 pin = 0, outputs source oscillation (initial value). when step1 pin = 1, used for testing. 0 does not use table. dlsep delay ram table area switching 1 uses 2-k word area as the table (initial value). 0 one access/6 cycles (initial value) dlac4 delay ram access method 1 one access/4 cycles command-4fh (m-rst) 0100 1111 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mrst 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 name description value operation 0 does not initialize. mrst initialization from the microcontroller 1 initializes (after initialization, automatically set to 0).
TC9447F 2002-02-05 25 command-50h (mon-db) 0101 0000 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name description value operation d [23:0] data bus monitor 000000h~ffffffh reads data bus on the condition cmd: 4bh, 4ch. command-51h (mon-cp) 0101 0001 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 0 000000cp8cp7cp6cp5 cp4 cp3 cp2 cp1cp0 name description value operation cp [8:0] cp monitor 000000h~00013h reads cp on the condition cmd: 4bh, 4ch. command-52h (mon-ofp) 0101 0010 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 0 000000000 ofp 5 ofp 4 ofp 3 ofp 2 ofp 1 ofp 0 name description value operation ofp [5:0] ofp monitor 000000h~00003h reads ofp on the condition cmd: 4bh, 4ch. command-53h (mon-bp) 0101 0011 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 0 0 0 0 bp 11 bp 10 bp 9 bp 8 bp 7 bp 6 bp 5 bp 4 bp 3 bp 2 bp 1 bp 0 name description value operation bp [11:0] bp monitor 000000h~000fffh reads bp on the condition cmd: 4bh, 4ch. command-54h (mon-ar) 0101 0100 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 0 0 0 0 ar 11 ar 10 ar 9 ar 8 ar 7 ar 6 ar 5 ar 4 ar 3 ar 2 ar 1 ar 0 name description value operation ar [11:0] delay ram address monitor 000000h~000fffh reads delay ram address on the condition cmd: 4bh, 4ch.
TC9447F 2002-02-05 26 command-55h (mon-crp) 0101 0101 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 0 000000 crp 8 crp 7 crp 6 crp 5 crp 4 crp 3 crp 2 crp 1 crp 0 name description value operation crp [8:0] crp (lin-log adjustment pointer) monitor 000000h~0001ffh reads crp on the condition cmd: 4bh, 4ch. command-56h (mon-sr) 0101 0110 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 0 lrf gf3 gf2 gf1 gf0 li lg lg li ov 1e ov 0e rd 24 rd 16 v1f v0f zf sf name description value operation sr sr (status register) monitor D reads sr on the condition cmd: 4bh, 4ch.
TC9447F 2002-02-05 27 4. self-boot function description (1) self-boot function the TC9447F supports a self-boot function for setting coefficients and offsets. as figure 1 shows, the data are set via the microcontroller interface circuit. first saving the data to be set via the microcontroller in the self-boot rom (sbrom) allows various modes to be set later. the microcontroller interface circuit supports two formats: i 2 c and the original mode. however, the boot must be executed in standard transmission (the original) mode. figure 1 self-boot system (2) boot rom format the following shows the breakdown of the 18 bits. 00 data that are being sent 01 command 10 final data (after the data are sent, the cs signal is set to ?h?). 11 jump address (jump to any address in the self-boot rom). figure 2 boot rom format and example boot mode completes when the address reaches 3ffh, the maximum value. therefore, for the final address, write jmp 3ffh (data = 303ffh).
TC9447F 2002-02-05 28 (3) self-boot operation self-boot operations support two modes: one for use at reset and one for setting the microcontroller. the modes can be used in combination. (3-1) self-boot operation at reset to enter this mode, set the boot pin to high, then set the rst pin from low to high. the 2048 fs period (46.4 ms when fs = 44.1 khz) after a reset release is a wait period (for power-on reset). the boot operation starts at the end of this period. when switching the setting according to the application, specify the start address using the ba [1:0] pin. at addresses 000h to 002h, set jump addresses. the data setting speed is one word of sbrom per 1 fs. as up to 1024 words can be set in the sbrom, the maximum time required for setting the data is half of the wait period. table 2 relationship between fs and wait period fs wait period boot time (maximum) 32 khz 64.0 ms 32.0 ms 44.1 khz 46.4 ms 23.2 ms 48 khz 42.7 ms 21.3 ms table 3 relationship between ba [1:0] pin value and start address ba1 ba0 start address 0 0 000h 0 1 001h 1 0 002h 1 1 003h (3-2) self-boot operation when setting microcontroller in this mode, the microcontroller can specify any address and the operation starts from that address. the boot pin can be set to either high or low. setting the self-boot rom start address using the boot command (cmd: 41h) from the microcontroller starts the boot operation with no wait. the boot operation when set from the microcontroller is the same as the self-boot operation at reset except that the boot operation can start from any address.
TC9447F 2002-02-05 29 figure 3 boot timing chart (at reset)
TC9447F 2002-02-05 30 table 4 differences depending on operating mode parameter boot mode at reset boot mode set from microcontroller boot wait period yes no boot start address select from 000h to 003h any address specified from microcontroller boot pin ?h? level don't care (4) programming examples
TC9447F 2002-02-05 31 (5) code format example the following shows the format for storing data in sbrom.
TC9447F 2002-02-05 32 5. cautions on use (1) the cautions at the time of using ifok terminal the timing which outputs ifok signal is the signal which shows whether the command received from the microcomputer was performed normally. since the initial value of ifck signal is unfixed when a control microcomputer is checking ifok signal, before sending a command, it may stop performing control from a microcomputer. (2) the cautions at the time of using acmp (address comparing mode) in rewriting coefficient data and offset data using acmp mode, please do not use it the following condition. (2-1) please do not transmit the following command before completing rewriting of data. please do not send the following command before completing rewriting of data of cram or ofram. please check that waiting the term after rewriting of data is completed until it transmits the following command was carried out, or rewriting has been completed using ifok signal. (2-2) please do not include data of an intact address. please do not include coefficient data of offset data of an address which are not used by the program under execution, into transmitting data. when data of an intact address is contained, operation in acmp mode cannot be ended. if the following command is transmitted in this state, ram data will become unfixed also by the command with the command unrelated to cram or ofram. it needs to reset and all data needs to be re-set up to interrupt before completing rewriting of data in the rewriting processing. (2-3) please do not perform continuation transmission over the 0th address. the transmission over the 0th address may incorrect-operate. the same of this restriction is said not only of acmp mode but continuation transmission of usual ram data. for example, when writing in 007h from 1bfh and 000h from 1b8h of cram, it must transmit in 2 steps. (3) the following cautions are required when transmitting a reset command and a boot command in the cautions i 2 c bus mode at the time of using the i 2 c bus mode. (3-1) at the time of reset command use when transmitting a reset command (4fh: m-rst) from a microcomputer, the acknowledgement signal in front of the end conditions outputted from ifdi terminal is not transmitted to a microcomputer. therefore, the acknowledgement signal of the last of ifdi signal should repeal at the time of reset command transmission. the timing at the time of reset command transmission is shown if figure 4. figure 4 timing at the time of command transmission
TC9447F 2002-02-05 33 (3-2) at the time of self boot command use when a self boot command (41h: boot) is transmitted, even if end conditions happen to the acknowledgement signal of the last of boot command data, please repeal. if it becomes the boot mode, data will be transmitted internal boot rom data using the internal circuit of a microcomputer interface. data is transmitted not in the i 2 c bus mode but in the standard transmitting mode at the time of boot mode operation in that case. therefore, ifdi terminal will be in the state of h level, and operation of an i 2 c bus and conditions may not be performed normally. the timing at the time of self boot command transmission is shown if figure 5. figure 5 timing at the time of self boot command transmission
TC9447F 2002-02-05 34 peripheral circuit example 1 (standard transmission mode) the circuit below is an example circuit only. the operation of this circuit is not guaranteed by toshiba.
TC9447F 2002-02-05 35 peripheral circuit example 2 (i 2 c bus mode) the circuit below is an example circuit only. the operation of this circuit is not guaranteed by toshiba.
TC9447F 2002-02-05 36 maximum ratings (ta = 25c) characteristics symbol rating unit power supply voltage v dd ? 0.3~6.0 v input voltage v in ? 0.3~v dd + 0.3 v power dissipation p d 1500 mw operating temperature t opr ? 40~75 (note 3) c storage temperature t stg ? 55~150 c note 3: only when frequency of operation is 340 step mode, a temperature of operation becomes ta = ? 40~85c. electrical characteristics (unless otherwise noted, ta = 25c, v dd = v dx = v ddr = v dl = v dr = v dal = v dar = v dac = v das = 5 v) dc characteristics characteristics symbol test circuit test condition min typ. max unit operating power supply voltage v dd D ta = ? 40~75c 4.5 5.0 5.25 v 340-step mode 8 15 25 operating frequency range f opr D 511-step mode 12 33.8 34 mhz operating power supply current i dd D f opr = 33.8688 mhz 511-step mode D 135 140 ma clock pins (xi, xo, ecki, ecko) characteristics symbol test circuit test condition min typ. max unit ?h? level v ih1 D 3.5 D D input voltage (1) ?l? level v il1 D xi, ecki pin D D 1.5 v ?h? level v oh1 D i oh = ? 3.0 ma 4.5 D D output voltage (1) ?l? level v ol1 D i ol = 5.0 ma xo, ecko pin D D 0.5 v pull-down resistance r xd D xi, ecki pin D 3.0 5.0 k ? input pins characteristics symbol test circuit test condition min typ. max unit ?h? level v ih2 D 4.2 D D input voltage (2) ?l? level v il2 D (note 4) D D 0.8 v ?h? level i ih2 D v in = v dd D D 10 input leakage current ?l? level i il2 D v in = 0 v (note 4) ? 10 D D a ?h? level v p D D 2.8 D threshold voltage ?l? level v n D (note 5) D 2.0 D v hysteresis voltage v h D (note 5) D 0.8 D v note 4: cks, step0, step1, rst , sync, elro, elri, ebco, ebci, din, em0, em1, i 2 cs, cs , ifck, ifdi, boot, ba0, ba1, tst0~3 (normally input pins and schmitt input pins) note 5: pins excluding i 2 cs pins in note 1 above (schmitt input pins)
TC9447F 2002-02-05 37 output pins characteristics symbol test circuit test condition min typ. max unit ?h? level v oh2 D i oh = ? 2.0 ma 4.5 D D output voltage (2) ?l? level v ol2 D i ol = 2.0 ma (note 6) D D 0.5 v ?h? level v oh3 D i oh = ? 4.0 ma 4.5 D D output voltage (3) ?l? level v ol3 D i ol = 4.0 ma (note 7) D D 0.5 v output voltage (4) ?l? level v ol4 D i ol = 4.0 ma D D 0.5 v output open leakage current i oz4 D v oh = v dd (note 8) D D 10 a note 6: fs, cko0, cko1, mck, dout (normally output) note 7: ifdo (normally output) note 8: ifdi (when i 2 c mode output), ifok, ack , err (open drain output)
TC9447F 2002-02-05 38 ac characteristics (1) analog ad converter characteristics characteristics symbol test circuit test condition min typ. max unit maximum input signal level v i D input level that adc digital output does not overflow (note 9) 1.13 1.20 D vrms input impedance z in D lin, rin pins (note 9) D 27.0 D k ? s/n a1 D a-weight, when using x'tal oscillator at 33.8688 mhz (note 9) 90 98 D s/(n + d) ratio s/n a2 D ccir-arm, when using x'tal oscillator at 33.8688 mhz (note 9) 88 94 D db thd + n thd a D 20 khz lpf, when using x'tal oscillator at 33.8688 mhz (note 9) D ? 77 ? 70 db crosstalk ct a D a-weight, when using x'tal oscillator at 33.8688 mhz (note 9) D ? 95 ? 88 db dynamic range dr a D a-weight, when using x'tal oscillator at 33.8688 mhz (note 9) D 95 90 db note 9: input channels: lin, rin da converter characteristics characteristics symbol test circuit test condition min typ. max unit v o1 D output voltage at full-scale digital input (note 10) 1.10 1.21 1.32 output signal level v o2 D output voltage at full-scale digital input (trim output) (note 11) 1.35 1.52 1.61 vrms trim output pin: attenuation level vo al D (note 11) 0 D ? 20 db trim output pin: step level vo as D (note 11) D 1 D db s/n ratio s/n d D a-weight, when using x'tal oscillator at 33.8688 mhz (note 12) 90 100 D db thd d1 D 20 khz, when using x'tal oscillator at 33.8688 mhz (note 10) D ? 87 ? 80 thd+n thd d2 D 20 khz, when using x'tal oscillator at 33.8688 mhz (note 11) D ? 82 ? 75 db crosstalk ct d D a-weight, when using x'tal oscillator at 33.8688 mhz (note 12) D ? 95 ? 88 db dynamic range dr d D a-weight, when using x'tal oscillator at 33.8688 mhz (note 12) D 95 90 db note 10: output channel: aol, aor, aoc, aos note 11: output channel: aoct, aost note 12: output channel: aol, aor, aoc, aos, aoct, aost
TC9447F 2002-02-05 39 ac characteristics (2) timing clock input pins (xi, ecki) characteristics symbol test circuit test condition min typ. max unit clock cycle t xi D D 29 D D ns clock ?h? cycle width t xih D D D 14.5 D ns clock ?l? cycle width t xil D D D 14.5 D ns reset pin ( rst ) characteristics symbol test circuit test condition min typ. max unit standby time t rrs D D 10 D D ms reset pulse width t wrs D D 1.0 D D s timing output characteristics symbol test circuit test condition min typ. max unit cko output delay time t dfc D D ? 150 D 150 ns audio serial interface (ebci, din, ebco, dout) characteristics symbol test circuit test condition min typ. max unit elri hold time t lih D c l = 30 pf ? 75 D 75 ns din setup time t sdi D c l = 30 pf 50 D D ns din hold time t hdi D c l = 30 pf 50 D D ns ebci clock cycle t ebci D c l = 30 pf 300 D D ns ebci clock ?h? cycle width t ebih D c l = 30 pf 150 D D ns ebci clock ?l? cycle width t ebil D c l = 30 pf 150 D D ns elro hold time t loh D c l = 30 pf ? 75 D 75 ns dout output delay time (1) t do1 D c l = 30 pf D D 60 ns dout output delay time (2) t do2 D c l = 30 pf D D 60 ns ebco clock cycle t ebco D c l = 30 pf 300 D D ns ebco clock ?h? cycle width t eboh D c l = 30 pf 150 D D ns ebco clock ?l? cycle width t ebol D c l = 30 pf 150 D D ns
TC9447F 2002-02-05 40 microcontroller interface standard transmission mode ( cs , ifck, ifdi, ifdo, a c k ) characteristics symbol test circuit test condition min typ. max unit standby time t stb D 1.0 D D s cs - ifck setup time (mode 1) t ccd D 0.5 D D s ifck ?l? cycle width t wlc D 0.5 D D s ifck ?h? cycle width t whc D 0.5 D D s ifck - cs setup time t ckc D 0.5 D D s cs ?h? cycle width t wcs D (note 13) 1.0 D D s ifck - cs setup time (mode 2) t ccu D 0.5 D D s ifck - cs setup time t sck D 0.5 D D s ifdi - ifck setup time t scd D 0.5 D D s ifck - ifdi hold time t hcd D 0.5 D D s ifck - ifdo propagation delay time t ddo D c l = 30 pf D D 0.5 s ifck - ack propagation delay time t dakd D c l = 30 pf (pull-up resistor) r l = 1 k ? D D 0.5 s ifck - ack propagation delay time t dakz D c l = 30 pf (pull-up resistor) r l = 1 k ? D D 0.5 s note 13: the command which is "sync" in the transfer sync with sync signal of a 17 page table 1 control command table needs to set the cs = h section to a minimum of 1 fs more until it transmits the following command.(it needs more than 22.68 s at fs = 44.1 khz) i 2 c mode ( cs , ifck, ifdi) characteristics symbol test circuit test condition min typ. max unit ifck clock frequency f ifck D c l = 400 pf 0 D 400 khz ifck ?h? cycle width t h D c l = 400 pf 0.6 D D s ifck ?l? cycle width t l D c l = 400 pf 1.3 D D s data setup time t ds D c l = 400 pf 0.1 D D s data hold time t dh D c l = 400 pf 0 D D s transmission start condition hold time t sch D c l = 400 pf 0.6 D D s repeat transmission start condition setup time t scs D c l = 400 pf 0.6 D D s transmission end condition setup time t ecs D c l = 400 pf 0.6 D D s data transmission interval t buf D c l = 400 pf 1.3 D D s i 2 c rise time t r D c l = 400 pf D D 0.3 s i 2 c fall time t f D c l = 400 pf D D 0.3 s
TC9447F 2002-02-05 41 ac characteristics test points 1. clock pins (xi, ecki) 2. reset 3. timing output 4. audio serial interface (elri, ebci, din, elro, ebco, dout)
TC9447F 2002-02-05 42 5. microcontroller interface in standard transmission mode ( cs , ifck, ifdi, ifdo, a c k ) 6. microcontroller interface in i 2 c mode (ifck, ifdi) purchase of toshiba i 2 c components conveys a license under the philips i 2 c patent right to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips.
TC9447F 2002-02-05 43 package dimensions weight: 1.57 g (typ.)
TC9447F 2002-02-05 44 toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. the products described in this document are subject to the foreign exchange and foreign trade laws. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. the information contained herein is subject to change without notice. 000707eb a restrictions on product use

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