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mos integrated circuit m m m m pd16715a 384-output tft-lcd source driver (compatible with 64-gray scales) ? 1998,1999 document no. s13944ej2v0ds00 (2nd edition) date published december 1999 ns cp(k) printed in japan data sheet the mark ? ? ? ? shows ma j or revised p oints. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. description the m pd16715a is a source driver for tft-lcds capable of dealing with displays with 64-gray scales. data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values g -corrected by an internal d/a converter and 5-by-2 external power modules. because the output dynamic range is as large as v ss2 + 0.1 v to v dd2 C 0.1 v, level inversion operation of the lcds common electrode is rendered unnecessary. also, to be able to deal with dot-line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit d/a converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. assuring a maximum clock frequency of 55 mhz when driving at 3.0 v, this driver is applicable to xga/sxga-standard tft-lcd panels. features ? cmos level input ? 384 outputs ? input of 6 bits (gradation data) by 6 dots ? capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a d/a converter ? logic power supply (v dd1 ): 3.3 v 0.3 v ? driver power supply (v dd2 ): 11.0 v v ? high-speed data transfer: f clk = 55 mhz (internal data transfer speed when operating at 3.0 v) ? output dynamic range v ss2 + 0.1 v to v dd2 C 0.1 v ? apply for only dot-line inversion ? single bank arrangement is possible (pol) ? display data inversion function (pol2) ? low power control function (lpc) ? single-sided mounting (slim tcp) ordering information part number package m pd16715an- xxx tcp (tab pack age) remark the tcps external shape is customized. to order your tcps external shape, please contact an nec salesperson. + 2.5 C 2.0 ? ? ? ?
data sheet s13944ej2v0ds00 2 m m m m pd16715a 1. block diagram 64-bit bidirectional shift register c 1 c 2 c 63 c 64 data register latch level shifter d/a converter voltage follower output s 1 s 2 s 3 s 384 v 0 to v 9 pol d 00 to d 05 d 10 to d 15 d 20 to d 25 sthr r,/l clk stb sthl v dd1 v ss1 v dd2 v ss2 pol2 d 30 to d 35 d 40 to d 45 d 50 to d 55 lpc remark /xxx indicates active low signal. 2. relationship between output circuit and d/a converter v 0 v 4 v 5 v 9 5 5 s 1 s 2 s 383 s 384 6-bit d/a converter multi- plexer pol
data sheet s13944ej2v0ds00 3 m m m m pd16715a 3. pin configuration ( m m m m pd16715an- ) remark this figure does not specify the tcp package. s 384 s 383 v ss2 s 382 v dd2 s 381 r , /l pol stb d 55 d 54 d 53 d 52 d 51 d 50 d 45 d 44 d 43 d 42 d 41 d 40 d 35 d 34 d 33 d 32 d 31 d 30 sthl v 9 v 8 v 7 v 6 v 5 v 4 v 3 v 2 v 1 v 0 v dd1 clk v ss1 pol2 sthr d 25 d 24 d 23 d 22 d 21 d 20 d 15 d 14 d 13 d 12 d 11 d 10 d 05 d 04 d 03 d 02 d 01 d 00 s 4 lpc s 3 test s 2 v dd2 s 1 v ss2 copper foil surface
data sheet s13944ej2v0ds00 4 m m m m pd16715a 4. pin functions (1/2) pin symbol pin name description s 1 to s 384 driver output the d/a converted 64-gray scale analog voltage is output. d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 d 40 to d 45 d 50 to d 55 display data input the display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2 pixels). d x0 : lsb, d x5 : msb r,/l shift direction control input these refer to the start pulse input/output pins when driver ics are connected in cascade. the shift directions of the shift registers are as follows. r,/l = h: sthr input, s 1 ? s 384 , sthl output r,/l = l : sthl input, s 384 ? s 1 , sthr output sthr right shift start pulse input/output r,/l = h: becomes the start pulse input pin. r,/l = l : becomes the start pulse output pin. sthl left shift start pulse input/output r,/l = h: becomes the start pulse output pin. r,/l = l : becomes the start pulse input pin. clk shift clock input refers to the shift registers shift clock input. the display data is incorporated into the data register at the rising edge. at the rising edge of the 64th clock after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. the initial-level drivers 64th clock becomes valid as the next-level drivers start pulse is input. if 66 clock pulses are input after input of the start pulse, input of display data is halted automatically. the contents of the shift register are cleared at the stbs rising edge. stb latch input the contents of the data register are transferred to the latch circuit at the rising edge. and, at the falling edge, the gray scale voltage is supplied to the driver. it is necessary to ensure input of one pulse per horizontal period. pol polarity input pol = l: the s 2nC1 output uses v 0 to v 4 as the reference supply ; the s 2n output uses v 5 to v 9 as the reference supply. pol = h : the s 2nC1 output uses v 5 to v 9 as the reference supply ; the s 2n output uses v 0 to v 4 as the reference supply. s 2n-1 indicates the odd output: and s 2n indicates the even output. input of the pol signal is allowed the setup time (t pol - stb ) with respect to stbs rising edge. pol2 data inversion pol2 = h : display data is inverted. pol2 = l : display data is not inverted lpc driver voltage selection the output buffer constant current source is blocked, reducing current consumption. low power mode (lpc = h: dc-level input possible). the condition that low power mode can be used is that the load constant is at least 10 k w + 50 pf. v 0 to v 9 g -corrected power supplies input the g -corrected power supplies from outside by using operational amplifier. make sure to maintain the following relationships. during the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. v dd2 C 0.1 v > v 0 > v 1 > v 2 > v 3 > v 4 > v 5 > v 6 > v 7 > v 8 > v 9 > v ss2 + 0.1 v test test pin test pin. please input h or open. v dd1 logic power supply 3.3 v 0.3 v v dd2 driver power supply 11.0 v v v ss1 logic ground grounding v ss2 driver ground grounding + 2.5 - 2. 0
data sheet s13944ej2v0ds00 5 m m m m pd16715a cautions 1. the power start sequence must be v dd1 , logic input, and v dd2 & v 0 to v 9 in that order. reverse this sequence to shut down. (simultaneous power application to v dd2 and v 0 to v 9 is possible.) 2. to stabilize the supply voltage, please be sure to insert a 0.47 m m m m f bypass capacitor between v dd1 -v ss1 and v dd2 -v ss2 . furthermore, for increased precision of the d/a converter, insertion of a bypass capacitor of about 0.01 m m m m f is also advised between the g g g g -corrected power supply terminals (v 0 , v 1 , v 2 , , v 9 ) and v ss2 . 5. relationship between input data and output voltage value the m pd16715a incorporates a 6-bit d/a converter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the lcd's counter electrode (common electrode) voltage. the d/a converter consists of ladder resistors and switches. the ladder resistors r 0 to r 62 are so designed that the ratios between the lcd panel's g - corrected voltages and v 0' to v 63' and v 0" to v 63" are roughly equal; and their respective resistance values are as shown on next page. among the 5-by-2 g -corrected voltages, input gray scale voltages of the same polarity with respect to the common voltage, for the respective five g -corrected voltages of v 0 to v 4 and v 5 to v 9 figure 5-1 shows the relationship between the driving voltages such as liquid-crystal driving voltages v dd2 and v ss2 , common electrode potential v com , and g - corrected voltages v 0 to v 9 and the input data. be sure to maintain the voltage relationships of v dd2 C 0.1 v > v 0 > v 1 > v 2 > v 3 > v 4 > v 5 > v 6 > v 7 > v 8 > v 9 > v ss2 + 0.1 v. figures 5-2 and 5-3 show the relationship between the input data and the output voltage. therefore, please do not use it for g - corrected power supply level inversion in double-sided mounting. figure 5 - - - - 1. relationship between input data and g g g g - corrected power supply 0.1 v 0.1 v v dd2 v 0 v 1 v 2 v 3 v 4 v 5 v 6 v 7 v 8 v com v 9 v ss2 00 08 20 38 3f input data (hex) 24 7 7 24 8 8 24 24 split interval
data sheet s13944ej2v0ds00 6 m m m m pd16715a figure 5 - - - - 2. relationship between input data and output voltage (1/2) v dd2 C 0.1 v > v 0 > v 1 > v 2 > v 3 > v 4 v 0 v 1 v 2 v 3 v 4 v 5 v 6 v 7 v 8 v 9 v 31 v 32 v 33 v 55 v 56 v 57 v 58 v 59 v 60 v 61 v 62 v 63 v 0 r 0 r 1 r 2 r 3 r 4 r 5 r 6 r 7 v 1 r 8 r 9 r 30 r 31 v 2 r 32 r 33 r 54 r 55 v 3 r 56 r 57 r 58 r 59 r 60 r 61 r 62 v 4 v 63 v 62 v 61 v 5 r 62 r 61 r 60 data d x5 d x4 d x3 d x2 d x1 d x0 00h 000000v 0 'v 0 r0 800 01h 000001v 1 'v 1 +(v 0 -v 1 ) 4300 / 5100 r1 750 02h 000010v 2 'v 1 +(v 0 -v 1 ) 3550 / 5100 r2 700 03h 000011v 3 'v 1 +(v 0 -v 1 ) 2850 / 5100 r3 650 04h 000100v 4 'v 1 +(v 0 -v 1 ) 2200 / 5100 r4 600 05h 000101v 5 'v 1 +(v 0 -v 1 ) 1600 / 5100 r5 550 06h 000110v 6 'v 1 +(v 0 -v 1 ) 1050 / 5100 r6 550 07h 000111v 7 'v 1 +(v 0 -v 1 ) 500 / 5100 r7 500 08h 001000v 8 'v 1 r8 500 09h 001001v 9 'v 1 +(v 0 -v 1 ) 5200 / 5700 r9 400 0ah 001010v 10 'v 1 +(v 0 -v 1 ) 4800 / 5700 r10 400 0bh 001011v 11 'v 1 +(v 0 -v 1 ) 4400 / 5700 r11 350 0ch 001100v 12 'v 1 +(v 0 -v 1 ) 4050 / 5700 r12 350 0dh 001101v 13 'v 1 + ( v 0 -v 1 ) 3700 / 5700 r13 350 0eh 001110v 14 'v 1 +(v 0 -v 1 ) 3350 / 5700 r14 300 0fh 001111v 15 'v 1 +(v 0 -v 1 ) 3050 / 5700 r15 300 10h 010000v 16 'v 1 +(v 0 -v 1 ) 2750 / 5700 r16 300 11h 010001v 17 'v 2 +(v 1 -v 2 ) 2450 / 5700 r17 250 12h 010010v 18 'v 2 +(v 1 -v 2 ) 2200 / 5700 r18 250 13h 010011v 19 'v 2 +(v 1 -v 2 ) 1950 / 5700 r19 250 14h 010100v 20 'v 2 +(v 1 -v 2 ) 1700 / 5700 r20 200 15h 010101v 21 'v 2 + ( v 1 -v 2 ) 1500 / 5700 r21 200 16h 010110v 22 'v 2 +(v 1 -v 2 ) 1300 / 5700 r22 200 17h 010111v 23 'v 2 +(v 1 -v 2 ) 1100 / 5700 r23 150 18h 011000v 24 'v 2 +(v 1 -v 2 ) 950 / 5700 r24 150 19h 011001v 25 'v 2 +(v 1 -v 2 ) 800 / 5700 r25 150 1ah 011010v 26 'v 2 +(v 1 -v 2 ) 650 / 5700 r26 150 1bh 011011v 27 'v 2 +(v 1 -v 2 ) 500 / 5700 r27 100 1ch 011100v 28 'v 2 +(v 1 -v 2 ) 400 / 5700 r28 100 1dh 011101v 29 'v 2 +(v 1 -v 2 ) 300 / 5700 r29 100 1eh 011110v 30 'v 2 +(v 1 -v 2 ) 200 / 5700 r30 100 1fh 011111v 31 'v 2 +(v 1 -v 2 ) 100 / 5700 r31 100 20h 100000v 32 'v 2 r32 100 21h 100001v 33 'v 3 +(v 2 -v 3 ) 2450 / 2550 r33 100 22h 100010v 34 'v 3 +(v 2 -v 3 ) 2350 / 2550 r34 100 23h 100011v 35 'v 3 +(v 2 -v 3 ) 2250 / 2550 r35 100 24h 100100v 36 'v 3 +(v 2 -v 3 ) 2150 / 2550 r36 100 25h 100101v 37 'v 3 +(v 2 -v 3 ) 2050 / 2550 r37 100 26h 100110v 38 'v 3 +(v 2 -v 3 ) 1950 / 2550 r38 100 27h 100111v 39 'v 3 +(v 2 -v 3 ) 1850 / 2550 r39 100 28h 101000v 40 'v 3 + ( v 2 -v 3 ) 1750 / 2550 r40 100 29h 101001v 41 'v 3 +(v 2 -v 3 ) 1650 / 2550 r41 100 2ah 101010v 42 'v 3 +(v 2 -v 3 ) 1550 / 2550 r42 100 2bh 101011v 43 'v 3 +(v 2 -v 3 ) 1450 / 2550 r43 100 2ch 101100v 44 'v 3 +(v 2 -v 3 ) 1350 / 2550 r44 100 2dh 101101v 45 'v 3 +(v 2 -v 3 ) 1250 / 2550 r45 100 2eh 101110v 46 'v 3 +(v 2 -v 3 ) 1150 / 2550 r46 100 2fh 101111v 47 'v 3 +(v 2 -v 3 ) 1050 / 2550 r47 100 30h 110000v 48 'v 3 +(v 2 -v 3 ) 950 / 2550 r48 100 31h 110001v 49 'v 4 +(v 3 -v 4 ) 850 / 2550 r49 100 32h 110010v 50 'v 4 +(v 3 -v 4 ) 750 / 2550 r50 100 33h 110011v 51 'v 4 +(v 3 -v 4 ) 650 / 2550 r51 100 34h 110100v 52 'v 4 +(v 3 -v 4 ) 550 / 2550 r52 100 35h 110101v 53 'v 4 +(v 3 -v 4 ) 450 / 2550 r53 150 36h 110110v 54 'v 4 +(v 3 -v 4 ) 300 / 2550 r54 150 37h 110111v 55 'v 4 +(v 3 -v 4 ) 150 / 2550 r55 150 38h 111000v 56 'v 3 r56 200 39h 111001v 57 'v 4 +(v 3 -v 4 ) 2300 / 2500 r57 200 3ah 111010v 58 'v 4 +(v 3 -v 4 ) 2100 / 2500 r58 250 3bh 111011v 59 'v 4 + ( v 3 -v 4 ) 1850 / 2500 r59 250 3ch 111100v 60 'v 4 +(v 3 -v 4 ) 1600 / 2500 r60 300 3dh 111101v 61 'v 4 +(v 3 -v 4 ) 1300 / 2500 r61 500 3eh 111110v 62 'v 4 +(v 3 -v 4 ) 800 / 2500 r62 800 3fh 111111 v 63 'v 4 rtotal 15850 r n ( w ) output volta g e
data sheet s13944ej2v0ds00 7 m m m m pd16715a figure 5 - - - - 3. relationship between input data and output voltage (2/2) v 5 > v 6 > v 7 > v 8 > v 9 > v ss2 + 0.1 v v 63 v 62 v 61 v 60 v 59 v 58 v 57 v 56 v 55 v 33 v 32 v 31 v 9 v 8 v 7 v 6 v 5 v 4 v 3 v 2 v 1 v 0 v 5 r 62 r 61 r 60 r 59 r 58 r 57 r 56 v 6 r 55 r 54 r 33 r 32 v 7 r 31 r 30 r 9 r 8 v 8 r 7 r 6 r 5 r 4 r 3 r 2 r 1 r 0 v 9 v 61 v 62 v 63 r 60 r 61 r 62 v 4 data d x5 d x4 d x3 d x2 d x1 d x0 00h 000000v 0 '' v 9 r0 800 01h 000001v 1 '' v 9 +(v 8 -v 9 ) 800 / 5100 r1 750 02h 000010v 2 '' v 9 +(v 8 -v 9 ) 1550 / 5100 r2 700 03h 000011v 3 '' v 9 +(v 8 -v 9 ) 2250 / 5100 r3 650 04h 000100v 4 '' v 9 +(v 8 -v 9 ) 2900 / 5100 r4 600 05h 000101v 5 '' v 9 +(v 8 -v 9 ) 3500 / 5100 r5 550 06h 000110v 6 '' v 9 +(v 8 -v 9 ) 4050 / 5100 r6 550 07h 000111v 7 '' v 9 +(v 8 -v 9 ) 4600 / 5100 r7 500 08h 001000v 8 '' v 8 r8 500 09h 001001v 9 '' v 9 +(v 8 -v 9 ) 500 / 5700 r9 400 0ah 001010v 10 '' v 9 +(v 8 -v 9 ) 900 / 5700 r10 400 0bh 001011v 11 '' v 9 +(v 8 -v 9 ) 1300 / 5700 r11 350 0ch 001100v 12 '' v 9 +(v 8 -v 9 ) 1650 / 5700 r12 350 0dh 001101v 13 '' v 9 +(v 8 -v 9 ) 2000 / 5700 r13 350 0eh 001110v 14 '' v 9 +(v 8 -v 9 ) 2350 / 5700 r14 300 0fh 001111v 15 '' v 9 +(v 8 -v 9 ) 2650 / 5700 r15 300 10h 010000v 16 '' v 9 +(v 8 -v 9 ) 2950 / 5700 r16 300 11h 010001v 17 '' v 8 +(v 7 -v 8 ) 3250 / 5700 r17 250 12h 010010v 18 '' v 8 +(v 7 -v 8 ) 3500 / 5700 r18 250 13h 010011v 19 '' v 8 +(v 7 -v 8 ) 3750 / 5700 r19 250 14h 010100v 20 '' v 8 +(v 7 -v 8 ) 4000 / 5700 r20 200 15h 010101v 21 '' v 8 +(v 7 -v 8 ) 4200 / 5700 r21 200 16h 010110v 22 '' v 8 +(v 7 -v 8 ) 4400 / 5700 r22 200 17h 010111v 23 '' v 8 +(v 7 -v 8 ) 4600 / 5700 r23 150 18h 011000v 24 '' v 8 +(v 7 -v 8 ) 4750 / 5700 r24 150 19h 011001v 25 '' v 8 +(v 7 -v 8 ) 4900 / 5700 r25 150 1ah 011010v 26 '' v 8 +(v 7 -v 8 ) 5050 / 5700 r26 150 1bh 011011v 27 '' v 8 +(v 7 -v 8 ) 5200 / 5700 r27 100 1ch 011100v 28 '' v 8 +(v 7 -v 8 ) 5300 / 5700 r28 100 1dh 011101v 29 '' v 8 +(v 7 -v 8 ) 5400 / 5700 r29 100 1eh 011110v 30 '' v 8 +(v 7 -v 8 ) 5500 / 5700 r30 100 1fh 011111v 31 '' v 8 +(v 7 -v 8 ) 5600 / 5700 r31 100 20h 100000v 32 '' v 7 r32 100 21h 100001v 33 '' v 7 +(v 6 -v 7 ) 100 / 2550 r33 100 22h 100010v 34 '' v 7 +(v 6 -v 7 ) 200 / 2550 r34 100 23h 100011v 35 '' v 7 +(v 6 -v 7 ) 300 / 2550 r35 100 24h 100100v 36 '' v 7 +(v 6 -v 7 ) 400 / 2550 r36 100 25h 100101v 37 '' v 7 +(v 6 -v 7 ) 500 / 2550 r37 100 26h 100110v 38 '' v 7 +(v 6 -v 7 ) 600 / 2550 r38 100 27h 100111v 39 '' v 7 +(v 6 -v 7 ) 700 / 2550 r39 100 28h 101000v 40 '' v 7 +(v 6 -v 7 ) 800 / 2550 r40 100 29h 101001v 41 '' v 7 +(v 6 -v 7 ) 900 / 2550 r41 100 2ah 101010v 42 '' v 7 +(v 6 -v 7 ) 1000 / 2550 r42 100 2bh 101011v 43 '' v 7 +(v 6 -v 7 ) 1100 / 2550 r43 100 2ch 101100v 44 '' v 7 +(v 6 -v 7 ) 1200 / 2550 r44 100 2dh 101101v 45 '' v 7 +(v 6 -v 7 ) 1300 / 2550 r45 100 2eh 101110v 46 '' v 7 +(v 6 -v 7 ) 1400 / 2550 r46 100 2fh 101111v 47 '' v 7 +(v 6 -v 7 ) 1500 / 2550 r47 100 30h 110000v 48 '' v 7 +(v 6 -v 7 ) 1600 / 2550 r48 100 31h 110001v 49 '' v 6 +(v 5 -v 6 ) 1700 / 2550 r49 100 32h 110010v 50 '' v 6 +(v 5 -v 6 ) 1800 / 2550 r50 100 33h 110011v 51 '' v 6 +(v 5 -v 6 ) 1900 / 2550 r51 100 34h 110100v 52 '' v 6 +(v 5 -v 6 ) 2000 / 2550 r52 100 35h 110101v 53 '' v 6 +(v 5 -v 6 ) 2100 / 2550 r53 150 36h 110110v 54 '' v 6 +(v 5 -v 6 ) 2250 / 2550 r54 150 37h 110111v 55 '' v 6 +(v 5 -v 6 ) 2400 / 2550 r55 150 38h 111000v 56 '' v 6 r56 200 39h 111001v 57 '' v 6 +(v 5 -v 6 ) 200 / 2500 r57 200 3ah 111010v 58 '' v 6 +(v 5 -v 6 ) 400 / 2500 r58 250 3bh 111011v 59 '' v 6 +(v 5 -v 6 ) 650 / 2500 r59 250 3ch 111100v 60 '' v 6 +(v 5 -v 6 ) 900 / 2500 r60 300 3dh 111101v 61 '' v 6 +(v 5 -v 6 ) 1200 / 2500 r61 500 3eh 111110v 62 '' v 6 +(v 5 -v 6 ) 1700 / 2500 r62 800 3fh 111111 v 63 '' v 5 rtotal 15850 output volta g ern ( w )
data sheet s13944ej2v0ds00 8 m m m m pd16715a 6. relationship between output data and d/a converter data format : 6 bits 2 rgbs (6 dots) input width : 36 bits (2-pixel data) r,/l = h (right shift) output s 1 s 2 s 3 s 4 xxx s 383 s 384 data d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 xxx d 40 to d 45 d 50 to d 55 r,/l = l (left shift) output s 1 s 2 s 3 s 4 xxx s 383 s 384 data d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 xxx d 40 to d 45 d 50 to d 55 pol s 2nC1 note s 2n note lv 0 to v 4 v 5 to v 9 hv 5 to v 9 v 0 to v 4 note s 2n-1 (odd output), s 2n (even output), n = 1,2, ,192 7. relationship between stb, pol, and output waveform the output voltage is written to the lcd panel synchronized with the stb falling edge. stb pol s 2nC1 s 2n selected voltage of v 0 to v 4 selected voltage of v 5 to v 9 hi-z hi-z hi-z selected voltage of v 0 to v 4 selected voltage of v 0 to v 4 selected voltage of v 5 to v 9 selected voltage of v 5 to v 9
data sheet s13944ej2v0ds00 9 m m m m pd16715a 8. relationship between output data and d/a converter the m pd16715a is a dot inversion and inverts dots by alternately using a charging output buffer and a discharging output buffer. therefore, the output voltage of the first line may not be correctly written because the last lines output polarity of frame n (n + 1) and the first lines output polarity are the same (refer to figure 8-1). consequently, polarity inversion and write operation must be performed between frames (vertical blanking period) in order to invert (clear) the polarity of the wiring level of the liquid crystal panel by using the last line output of the previous frame (refer to figure 8-2). figure 8-1. incase of the output voltage may not be correctly written stb last line of frame n vertical blanking period second line of frame (n + 1) first line of frame (n + 1) charging output buffer discharging output buffer v com pol hi-z hi-z hi-z s 2n if the write voltage of the first line of the last (n + 1) frame is greater than the write voltage of the last line of frame n, the targeted voltage cannot be correctly written with the figure 8-2. polarity inversion and write operation last line of frame n vertical blanking period first line of frame (n + 1) second line of frame (n + 1) v com hi-z hi-z hi-z hi-z stb pol s 2n because data of negative polarity is to be written on the first line of frame (n + 1),
data sheet s13944ej2v0ds00 10 m m m m pd16715a 5. electrical specifications absolute maximum ratings (t a = 25 c, v ss1 = v ss2 = 0 v) parameter symbol ratings unit logic part supply voltage v dd1 C0.3 to + 6.5 v driver part supply voltage v dd2 C0.5 to + 15.0 v logic part input voltage v i1 C0.3 to v dd1 + 0.3 v driver part input voltage v i2 C0.3 to v dd2 + 0.3 v logic part output voltage v o1 C0.3 to v dd1 + 0.3 v driver part output voltage v o2 C0.3 to v dd2 + 0.3 v operating ambient temperature t a C10 to +75 c storage temperature t stg C55 to +125 c caution if the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. be sure to use the product within the range of the absolute maximum ratings. recommended operating range (t a = C10 to +75 c, v ss1 = v ss2 = 0 v) parameter symbol min. typ. max. unit logic supply voltage v dd1 3.0 3.3 3.6 v driver supply voltage v dd2 9.0 11.0 13.5 v high-level input voltage v ih 0.7 v dd1 v dd1 v low-level input voltage v il 0 0.3 v dd1 v g -corrected voltage v 0 to v 9 v ss2 + 0.1 v dd2 - 0.1 v driver part output voltage v o v ss2 + 0.1 v dd2 - 0.1 v clock frequency f clk 55 mhz
data sheet s13944ej2v0ds00 11 m m m m pd16715a electrical characteristics (t a = C10 to +75 c, v dd1 = 3.3 v 0.3 v, v dd2 = 11.0 v v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit input leak current i il 1.0 m a high-level output voltage v oh sthr (sthl), i oh = 0 ma v dd1 - 0.1 v dd1 v low-level output voltage v ol sthr (sthl), i ol = 0 ma 0.1 v v 0 pin, v 5 pin 0.31 0.8 ma g -corrected supply current i g v dd2 = 13 v, v 0 to v 4 = v 5 to v 9 = 6.0 v v 4 pin, v 9 pin C0.8 C0.31 ma i voh v x = 8.0 v, v out = 6.0 v C0.25 ma driver output current i vol v x = 1.0 v, v out = 3.0 v 0.25 ma output voltage deviation d v o input data 20 mv average output voltage variation d v av input data 10 mv output voltage range v o input data v dd2 +0.1 v dd2 C 0.1 v logic part dynamic current consumption i dd1 v dd1 = 3.6 v, t a = 25c 1.5 8 ma driver part dynamic current consumption i dd2 v dd1 = 3.0 v, v dd2 = 13.5 v, no loads, t a = 25c 3.5 8 ma cautions 1. the output voltage deviation refers to the voltage difference between adjoining output pins when the display data is the same (within the chip). 2. the average output voltage variation refers to the average output voltage difference between chips. the average output voltage refers to the average voltage between chips when the display data is the same. 3. the stb cycle is defined to be 20 m m m m s at f clk = 33 mhz. 4. the typ. values refer to an all black or all white input pattern. the max. value refers to the measured values in the dot checkerboard input pattern. 5. refers to the current consumption per driver when cascades are connected under the assumption of xga single-sided mounting (8 units). switching characteristics (t a = C10 to +75 c, v dd1 = 3.3 v 0.3 v, v dd2 = 11.0 v v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit start pulse delay time t plh1 c l = 25 pf 9.1 14 ns t plh2 5.2 11 m s t plh3 9.9 17 m s t phl2 5.3 11 m s driver output delay time t phl3 c l = 50 pf, r l = 50 k w 10.4 17 m s c i1 sthr (sthl) excluded, t a = 25c 5.8 15 pf input capacitance c i2 sthr (sthl),t a = 25c 5.7 15 pf +2.5 C2.0 ? ? ? ? +2.5 C2.0
data sheet s13944ej2v0ds00 12 m m m m pd16715a timing requirement (t a = C10 to +75 c, v dd1 = 3.3 v 0.3 v, v ss1 = v ss2 = 0 v, t r = t f = 8.0 ns) parameter symbol condition min. typ. max. unit clock pulse width pw clk 18 ns clock pulse high period pw clk(h) 5ns clock pulse low period pw clk(l) 5ns data setup time t setup1 0ns data hold time t hold1 8ns start pulse setup time t setup2 4ns start pulse hold time t hold2 5ns pol2 setup time t setup3 0ns pol2 hold time t hold3 8ns stb pulse width pw stb 500 ns data invalid period t inv 1clk last data timing t ldt 2clk clk-stb time t clk-stb clk - ? stb - 5ns stb-clk time t stb-clk stb - ? clk - 5ns time between stb and start pulse t stb-sth stb - ? sthr(sthl) - 50 ns pol-stb time t pol-stb pol - or ? stb - C7 ns stb-pol time t stb-pol stb ? pol or - 9ns
data sheet s13944ej2v0ds00 13 m m m m pd16715a 9. switching characteristics waveform (r,/l = h) (unless otherwise specified, the input level is defined to be v ih =0.5 v dd1. ) t hold3 v dd1 v ss1 t setup2 pol2 d n0 - d n5 v out clk sthr (1st dr.) sthl (1st dr.) stb pol t hold1 t setup1 t plh1 t stb-sth t r 90% 10% pw stb t ldt t inv t pol-stb hi-z t phl3 t plh3 t phl2 t plh2 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 t setup3 t hold2 pw clk(l) pw clk t f 1 d 1 - d 6 d 1 - d 6 d 7 - d 12 d 373 - d 378 d 379 - d 384 d 385 - d 390 d 3067 - d 3072 d 7 - d 12 1025 2 65 66 3 12 64 invalid invalid invalid invalid t clk-stb t stb-clk pw clk(h) target voltage 0.1v dd2 6-bit accuracy v dd1 v ss1 t stb-pol 1026 ? ? ? ?
data sheet s13944ej2v0ds00 14 m m m m pd16715a 7. recommended soldering conditions the following conditions must be met for soldering conditions of the m pd16715a. for more details, refer to the semiconductor device mounting technology manual (c10535e). please consult with our sales offices in case other soldering process is used, or in case the soldering is done under different conditions. type of surface mount device m m m m pd16715an- : tcp (tab package) mounting condition mounting method condition soldering heating tool 300 to 350c, heating for 2 to 3 seconds: pressure 100g (per solder) thermocompression acf (adhesive conductive film) temporary bonding 70 to 100c: pressure 3 to 8 kg/cm 2 : time 3 to 5 seconds. real bonding 165 to 180c: pressure 25 to 45 kg/cm 2 : time 30 to 40 seconds. (when using the anisotropy conductive film sumizac1003 of sumitomo bakelite, ltd.) caution to find out the detailed conditions for packaging the acf part, please contact the acf manufacturing company. be sure to avoid using two or more packaging methods at a time.
data sheet s13944ej2v0ds00 15 m m m m pd16715a notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m m m m pd16715a reference documents nec semiconductor device reliability / quality control system (c10983e) quality grades to necs semiconductor devices (c11531e) the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8

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