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a preliminary technical data multiport internet gateway processor this information applies to a product under development. its characteristics and specifications are subject to change without notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. one technology way, p .o.box 9106, norwood, ma 02062-9106, u.s.a. tel:781/329-4700 world wide web site: http://www.analog.com fax:781/326-8703 ?analog devices,inc., 2001 r e v . p rb 6/2001 adsp-21mod980n performance features complete single device multi-port internet gateway processor (no external memory required) implements sixteen modem channels or forty voice channels in one package each dsp can implement two v.34/v.90 data/fax modem channels (includes datapump and controller) low power version: 640 mips sustained performance, 12.5 ns instruction time @ 1.9 volts nominal (internal) open architecture extensible to voice-over-network (von) and other applications low power dissipation, 25 mw (typical) per channel powerdown mode featuring low cmos standby power dissipation integration features adsp-2100 family code-compatible, with instruction set extensions 16 mbits of on-chip sram, configured as 9 mbits of program memory and 7 mbits of data memory dual-purpose program memory, for both instruction and data storage 352-ball pbga with a 35mm 35mm footprint system configuration features 16-bit internal dma port for high-speed access to on-chip memory (mode-selectable) programmable multichannel serial port supports 24/32 channels two double-buffered serial ports with companding hardware and automatic data buffering separate reset pins for each internal processor figure 1. mod980n multiport internet gateway processor block diagram 2188n dsp 1 2188n dsp 2 2188n dsp 3 2188n dsp 4 2188n dsp 5 2188n dsp 6 2188n dsp 8 2188n dsp 7 host idma sport0 sport1 control 21mod980n
2 6 / 20 01 r e v . p rb for current information contact analog devices at (800) analogd a d sp- 2 1mo d 9 8 0n preliminary technical data general description the adsp-21mod980n is a multi-port internet gateway processor optimized for implementation of a complete v.34/v.90 digital modem. all datapump and controller functions can be implemented on a single device, offering the lowest power consumption and highest possible modem port density. the adsp-21mod980n combines the adsp-2100 family base architecture (three computational units, data address generators, and a program sequencer) with two serial ports, a 16-bit internal dma port, a byte dma port, a program- mable timer, flag i/o, extensive interrupt capabilities, and on-chip program and data memory. the adsp-21mod980n integrates 16 mbits of on-chip memory, configured as 384 kwords (24-bit) of program ram, and 448 kwords (16-bit) of data ram. power-down circuitry is also provided to reduce the average and standby power consumption of equipment which in turn reduces equipment cooling requirements. the adsp-21mod980n is available in a 35 mm x 35 mm, 352-lead pbga package. fabricated in a high-speed, low-power, cmos process, the adsp-21mod980n operates with a 12.5 ns instruction cycle time. every instruction can execute in a single proces- sor cycle. the adsp-21mod980n?s flexible architecture and com- prehensive instruction set allow the processor to perform multiple operations in parallel. in one processor cycle, the adsp-21mod980n can: generate the next program address fetch the next instruction perform one or two data moves update one or two data address pointers perform a computational operation this takes place while the processor continues to: receive and transmit data through the two serial ports receive and/or transmit data through the internal dma port receive and/or transmit data through the byte dma port decrement timer modem software the following software is available as object code from analog devices inc. adsp-21mod family dynamic internet voice access tm (diva) voice over network solution. adsp-21mod980-210n multiport internet gateway processor modem solution. a complete system implementation requires the adsp-21mod980n device plus modem or voice software. the modem software executes general modem control, command sets, error correction, and data compression, data modulations (for example, v.34 and v.90), and host interface functions.the host interface allows system access to modem statistics, such as call progress, connect speed, retrain count, symbol rate, and other modulation parameters. the modem datapump and controller software reside in on-chip sram and do not require additional memory. you can configure the adsp-21mod980n dynamically by downloading software from the host through the 16-bit idma interface. this sram-based architecture provides a software upgrade path to other applications, such as voice-over-ip, and to future standards. development system analog devices' wide range of software and hardware devel- opment tools supports the adsp-218x n series. the dsp tools include an integrated development environment (ide), an evaluation kit, and a serial port emulator. visualdsp? is an integrated development environment, allowing for fast and easy development, debug and deploy- ment. the visualdsp project management environment lets programmers develop and debug an application. this environment includes an easy-to-use assembler that is based on an algebraic syntax; an archiver (librarian/library builder); a linker; a loader; a cycle-accurate, instruc- tion-level simulator; a c compiler; and a c run-time library that includes dsp and mathematical functions. debugging both c and assembly programs with the visu- aldsp debugger, programmers can: view mixed c and assembly code (interleaved source and object information) insert break points set conditional breakpoints on registers, memory, and stacks trace instruction execution fill and dump memory source level debugging
3 r e v . p rb 6/2001 for current information contact analog devices at (800) analogd adsp-21mod980n preliminary technical data the visualdsp ide lets programmers define and manage dsp software development. the dialog boxes and property pages let programmers configure and manage all of the adsp-218x development tools, including the syntax high- lighting in the visualdsp editor. this capability controls how the development tools process inputs and generate outputs. the adsp-218x ez-ice ? emulator provides an easier and more cost-effective method for engineers to develop and optimize dsp systems, shortening product develop- ment cycles for faster time-to-market. the adsp-21mod980n integrates on-chip emulation support with a 14-pin ice-port interface. this interface provides a simpler target board connection that requires fewer mechanical clearance considerations than other adsp-2100 family ez-ices. the adsp-21mod980n device need not be removed from the target system when using the ez-ice, nor are any adapters needed. due to the small footprint of the ez-ice connector, emulation can be supported in final board designs.the ez-ice performs a full range of functions, including: in-target operation up to 20 breakpoints single-step or full-speed operation registers and memory values can be examined and altered pc upload and download functions instruction-level emulation of program booting and execution complete assembly and disassembly of instructions c source-level debugging additional information this data sheet provides a general overview of adsp-21mod980n functionality. for specific information about the modem processors, refer to the adsp-2188n data sheet. for additional information on the architecture and instruction set of the modem processors, refer to the adsp-2100 family user ? s manual (3rd edition). for more information about the development tools, refer to the adsp-2100 family development tools data sheet.
4 6 /2 00 1 r e v . p rb for current information contact analog devices at (800) analogd a d sp- 2 1mo d 9 8 0n preliminary technical data architecture overview figure 2 on page 4 is a functional block diagram of the adsp-21mod980n. it contains eight independent digital signal processors. every modem processor has: a dsp core 256k bytes of ram two s e r i a l p o r t s an idma host. the signals of each modem processor are accessed through the external pins of the adsp-21mod980n. some signals are bussed with the signals of the other processors and are accessed through a single external pin. other signals remain separate and they are accessed through separate external pins for each processor. the arrangement of the eight modem processors in the adsp-21mod980n makes one basic configuration possi- ble: a slave configuration. in this configuration, the data pins of all eight processors connect to a single bus structure. figure 2. adsp-21mod980n functional block diagram iad<15:0>, idma cntl pf<0:2>/mode a:c 20 3 2188n 2188n 2188n 2188n2188n 17 2188n 4 4 8 4 2188n 2188n 20 sport1 sport0a clkin emulator subtotal = 177 signal balls signals routed to each respective die 8 bg <8:1> 8 br <8:1> ee <8:1> 8 is <8:1> 8 reset <8:1> 8 clkout <8:1> 8 tfs0 <8:1> 8 dt1 <8:1> 8 interrupts <8:1> 32 22 vddint 44 vddext subtotal = 175 power balls total = 352 balls 109 gnd data<23:8>, a<0> iad <15:0>, idma cntl sport0b idma cntl = ial, ird, iwr, iack interrupts = irqe (pf4), irql0(pf5), irql1(pf6), irq2(pf7) emulator = ems, eint, elin, ebr, ebg, eclk elout, ereset sport0a, sport 0b = rfs0, dr0, dt0, sckl0 sport1 = rfs1, tfs1, dr1, sckl1 note: 1. pwd and pf3/mode d are tied high dsp 1 dsp 2 dsp 3 dsp 4 dsp 5 dsp 6 dsp 7 dsp 8
5 r e v . p rb 6/2001 for current information contact analog devices at (800) analogd adsp-21mod980n preliminary technical data all eight modem processors have identical functions and have equal status. each of the modem processors is con- nected to a common idma bus and each modem processor is configured to operate in the same mode (see the slave mode and the memory mode descriptions in ? memory architecture ? on page 10 ). the slave mode is considered to be the only mode of operation in the adsp-21mod980n modem pool. serial ports the adsp-21mod980n has a multichannel serial port (sport) connected to each internal digital modem pro- cessor for serial communications. the following is a brief list of adsp-21mod980n sport features. for additional information on the internal serial ports, refer to the adsp-2100 family user ? s manual. each sport: is bidirectional and has a separate, double-buffered transmit and receive section. can use an external serial clock or generate its own serial clock internally. has independent framing for the receive and transmit sections. sections run in a frameless mode or with frame synchronization signals internally or externally generated. frame sync signals are active high or inverted, with either of two pulse widths and timings. supports serial data word lengths from 3 to 16 bits and provides optional a-law and -law companding accord- ing to ccitt recommendation g.711. receive and transmit sections can generate unique interrupts on completing a data word transfer. can receive and transmit an entire circular buffer of data with one overhead cycle per data word. an inter- rupt is generated after a data buffer transfer. a multichannel interface selectively receives and transmits a 24 or 32 word, time-division multiplexed, serial bitstream. pin descriptions the adsp-21mod980n is available in a 352-lead pbga package. in order to maintain maximum functionality and reduce package size and pin count, some serial port, pro- grammable flag, interrupt and external bus pins have dual, multiplexed functionality. the external bus pins are config- ured during reset only, while serial por t pins are software configurable during program execution. flag and interrupt functionality is retained concurrently on multiplexed pins. table on page 6 lists the pin names and their functions. in cases where pin functionality is reconfigurable, the default state is shown in plain text; alternate functionality is shown in italics.
6 6/ 20 01 r e v . p rb for current information contact analog devices at (800) analogd a d sp- 2 1mo d 9 8 0n preliminary technical data memory interface pins the adsp-21mod980n modem pool is used in slave mode. in slave mode, the modem processors operate in host configuration. the operating mode is determined by the state of the mode c pin during reset and cannot be changed while the modem pool is running. see the ? mem- ory architecture ? section for more information. table 1. common mode pins pin name(s) # of pins input/output function reset 8 i processor reset input br 8 i bus request input bg 8 o bus grant output irq2 / 8 i edge- or level-sensitive interrupt request 1 pf7 8 i/o programmable i/o pin irql1 / 8 i level-sensitive interrupt requests 1 pf6 8 i/o programmable i/o pin irql0 / 8 i level-sensitive interrupt requests 1 pf5 8 i/o programmable i/o pin irqe / 8 i edge-sensitive interrupt requests 1 pf4 8 i/o programmable i/o pin mode c / 1 i mode select input - checked only during reset pf2 1 i/o programmable i/o pin during normal operation mode b / 1 i mode select input - checked only during reset pf1 1 i/o programmable i/o pin during normal operation mode a / 1 i mode select input - checked only during reset pf0 1 i/o programmable i/o pin during normal operation clkin 1 i clock input clkout 8 o processor clock output sport 28 i/o serial port i/o pins 2 v dd and gnd 175 i power and ground ez-port 16 i/o for emulation use 1 interrupt/flag pins retain both functions concurrently. if imask is set to enable the corresponding interrupts, then the adsp-2 1mod980n will vector to the appropriate interrupt vector address when the pin is asserted, either by external devices, or set as a programmable flag . 2 sport configuration determined by the adsp-21mod980n system control register. software configurable.
7 r e v . p rb 6/2001 for current information contact analog devices at (800) analogd adsp-21mod980n preliminary technical data interrupts the interrupt controller allows each modem processor in the modem pool to respond individually to eleven possible interrupts and reset with minimum overhead. the adsp-21mod980n provides four dedicated external inter- rupt input pins, irq2 , irql1 , irql0 , and irqe (shared with the pf[7:4] pins) for each modem processor. the adsp-21mod980n also supports internal interrupts from the timer, the byte dma port, the serial port, software, and the power-down control circuit. the interrupt levels are internally prioritized and individually maskable (except power down and reset ). the irq2 , irq1 , and irq0 input pins can be programmed to be either level- or edge-sensitive. irql0 and irql1 are level-sensitive and irqe is edge sensitive. the priorities and vector addresses of all interrupts are shown in table on page 7 . when the modem pool is reset, interrupt servicing is disabled. low power operation the adsp-21mod980n has three low power modes that significantly reduce the power dissipation when the device operates under standby conditions. these modes are: power down idle slow idle the clkout pin may also be disabled to reduce external power dissipation. power down the adsp-21mod980n modem pool has a low power fea- ture that lets the modem pool enter a very low power dormant state through software control. here is a brief list table 2. host pins (mode c = 1) modem processors 1-8 pin name # of pins input/ output function iad[15:0] 32 1 1 there are two distinct iad buses. one addresses dsps 1-4 and the other communicates with dsps 5-8. see figure 2 for details. i/o idma port address/data bus a0 1 o address pin for exter- nal i/o, program, data, or byte access d[23:8] 16 i/o data i/o pins for pro- gram, data byte and i/o spaces iwr 2 1 i idma write enable ird 2 1 i idma read enable ial 2 1 i idma address latch pin is 8 i idma selects iack 2 1 o idma port acknowl- edge configurable in mode d; open drain table 3. interrupt priority and interrupt vector addresses source of interrupt interrupt vector address (hex) reset (or power-up with pucr = 1) 0x0000 (highest priority) power down (nonmaskable) 0x002c irq2 0x0004 irql1 0x0008 irql0 0x000c sport0 transmit 0x0010 sport0 receive 0x0014 irqe 0x0018 bdma interrupt 0x001c sport1 transmit or irq1 0x0020 sport1 receive or irq0 0x0024 timer 0x0028 (lowest priority)
8 6 / 200 1 r e v . p rb for current information contact analog devices at (800) analogd a d sp- 2 1mo d 9 8 0n preliminary technical data of power-down features. refer to the adsp-2100 family user ? s manual, ? system interface ? chapter, for detailed information about the power-down feature. quick recovery from power down. the modem pool begins executing instructions in as few as 200 clkin cycles. support for an externally generated ttl or cmos processor clock. the external clock can continue run- ning during power down without affecting the lowest power rating and 200 clkin cycle recovery. power down is initiated by the software power-down force bit. interrupt support allows an unlimited num- ber of instructions to be executed before optionally powering down. context clear/save control allows the modem pool to continue where it left off or start with a clean context when leaving the power down state. the reset pin also can be used to terminate power down. idle when the adsp-21mod980n is in the idle mode, the modem pool waits indefinitely in a low power state until an interrupt occurs. when an unmasked interrupt occurs, it is serviced; execution then continues with the instruction fol- lowing the idle instruction. in idle mode idma, bdma and autobuffer cycle steals still occur. slow idle the idle instruction is enhanced on the adsp-21mod980n to let the modem pool ? s internal clock signal be slowed, further reducing power consumption. the reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor given in the idle instruction. the format of the instruction is: idle (n); where n = 16, 32, 64, or 128. this instruction keeps the modem pool fully functional, but operating at the slower clock rate. while it is in this state, the modem pool ? s other internal clock signals, such as sclk, clkout, and timer clock, are reduced by the same ratio. the default form of the instruction, when no clock divisor is given, is the stan- dard idle instruction. when the idle (n) instruction is used, it effectively slows down the modem pool ? s internal clock and thus its response time to incoming interrupts. the one-cycle response time of the standard idle state is increased by n, the clock divisor. when an enabled interrupt is received, the adsp-21mod980n will remain in the idle state for up to a maximum of n modem pool cycles (n = 16, 32, 64, or 128) before resuming normal operation. when the idle (n) instruction is used in systems that have an externally generated serial clock (sclk), the serial clock rate may be faster than the modem pool ? s reduced internal clock rate. under these conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional time the modem pool takes to come out of the idle state (a maximum of n cycles). system configuration figure on page 9 shows the hardware interfaces for a typi- cal multichannel modem configuration with the adsp-21mod980n. other system design considerations such as host processing requirements, electrical loading, and overall bus timing must all be met. a line interface can be used to connect the multichannel subscriber or client data stream to the multichannel serial port of the adsp-21mod980n. the idma port of the adsp-21mod980n is used to give a host processor full access to the internal memory of the adsp-21mod980n. this lets the host dynamically configure the adsp-21mod980n by loading code and data into its inter- nal memory. this configuration also lets the host access server data directly from the adsp-21mod980n ? s internal memory. in this configuration, the modem processors should be put into host memory mode where mode c = 1, mode b = 0, and mode a = 1.
9 r e v . p rb 6 /2 00 1 for current information contact analog devices at (800) analogd adsp-21mod980n preliminary technica l data clock signals the adsp-21mod980n is clocked by a ttl-compatible clock signal that runs at half the instruction rate; a 40 mhz input clock yields a 12.5 ns processor cycle, which is equiv- alent to 80 mhz. normally, instructions are executed in a single processor cycle. all device timing is relative to the internal instruction clock rate, which is indicated by the clkout signal when enabled. the clock input signal is connected to the processor ? s clkin input. the clkin input cannot be halted, changed during oper- ation, or operated below the specified frequency during normal operation. the only exception is while the processor is in the power down state. for additional information, refer to chapter 9, adsp-2100 family user ? s manual for a detailed explanation of this power down feature. figure 3. multichannel modem configuration sport 21mod980n st/cntl idma sport 21mod980n st/cntl idma 21mod980n st/cntl idma t1/e1 line interface sport t1/e1 line interface t1/e1 line interface
10 6 / 20 01 r e v . p rb for current information contact analog devices at (800) analogd a d sp- 2 1mo d 9 8 0n preliminary technical data a clock output (clkout) signal is generated by the pro- cessor at the processor ? s cycle rate. this can be enabled and disabled by the clkodis bit in the sport0 autobuffer control register. reset the reset signals initiate a reset of each modem proces- sor in the adsp-21mod980n. the reset signals must be asserted during the power-up sequence to assure proper ini- tialization. reset during initial power-up must be held long enough to let the internal clocks stabilize. if reset s are activated any time after power up, the clocks continue to run and do not require stabilization time. the power-up sequence is defined as the total time required for the oscillator circuits to stabilize after a valid v dd is applied to the processors, and for the internal phase-locked loops (pll) to lock onto the specific frequency. a mini- mum of 2000 clkin cycles ensures that the plls have locked, but this does not include the oscillators ? start-up time. during this power-up sequence, the reset signals should be held low. on any subsequent resets, the reset signals must meet the minimum pulse width specification, t rsp . the reset input contains some hysteresis; however, if you use an rc circuit to generate your reset signals, the use of an external schmidt triggers are recommended. the reset for each individual modem processor sets the internal stack pointers to the empty stack condition, masks all interrupts and clears the mstat register. when a reset is released, if there is no pending bus request and the modem processor is configured for booting, the boot-loading sequence is performed. the first instruction is fetched from on-chip program memory location 0x0000 once boot loading completes. memory architecture the adsp-21mod980n provides a variety of memory and peripheral interface options for modem processor 1. the key functional groups are program memory, data memory, byte memory, and i/o. refer to the following figures and tables for pm and dm memory allocations in the adsp-21mod980n. the adsp-21mod980n modem pool operates in one memory mode: slave mode. the following figures and tables describe the memory of the adsp-21mod980n: figure on page 10 shows program memory table on page 10 shows the generation of address bits based on the pmovlay values figure on page 11 shows data memory table on page 11 shows the generation of address bits based on the dmovlay values. access to external memory is not available figure 4. program memory map table 4. pmovlay bits pmovlay memory a13 a[12:0] 0, 4, 5, 6, 7 internal not applicable not applicable 0x2000 - 0x3fff accessible when pm ovlay = 7 0x2000 - 0x3fff accessible when pm ovlay = 6 0x2000 - 0x3fff accessible when pm ovlay = 5 pm ovlay = 0 accessible when 0x2000 - 0x3fff 0x2000 - 0x3fff accessible when pm ovlay = 4 pm mode b = 0 always accessible at address 0x0000 - 0x1fff 0x3fff 8k internal 0x0000 8k internal pmovlay = 0, 4, 5, 6, 7 0x1fff 0x2000 program memory mode b=0 address internal memory
11 r e v . p rb 6/2001 for current information contact analog devices at (800) analogd adsp-21mod980n preliminary technical data memory mapped registers (new to the adsp-21mod980n) the adsp-21mod980n has three memory mapped regis- ters that differ from other adsp-21xx family dsps. see ? waitstate control register ? on page 11. see ? programmable flag & composite select control regis- ter ? on page 12. see ? system control register ? on page 12. the slight modifications to these registers provide the adsp-21mod980n ? s waitstate and bms control features. figure 5. data memory map accessible when dm ovlay = 8 0x0000 - 0x1fff accessible when dm ovlay = 7 0x0000 - 0x1fff accessible when dm ovlay = 6 32 memory mapped registers 0x3fff internal 8160 words data memory addr 0x3fe0 8k internal dmovlay = 0, 4, 5, 6, 7, 8 0x1fff 0x3fdf 0x2000 accessible when dm ovlay = 5 accessible when dm ovlay = 4 0x0000 - 0x1fff accessible when dm ovlay = 0 0x0000 - 0x1fff 0x0000 - 0x1fff data memory always accessible at address 0x2000 - 0x3fff internal memory 0x0000 - 0x1fff table 5. dmovlay bits dmovlay memory a13 a[12:0] 0, 4, 5, 6, 7, 8 internal not applicable not applicable . figure 6. waitstate control register 1514131211109876543210 11111111 1111 11 1 1 iow ait 0 wait state mode select 0 = normal mode (pwait, dwait, iowait0-3 = n wait states, ranging from 0 to 7) 1 = 2n+1 mode (pwait, dwait, iowait0-3 = 2n+1 wait states, ranging from 0 to 15) dm(0x3ffe) iow ait 1 iow ait 2 iow ait 3 dwait
12 6 / 20 0 1 r e v . p rb for current information contact analog devices at (800) analogd a d sp- 2 1mo d 9 8 0n preliminary technical data slave mode this section describes the slave mode memory configura- tion of the modem processors. internal memory dma port (idma port) the idma port provides an efficient way for a host system and the adsp-21mod980n to communicate. the port is used to access the on-chip program memory and data mem- ory of each modem processor with only one processor cycle per word overhead. the idma port cannot be used, how- figure 7. programmable flag 1 & composite select control register 1 since they are multiplexed within the adsp-21mod980n, pf[2:0] should be configured as an output for only one processor at a tim e. bit [3] of dm (0x3fe6) must also be 0 to ensure that pf[3] is never an output. 1514131211109876543210 11111 0 11 0000 00 0 0 dm(0x3fe6) pftype 0 = input 1 = output cmssel 0 = disable cms 1 = enable cms (where bit: 11-iom, 10-bm, 9-dm, 8-pm) bmwait figure 8. system control register 1514131211109876543210 00000100 0111 00 0 0 sport1 enable 0 = disable 1 = enable pwait program memory wait states sport1 configure 0 = fi, fo, irq0, irq1, sclk 1= sport1 disable bms 0 = enable bms 1 = disable bms, except when memory strobes are three-stated sport0 enable 0 = disable 1 = enable dm(0x3fff) reserved set to 0 reserved set to 0 table 6. adsp-21mod980n mode of operation mode c mode b mode a booting method 101 idma feature is used to load internal memory as desired. program execution is held off until internal program memory location 0x0000 is written to. chip is configured in slave mode. 1 iack requires external pulldown. 2 1 considered standard operating settings. these configurations simplify your design and improve memory management. 2 idma timing details and the correct usage of iack are described in the adsp-2100 family user?s manual .
13 r e v . p rb 6/2001 for current information contact analog devices at (800) analogd adsp-21mod980n preliminary technical data ever, to write to the processor ? s memory-mapped control registers. a typical idma transfer process is described as follows: 1. host starts idma transfer 2. host uses is and ial control lines to latch either the dma starting address (idmaa) or the pm/dm ovlay selection into the processor ? s idma control registers. if iad [15] = 1, the value of iad [7:0] represents the idma overlay: iad[14:8] must be set to 0. if iad [15] = 0, the value of iad [13:0] represents the starting address of internal memory to be accessed and iad [14] reflects pm or dm for access. 1. host uses is and ird (or iwr ) to read (or write) pro- cessor internal memory (pm or dm). 2. host ends idma transfer. the idma port has a 16-bit multiplexed address and data bus and supports 24-bit program memory. the idma port is completely asynchronous and can be written to, while the adsp-21mod980n is operating at full speed. the processor memory address is latched and then auto- matically incremented after each idma transaction. an external device can therefore access a block of sequentially addressed memory by specifying only the starting address of the block. this increases throughput as the address does not have to be sent for each memory access. idma port access occurs in two phases. the first is the idma address latch cycle . when the acknowledge is asserted, a 14-bit address and 1-bit destination type can be driven onto the bus by an external device. the address specifies an on-chip memory location, the destination type specifies whether it is a dm or pm access. the falling edge of the address latch signal latches this value into the idmaa register. once the address is stored, data can then be either read from, or written to, the adsp-21mod980n ? s on-chip memory. asserting the select line (is ) and the appropriate read or write line (ird and iwr respectively) signals the adsp-21mod980n that a particular transaction is required. in either case, there is a one-processor-cycle delay for synchronization. the memory access consumes one additional processor cycle. once an access has occurred, the latched address is auto- matically incremented, and another access can occur. through the idmaa register, the processor can also spec- ify the starting address and data format for dma operation. asserting the idma port select (is ) and address latch enable (ial) directs the adsp-21mod980n to write the address onto the iad [14:0] bus into the idma control register. if iad [15] is set to 0, idma latches the address. if iad [15] is set to 1, idma latches ovlay memory. the idmaa register is memory mapped at address dm (0x3fe0). note that the latched address (idmaa) or over- lay register cannot be read back by the host. the idma overlay register is memory mapped at address dm(0x3fe7). see figure on page 13 for more informa- tion on idma memory mapping. when bit 14 in 0x3fe7 is set to 1, then timing in figure on page 35 applies for short reads. when bit 14 in 0x3fe7 is set to zero short reads use the timing shown in figure on page 34 . figure 9. idma control/ovlay registers 1514131211109876543210 idma overlay dm(0x3fe7) id dm ovlay id pmovlay reserved set to 0 1514131211109876543210 idma control (u=undefined at reset) u dm(0x3fe0) idmaa address idmad destination memory type: 0=pm 1=dm uuuuuuuuuuuuuu short read only enable 1 = enable 0 = disable 0 0 0 0 0 0 0 0 00 0 0 0 00 0 0 reserved alw ays set to 0 reserved alw ays set to 0
14 6/ 20 01 r e v . p rb for current information contact analog devices at (800) analogd a d sp- 2 1mo d 9 8 0n preliminary technical data figure 10. direct memory access - pm and dm memory maps accessible when dm ovlay = 8 accessible when dm ovlay = 7 0x0000 - 0x1fff 0x0000 - 0x1fff accessible when pm ovlay = 7 0x2000 - 0x3fff accessible when pm ovlay = 6 accessible when pm ovlay = 5 accessible when pm ovlay = 4 0x2000 - 0x3fff accessible when pm ovlay = 0 0x2000 - 0x3fff 0x2000 - 0x3fff always accessible at address 0x0000 - 0x1fff 0x2000 - 0x3fff accessible when dm ovlay = 6 accessible when dm ovlay = 5 accessible when dm ovlay = 4 0x0000 - 0x1fff accessible when dm ovlay = 0 0x0000 - 0x1fff 0x0000 - 0x1fff always accessible at address 0x2000 - 0x3fff 0x0000 - 0x1fff
15 r e v . p rb 6/2001 for current information contact analog devices at (800) analogd adsp-21mod980n preliminary technical data idma port booting the adsp-21mod980n boots programs through its inter- nal dma port.when mode c = 1, mode b = 0, and mode a = 1, the adsp-21mod980n boots from the idma port. idma feature can load as much on-chip memory as desired. program execution is held off until on-chip pro- gram memory location 0 is written to. flag i/o pins each modem processor has eight general purpose program- mable input/output flag pins. they are controlled by two memory mapped registers. the pftype register deter- mines the direction, 1 = output and 0 = input. the pfdata register is used to read and write the values on the pins. data being read from a pin configured as an input is synchronized to the adsp-21mod980n ? s clock. bits that are programmed as outputs will read the value being out- put. the pf pins default to input during reset . note: pins pf0, pf1, and pf2 are also used for device con- figuration during reset . since they are multiplexed within the adsp-21mod980n, pf[2:0] should be config- ured as an output for only one processor at a time.
16 6 / 200 1 r e v . p rb for current information contact analog devices at (800) analogd a d sp- 2 1mo d 9 8 0n preliminary technical data designing an ez-ice-compatible system the adsp-21mod980n has on-chip emulation support and an ice-port, a special set of pins that interface to the ez-ice. these features allow in-circuit emulation without replacing the target system processor by using only a 14-pin connection from the target system to the ez-ice. target systems must have a 14-pin connector to accept the ez-ice ? s in-circuit probe, a 14-pin plug. the ez-ice can emulate only one modem processor at a time. you must include hardware to select which processor in the adsp-21mod980n you want to emulate. figure on page 16 is a functional representation of the modem proces- sor selection hardware. you can use one ice-port connector with two adsp-21mod980n processors without using additional buffers. issuing the ? chip reset ? command during emulation causes the modem processor to perform a full chip reset, including a reset of its memory mode. therefore, it is vital that the mode pins are set correctly prior to issuing a chip reset command from the emulator user interface. as the mode pins share functionality with pf[2:0] on the figure 11. selecting a modem processor in the adsp-21mod980n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 bg br ent elin eclk ems ereset gnd ebg ebr key elout ee reset bg6 br6 reset6 ee6 bg7 br7 reset7 ee7 bg5 br5 reset5 ee5 bg4 br4 reset4 ee4 bg3 br3 reset3 ee3 bg2 br2 reset2 ee2 bg1 br1 reset1 ee1 bg0 br0 reset0 ee0 elout ebr ebg eint elin eclk ems ereset adsp-21m od980n
17 r e v . p rb 6/2001 for current information contact analog devices at (800) analogd adsp-21mod980n preliminary technical data adsp-21mod980n, it may be necessary to reset the target hardware separately to insure the proper mode selection state on emulator chip reset. see the adsp-2100 family ez-tools data sheet for complete information on ice products. the ice-port interface consists of the following adsp-21mod980n pins: ebr eint ee ebg eclk ereset elin ems elout these adsp-21mod980n pins must be connected only to the ez-ice connector in the target system. these pins have no function except during emulation, and do not require pull-up or pull-down resistors. the traces for these signals between the adsp-21mod980n and the connector must be kept as short as possible ? no longer than 3 inches. the following pins are also used by the ez-ice: br bg reset gnd the ez-ice uses the ee (emulator enable) signal to take control of the adsp-21mod980n in the target system. this causes the processor to use its ereset , ebr , and ebg pins instead of the reset , br , and bg pins. the bg output is three-stated. these signals do not need to be jumper-isolated in your system. the ez-ice connects to your target system via a ribbon cable and a 14-pin female plug. the female plug is plugged onto the 14-pin connector (a pin strip header) on the target board. target board connector for ez-ice probe the ez-ice connector (a standard pin strip header) is shown in figure on page 17 . you must add this connector to your target board design if you intend to use the ez-ice. be sure to allow enough room in your system to fit the ez-ice probe onto the 14-pin connector. the 14-pin, 2-row pin strip header is keyed at the pin 7 location ? you must remove pin 7 from the header. the pins must be 0.025 inch square and at least 0.20 inch in length. pin spacing should be 0.1 0.1 inches. the pin strip header must have at least 0.15 inch clearance on all sides to accept the ez-ice probe plug. pin strip headers are available from vendors such as 3m, mckenzie, and samtec. ta r g e t m e m o r y i n t e r f a c e for your target system to be compatible with the ez-ice emulator, it must comply with the memory interface guide- lines listed below. target system interface signals when the ez-ice board is installed, the performance on some system signals change. design your system to be com- patible with the following system interface signal changes introduced by the ez-ice board: ez-ice emulation introduces an 8 ns propagation delay between your target circuitry and the processor on the reset signal. ez-ice emulation introduces an 8 ns propagation delay between your target circuitry and the processor on the br signal. ez-ice emulation ignores reset and br when single-stepping. ez-ice emulation ignores reset and br when in emulator space (processor halted). ez-ice emulation ignores the state of target br in cer- tain modes. as a result, the target system may take control of the processor ? s external memory bus only if bus grant (bg ) is asserted by the ez-ice board ? s processor. figure 12. target board connector for ez-ice ? 12 34 56 78 910 11 12 13 14 gnd key (no pin) reset br bg top view ebg ebr elout ee eint elin eclk ems ereset
18 6 / 20 01 r e v . p rb for current information contact analog devices at (800) analogd a d sp- 2 1mo d 9 8 0n preliminary technical data electrical specifications recommended operating conditions parameter description min max unit v ddext external supply 2.98 3.63 v v ddint internal supply 1.81 2.0 v v input input voltage v il = ? 0.3 v ih = +3.6 v t amb ambient temperature 0 +70 c electrical characteristics parameter test conditions min typ max unit v ih , hi-level input voltage 1, 2 @ v ddint = max 1.5 v v ih , hi-level clkin voltage @ v ddint = max 2.0 v v il , lo-level input voltage 1, 3 @ v ddint = min 0.7 v v oh , hi-level output voltage 1, 4, 5 @ v ddext = min i oh = ? 0.5 ma 2.4 v @ v ddext = min i oh = ? 100 a 6 v ddext -0.3 v v ol , lo-level output voltage 1, 4, 5 @ v ddext = min i ol = 2 ma 0.4 v i ih , hi-level input leakage current 3 @ v ddint = max v in = 3.6v 10 a i il , lo-level input leakage current 3 @ v ddint = max v in = 0 v 10 a i ozh , three-state leakage current 7 @ v ddext = max v in = 3.6v 8 10 a i ozl , three-state leakage current 7 @ v ddext = max v in = 0 v 8 10 a
19 r e v . p rb 6/2001 for current information contact analog devices at (800) analogd adsp-21mod980n preliminary technical data i dd , supply current (idle) @ v ddint = 1.9v t ck = 12.5 ns 50 ma i dd , supply current (dynamic) @ v ddint = 1.9v t ck = 12.5 ns 9 t amb = +25 c 200 ma i dd , supply current (powerdown) 10 lowest power mode 800 a c i , input pin capacitance reset , br , is , tfs0, pf[7:4] @ v in = 2.5 v, f in = 1.0 mhz, t amb = +25 c 8pf c i , input pin capacitance iwr , ird , ial, dr0, rfs0, sclk0, iad [15:0] @ v in = 2.5 v, f in = 1.0 mhz, t amb = +25 c 32 pf c i , input pin capacitance tfs1, pf[2:0], clkin, dr1, rfs1, sclk1 @ v in = 2.5 v, f in = 1.0 mhz, t amb = +25 c 64 pf c o , output pin capacitance 1, 6, 7, 10, 11 bg , clkout, tfs0, pf[7:4], dt1 @ v in = 2.5 v, f in = 1.0 mhz, t amb = +25 c 8pf c o , output pin capacitance 1, 6, 7, 9, 10 iad [15:0] , dt0, iack , rfs0, sclk0 @ v in = 2.5 v, f in = 1.0 mhz, t amb = +25 c 32 pf c o , output pin capacitance 1, 6, 7, 9, 10 sclk1, tfs1, pf[2:0], data [23:8], a0, rfs1 @ v in = 2.5 v, f in = 1.0 mhz, t amb = +25 c 64 pf 1 bidirectional pins: rfs0, rfs1, sclk0, sclk1, tfs0, tfs1, iad [15:0], pf[2:0], pf[7:4]. 2 input only pins: reset , br , dr0, dr1, is , ial,ird , iwr . 3 input only pins: clkin, reset , br , dr0, dr1. 4 output pins: bg , a0, dt0, dt1, clkout, iack . 5 although specified for ttl outputs, all adsp-21mod980n outputs are cmos-compatible and will drive to v ddext and gnd, assuming no dc loads. 6 guaranteed but not tested. 7 three-statable pins: dt0, dt1, sclk0, sclk1, tfs0, tfs1, rfs0, rsf1, iad[15:0]. 8 0 volts on br . 9 vin = 0v and 3v. for typical supply current figures refer to ? power dissipation ? section. 10 see the adsp-2100 family user ? s manual for details. 11 output pin capacitance is the capacitive load for any three-stated output pin electrical characteristics (continued) parameter test conditions min typ max unit
20 6/ 20 01 r e v . p rb for current information contact analog devices at (800) analogd a d sp- 2 1mo d 9 8 0n preliminary technical data absolute maximum ratings parameter description min. max unit v ddint internal supply voltage ? 0.3 +2.5 v v ddext external supply voltage ? 0.3 +4.6 v input voltage 1 ? 0.5 +4.6 v output voltage swing 2 ? 0.5 v ddext + 0.5 v storage temperature range ? 65 c +150 c c 1 applies to bidirectional pins (d0:d23, rfs0, rfs1, sclk0, sclk1, tfs0, tfs1, a1:a13, pf0:pf7) and input only pins (clkin, reset , br , dr0, dr1). 2 applies to output pins (bg , pwdack, a0, dt0, dt1, clkout). esd sensitivity caution: esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000v readily accumulate on the human body and test equipment and can discharge without detection. although the device features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic dis- charges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
21 r e v . p rb 6/2001 for current information contact analog devices at (800) analogd adsp-21mod980n preliminary technical data power dissipation to determine total power dissipation in a specific applica- tion, the following equation should be applied for each output: c v dd 2 f c = load capacitance f = output switching frequency example: in an application where an external host is accessing inter- nal memory and no other outputs are active, power dissipation is calculated as follows: assumptions: assumptions: external data memory is accessed every fourth cycle with 50% of the address pins switching. external data memory writes occur every fourth cycle with 50% of the data pins switching. each address and data pin has a 64 pf total load at the pin. application operates at v ddext = 3.3 v and t ck = 30 ns. total power dissipation = p int + ( c v ddext 2 f) p int = internal power dissipation from figure 15 (c v ddext 2 f) is calculated for each output, as in the example in table 7 . total power dissipation for this example is: pd = p int + 222.7 mw table 7. example power dissipation calculation parameters # of pins c (pf) v ddext 2 (v) f (mhz) pd (mw) address 8 64 3.3 2 18.8 104.8 data output, wr 9643.3 2 18.8 117.9 222.7
22 6 /2 00 1 r e v . p rb for current information contact analog devices at (800) analogd a d sp- 2 1mo d 9 8 0n preliminary technical data environmental conditions figure 13. power vs. frequency mod980n core power, idle 50 60 70 80 90 100 110 120 55 60 65 70 75 80 85 1/t ck - m hz v dd = 1.8v 108mw v dd = 1.9v v dd = 2.0v 68mw 76mw 84mw 96mw 84mw mod980n core power, dynamic 175 225 275 325 375 425 475 55 60 65 70 75 80 85 1/t ck - m hz v dd = 2.0v v dd = 1.9v 287mw 336mw 375mw 440mw 336mw 256mw v dd = 1.8v table 8. thermal resistance rating description 1 1 where the ambient temperature rating (t amb ) is: t amb = t case ? (pd ca ) t case = case temperature in c pd = power dissipation in w symbol pbga thermal resistance (case-to- ambient) ca 23 o c /w thermal resistance (junction-to- ambient) ja 28.2 o c /w thermal resistance (junction-to- case) jc 5.2 o c /w
23 r e v . p rb 6/2001 for current information contact analog devices at (800) analogd adsp-21mod980n preliminary technical data test conditions output disable time output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state. the output disable time (t dis ) is the difference of t measured and t decay , as shown in figure 16 . the time is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 v from the measured output high or low voltage. the decay time, t decay , is dependent on the capacitive load, c l , and the current load, i l , on the output pin. it can be approximated by the following equation: from which is calculated. if multiple pins (such as the data bus) are dis- abled, the measurement value is that of the last pin to stop driving. output enable time output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. the output enable time (t ena ) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in figure 16 . if multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. figure 14. voltage reference levels for ac measurements (except output enable/disable) figure 15. equivalent loading for ac measurements (including all fixtures) figure 16. output enable/disable 1.5v output input 1.5v 2.0v 0.8v to output pin 50pf 1.5v i oh i ol 2.0v 1.0v t ena reference signal output t decay v oh (measured) output stops driving output starts driving t dis t measured v ol (measured) v oh (measured) - 0.5v v ol (measured) +0.5v high-impedance state. test conditions cause this voltage level to be approximately 1.5v. v oh (measured) v ol (measured) t decay c l 0.5 v i l ------------------------- = t dis t measured t decay ?=
24 6 / 20 01 r e v . p rb for current information contact analog devices at (800) analogd a d sp- 2 1mo d 9 8 0n preliminary technical data timing specifications this section contains timing information for the dsp ? s external signals. general notes use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of oth- ers. while addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. conse- quently, you cannot meaningfully add up parameters to derive longer times. timing notes switching characteristics specify how the processor changes its signals. you have no control over this timing ? circuitry external to the processor must be designed for compatibility with these signal characteristics. switching characteristics tell you what the processor will do in a given circumstance. you can also use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with other devices. frequency dependency for timing specifications t ck is defined as 0.5 t cki . the adsp-21mod980n uses an input clock with a frequency equal to half the instruction rate. for example, a 40 mhz input clock (which is equiva- lent to 25 ns) yields a 12.5 ns processor cycle (equivalent to 80 mhz). t ck values within the range of 0.5 t cki period should be substituted for all relevant timing parameters to obtain the specification value. example: t ckh = 0.5 t ck ? 2 ns = 0.5 (12.5 ns) ? 2 ns = 4.25 ns output drive currents figure 14 shows typical i-v characteristics for the output drivers on the adsp-21mod980n. the curves represent the current drive capability of the output drivers as a func- tion of output voltage capacitive loading figure 16 and figure 17 show the capacitive loading char- acteristics of the adsp-21mod980n. figure 17. typical output rise time vs.load capacitance (at maximum ambient operating temperature) figure 18. typical output valid delay or hold vs.load capacitance, cl (at maximum ambient operating temperature) c l - pf ri se t im e (0 . 4 v - 2. 4 v ) - n s 30 300 0 50 100 1 50 200 2 50 25 15 10 5 0 20 t = 85 c v dd = 0v to 2.0v c l - pf 14 0 va li d ou t pu t de la y or ho l d - ns 50 100 1 50 250200 12 4 2 -2 10 8 nominal 16 18 6 -4 -6
25 r e v . p rb 6/2001 for current information contact analog devices at (800) analogd adsp-21mod980n preliminary technical data clock and reset signals table 9. clock and reset signals parameter description min. max unit clock signals (timing requirements): t cki clkin period 25.0 40.0 ns t ckil clkin width low 8 ns t ckih clkin width high 8 ns t ckrise clkin rise time 1 4ns t ckfall clkin fall time 4 ns clock signals (switching characteristics) 2 : t ckl clkout width low 0.5t ck - 3 ns t ckh clkout width high 0.5t ck - 3 ns t ckoh clkin high to clkout high 0 8 ns control signals (timing requirements): t rsp reset width low 5t ck 3 ns t ms mode setup before reset high 4 ns t mh mode hold after reset high 5 ns 1 t ckrise and t ckfall are specified between the 10% and 90% points on the signal edge. 2 if it is not needed by the application, clkout should be disabled to reduce noise (dm(0x3ff3) bit 14). 3 applies after power-up sequence is complete. internal phase lock loop requires no more than 2000 clkin cycles assuming stable c lkin (not including crystal oscillator start-up time).
26 6 / 2 00 1 r e v . p rb for current information contact analog devices at (800) analogd a d sp- 2 1mo d 9 8 0n preliminary technical data figure 19. clock and reset signals t mh pf(2:0)* reset t ms *pf2 is mode c, pf1 is mode b, pf0 is mode a clkin clkout t ckil t ckoh t ckh t ckl t cki t ckih
27 r e v . p rb 6/2001 for current information contact analog devices at (800) analogd adsp-21mod980n preliminary technical data interrupts and flags table 10. interrupts and flags parameter description min. max unit timing requirements: t ifs irqx , fi, or pfx setup before clkout low 1, 2, 3, 4 0.25t ck + 10 ns t ifh irqx , fi, or pfx hold after clkout high 1, 2, 3, 4 0.25t ck ns switching characteristics: t foh flag output hold after clkout low 5 0.5t ck - 5 ns t fod flag output delay from clkout low 5 0.5t ck + 4 ns 1 if irqx and fi inputs meet t ifs and t ifh setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the following cycle. (refer to interrupt controller operation in the program control chapter of the adsp-2100 family user ? s manual for further information on interrupt servicing.) 2 edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced. 3 irqx = irq0 , irq1 , irq2 , irql0 , irql1 , irqe . 4 pfx = pf0, pf1, pf2, pf4, pf5, pf6, pf7. 5 flag outputs = pfx, flag_out 4 . figure 20. interrupts and flags t ifh t ifs clkout ir q x fi pfx
28 6 / 20 01 r e v . p rb for current information contact analog devices at (800) analogd a d sp- 2 1mo d 9 8 0n preliminary technical data serial ports table 11. serial ports parameter description min. max unit timing requirements: t sck sclk period 30 ns t scs dr/tfs/rfs setup before sclk low 4 ns t sch dr/tfs/rfs hold after sclk low 7 ns t scp sclkin width 12 ns switching characteristics: t cc clkout high to sclkout 0.25t ck 0.25t ck + 6 ns t scde sclk high to dt enable 0 ns t scdv sclk high to dt valid 12 ns t rh tfs/rfsout hold after sclk high 0 ns t rd tfs/rfsout delay from sclk high 12 ns t scdh dt hold after sclk high 0 ns t tde tfs (alt) to dt enable 0 ns t tdv tfs (alt) to dt valid 12 ns t scdd sclk high to dt disable 12 ns t rdv rfs (multichannel, frame delay zero to dt valid 12 ns
29 r e v . p rb 6/2001 for current information contact analog devices at (800) analogd adsp-21mod980n preliminary technical data figure 21. serial ports clkout sclk tfs out rfs out dt alternate frame mode t cc t cc t scs t sch t rh t scde t scdh t scdd t tde t rdv multichannel mode, fram e delay 0 (m fd = 0) dr tfs in rfs in rfs out tfs out t tdv t scdv t rd t scp t sck t scp tfs in rfs in alternate frame mode t rdv multichannel mode, frame delay 0 (mfd = 0) t tde t tdv
30 6 / 20 01 r e v . p rb for current information contact analog devices at (800) analogd a d sp- 2 1mo d 9 8 0n preliminary technical data idma address latch table 12. idma address latch parameter description min. max unit timing requirements: t ialp duration of address latch 1, 2, 3 10 ns t iasu iad[15:0] address setup before address latch end 2, 3 5ns t iah iad[15:0] address hold after address latch end 2, 3 3ns t ika iack low before start of address latch 2, 3, 4 0ns t ials start of write or read after address latch end 2, 3, 4 3ns t iald address latch start after address latch end 1, 2, 3 2ns 1 start of address latch = is low and ial high. 2 end of address latch = is high or ial low. 3 for idma, please refer to the adsp-2100 family user ? s manual . 4 start of write or read = is low and iwr low or ird low. figure 22. idma address latch iad 15-0 t ika ird iwr or iack ia l is t ialp t iald t ials t ias u t iasu t iah t iah t ialp
31 r e v . p rb 6/2001 for current information contact analog devices at (800) analogd adsp-21mod980n preliminary technical data idma write, short write cycle table 13. idma write, short write cycle parameter description min. max unit timing requirements: t ikw iack low before start of write 1, 2 0ns t iwp duration of write 1, 2, 3 10 ns t idsu iad[15:0] data setup before end of write 2, 3, 4, 5 3ns t idh iad[15:0] data hold after end of write 2, 3, 4, 5 2ns switching characteristics: t ikhw start of write to iack high 10 ns 1 start of write = is low and iwr low. 2 for idma, please refer to the adsp-2100 family user ? s manual . 3 end of write = is high or iwr high. 4 if write pulse ends before iack low, use specifications t idsu , t idh . 5 if write pulse ends after iack low, use specifications t iksu , t ikh . figure 23. idma write, short write cycle iad 15-0 data t ikhw t ikw t id su iack t iw p t idh is iw r
32 6 / 20 01 r e v . p rb for current information contact analog devices at (800) analogd a d sp- 2 1mo d 9 8 0n preliminary technical data idma write, long write cycle table 14. idma write, long write cycle parameter description min. max unit timing requirements t ikw iack low before start of write 1 0ns t iksu iad[15:0] data setup before end of write 2, 3, 4 0.5t ck + 5 ns t ikh iad[15:0] data hold after end of write 2, 3, 4 0ns switching characteristics: t iklw start of write to iack low 4 1.5t ck ns t ikhw start of write to iack high 10 ns 1 start of write = is low and iwr low. 2 if write pulse ends before iack low, use specifications t idsu , t idh . 3 if write pulse ends after iack low, use specifications t iksu , t ikh . 4 this is the earliest time for iack low from start of write. for idma write cycle relationships, please refer to the adsp-2100 family user ? s manual . figure 24. idma write, long write cycle iad 15-0 data t ikhw t ik w iac k is iw r t iklw t ikh t iksu
33 r e v . p rb 6/2001 for current information contact analog devices at (800) analogd adsp-21mod980n preliminary technical data idma read, long read cycle table 15. idma read, long read cycle parameter description min. max unit timing requirements: t ikr iack low before start of read 1, 2 0ns t irk end of read after iack low 2, 3 2ns switching characteristics: t ikhr iack high after start of read 1, 2 10 ns t ikds iad[15:0 data setup before iack low 2 0.5t ck - 2 ns t ikdh iad[15:0] data hold after end of read 2, 3 0ns t ikdd iad[15:0] data disabled after end of read 2, 3 10 ns t irde iad[15:0] previous data enabled after start of read 2 0ns t irdv iad[15:0] previous data valid after start of read 2 10 ns t irdh 1 iad[15:0] previous data hold after start of read (dm/pm1) 2, 4 2t ck - 5 ns t irdh 2 iad[15:0] previous data hold after start of read (pm2) 2, 5 t ck - 5 ns 1 start of read = is low and ird low. 2 for idma, please refer to the adsp-2100 family user ? s manual . 3 end of read = is high or ird high. 4 dm read or first half of pm read. 5 second half of pm read. figure 25. idma read, long read cycle t ir k t ik r previous data read data t ikhr t ik ds t ir dv t irdh t ikdd t ir de t ikdh iad 15-0 iack is ird
34 6/ 20 01 r e v . p rb for current information contact analog devices at (800) analogd a d sp- 2 1mo d 9 8 0n preliminary technical data idma read, short read cycle table 16. idma read, short read cycle 1 parameter description min. max unit timing requirements: t ikr iack low before start of read 2 0ns t irp duration of read 10 ns switching characteristics: t ikhr iack high after start of read 2, 3 10 ns t ikdh iad[15:0] data hold after end of read 3, 4 0ns t ikdd iad[15:0] data disabled after end of read 3, 4 10 ns t irde iad[15:0] previous data enabled after start of read 3 0ns t irdv iad[15:0] previous data valid after start of read 3 10 ns t irdh 1 iad[15:0] previous data hold after start of read (dm/pm1) 3,5 2t ck - 5 ns t irdh 2 iad[15:0] previous data hold after start of read (pm2) 3, 6 t ck - 5 ns 1 timing applies to adsp-21mod980n when short read only mode is disabled. see table on page 35 . 2 start of read = is low and ird low. 3 for idma, please refer to the adsp-2100 family user ? s manual . 4 end of read = is high or ird high. 5 dm read or first half of pm read. 6 second half of pm read. figure 26. idma read, short read cycle iack is ir d t ikr t ikhr t irde t irdv previous data new read data iad[15:0]
35 r e v . p rb 6/2001 for current information contact analog devices at (800) analogd adsp-21mod980n preliminary technical data idma read - short read cycle in short read only mode table 17. idma read - short read cycle in short read only mode 1 1 short read only is enabled by setting bit 14 of the idma overlay register to 1 (0x3fe7). short read only can be enabled by the processor core writing to the register or by an external host writing to the register. disabled by default. parameter description min. max unit timing requirements: t ikr iack low before start of read 2, 4 2 start of read = is low and ird low. previous data remains until end of read. 0ns t irp duration of read after iack low 3, 4 3 end of read = is high or ird high. 10 ns switching characteristics: t ikhr iack high after start of read 2, 4 4 for idma, please refer to the adsp-2100 family user ? s manual . 10 ns t ikdh iad[15:0] previous data hold after end of read 3, 4 0ns t ikdd iad[15:0] previous data disabled after end of read 3, 4 10 ns t irde iad[15:0] previous data enabled after start of read 4 0ns t irdv iad[15:0] previous data valid after start of read 4 10 ns figure 27. idma read, short read only mode iack is ir d t irde t rdv t ikr t ikhr t ikdh t ikdd previous data iad[15:0]
36 6 / 20 01 r e v . p rb for current information contact analog devices at (800) analogd a d sp- 2 1mo d 9 8 0n preliminary technical data 352-ball pbga package pinout a physical layout of all sig- nals is shown in the following tables. figure on page 40 shows the signals on the left side of the device when viewed from the top. figure on page 41 shows the signals on the right side of the device when viewed from the top. the pin num- ber for each signal is listed in table on page 36 . table 18. pinout by signal name signal name pin a0 a2 bg _1 f3 bg _2 d14 bg _3 f25 bg _4 ac5 bg _5 r25 bg _6 r4 bg _7 ad15 bg _8 ad25 br _1 g4 br _2 b13 br _3 g25 br _4 ac9 br _5 n24 br _6 u4 br _7 ae15 br _8 ae26 clkin e3 clkout_1 g1 clkout_2 a10 clkout_3 c20 clkout_4 ac1 clkout_5 l24 clkout_6 p4 clkout_7 ad10 clkout_8 af15 d08 f23 d09 e25 d10 e24 d11 d26 d12 d25 d13 d24 d14 c26 d15 c25 d16 b26 d17 b24 d18 a25 d19 b23 d20 c23 d21 a24 d22 a23 d23 a22 dr0a e1 dr0b af22 dr1 ae7 dt0a p2 dt0b af20 dt1_1 p3 dt1_2 a12 dt1_3 d21 table 18. pinout by signal name (continued) signal name pin dt1_4 af2 dt1_5 t25 dt1_6 u3 dt1_7 ad13 dt1_8 ae20 ebg f26 ebr g26 eclk j23 ee_1 m4 ee_2 c13 ee_3 g23 ee_4 ae9 ee_5 t26 ee_6 y2 ee_7 ac13 ee_8 ae22 eint j26 elin j25 elout j24 ems e23 ereset e26 gnd d19 gnd d20 gnd d23 gnd f1 gnd f2 gnd f4 gnd g2 gnd g3 gnd h1 table 18. pinout by signal name (continued) signal name pin gnd h2 gnd h3 gnd h4 gnd h23 gnd h24 gnd h25 gnd h26 gnd n1 gnd n2 gnd n3 gnd n4 gnd r23 gnd r24 gnd t3 gnd t24 gnd u1 gnd u2 gnd u23 gnd u24 gnd u25 gnd u26 gnd w1 gnd w2 gnd w3 gnd w4 gnd af1 gnd af4 gnd af8 gnd af10 gnd af12 table 18. pinout by signal name (continued) signal name pin
37 r e v . p rb 6/2001 for current information contact analog devices at (800) analogd adsp-21mod980n preliminary technical data gnd af16 gnd af17 gnd af21 gnd af23 gnd af26 gnd b2 gnd b5 gnd b11 gnd b12 gnd b16 gnd b19 gnd b21 gnd b25 gnd c3 gnd c5 gnd c11 gnd c16 gnd c19 gnd c21 gnd c24 gnd d4 gnd d5 gnd d11 gnd d16 gnd ac12 gnd ac17 gnd ac21 gnd ac23 gnd ad2 gnd ad3 table 18. pinout by signal name (continued) signal name pin gnd ad4 gnd ad5 gnd ad7 gnd ad8 gnd ad11 gnd ad12 gnd ad16 gnd ad17 gnd ad21 gnd ad22 gnd ad23 gnd ad24 gnd ae1 gnd ae2 gnd ae4 gnd ae8 gnd ae10 gnd ae12 gnd ae16 gnd ae17 gnd ae21 gnd ae23 gnd ae25 gnd a1 gnd a5 gnd a11 gnd a16 gnd a19 gnd a20 gnd a21 table 18. pinout by signal name (continued) signal name pin gnd a26 gnd aa23 gnd aa24 gnd aa25 gnd aa26 gnd ac4 gnd ac6 gnd ac8 gnd ac10 gnd w23 iack _a t4 iack _b ac26 iad0_a b4 iad0_b v26 iad1_a b1 iad1_b v23 iad10_a aa2 iad10_b l26 iad11_a v3 iad11_b l23 iad12_a aa4 iad12_b m25 iad13_a e2 iad13_b ad26 iad14_a d1 iad14_b ac24 iad15_a e4 iad15_b ac25 iad2_a c2 iad2_b v24 table 18. pinout by signal name (continued) signal name pin iad3_a d3 iad3_b w24 iad4_a c1 iad4_b w25 iad5_a d2 iad5_b w26 iad6_a v4 iad6_b m26 iad7_a y4 iad7_b n26 iad8_a ad6 iad8_b m23 iad9_a y3 iad9_b m24 ial_a c8 ial_b y25 ird _a c4 ird _b y24 is _1 d6 is _2 a14 is _3 f24 is _4 aa3 is _5 v25 is _6 ac7 is _7 ac16 is _8 y26 iwr _a d8 iwr _b y23 pf0 a6 pf1 b6 table 18. pinout by signal name (continued) signal name pin
38 6/ 20 01 r e v . p rb for current information contact analog devices at (800) analogd a d sp- 2 1mo d 9 8 0n preliminary technical data pf2 c6 pf4_1 m1 pf4_2 c10 pf4_3 d18 pf4_4 ac2 pf4_5 l25 pf4_6 t1 pf4_7 af7 pf4_8 ad18 pf5_1 m2 pf5_2 d10 pf5_3 c18 pf5_4 ac3 pf5_5 g24 pf5_6 v1 pf5_7 ae11 pf5-8 ae18 pf6_1 m3 pf6_2 b10 pf6_3 b18 pf6_4 ad1 pf6_5 r26 pf6_6 t2 pf6_7 ad9 pf6_8 ac18 pf7_1 j4 pf7_2 d12 pf7_3 a18 pf7_4 ae3 pf7_5 n25 table 18. pinout by signal name (continued) signal name pin pf7_6 v2 pf7_7 af9 pf7_8 af18 reset _1 j1 reset _2 d13 reset _3 c22 reset _4 af6 reset _5 t23 reset _6 aa1 reset _7 ac11 reset _8 ac22 rfs0a j3 rfs0b ad20 rfs1 ae6 sclk0a p1 sclk0b ae24 sclk1 af5 tfs0_1 j2 tfs0_2 c12 tfs0_3 b20 tfs0_4 ae5 tfs0_5 n23 tfs0_6 y1 tfs0_7 af11 tfs0_8 ac20 tfs1 af3 vddext b22 vddext c7 vddext c9 vddext c14 table 18. pinout by signal name (continued) signal name pin vddext c15 vddext c17 vddext d7 vddext d9 vddext d15 vddext d17 vddext d22 vddext k1 vddext k2 vddext k3 vddext k4 vddext k23 vddext k24 vddext k25 vddext k26 vddext l1 vddext l2 vddext l3 vddext l4 vddext a7 vddext a8 vddext a9 vddext a13 vddext a15 vddext a17 vddext ac14 vddext ac15 vddext ac19 vddext ad14 vddext ad19 table 18. pinout by signal name (continued) signal name pin vddext ae14 vddext ae19 vddext af14 vddext af19 vddext b7 vddext b8 vddext b9 vddext b14 vddext b15 vddext b17 vddint a3 vddint a4 vddint ab1 vddint ab2 vddint ab3 vddint ab4 vddint ab23 vddint ab24 vddint ab25 vddint ab26 vddint ae13 vddint af13 vddint af24 vddint af25 vddint b3 vddint p23 vddint p24 vddint p25 vddint p26 table 18. pinout by signal name (continued) signal name pin
39 r e v . p rb 6/2001 for current information contact analog devices at (800) analogd adsp-21mod980n preliminary technical data vddint r1 vddint r2 vddint r3 table 18. pinout by signal name (continued) signal name pin
40 6 /2 00 1 r e v . p rb for current information contact analog devices at (800) analogd a d sp- 2 1mo d 9 8 0n preliminary technical data signals by pin location?top view, left to right 1 234 5678910 111213 a gnd a0 vddint vddint gnd pf0 vddext vddext vddext clkout_2 gnd dt1_2 vddext b iad1_a gnd vddint iad0_a gnd pf1 vddext vddext vddext pf6_2 gnd gnd br_2 c iad4_a iad2_a gnd ird_a gnd pf2 vddext ial_a vddext pf4_2 gnd tfs0_2 ee_2 d iad14_a iad6_a iad3_a gnd gnd is_1 vddext iwr_a vddext pf5_2 gnd pf7_2 reset_2 e dr0a iad13_a clkin iad15_a f gnd gnd bg_1 gnd g clkout_1 gnd gnd br_1 h gnd gnd gnd gnd j reset_1 tfs0_1 rfs0a pf7_1 k vddext vddext vddext vddext l vddext vddext vddext vddext m pf4_1 pf5_1 pf6_1 ee_1 n gnd gnd gnd gnd p sclk0a dt0a dt1_1 clkout_6 r vddint vddint vddint bg_6 t pf4_6 pf6_6 gnd iack_a u gnd gnd dt1_6 br_6 v pf5_6 pf7_6 iad11_a iad6_a w gnd gnd gnd gnd y tfs0_6 ee_6 iad9_a iad7_a aa reset_6 iad10_a is_4 iad12_a ab vddint vddint vddint vddint ac clkout_4 pf4_4 pf5_4 gnd bg_4 gnd is_6 gnd br_4 gnd reset_7 gnd ee_7 ad pf6_4 gnd gnd gnd gnd iad8_a gnd gnd pf6_7 clkout_7 gnd gnd dt1_7 ae gnd gnd pf7_4 gnd tfs0_4 rfs1 dr1 gnd ee_4 gnd pf5_7 gnd vddint af gnd dt1_4 tfs1 gnd sclk1 reset_4 pf4_7 gnd pf7_7 gnd tfs0_7 gnd vddint 1 234 5678910 111213
41 r e v . p rb 6/2001 for current information contact analog devices at (800) analogd adsp-21mod980n preliminary technical data outline dimensions ? 352 plastic ball grid array signals by pin location ? top view, left to right (continued) 14 15 16 17 18 19 20 21 22 23 24 25 26 is_2 vddext gnd vddext pf7_3 gnd gnd gnd d23 d22 d21 d18 gnd a vddext vddext gnd vddext pf6_3 gnd trs0_3 gnd vddext d19 d17 gnd d16 b vddext vddext gnd vddext pf5_3 gnd clkout_3 gnd reset_3 d20 gnd d15 d14 c bg_2 vddext gnd vddext pf4_3 gnd gnd dt1_3 vddext gnd d13 d12 d11 d ems d10 d09 ereset e d08 is_3 bg_3 ebg f ee_3 pf5_5 br_3 ebr g gnd g nd gnd g nd h eclk elout elin eint j vddext vddext vddext vddext k iad11_b clkout_5 pf4_5 iad10_b l iad8_b iad9_b iad12_b iad6_b m tfs0_5 br_5 pf7_5 iad7_b n vddint vddint vddint vddint p gnd gnd bg_5 pf6_5 r reset_5 gnd dt1_5 ee_5 t gnd g nd gnd g nd u iad1_b iad2_b is_5 iad0_b v gnd iad3_b iad4_b iad5_b w iwr_b ird_b ial_b is_8 y gnd g nd gnd g nd aa vddint vddint vddint vddint ab vddext vddext is_7 gnd pf6_8 vddext tfs0_8 gnd reset_8 gnd iad14_b iad15_b iack_b ac vddext bg_7 gnd gnd pf4_8 vddext rfs0b gnd gnd gnd gnd bg_8 iad13_b ad vddext br_7 gnd gnd pf5_8 vddext dt1_8 gnd ee_8 gnd sclk0b gnd br_8 ae vddext clkout_8 gnd gnd pf7_8 vddext dt0b gnd dr0b gnd vddint vddint gnd af 14 15 16 17 18 19 20 21 22 23 24 25 26
42 6 /2 00 1 r e v . p rb for current information contact analog devices at (800) analogd a d sp- 2 1mo d 9 8 0n preliminary technical data ordering guide a complete modem requires the device listed in table 19 plus a software solution as described in m odem s oftware on page 2. figure 28. 352-lead metric plastic ball grid array (pbga) (b-352) detail a 2.62 2.37 2.12 bottom view a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 25 23 21 19 17 15 13 11 9 7 5 3 1 26 24 22 20 18 16 14 12 10 8 6 4 2 1.27 bsc sq ball pitch 31.75 bsc sq 35.00 bsc sq top view ball a1 indicator 30.70 30.00 sq 29.50 1.22 1.17 1.12 seating plane 0.20 max detail a 0.90 0.75 0.60 ball diameter 0.70 0.60 0.50 0.70 0.60 0.50 notes: 1. the actual position of the ball grid is within 0.30 of the ideal position relative to the package edges. 2. the actual position of each ball is within 0.15 of its ideal position relative to the ball grid. 3. center figures are nominal unless otherwise noted. table 19. ordering guide part number ambient temperature range instruction rate package description package option ADSP-21MOD980N-000 0 o c to +70 o c 80 mhz 352-ball pbga b-352

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