1 ps8372 12/17/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74alvchr16269 12-bit to 24-bit registered bus exchanger with 3-state outputs logic block diagram product description pericom semiconductor?s pi74alvch series of logic circuits are produced using the company?s advanced 0.5 micron cmos technology, achieving industry leading speed. the pi7alvchr16269 is used in applications in which two separate ports must be multiplexed onto, or demultiplexed from, a single port. it is particularly suitable as an interface between synchronous dram?s and high-speed microprocessors. data is stored on the internal b-port registers on the low-to-high transition of the clock (clk) input when the appropriate clock-enable (clkena) inputs are low. proper control of these inputs allows two sequential 12-bit words to be presented as a 24-bit word on the b-port. for data transfer in the b-to-a direction, a single storage register is provided. the select (sel) line selects 1b or 2b data for the a outputs. the register on the a output permits the fastest possible data transfer, thus extending the period during which the data is valid on the bus. the control terminals are registered so that all transactions are synchronous with clk. data flow is controlled by the active-low output enables (oea, oeb1, and oeb2). to ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible and oe should be tied to v cc through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. due to oe being routed through a register, the active state of the outputs cannot be determined prior to the arrival of the first clock pulse. active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. all outputs are designed to sink up to 12ma and include 26-ohm resistors to reduce overshoot and undershoot. product features pi74alvchr16269 is designed for low voltage operation v cc = 2.3v to 3.6v hysteresis on all inputs typical v olp (output ground bounce) < 0.8v at v cc = 3.3v, t a = 25c typical v ohv (output v oh undershoot) < 2.0v at v cc = 3.3v, t a = 25c all output ports have equivalent 26w series resistors, no external resistors are required bus hold retains last active bus state during 3-state, eliminating the need for external pullup resistors industrial operation at ?40c to +85c packages available: ? 56-pin 240 mil wide plastic tssop (a) ? 56-pin 300 mil wide plastic ssop (v)
2 ps8372 12/17/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74alvchr16269 12-bit to 24-bit registered bus exchanger with 3-state outputs s t u p n is t u p t u o k l ca e ob e oa b 2 , b 1 - hhz z - hlz e v i t c a - lh e v i t c az - ll e v i t c ae v i t c a notes: 1. h = high signal level l = low signal level x = irrelevant z = high impedance - = transition, low to high 2. output level before indicated steady state input conditions e stablished s t u p n i s t u p t u o a k l cl e sb 1b 2 xhxx0 a ) 2 ( xlxx0 a ) 2 ( - hlxl - h h xh - lxll - lxhh s t u p n is t u p t u o 1 a n e k l c2 a n e k l ck l cab 1b 2 lh - llb 2 0 ) 2 ( lh - hhb 2 0 ) 2 ( ll - ll l ll - hh h hl - lb 1 0 ) 2 ( l hl - hb 1 0 ) 2 ( h hhxxb 1 0 ) 2 ( b 2 0 ) 2 ( pin name description oe output enable input (active low) clk clock sel select (active low) clken clock enable (active low) a,1b,2b 3-state outputs gnd ground vcc power 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 25 26 27 28 32 31 30 29 product pin description product pin configuration 56-pin a, v oea oeb1 2b3 gnd 2b2 2b1 v cc a1 a2 a3 gnd a4 a5 a6 a7 a8 a9 gnd a10 a11 a12 v cc 1b1 1b2 gnd 1b3 nc sel oeb2 clkena2 2b4 gnd 2b5 2b6 v cc 2b7 2b8 2b9 gnd 2b10 2b11 2b12 1b12 1b11 1b10 gnd 1b9 1b8 1b7 v cc 1b6 1b5 gnd 1b4 clkena1 clk truth tables (1) a to b storage (oeb = l) b to a storage (oea = l)
3 ps8372 12/17/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74alvchr16269 12-bit to 24-bit registered bus exchanger with 3-state outputs note: 1. unused control inputs must be held high or low to prevent them from floating. dc electrical characteristics (over the operating range, t a = ?40c to +85c, v cc = 3.3v 10%) s r e t e m a r a pn o i t p i r c s e ds n o i t i d n o c t s e t. n i m. p y t. x a ms t i n u v c c e g a t l o v y l p p u s3 . 26 . 3 v v h i ) 1 ( e g a t l o v h g i h t u p n i v c c v 7 . 2 o t v 3 . 2 =7 . 1 v c c v 6 . 3 o t v 7 . 2 =0 . 2 v l i ) 1 ( e g a t l o v w o l t u p n i v c c v 7 . 2 o t v 3 . 2 =7 . 0 v c c v 6 . 3 o t v 7 . 2 =8 . 0 v n i ) 1 ( e g a t l o v t u p n i0v c c v t u o ) 1 ( e g a t l o v t u p t u o0v c c i h o ) 1 ( l e v e l - h g i h t n e r r u c t u p t u o 6 ? a m 8 ? v c c v 0 . 3 =2 1 ? i l o ) 1 ( l e v e l - w o l t n e r r u c t u p t u o v c c v 3 . 2 =6 v c c v 7 . 2 =8 v c c v 0 . 3 =2 1 t a e r u t a r e p m e t r i a - e e r f g n i t a r e p o0 4 -5 8c o d / t a v e t a r l l a f r o e s i r n o i t i s n a r t t u p n i0 1v / s n note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) storage temperature ................................................ ?65c to +150c supply voltage range, v cc ................................................. ?0.5v to 4.6v input voltage range,v i : except i/o ports (1) ................................................................................ ?0.5v to 4.6v i/o ports (1,2) ............................................................... ?0.5v to v cc + 0.5v output voltage range, v o (1,2) .............................. ?0.5v to v cc + 0.5v input clamp current, i ik (v i < 0) ............................................ ?50ma output clamp current, i ok (v o < 0) ....................................... ?50ma continous output current, i o .................................................. 50ma continous current through each v cc or gnd ...................... 100ma maximum power dissipation: a package ........................................................................................ 1w v package .....................................................................................1.4w notes: 1. the input and output negative-voltage ratings maybe exceeded if the input and outputclamp-current ratings are observed. 2. this value is limited to 4.6v maximum.
4 ps8372 12/17/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74alvchr16269 12-bit to 24-bit registered bus exchanger with 3-state outputs s r e t e m a r a ps n o i t i d n o c t s e tv c c ) 1 ( . n i m. p y t ) 2 ( . x a ms t i n u v h o i h o =0 1 - 0a m . x a m o t . n i mv c c 2 . 0 - v i h o =4 -m a v h i =v 7 . 1v 3 . 29 . 1 v h i =v 0 . 2v 7 . 22 . 2 i h o =6 -m a v h i =v 7 . 1v 3 . 27 . 1 v h i =v 0 . 2v 0 . 34 . 2 i h o =8 -m a v h i =v 0 . 2v 7 . 20 . 2 i h o =2 1 -m a v h i =v 0 . 2v 0 . 30 . 2 v l o i l o =0 1 0a m . x a m o t . n i m2 . 0 i l o =4m a v l i =v 7 . 0v 3 . 24 . 0 v l i =v 8 . 0v 7 . 24 . 0 i l o =6m a v l i =v 7 . 0v 3 . 25 5 . 0 v l i =v 8 . 0v 0 . 35 5 . 0 i l o =8m a v l i =v 8 . 0v 7 . 26 . 0 i l o =2 1m a v l i =v 8 . 0v 0 . 38 . 0 i i v i =v cc r od n gv 6 . 35 a m i i ) d l o h ( ) 3 ( v i =v 7 . 0 v 3 . 2 5 4 v i =v 7 . 15 4 - v i =v 8 . 0 v 0 . 3 5 7 v i =v 0 . 25 7 - v i =0 v 6 . 3 o tv 6 . 30 0 5 i z o ) 4 ( v o =v c c d n g r ov 6 . 30 1 i c c v i =v c c i , d n g r o o 0 =v 6 . 30 4 i d c c v t a t u p n i e n o c c r e h t o , v 6 . 0 - v t a s t u p n i c c d n g r o v 6 . 3 o t v 30 5 7 c i cl o r t n ois t u p nv i =v c c d n g r ov 3 . 35 . 3 f p c o i ar obp s t r ov o =v c c d n g r ov 3 . 35 . 8 dc electrical characteristics -continued (over the operating range, t a = -40oc to +85oc, v cc = 3.3v 10% notes: 1. for max. or min. conditions, use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at v cc = 3.3v, +25oc ambient and maximum loading. 3. bus hold maximum dynamic current required to switch the input from one state to another 4. for i/o ports, the i oz includes the input leakage current.
5 ps8372 12/17/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74alvchr16269 12-bit to 24-bit registered bus exchanger with 3-state outputs s r e t e m a r a pn o i t p i r c s e d v c c v 5 . 2 = v 2 . 0v c c v 7 . 2 = v c c v 3 . 3 = v 3 . 0 s t i n u . n i m. x a m. n i m. x a m. n i m. x a m f k c o l c y c n e u q e r f k c o l c5 95 1 15 3 1z h m t w k l c , n o i t a r u d e s l u p w o l r o h g i h 2 . 53 . 43 . 3 s n t u s e m i t p u t e s k l c e r o f e b a t a d a - 4 . 14 . 11 k l c e r o f e b a t a d b - 6 . 15 . 11 . 1 k l c e r o f e b l e s - 8 . 01 . 13 . 1 a n e k l c r o 1 a n e k l c 2 k l c e r o f e b - 8 . 018 . 0 k l c e r o f e b a t a d e o - 7 . 16 . 12 . 1 t h e m i t d l o h k l c r e t f a a t a d a - 9 . 09 . 02 . 1 k l c r e t f a a t a d b - 8 . 06 . 01 k l c r e t f a l e s - 1 . 18 . 07 . 1 a n e k l c r o 1 a n e k l c 2 k l c r e t f a - 4 . 116 . 1 k l c r e t f a e o - 9 . 08 . 02 . 1 timing requirements over operating range notes: 1. unused control inputs must be held high or low to prevent them from floating. 2. minimum limits are guaranteed but not tested on propagation delays. switching characteristics over operating range (1) s r e t e m a r a p m o r f ) t u p n i ( o t ) t u p t u o ( v c c v 2 . 0 v 5 . 2 =v c c v 7 . 2 =v c c v 3 . 0 v 3 . 3 = s t i n u . n i m ) 2 ( . x a m. n i m ) 2 ( . x a mn i m . ) 2 ( . x a m f x a m 5 95 1 15 3 1 s n t d p k l c b3 . 27 . 79 . 62 . 28 . 5 a9 . 14 . 68 . 522 . 5 t n e b5 . 27 . 79 . 63 . 28 . 5 a2 . 27 . 661 . 23 . 5 t s i d b3 . 31 . 87 . 64 . 26 a7 . 28 2 . 61 . 26 pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com operating characteristics, ta = 25 c r e t e m a r a p t s e t s n o i t i d n o c v c c v 2 . 0 v 5 . 2 =v c c v 3 . 0 v 3 . 3 = s t i n u l a c i p y t c d p e c n a t i c a p a c n o i t a p i s s i d r e w o p r e g n a h c x e r e p d e l b a n e s t u p t u o c l , f p 0 = z h m 0 1 = f 2 4 12 7 1 f p d e l b a s i d s t u p t u o5 1 19 2 1
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