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wideband, single-supply operational amplifiers opa634 opa635 features high bandwidth: 150mhz (g = +2) +3v to +10v supply operation zero power disable (opa635) input range includes ground 4.8v output swing on +5v supply high output current: 80ma high slew rate: 250v/ s low input voltage noise: 5.6nv/ hz available in sot23 package description the opa634 and opa635 are low-power, voltage- feedback, high-speed amplifiers designed to operate on +3v or +5v single-supply voltages. operation on 5v or +10v supplies is also supported. the input range extends below ground and to within 1.2v of the positive supply. using complementary common-emitter outputs provides an output swing to within 30mv of ground and 140mv of positive supply. the high output drive cur- rent, low differential gain and phase errors make them ideal for single-supply composite video line driving. low-distortion operation is ensured by the high gain bandwidth product (140mhz) and slew rate (250v/ s). this makes the opa634 and opa635 ideal input buffer stages to 3v and 5v cmos converters. unlike other low-power, single-supply operational amplifiers, distor- tion performance improves as the signal swing is de- creased. a low 5.6nv input voltage noise supports wide dynamic range operation. multiplexing or system power reduc- tion can be achieved using the high-speed disable line with the opa635. power dissipation can be reduced to zero by taking the disable line high. the opa634 and opa635 are available in an industry standard so-8 package. the opa634 is also available in an ultra-small sot23-5 package, while the opa635 is available in the sot23-6. where lower supply current and speed are required, consider the opa631 and opa632. applications single-supply adc input buffers single supply video line drivers wireless lan if amplifiers ccd imaging channels low-power ultrasound tm o p a 6 3 4 description singles duals medium speed, no disable opa631 opa2631 with disable opa632 high speed, no disable opa634 opa2634 with disable opa635 related products copyright ?1999, texas instruments incorporated sbos097a printed in u.s.a. february, 2001 www.ti.com opa635 v in 750 ? 562 ? 2.26k ? 374 ? 22pf +3v 100 ? pwrdn dis disable +3v ads900 10-bit 20msps
opa634, opa635 2 sbos097a opa634u, n opa635u, n typ guaranteed 0 c to C40 c to min/ test parameter conditions +25 c +25 c70 c +85 c units max level (1) specifications: v s = +5v at t a = 25 c, g = +2, r f = 750 ? , and r l = 150 ? to v s /2, unless otherwise noted (see figure 1). ac performance (figure 1) small-signal bandwidth g = +2, v o 0.5vp-p 150 100 84 78 mhz min b g = +5, v o 0.5vp-p 36 24 20 18 mhz min b g = +10, v o 0.5vp-p 16 11 10 8 mhz min b gain bandwidth product g +10 140 100 82 75 mhz min b peaking at a gain of +1 v o 0.5vp-p 5 db typ c slew rate g = +2, 2v step 250 170 125 115 v/ s min b rise time 0.5v step 2.4 3.4 4.7 5.2 ns max b fall time 0.5v step 2.4 3.5 4.5 4.8 ns max b settling time to 0.1% g = +2, 1v step 15 19 22 23 ns max b spurious free dynamic range v o = 2vp-p, f = 5mhz 63 56 51 50 dbc min b input voltage noise f > 1mhz 5.6 6.2 7.3 7.7 nv/ hz max b input current noise f > 1mhz 2.8 3.8 4.2 5 pa/ hz max b ntsc differential gain 0.10 % typ c ntsc differential phase 0.16 degrees typ c dc performance open-loop voltage gain 66 63 60 53 db min a input offset voltage 3 7 8 10 mv max a average offset voltage drift 4.6 v/ c max b input bias current v cm = 2.0v 25 47 57 84 a max a input offset current v cm = 2.0v 0.6 2.25 2.6 4.5 a max a input offset current drift 15 na/ c max b input least positive input voltage C 0.24 C 0.1 C 0.05 C 0.01 v max b most positive input voltage 3.8 3.5 3.45 3.4 v min a common-mode rejection (cmrr) input referred 78 73 71 63 db min a input impedance differential-mode 10 || 2.1 k ? || pf typ c common-mode 400 || 1.2 k ? || pf typ c output least positive output voltage r l = 1k ? to 2.5v 0.03 0.07 0.08 0.09 v max a r l = 150 ? to 2.5v 0.1 0.14 0.15 0.22 v max a most positive output voltage r l = 1k ? to 2.5v 4.86 4.8 4.75 4.7 v min a r l = 150 ? to 2.5v 4.65 4.55 4.5 4.4 v min a current output, sourcing 80 50 45 20 ma min a current output, sinking 100 73 59 18 ma min a short-circuit current (output shorted to either supply) 100 ma typ c closed-loop output impedance g = +2, f 100khz 0.2 ? typ c disable (opa635 only) on voltage (device enabled low) 1.0 1.0 1.0 1.0 v max a off voltage (device disabled high) 4.0 4.1 4.2 4.3 v min a on disable current (dis pin) 70 110 120 120 a max a off disable current (dis pin) 0 a typ c disabled quiescent current 0 30 40 50 a max a disable time 100 ns typ c enable time 60 ns typ c off isolation f = 5mhz, input to output 70 db typ c power supply minimum operating voltage 2.7 2.7 2.7 v min b maximum operating voltage 10.5 10.5 10.5 v max a maximum quiescent current 12 12.7 13.2 13.5 ma max a minimum quiescent current 12 11.3 9.75 8.5 ma min a power supply rejection ratio (psrr) input referred 55 52 50 49 db min a thermal characteristics specification: u, n C 40 to +85 c typ c thermal resistance u so-8 125 c/w typ c n sot23-5, sot23-6 150 c/w typ c note: (1) test levels: (a) 100% tested at 25 c. over temperature limits by characterization and simulation. (b) limits set by characterization and simulation. (c) typical value only for information.
opa634, opa635 3 sbos097a opa634u, n opa635u, n typ guaranteed 0 c to C40 c to min/ test parameter conditions +25 c +25 c70 c +85 c units max level (1) specifications: v s = +3v at t a = 25 c, g = +2 and r l = 150 ? to v s /2, unless otherwise noted (see figure 2). ac performance (figure 2) small-signal bandwidth g = +2, v o 0.5vp-p 110 77 65 58 mhz min b g = +5, v o 0.5vp-p 39 24 20 19 mhz min b g = +10, v o 0.5vp-p 16 12 10 8 mhz min b gain bandwidth product g +10 150 100 85 80 mhz min b peaking at a gain of +1 v o 0.5vp-p 5 db typ c slew rate 1v step 215 160 123 82 v/ sminb rise time 0.5v step 2.8 4.3 4.5 6.3 ns max b fall time 0.5v step 3.0 4.4 4.6 6.0 ns max b settling time to 0.1% 1v step 14 30 32 38 ns max b spurious free dynamic range v o = 1vp-p, f = 5mhz 65 56 52 47 dbc min b input voltage noise f > 1mhz 5.6 6.2 7.3 7.7 nv/ hz max b input current noise f > 1mhz 2.8 3.7 4.2 4.4 pa/ hz max b dc performance open-loop voltage gain 67 61 57 53 db min a input offset voltage 1.5 4 5 6 mv max a average offset voltage drift 46 v/ c max b input bias current v cm = 1.0v 25 45 59 64 a max a input offset current v cm = 1.0v 0.6 2 2.3 4 a max a input offset current drift 40 na/ c max b input least positive input voltage C 0.25 C 0.1 C 0.05 C 0.01 v max b most positive input voltage 1.8 1.6 1.55 1.5 v min a common-mode rejection (cmrr) input referred 75 65 62 59 db min a input impedance differential-mode 10 || 2.1 k ? || p typ c common-mode 400 || 1.2 k ? || p typ c output least positive output voltage r l = 1k ? to 1.5v 0.035 0.043 0.045 0.06 v max a r l = 150 ? to 1.5v 0.06 0.16 0.19 0.43 v max a most positive output voltage r l = 1k ? to 1.5v 2.9 2.86 2.85 2.45 v min a r l = 150 ? to 1.5v 2.8 2.70 2.69 2.65 v min a current output, sourcing 45 35 30 12 ma min a current output, sinking 65 30 27 10 ma min a short circuit current (output shorted to either supply) 100 ma typ c closed-loop output impedance figure 2, f < 100khz 0.2 ? typ c disable (opa635 only) on voltage (device enabled low) 1.0 0.5 0.5 0.5 v max a off voltage (device disabled high) 1.8 1.9 2.1 2.2 v min a on disable current (dis pin) 66 100 110 110 a max a off disable current (dis pin) 0 a typ c disabled quiescent current 0 30 40 50 a max a disable time 100 ns typ c enable time 60 ns typ c off isolation f = 5mhz, input to output 70 db typ c power supply minimum operating voltage 2.7 2.7 2.7 v min b maximum operating voltage 10.5 10.5 10.5 v max a maximum quiescent current 10.8 11.5 11.8 12 ma max a minimum quiescent current 10.8 10.1 8.6 8.0 ma min a power supply rejection ratio (psrr) input referred 50 49 45 44 db min a thermal characteristics specification: u, n C 40 to +85 c typ c thermal resistance u so-8 125 c/w typ c n sot23-5, sot23-6 150 c/w typ c note: (1) test levels: (a) 100% tested at 25 c. over temperature limits by characterization and simulation. (b) limits set by characterization and simulation. (c) typical value only for information.
opa634, opa635 4 sbos097a 1 2 3 4 8 7 6 5 nc inverting input non-inverting input gnd dis (opa635 only) +v s output nc pin configurations absolute maximum ratings power supply ................................................................................ +11v dc internal power dissipation .................................... see thermal analysis differential input voltage .................................................................. 1.2v input voltage range ............................................................... C 0.5 to +v s storage temperature range: p, u, n ........................... C 40 c to +125 c lead temperature (soldering, 10s) .............................................. +300 c junction temperature (t j ) ........................................................... +175 c electrostatic discharge sensitivity electrostatic discharge can cause damage ranging from perfor- mance degradation to complete device failure. burr-brown corpo- ration recommends that all integrated circuits be handled and stored using appropriate esd protection methods. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. 1 2 3 6 5 4 output gnd non-inverting input +v s dis inverting input a35 1 2 3 6 5 4 pin orientation/package marking package specified drawing temperature package ordering transport product package number range marking number (1) media opa634u so-8 surface-mount 182 C 40 c to +85 c opa634u opa634u rails """"" opa634u/2k5 tape and reel opa634n sot23-5 331 C 40 c to +85 c b34 opa634n/250 tape and reel """"" opa634n/3k tape and reel opa635u so-8 surface-mount 182 C 40 c to +85 c opa635u opa635u rails """"" opa635u/2k5 tape and reel opa635n sot23-6 332 C 40 c to +85 c a35 opa635n/250 tape and reel """"" opa635n/3k tape and reel note: (1) models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2k5 indicates 2500 de vices per reel). ordering 3000 pieces of opa635n/3k will get a single 3000-piece tape and reel. package/ordering information 1 2 3 6 4 output gnd non-inverting input +v s inverting input b34 1 2 3 6 4 pin orientation/package marking top viewopa634, opa635 so top viewopa634 sot23-5 top viewopa635 sot23-6
opa634, opa635 5 sbos097a typical performance curves: v s = +5v at t a = 25 c, g = +2, r f = 750 ? , and r l = 150 ? to v s /2, unless otherwise noted (see figure 1). 6 3 0 C 3 C 6 C 9 C 12 C 15 C 18 small-signal frequency response frequency (mhz) normalized gain (db) 1 10 100 300 v o = 0.2vp-p g = +10 g = +2 g = +5 12 9 6 3 0 C 3 C 6 C 9 C 12 large-signal frequency response frequency (mhz) gain (db) 1 10 100 300 v o = 0.2vp-p v o = 4vp-p v o = 2vp-p v o = 1vp-p small-signal pulse response time (10ns/div) input and output voltage (50mv/div) v o = 200mvp-p v o v in large-signal pulse response time (10ns/div) input and output voltage (500mv/div) v o = 2vp-p v o v in C 35 C 40 C 45 C 50 C 55 C 60 C 65 C 70 C 75 C 80 C 85 disable feedthrough vs frequency frequency (mhz) 1 10 100 1000 feedthrough (db) opa635 only v dis = +5v large-signal disable/enable response time (50ns/div) disable voltage (1v/div) output voltage (250mv/div) v in = 0.5v opa635 only v o v dis
opa634, opa635 6 sbos097a typical performance curves: v s = +5v (cont.) at t a = 25 c, g = +2, r f = 750 ? , and r l = 150 ? to v s /2, unless otherwise noted (see figure 1). C 40 C 45 C 50 C 55 C 60 C 65 C 70 C 75 C 80 C 85 C 90 5mhz 2nd-harmonic distortion vs output voltage output voltage (vp-p) 1 0.1 4 2nd-harmonic distortion (dbc) r l = 150 ? r l = 250 ? r l = 500 ? C 40 C 45 C 50 C 55 C 60 C 65 C 70 C 75 C 80 C 85 C 90 5mhz 3rd-harmonic distortion vs output voltage output voltage (vp-p) 1 0.1 4 3rd-harmonic distortion (dbc) r l = 500 ? r l = 250 ? r l = 150 ? C 40 C 45 C 50 C 55 C 60 C 65 C 70 C 75 C 80 C 85 C 90 10mhz 2nd-harmonic distortion vs output voltage output voltage (vp-p) 1 0.1 4 2nd-harmonic distortion (dbc) r l = 150 ? r l = 250 ? r l = 500 ? C 40 C 45 C 50 C 55 C 60 C 65 C 70 C 75 C 80 C 85 C 90 10mhz 3rd-harmonic distortion vs output voltage output voltage (vp-p) 1 0.1 4 3rd-harmonic distortion (dbc) r l = 250 ? r l = 150 ? r l = 500 ? C 40 C 45 C 50 C 55 C 60 C 65 C 70 C 75 C 80 C 85 C 90 20mhz 2nd-harmonic distortion vs output voltage output voltage (vp-p) 1 0.1 4 2nd-harmonic distortion (dbc) r l = 500 ? r l = 150 ? r l = 250 ? C 40 C 45 C 50 C 55 C 60 C 65 C 70 C 75 C 80 C 85 C 90 20mhz 3rd-harmonic distortion vs output voltage output voltage (vp-p) 1 0.1 4 3rd-harmonic distortion (dbc) r l = 500 ? r l = 150 ? r l = 250 ?
opa634, opa635 7 sbos097a typical performance curves: v s = +5v (cont.) at t a = 25 c, g = +2, r f = 750 ? , and r l = 150 ? to v s /2, unless otherwise noted (see figure 1). C 40 C 45 C 50 C 55 C 60 C 65 C 70 C 75 C 80 C 85 C 90 2nd-harmonic distortion vs frequency frequency (mhz) 10 120 2nd-harmonic distortion (dbc) v o = 2vp-p r l = 100 ? g = +2 g = +10 g = +5 C 40 C 45 C 50 C 55 C 60 C 65 C 70 C 75 C 80 C 85 C 90 3rd-harmonic distortion vs frequency frequency (mhz) 10 120 3rd-harmonic distortion (dbc) v o = 2vp-p r l = 100 ? g = +5 g = +2 g = +10 C 40 C 45 C 50 C 55 C 60 C 65 C 70 C 75 C 80 C 85 C 90 harmonic distortion vs load resistance r l ( ? ) 100 200 300 400 500 harmonic distortion (dbc) v o = 2vp-p f o = 5mhz 3rd-harmonic distortion 2nd-harmonic distortion C 40 C 45 C 50 C 55 C 60 C 65 C 70 C 75 C 80 C 85 C 90 two-tone, 3rd-order intermodulation spurious single-tone load power (dbm) C 16 C 14 C 12 C 10 C 8 C 6 C 4 C 20 3rd-order spurious level (dbc) f o = 5mhz f o = 10mhz f o = 20mhz load power at matched 50 ? load 80 75 70 65 60 55 50 45 40 35 30 cmrr and psrr vs frequency frequency (hz) 100 1k 10k 100k 1m 10m rejection ratio, input referred (db) psrr cmrr 100 10 1 input noise density vs frequency frequency (hz) 100 1k 10k 100k 1m 10m voltage noise (nv/ hz) current noise (pa/ hz) voltage noise, e ni = 5.6nv/ hz current noise, i ni = 2.8pa/ hz
opa634, opa635 8 sbos097a typical performance curves: v s = +5v (cont.) at t a = 25 c, g = +2, r f = 750 ? , and r l = 150 ? to v s /2, unless otherwise noted (see figure 1). 1000 100 10 1 r s vs capacitive load capacitive load (pf) 1 10 100 1000 r s ( ? ) 2 1 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 C 8 frequency response vs capacitive load frequency (mhz) 1 10 100 300 normalized gain (db) v o = 0.2vp-p r s opa63x v o 1k ? c l +v s /2 c l = 100pf c l = 1000pf c l = 10pf 100 90 80 70 60 50 40 30 20 10 0 C 10 C 20 open-loop gain and phase frequency (hz) 1k 10k 100k 1m 10m 100m 1g open-loop gain (db) 0 C 30 C 60 C 90 C 120 C 150 C 180 C 210 C 240 C 270 C 300 C 330 C 360 open-loop phase ( ) open-loop phase open-loop gain 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 input dc errors vs temperature temperature ( c) C 40 C 20 0 20 40 60 80 100 input offset voltage (mv) 50 45 40 35 30 25 20 15 10 5 0 input bias current ( a) 10x input offset current ( a) input offset voltage input bias current 10x input offset current 100 10 1 0.1 closed-loop output impedance vs frequency frequency (hz) 1k 10k 100k 1m 10m 100m output impedance ( ? ) g = +1 r f = 25 ? 16 14 12 10 8 6 4 2 0 supply and output current vs temperature temperature ( c) C 40 C 20 0 20 40 60 80 100 power-supply current (ma) 160 140 120 100 80 60 40 20 0 output current (ma) sinking output current sourcing output current quiescent supply current
opa634, opa635 9 sbos097a typical performance curves: v s = +3v at t a = 25 c, g = +2, r f = 750 ? , and r l = 150 ? to v s /2, unless otherwise noted (see figure 2). 12 9 6 3 0 C 3 C 6 C 9 C 12 large-signal frequency response frequency (mhz) gain (db) 1 10 100 300 v o = 0.2vp-p v o = 2vp-p v o = 1vp-p 6 3 0 C 3 C 6 C 9 C 12 C 15 C 18 small-signal frequency response frequency (mhz) normalized gain (db) 1 10 100 300 v o = 0.2vp-p g = +10 g = +2 g = +5 C 40 C 45 C 50 C 55 C 60 C 65 C 70 C 75 C 80 C 85 C 90 harmonic distortion vs load resistance r l ( ? ) 100 500 400 300 200 harmonic distortion (dbc) v o = 1vp-p f o = 5mhz 3rd-harmonic distortion 2nd-harmonic distortion C 40 C 45 C 50 C 55 C 60 C 65 C 70 C 75 C 80 C 85 C 90 two-tone, 3rd-order intermodulation spurious single-tone load power (dbm) C 16 C 14 C 12 C 10 C 8 C 6 C 4 3rd-order spurious level (dbc) f o = 20mhz f o = 10mhz f o = 5mhz load power at matched 50 ? load C 40 C 45 C 50 C 55 C 60 C 65 C 70 C 75 C 80 C 85 C 90 2nd-harmonic distortion vs frequency frequency (mhz) 10 120 2nd-harmonic distortion (dbc) g = +10 g = +5 g = +2 v o = 1vp-p r l = 100 ? C 40 C 45 C 50 C 55 C 60 C 65 C 70 C 75 C 80 C 85 C 90 3rd-harmonic distortion vs frequency frequency (mhz) 10 120 3rd-harmonic distortion (dbc) g = +10 v o = 1vp-p r l = 100 ? g = +5 g = +2
opa634, opa635 10 sbos097a typical performance curves: v s = +3v (cont.) at t a = 25 c, g = +2, r f = 750 ? , and r l = 150 ? to v s /2, unless otherwise noted (see figure 2). 1000 100 10 1 r s vs capacitive load capacitive load (pf) 1 10 100 1000 r s ( ? ) 2 1 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 C 8 frequency response vs capacitive load frequency (mhz) 1 10 100 300 normalized gain (db) v o = 0.2vp-p r s opa63x v o 1k ? c l +v s /2 c l = 100pf c l = 1000pf c l = 10pf 3.0 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 output swing vs load resistance r l ( ? ) 50 100 1000 maximum output voltage (v) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 minimum output voltage (v) maximum v o minimum v o right scale left scale
opa634, opa635 11 sbos097a applications information wideband voltage feedback operation the opa634 and opa635 are unity-gain stable, very high- speed voltage feedback op amps designed for single supply operation (+3v to +10v). the input stage supports input voltages below ground, and to within 1.2v of the positive supply. the complementary common-emitter output stage provides an output swing to within 30mv of ground and 140mv of the positive supply. they are compensated to provide stable operation with a wide range of resistive loads. the opa635? internal disable circuitry is designed to minimize supply current when disabled. figure 1 shows the ac-coupled, gain of +2 configuration used for the +5v specifications and typical performance curves. for test purposes, the input impedance is set to 50 ? with a resistor to ground. voltage swings reported in the specifications are taken directly at the input and output pins. for the circuit of figure 1, the total effective load on the output at high frequencies is 150 ? || 1500 ? . the disable pin needs to be driven by a low impedance source, such as a cmos inverter. the 1.50k ? resistors at the non-inverting input provide the common-mode bias voltage. their parallel combination equals the dc resistance at the inverting input, (r f ), minimizing the dc offset. single supply adc converter interface the front page shows a dc-coupled, single-supply adc (analog-to-digital converter) driver circuit. many systems are now requiring +3v supply capability of both the adc and its driver. the opa635 provides excellent performance in this demanding application. its large input and output voltage ranges, and low distortion, support converters such as the ads900 shown in this figure. the input level-shifting circuitry was designed so that v in can be between 0v and 0.5v, while delivering an output voltage of 1v to 2v for the ads900. both the opa635 and ads900 have power reduc- tion pins with the same polarity for those systems that need to conserve power. figure 2 shows the dc-coupled, gain of +2 configuration used for the +3v specifications and typical performance curves. for test purposes, the input impedance is set to 50 ? with a resistor to ground. though not strictly a ?ail-to-rail design, these parts come very close, while maintaining excellent performance. they will deliver 2.8vp-p on a single +3v supply with 70mhz bandwidth. the 374 ? and 2.26k ? resistors at the input level-shift v in so that v out is within the allowed output voltage range when v in = 0. see the typical performance curves for information on driving capacitive loads. figure 1. ac-coupled signal?esistive load to supply midpoint. figure 2. dc-coupled signal?esistive load to supply midpoint. opa63x +v s = 5v dis (opa635 only) v out 53.6 ? v in 1.50k ? 1.50k ? r l 150 ? +v s 2 6.8 f + 0.1 f 0.1 f 0.1 f r f 750 ? r g 750 ? opa63x +v s = 3v dis (opa635 only) v out 57.6 ? v in r f 750 ? r g 562 ? 374 ? 2.26k ? r l 150 ? +v s 2 6.8 f + 0.1 f z
opa634, opa635 12 sbos097a dc level shifting figure 3 shows a dc-coupled non-inverting amplifier that level-shifts the input up to accommodate the desired output voltage range. given the desired signal gain (g), and the amount v out needs to be shifted up ( ? v out ) when v in is at the center of its range, the following equations give the resistor values that produce the desired performance. start by setting r 4 between 200 ? and 1.5k ? . ng = g + ? v out /v s r 1 = r 4 /g r 2 = r 4 /(ng ?g) r 3 = r 4 /(ng ?) where: ng = 1 + r 4 /r 3 v out = (g)v in + (ng ?g)v s make sure that v in and v out stay within the specified input and output voltage ranges. non-inverting amplifier with reduced peaking figure 4 shows a non-inverting amplifier that reduces peak- ing at low gains. the resistor r c compensates the opa634 or opa635 to have higher noise gain (ng), which reduces the ac response peaking (typically 5db at g = +1 without r c ) without changing the dc gain. v in needs to be a low impedance source, such as an op amp. the resistor values are low to reduce noise. using both r t and r f helps minimize the impact of parasitic impedances. opa63x +v s v out v in r 3 r 2 r 1 r 4 figure 3. dc level-shifting circuit. opa63x v out v in r g r t r f r c figure 4. compensated non-inverting amplifier. the front page circuit is a good example of this type of application. it was designed to take v in between 0v and 0.5v, and produce v out between 1v and 2v, when using a +3v supply. this means g = 2.00, and ? v out = 1.50v ?g ?0.25v = 1.00v. plugging into the above equations (with r 4 = 750 ? ) gives: ng = 2.33, r 1 = 375 ? , r 2 = 2.25k ? , and r 3 = 563 ? . the resistors were changed to the nearest standard values. the noise gain can be calculated as follows: g r r g rrg r ng g g f g tf c 1 2 1 12 1 1 =+ =+ + = / a unity gain buffer can be designed by selecting r t = r f = 20.0 ? and r c = 40.2 ? (do not use r g ). this gives a noise gain of 2, so its response will be similar to the characteris- tics plots with g = +2. decreasing r c to 20.0 ? will increase the noise gain to 3, which typically gives a flat frequency response, but with less bandwidth. the circuit in figure 1 can be redesigned to have less peaking by increasing the noise gain to 3. this is accom- plished by adding r c = 2.55k ? between the op amps inputs.
opa634, opa635 13 sbos097a design-in tools demonstration boards two pc boards are available to assist in the initial evaluation of circuit performance using the opa634 and opa635 in their three package styles. these are available free as an unpopulated pc board delivered with descriptive documen- tation. the summary information for these boards is shown in table i. bandwidth versus gain: non-inverting operation voltage feedback op amps exhibit decreasing closed-loop bandwidth as the signal gain is increased. in theory, this relationship is described by the gain bandwidth product (gbp) shown in the specifications. ideally, dividing gbp by the non-inverting signal gain (also called the noise gain, or ng) will predict the closed-loop bandwidth. in practice, this only holds true when the phase margin approaches 90 , as it does in high gain configurations. at low gains (increased feedback factors), most amplifiers will exhibit a more com- plex response with lower phase margin. the opa634 and opa635 are compensated to give a slightly peaked response in a non-inverting gain of 2 (figure 1). this results in a typical gain of +2 bandwidth of 150mhz, far exceeding that predicted by dividing the 140mhz gbp by 2. increasing the gain will cause the phase margin to approach 90 and the bandwidth to more closely approach the predicted value of (gbp/ng). at a gain of +10, the 16mhz bandwidth shown in the typical specifications is close to that predicted using the simple formula and the typical gbp. the opa634 and opa635 exhibit minimal bandwidth re- duction going to +3v single supply operation as compared with +5v supply. this is because the internal bias control circuitry retains nearly constant quiescent current as the total supply voltage between the supply pins is changed. inverting amplifier operation since the opa634 and opa635 are general-purpose, wideband voltage- feedback op amps, all of the familiar op amp appli- cation circuits are available to the designer. figure 5 shows a typical inverting configuration where the i/o impedances and signal gain from figure 1 are retained in an inverting circuit configuration. inverting operation is one of the more common requirements and offers several performance benefits. the inverting configuration shows improved slew rate and distor- tion. it also allows the input to be biased at v s /2 without any headroom issues. the output voltage can be independently moved to be within the output voltage range with coupling capacitors, or bias adjustment resistors. board literature part request product package number number opa63xu so-8 dem-opa68xu mkt-351 opa63xn sot23-5 dem-opa6xxn mkt-348 " sot23-6 "" table i. demo board summary information. contact the texas instruments technical applications sup- port line at 1-972-644-5580 to request any of these boards. operating suggestions optimizing resistor values since the opa634 and opa635 are voltage feedback op amps, a wide range of resistor values may be used for the feedback and gain setting resistors. the primary limits on these values are set by dynamic range (noise and distortion) and parasitic capacitance considerations. for a non-inverting unity gain follower application, the feedback connection should be made with a 20 ? resistor, not a direct short (see figure 4 with r g = ). this will isolate the inverting input capacitance from the output pin and improve the frequency response flatness. usually, for g > 1 application, the feed- back resistor value should be between 200 ? and 1.5k ? . below 200 ? , the feedback network will present additional output loading which can degrade the harmonic distortion performance. above 1.5k ? , the typical parasitic capacitance (approximately 0.2pf) across the feedback resistor may cause unintentional band-limiting in the amplifier response. a good rule of thumb is to target the parallel combination of r f and r g (figure 1) to be less than approximately 400 ? . the combined impedance r f || r g interacts with the invert- ing input capacitance, placing an additional pole in the feedback network and thus, a zero in the forward response. assuming a 3pf total parasitic on the inverting node, hold- ing r f || r g <400 ? will keep this pole above 130mhz. by itself, this constraint implies that the feedback resistor r f can increase to several k ? at high gains. this is acceptable as long as the pole formed by r f and any parasitic capaci- tance appearing in parallel is kept out of the frequency range of interest. figure 5. ac-coupled, gain of ? example circuit. opa63x 50 ? r f 750 ? r g 374 ? 2r t 1.5k ? r m 57.6 ? source dis +5v 2r t 1.5k ? r o 50 ? 0.1 f 6.8 f + 0.1 f 0.1 f 50 ? load
opa634, opa635 14 sbos097a in the inverting configuration, three key design consider- ation must be noted. the first is that the gain resistor (r g ) becomes part of the signal channel input impedance. if input impedance matching is desired (which is beneficial when- ever the signal is coupled through a cable, twisted pair, long pc board trace, or other transmission line conductor), r g may be set equal to the required termination value and r f adjusted to give the desired gain. this is the simplest approach and results in optimum bandwidth and noise per- formance. however, at low inverting gains, the resultant feedback resistor value can present a significant load to the amplifier output. for an inverting gain of 2, setting r g to 50 ? for input matching eliminates the need for r m but requires a 100 ? feedback resistor. this has the interesting advantage of the noise gain becoming equal to 2 for a 50 ? source impedance?he same as the non-inverting circuits considered above. however, the amplifier output will now see the 100 ? feedback resistor in parallel with the external load. in general, the feedback resistor should be limited to the 200 ? to 1.5k ? range. in this case, it is preferable to increase both the r f and r g values, as shown in figure 5, and then achieve the input matching impedance with a third resistor (r m ) to ground. the total input impedance becomes the parallel combination of r g and r m . the second major consideration, touched on in the previous paragraph, is that the signal source impedance becomes part of the noise gain equation and hence influences the bandwidth. for the example in figure 5, the r m value combines in parallel with the external 50 ? source imped- ance (at high frequencies), yielding an effective driving impedance of 50 ? || 576 ? = 26.8 ? . this impedance is added in series with r g for calculating the noise gain. the resultant is 2.87 for figure 5, as opposed to only 2 if r m could be eliminated as discussed above. the bandwidth will therefore be lower for the gain of ? circuit of figure 5 (ng = +2.87) than for the gain of +2 circuit of figure 1. the third important consideration in inverting amplifier design is setting the bias current cancellation resistors on the non-inverting input (a parallel combination of r t = 750 ? ). if this resistor is set equal to the total dc resistance looking out of the inverting node, the output dc error, due to the input bias currents, will be reduced to (input offset current) times r f . with the dc blocking capacitor in series with r g , the dc source impedance looking out of the inverting mode is simply r f = 750 ? for figure 5. to reduce the additional high-frequency noise introduced by this resistor, and power- supply feedthrough, r t is bypassed with a capacitor. as long as r t < 400 ? , its noise contribution will be minimal. as a minimum, the opa634 and opa635 require an r t value of 50 ? to damp out parasitic-induced peaking? direct short to ground on the non-inverting input runs the risk of a very high-frequency instability in the input stage. output current and voltage the opa634 and opa635 provide outstanding output volt- age capability. under no-load conditions at +25 c, the output voltage typically swings closer than 140mv to either supply rail; the guaranteed over temperature swing is within 300mv of either rail (v s = +5v). the minimum specified output voltage and current specifi- cations over temperature are set by worst-case simulations at the cold temperature extreme. only at cold start-up will the output current and voltage decrease to the numbers shown in the guaranteed tables. as the output transistors deliver power, their junction temperatures will increase, decreasing their v be ? (increasing the available output voltage swing) and increasing their current gains (increasing the available out- put current). in steady-state operation, the available output voltage and current will always be greater than that shown in the over-temperature specifications, since the output stage junction temperatures will be higher than the minimum specified operating ambient. to maintain maximum output stage linearity, no output short-circuit protection is provided. this will not normally be a problem, since most applications include a series matching resistor at the output that will limit the internal power dissipation if the output side of this resistor is shorted to ground. however, shorting the output pin directly to the adjacent positive power-supply pin (8-pin packages) will, in most cases, destroy the amplifier. if additional short-circuit protection is required, consider a small series resistor in the power-supply leads. this will, under heavy output loads, reduce the available output voltage swing. driving capacitive loads one of the most demanding and yet very common load conditions for an op amp is capacitive loading. often, the capacitive load is the input of an adc?ncluding additional external capacitance which may be recommended to im- prove adc linearity. a high-speed, high open-loop gain amplifier like the opa634 and opa635 can be very suscep- tible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. when the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the sim- plest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. the typical performance curves show the recommended r s versus capacitive load and the resulting frequency re- sponse at the load. parasitic capacitive loads greater than 2pf can begin to degrade the performance of the opa634 and opa635. long pc board traces, unmatched cables, and connections to multiple devices can easily exceed this value. always consider this effect carefully, and add the recom- mended series resistor as close as possible to the output pin (see board layout guidelines section).
opa634, opa635 15 sbos097a the criterion for setting this r s resistor is a maximum bandwidth, flat frequency response at the load. for a gain of +2, the frequency response at the output pin is already slightly peaked without the capacitive load, requiring rela- tively high values of r s to flatten the response at the load. increasing the noise gain will also reduce the peaking (see figure 4). distortion performance the opa634 and opa635 provide good distortion perfor- mance into a 150 ? load. relative to alternative solutions, it provides exceptional performance into lighter loads and/or operating on a single +3v supply. generally, until the fundamental signal reaches very high frequency or power levels, the 2nd harmonic will dominate the distortion with a negligible 3rd harmonic component. focusing then on the 2nd harmonic, increasing the load impedance improves distortion directly. remember that the total load includes the feedback network; in the non-inverting configuration (figure 1) this is sum of r f + r g , while in the inverting configuration, only r f needs to be included in parallel with the actual load. noise performance high slew rate, unity gain stable, voltage-feedback op amps usually achieve their slew rate at the expense of a higher input noise voltage. the 5.6nv/ hz input voltage noise for the opa634 and opa635 is, however, much lower than comparable amplifiers. the input-referred voltage noise, and the two input-referred current noise terms (2.8pa/ hz), combine to give low output noise under a wide variety of operating conditions. figure 6 shows the op amp noise analysis model with all the noise terms included. in this model, all noise terms are taken to be noise voltage or current density terms in either nv/ hz or pa/ hz. the total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. equation 1 shows the general form for the output noise voltage using the terms shown in figure 6: (1) e o = e ni 2 + i bn r s () 2 +4 ktr s () ng 2 + i bi r f () 2 +4 ktr f ng dividing this expression by the noise gain (ng = (1 + r f /r g )) will give the equivalent input-referred spot noise voltage at the non-inverting input, as shown in equation 2: (2) e n = e ni 2 + i bn r s () 2 +4 ktr s + i bi r f ng ? ? ? ? 2 + 4 ktr f ng evaluating these two equations for the circuit and compo- nent values shown in figure 1 will give a total output spot noise voltage of 12.5nv/ hz and a total equivalent input spot noise voltage of 6.3nv/ hz. this is including the noise added by the resistors. this total input-referred spot noise voltage is not much higher than the 5.6nv/ hz specification for the op amp voltage noise alone. this will be the case as long as the impedances appearing at each op amp input are limited to the previously recommend maximum value of 400 ? , and the input attenuation is low. dc accuracy and offset control the balanced input stage of a wideband voltage-feedback op amp allows good output dc accuracy in a wide variety of applications. the power-supply current trim for the opa634 and opa635 gives even tighter control than comparable products. although the high-speed input stage does require relatively high input bias current (typically 25 a out of each input terminal), the close matching between them may be used to reduce the output dc error caused by this current. this is done by matching the dc source resistances appear- ing at the two inputs. evaluating the configuration of figure 1 (which has matched dc input resistances), using worst-case +25 c input offset voltage and current specifica- tions, gives a worst-case output offset voltage equal to: (ng = non-inverting signal gain at dc) (ng ?v os(max) ) (r f ?i os(max) ) = (1 ?7.0mv) (750 ? ?2.25 a) = 8.7mv a fine scale output offset null, or dc operating point adjustment, is often required. numerous techniques are available for introducing dc offset control into an op amp circuit. most of these techniques are based on adding a dc current through the feedback resistor. in selecting an offset trim method, one key consideration is the impact on the desired signal path frequency response. if the signal path is figure 6. noise analysis model. 4kt r g r g r f r s opa63x i bi e o i bn 4kt = 1.6e C 20j at 290 k e rs e ni 4ktr s 4ktr f
opa634, opa635 16 sbos097a intended to be non-inverting, the offset control is best applied as an inverting summing signal to avoid interaction with the signal source. if the signal path is intended to be inverting, applying the offset control to the non-inverting input may be considered. bring the dc offsetting current into the inverting input node through resistor values that are much larger than the signal path resistors. this will insure that the adjustment circuit has minimal effect on the loop gain and hence the frequency response. disable operation the opa635 provides a disable feature that may be used either to reduce system power or to implement a simple channel multiplexing operation. to disable, the control pin must be asserted high. figure 7 shows a simplified internal circuit for the disable control feature. output stage (p dl ) to deliver load power. quiescent power is simply the specified no-load supply current times the total supply voltage across the part. p dl will depend on the required output signal and load but would, for resistive load connected to mid-supply (v s /2), be at a maximum when the output is fixed at a voltage equal to v s /4 or 3v s /4. under this condition, p dl = v s 2 /(16 ?r l ), where r l includes feedback network loading. note that it is the power in the output stage, and not into the load, that determines internal power dissipation. as a worst-case example, compute the maximum t j using an opa635 (sot23-6 package) in the circuit of figure 1 operating at the maximum specified ambient temperature of +85 c and driving a 150 ? load at mid-supply. p d = 10v ?13.5ma + 5 2 /(16 ?(150 ? || 1500 ? )) = 144mw maximum t j = +85 c + (0.14w ?150 c/w) = 107 c. although this is still well below the specified maximum junction temperature, system reliability considerations may require lower guaranteed junction temperatures. the highest possible internal dissipation will occur if the load requires current to be forced into the output at high output voltages or sourced from the output at low output voltages. this puts a high current through a large internal voltage drop in the output transistors. board layout guidelines achieving optimum performance with a high frequency amplifier like the opa634 and opa635 requires careful attention to board layout parasitics and external component types. recommendations that will optimize performance include: a) minimize parasitic capacitance to any ac ground for all of the signal i/o pins. parasitic capacitance on the output and inverting input pins can cause instability: on the non- inverting input, it can react with the source impedance to cause unintentional bandlimiting. to reduce unwanted ca- pacitance, a window around the signal i/o pins should be opened in all of the ground and power planes around those pins. otherwise, ground and power planes should be unbro- ken elsewhere on the board. b) minimize the distance (<0.25") from the power-supply pins to high frequency 0.1 f decoupling capacitors. at the device pins, the ground and power plane layout should not be in close proximity to the signal i/o pins. avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. each power-supply connec- tion should always be decoupled with one of these capacitors. an optional supply decoupling capacitor (0.1 f) across the two power supplies (for bipolar operation) will improve 2nd- harmonic distortion performance. larger (2.2 f to 6.8 f) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. these may be placed somewhat farther from the device and may be shared among several devices in the same area of the pc board. 50k ? i s control v dis +v s q1 figure 7. simplified disable control circuit (opa635). in normal operation, base current to q1 is provided through the 50k ? resistor. one key parameter in disable operation is the output glitch when switching in and out of the disabled mode. the transition edge rate (dv/dt) of the dis control line will influence this glitch. adding a simple rc filter into the dis pin from a higher speed logic line will reduce the glitch. if extremely fast transition logic is used, a 1k ? series resistor will provide adequate bandlimiting using just the parasitic input capacitance on the dis pin while still ensuring ad- equate logic level swing. thermal analysis maximum desired junction temperature will set the maxi- mum allowed internal power dissipation, as described be- low. in no case should the maximum junction temperature be allowed to exceed 175 c. operating junction temperature (t j ) is given by t a + p d ja . the total internal power dissipation (p d ) is the sum of quiescent power (p dq ) and additional power dissipated in the
opa634, opa635 17 sbos097a c) careful selection and placement of external compo- nents will preserve the high-frequency performance. resistors should be a very low reactance type. surface- mount resistors work best and allow a tighter overall layout. metal film or carbon composition axially-leaded resistors can also provide good high-frequency performance. again, keep their leads and pc board traces as short as possible. never use wirewound type resistors in a high-frequency application. since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. other network components, such as non-inverting input termination resistors, should also be placed close to the package. where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. good axial metal film or surface- mount resistors have approximately 0.2pf in shunt with the resistor. for resistor values >1.5k ? , this parasitic capaci- tance can add a pole and/or zero below 500mhz that can effect circuit operation. keep resistor values as low as possible consistent with load driving considerations. the 750 ? feedback used in the typical performance specifica- tions is a good starting point for design d) connections to other wideband devices on the board may be made with short direct traces or through on-board transmission lines. for short connections, consider the trace and the input to the next device as a lumped capacitive load. relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. estimate the total capacitive load and set r s from the typical performance curve ?ecommended r s vs capacitive load? low parasitic capacitive loads (< 5pf) may not need an r s since the opa634 and opa635 are nominally com- pensated to operate with a 2pf parasitic load. higher para- sitic capacitive loads without an r s are allowed as the signal gain increases (increasing the unloaded phase margin) if a long trace is required, and the 6db signal loss intrinsic to a doubly-terminated transmission line is acceptable, imple- ment a matched impedance transmission line using microstrip or stripline techniques (consult an ecl design handbook for microstrip and stripline layout techniques). a 50 ? environ- ment is normally not necessary on board, and in fact, a higher impedance environment will improve distortion as shown in the distortion versus load plots. with a character- istic board trace impedance defined (based on board material and trace dimensions), a matching series resistor into the trace from the output of the opa634 and opa635 is used as well as a terminating shunt resistor at the input of the destination device. remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device; this total effective impedance should be set to match the trace impedance. if the 6db attenuation of a doubly termi- nated transmission line is unacceptable, a long trace can be series-terminated at the source end only. treat the trace as a capacitive load in this case and set the series resistor value as shown in the typical performance curve ?ecommended r s vs capacitive load? this will not preserve signal integ- rity as well as a doubly-terminated line. if the input imped- ance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) socketing a high-speed part is not recommended. the additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. best results are obtained by soldering the opa634 and opa635 onto the board. if socketing for the dip package is desired, high frequency flush mount pins (e.g., mckenzie technology #710c) can give good results. input and esd protection the opa634 and opa635 are is built using a very high- speed complementary bipolar process. the internal junction breakdown voltages are relatively low for these very small geometry devices. these breakdowns are reflected in the absolute maximum ratings table. all device pins are pro- tected with internal esd protection diodes to the power supplies, as shown in figure 8. external pin +v cc C v cc internal circuitry figure 8. internal esd protection. these diodes provide moderate protection to input overdrive voltages above the supplies as well. the protection diodes can typically support 30ma continuous current. where higher currents are possible (e.g., in systems with 15v supply parts driving into the opa634 and opa635), current-limit- ing series resistors should be added into the two inputs. keep these resistor values as low as possible, since high values degrade both noise performance and frequency response.
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