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em78p458/459 otp rom em78p458/459 8-bit micro-controller version 1.4
em78p458/459 otp rom specification revision history version content 1 . 0 i n i t i a l v e r s i o n 1.1 modify erc frequency 03/06/2003 1.2 add ad & op spec 05/07/2003 1.3 change power on reset content 07/01/2003 1.4 add the device characterist ic at section 6.5 06/25/2004 application note an-001 a/d pre-amplifier an-002 calibration offset on a/d an-003 example of microcomputer digital thermometer an-004 tips on how to apply em78p458 an-005 tips on how to apply a/d converter an-006 ad & r4 an-007 enhancing noise immunity this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 2
em78p458/459 otp rom 1. general description em78p45 8 and em78p45 9 are 8-bit microp ro ce ssor s desi gne d and develo ped with lo w-po we r and high -spee d cmos technol ogy. it is eq ui pped with a 4 k *13-bit elect r ical on e tim e pro g ra mma ble rea d only memory (otp-rom). with its otp-rom feature, it is able to offer a conv eni ent way of de veloping an d verifying use r ? s prog ram s . moreover, user can take advantage of emc wri ter to easily program his development code. this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 3
em78p458/459 otp rom 2. features ? operating voltage range: 2.3v~5.5v ? operating temperature range: 0
em78p458/459 otp rom * 20 pin dip 300mil : em78p458ap * 20 pin sop 300mil : em78p458am * 24 pin skinny dip 300mil : em78p459ak * 24 pin sop 300mil : EM78P459AM this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 5
em78p458/459 otp rom 3. pin assignment p 56/ci n+ p 57/co p 60/adc1 p 61/adc2 vs s p 62/adc3 p 63/adc4 p 64/adc5 p 65/adc6 p 66/adc7 p 55/ cin- p 54/tcc os ci osc o vd d p 53/vref p 52/p w m 2 p 51/p w m 1 p5 0/ i n t p 67/adc8 em 78p458 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 p 56/ cin+ p57 / c o p 6 0/ adc1 p 6 1/ adc2 vss p 6 2/ adc3 p 6 3/ adc4 p 6 4/ adc5 p 6 5/ adc6 p 6 6/ adc7 en tc c vss p 55/cin- p 5 4/tcc osc i os co vdd p 5 3/vre f p5 2 / pw m2 p5 1 / pw m1 p5 0 / i n t p 6 7/a dc8 re s e t vdd em 78p459 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 fig. 1 pin assignment t a ble 1 em78p458 pin description symbol pin no. type function v d d 1 6 - p o w e r s u p p l y . o s c i 1 8 i * xtal type: crystal input terminal or external clock input pin. * rc type: rc oscillator input pin. o s c o 1 7 o *xtal type: output terminal for crysta l oscillator or external clock input pin. *rc type: clock output with a period of one instruction cycle time, the prescaler is determined by the cont register. * external clock signal input. p 5 0 1 2 i * general-purpose input only. * default value while power-on reset. p51 ~ p57 13~15 19, 20, 1, 2 i/o * general-purpose i/o pin. * default value while power-on reset. p60 ~ p67 3, 4, 6~11 i/o * general-purpose i/o pin. * default value while power-on reset. int 12 i * external interrupt pin triggered by falling edge. adc1~adc8 3, 4, 6 ~ 11 i * analog to digital converter. * defined by ad-cmpcon (ioca0)<2:4>. pwm1, pwm2 13, 14 o * pulse width modulation outputs. * defined by pwmcon (ioc51)<6, 7> v r e f 1 5 i * external reference voltage for adc * defined by ad-cmpcon (ioca0)<7>. this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 6
em78p458/459 otp rom cin-, cin+, co 20, 1,2 i o * ?-? -> the input pin of vin- of the comparator. * ?+?-> the input pin of vin+ of the comparator. * pin co is the output of the comparator. * defined by ad-cmpcon (ioca0) <5, 6> t c c 1 9 i * real time cl ock/co unte r with schmitt trigg e r inp u t pin; it must be tied to vdd or vss if it is not in us e. v s s 5 - g r o u n d . t a ble 2 em78p459 pin description symbol pin no. type function vdd 19, 18 - power supply. o s c i 2 2 i * xtal type: crystal input terminal or external clock input pin. * rc type: rc oscillator input pin. o s c o 2 1 o * xtal type: output terminal for crystal oscillator or external clock input pin. * rc type: clock output with a period of one instruction cycle time, the prescaler is determined by the cont register. * external clock signal input. p 5 0 1 4 i * general-purpose input only. * default value while power-on reset. p51 ~ p57 15~17 23, 24 1, 2 i/o * general-purpose i/o pin. * default value while power-on reset. p60 ~ p67 3, 4, 8~13 i/o * general-purpose i/o pin. * default value while power-on reset. int 14 i * external interrupt pin triggered by falling edge. adc1~adc8 3, 4, 8~13 i * analog to digital converter. * defined by ad-cmpcon (ioca0)<2:4>. pwm1, pwm2 15, 16 o * pulse width modulation outputs. * defined by pwmcon (ioc51)<6, 7> v r e f 1 7 i * external reference voltage for adc * defined by ad-cmpcon (ioca0)<7>. cin-, cin+, co 24, 1, 2 i * ?-? -> the vin- input pins of the comparators. * ?+? -> the vin+ input pins of the comparators. * pin co is the output of the comparator. * defined by ad-cmpcon (ioca0) <5, 6> / r e s e t 2 0 i * if it remains at logic low, the device will be reset. * wake up from sleep mode when pins status changes. * voltage on /reset/vpp must not be over vdd during normal mode. * pull-high is on if /reset is as s e rted. t c c 2 3 i * real time clock/counter with schmitt trigger input pin; it must be tied to vdd or vss if it is not in us e. entcc 5 i 1: enable tcc; 0: disable tcc. v s s 6 , 7 - g r o u n d . this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 7
em78p458/459 otp rom 4. function description data & control bus ioc5 r5 p 5 0 p 5 1 p 5 2 p 5 3 p 5 4 p 5 5 p 5 6 p 5 7 comparators 8 adc 2 pwms ioc6 r6 p 6 0 p 6 1 p 6 2 p 6 3 p 6 4 p 6 5 p 6 6 p 6 7 acc r3 stack 0 stack 1 stack 2 stack 3 stack 4 p c rom instruction register instruction decoder alu interrupt control / int r4 ram wdt timer prescaler oscillator/ timming control wdt time-out r1(tcc) sleep & wake up control entcc stack 5 stack 6 stack 7 fig. 2 the functional block diagram of em78p458/459 4.1 operational registers 1. r0 (indirect addressing register) r0 is not a ph ysically imple m ented regi ster. its majo r functio n is to perform as an i ndirect add re ssi ng pointe r . any instructio n u s i ng r0 a s a p o inter, a c tuall y accesse s d a ta pointe d b y the ram select register (r4). 2. r1 (time clock /counter) ? increased by an external signal edge through the t cc pin, or by the inst ruction cycle clock. ? the signals to increase the counter are deci ded by bit 4 and bit 5 of the cont register. ? writable and readable as any other registers. 3. r2 (program counter) & stack ? r2 and hardware stacks are 12-bit wide. the structure is depicted in fig. 4. ? generate s 4k
em78p458/459 otp rom ? "jmp" instru ction allo ws the dire ct load ing of t he lower 10 prog ra m counte r bits. thus, "jm p " allows pc to jump to any location within a page. ? "call" instruction l oad s the lo wer 10 b i ts of the pc, and the n pc+1 is pu sh ed in to the stack. thu s , the subroutine entry address can be located anywhere within a page. ? "ret" ("re tl k", "reti") instructio n lo ads th e p r og ram counte r wi th the co ntent s of the top of stack. ? "add r2, a" allows a rela tive address to be added to the current pc, and the ninth and tenth bits of the pc are cleared. ? "mov r2, a" allows to lo ad an a ddress from the "a " registe r to the lower 8 bits of the pc, and the ninth and tenth bits of the pc are cleared. ? any ins t ruc t ion that is written to r2 (e.g. "add r2, a " , "mov r2, a", "bc r2, 6", ????? ) will cause the ninth bit and the tenth bit (a8~a9 ) of the pc to be cleared. thu s , the computed ju mp is limited to th e first 256 locations of a page. ? in the case of em78p458 /459, the most two sig n ificant bits (a11 and a10 ) will be load ed wit h the conte n t of ps1 and ps0 in the statu s reg i ster (r 3) upo n the exe c uti on of a " j mp" , "call", or a n y other instructions set which write to r2. ? a ll inst ruct io ns a r e si ngle inst r u ct io n cy cle (f clk/ 2 o r fclk/4 ) except for the inst ru ctions which write to r2, need one more instruction cycle. a9 ~ a0 stac k level 0 stac k level 2 stac k level 1 stac k level 3 stac k level 4 000h fffh 008h in te r r u p t ve cto r u s e r me mo r y s pac e r e se t ve cto r a11, a10 on-chip program memory pc pa ge 0 pa ge 1 pa ge 2 pa ge 3 00 01 10 11 stac k level 5 stac k level 6 stac k level 7 0 0 0 3 f f 4 0 0 7 f f 8 0 0 b f f c 0 0 f f f fig. 3 program counter organization this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 9
em78p458/459 otp rom address p a ge registers ioc p a ge registers ioc p a ge registers 00 r0 ( i a r ) r e s e r v e reserv e 01 r1 ( t c c ) r e s e r v e reserv e 02 r2 ( p c ) r e s e r v e reserv e 03 r3 (s t a t u s ) r e s e r v e reserv e 04 r4 r s r ) r e s e r v e reserv e 05 r5 (port5) ioc50 (i/o port control register) ioc51 (pwmcon) 06 r6 (port6) ioc60 (i/o port control register) ioc61 (dt1l) 07 r7 general registers reserve ioc71 (dt1h) 08 r8 general registers reserve ioc81 (prd1) 09 r9 (adcon) ioc90 (gcon) ioc91 (dt2l ) 0a ra (adda t a ) ioca0 (ad-cmpcon) i o c a 1 (dt2h) 0b rb general registers iocb0 (pull-down control register) iocb1 (prd2) 0c rc general registers (only two bit s ) iocc0 (open-d r ain control regi ster ) iocc1 (dl1l) 0d rd general registers iocd0 (pull-high control register) iocd1 (dl1h) 0e re general registers (only two bit s ) ioce0 (wdt control register) ioce1 (dl2l) 0f rf (interrupt st atus) iocf0 (interrupt mask register) iocf1 (dl2h) 10 ?j 1f general registers 20 ?j 3f bank 0 bank 1 fig. 4 dat a memory configuration this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 10
em78p458/459 otp rom 4. r3 (status register) 7 6 5 4 3 2 1 0 c m p o u t p s 1 p s 0 t p z d c c ? bit 7 (cmpout) the result of the comparator output. ? bit 6 (ps1) ~ 5 (ps0 ) pa ge sele ct bits. ps0~ps1 are used to sele ct a prog ram memo ry page . when executin g a " j mp", "call " , or othe r in structio ns whi c h ca use the p r og ram co unt er to b e cha n ged (e.g. mov r2 , a), ps0~ps1 are lo ade d into the 11th a nd 12th bit s o f the prog ram counte r whe r e it sele cts one o f the availabl e pro g ram m e mory p age s. note that ret (ret l, re ti) instru ction doe s not cha nge th e ps0~ps1 bits. that is, th e return w ill always b e to th e page from the pla c e wh ere the subroutine was called, regardless of t he current setting of ps0~ps1 bits. ps1 ps0 program memory page [address] 0 0 page 0 [000-3ff] 0 1 page 1 [400-7ff] 1 0 page 2 [800-bff] 1 1 page 3 [c00-fff] ? bit 4 (t) ti me-o ut bit. set to 1 by the "slep" and "wdtc" com m and s, or during powe r on and re set to 0 by wdt time-out. ? bit 3 (p) powe r-d own bit. set to 1 during power-on or by a "wdtc" comma nd and re set to 0 by a "slep" command. ? bit 2 (z) zero flag. set to "1" if the result of an arithmetic or logic operation is zero. ? bit 1 (dc) auxiliary carry flag ? bit 0 (c) carry flag 5. r4 (ram select register) ? bit 7 is a general-purpose read/write bit. ? bit 6 is used to select bank 0 or bank 1. ? bits 0~5 are used to select registers ( address: 00~3f) in the indirect address mode. 6. r5 ~ r6 (port 5 ~ port 6) ? r5 and r6 are i/o registers. 7. r7 ~ r8 ? all of these are 8-bit general-purpose registers. 8. r9 (adcon: analog to digital control) 7 6 5 4 3 2 1 0 - - i o c s a d r u n a d p d a d i s 2 a d i s 1 a d i s 0 ? bit 7:bit 6 unemployed, read as ?0?; ? bit 5(iocs): select the segment of io control register. this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 11
em78p458/459 otp rom 1 = segment 1 ( ioc51~iocf1 ) selected; 0 = segment 0 ( ioc50~iocf0 ) selected; ? bit 4 (adrun) : adc starts to run. 1 = an a/d conversion is started. this bit can be set by software; 0 = reset on completion of the conversion. this bit can not be reset though software; ? bit 3 (adpd) : adc power-down mode. 1 = adc is operating; 0 = switch off the resistor reference to save power even while the cpu is operating. ? bit2:bit0 (adis2:adis0) : analog input select. 000 = an0; 001 = an1; 010 = an2; 011 = an3; 100 = an4; 101 = an5; 110 = an6; 111 = an7; they can only be changed when the adif bit and the adrun bit are both low. 9. ra (addata: the converted value of adc) whe n the a/d conversio n is complete, t he re sult i s lo aded i n to the addata. th e start//end bit is cleared, and the adif is set. 10. rb an 8-bit general-purpose register. 11. rc a 2-bit, bit 0and bit 1 register. 12. rd an 8-bit general-purpose register. 13. re a 2-bit, bit 0 and bit 1 register. 14. rf (interrupt status register) this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 12
em78p458/459 otp rom 7 6 5 4 3 2 1 0 - c m p i f pwm2if pwm1if a d i f e x i f i c i f t c i f ?1? means interrupt request, and ?0? means no interrupt occurs. ? bit 7 unemployed, read as ?0?; ? bit 6 (c mpif) hig h -com p a re d interrupt flag. set whe n a ch ang e o c cu rs in th e out put of com p a r ator, res e t by s o ftware. ? bit 5 (pw m 2if) pwm 2 (pulse widt h mod u lation ) interru p t flag. set whe n a sel e cte d p e rio d is reached, reset by software. ? bit 4 (pw m 1if) pwm 1 (pulse widt h mod u lation ) interru p t flag. set whe n a sel e cte d p e rio d is reached, reset by software. ? bit 3 (a dif ) interrupt fla g for a nalo g to digital conv er sion. set when a d conv ersion i s com p leted, res e t by s o ftware. ? bit 2 (exif) external interrupt flag. set by falli ng edge on /int pin, reset by software. ? bit 1 (icif) port 6 input status chan ge interrupt flag. set when port 6 input chan ge s, re set b y software. ? bit 0 (tcif) tcc overflow interrupt flag. set w hen tcc overflows, reset by software. ? rf can be cleared by instruction but cannot be set. ? iocf0 is the interrupt mask register. ? note that to read rf will result to "logic and" of rf and iocf0. 15. r10 ~ r3f ? all of these are 8-bit general-purpose registers. 4.2 special purpose registers 1. a (accumulator) ? internal data transfer, or instruction operand holding ? it can not be addressed. 2. cont (control register) 7 6 5 4 3 2 1 0 i n t e i n t t s t e p a b p s r 2 p s r 1 p s r 0 ? bit 7 (inte) int signal edge 0: interrupt occurs at the rising edge on the int pin 1: interrupt occurs at the falling edge on the int pin ? bit 6 (int) interrupt enable flag 0: masked by disi or hardware interrupt 1: enabled by the eni/reti instructions this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 13
em78p458/459 otp rom ? bit 5 (ts) tcc signal source 0: int e rnal inst ruct ion cy cle clock. i f p54 is used as i/o pin, ts must be 0. 1: transition on the tcc pin ? bit 4 (te) tcc signal edge 0: increment if the transition from lo w to high takes place on the tcc pin; 1: increment if the transition from hi gh to low takes place on the tcc pin. ? bit 3 (pab) prescaler assignment bit. 0: tcc; 1: wdt. ? bit 2 (psr2) ~ bit 0 (psr0) tcc/wdt prescaler bits. psr2 psr1 psr0 tcc rate wdt rate 0 0 0 1 : 2 1 : 1 0 0 1 1 : 4 1 : 2 0 1 0 1 : 8 1 : 4 0 1 1 1 : 1 6 1 : 8 1 0 0 1 : 3 2 1 : 1 6 1 0 1 1 : 6 4 1 : 3 2 1 1 0 1 : 1 2 8 1 : 6 4 1 1 1 1 : 2 5 6 1 : 1 2 8 ? cont register is both readable and writable. 3. ioc50 ~ ioc60 (i/o port control register) ? "1" puts the relative i/o pin into high impedance, while "0" defines the relative i/o pin as output. ? ioc50 and ioc60 registers are both readable and writable. 4. ioc90 (gcon: i/o configuration & control of adc ) 7 6 5 4 3 2 1 0 o p 2 e o p 1 e g 2 2 g 2 1 g 2 0 g 1 2 g 1 1 g 1 0 ? bit 7 ( op 2 e ) enabl e the gain amplifier whi c h input is c onne cted to p64 and output is conn ected to the 8-1 analog switch. 0 = op2 is off ( default value ), and by passes the input signal to the adc; 1 = op2 is on. ? bit 6 ( op 1 e ) enable th e gain amplifi e r who s e i npu t is co nn ecte d to p60 an d o u tput is co nne cted to the 8-1 analog switch. 0 = op1 is off (default value), and by passes the input signal to the adc; 1 = op1 is on. ? bit 5:bit 3 (g22 and g20) : select the gain of op2. 000 = is x 1 (default value); this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 14
em78p458/459 otp rom 001 = is x 2; 010 = is x 4; 011 = is x 8; 100 = is x 16; 101 = is x 32; legend: is = the input signal ? bit 2:bit 0 (g12 and g10 ) : select the gain of op1. 000 = is x 1 (default value); 001 = is x 2; 010 = is x 4; 011 = is x 8; 100 = is x 16; 101 = is x 32; legend: s = the input signal 5. ioca0 ( ad-cmpcon ): 7 6 5 4 3 2 1 0 v r e f s c e c o e i m s 2 i m s 1 i m s 0 c k r 1 c k r 0 ? bit 7 : the input source of the vref of the adc. 0 = t he vref of the adc is con n e c ted to vdd (d efault value), a nd th e p53/vref pin carrie s o u t the function of p53; 1 = the vref of the adc is connected to p53/vref. ? bit 6 (ce): comparator enable bit 0 = comparator is off (default value); 1 = comparator is on. ? bit 5 ( coe ): set p57 as the output of the comparator 0 = the comparator acts as an op if ce=1. 1 = act as a comparator if ce=1. ? bit4:bit2 (ims2:ims0) : input mode s e lect. adc co nfiguration de finition bi t. the followi ng ta ble de scrib e s how to d e fine the characteristic of each pin of r6. table 3 description of ad configuration control bits ims2:ims0 p60 p61 p62 p63 p64 p65 p66 p67 0 0 0 a d d d d d d d 0 0 1 a a d d d d d d 0 1 0 a a a d d d d d this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 15
em78p458/459 otp rom 0 1 1 a a a a d d d d 1 0 0 a a a a a d d d 1 0 1 a a a a a a d d 1 1 0 a a a a a a a d 1 1 1 a a a a a a a a ? bit 1: bit 0 (ckr1: ckr0): the prescaler of oscillator clock rate of adc 00 = 1: 4 (default value); 01 = 1: 16; 10 = 1: 64; 11 = the oscillator clock source of adc is from wdt ring oscillator frequency. ( frequency=256/18ms ? 14.2khz) 6. iocb0 (pull-dow n control register) 7 6 5 4 3 2 1 0 / p d 7 / p d 6 / p d 5 / p d 4 / p d 3 / p d 2 / p d 1 / p d 0 ? bit 7 (/pd7) control bit is used to enable the pull-down of the p67 pin. 0: enable internal pull-down; 1: disable internal pull-down. ? bit 6 (/pd6) control bit is used to enable the pull-down of the p66 pin. ? bit 5 (/pd5) control bit is used to enable the pull-down of the p65 pin. ? bit 4 (/pd4) control bit is used to enable the pull-down of the p64 pin. ? bit 3 (/pd3) control bit is used to enable the pull-down of the p63 pin. ? bit 2 (/pd2) control bit is used to enable the pull-down of the p62 pin. ? bit 1 (/pd1) control bit is used to enable the pull-down of the p61 pin. ? bit 0 (/pd0) control bit is used to enable the pull-down of the p60 pin. ? iocb0 register is both readable and writable. 7. iocc0 (open-drain control register) 7 6 5 4 3 2 1 0 / o d 7 / o d 6 / o d 5 / o d 4 / o d 3 / o d 2 / o d 1 / o d 0 ? bit 7 (od7) control bit used to enable the open-drain of the p57 pin. 0: enable open-drain output 1: disable open-drain output ? bit 6 (od6) control bit is used to enable the open-drain of the p54 pin. ? bit 5 (od5) control bit is used to enable the open-drain of the p52 pin. ? bit 4 (od4) control bit is used to enable the open-drain of the p51 pin. ? bit 3 (od3) control bit is used to enable the open-drain of the p67 pin. ? bit 2 (od2) control bit is used to enable the open-drain of the p66 pin. this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 16
em78p458/459 otp rom ? bit 1 (od1) control bit is used to enable the open-drain of the p65 pin. ? bit 0 (od0) control bit is used to enable the open-drain of the p64 pin. ? iocc0 register is both readable and writable. 8. iocd0 (pull-high control register) 7 6 5 4 3 2 1 0 / p h 7 / p h 6 / p h 5 - / p h 3 / p h 2 / p h 1 / p h 0 ? bit 7 (/ph7) control bit is used to enable the pull-high of the p56 pin. 0: enable internal pull-high; 1: disable internal pull-high. ? bit 6 (/ph6) control bit is used to enable the pull-high of the p55 pin. ? bit 5 (/ph5) control bit is used to enable the pull-high of the p53 pin. ? bit 4 not used. ? bit 3 (/ph3) control bit is used to enable the pull-high of the p63 pin. ? bit 2 (/ph2) control bit is used to enable the pull-high of the p62 pin. ? bit 1 (/ph1) control bit is used to enable the pull-high of the p61 pin. ? bit 0 (/ph0) control bit is used to enable the pull-high of the p60 pin. ? iocd0 register is both readable and writable. 9. ioce0 (wdt control register) 7 6 5 4 3 2 1 0 w d t e e i s - - - - - - ? bit 7 (wdte) control bit is used to enable watchdog timer. 0: disable wdt; 1: enable wdt. wdte is both readable and writable ? bit 6 (eis) control bit is used to define the function of the p50 (/int) pin. 0: p50, input pin only; 1: /int, ex ternal interrupt pin. in this c a se, the i / o con t rol bit of p50 (bit 0 of ioc50) mu st be set to "1". whe n eis is "0", the path of /int is masked. when ei s is "1", the status of /int pin can also be read by way of reading port 5 (r5). refer to fig. 7. eis is both readable and writable. ? bits 5~0 not used. this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 17
em78p458/459 otp rom 10. iocf0 (interrupt mask register) 7 6 5 4 3 2 1 0 - c m p i e pwm2ie pwm1ie ad i e e x i e i c i e t c i e ? bit 7 : unimplemented, read as ?0?. individual interrupt is enabled by setting its a ssociated control bit in the iocf0 to "1". global inte rru p t is enabl ed by the eni instructio n and is disabl ed by the disi inst ru ction. refe r to fig. 11. ? bit 6 (cmpie) cmpif interrupt enable bit. 0: disable cmpif interrupt 1: enable cmpif interrupt ? bit 5 (pwm2ie) pwm2if interrupt enable bit. 0: disable pwm2 interrupt 1: enable pwm2 interrupt ? bit 4 (pwm1ie) pwm1if interrupt enable bit. 0: disable pwm1 interrupt 1: enable pwm1 interrupt ? bit 3 (adie) adif interrupt enable bit. 0: disable adif interrupt 1: enable adif interrupt ? bit 2 (exie) exif interrupt enable bit. 0: disable exif interrupt 1: enable exif interrupt ? bit 1 (icie) icif interrupt enable bit. 0: disable icif interrupt 1: enable icif interrupt ? bit 0 (tcie) tcif interrupt enable bit. 0: disable tcif interrupt 1: enable tcif interrupt iocf0 register is both readable and writable. 11. ioc51 ( pwmcon ): 7 6 5 4 3 2 1 0 p w m 2 e p w m 1 e t 2 e n t 1 e n t 2 p 1 t 2 p 0 t 1 p 1 t 1 p 0 ? bit 7 (pwm2e): pwm2 enable bit 0 = pwm2 is off (default value), and its re lated pin carries out the p52 function. 1 = pwm2 is on, and its related pi n will be set to output automatically. this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 18
em78p458/459 otp rom ? bit 6 (pwm1e): pwm1 enable bit 0 = pwm1 is off (default value), and its re lated pin carries out the p51 function; 1 = pwm1 is on, and its related pi n will be set to output automatically. ? bit 5 (t2en): tmr2 enable bit 0 = tmr2 is off (default value). 1 = tmr2 is on. ? bit 4 (t1en): tmr1 enable bit 0 = tmr1 is off (default value). 1 = tmr1 is on. ? bit 3: bit 2 ( t2p1:t2p0 ): tmr2 clock prescale option bits. t2p1 t2p0 p r escale 0 0 1 : 2 ( d e f a u l t ) 0 1 1 : 8 1 0 1 : 3 2 1 1 1 : 6 4 ? bit 1 : bit 0 ( t1p1:t1p0 ): tmr1 clock prescale option bits. t1p1 t1p0 p r escale 0 0 1 : 2 ( d e f a u l t ) 0 1 1 : 8 1 0 1 : 3 2 1 1 1 : 6 4 12. ioc61 ( dt1l: the least significant by te ( bit 7 ~ bit 0) of duty cy cle of pwm1 ) a specified value keeps the output of pwm1 to stay at high until the value matches with tmr1. 13. ioc71 ( dt1h: the most significant by te ( bit 1 ~ bit 0 ) of duty cy cle of pwm1 ) 7 6 5 4 3 2 1 0 c a l i 1 s i g n 1 vof1[2] v of1[1] vof1[0] - p w m 1 [ 9 ] pwm1[8] ? bit 7 (cali1): calibration enable bit 0 = calibration disable; 1 = calibration enable. ? bit 6 (sign1): polarity bit of offset voltage 0 = negative voltage; 1 = positive voltage. ? bit 5:bit 3 (vof1[2]:vof1[0]): offset voltage bits. ? bit 1:bit 0 (pwm1[9]:pwm1[8]) : the mos t signific ant byte of pwm1 duty cyc l e a specified value keeps the pwm1 output to st ay at high until the value matches with tmr1. this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 19
em78p458/459 otp rom 14. ioc81 ( prd1: period of pwm1 ): the conte n t o f ioc81 i s a p e rio d (time ba se ) of pwm 1 . the fre que ncy of pwm1 is the reve rse of the period. 15. ioc91 ( dt2l: the least significant by te ( bit 7 ~ bit 0 ) of duty cy cle of pwm2 ) a specified value keeps the of pwm1 output to stay at high until the value matches with tmr2. 16. ioca1 ( dt2h: the most significant by te ( bit 1 ~ bit 0 ) of duty cy cle of pwm2 ) 7 6 5 4 3 2 1 0 c a l i 2 s i g n 2 vof2[2] v of2[1] vof2[0] - p w m 2 [ 9 ] pwm2[8] ? bit 7 (cali2): calibration enable bit 0 = calibration disable; 1 = calibration enable. ? bit 6 (sign2): polarity bit of offset voltage 0 = negative voltage; 1 = positive voltage. ? bit 5:bit 3 (vof2[2]:vof2[0]): offset voltage bits ? bit 1:bit 0 (pwm2[9]:pwm2[8]) : the mos t signific ant byte of pwm1 duty cyc l e a specified value keeps the pwm2 output to st ay at high until the value matches with tmr2. 17. iocb1 ( prd2: period of pwm2 ) the conte n t o f iocb1 is a p e rio d (time ba se ) of pw m 2 . the fre que ncy of pwm2 is the reve rse of the period. 18. iocc1 ( dl1l: the least significant by te ( bit 7 ~ bit 0 ) of dut y cycl e latch of pwm1 ) the content of iocc1 is read-only. 19. iocd1 ( dl1h: the most significant byte ( bit 1 ~ bit 0 ) of d u t y cycle latch of pwm1 ) the content of iocd1 is read-only. 20. ioce1 ( dl2l: the least si gnificant by te ( bit 7 ~ bit 0) of duty cycle latch of pwm2 ) this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 20
em78p458/459 otp rom the content of ioce1 is read-only. 21. iocf1 ( dl2h: the most significant by te ( bit 1 ~ bit 0 ) of d u ty cy cle latch of pwm2 ) the content of iocf1 is read-only. this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 21
em78p458/459 otp rom 4.3 tcc/wdt & prescaler an 8-bit cou n t er is availabl e as prescal e r for the tc c or wdt. t he pre s cale r is a v ailable fo r ei ther the tcc or wdt only at any given time, a nd the pab bit of cont regi ster is u s ed to determ i ne the pre s cale r assignme n t. the psr0~psr2 bits determ i ne t he pre s cale ratio. the prescal e r is clea re d each time the instructio n is written to t c c und er t c c mode. the wdt an d prescaler, when a s sign ed to wdt mod e , are cle a re d by the wdt c o r slep i n stru ctio ns. fig. 5 de pict s the circuit diag ram of tcc/wdt. ? r1(tcc) is an 8-bit timer/ cou n ter . th e tcc clo ck so urce ca n be intern al or extern al clo ck in put (edg e sele ct a b le fro m tcc pin). if tcc signal sou r ce is from internal clo ck, tcc will increa se by 1 at every instructio n cy cle (witho ut pre s cale r). referri ng to fi g. 5, sele ctio n of clk=fo sc/2 o r clk=fosc/4 depe nd s on the co de opt i on bit clks. clk = fo sc/2 i f clks bit is "0", and clk=fosc/4 if clks bit is "1". ? if tcc sig n a l sou r ce is from external clock inpu t, tcc will incre a se by 1 at every falling edge or ri sin g edge of tcc pin. ? the wat c hd og timer i s a f r ee run n ing o n -chip rc oscillato r . the wdt will kee p on runni ng even af ter the oscillato r driver h a s be en turn ed of f (i.e. in sleep m ode ). duri ng norm a l ope rat i on or slee p mode, a wdt time-out (if enabled) will cause the device to reset. the wdt can be enabl ed or di sabl ed at an y time duri ng th e no rmal m o d e by sof t wa re pro g ra mmi ng . refer to wdte bit of ioce0 regi ste r . without presacler , the wdt time-out period is approximately 18 ms 1 . 1 note: vdd=5v,setup time period = 18ms 30%. vdd=3v,setup time period = 22ms 30%. this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 22
em78p458/459 otp rom 8-bit counter 8-to-1 mux mux m u x wdt tcc pin m u x m u x sync 2 cycles tcc (r1) pab pab pab ts te 0 0 1 1 1 0 wdte (in ioce) wdt timeout psr0 ~ psr2 0 1 data bus clk (fosc/2 or fosc/4) tcc overflow interrupt fig. 5 block diagram of tcc and wdt 4.4 i/o ports port 5, port 6, and the i/o regi ste r s a r e bi -directi o nal tri-state i/o port s . the function of pull-hi gh, pull-do wn, a n d ope n -d rai n can be set in ternally by io cb0, iocc0, and io cd0, re spe c tively. port 6 feature s an i nput statu s chang ed inte rrupt (o r wa ke-up) fun c tion. each i/o pin can be defin ed a s "input" or "out put" pin by the i/o control regi ster (ioc50 ~ io c60 ) . the i/o regi st ers and i/o control regi sters a r e both re ada ble and writ able. the i/o interf ace circuit s for port 5 and port 6 are sh own in the following fig. 6, fig. 7, and fig. 8 respectively. this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 23
em78p458/459 otp rom m u x port pcwr pdwr iod pdrd 0 1 pcrd d d q q q q _ _ c l c l p r clk clk note: pull-down is not shown in the figure. fig. 6 the ccircuit of i/o port and i/o control register for port 5 pcrd m u x iod 0 1 int pdrd p50, /int bit 6 of ioce0 pcwr d q q _ clk p r c l pdwr d q q _ clk p r c l p r c l clk dq q _ p r c l clk dq q _ port ti 0 note: pull-high (down) and open-drain are not shown in the figure. fig. 7 the circuit of i/o port a nd i/o control register for p50(/int) this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 24
em78p458/459 otp rom pcrd m u x iod 0 1 pdrd p60 ~ p67 pcwr d q q _ clk p r c l pdwr d q q _ clk p r c l p r c l clk dq q _ ti n port note: pull-high (down) and open-drain are not shown in the figure. fig. 8 the circuit of i/o port a nd i/o control register for p60~p67 /slep t17 t10 t11 ioce.1 interrupt eni instruction disi instruction interrupt (wake-up from sleep) next instruction (wake-up from sleep) clk clk clk q q q q q q _ _ _ d d d p p p l l l r r r c c c re.1 fig. 9 block diagram of port 6 w i th input changed interrupt/w ake-up this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 25
em78p458/459 otp rom table 4 usage of port 6 input changed wake-up/interrupt function usage of port 6 input status changed wake-up/interrupt (i) wake-up from port 6 input status change (ii) port 6 input status change interrupt (a) before sleep 1. read i/o port 6 (mov r6,r6) 1. disable wdt 2. execute "eni" 2. read i/o port 6 (mov r6,r6) 3. enable interrupt (set iocf0.1) 3. execute "eni" or "disi" 4. if port 6 changed (interrupt) 4. enable interrupt (set iocf0.1) interrupt vector (008h) 5. execute "slep" instruction (b) after wake-up 1. if "eni" interrupt vector (008h) 2. if "disi" nex t inst ruct ion 4.5 reset and wake-up 1. the function of reset and wake-up a reset is initiated by one of the following events- (1) power-on reset (2) /reset pin input "low", or (3) wdt time-out (if enabled). the devi c e i s kept in a re set con d itio n for a p e ri od of approxima t ely 18ms (on e oscillato r st art-u p timer period) after the re s e t is detec t ed. onc e the reset oc c u rs , the following func tions are performed. ? the oscillator is running, or will be started. ? the program counter (r2) is set to all "0". ? all i/o port pins are configured as input mode (high-impedance state). ? the watchdog timer and prescaler are cleared. ? when power is switched on, the upper 3 bits of r3 are cleared. ? the bits of the cont register are set to all "1" except for the bit 6 (int flag). ? the bits of the iocb0 register are set to all "1". ? the iocc0 register is cleared. ? the bits of the iocd0 register are set to all "1". ? bit 7 of the ioce0 register is set to "1", and bit 6 is cleared. ? bits 0~6 of rf register and bits 0~6 of iocf0 register are cleared. executing the ?slep? in stru ction will asse rt the sle ep (p owe r do wn ) mode. while enteri ng sl ee p mode, the wdt (if enabled) is cleared but keeps on running. the controller can be awakened by- (1) external reset input on /reset pin. this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 26
em78p458/459 otp rom (2) wdt time-out (if enabled). (3) port 6 input status change (if enabled). (4) comparator high. (5) adc c o mplete. the first two ca se s will ca use the em7 8 p458/4 59 to re set. the t and p fla g s o f r3 can be u s ed to determi ne th e source of the reset (wa k e - up ). ca se 3 is co n s ide r ed th e conti nuation of p r ogram executio n an d the global interrupt ("eni" or "d isi" being execu t ed) deci d e s wheth e r or n o t the cont rolle r b r a n ch es to the interrupt vect or follo wi n g wa ke -up. if eni is ex ecute d befo r e sle p , the instructio n wil l begin to exe c ute from the add re ss 0x 8 after wake-u p . if disi is executed befo r e slep, the execution will restart from the instru ction right next to slep after wake-up. only one of the cases 2, to 4 can be enabled before entering into sleep mode. that is, [a] if port 6 input status cha nge inte rrupt is e nabl ed befo r e sl ep , wdt must be di sa bl ed by softwa r e. ho weve r, the wdt bit in the opt io n regi ste r re main s en abl ed. hen c e, the em78p458/459 can be awakened only by case 1 or 3. [b] if wdt i s enabl ed b e fore slep, port 6 input stat us cha nge d interrupt mu st b e disable d . hence, the em78p45 8/459 can be awa k e ned o n l y by case 1 or 2. refe r to the se ction o n interru pt for further details. [c] if com p a r ator hig h interrupt is ena bled b e fo re slep, wdt must b e di sa bled by softwa r e. ho weve r, the wdt bit in the option re gi ster re main s enabl ed. hen c e, the em78p458/45 9 ca n be awakened only by case 1 or 4. if port 6 input status chan ge interru pt is used to wake up the em78p458/45 9 (as in case [a] above), the following instructions mu st be executed before slep: mov a, @0bxx000110 ; select internal t cc clock cont w clr r1 ; clear t cc and prescaler m o v a, @0bxxxx1110 ; select w d t pr escaler cont w w d t c ; clear w d t and prescaler m o v a , @0b 0 xxxxxxx ; dis able w d t iow re mov r6, r6 ; read port 6 mov a, @0b00000x1x ; enable po rt 6 input change interrupt iow rf this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 27
em78p458/459 otp rom eni (or disi) ; enable (or disable) global interrupt slep ; sleep nop similarly, if the comp arator high interrupt is used to wake up the em78p458 /459 (as in case [c] above), the following instructions must be executed before slep: mov a, @0bxx000110 ; select internal t cc clock cont w clr r1 ; clear t cc and prescaler m o v a, @0bxxxx1110 ; select w d t pr escaler cont w w d t c ; clear w d t and prescaler m o v a , @0b 0 xxxxxxx ; dis able w d t iow re m o v a, @0b01 xxxxxx ; enable co m par at or high int e r r upt iow rf eni (or disi) ; enable (or disable) global interrupt slep ; sleep nop one proble m use r mu st be awa r e of, is that afte r wa ki ng up from th e slee p mode , the wdt function will en able a u tomatically. the wdt o peration (bei ng en able d or di sabl ed ) sho u ld b e h andle d appropriately by software after waking up from the sleep mode. 2. the status of t, and p of status register a reset condition is initiated by one of the following events : (1) a power-on condition, (2) a high-low-high puls e on /reset pin, or (3) watchdog timer time-out. the values of t and p, as listed in table 5 below, are used to check how the pro c e s sor wa ke s up. table 6 shows the events, which ma y affect the status of t and p. this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 28
em78p458/459 otp rom table 5 the values of rst, t, and p after reset reset type t p p o w e r - o n 1 1 /reset during operating mode *p *p /reset wake-up during sleep mode 1 0 wdt during operating mode 0 *p wdt wake-up during sleep mode 0 0 wake-up on pin change during sleep mode 1 0 *p: previous status before reset table 6 the status of rst, t and p being affected by ev ents event t p p o w e r - o n 1 1 wdtc instruction 1 1 wdt time-out 0 *p slep instruction 1 0 wake-up on pin changed during sleep mode 1 0 *p: previous value before reset wdt timeout o scillator d q clk clr wdt vdd setup time reset clk /reset power-on reset voltage detector w fig. 10 block diagram of reset of controller this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 29
em78p458/459 otp rom 4.6 interrupt the em78p458/459 has six interrupts as listed below: (1) tcc overflow interrupt (2) port 6 input status change interrupt (3) external interrupt [(p50, /int) pin]. (4) analog to digital conversion completed. (5) when tmr1/tmr2 matches with p rd1/prd2 respectively in pwm. (6) when the comparators output change. before the p o rt 6 input status cha nge interru pt is e nable d , rea d i ng port 6 (e. g . "mov r6, r 6") i s necessary. each port 6 pin will have this feature if its st atus changes. any pin c onfigured as out put or p50 pin confi gured a s /int , is exclud ed from this fun c tion. port 6 input status ch ange inte rrup t will wa ke up the em78p45 8/4 59 from the sl eep mod e if it is ena bled p r i o r to going int o the sleep m ode b y executin g sl ep. when the controller i s wa ke -up, it will continu e to execute the succee ding p r ogram if the global int e rrupt is di sa bled, or b r an che s out to t he interrupt vector 0 0 8 h if the glob al inte rru pt is enabled. rf, the interrupt status re g i ster t hat reco rd s the interrupt requ est s in the relative flags /bits . iocf0 is an interru p t mask re giste r . the glo bal int e rrupt is e nab led by the eni instru ction an d is di sabl ed by the disi instru ction. whe n on e of the interrupt s (when enabl ed ) occurs, the next instru ction will be fetched f r om add re ss 008 h. on ce i n th e interrupt se rv ice routin e, the so urce of an inte rrupt can be determi ned b y polling th e fl ag bit s in rf. the i n terrupt flag bit mu st be clea red by instructio ns before leaving the interrupt service routi ne to avoid recursive interrupts. the flag (except icif bit) in the interrup t status r egi ster (rf) is set regardl e s s of the status of its mask bit or the execution of eni. note th at the out com e of rf will be the logic a nd of rf and iocf0 (refe r to fig. 11). the ret i instru ction e nds the in te rrupt routin e an d enabl es the global inte rru pt (the execution of eni). whe n an i n te rru pt is g ene rated by the i n t in stru ctio n (when ena bled ), the ne xt instructio n will be fetched from address 001h. this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 30
em78p458/459 otp rom fig. 1 1 interrupt input circuit 4.7 analog-to-digital converter (adc) the an alog -t o-di git a l ci rcuitry con s i s t s of an 8 - bi t analog mu ltiplexer , thre e cont rol re giste r s (adcon/r9, ad-cmp-con/ioca 0, gco n /ioc9 0), on e dat a regi ster (adda t a/ ra) a n d an adc with 8-bit re solution. the function al blo ck di agr am o f the adc is sho w n in fig. 12. the analog reference volt age (v ref) and analog ground ar e connected via sep a rate input pins. the adc mo dule utilize s su ccessive a pproximation to convert the unkno wn analo g sign al into a digital value. the result is fed to the adda ta. in put ch ann els are sel e cte d by the anal og inp u t multiplexer via the adcon register bits adis0, adis1, and adis2. 0 1 2 3 4 5 6 7 op2 gcon 54 3 2 10 addata op1 data bus adc4 adc3 adc2 adc1 adc5 adc6 adc7 adc8 vref power-down fsco internal rc 4-1 mux 2 3 4 3 4 adc ( successive approximation ) 3 8-1 a nal og swi t c h 0 1 0 1 2 ad-cmpcon rf ad-cmpcon adcon adcon + + - - start to convert fig. 12 the functional block diagram of analog-to-digit al conv ersion this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 31
em78p458/459 otp rom 1. adc control register (adcon/ r9, ad-cmp-con/ioca0, gcon/ioc90) 1.1 adcon/r9 the adco n regi ster cont rols the op erat ion of t he a/d conversio n a nd de cide s which pi n sh ou ld be currently active. bit 7 6 5 4 3 2 1 0 s y m b o l - - i o c s adrun adpd a d i s 2 a d i s 1 adis0 * i n i t _ v a l u e 0 0 0 0 0 0 0 0 *init_value: initial value at power on reset ? adrun (bit 4) : adc starts to run. 1 = an a/d conversion is started. this bit can be set by software. 0 = reset on completion of the conversion. this bit can not be reset in software. ? adpd (bit 3) : adc power-down mode. 1 = adc is operating; 0 = switch off the resistor reference to sa ve power even when the cpu is operating. ? adis2~adis0 (bit 2~0) : analog input select. 000 = an0; 001 = an1; 010 = an2; 011 = an3; 100 = an4; 101 = an5; 110 = an6; 111 = an7; change occurs only when the adif bit and the adrun bit are both low. 1.2 ad-cmp-con/ioca0 the ad-cm p -co n re gister define s the pins of port 6 as analog inp u ts or as digita l i/o, individually. bit 7 6 5 4 3 2 1 0 s y m b o l v r e f s c e c o e i m s 2 ims1 i m s 0 ckr1 ckr0 * i n i t _ v a l u e 0 0 0 0 0 0 0 0 *init_value: initial value at power on reset ? vrefs (bit 7): the input source of the vref of the adc. 0 = the vref of the adc is con n e c ted to vdd (default value), and th e p53/vref pin ca rrie s out the function of p53; this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 32
em78p458/459 otp rom 1 = the vref of the adc is connected to p53/vref. ? ce (bit 6): control bit used to enable comparator. 0 = disable comparator 1 = enable comparator ? coe (bit 5): set p57 as the output of the comparator 0 = the comparator acts as an op if ce=1. 1 = act as a comparator if ce=1. ? ims2~ims0 (bit 4 ~ bit 2): adc configuration definition bit. ? ckr1 and ckr0 (bit 1 and bit 0) : the conversion time select. 00 = fosc/4; 01 = fosc/16; 10 = fsco/64; 11 = the oscillator clock source of adc is from wdt ring oscillator frequency. ( frequency=256/18ms ? 14.2khz) 1.3 gcon/ioc90 as sh own in fig. 12, op1 and op2, the gain am p lifie rs, a r e lo cate d in the mid d l e of the anal og input pins (adc1 and adc5) and the 8-1analog switch . the gcon register controls the gains. table 7 table 7 show s the gains and the operating range of adc. bit 7 6 5 4 3 2 1 0 s y m b o l o p 2 e op1e g22 g 2 1 g 2 0 g 1 2 g 1 1 g10 * i n i t _ v a l u e 0 0 0 0 0 0 0 0 table 8 the gains and the operating range of adc g10:g12/g20:g22 gain range of operating voltage 000 1 0 ~ vref 001 2 0 ~ (1/2)vref 010 4 0 ~ (1/4)vref 011 8 0 ~ (1/8)vref 100 16 0 ~ (1/16)vref 101 32 0 ~ (1/32)vref v r ef can not be less than 3 volt s. 2. adc data register (addata/ra) whe n the a/d conversio n is co mple te, the re sult is l oade d to t he addata. th e start/end bit is clear, and the adif is set. this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 33
em78p458/459 otp rom 3. a/d sampling time the a c curacy , linearity, an d sp eed of th e su cce ssive app roximatio n a/d convert e r a r e d epe n dent on the prope rtie s of the a dc and th e co mparator. t h e so urce i m p edan ce and the inte rnal samplin g imped an ce dire ctly affect the time requi red to c harge the sample holding capa ci tor. the applicatio n pro g ra m co ntrol s the lengt h of the samp le time to meet the spe c ified accu ra cy. gene rally sp eaki ng, the pro g ram sho u ld wait fo r 1 g s f o r ea ch k ?
em78p458/459 otp rom (a) select a/d input channel ( adas2:adas0 ); (b) select the proper gains by writing to the gcon register ( optional ); (c) define a/d conversion clock rate ( ckr1:ckr0 ); (d) set the adpd bit to 1 to begin sampling. (3) put ?eni? instruction, if t he interrupt function is employed. (4) set the adrun bit to 1. (5) wait for either the interrupt flag to be set or the adc interrupt to occur. (6) read addata, the c onversion data register. (7) clear the interrupt flag bit (adif). (8) fo r next conversio n , go to step 1 or step 2 as require d. at least 2 tct is requi red befo r e ne xt acquisition starts. : to o b tain an a c cu rate value, it is ne ce ss ary t o avoid any d a ta tran sition on i/o pins d u ring ad conversion. 2. the demonstration programs ; t o define the general registers r_0 = = 0 ; indirect addressing register psw = = 3 ; status register port 5 = = 5 port 6 = = 6 r_f = = 0xf ; interrupt status register ; t o define the control register ioc50 = = 0x5 ; control register of port 5 ioc60 = = 0x6 ; control register of port 6 c_int = = 0xf ; interrupt control register ;adc control registers addat a = = 0xa ; t he content s are the results of adc adcon r== 0x 9 ; 7 6 5 4 3 2 1 0 this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 35
em78p458/459 otp rom ; - - iocs adrun adpd adis2 adis1 adis0 adconc== 0x a ; 7 6 5 4 3 2 1 0 ; vrefs x x ims2 ims1 ims0 ckr1 ckr0 gcon == 0x 9 ; 7 6 5 4 3 2 1 0 ; ope2 ope1 g22 g21 g20 g12 g11 g10 ;t o define bits ;in adconr adrun == 0x4 ; adc is executed as the bit is set adpd = = 0x3 ; pow e r mode of adc org 0 ; initial address jmp init ial ; org 0x 08 ; interrupt vector (user program) clr r_f ; t o clear the adcif bit bs adconr, adrun ; t o start to execute the next ad conversion if necessary ret i init ial: m o v a, @0bxxxx1xxx ; enable t he int e r r upt f unct i on of adc, ? x ? by applicat ion iow c_int mov a, @0xxx ; interrupt disabled:< 6 > cont w mov a, @0b00000000 ; t o employ vdd as the referenc e voltage, to define p60 as iow adconc ; an analog input and set clock rate at fosc/4 en_adc: this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 36
em78p458/459 otp rom m o v a, @0b xxxxxxx1 ; t o def i ne p60 as an i nput pi n, and t he ot her s ar e de pen de n t iow port 6 ; on applications mov a, @0b01000101 ; t o enable the op1, and set the gain as 32 iow gcon bs adconr, adpd ; t o disabl e the pow er-dow n mode of adc eni ; enable the interrupt function bs adconr, adrun ; start to run the adc ; if the interrupt function is employ ed, the follow i ng three lines may be ignored p o l l i n g : jbc adconr, adrun ; t o check the adrun bit continuously ; jmp polling ; adrun bit w ill be reset as the ad conversion is completed (user program) : : : 4.8 dual sets of pwm ( pulse width modulation ) 1. overview in pwm mode, both pwm1 and pwm2 pins produ ce up to a 10-bit re solutio n pwm output (see. fig. 13 for the functional blo c k diag ram ) . a pwm output has a peri od and a duty cycle, and it keeps the output in high . the baud rat e of the pwm is the inve rse of the period. fig. 14 depicts the relation ship s between a period and a duty cycle. this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 37
em78p458/459 otp rom da t a b u s da t a b u s pr d1 c o m par at o r c o m par at or tm r 1 h + tm r 1 l s rq mu x d u t y c ycl e ma t c h pe r i od ma t c h p wm1 t1p0 t1p1 t1 e n io c 5 1 pr d2 c o m par at o r c o m par at o r s rq mu x d u t y c ycl e ma t c h pe r i od ma t c h p wm2 t2p0 t2p1 t2 e n io c 5 1 to pw m 1 i f to pw m 2 i f re s e t re s e t la tc h la tc h 1: 2 1: 8 1: 32 fo s c 1: 64 1: 2 1: 8 1: 32 fo s c 1: 64 tm r 2 h + tm r 2 l dt2 h + dt2 l dt1 h + dt1 l dl 2 h + dl 2 l dl 1 h + dl 1 l fig. 13 the functional block diagram of the dual pwms period duty cycle dt1 = tmr1 prd1 = tmr1 fig. 14 the output t i ming of the pwm 2. increment timer counter ( tmrx : tmr1h/twr1l or tmr2h/twr2l ) tmrx are te n-bit clo c k co unters with prog ramm able prescal e rs. they are de signed for the pwm modul e as b aud rate cl o ck gen erato r s. tmrx ca n be read, written, an d clea re d at a n y rese t con d ition s . if employed, they can be tur ned do wn for power saving by setting t1e n bit [pwmcon< 4> ] or t2en bit [pwmcon< 5> ] to 0. 3. pwm period ( prdx : prd1 or prd2 ) the pwm pe riod i s defin e d by writin g to the prdx regi ster. whe n tmrx i s e qual to prdx, the this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 38
em78p458/459 otp rom following events occur on t he next increment cycle: ? tmrx is cleared. ? the pwmx pin is set to 1. ? the pwm duty cycle is latched from dt1/dt2 to dtl1/dtl2. < note > the pwm output will not be set, if the duty cycle is 0; ? the pwmxif pin is s e t to 1. the following formula describes how to calculate the pwm period: period = (prdx + 1) * 4 * (1/fosc) * (tmrx prescale v a lue ) 4. pwm duty cy cle ( dtx: dt1h/ dt1l and dt2h/ dt2l; dtl: dl1h/dl1l and dl2h/dl2l ) the pwm dut y cycle i s d e fined by writin g to the dtx regi ster, a nd i s latched fro m dtx to dl x whil e tmrx is cl ea red. wh en dlx is equal to tmrx, t he pwmx pin is cl eared. dtx can be load ed at any time. however, it cannot be latched into dtl unt il the current value of dlx is equal to tmrx. the following formula describes how to calculate the pwm duty cycle: duty cy cle = (dtx) * (1/fosc) * (tmrx prescale v a lue ) 5. comparator x to change the output status while the match occurs , the tmrxif flag will be set at the same time. 6. pwm programming procedures/steps (1) load prdx with the pwm period.. (2) load dtx with the pwm duty cycle. (3) enable interrupt function by writing iocf0, if required. (4) set pwmx pin to be output by writing a desired value to ioc51. (5) loa d a d e s ired valu e to ioc51 with t m rx p r e s cal e r valu e an d enabl e both pwmx an d t m rx. this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 39
em78p458/459 otp rom 4.9 timer 1. overview timer1 (t mr1) a nd tim e r2 (tm r 2 ) (tm r x) a r e 10 -bit clo c k counte r s with prog ra mmable prescale rs, re spe c tively. they are de si gned fo r the pwm mo dul e as b aud rate clo ck gen era t ors. tm rx can b e read, written, and cleared at any reset conditions. 2. function description fig. 15 shows tmrx block diagram. each signal and block are described as follows: data bus data bus prd1 comparator tmr1x mux period match t1p0 t1p1 t1en prd2 comparator tmr2x mux period match t2p0 t2p1 t2en to pwm1if to pwm2if reset reset 1:2 1:8 1:32 f osc 1:64 1:2 1:8 1:32 fosc 1:64 *tmr1x = tmr1h + tmr1l; *tmr2x = tmr2h +tmr2l fig. 15 tmrx block diagram fosc : input clock. prescale r ( t1p0 and t 1 p1/t2p1 and t2p0 ) : options of 1:2, 1:8, 1:32, and 1:64 are defi ned by tmrx. it is cleared when any type of reset occurs. tmr1x and tmr2x (tmr1h/twr1l and tmr2h/tmr2l ) : timer x regis t er; tmrx is increased until it matches with prdx, and t hen is reset to 0. tmrx cannot be read. prdx ( prd1 and prd2 ): pwm period register. compar ato r x ( compar a t or 1 an d co mparator 2 ): to re set tmrx while a match occu rs a nd the tmrxif flag is s e t at the s a me time. this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 40
em78p458/459 otp rom 3. programming the related registers when defining tmrx, refer to the related regi sters of its operation as shown in table 9.it must be noted that the pwmx bits must b e di sa bled if thei r re lated tm rxs are employe d . that is, bit 7 and bit 6 of the pwmcon register must be set to ?0?. table 10 related control registers of tmr1 and tmr2 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 i o c 5 1 p w m c o n / i o c 5 1 pwm2e p wm1e t2en t1en t 2 p 1 t 2 p 0 t1p1 t1p0 4. timer programming procedures/steps (1) load prdx with the timer period. (2) enable interrupt function by writing iocf0, if required (3) lo ad a de sired value to pwmco n with the tmrx prescal e r value and ena bl e both tmrx and disable pwmx. 4.10 comparator em78p45 8/4 59 ha s o ne compa r ato r , which ha s two analo g inp u ts and o ne o u tput. the com parator can be employed to wake up from the sleep mode. fig. 16 shows the circuit of the comparator. + - cin - cin + co cmp fig. 16 comp arator operating mode 1. external reference signal the anal og si gnal that is prese n ted at ci n- co mpa r e s to the sign al at cin+, an d the digital output (co ) of the comparator is adjusted accordingly. ? the reference signal must be between vss and vdd. ? the reference voltage can be applied to either pi of comparator. ? threshold detector applications ma y be of the same reference. ? the comparator can operate from the same or different reference source. 2. comparator outputs ? the compared result is stored in the cmpout of r3. ? the compa r ator output s is output to p57 by pr og ra mming bit5 of the ad-cmpco n regi ster to 1. this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 41
em78p458/459 otp rom ? p57 must be defined as an output if implemented as the comparator output. ? fig. 17 shows the comparator output block diagram. q q en en d d to c0 to cpif to cmpout cmrd cmrd from other comparator reset from op i/o fig. 17 the output configuration of a comp arator 3. using as an operation amplifier the co mpa r a t or can b e used as an o p e r ation am plif ier if a feedba ck resi sto r is con n e c ted fro m the input to the o u tput external ly. in this case, t he schmitt trigger can be disa bled for power saving by setting ce to 1 and coe to 0. 4. interrupt ? cmpie (iocf0.6) must be enabled. ? interrupt occurs at the rising edge of the comparator output pin. ? the actual change on the pin can be deter mined by reading the bit cmpout, r3<7>. ? cmpif (rf.6), the comparator interrupt flag, can only be cleared by software. 5. wake-up from sleep mode ? if enabled, the com p a r ato r remai n s a c ti ve and t he interrupt rem a in s functio nal, even und er sleep mode. ? if a mismatch occurs, the interrupt will wake up the device from sleep mode. ? the power consumption should be taken into cons ideration for the benefit of energy conservation. ? if the function is unem pl oyed during sleep mode, tu rn off com parator before enteri ng int o sleep mode. this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 42
em78p458/459 otp rom 4.11 the initialized values after reset table 11 the summary of the initialized values for registers address name reset ty pe bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit name c57 c56 c55 c 5 4 c 5 3 c 5 2 c 5 1 c 5 0 pow e r - o n 1 1 1 1 1 1 1 1 /reset a n d w d t 1 1 1 1 1 1 1 1 n/ a i o c 5 0 w a ke-up from pin changed p p p p p p p p bit name c67 c66 c65 c64 c 6 3 c 6 2 c 6 1 c 6 0 pow e r - o n 1 1 1 1 1 1 1 1 /reset a n d w d t 1 1 1 1 1 1 1 1 n/ a i o c 6 0 w a ke-up from pin changed p p p p p p p p bit name /pd 7 /pd 6 */pd 5 */pd 4 /pd 3 / p d 2 / p d 1 /pd 0 pow e r - o n 1 1 1 1 1 1 1 1 /reset a n d w d t 1 1 1 1 1 1 1 1 n/ a i o c b 0 w a ke-up from pin changed p p p p p p p p bit name od7 od6 od5 od4 o d 3 o d 2 o d 1 o d 0 pow e r - o n 1 1 1 1 1 1 1 1 /reset a n d w d t 1 1 1 1 1 1 1 1 n/ a i o c c 0 w a ke-up from pin changed p p p p p p p p bit name /ph 7 /ph 6 /ph 5 /ph 4 /ph 3 / p h 2 / p h 1 /ph 0 pow e r - o n 1 1 1 1 1 1 1 1 /reset a n d w d t 1 1 1 1 1 1 1 1 n/ a i o c d 0 w a ke-up from pin changed p p p p p p p p bit name wd t e eis x x x x x x pow e r - o n 1 0 1 1 1 1 1 1 /reset a n d w d t 1 0 1 1 1 1 1 1 n/ a i o c e 0 w a ke-up from pin changed p p 1 1 1 1 1 1 bit name x cmpi e p mw 2i e p w m 1i e a di e ex ie ic ie tci e pow e r - o n 0 0 0 0 0 0 0 0 /reset a n d w d t 0 0 0 0 0 0 0 0 n/ a i o c f 0 w a ke-up from pin changed 0 p p p p p p p bit name op2e op1e g22 g21 g 2 0 g 1 2 g 1 1 g 1 0 pow e r - o n 0 0 0 0 0 0 0 0 /reset a n d w d t 0 0 0 0 0 0 0 0 n/ a ioc90 (gcon) w a ke-up from pin changed p p p p p p p p bit name vrefs ce coe im s2 i m s 1 i m s 0 ckr1 ckr0 pow e r - o n 0 0 0 0 0 0 0 0 /reset a n d w d t 0 0 0 0 0 0 0 0 n/ a ioc a 0 (ad-cmp con) w a ke-up from pin changed p p p p p p p p bit name pw m2e pw m2e t2en t1en t 2 p 1 t 2 p 0 t 1 p 1 t 1 p 0 pow e r - o n 0 0 0 0 0 0 0 0 /reset a n d w d t 0 0 0 0 0 0 0 0 n/ a ioc51 (pw m con) w a ke-up from pin changed p p p p p p p p bit n a m e b i t 7 b i t 6 b i t 5 b i t 4 bit3 bit2 bit1 bit0 pow e r - o n 0 0 0 0 0 0 0 0 n/ a /reset a n d w d t 0 0 0 0 0 0 0 0 ioc61 (dt1l) w a ke-up from pin changed p p p p p p p p bit name cali 1 s i g n1 vof1[ 2 ] v of1[ 1] vof 1 [0] x bit1 bit0 pow e r - o n 0 1 1 0 0 0 0 0 /reset a n d w d t 0 1 1 0 0 0 0 0 n/ a ioc71 (dt1h) w a ke-up from pin changed p p p p p 0 p p b i t n a m e - - - - - - - - pow e r - o n 0 0 0 0 0 0 0 0 /reset a n d w d t 0 0 0 0 0 0 0 0 n/ a ioc81 (prd1) w a ke-up from pin changed p p p p p p p p bit n a m e b i t 7 b i t 6 b i t 5 b i t 4 bit3 bit2 bit1 bit0 pow e r - o n 0 0 0 0 0 0 0 0 /reset a n d w d t 0 0 0 0 0 0 0 0 n/ a ioc91 (dt2l) w a ke-up from pin changed p p p p p p p p n/ a i o c a 1 bit n a m e cali 2 s i g n2 vof2[ 2 ] v of2[ 1] vof 2 [0] x bit1 bit0 this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 43
em78p458/459 otp rom address name reset ty pe bit 7 bit 4 bit 2 bit 1 bit 0 bit 6 bit 5 bit 3 pow e r - o n 0 1 1 0 0 0 0 0 /reset a n d w d t 0 1 1 0 0 0 0 0 (dt2h) w a ke-up from pin changed p p p p p 0 p p b i t n a m e - - - - - - - - pow e r - o n 0 0 0 0 0 0 0 0 /reset a n d w d t 0 0 0 0 0 0 0 0 n/ a ioc b 1 (prd2) w a ke-up from pin changed p p p p p p p p bit n a m e b i t 7 b i t 6 b i t 5 b i t 4 bit3 bit2 bit1 bit0 pow e r - o n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n/ a i o cc1 (dl1l) w a ke-up from pin changed p p p p p p p p b i t n a m e x x x x x x bit1 bit0 pow e r - o n 0 0 0 0 0 0 0 0 /reset a n d w d t 0 0 0 0 0 0 0 0 n/ a i o cd1 (dl1h) w a ke-up from pin changed 0 0 0 0 0 0 p p bit n a m e b i t 7 b i t 6 b i t 5 b i t 4 bit3 bit2 bit1 bit0 pow e r - o n 0 0 0 0 0 0 0 0 /reset a n d w d t 0 0 0 0 0 0 0 0 n/ a ioc e 1 (dl2l) w a ke-up from pin changed p p p p p p p p b i t n a m e x x x x x x bit1 bit0 pow e r - o n 0 0 0 0 0 0 0 0 /reset a n d w d t 0 0 0 0 0 0 0 0 n/ a ioc f 1 (dl2h) w a ke-up from pin changed 0 0 0 0 0 0 p p bit n a m e in t e in t ts te p a b p s r 2 p s r 1 psr0 pow e r - o n 1 0 1 1 1 1 1 1 /reset a n d w d t 1 0 1 1 1 1 1 1 n/ a c o n t w a ke-up from pin changed p p p p p p p p b i t n a m e - - - - - - - - pow e r - o n u u u u u u u u /reset a n d w d t p p p p p p p p 0x 0 0 r 0 ( i a r ) w a ke-up from pin changed p p p p p p p p b i t n a m e - - - - - - - - pow e r - o n 0 0 0 0 0 0 0 0 /reset a n d w d t 0 0 0 0 0 0 0 0 0x 0 1 r 1 ( t c c ) w a ke-up from pin changed p p p p p p p p b i t n a m e - - - - - - - - pow e r - o n 0 0 0 0 0 0 0 0 /reset a n d w d t 0 0 0 0 0 0 0 0 0x 0 2 r 2 ( p c ) w a ke-up from pin changed jump to address 0x 08 or continue to ex ecute nex t instruction bit name gp2 ps1 ps0 t p z dc c pow e r - o n 0 0 0 1 1 u u u /reset and w d t 0 0 0 t t p p p 0x 0 3 r 3 ( s r ) w a ke-up from pin changed p p p t t p p p bit name bs7 bs6 - - - - - - pow e r - o n 0 0 u u u u u u /reset a n d w d t 0 0 p p p p p p 0x 0 4 r 4 ( r s r ) w a ke-up from pin changed p p p p p p p p bit n a m e p 5 7 p 5 6 p 5 5 p 5 4 p 5 3 p 5 2 p 5 1 p 5 0 pow e r - o n 1 1 1 1 1 1 1 1 /reset a n d w d t 1 1 1 1 1 1 1 1 0x 0 5 p 5 w a ke-up from pin changed p p p p p p p p bit name p67 p66 p65 p64 p 6 3 p 6 2 p 6 1 p 6 0 pow e r - o n 1 1 1 1 1 1 1 1 /reset a n d w d t 1 1 1 1 1 1 1 1 0x 0 6 p 6 w a ke-up from pin changed p p p p p p p p b i t n a m e - - - - - - - - pow e r - o n u u u u u u u u /reset a n d w d t p p p p p p p p 0x 7~0x 8 r 7 ~ r 8 w a ke-up from pin changed p p p p p p p p bit name x x i o cs adrun adpd adas2 adas1 adas0 pow e r - o n 0 0 0 0 0 0 0 0 0x 9 r 9 (adcon) /reset a n d w d t 0 0 0 0 0 0 0 0 /reset a n d w d t this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 44
em78p458/459 otp rom address name reset ty pe bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w a ke-up from pin changed p p p p p p p p b i t n a m e - - - - - - - - pow e r - o n 0 0 0 0 0 0 0 0 /reset a n d w d t 0 0 0 0 0 0 0 0 0x a ra (adddata) w a ke-up from pin changed p p p p p p p p bit n a m e b i t 7 b i t 6 b i t 5 b i t 4 bit3 bit2 bit1 bit0 pow e r - o n 0 0 0 0 0 0 0 0 /reset a n d w d t 0 0 0 0 0 0 0 0 0x b rb (tmr1l) w a ke-up from pin changed p p p p p p p p b i t n a m e x x x x x x bit1 bit0 pow e r - o n 0 0 0 0 0 0 0 0 /reset a n d w d t 0 0 0 0 0 0 0 0 0x c rc (tmr1h) w a ke-up from pin changed 0 0 0 0 0 0 p p bit n a m e b i t 7 b i t 6 b i t 5 b i t 4 bit3 bit2 bit1 bit0 pow e r - o n 0 0 0 0 0 0 0 0 /reset a n d w d t 0 0 0 0 0 0 0 0 0x d rd (tmr2l) w a ke-up from pin changed p p p p p p p p b i t n a m e x x x x x x bit1 bit0 pow e r - o n 0 0 0 0 0 0 0 0 /reset a n d w d t 0 0 0 0 0 0 0 0 0x e re (tmr2h) w a ke-up from pin changed 0 0 0 0 0 0 p p bit name x cmpi f p w m 2i f p w m 1i f adif ex if ic if tci f pow e r - o n 0 0 0 0 0 0 0 0 /reset a n d w d t 0 0 0 0 0 0 0 0 0x f rf (isr) w a ke-up from pin changed 0 p p p p p p p b i t n a m e - - - - - - - - pow e r - o n u u u u u u u u /reset a n d w d t p p p p p p p p 0x 10~0x 3 f r 1 0 ~ r 3 f w a ke-up from pin changed p p p p p p p p x: not used. u: unknown or don?t care . p: previous value before reset. t: check table 5 4.12 oscillator 1. oscillator modes the em7 8 p4 58 an d em7 8 p459 ca n b e ope rate d in four diffe rent oscillato r mo des, su ch as hig h xtal oscillat o r mod e (hx t ), low xta l oscillato r m ode (lxt), external rc o s cillato r mod e (erc), and rc o s cill ator mo de wit h internal ca p a cito r (ic). users ca n sele ct one of them by prog ram m i ng the mask option. the up-limit ed operation frequenc y of cr ys tal/res o nat or on the different vdds is lis t ed in table 11. table 12 the summary of maximum operating speeds conditions vdd fx t max . (mhz) 2 . 3 4 3 . 0 8 two clocks 5 . 0 2 0 2. cry s tal oscillator/cera mic resonators (xtal) em78p45 8/4 59 can be dri v en by an extern al clo c k si gnal throug h the osci pin as sho w n in fig. 18 this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 45
em78p458/459 otp rom below. osci osco ext. clock em78p458 em78p459 fig. 18 circuit for external clock input in the most appli c ation s , pin osci an d pin osco can b e co n necte d with a cry s tal or ce rami c re son a tor to g ene rate oscill ation. fig. 19 depi cts such circuit. the sa me applie s to the hxt mod e and the lxt mod e . table 12 provided the re comm end ed va lues of c1 and c2. since each re son a tor ha s its own attrib ute, use r sho u ld refe r to th eir spe c if icati ons fo r ap pro p riate valu es of c1 an d c2 . rs, a serial resistor, may be necessary for at strip cut crystal or low frequency mode. osci osco em78p458 em78p459 c1 c2 xtal rs fig. 19 circuit for cry s t a l/resonator table 13 capacitor selection guide for cry s tal oscillator or ceramic resonators oscillator type frequency mode frequency c1(pf) c2(pf) 455 khz 100~150 100~150 2.0 mhz 20~40 20~40 ceramic resonators hxt 4.0 mhz 10~30 10~30 32.768khz 25 15 100khz 25 25 lxt 200khz 25 25 4 5 5 k h z 2 0 ~ 4 0 2 0 ~ 1 5 0 1 . 0 m h z 1 5 ~ 3 0 1 5 ~ 3 0 2 . 0 m h z 1 5 1 5 crystal oscillator hxt 4 . 0 m h z 1 5 1 5 3. external rc oscillator mode for som e ap plicatio ns that do not require preci s e ti ming cal c ulatio n , the rc oscil l ator (fig. 20) could this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 46
em78p458/459 otp rom offer users wi th an effective co st savin g s . neve rt hele ss, it sh ould be noted th at the freque ncy of the rc o scill ator is influen ced b y the supply voltage, the values of the resi stor (r ext), the capa citor(cext) , and even by the ope ration t e mpe r atu r e. more over, t he freque ncy a l so chan ge s slightly from one chi p to another due to the manufacturing process variation. in orde r to maintain a sta b l e system fre quen cy, the value s of the cext sho u ld n o t be less tha n 20pf, and that the value of rext should n o t be gre a ter than 1 m ohm. if they cannot b e kept in this ra n ge, the frequency can be affected easily by noise, humidity, and leakage. the smalle r the rext in the rc oscillato r, the faster its freque ncy wil l be. on the contra ry, for very low rext values, for instan ce , 1 k ?
em78p458/459 otp rom 3.3k 510 khz 470 khz 5.1k 340 khz 320 khz 10k 175 khz 170 khz 300 pf 100k 19 khz 19 khz 1. measured on dip packages. 2. design reference only 4. rc oscillator mode w i th internal capacitor if both pre c isi on an d cost a r e taken into con s id erat ion , em78p257a /b also offers a sp eci a l o sci llation mode. it is equipp ed with an internal cap a cito r an d an external resi stor (co n necte d to vcc). the intern al cap a c itor fun c tion s as temperatu r e com pen sa t o r. in order to obtain more accurate frequ ency, a precise resistor is recommended. os c i em 78p458 vcc r ext em 78p459 fig. 21 circuit for internal c oscillator mode table 15 r oscillator frequencies rex t average fosc 5v,25
em78p458/459 otp rom applications are involved, extra dev ices are required to assist in solving the power-up problems. 1. external pow e r on reset circuit the circuit sh own in fig. 22 implement s an external rc to prod uce a reset pul se. the pulse width (time con s tan t ) sho u ld b e kept long e n o ugh to allo w vdd to rea c h minimum o p e r ation voltag e . this circuit i s u s e d wh en th e p o we r sup p ly has a slo w ri se time. be cause the cu rrent lea k ag e f r om the /reset pin is about
em78p458/459 otp rom em78p458 em78p459 /reset vdd q1 vdd r3 r2 r1 fig.24 circuit 2 for the residue v o lt age protection 4.14 code option em78p45 8/4 59 ha s o ne co de optio n word an d o ne cu stom er id wo rd that are n o t a pa rt of the normal program memory. word 0 word 1 bit12~ b i t 0 b i t 1 2 ~ b i t 0 code option12~0 code option12~0 1. code option register (word 0) bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5~ b it0 ms /enwdt clks /ptb hlf rct hlp id ? bit 12 (ms): oscillator type selection. 0: rc type 1: xtal type ? bit 11 (/enwtd) : watchdog timer enable bit. 0: enable 1: disable ? bit 10 (clks): clocks of each inst ruct ion cy cle. 0: two clocks 1: four clocks refer to the s e c t ion of ins t ruc t ion set. ? bit 9 (/ptb): protect bit. 0: enable 1: disable ? bit 8 (hlf) : xtal frequency selection. 0: low frequency this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 50
em78p458/459 otp rom 1: high frequency ? bit 7 (rct) : resistor capacitor 0: inter c, external r 1: external rc ? bit 6 (hlp) : power consumption selection. 0: low power. 1: high power. ? bit 5 ~ bit 0 (id[5]~id[0]): cus t omer?s id. 2. code option register (word 1) bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4~bit0 sign2 vof2[2] vof2[1] vof2[0] sign1 vof1[2] vof1[1] vof1[0] - ? bit 12 (sign2): polarity bit of offset voltage. 0: negative voltage 1: positive voltage ? bit 11 ~ bit 9 (vof2[2]~vof2[0]): offset voltage bits ? bit 8 (sign1): polarity bit of offset voltage. 0: negative voltage 1: positive voltage ? bit 7 ~ bit 5 (vof1[2]~vof210)): offset voltage bits ? bit 4 ~ bit 0 : not used. 4.15 instruction set each in stru cti on in the inst ru ction set is a 13- bit wo rd divided into an op cod e and one o r more ope ran d s. no rmally, all in stru ction s are e x ecuted wi thi n one sin g le i n structio n cy cle (one i n st ruction con s i s ts of 2 oscillato r pe ri ods), unle s s the prog ram counte r is ch a nged by in struction "m ov r2,a", "add r2,a", or by inst ru ctions of arithm etic or lo gi c o peration on r2 (e.g. "sub r2,a", "bs(c) r2,6", "clr r2", ????
em78p458/459 otp rom affected by the operation. the symbol "k" repres ents an 8 or 10-bit constant or literal value. t a ble 16 the list of the instruction set of em78p458/459 inst ruct ion binary hex mnemonic operat ion st at us affect ed 0 0000 0000 0000 0000 nop no operation none 0 0000 0000 0001 0001 daa decimal adjust a c 0 0000 0000 0010 0002 cont w a ?
em78p458/459 otp rom inst ruct ion binary hex mnemonic operat ion st at us affect ed 0 101b bbrr rrrr 0xxx bs r, b 1
em78p458/459 otp rom 4.16 timing diagrams reset t i m i n g ( c l k = " 0 " ) cl k / r eset no p i n st r u ct i o n 1 exe c ut ed td r h tc c i nput ti m i ng ( c lk s = " 0 " ) cl k tc c tt c c ti n s a c t e st i n g : i n p u t i s d r i v en at 2. 4v f o r l o g i c "1", a n d 0. 4 v f o r l o g i c "0". t i m i n g m e as u r e m en t s a r e m a de a t 2 . 0 v f o r l ogi c " 1 " , a nd 0 . 8 v f o r l ogi c " 0 " . a c test i nput / o ut put w a v e f o r m 2. 4 0. 4 2. 0 0. 8 tes t po i n ts 2. 0 0. 8 this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 54
em78p458/459 otp rom 5. absolute maximum ratings items rating temperature under bias 0
em78p458/459 otp rom 6. electrical characteristics 6.1 dc electrical characteristic (ta=0 ? % %
em78p458/459 otp rom 6.2 ac electrical characteristic (ta=0 ? ?
em78p458/459 otp rom 6.4 comparator(op) characteristic (vdd = 5.0v,vss=0v,ta=0 to 70 j ) sy mbol parameter condition min. ty p . max . unit s r s l e w r a t e 0 . 1 0 . 2 v/us ivr input voltage range vdd = 5 .0v, v ss = 0 .0v 0 5 v 0 0 . 2 0 . 3 ovs output voltage sw ing vd = 5 .0v, v ss =0.0v,rl=10k ?
em78p458/459 otp rom v i h/ v i l ( i n put pi ns w i t h s c hm i t t i n ve r t e r ) 0 0. 5 1 1. 5 2 2. 5 2. 5 3 3 . 5 4 4. 5 5 5 . 5 vd d ( vo l t ) vih vil(volt ) vih max ( 0 j to 70 j ) vih ty p 25 j vih min(0 j to 70 j ) vil max ( 0 j to 70 j ) vil ty p 25 j vil min( 0 j to 70 j ) fig. 25 v i h, v il of p50 vs vdd v i h/ v i l ( i n put pi ns w i t h s c hm i t t i n ve r t e r ) 0 0. 5 1 1. 5 2 2. 5 2. 5 3 3 . 5 4 4. 5 5 5 . 5 vd d ( vo l t ) vih vil(volt ) vih max ( 0 j to 70 j ) vih ty p 25 j vih min(0 j to 70 j ) vil max ( 0 j to 70 j ) vil ty p 25 j vil min( 0 j to 70 j ) fig. 26 vih, vil of p51,p52,p54 vs vdd this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 59
em78p458/459 otp rom v i h/ v i l ( i n put pi ns w i t h s c hm i t t i n ve r t e r ) 0 0.5 1 1.5 2 2.5 2.5 3 3.5 4 4. 5 5 5. 5 v dd( v o l t ) vih vil(volt) vih max ( 0 j to 70 j ) vih ty p 25 j vih min(0 j to 70 j ) vil max ( 0 j to 70 j ) vil ty p 25 j vil min( 0 j to 70 j ) fig. 27 vih, vil of p53,p55~p57,p60~p67 vs vdd vo h / io h (vdd=5 v ) -3 0 -2 5 -2 0 -1 5 -1 0 -5 0 012345 voh(vol t ) ioh(ma) vo h / i o h ( vdd= 3 v ) -1 2 -1 0 -8 -6 -4 -2 0 00 . 5 11 . 5 22 . 5 3 v oh( v o l t ) ioh(ma ) min 70 j min 70 j typ 25 j typ 25 j max 0 j max 0 j this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 60
em78p458/459 otp rom fig.28 port5, port6, v oh v s . ioh, vdd= 5v fig.29 port5, port6, v oh v s . ioh, vdd= 3v vo l/io l (vdd=5 v ) 0 10 20 30 40 50 60 70 80 01 23 45 vo l(vo lt) iol(ma) vol / i ol ( v dd= 3 v ) 0 5 10 15 20 25 30 35 0 0 .5 1 1 .5 2 2 .5 3 vo l( vo lt) iol(ma ) max 0 j max 0 j typ 25 j typ 25 j min 70 j min 70 j fig. 30 port5, and p60~p63,p66,p67 v o l, vdd=5v fig. 31 po rt5, and p60~p63,p66,p6 7 v o l , vdd=3v this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 61
em78p458/459 otp rom vo l/io l (3 v) 0 5 10 15 20 25 30 35 40 45 50 00 . 5 11 . 522 . 5 3 vo l(vo lt) iol(ma) vo l/iol (3 v) 0 5 10 15 20 25 30 35 40 45 50 0 0 .5 1 1 .5 2 2 .5 3 vol(vo lt) iol(ma) max 0 j max 0 j typ 25 j typ 25 j min 70 j min 70 j fig. 32 p64,p65 v o l v s . iol, vdd= 5v fig. 33 p64,p65 v o l v s . iol, vdd= 3v this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 62
em78p458/459 otp rom w d t t i m e _out 0 5 10 15 20 25 30 35 23 45 6 vd d ( v o l t ) wdt period (ms) max 70 j typ 25 j min 0 j fig. 34 wdt time out period v s . vdd, prescaler set to 1 : 1 this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 63
em78p458/459 otp rom c e xt = 100pf , t ypic a l r c o s c f r e que nc y 0 0. 2 0. 4 0. 6 0. 8 1 1. 2 1. 4 2. 5 3 3. 5 4 4. 5 5 5. 5 vdd( vo l t ) frequency(m hz) r = 3.3 k r = 5.1 k r = 10 k r = 100 k fig. 35 t y pical rc osc frequency v s . vdd ?] cext=100pf , t e mperature at 25 j?^ this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 64
em78p458/459 otp rom four conditions exist w i th the operating current icc1 to icc4. these conditions are as follow s ?g icc1 ?g vdd=3v , fosc=32 khz, 2clock, wdt disable. icc2 ?g vdd=3v , fosc=32 khz, 2clock, wdt enable. icc3 ?g vdd=5v , fosc=2 mhz, 2clock, wdt enable. icc4 ?g vdd=5v , fosc=4 mhz, 2clock, wdt enable. t y p i cal i c c 1 an d i c c 2 vs . t e m p e r at u r e 9 12 15 18 21 0 1 02 0 3 04 0 5 06 0 7 0 t e m p er at u r e ( j ) current (ua ) ty p icc2 ty p icc1 fig. 36 t y pical operating current ?] icc1 and icc2 ?^ v s . t e mperature m axi m u m i c c 1 an d i c c 2 vs . t e m p e r at u r e 15 18 21 24 27 30 0 1 0 2 03 04 05 0 6 0 7 0 t e mp er at u r e ( j ) current (ua) max icc2 max icc1 fig. 37 maximum operating current ?] icc1 and icc2 ?^ v s . temperature this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 65
em78p458/459 otp rom t y p i c a l i c c 3 an d i c c 4 vs . t e m p e r at u r e 0. 5 0. 7 0. 9 1. 1 1. 3 1. 5 1. 7 1. 9 0 1 02 03 0 4 05 06 07 0 t e mp er at u r e ( j ) current (ma) ty p icc4 ty p icc3 fig. 38 t y pical operating current ?] icc3 and icc4 ?^ v s . t e mperature m axi m u m i c c 3 an d i c c 4 vs . t e m p e r at u r e 1 1. 2 1. 4 1. 6 1. 8 2 2. 2 0 1 02 03 0 4 05 06 07 0 t e m p er at u r e ( j ) current (ma ) max icc4 max icc3 fig. 39 maximum operating current ?] icc3 and icc4 ?^ v s . t e mperature t w o conditions exist w i th the st andby current isb1 and isb2. these conditions are as follow ?g isb1 ?g vdd=5v , wdt disable isb2 ?g vdd=5v , wdt enable this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 66
em78p458/459 otp rom t y pi c a l i s b 1 a nd i s b 2 v s . t e m p e r a t ur e 0 3 6 9 12 0 1 0 2 03 04 05 0 6 07 0 t e m p er at u r e ( j ) current (ua ) typ isb2 typ isb1 fig. 40 t y pical s t andby current ?] isb1 and isb2 ?^ v s . t e mperature m axi m u m i s b 1 an d i s b 2 vs . t e m p e r at u r e 0 3 6 9 12 0 1 0 2 03 04 05 0 6 07 t e m p er at u r e ( j ) current (ua 0 ) max isb2 max isb1 fig. 41 maximum s t andby current ?] isb1 and isb2 ?^ v s . t e mperature this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 67
em78p458/459 otp rom operating voltage (0j~70j) 0 5 10 15 20 25 22 . 533 . 5 44 . 555 . 5 6 vdd(vol t ) frequency(m hz) fig. 42 operating v o lt age in t e mperature range from 0 j to 70 j this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 68
em78p458/459 otp rom em 78p458/459 hxt i-v 0 0.5 1 1.5 2 2.5 22 . 5 33 . 5 44 . 5 55 . 5 6 fig. 43 em78p458/459 i-v curv e operating at 4 mhz e m 78p 458/ 459 h x t i - v 0 0. 5 1 1. 5 2 2. 5 23456 fig. 44 em78p458_g/459-g i-v curv e operating at 4 mhz this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 69
em78p458/459 otp rom e m 78p 458/ 459 l x t i - v 0 50 100 150 200 23456 fig. 45 em78p458/459 i-v curv e operating at 32.768 khz e m 78p 458/ 459 l x t i - v 0 20 40 60 80 100 120 140 23456 fig. 46 em78p458_g/459_g i-v curv e operating at 32.768 khz this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 70
em78p458/459 otp rom appendix package ty pes: otp mcu package type pin count package size e m 7 8 p 4 5 8 a p d i p 2 0 p i n 3 0 0 m i l e m 7 8 p 4 5 8 a m s o p 2 0 p i n 3 0 0 m i l em78p459ak skinny dip 24 pin 300mil e m 7 8 p 4 5 9 a m s o p 2 4 p i n 3 0 0 m i l this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 71
em78p458/459 otp rom package information 20-lead plastic dual in line (pdip) ?x 300 mil this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 72
em78p458/459 otp rom 20-lead plastic small outline (sop) ?x 300 mil this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 73
em78p458/459 otp rom 24-lead plastic dual in line (pdip) ?x 300 mil this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 74
em78p458/459 otp rom 24-lead plastic small outline (sop) ?x 300 mil this specification is subject to cha nge w i thout prio r notice. 06.25.2004 (v1.4) 75
em78p458/459 otp rom this specification is subject to cha nge without prior notice. 06.25.2004 (v1.4) 76 elan (headquarter) microe lectronics corp., ltd. address : no. 12, innovation 1st. rd. science- based industrial park, hsinchu city, taiwan. telephone: 886-3-5639977 facsimile : 886-3-5639966 elan (h.k.) microele ctronics corp., ltd. address : rm. 1005b, 10/f, empire centre, 68 mody road, tsimshatsui, kowloon, hong kong. telephone: 852-27233376 facsimile : 852-27237780 e-mail : elanhk@emc.com.hk elan microelectroni cs shenzhen, ltd. address : ssmec bldg. 3f , gaoxin s. ave. 1st , south area , shenzhen high-tech industrial park., shenzhen telephone: 86-755-26010565 facsimile : 86-755-26010500 elan microelectroni cs shanghai, ltd. address : #23 building no.115 lane 572 bibo road. zhangjiang, hi-tech park, shanghai telephone: 86-21-50803866 facsimile : 86-21-50804600 elan information technology group. address: 1821 saratoga avenue, suite 250, saratoga, ca 95070, usa telephone: 1-408-366-8225 facsimile : 1-408-366-8220 elan microelectronics corp. (europe) address: dubendorfstrasse 4, 8051 zurich, switzerland telephone: 41-43-2994060 facsimile : 41-43-2994079 email : info@elan-europe.com web-site : www.elan-europe.com copyright ? 2004 elan microelectr onics corp. all rights reserved. elan owns the intellectual property rights, concepts, ideas, inventions, know-how (whether patentable or not) related to the information and technology (herein after referred as " information and technology") mentioned above, and all its related indust rial property rights throughout the world, as now may exist or to be created in the future. elan repr esents no warranty for the use of the specifications described, either expressed or implied, including, but not limited, to the implied warranties of merchantability and fitness for particular purposes. th e entire risk as to the quality and performance of the application is with the user. in no even shall elan be liable for any loss or damage to revenues, profits or goodwill or other special, incidental, i ndirect and consequential damages of any kind, resulting from the performance or failure to perform, includi ng without limitation any interruption of business, whatever resulting from breach of contract or breach of warranty, even if elan has been advised of the possibility of such damages. the specifications of the product and its applied technology will be updated or changed time by time. a ll the information and explanations of the products in th is website is only for your reference. the actual specifications and applied technology will be based on each confirmed order. elan reserves the right to modify the informati on without prior notificati on. the most up-to-day information is available on the website http://www.emc.com.tw .

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